HEF40175BTT,118

HEF40175B Quad D-type flip-flop Rev. 8 — 21 November 2011 Product data sheet 1. General description The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of CP and D0 to D3. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits      Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications  Shift registers  Buffer/storage register  Pattern generator 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF40175BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF40175BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF40175BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 HEF40175B NXP Semiconductors Quad D-type flip-flop 5. Functional diagram 4 5 D0 12 D1 D Q FF 1 CP Q D Q FF 2 CP Q CD 9 13 D2 D3 D Q FF 3 CP Q CD D Q FF 4 CP Q CD CD CP MR 1 Q0 Q0 3 Q1 Q1 6 2 Q2 Q2 11 7 Q3 Q3 14 10 15 001aae569 Fig 1. Functional diagram D0 D1 D Q FF 1 CP Q D2 D Q FF 2 CP Q CD D3 D Q FF 3 CP Q CD D Q FF 4 CP Q CD CD CP MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 001aae571 Fig 2. Logic diagram HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 6. Pinning information 6.1 Pinning HEF40175B MR 1 16 VDD Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 Q1 Q1 VSS HEF40175B MR 1 16 VDD Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 VSS 8 12 D2 5 11 Q2 6 10 Q2 7 9 8 CP Fig 3. 9 CP 001aan211 001aae570 Pin configuration SOT38-4 and SOT109-1 Fig 4. Pin configuration SOT403-1 6.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 master reset input (active LOW) Q0 to Q3 2, 7, 10, 15 buffered output Q0 to Q3 3, 6, 11, 14 complementary buffered output D0 to D3 4, 5, 12, 13 data input VSS 8 ground supply voltage CP 9 clock input (LOW-to-HIGH edge-triggered) VDD 16 supply voltage 7. Functional description Table 3. Function table [1] Input Output CP Dn MR Qn Qn  H H H L  L H L H  X H no change no change X X L L H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition. HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O Conditions VI < 0.5 V or VI > VDD + 0.5 V Min Max 0.5 +18 V 10 mA 0.5 VDD + 0.5 V - 10 mA input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation P power dissipation VO < 0.5 V or VO > VDD + 0.5 V Unit Tamb = 40 C to +125 C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW TSSOP16 package [3] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. [3] For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage 3 VI input voltage 0 Tamb ambient temperature in free air 40 t/V input transition rise and fall rate VDD = 5 V HEF40175B Product data sheet Conditions Max Unit - 15 V - VDD V - +125 C - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 Min Typ © NXP B.V. 2011. All rights reserved. 4 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage supply current Min Max Min Max Min Max - 3.5 - 3.5 - 3.5 - V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA IO < 1 A IDD Max 3.5 LOW-level output voltage LOW-level output current Min 5V IO < 1 A HIGH-level output current Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit 10 V IO < 1 A input leakage current VDD IO < 1 A HIGH-level output voltage II CI Conditions VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A 5V - 1.0 - 1.0 - 30 - 30 A 10 V - 2.0 - 2.0 - 60 - 60 A 15 V - 4.0 - 4.0 - 120 - 120 A - - - - 7.5 - - - - pF Typ Max Unit all valid input combinations; IO = 0 A input capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions CP to Qn or Qn; see Figure 5 MR to Qn; see Figure 5 HEF40175B Product data sheet VDD Extrapolation formula Min 5V 53 ns + (0.55 ns/pF) CL - 80 160 ns 10 V 24 ns + (0.23 ns/pF) CL - 35 70 ns 15 V 17 ns + (0.16 ns/pF) CL - 25 50 ns 5V 48 ns + (0.55 ns/pF) CL - 75 155 ns 10 V 19 ns + (0.23 ns/pF) CL - 30 65 ns 15 V 17 ns + (0.16 ns/pF) CL - 25 50 ns All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified. Symbol Parameter tPLH LOW to HIGH propagation delay Conditions VDD CP to Qn or Qn; see Figure 5 Extrapolation formula Min Typ Max Unit 43 ns + (0.55 ns/pF) CL - 70 140 ns 10 V 19 ns + (0.23 ns/pF) CL - 30 65 ns 15 V 17 ns + (0.16 ns/pF) CL - 25 45 ns 5V 43 ns + (0.55 ns/pF) CL - 70 140 ns 10 V 19 ns + (0.23 ns/pF) CL - 30 65 ns 17 ns + (0.16 ns/pF) CL - 25 50 ns 5V MR to Qn; see Figure 5 [1] 15 V transition time tt set-up time tsu hold time th pulse width; tW recovery time trec 5V Dn to CP; see Figure 5 Dn to CP; see Figure 5 10 ns + (1.00 ns/pF) CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF) CL - 20 40 ns 5V 60 30 - ns 10 V 20 10 - ns 15 V 15 5 - ns 5V +25 5 - ns 10 V 10 0 - ns 15 V 10 0 - ns CP input LOW; minimum pulse width see Figure 5 5V 90 45 - ns 10 V 35 15 - ns 15 V 25 10 - ns MR input LOW; minimum pulse width see Figure 5 5V 80 40 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 0 30 - ns 10 V 0 20 - ns 15 V 0 15 - ns 5V 5 11 - MHz 10 V 15 30 - MHz 15 V 20 45 - MHz MR input; see Figure 5 maximum frequency fmax [1] see Figure 5 [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formula shown (CL in pF). Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula for PD (W) where: 5V PD = 2000  fi + (fo  CL)  VDD 2 10 V PD = 8400  fi + (fo  CL)  VDD 2 15 V PD = 22500  fi + (fo  CL)  VDD fi = input frequency in MHz, fo = output frequency in MHz, 2 CL = output load capacitance in pF, VDD = supply voltage in V, (fo  CL) = sum of the outputs. HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 12. Waveforms VI MR input 0V VI CP input VM 0V VI Dn input 0V tPLH VOH Qn output VOL VM 10 % tPHL tPHL 90 % tTLH tTHL 001aak039 a. CP and MR to Qn Propagation delays and Qn transition times 1/fmax VI VM CP input 0V tsu th tW VI VM Dn input 0V trec VI VM MR input 0V tW 001aae568 b. Minimum pulse widths for CP and MR, MR to CP recovery time, and set-up and hold time for Dn to CP VOH and VOL are typical output voltage levels that occur with the output load. Set-up and hold times are shown as positive values but may be specified as negative values. The shaded area are where input changes result in predicable output performance. Measurement points are given in Table 9. Fig 5. Waveforms showing switching times HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop tW VI 90 % 90 % negative pulse VM VM 10 % 0V 10 % tf tr tr tf VI 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD VI VO G DUT CL RT 001aag182 b. Test circuit Test and measurement data is given in Table 9 Definitions test circuit: DUT = Device Under Test; RT = Termination resistance should be equal to output impedance Zo of the pulse generator; CL = Load capacitance including jig and probe capacitance. Fig 6. Test circuit for measuring switching times Table 9. Measurement points and test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD  20 ns 50 pF HEF40175B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 7. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 Fig 9. REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Package outline SOT403-1 (TSSOP16) HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF40175B v.8 20111121 Product data sheet - HEF40175B v.7 Modifications: • • Legal pages updated. Changes in “General description”, “Features and benefits” and “Applications”. HEF40175B v.7 20110503 Product data sheet - HEF40175B v.6 HEF40175B v.6 20101214 Product data sheet - HEF40175B v.5 HEF40175B v.5 20100105 Product data sheet - HEF40175B v.4 HEF40175B v.4 20090813 Product data sheet - HEF40175B_CNV v.3 HEF40175B_CNV v.3 19950101 Product specification - HEF40175B_CNV v.2 HEF40175B_CNV v.2 19950101 Product specification - - HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 15 HEF40175B NXP Semiconductors Quad D-type flip-flop 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 November 2011 Document identifier: HEF40175B