HEF40193BT,652

HEF40193B 4-bit up/down binary counter Rev. 8 — 18 November 2011 Product data sheet 1. General description The HEF40193B is a 4-bit synchronous up/down binary counter. The counter has a count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel load input (PL), four parallel data inputs (D0 to D3), an asynchronous master reset input (MR), four counter outputs (Q0 to Q3), an active LOW terminal count-up (carry) output (TCU), and an active LOW terminal count-down (borrow) output (TCD). The counter outputs change state on the LOW-to-HIGH transition of either clock input. However, for correct counting, both clock inputs cannot be LOW simultaneously. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of ‘15’, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on D0 to D3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits      Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF40193BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF40193BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF40193B NXP Semiconductors 4-bit up/down binary counter 4. Functional diagram 15 1 D0 11 5 4 14 PL CPU D1 D3 D2 CD/SD TCU 12 UP/DOWN COUNTER TCD CD Q0 3 Fig 1. 9 PARALLEL LOAD CIRCUITRY CPD MR 10 Q1 2 Q2 6 13 Q3 7 001aae580 Functional diagram HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PL D1 D2 Rev. 8 — 18 November 2011 All information provided in this document is subject to legal disclaimers. SD SD Q T FF1 T Q FF3 Q T FF4 TCU Q Q CD Q1 TCD CD Q2 Q3 001aak069 HEF40193B Logic diagram SD 4-bit up/down binary counter 3 of 19 © NXP B.V. 2011. All rights reserved. Fig 2. T CD Q0 CPU Q FF2 Q CPD SD Q CD MR D3 NXP Semiconductors HEF40193B Product data sheet D0 HEF40193B NXP Semiconductors 4-bit up/down binary counter 5. Pinning information 5.1 Pinning HEF40193B D1 1 16 VDD Q1 2 15 D0 Q0 3 14 MR CPD 4 13 TCD CPU 5 12 TCU Q2 6 11 PL Q3 7 10 D2 VSS 8 9 D3 001aae581 Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description D0 to D3 15, 1, 10, 9 parallel data input CPU 5 count-up clock pulse input (LOW-to-HIGH, edge-triggered) CPD 4 count-down clock pulse input (LOW-to-HIGH, edge-triggered) PL 11 parallel load input (active LOW) MR 14 master reset input (asynchronous) Q0 to Q3 3, 2, 6, 7 buffered counter output TCU 12 buffered terminal count-up (carry) output (active LOW) TCD 13 buffered terminal count-down (borrow) output (active LOW) VDD 16 supply voltage VSS 8 ground supply voltage HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 6. Functional description Table 3. Function table [1] MR PL CPU CPD Mode H X X X reset (asynchronous) L L X X parallel load L H  H count-up L H H  count-down [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition. MR PL D0 D1 D2 D3 CPU CPD Q0 Q1 Q2 Q3 TCU TCD COUNT 0 13 14 15 0 1 2 1 0 15 14 13 001aae586 Fig 4. Timing diagram HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 0 1 2 3 4 15 5 14 6 13 7 11 12 10 count up count down 9 8 001aae584 Logic equations for terminal count: TCU = Q0  Q1  Q2  Q3  CPU TCD = Q0  Q1  Q2  Q3  CPD Fig 5. State diagram 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA input/output current - 10 mA IIK input clamping current VI input voltage IOK output clamping current II/O VI < 0.5 V or VI > VDD + 0.5 V Min VO < 0.5 V or VO > VDD + 0.5 V IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature total power dissipation Ptot P power dissipation 40 +85 C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage 3 VI input voltage 0 Tamb ambient temperature 40 - HEF40193B Product data sheet Conditions in free air All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 Min Typ Max Unit - 15 V - VDD V +85 C © NXP B.V. 2011. All rights reserved. 6 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter Table 5. Recommended operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current II input leakage current IDD supply current CI input capacitance HEF40193B Product data sheet Conditions Tamb = 25 C Tamb = 85 C Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V VDD |IO| < 1 A IO < 1 A IO < 1 A Tamb = 40 C Unit 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA VO = 4.6 V 5V - 0.52 - 0.44 - 0.36 mA VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - 0.3 - 0.3 - 1.0 A 5V - 20 - 20 - 150 A 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A - - - - 7.5 - - pF IO < 1 A IO = 0 A All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 10. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions CPU to Qn; see Figure 6 CPD to Qn; see Figure 6 CPU to TCU; see Figure 6 CPD to TCD; see Figure 6 MR to Qn; see Figure 6 MR to TCD PL  Qn HEF40193B Product data sheet Extrapolation formula[1] Min Typ Max Unit 5V 183 ns + (0.55 ns/pF)CL - 210 415 ns 10 V 74 ns + (0.23 ns/pF)CL - 85 165 ns 15 V 52 ns + (0.16 ns/pF)CL - 60 120 ns 5V 183 ns + (0.55 ns/pF)CL - 210 425 ns 10 V 74 ns + (0.23 ns/pF)CL - 85 170 ns 15 V 57 ns + (0.16 ns/pF)CL - 60 125 ns 5V 98 ns + (0.55 ns/pF)CL - 125 250 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns VDD 5V 113 ns + (0.55 ns/pF)CL - 140 280 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 168 ns + (0.55 ns/pF)CL - 195 390 ns 10 V 69 ns + (0.23 ns/pF)CL - 80 160 ns 15 V 52 ns + (0.16 ns/pF)CL - 60 120 ns 5V 338 ns + (0.55 ns/pF)CL - 365 730 ns 10 V 119 ns + (0.23 ns/pF)CL - 130 265 ns 15 V 92 ns + (0.16 ns/pF)CL - 100 205 ns 5V 158 ns + (0.55 ns/pF)CL - 185 360 ns 10 V 64 ns + (0.23 ns/pF)CL - 75 150 ns 15 V 47 ns + (0.16 ns/pF)CL - 55 110 ns All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter Conditions tPLH CPU to Qn; see Figure 6 LOW to HIGH propagation delay CPD to Qn; see Figure 6 CPU to TCU; see Figure 6 CPD to TCD; see Figure 6 MR to TCU PL to Qn tt fmax tW trec transition time see Figure 6 maximum frequency see Figure 6 pulse width recovery time Product data sheet Min Typ Max Unit 5V 143 ns + (0.55 ns/pF)CL - 170 340 ns 10 V 59 ns + (0.23 ns/pF)CL - 70 140 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 143 ns + (0.55 ns/pF)CL - 170 340 ns 10 V 59 ns + (0.23 ns/pF)CL - 70 140 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 68 ns + (0.55 ns/pF)CL - 95 185 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 73 ns + (0.55 ns/pF)CL - 100 195 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 85 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 65 ns 5V 118 ns + (0.55 ns/pF)CL - 145 285 ns 10 V 49 ns + (0.23 ns/pF)CL - 60 115 ns 15 V 37 ns + (0.16 ns/pF)CL - 45 90 ns 5V 118 ns + (0.55 ns/pF)CL - 145 290 ns 10 V 49 ns + (0.23 ns/pF)CL - 60 120 ns 15 V 37 ns + (0.16 ns/pF)CL - 45 90 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 2.5 5 - MHz 10 V 7 14 - MHz 15 V 9 18 - MHz 5V 150 75 - ns 10 V 50 25 - ns 15 V 5V CPU or CPD LOW; minimum width; see Figure 6 35 20 - ns MR input HIGH; minimum width; see Figure 6 5V 180 90 - ns 10 V 70 35 - ns 15 V 60 30 - ns PL input LOW; minimum width; see Figure 6 5V 120 60 - ns 10 V 45 20 - ns 15 V 30 15 - ns 5V 125 65 - ns 10 V 70 35 - ns 15 V 50 25 - ns 5V 90 45 - ns 10 V 35 15 - ns 15 V 25 10 - ns MR input; see Figure 6 PL input see Figure 6 HEF40193B Extrapolation formula[1] VDD All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter Conditions tsu Dn to PL; see Figure 6 set-up time hold time th [1] Dn to PL; see Figure 6 VDD Extrapolation formula[1] Min Typ Max Unit 5V 160 80 - ns 10 V 60 30 - ns 15 V 50 25 - ns 5V +10 70 - ns 10 V +5 25 - ns 15 V +5 20 - ns The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula for PD (W) 5V PD = 600  fi + (fo  CL)  VDD2 10 V 15 V where: fi = input frequency in MHz, PD = 2700  fi + (fo  CL)  VDD 2 fo = output frequency in MHz, PD = 7500  fi + (fo  CL)  VDD 2 CL = output load capacitance in pF, VDD = supply voltage in V, (fo  CL) = sum of the outputs. HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 11. Waveforms VI MR input 0V VI CPU or CPD input 0V VM tPHL tPLH VI TCU input 0V tPHL VI TCD input 0V tPLH VOH VM 10 % Qn output VOL tPHL tPHL 90 % tt tt 001aak070 a. Propagation delays and output transition times tW VI CPU or CPD input 0V VM tW trec VI PL input VM 0V tsu th VI Dn input VM 0V tW trec VI VM MR input 0V 001aae585 b. PL and MR recovery times, CPU, CPD, PL and MR minimum pulse widths, and Dn to PL set-up and hold times VOH and VOL are typical output voltage levels that occur with the output load. Set-up and hold times are shown as positive values but may be specified as negative values. The shaded area is where the data can change for predictable performance. Measurement points are given in Table 9. Fig 6. Waveforms showing switching times HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter tW VI 90 % 90 % negative pulse VM VM 10 % 0V 10 % tf tr tr tf VI 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD VI VO G DUT RT CL 001aag182 b. Test circuit Test data is given in Table 9. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 7. Test circuit for switching times Table 9. Measurement points and test data Supply voltage 5 V to 15 V HEF40193B Product data sheet Input Load VI VM tr, tf CL VDD 0.5VI  20 ns 50 pF All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 12. Application information Some examples of applications for the HEF40193B are: • Up/down difference counting • Multistage ripple counting • Multistage synchronous counting D0 clock up CPU clock down CPD D1 D2 D3 D0 TCU CPU TCD CPD HEF40193B Q0 Q1 Q2 Q3 MR PL D1 D2 D3 TCU CARRY TCD BORROW HEF40193B Q0 Q1 Q2 Q3 MR PL MR 001aae587 PL Fig 8. Example of cascaded HEF40193B ICs HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 9. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF40193B v.8 20111118 Product data sheet - HEF40193B v.7 Modifications: • • • Legal pages updated. Changes in “General description” and “Features and benefits”. Section “Applications” removed. HEF40193B v.7 20110914 Product data sheet - HEF40193B v.6 HEF40193B v.6 20091222 Product data sheet - HEF40193B v.5 HEF40193B v.5 20090615 Product data sheet - HEF40193B v.4 HEF40193B v.4 20090505 Product data sheet - HEF40193B_CNV v.3 HEF40193B_CNV v.3 19950101 Product specification - HEF40193B_CNV v.2 HEF40193B_CNV v.2 19950101 Product specification - - HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 16 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 17 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF40193B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 18 of 19 HEF40193B NXP Semiconductors 4-bit up/down binary counter 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 November 2011 Document identifier: HEF40193B