HEF4020BT

HEF4020B 14-stage binary counter Rev. 04 — 4 December 2008 Product data sheet 1. General description The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the device is its high speed (typ. 35 MHz at VDD = 15 V). It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features I I I I I I I High speed operation Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Applications I Industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C. Type number HEF4020BP HEF4020BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1 NXP Semiconductors HEF4020B 14-stage binary counter 5. Functional diagram CP MR 10 11 T 14-STAGE COUNTER CD 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad722 Fig 1. Functional diagram CTR14 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 9 7 5 4 6 13 12 14 15 1 2 3 10 11 + CT 0 9 7 5 4 6 13 12 14 15 1 2 3 10 CP CT 11 MR 13 001aad723 001aad724 Fig 2. Logic symbol Fig 3. IEC Logic symbol CP FF T0 Q FF T1 Q FF T2 Q FF T3 Q FF T4 Q FF T5 Q FF T6 Q Q RD MR RD Q RD Q RD Q RD Q RD Q RD Q Q0 Q3 Q4 Q5 Q6 FF T7 Q FF T8 Q FF T9 Q FF T 10 Q FF T 11 Q FF T 12 Q FF T 13 Q Q RD RD Q RD Q RD Q RD Q RD Q RD Q Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad725 Fig 4. HEF4020B_4 Logic diagram © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 2 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 6. Pinning information 6.1 Pinning HEF4020B Q11 Q12 Q13 Q5 Q4 Q6 Q3 VSS 1 2 3 4 5 6 7 8 001aaj101 16 VDD 15 Q10 14 Q9 13 Q7 12 Q8 11 MR 10 CP 9 Q0 Fig 5. Pin configuration 6.2 Pin description Table 2. Symbol Q3 to Q13 VSS Q0 CP MR VDD Pin description Pin 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 8 9 10 11 16 Description parallel output (Q3 to Q13) ground supply voltage parallel output clock input (HIGH-to-LOW edge triggered) master reset input (active HIGH) supply voltage 7. Functional description Table 3. Input CP ↑ Functional table[1] Output MR L L H Q0, Q3 to Q13 no change count L ↓ X [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition. HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 3 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 1 CP input MR input Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 001aad726 Fig 6. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation Tamb −40 °C to +85 °C DIP16 package SO16 package P [1] [2] [1] [2] Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −65 −40 - Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +85 750 500 100 Unit V mA V mA mA mA °C °C mW mW mW power dissipation per output For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 4 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Typ Max 15 VDD +85 3.75 0.5 0.08 Unit V V °C ns/V ns/V ns/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 µA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 µA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 µA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 µA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current IO = 0 A 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = −40 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.52 −1.3 −3.6 0.52 1.3 3.6 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 20 40 80 Tamb = 25 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.44 −1.1 −3.0 0.44 1.1 3.0 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 20 40 80 7.5 Tamb = 85 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 150 300 600 V V V V V V V V V V V V mA mA mA mA mA mA mA µA µA µA µA pF Unit HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 5 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions CP to Q0; see Figure 7 VDD 5V 10 V 15 V Qn to Qn + 1 5V 10 V 15 V MR to Qn; see Figure 7 5V 10 V 15 V tPLH LOW to HIGH propagation delay CP to Q0; see Figure 7 5V 10 V 15 V Qn to Qn + 1 5V 10 V 15 V tt transition time see Figure 7 5V 10 V 15 V tW pulse width CP = HIGH; minimum width; see Figure 7 MR = HIGH; minimum width; see Figure 7 trec recovery time MR input; see Figure 7 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V fmax maximum frequency see Figure 7 5V 10 V 15 V [1] Extrapolation formula[1] 78 ns + (0.55 ns/pF) CL 34 ns + (0.23 ns/pF) CL 22 ns + (0.16 ns/pF) CL 53 ns + (0.55 ns/pF) CL 19 ns + (0.23 ns/pF) CL 12 ns + (0.16 ns/pF) CL 153 ns + (0.55 ns/pF) CL 79 ns + (0.23 ns/pF) CL 62 ns + (0.16 ns/pF) CL 78 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 27 ns + (0.16 ns/pF) CL 43 ns + (0.55 ns/pF) CL 14 ns + (0.23 ns/pF) CL 12 ns + (0.16 ns/pF) CL 10 ns + (1.00 ns/pF) CL 9 ns + (0.42 ns/pF) CL 6 ns + (0.28 ns/pF) CL Min 50 25 20 130 95 90 115 65 55 5 13 18 Typ 105 45 30 80 30 20 180 90 70 105 50 35 70 25 20 60 30 20 25 15 10 65 50 45 60 35 25 10 25 35 Max 210 90 65 160 60 40 360 180 140 210 95 70 140 50 40 120 60 40 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 6 of 13 NXP Semiconductors HEF4020B 14-stage binary counter Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (µW) PD = 600 × fi + Σ(fo × CL) × VDD PD = 8200 × fi + Σ(fo × CL) × 2 where: fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, Σ(CL × fo) = sum of the outputs. PD = 2800 × fi + Σ(fo × CL) × VDD2 VDD2 12. Waveforms VI MR INPUT VSS VI CP INPUT VSS VOH Q0 or Qn OUTPUT VOL tPHL VM tt tt 001aae591 VM tW trec VM tW 1/fmax tPLH tPHL Measurement points are given in Table 9. Fig 7. Table 9. VDD Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency Measurement points Input VM 0.5VDD Output VM 0.5VDD Supply voltage 5 V to 15 V VDD VI G RT VO DUT CL 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 8. Test circuit HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 7 of 13 NXP Semiconductors HEF4020B 14-stage binary counter Table 10. VDD 5 V to 15 V Test data Input VI VSS or VDD tr, tf ≤ 20 ns Load CL 50 pF Supply voltage HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 8 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 9. HEF4020B_4 Package outline SOT38-4 (DIP16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 9 of 13 NXP Semiconductors HEF4020B 14-stage binary counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 10 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 14. Abbreviations Table 11. Acronym DUT ESD HBM MM Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 12. Revision history Release date 20081204 Data sheet status Product data sheet Change notice Supersedes HEF4020B_CNV_3 Document ID HEF4020B_4 Modifications: • • • • • • • • • • • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Parallel output pins renamed Q0 to Q13 throughout. Temperature statement added to Section 1 “General description”. Section 2 “Features” added. Table 1 “Ordering information” restructured. Package version SOT38-1 changed to SOT38-4 in Section 4, and Figure 9. Package SOT74 removed from Section 4. Figure 1 “Functional diagram”, Figure 4 “Logic diagram”, Figure 5 “Pin configuration”, Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency” and Figure 6 “Timing diagram” changed for pin name changes. Figure 2 “Logic symbol” and Figure 3 “IEC Logic symbol” added. Table 2 “Pin description” edited for pin name changes. Section 7 “Functional description” added. Section 8 “Limiting values” and Section 10 “Static characteristics” added, taken from the HE4000B Family Specifications data sheet. tRMR, tWCPH and tWMRH changed to trec and tW for Table 7 “Dynamic characteristics” and Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency”. 50 % replaced by VM for Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency”. Table 9 “Measurement points”, Figure 8 “Test circuit” and Table 10 “Test data” added. Product specification Product specification HEF4020B_CNV_2 - HEF4020B_CNV_3 HEF4020B_CNV_2 19950101 19950101 HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 11 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4020B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 December 2008 12 of 13 NXP Semiconductors HEF4020B 14-stage binary counter 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 December 2008 Document identifier: HEF4020B_4