HEF4021B-Q100
8-bit static shift register
Rev. 5 — 1 December 2021
Product data sheet
1. General description
The HEF4021B-Q100 is an 8-bit static shift register (parallel-to-serial converter). It has a
synchronous serial data input (DS), a clock input (CP) and an asynchronous active HIGH parallel
load input (PL). The HEF4021B-Q100 also has eight asynchronous parallel data inputs (D0 to D7)
and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type
master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is
asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is
LOW, data on DS is shifted into the first register position. All the data in the register is shifted one
position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock
input highly tolerant of slower rise and fall times.
The device operates over a recommended VDD power supply range of 3 V to 15 V referenced to
VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 3.0 V to 15.0 V
CMOS low power dissipation
High noise immunity
Tolerant of slower rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
Type number
Package
HEF4021BT-Q100
Temperature range
Name
Description
Version
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
HEF4021BTT-Q100 -40 °C to +125 °C
TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
HEF4021B-Q100
Nexperia
8-bit static shift register
4. Functional diagram
7
6
5
4
13
14
15
1
D0
D1
D2
D3
D4
D5
D6
D7
9 PL
SD/CD
D
11 DS
10 CP
CP
SHIFT REGISTER
8-BITS
Q5 Q6 Q7
2
Fig. 1.
12
3
001aae608
Functional diagram
D0
D5
SD
DS
D
SD
O
CP
D6
D
D7
SD
O
D
CP
SD
O
D
CP
O
CP
FF 1
FF 6
FF 7
FF 8
CD
CD
CD
CD
PL
CP
Q5
Q6
Q7
001aae610
Fig. 2.
Logic diagram
HEF4021B_Q100
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
5. Pinning information
5.1. Pinning
HEF4021B
D7
1
16 VDD
Q5
2
15 D6
Q7
3
14 D5
D3
4
13 D4
D2
5
12 Q6
D1
6
11 DS
D0
7
10 CP
VSS
8
9
PL
001aae609
Fig. 3.
Pin configuration for SOT109-1 (SO16) and SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
Q5, Q6, Q7
2, 12, 3
buffered parallel output from the last three stages
D0, D1, D2, D3, D4, D5, D6, D7
7, 6, 5, 4, 13, 14,15, 1
parallel data input
VSS
8
ground supply voltage
PL
9
parallel load input
CP
10
clock input (LOW-to-HIGH edge-triggered)
DS
11
serial data input
VDD
16
supply voltage
HEF4021B_Q100
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑ = LOW to HIGH clock transition; ↓ = HIGH to LOW clock transition;
th
data n = data (HIGH or LOW) on the DS input at the n ↑ CP transition.
Number of clock Inputs
transitions
CP
Outputs
DS
PL
Q5
Q6
Q7
Serial operation
1
↑
data 1
L
X
X
X
2
↑
data 2
L
X
X
X
3
↑
data 3
L
X
X
X
6
↑
X
L
data 1
X
X
7
↑
X
L
data 2
data 1
X
8
↑
X
L
data 3
data 2
data 1
↓
X
L
no change
no change
no change
X
X
H
D5
D6
D7
Parallel operation
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
IDD
Tstg
Conditions
VI < -0.5 V or VI > VDD + 0.5 V
Min
Max
Unit
-0.5
+18
V
-
±10
mA
-0.5
-
±10
mA
input/output current
-
±10
mA
supply current
-
50
mA
storage temperature
-65
+150
°C
Tamb
ambient temperature
-40
+125
°C
Ptot
total power dissipation
Tamb -40 °C to +125 °C
-
500
mW
P
power dissipation
per output
-
100
mW
[1]
VO < -0.5 V or VO > VDD + 0.5 V
VDD + 0.5 V
[1]
For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
HEF4021B_Q100
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
3
-
15
V
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
-40
-
+125
°C
Δt/ΔV
input transition rise and fall rate
VDD = 5 V
-
-
3.75
μs/V
VDD = 10 V
-
-
0.5
μs/V
VDD = 15 V
-
-
0.08
μs/V
9. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
Conditions
VDD
Tamb = -40 °C
Tamb = +25 °C
Tamb = +85 °C
Tamb = +125 °C Unit
Min
Max
Min
Max
Min
Max
Min
Max
5V
3.5
-
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
-
0.05
V
5V
-
-1.7
-
-1.4
-
-1.1
-
-1.1
mA
5V
-
-0.64
-
-0.5
-
-0.36
-
-0.36
mA
VO = 9.5 V
10 V
-
-1.6
-
-1.3
-
-0.9
-
-0.9
mA
VO = 13.5 V
15 V
-
-4.2
-
-3.4
-
-2.4
-
-2.4
mA
5V
0.64
-
0.5
-
0.36
-
0.36
-
mA
HIGH-level
input voltage
|IO| < 1 μA
LOW-level
input voltage
|IO| < 1 μA
HIGH-level
output
voltage
|IO| < 1 μA
LOW-level
output
voltage
|IO| < 1 μA
VO = 2.5 V
HIGH-level
output current V = 4.6 V
O
VO = 0.4 V
LOW-level
output current V = 0.5 V
O
10 V
1.6
-
1.3
-
0.9
-
0.9
-
mA
VO = 1.5 V
15 V
4.2
-
3.4
-
2.4
-
2.4
-
mA
II
input leakage VDD = 15 V
current
15 V
-
±0.1
-
±0.1
-
±1.0
-
±1.0
μA
IDD
supply
current
5V
-
5
-
5
-
150
-
150
μA
10 V
-
10
-
10
-
300
-
300
μA
15 V
-
20
-
20
-
600
-
600
μA
-
-
-
-
7.5
-
-
-
-
pF
CI
input
capacitance
HEF4021B_Q100
Product data sheet
IO = 0 A
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HEF4021B-Q100
Nexperia
8-bit static shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C unless otherwise specified; for test circuit see Fig. 7.
Symbol
Parameter
Conditions
VDD
Extrapolation formula[1]
Min
Typ
Max
Unit
tPHL
HIGH to LOW
propagation delay
CP to Qn; see Fig. 4 5 V
98 ns + (0.55 ns/pF)CL
-
125
250
ns
10 V
44 ns + (0.23 ns/pF)CL
-
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
93 ns + (0.55 ns/pF)CL
-
120
240
ns
10 V
44 ns + (0.23 ns/pF)CL
-
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
88 ns + (0.55 ns/pF)CL
-
115
230
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
78 ns + (0.55 ns/pF)CL
-
105
210
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
+25
-15
-
ns
10 V
+25
-10
-
ns
15 V
+15
-5
-
ns
50
25
-
ns
10 V
30
10
-
ns
15 V
20
5
-
ns
40
20
-
ns
10 V
20
10
-
ns
15 V
15
8
-
ns
+15
-10
-
ns
10 V
15
0
-
ns
15 V
15
0
-
ns
CP = LOW;
minimum width;
see Fig. 5
5V
70
35
-
ns
10 V
30
15
-
ns
15 V
24
12
-
ns
PL = HIGH;
minimum width;
see Fig. 6
5V
70
35
-
ns
10 V
30
15
-
ns
15 V
24
12
-
ns
PL input; see Fig. 6
5V
50
10
-
ns
10 V
40
5
-
ns
15 V
35
5
-
ns
PL to Qn; see Fig. 4 5 V
tPLH
LOW to HIGH
propagation delay
CP to Qn; see Fig. 4 5 V
PL to Qnl; see Fig. 4 5 V
tt
tsu
transition time
set-up time
Qn; see Fig. 4
DS to CP; see Fig. 5 5 V
Dn to PL; see Fig. 6 5 V
th
hold time
DS to CP; see Fig. 5 5 V
Dn to PL; see Fig. 6 5 V
tW
trec
pulse width
recovery time
HEF4021B_Q100
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
Symbol
Parameter
Conditions
fclk(max)
maximum clock
frequency
CP input; see Fig. 5 5 V
[1]
VDD
Extrapolation formula[1]
Min
Typ
Max
Unit
6
13
-
MHz
10 V
15
30
-
MHz
15 V
20
40
-
MHz
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
PD
dynamic power
dissipation
VDD
Typical formula for PD (μW)
5V
PD = 900 × fi + Σ(fo × CL) × VDD
where:
2
2
10 V
PD = 4300 × fi + Σ(fo × CL) × VDD
15 V
PD = 12000 × fi + Σ(fo × CL) × VDD
2
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VDD = supply voltage in V
Σ(fo × CL) = sum of the outputs
10.1. Waveforms and test circuit
VDD
CP or PL INPUT
VM
VSS
tPHL
VOH
VY
Qn OUTPUT
VM
VX
VOL
Fig. 4.
tPLH
tt
tt
001aaj060
Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times
1 / fclk(max)
VDD
CP INPUT
VSS
VM
tsu
th
tW
VDD
DS INPUT
VM
VSS
Fig. 5.
001aae611
Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS
HEF4021B_Q100
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
VDD
CP INPUT
VM
VSS
tW
trec
VDD
PL INPUT
VM
VSS
tsu
VDD
th
90 %
Dn INPUT
VM
10 %
VSS
tf
tr
001aae612
Set-up times and hold times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Fig. 6.
Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL
Table 9. Measurement points
Supply voltage
Input
Output
VDD
VM
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
tW
VI
90 %
negative
pulse
90 %
VM
VM
10 %
0V
VI
10 %
tf
tr
tr
tf
90 %
positive
pulse
90 %
VM
VM
10 %
0V
10 %
tW
001aaj781
a. Input waveform
VDD
G
VI
VO
DUT
RT
CL
001aag182
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig. 7.
Test circuit for measuring switching times
HEF4021B_Q100
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
Table 10. Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
HEF4021B_Q100
Product data sheet
Load
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HEF4021B-Q100
Nexperia
8-bit static shift register
11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
w M
bp
0
2.5
detail X
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.05
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
0.244
0.041
0.228
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig. 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4021B_Q100
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
D
SOT403-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
Fig. 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Package outline SOT403-1 (TSSOP16)
HEF4021B_Q100
Product data sheet
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Rev. 5 — 1 December 2021
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Nexperia B.V. 2021. All rights reserved
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HEF4021B-Q100
Nexperia
8-bit static shift register
12. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
13. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4021B_Q100 v.5
20211201
Product data sheet
-
HEF4021B_Q100 v.4
Modifications:
•
•
•
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Section 2 updated.
Table 4: Derating values for Ptot total power dissipation updated.
HEF4021B_Q100 v.4
20160321
Modifications:
•
HEF4021B_Q100 v.3
20130830
Modifications:
•
HEF4021B_Q100 v.2
20130220
Modifications:
•
HEF4021B_Q100 v.1
20120807
HEF4021B_Q100
Product data sheet
Product data sheet
-
HEF4021B_Q100 v.3
Type number HEF4021BP-Q100 (SOT38-4) removed.
Product data sheet
-
HEF4021B_Q100 v.2
-
HEF4021B_Q100 v.1
-
-
HEF4021BTT-Q100 (TSSOP16) added.
Product data sheet
HEF4021BP-Q100 (DIP16) added.
Product data sheet
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HEF4021B-Q100
Nexperia
8-bit static shift register
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
14. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
This document contains data from
the preliminary specification.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Product [short]
data sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
HEF4021B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 1 December 2021
©
Nexperia B.V. 2021. All rights reserved
13 / 14
HEF4021B-Q100
Nexperia
8-bit static shift register
Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description............................................................. 3
6. Functional description................................................. 4
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................5
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 6
10.1. Waveforms and test circuit........................................ 7
11. Package outline........................................................ 10
12. Abbreviations............................................................ 12
13. Revision history........................................................12
14. Legal information......................................................13
©
Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 1 December 2021
HEF4021B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 1 December 2021
©
Nexperia B.V. 2021. All rights reserved
14 / 14
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