HEF40240B
Octal inverting buffers with 3-state outputs
Rev. 5 — 15 November 2011
Product data sheet
1. General description
The HEF40240B is an octal inverting buffer with 3-state outputs. It features output stages
with high current output capability suitable for driving highly capacitive loads.
The 3-state outputs are controlled by the output enable inputs nOE. A HIGH on nOE
causes the outputs to assume a high-impedance OFF-state. The device also features
hysteresis on all inputs to improve noise immunity. Schmitt-trigger action makes the inputs
highly tolerant to slow input rise and fall times.
The HEF40240B is pin and functionally compatible with the TTL ‘240’ device.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow input rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
Description
Version
HEF40240BP
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
HEF40240BT
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
4. Functional diagram
1A0
1A1
1A2
1A3
1OE
2A0
2A1
2A2
2A3
2OE
2
18
4
16
6
14
8
12
1Y0
1Y1
1Y2
1Y3
1
11
9
13
7
15
5
3
17
nA0
nY0
2Y1
nA1
nY1
2Y2
nA2
nY2
nA3
nY3
2Y0
2Y3
19
nOE
001aal325
Fig 1.
Functional diagram
001aal373
Fig 2.
Logic diagram
5. Pinning information
5.1 Pinning
HEF40240B
1OE
1
20 VDD
1A0
2
19 2OE
2Y3
3
18 1Y0
1A1
4
17 2A3
HEF40240B
1OE
1
20 VDD
1A0
2
19 2OE
2Y3
3
18 1Y0
1A1
4
17 2A3
2Y2
5
16 1Y1
1A2
6
15 2A2
13 2A1
2Y1
7
14 1Y2
12 1Y3
1A3
8
13 2A1
2Y0
9
12 1Y3
VSS 10
11 2A0
2Y2
5
16 1Y1
1A2
6
15 2A2
2Y1
7
1A3
8
2Y0
14 1Y2
9
VSS 10
11 2A0
001aal326
Fig 3.
Pin configuration DIP20
HEF40240B
Product data sheet
001aal372
Fig 4.
Pin configuration SO20
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
2 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE
1
output enable input (active LOW)
1A0, 1A1, 1A2, 1A3
2, 4, 6, 8
data input
VSS
10
ground (0 V)
2Y0, 2Y1, 2Y2, 2Y3
9, 7, 5, 3
data output
2A0, 2A1, 2A2, 2A3
11, 13, 15, 17
data input
VDD
20
supply voltage
1Y0, 1Y1, 1Y2, 1Y3
18, 16, 14, 12
data output
2OE
19
output enable input (active LOW)
6. Functional description
Table 3.
Function table[1]
Inputs
Output
nAn
nOE
nYn
H
L
L
L
L
H
X
H
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
VI < 0.5 V or VI > VDD + 0.5 V
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO < 0.5 V or VO > VDD + 0.5 V
II
input leakage current
into any input
[1]
Min
Max
Unit
0.5
+18
V
-
10
mA
0.5
VDD + 0.5
V
-
10
mA
-
10
mA
-
25
mA
-
100
mA
IO
output current
sink or source current
IDD
supply current
to any supply terminal
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+85
C
Ptot
total power dissipation
P
power dissipation
Tamb = 40 C to +85 C
DIP20 package
[2]
-
750
mW
SO20 package
[3]
-
500
mW
-
100
mW
per output
[1]
See Figure 6.
[2]
For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C.
[3]
For SO20 package: Ptot derates linearly with 8 mW/K above 70 C.
HEF40240B
Product data sheet
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
3 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
VDD
P
0
N
VSS
001aal328
Fig 5.
Schematic diagram of a buffer output stage
001aal327
0
IOH
(mA)
(1)
−25 VDD = 5 V
10 V
−50
(2)
15 V
−75
−100
−2.0
−1.5
−1.0
−0.5
0
(VDD − VOH) (V)
(1) P-channel MOS transistor conducting.
(2) P-channel MOS transistor and bipolar NPN transistor conducting.
Fig 6.
Typical output source current characteristic
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
supply voltage
3
-
15
V
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
HEF40240B
Product data sheet
Conditions
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
4 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
9. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C
Min
VIH
VIL
VH
VOH
VOL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
hysteresis voltage
IO < 1 A
HIGH-level output current
LOW-level output current
II
input leakage current
IDD
supply current
Min
Max
Tamb = +85 C Unit
Min
Max
5V
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
-
-
-
220.0
-
-
mV
10 V
-
-
-
250.0
-
-
mV
15 V
-
-
-
320.0
-
-
mV
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 3.6 V
5V
-
9.3
24.0
10.0
-
10.7 mA
VO = 8.4 V
10 V
-
14.4
46.0
15.0
-
15.0 mA
VO = 13.2 V
15 V
-
19.5
62.0
20.0
-
19.8 mA
VO = 4.6 V
5V
-
0.75
1.2
0.6
-
0.45 mA
VO = 9.5 V
10 V
-
1.85
3.0
1.5
-
1.1
15.5 mA
IO < 1 A
for any input
HIGH-level output voltage IO < 1 A
LOW-level output voltage
Max
Tamb = +25 C
IO < 1 A
mA
VO = 13.5 V
15 V
-
14.5
50.0
15.0
-
VO = 0.4 V
5V
2.9
-
2.3
5.4
1.75
-
mA
VO = 0.5 V
10 V
9.5
-
7.6
17.0
5.50
-
mA
VO = 1.5 V
15 V
30.0
-
25.0
45.0
19.0
-
mA
15 V
-
0.3
-
0.3
-
1.0
A
5V
-
4
-
4
-
30
A
10 V
-
8
-
8
-
60
A
15 V
-
16
-
16
-
120
A
IO = 0 A
IOZ
OFF-state output current
15 V
-
1.6
-
1.6
-
12
A
CI
input capacitance
-
-
-
-
7.5
-
-
pF
HEF40240B
Product data sheet
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
5 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
10. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 10; unless otherwise specified.
Symbol Parameter
HIGH to LOW
propagation delay
tPHL
tPLH
tPHZ
[1]
Max
Unit
83 ns + (0.24 ns/pF)CL
-
95
190
ns
10 V
35 ns + (0.10 ns/pF)CL
-
40
80
ns
15 V
26 ns + (0.07 ns/pF)CL
-
30
60
ns
82 ns + (0.06 ns/pF)CL
-
85
170
ns
10 V
38 ns + (0.03 ns/pF)CL
-
40
80
ns
15 V
29 ns + (0.02 ns/pF)CL
5V
[1]
-
30
60
ns
nOE to nYn;
nYn is HIGH;
see Figure 9
5V
-
70
140
ns
10 V
-
35
70
ns
15 V
-
30
60
ns
nOE to nYn;
nYn is LOW;
see Figure 9
5V
-
75
150
ns
10 V
-
40
80
ns
15 V
-
30
60
ns
nOE to nYn;
nYn goes HIGH;
see Figure 9
5V
-
80
160
ns
10 V
-
35
70
ns
15 V
-
30
60
ns
nOE to nYn;
nYn goes LOW;
see Figure 9
5V
-
90
180
ns
10 V
-
40
80
ns
15 V
-
30
60
ns
5V
-
40
80
ns
10 V
-
20
40
ns
15 V
-
15
30
ns
LOW to HIGH output see Figure 7 and
transition time
Figure 8
tTLH
Typ
5V
HIGH to LOW output see Figure 7 and
transition time
Figure 8
tTHL
Min
HIGH to OFF-state
propagation delay
OFF-state to LOW
propagation delay
tPZL
nAn to nYn;
see Figure 8
Extrapolation formula
[1]
nAn to nYn;
see Figure 8
OFF-state to HIGH
propagation delay
tPZH
VDD
LOW to HIGH
propagation delay
LOW to OFF-state
propagation delay
tPLZ
Conditions
5V
-
30
60
ns
10 V
-
20
40
ns
15 V
-
15
30
ns
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF40240B
Product data sheet
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
6 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
001aal329
104
tTHL
tTLH
(ns)
(1)
VDD = 5 V
10 V
15 V
103
(2)
102
VDD = 5 V
10 V
15 V
10
10
102
103
104
CL (pF)
(1) tTHL.
(2) tTLH.
Fig 7.
Output transition times as a function of the load capacitance
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
Typical formula for PD (W)
where:
5V
PD = 4250 fi + (fo CL) VDD
10 V
PD = 17000 fi + (fo CL)
15 V
PD = 46000 fi + (fo CL) VDD2
2
VDD2
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
HEF40240B
Product data sheet
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
7 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
11. Waveforms
VI
input nAn
VM
VM
GND
tPHL
VOH
tPLH
90 %
output nYn
90 %
VM
VM
10 %
VOL
10 %
tTHL
tTLH
001aal906
Measurement points are given in Table 9, VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
Waveforms showing propagation and transition delays
VI
nOE input
VM
VM
GND
tPLZ
nYn output
LOW-to-OFF
OFF-to-LOW
tPZL
VDD
VY
VX
VOL
tPHZ
VOH
tPZH
VY
nYn output
HIGH-to-OFF
OFF-to-HIGH
VX
GND
outputs on
outputs off
outputs on
001aal907
Measurement points are given in Table 9, VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
3-state enable and disable times
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
HEF40240B
Product data sheet
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
8 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
VI
tW
90 %
90 %
negative
pulse
VM
0V
10 %
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
90 %
VM
VM
10 %
10 %
tW
001aaj781
a. Input waveforms
VEXT
VDD
VI
RL
VO
G
DUT
RT
CL
001aaj915
b. Test circuit
For test data see Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 10. Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
5 V to 15 V
VSS or VDD
20 ns
50 pF
1 k
open
VDD
GND
HEF40240B
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 15 November 2011
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9 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
12. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
11
20
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
D
e
e1
L
ME
MH
w
Z (1)
max.
6.40
6.22
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2
0.25
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.078
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
SOT146-1
REFERENCES
IEC
JEDEC
JEITA
MS-001
SC-603
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 11. Package outline SOT146-1 (DIP20)
HEF40240B
Product data sheet
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
10 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
10
1
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 12. Package outline SOT163-1 (SO20)
HEF40240B
Product data sheet
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Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
11 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
13. Abbreviations
Table 11.
Abbreviations
Acronym
Description
DUT
Device Under Test
MOS
Metal Oxide Semiconductor
TTL
Transistor-Transistor Logic
14. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF40240B v.5
20111115
Product data sheet
-
HEF40240B v.4
Modifications:
•
•
Section Applications removed
Table 6: IOH minimum values changed to maximum
HEF40240B v.4
20100420
Product data sheet
-
HEF40240B_CNV v.3
HEF40240B_CNV v.3
19950101
Product specification
-
HEF40240B_CNV v.2
HEF40240B_CNV v.2
19950101
Product specification
-
-
HEF40240B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
12 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
HEF40240B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
13 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF40240B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 15 November 2011
© NXP B.V. 2011. All rights reserved.
14 of 15
HEF40240B
NXP Semiconductors
Octal inverting buffers with 3-state outputs
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 November 2011
Document identifier: HEF40240B
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