HEF4024BT,653

HEF4024B 7-stage binary counter Rev. 7 — 18 November 2011 Product data sheet 1. General description The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits       Tolerant of slow clock rise and fall time Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications  Frequency dividers  Time delay circuits 4. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C Type number Package Name Description Version HEF4024BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 HEF4024BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4024B NXP Semiconductors 7-stage binary counter 5. Functional diagram Q6 3 Q5 4 Q0 7-STAGE COUNTER Q4 5 1 Q1 CP Q3 6 Q2 Q3 Q2 9 2 Q1 11 Q4 MR Q5 Q0 12 Q6 12 11 9 6 5 4 3 001aab906 CP MR 1 2 001aab908 Fig 1. Functional diagram Fig 2. Q CP T Q FF 1 T Q FF 2 Q T Q FF 3 Q RD T Q FF 4 Q RD Logic symbol T Q RD Q FF 5 T Q RD Q FF 6 T FF 7 Q RD Q RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 001aab909 Fig 3. Logic diagram HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 14 HEF4024B NXP Semiconductors 7-stage binary counter 6. Pinning information 6.1 Pinning HEF4024B CP 1 14 VDD MR 2 13 n.c. Q6 3 12 Q0 Q5 4 11 Q1 Q4 5 10 n.c. Q3 6 9 Q2 VSS 7 8 n.c. 001aak329 Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description CP 1 clock input (HIGH to LOW edge-triggered) MR 2 master reset input VSS 7 ground (0 V) n.c. 8, 10, 13 not connected Q0 to Q6 12, 11, 9, 6, 5, 4, 3, buffered parallel outputs VDD 14 supply voltage 7. Functional description Table 3. Functional table[1] Input Output CP MR Q0 to Q6  L no change  L count X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition. HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 14 HEF4024B NXP Semiconductors 7-stage binary counter 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions VI < 0.5 V or VI > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA - 10 mA IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature in free air 40 +85 C Ptot total power dissipation Tamb 40 C to +85 C P power dissipation VO < 0.5 V or VO > VDD + 0.5 V DIP14 package [1] - 750 mW SO14 package [2] - 500 mW - 100 mW per output [1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Max Unit VDD supply voltage Conditions 3 15 V VI input voltage 0 VDD V Tamb ambient temperature in free air 40 +85 C t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V VDD = 10 V - 0.5 s/V VDD = 15 V - 0.08 s/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter Conditions VIH HIGH-level input voltage IO < 1 A VIL LOW-level input voltage HEF4024B Product data sheet IO < 1 A VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Unit Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 14 HEF4024B NXP Semiconductors 7-stage binary counter Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol VOH VOL IOH IOL Parameter Conditions HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current II input leakage current IDD supply current CI Tamb = 40 C VDD IO < 1 A 5V Tamb = 25 C Tamb = 85 C Unit Min Max Min Max Min Max 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V IO < 1 A 15 V - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA VO = 4.6 V 5V - 0.52 - 0.44 - 0.36 mA VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - 0.3 - 0.3 - 1.0 A 5V - 20 - 20 - 30 A 10 V - 40 - 40 - 60 A 15 V - 80 - 80 - 120 A - - - - 7.5 - - pF IO = 0 A input capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions CP ® Q0; see Figure 5 Qn  Qn + 1; see Figure 5 MR  Qn; see Figure 5 tPLH LOW to HIGH propagation delay CP ® Q0; see Figure 5 Qn  Qn + 1 see Figure 5 HEF4024B Product data sheet VDD Extrapolation formula[1] Min Typ Max Unit 5V 73 ns + (0.55 ns/pF)CL - 100 200 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 75 ns 15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns 5V 33 ns + (0.55 ns/pF)CL - 60 120 ns 10 V 14 ns + (0.23 ns/pF)CL - 25 50 ns 15 V 12 ns + (0.16 ns/pF)CL - 20 40 ns 5V 93 ns + (0.55 ns/pF)CL - 120 240 ns 10 V 34 ns + (0.23 ns/pF)CL - 45 90 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 34 ns + (0.23 ns/pF)CL - 45 85 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 23 ns + (0.55 ns/pF)CL - 50 100 ns 10 V 9 ns + (0.23 ns/pF)CL - 20 40 ns 15 V 7 ns + (0.16 ns/pF)CL - 15 30 ns All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 14 HEF4024B NXP Semiconductors 7-stage binary counter Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified. Symbol Parameter tt transition time pulse width tW recovery time trec maximum frequency fmax Conditions Extrapolation formula[1] VDD see Figure 5 Min Typ Max Unit 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL 5V [2] - 20 40 ns CP HIGH; minimum width see Figure 5 5V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns MR HIGH; minimum width see Figure 5 5V 80 40 - ns 10 V 35 20 - ns 15 V 25 15 - ns 5V 20 10 - ns 10 V 15 5 - ns 15 V 15 5 - ns 5V 5 10 - MHz 10 V 13 25 - MHz 15 V 18 35 - MHz MR; see Figure 5 CP input; J = K = HIGH; see Figure 5 [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] tt is the same as tTLH and tTHL. Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V Typical formula for PD (W) PD = 500  fi + (fo  CL)  VDD Where: 2 fi = input frequency in MHz; 10 V PD = 2100  fi + (fo  CL)  VDD2 fo = output frequency in MHz; 15 V PD = 5200  fi + (fo  CL)  VDD CL = output load capacitance in pF; 2 VDD = supply voltage in V; (fo  CL) = sum of the outputs. HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 14 HEF4024B NXP Semiconductors 7-stage binary counter 12. Waveforms MR input VM tW 1/fmax trec VM CP input tPHL tPLH tW Q0 or Qn output tPHL VM tTLH tTHL 001aab910 VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig 5. Waveforms showing propagation delays for MR to Qn and CP to Q0, minimum MR and CP pulse widths and recovery time for MR. Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 14 HEF4024B NXP Semiconductors 7-stage binary counter tW VI 90 % 90 % negative pulse VM VM 10 % 0V VI 10 % tf tr tr tf 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD VI VO G DUT CL RT 001aag182 b. Test circuit Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 6. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD  20 ns 50 pF HEF4024B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 14 HEF4024B NXP Semiconductors 7-stage binary counter 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 7. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 14 HEF4024B NXP Semiconductors 7-stage binary counter SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 14 HEF4024B NXP Semiconductors 7-stage binary counter 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4024B v.7 20111118 Product data sheet - HEF4024B v.6 Modifications: • • • Legal pages updated. Changes in “General description” and “Features and benefits”. Table 1, description below table title: +125 C changed to +85 C. HEF4024B v.6 20111010 Product data sheet - HEF4024B v.5 HEF4024B v.5 20091109 Product data sheet - HEF4024B v.4 HEF4024B v.4 20090902 Product data sheet - HEF4024B_CNV v.3 HEF4024B_CNV v.3 19950101 Product specification - HEF4024B_CNV v.2 HEF4024B_CNV v.2 19950101 Product specification - - HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 14 HEF4024B NXP Semiconductors 7-stage binary counter 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 14 HEF4024B NXP Semiconductors 7-stage binary counter Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4024B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 14 HEF4024B NXP Semiconductors 7-stage binary counter 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 November 2011 Document identifier: HEF4024B