HEF4069UBP,652

HEF4069UB Hex unbuffered inverter Rev. 10 — 10 February 2022 Product data sheet 1. General description The HEF4069UB is a hex unbuffered inverter. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Applications • Oscillator 4. Ordering information Table 1. Ordering information Type number Package Temperature rannge Name Description Version HEF4069UBT -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4069UBTT -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 HEF4069UB Nexperia Hex unbuffered inverter 5. Functional diagram 1A 2A 3A 4A 5A 6A 1 2 3 4 5 6 9 8 11 10 13 12 1Y 2Y 3Y 4Y VDD 5Y A 6Y VSS 001aag154 001aag152 Fig. 1. Y Functional diagram Fig. 2. Schematic diagram (one inverter) 6. Pinning information 6.1. Pinning 1A 1 14 VDD 1Y 2 13 6A 2A 3 12 6Y 2Y 4 HEF4069UB 11 5A 3A 5 10 5Y 3Y 6 9 4A VSS 7 8 4Y 001aag153 Fig. 3. Pin configuration 6.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 input 1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 output VSS 7 ground (0 V) VDD 14 supply voltage HEF4069UB Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 10 February 2022 © Nexperia B.V. 2022. All rights reserved 2 / 13 HEF4069UB Nexperia Hex unbuffered inverter 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDD supply voltage -0.5 +18 V IIK input clamping current - ±10 mA VI input voltage IOK output clamping current -0.5 VDD + 0.5 - ±10 mA II/O input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature -65 +150 °C Tamb ambient temperature -40 +125 °C Ptot total power dissipation Tamb = -40 °C to +125 °C - 500 mW P power dissipation per output - 100 mW [1] Conditions VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V [1] V For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 8. Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter Conditions VDD supply voltage VI input voltage Tamb ambient temperature in free air Min Typ Max Unit 3 - 15 V 0 - VDD V -40 - +125 °C 9. Static characteristics Table 5. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL Conditions HIGH-level input |IO| < 1 μA voltage LOW-level input |IO| < 1 μA voltage HIGH-level output voltage LOW-level output voltage HEF4069UB Product data sheet |IO| < 1 μA |IO| < 1 μA VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min Max Min Max Min Max Min Max 5V 4 - 4 - 4 - 4 - V 10 V 8 - 8 - 8 - 8 - V 15 V 12.5 - 12.5 - 12.5 - 12.5 - V 5V - 1 - 1 - 1 - 1 V 10 V - 2 - 2 - 2 - 2 V 15 V - 2.5 - 2.5 - 2.5 - 2.5 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V All information provided in this document is subject to legal disclaimers. Rev. 10 — 10 February 2022 © Nexperia B.V. 2022. All rights reserved 3 / 13 HEF4069UB Nexperia Hex unbuffered inverter Symbol Parameter IOH HIGH-level output current IOL LOW-level output current II input leakage current IDD supply current CI input capacitance Conditions VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min Max Min Max Min Max Min Max VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 - -1.1 mA VO = 4.6 V 5V - -0.64 - -0.5 - -0.36 - -0.36 mA VO = 9.5 V 10 V - -1.6 - -1.3 - -0.9 - -0.9 mA VO = 13.5 V 15 V - -4.2 - -3.4 - -2.4 - -2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA all valid input 5 V combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 μA - 0.5 - 0.5 - 15.0 - 15.0 μA - 1.0 - 1.0 - 30.0 - 30.0 μA digital inputs - - - 7.5 - - - - pF Min Typ Max Unit 10. Dynamic characteristics Table 6. Dynamic characteristics Tamb = 25 °C; for waveforms see Fig. 4; for test circuit see Fig. 5. Symbol Parameter Conditions VDD Extrapolation formula [1] tPHL nA to nY 5V 18 ns + (0.55 ns/pF)CL - 45 90 ns 10 V 9 ns + (0.23 ns/pF)CL - 20 40 ns 15 V 7 ns + (0.16 ns/pF)CL - 15 25 ns 5V 13 ns + (0.55 ns/pF)CL - 40 80 ns 10 V 9 ns + (0.23 ns/pF)CL - 20 40 ns 15 V 7 ns + (0.16 ns/pF)CL - 15 30 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns HIGH to LOW propagation delay tPLH LOW to HIGH propagation delay tTHL tTLH [1] nA to nY HIGH to LOW output transition time output nY LOW to HIGH output transition time output nY The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 7. Dynamic power dissipation VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD VDD dynamic power dissipation 5 V Typical formula Where 2 PD = 600 × fi + Σ(fo × CL) × VDD (μW) fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; 2 15 V PD = 22000 × fi + Σ(fo × CL) × VDD (μW) Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V. 2 10 V PD = 4000 × fi + Σ(fo × CL) × VDD (μW) HEF4069UB Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 10 February 2022 © Nexperia B.V. 2022. All rights reserved 4 / 13 HEF4069UB Nexperia Hex unbuffered inverter 10.1. Waveforms and test circuit tr VI VM input 0V tf 90 % 10 % tPHL VOH tPLH 90 % VM output 10 % VOL tTHL tTLH 001aag185 Measurement points: VM = 0.5VDD. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. Propagation delay and transition times VDD G VI VO DUT CL RT 001aag182 For test data refer to Table 8. Definitions for test circuit: CL = load capacitance including jig and probe capacitance; RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig. 5. Test circuit for measuring switching times Table 8. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4069UB Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 10 — 10 February 2022 © Nexperia B.V. 2022. All rights reserved 5 / 13 HEF4069UB Nexperia Hex unbuffered inverter 10.2. Transfer characteristics 001aag159 5.0 500 VO (V) ID (µA) 2.5 0 0 (1) ID (mA) 5 5 (2) (2) 2.5 VI (V) 10 VO (V) 250 (2) 001aag160 10 0 5.0 0 a. VDD = 5 V; IO = 0 A 0 (1) (2) 5 VI (V) 10 0 b. VDD = 10 V; IO = 0 A 001aag161 20 20 VO (V) ID (mA) 10 10 (2) 0 0 (1) (2) 10 VI (V) 20 0 c. VDD = 15 V; IO = 0 A (1) VO = output voltage. (2) ID = drain current. Fig. 6. Typical transfer characteristics HEF4069UB Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 10 February 2022 © Nexperia B.V. 2022. All rights reserved 6 / 13 HEF4069UB Nexperia Hex unbuffered inverter 11. Application information Some examples of applications for HEF4069UB. Fig. 7 shows an astable relaxation oscillator using two HEF4069UB inverters and two BAW62 diodes. The oscillation frequency is mainly determined by R1 × C1, provided R1