HEF4518BP,652

HEF4518B Dual BCD counter Rev. 9 — 3 December 2021 Product data sheet 1. General description The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has two clock inputs (CP0 and CP1 ), buffered outputs from all four bit positions (O0 to O3) and an asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 is HIGH or the HIGH to LOW transition of the CP1 input if CP0 is LOW. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of CP0 and CP1. Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C 3. Applications • • • Multistage synchronous counting Multistage asynchronous counting Frequency dividers 4. Ordering information Table 1. Ordering information Type number Package HEF4518BT Temperature range Name Description Version -40 °C to +85 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4518B Nexperia Dual BCD counter 5. Functional diagram 1Q0 3 1 1CP0 1Q1 4 2 1CP1 1Q2 5 1Q3 6 7 1MR 2Q0 11 9 2CP0 2Q1 12 10 2CP1 2Q2 13 2Q3 14 15 2MR 001aae698 Fig. 1. Functional diagram Q0 CP1 CP0 T FF1 Q1 Q T CD Q FF2 Q2 Q CD Q T FF3 Q3 Q T CD Q FF4 Q CD Q MR 001aae700 Fig. 2. Logic diagram for one counter HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 2 / 13 HEF4518B Nexperia Dual BCD counter 6. Pinning information 6.1. Pinning HEF4518B 1CP0 1 16 VDD 1CP1 2 15 2MR 1Q0 3 14 2Q3 1Q1 4 13 2Q2 1Q2 5 12 2Q1 1Q3 6 11 2Q0 1MR 7 10 2CP1 VSS 8 9 2CP0 001aae699 Fig. 3. Pin configuration for SOT109-1 (SO16) 6.2. Pin description Table 2. Pin description Symbol Pin Description 1CP0, 2CP0 1, 9 clock input (LOW-to-HIGH triggered) 1CP1, 2CP1 2, 10 clock input (HIGH-to-LOW triggered) 1Q0, 2Q0 3, 11 output 1Q1, 2Q1 4, 12 output 1Q2, 2Q2 5, 13 output 1Q3, 2Q3 6, 14 output 1MR, 2MR 7, 15 master reset input VDD 16 supply voltage VSS 8 ground supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition. nCP0 nCP1 nMR Mode ↑ H L counter advances L ↓ L counter advances ↓ X L no change X ↑ L no change ↑ L L no change H ↓ L no change X X H nQ0, nQ1, nQ2, nQ3 = LOW HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 3 / 13 HEF4518B Nexperia Dual BCD counter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 nCP0 nCP1 nMR 9 0 nQ0 nQ1 nQ2 nQ3 001aae703 Fig. 4. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg Conditions Min Max Unit -0.5 +18 V - ±10 mA -0.5 VDD + 0.5 - ±10 mA - ±10 mA - 50 mA storage temperature -65 +150 °C Tamb ambient temperature -40 +85 °C Ptot total power dissipation Tamb -40 °C to +85 °C - 500 mW P power dissipation per output - 100 mW VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V V 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +85 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD = 10 V - - 0.5 μs/V VDD = 15 V - - 0.08 μs/V HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Unit Nexperia B.V. 2021. All rights reserved 4 / 13 HEF4518B Nexperia Dual BCD counter 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage Conditions |IO| < 1 μA |IO| < 1 μA Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 5V |IO| < 1 μA HIGH-level output voltage |IO| < 1 μA LOW-level output voltage VDD 15 V - 0.05 - 0.05 - 0.05 V HIGH-level output current VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 mA VO = 4.6 V 5V - -0.52 - -0.44 - -0.36 mA VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA VO = 0.4 V 5V 0.52 - 0.5 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA LOW-level output current II input leakage current VDD = 15 V 15 V - ±0.3 - ±0.3 - ±1.0 μA IDD supply current IO = 0 A 5V - 20 - 20 - 150 μA 10 V - 40 - 40 - 300 μA 15 V - 80 - 80 - 600 μA - - - - 7.5 - - pF CI input capacitance HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 5 / 13 HEF4518B Nexperia Dual BCD counter 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C unless otherwise specified; for test circuit see Fig. 6. Symbol Parameter Conditions VDD Extrapolation formula[1] tPHL nCP0, nCP1 to nQn; see Fig. 5 5V HIGH to LOW propagation delay nMR to nQn; see Fig. 5 tPLH LOW to HIGH propagation delay tt transition time tW pulse width trec recovery time tsu set-up time nCP0, nCP1 to nQn; see Fig. 5 nQn; see Fig. 5 [1] maximum frequency Typ Max Unit 93 ns + (0.55 ns/pF)CL - 120 240 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 48 ns + (0.55 ns/pF)CL - 75 150 ns 10 V 24 ns + (0.23 ns/pF)CL - 35 70 ns 15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns 5V 93 ns + (0.55 ns/pF)CL - 120 240 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns nCP0 input LOW; minimum width; see Fig. 5 5V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns nCP1 input HIGH; minimum width see Fig. 5 5V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns nMR input HIGH; minimum width; see Fig. 5 5V 30 15 - ns 10 V 20 10 - ns 15 V 16 8 - ns nMR input; see Fig. 5 5V 50 25 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 50 25 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 50 25 - ns 10 V 30 15 - ns 15 V 20 10 - ns 8 16 - MHz 10 V 15 30 - MHz 15 V 20 40 - MHz nCP0 to nCP1; see Fig. 5 nCP1 to nCP0; see Fig. 5 fmax Min nCP0, nCP1; see Fig. 5 5 V The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 6 / 13 HEF4518B Nexperia Dual BCD counter Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD dynamic power dissipation HEF4518B Product data sheet VDD Typical formula for PD (μW) Where: 5V PD = 750 × fi + Σ(fo × CL) × VDD 10 V PD = 3300 × fi + Σ(fo × CL) × VDD 15 V PD = 8000 × fi + Σ(fo × CL) × VDD 2 2 2 All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; Σ(fo × CL) = sum of the outputs. © Nexperia B.V. 2021. All rights reserved 7 / 13 HEF4518B Nexperia Dual BCD counter 11.1. Waveforms and test circuit VI VM nCP0 input 0V VI nCP1 input VM 0V 0V tsu tsu VI nMR input VM 0V tPHL tPLH VOH nQn output tPHL 90 % VM 10 % VOL tt tt 001aae702 a. nCP0 and nCP1 set-up times, propagation delays, and output transition times 1/fmax VI nCP1 input (nCP0 = LOW) VM 0V tW VI nCP0 input (nCP1 = HIGH) VM 0V tW VI nMR input VM 0V tW trec 001aae701 b. nMR recovery time, minimum nCP0, nCP1, and nMR pulse widths, and maximum frequency Measurement points are given in table Table 9. The logic levels VOH and VOL are typical output voltage levels that occur with the output load. Fig. 5. Waveforms showing measurements for switching times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 8 / 13 HEF4518B Nexperia Dual BCD counter tW VI 90 % negative pulse 90 % VM VM 10 % 0V VI 10 % tf tr tr tf 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD G VI VO DUT CL RT 001aag182 b. Test circuit Test data is given in Table 10. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig. 6. Test circuit for measuring switching times Table 10. Test data Supply Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4518B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 9 / 13 HEF4518B Nexperia Dual BCD counter 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 10 / 13 HEF4518B Nexperia Dual BCD counter 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4518B v.9 20211203 Product data sheet - HEF4518B v.8 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Section 13 added. HEF4518B v.8 20160419 Modifications: • HEF4518B v.7 20111121 Modifications: • • HEF4518B v.6 20091210 Product data sheet - HEF4518B v.5 HEF4518B v.5 20090727 Product data sheet - HEF4518B v.4 HEF4518B v.4 20090703 Product data sheet - HEF4518B_CNV v.3 HEF4518B_CNV v.3 19950101 Product specification - HEF4518B_CNV v.2 HEF4518B_CNV v.2 19950101 Product specification - - HEF4518B Product data sheet Product data sheet - HEF4518B v.7 Type number HEF4518BP (SOT38-4) removed. Product data sheet - HEF4518B v.6 Table 6: IOH minimum values changed to maximum Fig. 6: added "DUT = Device Under Test" All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 11 / 13 HEF4518B Nexperia Dual BCD counter 15. Legal information injury, death or severe property or environmental damage. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 12 / 13 HEF4518B Nexperia Dual BCD counter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 8 12. Package outline........................................................ 10 13. Abbreviations............................................................ 11 14. Revision history........................................................11 15. Legal information......................................................12 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 3 December 2021 HEF4518B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 3 December 2021 © Nexperia B.V. 2021. All rights reserved 13 / 13