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I74F86D,602

I74F86D,602

  • 厂商:

    NXP(恩智浦)

  • 封装:

    SOIC14

  • 描述:

    IC GATE XOR 4CH 2-INP 14SO

  • 数据手册
  • 价格&库存
I74F86D,602 数据手册
INTEGRATED CIRCUITS 74F86 Quad 2-input exclusive-OR gate Product specification IC15 Data Handbook       1990 Feb 09 Philips Semiconductors Product specification Quad 2-input Exclusive-OR gate 74F86 FEATURE PIN CONFIGURATION • Industrial temperature range available (–40°C to +85°C) TYPE D0a 1 14 VCC D0b 2 13 D3b TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) Q0 3 12 D3a D1a 4 11 Q3 4.3ns 16.5mA D1b 5 10 D2b Q1 6 9 D2a GND 7 8 Q2 74F86 SF00038 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C PKG DWG # 14-pin plastic DIP N74F86N I74F86N SOT27-1 14-pin plastic SO N74F86D I74F86D SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dna, Dnb Data inputs 1.0/1.0 20µA/0.6mA Qn Data output 50/33 1.0mA/20mA NOTE: 1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC DIAGRAM FUNCTION TABLE 1 D0a D0b 4 5 D1a D1b 6 9 D2a D2b VCC = Pin 14 GND = Pin 7 3 2 8 10 12 D3a D3b 11 13 INPUTS Q0 Q1 Q2 Q3 OUTPUT Dna Dnb L L Qn L L H H H L H H H L NOTES: H = High voltage level L = Low voltage level SF00090 LOGIC SYMBOL IEC/IEEE SYMBOL 1 2 4 5 9 10 12 13 1 = 3 2 D0a D0bD1a D1b D2a D2b D3a D3b 4 6 5 Q0 Q1 Q2 Q3 9 8 VCC = Pin 14 GND = Pin 7 10 3 6 8 11 SF00040 12 11 13 SF00091 February 9, 1990 2 853–0336 98773 Philips Semiconductors Product specification Quad 2-input Exclusive-OR gate 74F86 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA 0 to +70 °C –40 to +85 °C –65 to +150 °C Commercial range Tamb Operating free-air free air temperature range Tstg Storage temperature range Industrial range RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current Tambb Operating temperature O erating free-air tem erature range V V 20 mA Commercial range 0 +70 °C Industrial range –40 +85 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) TEST CONDITIONS1 PARAMETER SYMBOL LIMITS MIN VOH O ±10%VCC 2.5 VIH = MIN, IOH = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX ±10%VCC VIH = MIN, IOL = MAX ±5%VCC VCC = MIN, VIL = MAX High level output voltage High-level TYP2 UNIT MAX V 3.4 V 0.30 0.50 V 0.30 0.50 V -0.73 –1.2 V 100 µA VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOS Short-circuit output current3 VCC = MAX –150 mA ICC Supplyy current ((total)) -60 ICCH VCC = MAX D0a = GND, D0b = 4.5V ICCL VCC = MAX VIN = 4.5V 15 23 mA 18 28 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. February 9, 1990 3 Philips Semiconductors Product specification Quad 2-input Exclusive-OR gate 74F86 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF RL = 500Ω VCC = +5.0V Tamb = +25°C CL = 50pF RL = 500Ω TEST CONDITION PARAMETER VCC = +5.0V ± 10% Tamb = –40°C to +85°C CL = 50pF RL = 500Ω MIN TYP MAX MIN MAX MIN MAX UNIT tPLH tPHL Propagation delay Dna or Dnb to Qn (other input Low) Waveform 1 3.0 3.0 4.0 4.2 5.5 5.5 3.0 3.0 6.5 6.5 3.0 2.5 7.0 8.0 ns tPLH tPHL Propagation delay Dna or Dnb to Qn (other input High) Waveform 2 3.5 3.0 5.3 4.7 7.0 6.5 3.5 3.0 8.0 7.5 3.5 3.0 10.0 8.0 ns VM VM AC WAVEFORMS For all waveforms, VM = 1.5V. VIN VM tPLH tPHL VM VOUT VIN VM tPHL VM VOUT tPLH VM VM SF00093 SF00092 Waveform 1. Propagation Delay for Non-Inverting Outputs Waveform 2. Propagation Delay for Inverting Outputs TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 February 9, 1990 4 Philips Semiconductors Product specification Quad 2-input exclusive-OR gate 74F86 DIP14: plastic dual in-line package; 14 leads (300 mil) 1990 Feb 09 5 SOT27-1 Philips Semiconductors Product specification Quad 2-input exclusive-OR gate 74F86 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1990 Feb 09 6 SOT108-1 Philips Semiconductors Product specification Quad 2-input exclusive-OR gate 74F86 NOTES 1990 Feb 09 7 Philips Semiconductors Product specification Quad 2-input exclusive-OR gate 74F86 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number:       yyyy mmm dd 8 Date of release: 10-98 9397-750-05068
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