IP4855CX25
SD 3.0-compliant memory card integrated voltage level
translator with EMI filter and ESD protection
Rev. 2 — 24 May 2013
Product data sheet
1. General description
The device is an SD 3.0-compliant 6-bit bidirectional dual voltage level translator. It is
designed to interface between a memory card operating at 1.8 V or 2.9 V signal levels and
a host with a fixed nominal supply voltage of 1.2 V to 3.3 V. The device supports SD 3.0
SDR50, DDR50, SDR25, SDR12 and SD 2.0 High-Speed (50 MHz) and Default-Speed
(25 MHz) modes. The device has an integrated switchable voltage regulator to supply the
card-side I/Os, built-in EMI filters and robust ESD protections (IEC 61000-4-2, level 4).
2. Features and benefits
Supports up to 100 MHz clock rate
Feedback channel for clock synchronization
SD 3.0 specification-compliant voltage translation to support SDR50, DDR50, SDR25,
SDR12, High-Speed and Default-Speed modes
Low dropout voltage regulator to supply the card-side I/Os
Low-power consumption by push-pull output stage with break-before-make
architecture
Integrated pull-up and pull-down resistors: no external resistors required
Integrated EMI filters suppress higher harmonics of digital I/Os
Integrated 8 kV ESD protection according to IEC 61000-4-2, level 4 on card side
Level shifting buffers keep ESD stress away from the host (zero-clamping concept)
Pb-free, RoHS compliant and free of halogen and antimony (Dark Green compliant)
25-ball WLCSP; pitch 0.4 mm
3. Applications
SD, MMC, microSD memory card interfaces
Mobile phones, smartphones and tablet PCs
Card readers in computer
Digital cameras
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
IP4855CX25/P
Description
WLCSP25 wafer level chip-size package; 25 bumps (5 5); 2.04 2.04 0.5 mm
Version
IP4855CX25
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
5. Block diagram
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Fig 1.
Application diagram
IP4855CX25
Product data sheet
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Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
2 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
6. Functional diagram
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Fig 2.
Functional diagram
IP4855CX25
Product data sheet
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Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
3 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
7. Pinning information
7.1 Pinning
bump A1
index area
1
2
3
4
5
A
B
C
D
E
008aaa193
transparent top view,
solder balls facing down
Fig 3.
Pin configuration WLCSP25
Table 2.
Pin allocation table
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
A1
DATA2_H
A2
DIR_CMD
A3
DIR_0
A4
VSUPPLY
A5
DATA2_SD
B1
DATA3_H
B2
SEL
B3
VCCA
B4
VLDO
B5
DATA3_SD
C1
CLK_IN
C2
ENABLE
C3
GND
C4
VSD_REF
C5
CLK_SD
D1
DATA0_H
D2
CMD_H
D3
CD
D4
CMD_SD
D5
DATA0_SD
E1
DATA1_H
E2
CLK_FB
E3
DIR_1_3
E4
WP
E5
DATA1_SD
7.2 Pin description
Table 3.
Pin
Type [2]
Description
DATA2_H
A1
I/O
data 2 input or output on host side
DIR_CMD
A2
I
direction control input for command
DIR_0
A3
I
direction control input for data 0
VSUPPLY
A4
S
supply voltage (from battery or regulator)
DATA2_SD
A5
I/O
data 2 input or output on memory card side
DATA3_H
B1
I/O
data 3 input or output on host side
SEL
B2
I
card side I/O voltage level select
VCCA
B3
S
supply voltage from host side
VLDO
B4
O
internal supply decoupling
DATA3_SD
B5
I/O
data 3 input or output on memory card side
Symbol
IP4855CX25
Product data sheet
Pin description
[1]
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 3.
Pin description …continued
Pin
Type [2]
Description
CLK_IN
C1
I
clock signal input on host side
ENABLE
C2
I
device enable input
GND
C3
S
supply ground
Symbol
[1]
VSD_REF
C4
I
reference voltage for the internal voltage regulator
CLK_SD
C5
O
clock signal output on memory card side
DATA0_H
D1
I/O
data 0 input or output on host side
CMD_H
D2
I/O
command input or output on host side
CD
D3
O
card detect switch biasing output
CMD_SD
D4
I/O
command input or output on memory card side
DATA0_SD
D5
I/O
data 0 input or output on memory card side
DATA1_H
E1
I/O
data 1 input or output on host side
CLK_FB
E2
O
clock feedback output on host side
DIR_1_3
E3
I
direction control input for data 1, data 2, data 3
WP
E4
O
write protect switch biasing output
DATA1_SD
E5
I/O
data 1 input or output on memory card side
[1]
The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards.
[2]
I = input, O = output, I/O = input and output, S = power supply
8. Functional description
8.1 Level translator
The bidirectional level translator shifts the data between the I/O supply levels of the host
and the memory card. Dedicated direction control signals determine if a command and
data signals are transferred from the memory card to the host (card read mode) or from
the host to the memory card (card write mode). The voltage translator has to support
several clock and data transfer rates at the signaling levels specified in the SD 3.0
standard specification.
Table 4.
IP4855CX25
Product data sheet
Supported modes
Bus speed mode
Signal level (V)
Clock rate (MHz)
Data rate (MB/s)
Default-Speed
3.3
25
12.5
High-Speed
3.3
50
25
SDR12
1.8
25
12.5
SDR25
1.8
50
25
SDR50
1.8
100
50
DDR50
1.8
50
50
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
8.2 Enable and direction control
The pin ENABLE enables/disables the Low DropOut (LDO) and is used to put the
host-side, card-side I/O drivers into high-ohmic 3-state mode.
Table 5.
I/O function control signal truth table
Control
Host-side
Level[1]
Pin
Pin
Memory card-side
Function
Pin
Function
Pin ENABLE = HIGH and VCCA 1.62 V
DIR_CMD
H
CMD_H
input
CMD_SD
output
L
CMD_H
output
CMD_SD
input
H
DATA0_H
input
DATA0_SD
output
L
DATA0_H
output
DATA0_SD
input
H
DATA1_H
DATA2_H
DATA3_H
input
DATA1_SD
DATA2_SD
DATA3_SD
output
L
DATA1_H
DATA2_H
DATA3_H
output
DATA1_SD
DATA2_SD
DATA3_SD
input
-
-
CLK_IN
input
CLK_SD
output
-
-
CLK_FB
output
-
-
DIR_0
DIR_1_3
Pin ENABLE = LOW or VCCA 0.8 V
DIR_CMD
X
CMD_H
high-ohmic
CMD_SD
high-ohmic
DIR_0
X
DATA0_H
high-ohmic
DATA0_SD
high-ohmic
DIR_1_3
X
DATA1_H
DATA2_H
DATA3_H
high-ohmic
DATA1_SD
DATA2_SD
DATA3_SD
high-ohmic
-
-
CLK_IN
input
CLK_SD
high-ohmic
-
-
CLK_IN
high-ohmic
-
-
[1]
H = HIGH; L = LOW and X = don’t care.
8.3 Integrated voltage regulator
The low dropout voltage regulator delivers supply voltage for the voltage translators and
the card-side input/output stages. It has to support 1.8 V and 3 V signaling modes as
stipulated in the SD 3.0 specification. The switching time between the two output voltage
modes is compliant with SD 3.0 specification. Depending on the signaling level at pin
SEL, the regulator delivers 1.8 V (SEL = HIGH) or 2.9 V (SEL = LOW, VSD_REF < 1 V). For
card supply voltage, see Section 8.4.
Table 6.
SD card side voltage level control signal truth table
Input
Output
SEL[1]
VSD_REF
VLDO
Pin[2]
Function
H
irrelevant
1.8 V
DATA0_SD to DATA3_SD, CLK_SD
low supply voltage level (1.8 Vtyp)
L
1.5 V
VSD_REF
DATA0_SD to DATA3_SD, CLK_SD
supply voltage level based on VSD_REF
[1]
H = HIGH and L = LOW.
[2]
Host-side pins are not influenced by SEL.
IP4855CX25
Product data sheet
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Rev. 2 — 24 May 2013
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
8.4 Memory card voltage tracking (reference select)
The device can track the memory card supply via pin VSD_REF. This allows achieving
optimum interoperability by perfectly matching input/output levels between voltage
translator and memory card in the 3 V signaling mode. Therefore, the voltage regulator
aims to follow the reference voltage provided at input VSD_REF directly. If tracking of the
memory card supply is not desired, connect pin VSD_REF to ground so the voltage
regulator refers to an integrated voltage reference. For 1.8 V (SEL = HIGH) signaling, the
voltage regulator is referred to the internal reference which is independent of the voltage
at VSD_REF.
8.5 Feedback clock channel
The clock is transmitted from the host to the memory card side. The voltage translator and
the Printed-Circuit Board (PCB) tracks introduce some amount of delay. It reduces timing
margin for data read back from memory card, especially at higher data rates. Therefore, a
feedback path is provided to compensate the delay. The reasoning behind this approach
is the fact that the clock is always delivered by the host, while the data in the timing critical
read mode comes from the card.
8.6 EMI filter
All input/output driver stages are equipped with EMI filters to reduce interferences towards
sensitive mobile communication.
8.7 ESD protection
The device has robust ESD protections on all memory card pins as well as on the VSD_REF
and VSUPPLY pins. The architecture prevents any stress for the host: the voltage translator
discharges any stress to supply ground.
Pins Write Protect (WP) and Card Detection (CD) might be pulled down by the memory
card which has to be detected by the host. Both signals must be HIGH if no card is
inserted. Therefore the pins are equipped with International Electrotechnical
Commission (IEC) system-level ESD protections and pull-up resistors connected to the
host supply VCCA.
IP4855CX25
Product data sheet
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Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
9. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
4 ms transient
on pin VSUPPLY
0.5
+6.0
V
on pin VCCA
0.5
+4.6
V
VI
input voltage
4 ms transient at I/O pins
0.5
+4.6
V
Ptot
total power dissipation
Tamb = 40 C to +85 C
-
1000
mW
Tstg
storage temperature
55
+150
C
Tamb
ambient temperature
40
+85
C
8000
+8000
V
Human Body Model (HBM)
JEDEC JESD22-A114F; all pins
2000
+2000
V
Machine Model (MM) JEDEC JESD22-A115;
all pins
200
+200
V
100
+100
mA
VESD
Ilu(IO)
[1]
electrostatic discharge
voltage
IEC 61000-4-2, level 4, all memory card-side pins,
VSUPPLY, VSD_REF, WP and CD to ground
input/output latch-up current JESD 78B: 0.5 VCC < VI < 1.5 VCC; Tj < 125 C
[1]
All system level tests are performed with the application-specific capacitors connected to the supply pins VSUPPLY, VLDO and VCCA.
10. Recommended operating conditions
Table 8.
Operating conditions
Symbol Parameter
supply voltage
VCC
Conditions
[1]
on pin VSUPPLY
on pin VCCA
[2]
Min
Typ
Max
Unit
2.5
-
5.5
V
1.1
-
3.6
V
0.3
-
VCCA + 0.3
V
VI
input voltage
host side
memory card side
0.3
-
VO(reg) + 0.3
V
Cext
external
capacitance
recommended capacitor at pin VLDO
-
1.0
-
F
ESR
equivalent series
resistance
at pin VLDO
0
-
50
mW
Cext
external
capacitance
recommended capacitor at pin VSUPPLY
-
0.1
-
F
recommended capacitor at pin VCCA
-
0.1
-
F
[1]
By minimum value the device is still fully functional, but the voltage on pin VLDO might drop below the recommended memory card
supply voltage.
[2]
The voltage must not exceed 3.6 V.
IP4855CX25
Product data sheet
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Rev. 2 — 24 May 2013
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 9.
Integrated resistors
Tamb = 25 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
pull-down resistance R7; tolerance 30 %
Rpd
pull-up resistance
Rpu
series resistance
[1]
Max
Unit
329
470
611
k
R30; tolerance 30 %
70
100
130
R38; tolerance 30 %
200
350
500
k
R20, R21; tolerance 30 %
200
350
500
k
R10; tolerance 30 %
10.5
15
19.5
k
R11 to R13; tolerance 30 %
49
70
91
k
R14 and R15; tolerance 30 %
Rs
Typ
70
100
130
k
card side; R1 to R6; tolerance 20 %
[1]
32
40
48
host side; R31 to R37; tolerance 20 %
[1]
26
33
40
Guaranteed by design and characterization.
11. Static characteristics
Table 10. Static characteristics
At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
Cext = 1 F at pin VLDO; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
3.0
V
Supply voltage regulator for card-side I/O pin: VLDO
VO(reg)
Vdo(reg)
regulator output
voltage
regulator dropout
voltage
SEL = LOW; VSD_REF < 1 V; VSUPPLY 2.9 V
2.75
2.9
SEL = LOW; VSD_REF > 1.5 V;
VSUPPLY VSD_REF
VSD_REF
0.15
VSD_REF VSD_REF
+ 0.05
V
SEL = HIGH; VSUPPLY 2.5 V
1.7
1.8
1.95
V
SEL = LOW; VSUPPLY 2.9 V; IO = 50 mA
-
-
150
mV
Host-side input signals: CMD_H and DATA0_H to DATA3_H, CLK_IN
VIH
HIGH-level input
voltage
0.625
VCCA
-
VCCA +
0.3
V
VIL
LOW-level input
voltage
0.3
-
0.25
VCCA
V
ILI
input leakage current
-
-
1.0
nA
VCCA = 1.8 V; ENABLE = LOW
Host-side control signals
SEL, ENABLE
VIH
HIGH-level input
voltage
0.75
-
VCCA +
0.3
V
VIL
LOW-level input
voltage
0.3
-
0.15
V
DIR_0, DIR_1_3, DIR_CMD
VIH
HIGH-level input
voltage
0.65
VCCA
-
VCCA +
0.3
V
VIL
LOW-level input
voltage
0.3
-
0.35
VCCA
V
IP4855CX25
Product data sheet
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 10. Static characteristics …continued
At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
Cext = 1 F at pin VLDO; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
VSD_REF
VIH
HIGH-level input
voltage
1.5
-
3.63
V
VIL
LOW-level input
voltage
0.3
-
1.0
V
-
V
Host-side output signals: CLK_FB, CMD_H and DATA0_H to DATA3_H
VOH
HIGH-level output
voltage
IO = 2 mA; VI = VIH (card side)
0.75
VCCA
VOL
LOW-level output
voltage
IO = 2 mA; VI = VIL (card side)
-
-
0.125
VCCA
V
SEL = LOW (2.9 V interface)
0.625
VO(reg)
-
VO(reg) +
0.3
V
SEL = HIGH (1.8 V interface)
0.625
VO(reg)
-
VO(reg) +
0.3
V
SEL = LOW (2.9 V interface)
0.3
-
0.25
VO(reg)
V
SEL = HIGH (1.8 V interface)
0.3
-
0.25
VO(reg)
V
IO = 4 mA; VI = VIH (host side); SEL = LOW
(2.9 V interface)
0.75
VO(reg)
-
VO(reg) +
0.3
V
IO = 2 mA; VI = VIH (host side); SEL = HIGH
(1.8 V interface)
0.75
VO(reg)
-
VO(reg) +
0.3
V
IO = 4 mA; VI = VIL (host side); SEL = LOW
(2.9 V interface)
0.3
-
0.125
VO(reg)
V
IO = 2 mA; VI = VIL (host side); SEL = HIGH
(1.8 V interface)
0.3
-
0.125
VO(reg)
V
card-side pins connected to ground;
host-side input signals = HIGH;
VSD_REF = 3.6 V; VSUPPLY = 5.5 V;
VCCA = 3.6 V; SEL = LOW;
DIR_1_3, DIR_CMD, DIR_0 = HIGH
-
-
100
mA
Card-side input signals: CMD_SD and DATA0_SD to DATA3_SD
VIH
VIL
HIGH-level input
voltage
LOW-level input
voltage
Card-side output signal
CMD_SD and DATA0_SD to DATA3_SD, CLK_SD
VOH
VOL
IO(sc)
HIGH-level output
voltage
LOW-level output
voltage
short-circuit output
current
Bus signal equivalent capacitance
Cch
channel capacitance
IP4855CX25
Product data sheet
VI = 0 V; fi = 1 MHz; VSUPPLY = 3.5 V;
VCCA = 1.8 V
[2]
host side
-
3.5
5
pF
card side
-
5
10
pF
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Rev. 2 — 24 May 2013
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 10. Static characteristics …continued
At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
Cext = 1 F at pin VLDO; unless otherwise specified.
Symbol Parameter
Min
Typ[1]
Max
Unit
SEL = LOW (2.9 V interface)
-
-
100
A
SEL = HIGH (1.8 V interface)
-
-
100
A
ENABLE = LOW (inactive mode)
-
-
1
A
Conditions
Current consumption
ICC(stat)
ICC(stb)
static supply current
standby supply
current
ENABLE = HIGH (active mode);
all inputs = HIGH; DIR = LOW
[1]
Typical values are measured at Tamb = 25 C.
[2]
EMI filter line capacitance per data channel from I/O driver to pin; Cch is guaranteed by design.
12. Dynamic characteristics
12.1 Voltage regulator
Table 11. Voltage regulator
Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage regulator output pin: VLDO
tstartup(reg)
regulator start-up time
VCCA = 1.8 V; VSUPPLY = 3.5 V;
Cext = 1 F; see Figure 5
-
-
100
s
tf(o)
output fall time
VO(reg) = 2.9 V to 1.8 V;
SEL = LOW to HIGH; see Figure 4
-
-
1
ms
tr(o)
output rise time
VO(reg) = 1.8 V to 2.9 V;
SEL = HIGH to LOW; see Figure 4
-
-
100
s
IP4855CX25
Product data sheet
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Rev. 2 — 24 May 2013
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
9
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Fig 4.
Regulator mode change timing
VI
50 %
ENABLE
GND
tstartup(reg)
VO(reg)
97 %
regulator
output
0V
001aah981
Measuring points: ENABLE signal at 0.5 VCCA and regulator output signal at 0.97 VO(reg).
Fig 5.
Regulator start-up time
IP4855CX25
Product data sheet
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
12.2 ESD characteristic of pin write protect and card detect
Table 12. ESD characteristic of write protect and card detect
At recommended operating conditions; Tamb = +25 C; voltages are referenced to
GND (ground = 0 V); unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ESD protection pins: WP and CD
VBR
rdyn
[1]
breakdown voltage
dynamic resistance
TLP; I = 1 mA
-
8
-
V
positive transient
[1]
-
0.5
-
negative transient
[1]
-
0.5
-
TLP according to ANSI-ESD STM5.5.1/IEC 62615 Zo = 50 ; pulse width = 100 ns; rise time = 200 ps;
averaging window = 50 ns to 80 ns
13. Application information
The IP4855CX25 is optimized to connect SD 3.0 and SD 2.0 compatible memory cards to
1.8 V base band/host interfaces. While the internal I/O interface towards the memory card
is supplied by the IP4855CX25 integrated voltage regulator, any connected memory card
has to be supplied from an external source. Using for example DDR50 or SDR50 modes
requires a power supply with up to 400 mA DC current capabilities.
Place IP4855CX25 as close as possible to the card holder to minimize the influence of
trace length on the timing values. The trace length between IP4855CX25 and the card
has a much bigger influence on the timing than the identical length between the host
interface and the IP4855CX25.
IP4855CX25
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
13 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
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Fig 6.
IP4855CX25 application diagram and output driver structure
One main task of the level translator is to shift the signal within the SD 3.0 specification.
Therefore, the following simulation results show the low impact of the device. Use the
clock feedback channel for a compensation of delay introduced by PCB traces and
IP4855CX25.
IP4855CX25
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
14 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
13.1 Simulation setup for transition time, propagation delay and
set-up/hold times
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a. Host-side to card-side simulation setup
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b. Card-side to host-side simulation setup
Fig 7.
Timing simulation setup
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Fig 8.
WW
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Output rise and fall times
IP4855CX25
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
15 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
9&&
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Fig 9.
DDD
Set-up, hold and output delay timing
IP4855CX25
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
16 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
13.2 Interface voltage timing data
Table 13. Output rise and fall times card side
VSUPPLY = 4 V; unless otherwise specified; track impedance 35 , track length (to and from IP4855CX25) 15 mm;
Rsource = 50 ; see Figure 7 for set-up circuit and Figure 8 for timing diagram; VCCA = 1.8 V; transition time is the same as
output rise time and output fall time
Symbol
Parameter
Conditions
Min.
Typ
Max
Unit
Memory card-side output pins: CLK_SD, CMD_SD and DATA0_SD to DATA3_SD; 2.9 V mode (SEL = LOW)
Reference points at 20 % and 70 %
tt
transition time
CL = 10 pF
nominal case; Tamb = +25 C; VLDO = 2.9 V
0.8
1.1
1.3
ns
best case; Tamb = 40 C; VLDO = 3.6 V
0.8
1.0
1.2
ns
0.8
1.1
1.3
ns
nominal case; Tamb = +25 C; VLDO = 2.9 V
1.4
1.6
1.9
ns
best case; Tamb = 40 C; VLDO = 3.6 V
1.3
1.6
1.8
ns
worst case; Tamb = +85 C; VLDO = 2.7 V
1.4
1.6
1.9
ns
nominal case; Tamb = +25 C; VLDO = 2.9 V
1.9
2.1
2.4
ns
best case; Tamb = 40 C; VLDO = 3.6 V
1.9
2.0
2.2
ns
2.0
2.2
2.4
ns
nominal case; Tamb = +25 C; VLDO = 2.9 V
2.9
3.1
3.4
ns
best case; Tamb = 40 C; VLDO = 3.6 V
2.9
3.0
3.2
ns
worst case; Tamb = +85 C; VLDO = 2.7 V
2.9
3.2
3.5
ns
worst case; Tamb = +85 C; VLDO = 2.7 V
[1]
CL = 20 pF
Reference points at 10 % and 90 %
tt
transition time
[2]
CL = 10 pF
worst case; Tamb = +85 C; VLDO = 2.7 V
[1]
CL = 20 pF
Memory card-side output pins: CLK_SD, CMD_SD and DATA0_SD to DATA3_SD; 1.8 V mode (SEL = HIGH)
Reference points at 20 % and 70 %
tt
tt
transition time
transition time
CL = 10 pF
nominal case; Tamb = +25 C; VLDO = 1.8 V
0.8
best case; Tamb = 40 C; VLDO = 1.95 V
0.8
worst case; Tamb = +85 C; VLDO = 1.7 V
0.8
nominal case; Tamb = +25 C; VLDO = 1.8 V
1.4
1.6
best case; Tamb = 40 C; VLDO = 1.95 V
1.3
worst case; Tamb = +85 C; VLDO = 1.7 V
1.4
tt
transition time
IP4855CX25
Product data sheet
1.3
ns
1.0
1.2
ns
1.1
1.3
ns
1.9
ns
1.6
1.8
ns
1.6
1.9
ns
[1]
CL = 20 pF
Reference points at 10 % and 90 %
1.1
[2]
CL = 10 pF
nominal case; Tamb = +25 C; VLDO = 1.8 V
1.9
2.1
2.4
ns
best case; Tamb = 40 C; VLDO = 1.95 V
1.9
2.0
2.2
ns
worst case; Tamb = +85 C; VLDO = 1.7 V
2.0
2.2
2.4
ns
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
17 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 13. Output rise and fall times card side …continued
VSUPPLY = 4 V; unless otherwise specified; track impedance 35 , track length (to and from IP4855CX25) 15 mm;
Rsource = 50 ; see Figure 7 for set-up circuit and Figure 8 for timing diagram; VCCA = 1.8 V; transition time is the same as
output rise time and output fall time
Symbol
tt
Parameter
transition time
Conditions
Min.
Typ
Max
Unit
nominal case; Tamb = +25 C; VLDO = 1.8 V
2.9
3.1
3.4
ns
best case; Tamb = 40 C; VLDO = 1.95 V
2.9
3.0
3.2
ns
worst case; Tamb = +85 C; VLDO = 1.7 V
2.9
3.2
3.5
ns
[1]
CL = 20 pF
[1]
A capacitive load of CL = 20 pF is out of the range of allowed SD-card interface parasitic capacitance.
[2]
Reference points 90 % and 10 % are not required according to the SD 3.0 specification.
Table 14. Output rise and fall times host side
VSUPPLY = 4.0 V; SEL = LOW; VO(reg) = 2.9 V; unless otherwise specified; track impedance 35 , track length (to and from
IP4855CX25) 15 mm; Rsource = 50 ; see Figure 7 for set-up circuit and Figure 8 timing diagram;
transition time is the same as output rise time and output fall time
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
nominal case; Tamb = +25 C; VCCA = 3.3 V
0.5
best case; Tamb = 40 C; VCCA = 3.6 V
0.5
0.6
0.7
ns
0.6
0.7
ns
worst case; Tamb = +85 C; VCCA = 2.7 V
0.5
0.6
0.7
ns
nominal case; Tamb = +25 C; VCCA = 3.3 V
1.0
1.3
1.5
ns
best case; Tamb = 40 C; VCCA = 3.6 V
1.0
1.2
1.4
ns
worst case; Tamb = +85 C; VCCA = 2.7 V
1.3
1.4
1.6
ns
0.5
0.6
0.7
ns
Host-side output pins: CLK_FB, CMD_H and DATA0_H to DATA3_H (3.3 V host)
Reference points at 20 % and 70 %
transition time
tt
CL = 5 pF
Reference points at 10 % and 90 %
[1]
tt
CL = 5 pF
transition time
Host-side output pins: CLK_FB, CMD_H and DATA0_H to DATA3_H (1.8 V host)
Reference points at 20 % and 70 %
transition time
tt
CL = 5 pF
nominal case; Tamb = +25 C; VCCA = 1.8 V
best case; Tamb = 40 C; VCCA = 1.9 V
0.5
0.6
0.7
ns
worst case; Tamb = +85 C; VCCA = 1.62 V
0.5
0.6
0.7
ns
nominal case; Tamb = +25 C; VCCA = 1.8 V
1.0
1.3
1.5
ns
best case; Tamb = 40 C; VCCA = 1.9 V
1.0
1.2
1.4
ns
worst case; Tamb = +85 C; VCCA = 1.62 V
1.3
1.4
1.6
ns
Reference points at 10 % and 90 % [1]
tt
[1]
transition time
CL = 5 pF
Reference points 90 % and 10 % are not required according to the SD 3.0 specification.
IP4855CX25
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
18 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
13.3 DDR50 mode timing details
The Default-Speed (DS) and High-Speed (HS) modes use 3.3 V signaling and offer a
maximum of 25 MB/s. Besides these modes, IP4855CX25 also supports the SDR12,
SDR25 and DDR50 modes using 1.8 V signaling and up to 50 MB/s.
Especially the DDR50 mode introduces a basic change in the timing behavior of the
SD card interface. The SDR12 and SDR50 modes are similar to the DS and HS modes.
Any delay on all relevant signal lines (as shown in the timing diagram in Figure 10) is
uncritical for SD card write operations as long as the skew between the different signals is
small enough.
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Fig 10. DDR50 write timing diagram
IP4855CX25
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
19 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
In contrast to the write cycle, the read cycle is more complex to analyze and depends on
the IP4855CX25 delay, the maximum delay added by the PCB and the additional setup
time of the SD card.
Table 15.
DDR50 read mode: parameters for best case and worst case timings
Parameter
Best case timing (Figure 11)
Worst case timing (Figure 12)
PCB output impedance Zo
65
25
Symmetrical trace length
15 mm per side
100 mm per side
tPD
minimum
maximum
Driver model
fast
slow
The same mechanism is triggered on each falling clock edge too, as the DDR50 mode
uses both edges of the clock signal for data transfer.
According to the SD 3.01 physical layer specification, the maximum delay between
CLK_IN (CLK_SD signal) at the SD card and data out from the SD card (DATA[3:0]_SD
out) is 7.0 ns. This value is specified for a load of CL 25 pF.
IP4855CX25
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 May 2013
© NXP B.V. 2013. All rights reserved.
20 of 30
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
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