JN516X-EK006-120VZ

Data Sheet: JN516x IEEE802.15.4 Wireless Microcontroller Features: Radio Overview • 2.4GHz IEEE802.15.4 compliant The JN516x series is a range of ultra low power, high performance wireless microcontrollers supporting JenNet-IP, ZigBee PRO or RF4CE networking stacks to facilitate the development of Home Automation, Smart Energy, Light Link and Remote control applications. They feature an enhanced 32bit RISC processor with embedded Flash and EEPROM memory, offering high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low power operation with programmable clock speeds. They also include a 2.4GHz IEEE802.15.4 compliant transceiver and a comprehensive mix of analogue and digital peripherals. Three memory configurations are available to suit different applications. The best in class operating current of 15mA, with a 0.6uA sleep timer mode, gives excellent battery life allowing operation direct from a coin cell. • 128-bit AES security processor • MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers • Integrated ultra low power sleep oscillator – 0.6µA • 2.0V to 3.6V battery operation • Deep sleep current 0.12µA (Wake-up from IO) • = EN Prescaler D Q PWM/∆Σ PWM/∆Σ EN SYSCLK TIMxOut Counter Edge Select Delta Sigma PWM/∆Σ Figure 25: Timer Unit Block Diagram 38 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 The clock source for the Timer0 unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler prescale value. For example, a prescale where a value of 0 leaves the clock unmodified and other values divide it by 2 value of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz. The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the gate function is selected, then the counter is frozen when the clock/gate input is high. An interrupt can be generated whenever the counter is equal to the value in either of the High or Low registers. The following table details which DIO are used for timer0 and the PWM depending upon the configuration. DIO Assignment Signal Standard pins Alternative pins TIM0CK_GT DIO8 DIO2 TIM0CAP DIO9 DIO3 TIM0OUT DIO10 DIO4 PWM1 DIO11 DIO5 PWM2 DIO12 DIO6 PWM3 DIO13 DIO7 DIO17 DIO8 PWM4 Table 5: Timer and PWM IO The alternative pin locations can be configured separately for each counter/timer under software control, without affecting the operation or location of the others If operating in timer mode, it is not necessary to use any of the DIO pins, allowing the standard DIO functionality to be available to the application. 11.1.1 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode, as used by PWM timers 1,2 3 and 4 and optionally by Timer0, allows the user to specify an overall cycle time and pulse length within the cycle. The pulse can be generated either as a single shot or as a train of pulses with a repetition rate determined by the cycle time. In this mode, the cycle time and low periods of the PWM output signal can be set by the values of two independent 16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset and the cycle repeats. If either the cycle time or low periods are changed while in continuous mode, the new values are not used until a full cycle has completed. The PWM waveform is available on PWM1,2,3,4 or TIM0OUT when the output driver is enabled. Rise Fall Figure 26 PWM Output Timings 11.1.2 Capture Mode The capture mode can be used to measure the time between transitions of a signal applied to the capture input (TIM0CAP). When the capture is started, on the next low-to-high transition of the captured signal, the count value is stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register. The pulse width is the difference in counts in the two registers multiplied by the period of the prescaled clock. Upon reading the capture registers the counter is stopped. The values in the High and Low registers will be updated whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the mode was started. Therefore, if multiple pulses are seen on TIM0CAP before the counter is stopped only the last pulse width will be stored. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 39 9 5 4 3 CLK CAPT tRISE tRISE tFALL tFALL Capture Mode Enabled Rise x Fall 3 9 x 14 7 Figure 27: Capture Mode 11.1.3 Counter/Timer Mode The counter/timer can be used to generate interrupts, based on the timers or event counting, for software to use. As a timer the clock source is from the system clock, prescaled if required. The timer period is programmed into the fall register and the Fall register match interrupt enabled. The timer is started as either a single-shot or a repeating timer, and generates an interrupt when the counter reaches the Fall register value. When used to count external events on TIM0CK_GT the clock source is selected from the input pin and the number of events programmed into the Fall register. The Fall register match interrupt is enabled and the counter started, usually in single shot mode. An interrupt is generated when the programmed number of transitions is seen on the input pin. The transitions counted can configured to be rising, falling or both rising and falling edges. Edges on the event signal must be at least 100nsec apart, i.e. pulses must be wider than 100nsec. 11.1.4 Delta-Sigma Mode A separate delta-sigma mode is available, allowing a low speed delta-sigma DAC to be implemented with up to 16-bit resolution. This requires that a resistor-capacitor network is placed between the output DIO pin and digital ground. A stream of pulses with digital voltage levels is generated which is integrated by the RC network to give an analogue voltage. A conversion time is defined in terms of a number of clock cycles. The width of the pulses generated is the period of a clock cycle. The number of pulses output in the cycle, together with the integrator RC values, will determine the resulting analogue voltage. For example, generating approximately half the number of pulses that make up a complete conversion period will produce a voltage on the RC output of VDD1/2, provided the RC time constant is chosen correctly. During a conversion, the pulses will be pseudo-randomly dispersed throughout the cycle in order to produce a steady voltage on the output of the RC network. The output signal is asserted for the number of clock periods defined in the High register, with the total period being 16 2 cycles. For the same value in the High register, the pattern of pulses on subsequent cycles is different, due to the pseudo-random distribution. The delta-sigma converter output can operate in a Return-To-Zero (RTZ) or a Non-Return-to-Zero (NRZ) mode. The NRZ mode will allow several pulses to be output next to each other. The RTZ mode ensures that each pulse is separated from the next by at least one period. This improves linearity if the rise and fall times of the output are different to one another. Essentially, the output signal is low on every other output clock period, and the conversion 17 cycle time is twice the NRZ cycle time i.e. 2 clocks. The integrated output will only reach half VDD2 in RTZ mode, since even at full scale only half the cycle contains pulses. Figure 28 and Figure 29 illustrate the difference between RTZ and NRZ for the same programmed number of pulses. 40 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 1 2 N 3 1 3 2 N 217 Conversion cycle 2 Conversion cycle 1 Figure 28: Return To Zero Mode in Operation 1 2 3 N Conversion cycle 1 1 216 3 2 N Conversion cycle 2 Figure 29: Non-Return to Zero Mode 11.1.5 Infra-Red Transmission Mode Infra-red transmission mode is a special feature of Timer 2 that is used to facilitate the generation of waveforms for infra-red remote control transmission. Remote control protocols, such as Philips RC-6, apply On-Off Key (OOK) modulation to a carrier signal using an encoded bit stream. The infra-red transmission mode supports a variety of remote control protocols that have different carrier frequency, carrier duty-cycle and data bit encoding requirements. In this mode, Timer 2 is configured to produce a carrier waveform that is OOK modulated by a programmable bit sequence of up to 4096 bits stored in RAM. The resultant waveform is output to the associated Timer 2 output pin. The JN516x Integrated Peripherals API User Guide [4] includes some examples. 11.1.6 Example Timer/Counter Application Figure 30 shows an application of the JN516x timers to provide closed loop speed control. PWM1 is configured in PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET. This in turn controls the power in the DC motor. Timer 0 is configured to count the rising edge events on the clk/gate pin over a constant period. This converts the tacho pulse stream output into a count proportional to the motor speed. This value is then used by the application software executing the control algorithm. If required for other functionality, then the unused IO associated with the timers could be used as general purpose DIO. +12V 1N4007 JN516x PWM1 M Tacho IRF521 CLK/GATE Timer0 1 pulse/rev CAPTURE PWM Figure 30: Closed Loop PWM Speed Control Using JN516x Timers © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 41 11.2 Tick Timer The JN516x contains a hardware timer that can be used for generating timing interrupts to software. It may be used to implement regular events such as ticks for software timers or an operating system, as a high-precision timing reference or can be used to implement system monitor timeouts as used in a watchdog timer. Features include: • 32-bit counter • 28-bit match value • Maskable timer interrupt • Single-shot, Restartable or Continuous modes of operation Match Value = Match Tick Timer Interrupt & SysClk & Counter Reset Int Enable Run Mode Control Mode Figure 31 Tick Timer The Tick Timer is clocked from a continuous 16MHz clock, which is fed to a 32-bit wide resettable up-counter, gated by a signal from the mode control block. A match register allows comparison between the counter and a programmed value. The match value, measured in 16MHz clock cycles is programmed through software, in the range 0 to 0x0FFFFFFF. The output of the comparison can be used to generate an interrupt if the interrupt is enabled and used in controlling the counter in the different modes. Upon configuring the timer mode, the counter is also reset. If the mode is programmed as single shot, the counter begins to count from zero until the match value is reached. The match signal will be generated which will cause an interrupt if enabled, and the counter will stop counting. The counter is restarted by reprogramming the mode. If the mode is programmed as restartable, the operation of the counter is the same as for the single shot mode, except that when the match value is reached the counter is reset and begins counting from zero. An interrupt will be generated when the match value is reached if it is enabled. Continuous mode operation is similar to restartable, except that when the match value is reached, the counter is not reset but continues to count. An interrupt will be generated when the match value is reached if enabled. 11.3 Wakeup Timers Two -41 bit wakeup timers are available in the JN516x driven from the 32kHz internal clock. They may run during sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period timings that may be required by the application. The wakeup timers do not run during deep sleep and may optionally 42 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 be disabled in sleep mode through software control. When a wakeup timer expires it typically generates an interrupt, if the device is asleep then the interrupt may be used as an event to end the sleep period. See Section 18 for further details on how they are used during sleep periods. Features include: • 41-bit down-counter • Optionally runs during sleep periods • Clocked by 32kHz system clock; either 32kHz RC oscillator, 32kHz XTAL oscillator or 32kHz clock input A wakeup timer consists of a 41-bit down counter clocked from the selected 32 kHz clock. An interrupt or wakeup event can be generated when the counter reaches zero. On reaching zero the counter will continue to count down until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wakeup event is required, the timer interrupt should be enabled before loading the count value for the period. Once the count value is loaded and counter started, the counter begins to count down; the counter can be stopped at any time through software control. The counter will remain at the value it contained when the timer was stopped and no interrupt will be generated. The status of the timers can be read to indicate if the timers are running and/or have expired; this is useful when the timer interrupts are masked. This operation will reset any expired status flags. 11.3.1 32 KHZ RC Oscillator Calibration The 32 KHZ RC oscillator that can be used to time sleep periods is designed to require very little power to operate and be self-contained, requiring no external timing components and hence is lower cost. As a consequence of using on-chip resistors and capacitors, the inherent absolute accuracy and temperature coefficient is lower than that of a crystal oscillator, but once calibrated the accuracy approaches that of a crystal oscillator. Sleep time periods should be as close to the desired time as possible in order to allow the device to wake up in time for important events, for example beacon transmissions in the IEEE802.15.4 protocol. If the sleep time is accurate, the device can be programmed to wake up very close to the calculated time of the event and so keep current consumption to a minimum. If the sleep time is less accurate, it will be necessary to wake up earlier in order to be certain the event will be captured. If the device wakes earlier, it will be awake for longer and so reduce battery life. Please note, that oscillator has a default current consumption of around 0.5uA, optionally this can be reduced to 0.375uA, which can improve battery life, however, the calibrated accuracy and temperature coefficient will be worse as a consequence. For detailed electrical specifications, see Section 19.3.9. In order to allow sleep time periods to be as close to the desired length as possible, the true frequency of the RC oscillator needs to be determined to better than the initial 30% accuracy. The calibration factor can then be used to calculate the true number of nominal 32kHz periods needed to make up a particular sleep time. A calibration reference counter, clocked from the 16MHz system clock, is provided to allow comparisons to be made between the 32kHz RC clock and the 16MHz system clock when the JN516x is awake and running from the 32MHZ crystal. Wakeup timer0 counts for a set number of 32kHz clock periods during which time the reference counter runs. When the wakeup timer reaches zero the reference counter is stopped, allowing software to read the number of 16MHz clock ticks generated during the time represented by the number of 32kHz ticks programmed in the wakeup timer. The true period of the 32kHz clock can thus be determined and used when programming a wakeup timer to achieve a better accuracy and hence more accurate sleep periods For a RC oscillator running at exactly 32,000Hz the value returned by the calibration procedure should be 10000, for a calibration period of twenty 32,000Hz clock periods. If the oscillator is running faster than 32,000Hz the count will be less than 10000, if running slower the value will be higher. For a calibration count of 9000, indicating that the RC oscillator period is running at approximately 35kHz, to time for a period of 2 seconds the timer should be loaded with 71,111 ((10000/9000) x (32000 x 2)) rather than 64000. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 43 12 Pulse Counters Two 16-bit counters are provided that can increment during all modes of operation (including sleep). The first, PC0, increments from pulses received on DIO1 or DIO4. The other pulse counter, PC1 operates from DIO5 or DIO8 depending upon the configuration. This is enabled under software control. The pulses can be de-bounced using the 32kHz clock to guard against false counting on slow or noisy edges. Increments occur from a configurable rising or falling edge on the respective DIO input. Each counter has an associated 16-bit reference that is loaded by the user. An interrupt (and wakeup event if asleep) may be generated when a counter reaches its pre-configured reference value. The two counters may optionally be cascaded together to provide a single 32-bit counter, linked to any of the four DIO’s. The counters do not saturate at 65535, but naturally roll-over to 0. Additionally, the pulse counting continues when the reference value is reached without software interaction so that pulses are not missed even if there is a long delay before an interrupt is serviced or during the wakeup process. The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be used. 44 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 13 Serial Communications The JN516x has two Universal Asynchronous Receiver/Transmitter (UART) serial communication interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode. The interfaces perform serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from the CPU to external devices. In both directions, a configurable FIFO buffer (with a default depth of 16-bytes) allows the CPU to read and write multiple characters on each transaction. This means that the CPU is freed from handling data on a character-by-character basis, with the associated high processor overhead. The UARTs have the following features: • Emulates behaviour of industry standard NS16450 and NS16550A UARTs • Configurable transmit and receive FIFO buffers (with default depths of 16-bytes for each), with direct access to fill levels of each. Adds/deletes standard start, stop and parity bits to or from the serial data • Independently controlled transmit, receive, status and data sent interrupts • Optional modem flow control signals CTS and RTS on UART0. • Fully programmable data formats: baud rate, start, stop and parity settings • False start bit detection, parity, framing and FIFO overrun error detect and break indication • Internal diagnostic capabilities: loop-back controls for communications link fault isolation • Flow control by software or automatically by hardware Divisor Latch Interrupt ID Register Internal Interrupt Interrupt Logic Line Status Register Processor Bus Interrupt Enable Register RTS Baud Generator Logic Registers Line Control Register Receiver Logic Receiver FIFO Receiver Shift Register RXD Modem Status Register CTS Modem Signals Logic Modem Control Register FIFO Control Register Transmitter Logic Transmitter FIFO Transmitter Shift Register TXD Figure 32: UART Block Diagram The serial interfaces contain programmable fields that can be used to set number of data bits (5, 6,7 or 8), even, odd, set-at-1, set-at-0 or no-parity detection and generation of single or multiple stop bit, (for 5 bit data, multiple is 1.5 stop bits; for 6, 7 or 8 data bits, multiple is 2 bits). The baud rate is programmable up to 1Mbps, standard baud rates such as 4800, 9600, 19.2k, 38.4k etc. can be configured. For applications requiring hardware flow control, UART0 provides two control signals: Clear-To-Send (CTS) and Request-To-Send (RTS). CTS is an indication sent by an external device to the UART that it is ready to receive data. RTS is an indication sent by the UART to the external device that it is ready to receive data. RTS is controlled from software, while the value of CTS can be read. Monitoring and control of CTS and RTS is a software activity, normally performed as part of interrupt processing. The signals do not control parts of the UART hardware, but simply indicate to software the state of the UART external interfaces. Alternatively, the Automatic Flow Control mode can be set © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 45 where the hardware controls the value of the generated RTS (negated if the receive FIFO fill level is greater than a programmable threshold of 8, 11, 13 or 15 bytes), and only transmits data when the incoming CTS is asserted. Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO, one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other. The status of the Transmit FIFO can be checked to see if it is empty, and if there is a character being transmitted. The status of the Receive FIFO can also be checked, indicating if conditions such as parity error, framing error or break indication have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives) and if there is data held in the receive FIFO. UART0 and UART1 can both be configured to use standard or alternative DIO lines, as shown in Table 5. Additionally, UART0 can be configured to be used in 2-wire mode (where CTS0 and RTS0 are not configured), and UART1 can be configured in 1-wire mode (where RXD1 is not configured). These freed up DIO pins can then be used for other purposes. Signal DIO Assignment Standard pins Alternative pins CTS0 DIO4 DIO12 RTS0 DIO5 DIO13 TXD0 DIO6 DIO14 RXD0 DIO7 DIO15 TXD1 DIO14 DIO11 RXD1 DIO15 DIO9 Table 6: UART IO . Note: With the automatic flow control threshold set to 15, the hardware flow control within the UART’s block negates RTS when they receive FIFO that is about to become full. In some instances it has been observed that remote devices that are transmitting data do not respond quickly enough to the de-asserted CTS and continue to transmit data. In these instances the data will be lost in a receive FIFO overflow. 13.1 Interrupts Interrupt generation can be controlled for the UART’s block, and is divided into four categories: • Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times. • Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted. • Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive FIFO does not have a valid stop bit and (4) Break Interrupt – occurs when the RxD line has been held low for an entire character. • Modem Status: Generated when the CTS (Clear To Send) input control line changes. 13.2 UART Application The following example shows the UART0 connected to a 9-pin connector compatible with a PC. As the JN516x device pins do not provide the RS232 line voltage, a level shifter is used. 46 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 PC COM Port 5 1 6 9 JN516x TXD CTS UART0 RXD RS232 Level Shifter RTS Pin 1 2 3 4 5 6 7 8 9 Signal CD RD TD DTR SG DSR RTS CTS RI Figure 33: JN516x Serial Communication Link © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 47 14 JTAG Test Interface The JN516x includes an IEEE1149.1 compliant JTAG port for the purpose of manufacturing test. The software debugger is not supported with this product. The JTAG interface does not support boundary scan testing. It is recommended that the JN516x is not connected as part of the board scan chain. 48 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 15 Two-Wire Serial Interface (I2C) 2 The JN516x includes industry standard I C two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following features: Common to both master and slave: • Compatible with both I C and SMbus peripherals • Support for 7 and 10-bit addressing modes • Optional pulse suppression on signal inputs (60ns guaranteed, 125ns typical) 2 Master only: • Multi-master operation • Software programmable clock frequency • Supports Slave clock stretching • Software programmable acknowledge bit • Interrupt or bit-polling driven byte-by-byte data-transfers • Bus busy detection Slave only: • Programmable slave address • Simple byte level transfer protocol • Write data flow control using acknowledge mechanism • Read data flow control using clock stretching • Read data preloaded or provided as required The Serial Interface is accessed, depending upon the configuration, DIO14 and DIO15 or DIO16 and DIO17. This is enabled under software control. The following table details which DIO are used for the Serial Interface depending upon the configuration. DIO Assignment Signal Standard pins Alternative pins SIF_CLK DIO14 DIO16 SIF_D DIO15 DIO17 Table 7: Two-Wire Serial Interface IO 15.1 Connecting Devices The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO15 and DIO14 respectively. The serial interface function of these pins is selected when the interface is enabled. They are both bi-directional lines, connected internally to the positive supply voltage via weak (50kΩ) programmable pull-up resistors. However, it is recommended that external 4.7kΩ pull-ups be used for reliable operation at high bus speeds, as shown in Figure 34. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an opendrain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is solely dependent on the bus capacitance limit of 400pF. 2 As this is an optional interface with two alternate positions, the DIO cells have not been customised for I C operation. In particular, note that there are ESD diodes to the nominal 3 volt supply (VDD2) from the SIF_CLK and SIF_D pins. Therefore, if the VDD supply is removed from the JN5168 and this then discharges to ground, a path would exist that could pull down the bus lines (see 2.2.6). © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 49 VDD JN516x RP DIO14 SI F Pullup Resistors RP SIF_CLK SIF_D DIO15 D1_I N CLK1_I N CLK1_OUT D1_OUT D2_I N D2_OUT DEVICE 1 CLK2_I N CLK2_OUT DEVICE 2 Figure 34: Connection Details 15.2 Clock Stretching Slave devices can use clock stretching to slow down the read transfer bit rate. After the master has driven SIF_CLK low, the slave can drive SIF_CLK low for the required period and then release it. If the slave’s SIF_CLK low period is greater than the master’s low period the resulting SIF_CLK bus signal low period is stretched thus inserting wait states – see section 15.4 for further details. Clock held low by Slave SIF_CLK Master SIF_CLK SIF_CLK Slave SIF_CLK SIF_CLK Wired-AND SIF_CLK Figure 35: Clock Stretching 15.3 Master Two-wire Serial Interface When operating as a master device, it provides the clock signal and a prescale register determines the clock rate, allowing operation up to 400kbit/s. Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for indicating when start, stop, read, write and acknowledge control should be generated. Write data written into a transmit buffer will be written out across the two-wire interface when indicated, and read data received on the interface is made available in a receive buffer. Indication of when a particular transfer has completed may be indicated by means of an interrupt or by polling a status bit. The first byte of data transferred by the device after a start bit is the slave address. The JN516x supports both 7-bit and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address will respond by returning an acknowledge bit. The master interface provides a true multi-master bus including collision detection and arbitration that prevents data corruption. If two or more masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock. Because of the wired-AND connection of the interface, a high-to-low transition on the bus affects all connected devices. This means a high-to-low transition on the SIF_CLK line causes all concerned devices to count off their low period. Once the clock input of a device has gone low, it will hold the SIF_CLK line in that state until the clock high state is reached when it releases the SIF_CLK line. Due to the wired-AND connection, the SIF_CLK line will therefore be held low by the device with the longest low period, and held high by the device with the shortest high period. 50 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 Start counting low period Start counting high period Wait State SIF_CLK1 Master1 SIF_CLK SIF_CLK2 Master2 SIF_CLK SIF_CLK Wired-AND SIF_CLK Figure 36: Multi-Master Clock Synchronisation After each transfer has completed, the status of the device must be checked to ensure that the data has been acknowledged correctly, and that there has been no loss of arbitration. (N.B. Loss of arbitration may occur at any point during the transfer, including data cycles). An interrupt will be generated when arbitration has been lost. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 51 15.4 Slave Two-wire Serial Interface When operating as a slave device, the interface does not provide a clock signal, although it may drive the clock signal low if it is required to apply clock stretching during read transfers. Only transfers whose address matches the value programmed into the interface’s address register are accepted. The interface allows both 7 and 10 bit addresses to be programmed, but only responds with an acknowledge to a single address. Addresses defined as “reserved” will not be responded to, and should not be programmed into the address register. A list of reserved addresses is shown in Table 8. Address Name Behaviour 0000 000 General Call/Start Byte Ignored 0000 001 CBUS address Ignored 0000 010 Reserved Ignored 0000 011 Reserved Ignored 0000 1XX Hs-mode master code Ignored 1111 1XX Reserved Ignored 1111 0XX 10-bit address Only responded to if 10 bit address set in address register Table 8 : List of two-wire serial interface reserved addresses Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for taking write data from a receive buffer and providing read data to a transmit buffer when indicated. A series of interrupt status bits are provided to control the flow of data. For writes, in to the slave interface, it is important that data is taken from the receive buffer by the processor before the next byte of data arrives. To enable this, the interface returns a Not Acknowledge (NACK) to the master if more data is received before the previous data has been taken. This will lead to the termination of the current data transfer. For reads, from the slave interface, the data may be preloaded into the transmit buffer when it is empty (i.e. at the start of day, or when the last data has been read), or fetched each time a read transfer is requested. When using data preload, read data in the buffer must be replenished following a data write, as the transmit and received data is contained in a shared buffer. The interface will hold the bus using clock stretching when the transmit buffer is empty. Interrupts may be triggered when: 52 • Data Buffer read data is required – a byte of data to be read should be provided to avoid the interface from clock stretching • Data Buffer read data has been taken – this indicates when the next data may be preloaded into the data buffer • Data Buffer write data is available – a byte of data should be taken from the data buffer to avoid data backoff as defined above • The last data in a transfer has completed – i.e. the end of a burst of data, when a Stop or Restart is seen • A protocol error has been spotted on the interface JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 16 Random Number Generator A random number generator is provided which creates a 16-bit random number each time it is invoked. Consecutive calls can be made to build up any length of random number required. Each call takes approximately 0.25msec to complete. Alternatively, continuous generation mode can be used where a new number is generated approximately every 0.25msec. In either mode of operation an interrupt can be generated to indicate when the number is available, or a status bit can be polled. The random bits are generated by sampling the state of the 32MHz clock every 32kHz system clock edge. As these clocks are asynchronous to each other, each sampled bit is unpredictable and hence random. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 53 17 Analogue Peripherals The JN516x contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors and switches. Chip Boundary Supply Voltage (VDD1) Vref Internal Reference ADC1 Vref Select VREF/ADC2 ADC ADC3 (DIO0) ADC4 (DIO1) Temp Sensor COMP1P (DIO16) Comparator 1 COMP1M (DIO17) Figure 37: Analogue Peripherals In order to provide good isolation from digital noise, the analogue peripherals and radio are powered by the radio regulator, which is supplied from the analogue supply VDD1 and referenced to analogue ground VSSA. A reference signal Vref for the ADC can be selected between an internal bandgap reference or an external voltage reference supplied to the VREF pin. ADC input 2 cannot be used if an external reference is required, as this uses the same pin as VREF. Note also that ADC3 and ADC4 use the same pins as DIO0 and DIO1 respectively. These pins can only be used for the ADC if they are not required for any of their alternative functions. Similarly, the comparator inputs are shared with DIO16 and DIO17. If used for their analogue functions, these DIOs must be put into a passive state by setting them to Inputs with their pull-ups disabled. The ADC is clocked from a common clock source derived from the 16MHz clock. 17.1 Analogue to Digital Converter The 10-bit analogue to digital converter (ADC) uses a successive approximation design to perform high accuracy conversions as typically required in wireless sensor network applications. It has six multiplexed single-ended input channels: four available externally, one connected to an internal temperature sensor, and one connected to an internal supply monitoring circuit. 54 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 17.1.1 Operation The input range of the ADC can be set between 0V to either the reference voltage or twice the reference voltage. The reference can be either taken from the internal voltage reference or from the external voltage applied to the VREF pin. For example, an external reference of 1.2V supplied to VREF may be used to set the ADC range between 0V and 2.4V. VREF Gain Setting Maximum Input Range Supply Voltage Range (VDD) 1.2V 1.6V 1.2V 1.6V 0 0 1 1 1.2V 1.6V 2.4V 3.2V 2.2V - 3.6V 2.2V - 3.6V 2.6V - 3.6V 3.4V - 3.6V Table 9: ADC Maximum Input Range The input clock to the ADC is 16MHz and can be divided down to 2MHz, 1MHz, 500kHz and 250kHz. During an ADC conversion the selected input channel is sampled for a fixed period and then held. This sampling period is defined as a number of ADC clock periods and can be programmed to 2, 4, 6 or 8. The conversion rate is ((3 x Sample period) + 13) clock periods. For example for 500kHz conversion with sample period of 2 will be (3 x 2) + 13 = 19 clock periods, 38µsecs or 26.32kHz. The ADC can be operated in either a single conversion mode or alternatively a new conversion can be started as soon as the previous one has completed, to give continuous conversions. If the source resistance of the input voltage is 1kΩ or less, then the default sampling time of 2 clocks should be used. The input to the ADC can be modelled as a resistor of 5kΩ(typ) and 10kΩ (max) to represent the on-resistance of the switches and the sampling capacitor 8pF. The sampling time required can then be calculated, by adding the sensor source resistance to the switch resistance, multiplying by the capacitance giving a time constant. Assuming normal exponential RC charging, the number of time constants required to give an acceptable error can be calculated, 7 time constants gives an error of 0.091%, so for 10-bit accuracy 7 time constants should be the target. For a source with zero resistance, 7 time constants is 640 nsecs, hence the smallest sampling window of 2 clock periods can be used. Sample Switch 5 K ADC pin ADC front end 8 pF Figure 38: ADC Input Equivalent Circuit The ADC sampling period, input range and mode (single shot or continuous) are controlled through software. When the ADC conversion is complete, an interrupt is generated. Alternatively the conversion status can be polled. When operating in continuous mode, it is recommended that the interrupt is used to signal the end of a conversion, since conversion times may range from 9.5 to 148 µsecs. Polling over this period would be wasteful of processor bandwidth. To facilitate averaging of the ADC values, which is a common practice in microcontrollers, a dedicated accumulator has been added, the user can define the accumulation to occur over 2,4,8 or 16 samples. The end of conversion interrupt can be modified to occur at the end of the chosen accumulation period, alternatively polling can still be used. Software can then be used to apply the appropriate rounding and shifting to generate the average value, as well as setting up the accumulation function. For detailed electrical specifications, see Section 19.3.7. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 55 17.1.2 Supply Monitor The internal supply monitor allows the voltage on the analogue supply pin VDD1 to be measured. This is achieved with a potential divider that reduces the voltage by a factor of 0.666, allowing it to fall inside the input range of the ADC when set with an input range twice the internal voltage reference. The resistor chain that performs the voltage reduction is disabled until the measurement is made to avoid a continuous drain on the supply. 17.1.3 Temperature Sensor The on chip temperature sensor can be used either to provide an absolute measure of the device temperature or to detect changes in the ambient temperature. In common with most on chip temperature sensors, it is not trimmed and so the absolute accuracy variation is large; the user may wish to calibrate the sensor prior to use. The sensor forces a constant current through a forward biased diode to provide a voltage output proportional to the chip die temperature which can then be measured using the ADC. The measured voltage has a linear relationship to temperature as described in Section 19.3.13. Because this sensor is on chip, any measurements taken must account for the thermal time constants. For example, if the device just came out of sleep mode the user application should wait until the temperature has stabilised before taking a measurement. 17.1.4 ADC Sample Buffer Mode In this mode, the ADC operates in conjunction with a DMA (Direct Memory Access) engine as follows: • ADC sampling is triggered at a configurable rate using one of the on-chip Timers (Timer 0, 1, 2, 3 or 4) • ADC samples are automatically stored in a buffer located in RAM using a DMA mechanism • ADC inputs may be multiplexed between different analogue sources The 10-bit ADC data samples are transferred into the buffer in RAM as 16-bit words. The maximum number of 16-bit words that may allocated in RAM for ADC sample storage is 2047. The buffer may be configured to automatically wrap around to the start when full. Interrupts may be configured to indicate when the buffer is half-full, full and has overflowed. The CPU may perform other tasks while the data transfer and storage is being managed independently by the DMA engine - the CPU only needs to configure the ADC sample buffer mode and deal with the stored samples in the buffer when an interrupt occurs. ADC sample buffer mode allows up to six analogue inputs to be multiplexed in combination. These inputs comprise four external inputs (ADC1-4, corresponding to IO pins), an on-chip temperature sensor and an internal voltage monitor. Samples from all the selected inputs will be produced on each timer trigger and stored in consecutive RAM locations. 17.2 Comparator The JN516x contains one analogue comparator, COMP1, that is designed to have true rail-to-rail inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level can be set to a nominal value of 0mV, 10mV, 20mV or 40mV. The source of the negative input signal for the comparator can be set to the internal voltage reference, the negative external pin (COMP1M, which uses the same pin as DIO17) or the positive external pin (COMP1P, on the same pin as DIO16). The source of the positive input signal can be COMP1P or COMP1M. DIO16 and DIO17 cannot be used if the external comparator inputs are needed. The comparator output is routed to an internal register and can be polled, or can be used to generate interrupts. The comparator can be disabled to reduce power consumption. DIO16 and DIO17 should be set to inputs with pull-ups disabled, when using the comparator. The comparator also has a low power mode where the response time of the comparator is slower than the normal mode, but the current required is greatly reduced. These figures are specified in Section 19.3.8. It is the only mode that may be used during sleep, where a transition of the comparator output will wake the device. The wakeup action and the configuration for which edge of the comparator output will be active are controlled through software. In sleep mode the negative input signal source must be configured to be driven from the external pins. 56 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 18 Power Management and Sleep Modes 18.1 Operating Modes Three operating modes are provided in the JN516x that enable the system power consumption to be controlled carefully to maximise battery life. • Active Processing Mode • Sleep Mode • Deep Sleep Mode The variation in power consumption of the three modes is a result of having a series of power domains within the chip that may be controllably powered on or off. 18.1.1 Power Domains The JN516x has the following power domains: • VDD Supply Domain: supplies the wake-up timers and controller, DIO blocks, Comparator, SVM and BOR plus Fast RC, 32kHz RC and crystal oscillators. This domain is driven from the external supply (battery) and is always powered. The wake-up timers and controller, and the 32kHz RC and crystal oscillators may be powered on or off in sleep mode through software control. • Digital Logic Domain: supplies the digital peripherals, CPU, Flash, RAM when in Active Processing Mode, Baseband controller, Modem and Encryption processor. It is powered off during sleep mode. • RAM Domain: supplies the RAM when in Active Processing Mode. Also supplies the Ram during sleep mode to retain the memory contents. It may be powered on or off for sleep mode through software control. • Radio Domain: supplies the radio interface, ADCs and temperature sensor. It is powered during transmit and receive and when the analogue peripherals are enabled. It is controlled by the baseband processor and is powered off during sleep mode. The current consumption figures for the different modes of operation of the device is given in Section 19.2.2. 18.2 Active Processing Mode Active processing mode in the JN516x is where all of the application processing takes place. By default, the CPU will execute at the selected clock speed executing application firmware. All of the peripherals are available to the application, as are options to actively enable or disable them to control power consumption; see specific peripheral sections for details. Whilst in Active processing mode there is the option to doze the CPU but keep the rest of the chip active; this is particularly useful for radio transmit and receive operations, where the CPU operation is not required therefore saving power. 18.2.1 CPU Doze Whilst in doze mode, CPU operation is stopped but the chip remains powered and the digital peripherals continue to run. Doze mode is entered through software and is terminated by any interrupt request. Once the interrupt service routine has been executed, normal program execution resumes. Doze mode uses more power than sleep and deep sleep modes but requires less time to restart and can therefore be used as a low power alternative to an idle loop. Whilst in CPU doze the current associated with the CPU is not consumed, therefore the basic device current is reduced as shown in the figures in Section 19.2.2.1. 18.3 Sleep Mode The JN516x enters sleep mode through software control. In this mode most of the internal chip functions are shutdown to save power, however the state of DIO pins are retained, including the output values and pull-up enables, and this therefore preserves any interface to the outside world. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 57 When entering into sleep mode, there is an option to retain the RAM contents throughout the sleep period. If the wakeup timers are not to be used for a wakeup event and the application does not require them to run continually, then power can be saved by switching off the 32kHz oscillator if selected as the 32kHz system clock through software control. The oscillator will be restarted when a wakeup event occurs. Whilst in sleep mode one of four possible events can cause a wakeup to occur: transitions on DIO inputs, expiry of wakeup timers, pulse counters maturing or comparator events. If any of these events occur, and the relevant interrupt is enabled, then an interrupt is generated that will cause a wakeup from sleep. It is possible for multiple wakeup sources to trigger an event at the same instant and only one of them will be accountable for the wakeup period. It is therefore necessary in software to remove all other pending wakeup events prior to requesting entry back into sleep mode; otherwise, the device will re-awaken immediately. When wakeup occurs, a similar sequence of events to the reset process described in Section 6.1 happens, including the checking of the supply voltage by the Supply Voltage Monitor 6.4. The High-Speed RC oscillator is started up, once stable the power to CPU system is enabled and the reset is removed. Software determines that this is a reset from sleep and so commences with the wakeup process. If RAM contents were held through sleep, wakeup is quicker as the software does not have to initialise RAM contents meaning the application can recommence more quickly. See Section 19.3.5 for wake-up timings. 18.3.1 Wakeup Timer Event The JN516x contains two 41-bit wakeup timers that are counters clocked from the 32kHz oscillator, and can be programmed to generate a wake-up event. Following a wakeup event, the timers continue to run. These timers are described in Section 11.3. Timer events can be generated from both of the two timers; one is intended for use by the 802.15.4 protocol, the other being available for use by the Application running on the CPU. These timers are available to run at any time, even during sleep mode. 18.3.2 DIO Event Any DIO pin when used as an input has the capability, by detecting a transition, to generate a wake-up event. Once this feature has been enabled the type of transition can be specified (rising or falling edge). Even when groups of DIO lines are configured as alternative functions such as the UARTs or Timers etc, any input line in the group can still be used to provide a wakeup event. This means that an external device communicating over the UART can wakeup a sleeping device by asserting its RTS signal pin (which is the CTS input of the JN516x). 18.3.3 Comparator Event The comparator can generate a wakeup interrupt when a change in the relative levels of the positive and negative inputs occurs. The ability to wakeup when continuously monitoring analogue signals is useful in ultra-low power applications. For example, the JN516x can remain in sleep mode until the voltage drops below a threshold and then be woken up to deal with the alarm condition and the comparator has a low current mode to facilitate this. 18.3.4 Pulse Counter The JN516x contains two 16 bit pulse counters that can be programmed to generate a wake-up event. Following the wakeup event the counters will continue to operate and therefore no pulse will be missed during the wake-up process. These counters are described in Section 12.To minimize sleep current it is possible to disable the 32K RC oscillator and still use the pulse counters to cause a wake-up event, provided debounce mode is not required. 18.4 Deep Sleep Mode Deep sleep mode gives the lowest power consumption. All switchable power domains are off and most functions in the VDD supply power domain are stopped, including the 32kHz RC oscillator. However, the Brown-Out Reset remains active as well as all the DIO cells. This mode can be exited by a hardware reset on the RESETN pin, or an enabled DIO or comparator wakeup event. In all cases, the wakeup sequence is equivalent to a power-up sequence, with no knowledge retained from the previous time the device was awake. 58 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 19 Electrical Characteristics 19.1 Maximum Ratings Exceeding these conditions may result in damage to the device. Parameter Min Max Device supply voltage VDD1, VDD2 -0.3V 3.6V Supply voltage at voltage regulator bypass pins VB_xxx -0.3V 1.98V Voltage on analogue pins XTALOUT, XTALIN, VCOTUNE, RF_IN. -0.3V VB_xxx + 0.3V Voltage on analogue pins VREF, ADC1, IBIAS -0.3V VDD1 + 0.3V Voltage on any digital pin -0.3V VDD2 + 0.3V Storage temperature -40ºC 150ºC Reflow soldering temperature according to IPC/JEDEC J-STD-020C ESD rating Human Body Model 260ºC 1 Charged Device Model 2.0kV 2 500V 1) Testing for Human Body Model discharge is performed as specified in JEDEC Standard JESD22-A114. 2) Testing for Charged Device Model discharge is performed as specified in JEDEC Standard JESD22-C101. 19.2 DC Electrical Characteristics 19.2.1 Operating Conditions Supply Min Max VDD1, VDD2 2.0V 3.6V Standard Ambient temperature range -40ºC 85ºC Extended Ambient temperature range -40ºC 125ºC In the following sections typical is defined as 25ºC and VDD1,2 = 3V Most parameter values cover the extended temperature range up to 125 ºC, where this is not the case, two values are given, the value in italics type face is for standard temperature range up to 85ºC and the value in bold is for the extended range. © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 59 19.2.2 DC Current Consumption VDD = 2.0 to 3.6V, -40 to +125º C 19.2.2.1 Active Processing Mode: Min CPU processing 32,16,8,4,2 or 1MHz Typ Max Unit Notes 1700 + 205/MHz µA GPIOs enabled. When in CPU doze the current related to CPU speed is not consumed. Radio transmit 15.3 mA CPU in software doze – radio transmitting Radio receive 17.0 mA CPU in software doze – radio in receive mode The following current figures should be added to those above if the feature is being used ADC Comparator UART Timer 2-wire serial interface (I2C) 550 µA Temperature sensor and battery measurements require ADC 73/0.8 µA Normal/low-power 60 µA 21 µA 46 µA For each UART For each Timer 19.2.2.2 Sleep Mode Mode: Min Typ Max Unit Notes Sleep mode with I/O wakeup 0.12 µA Waiting on I/O event Sleep mode with I/O and RC Oscillator timer wakeup – measured at 25ºC 0.64 µA As above, but also waiting on timer event. If both wakeup timers are enabled then add another 0.05µA 32kHz crystal oscillator 1.4 µA As alternative sleep timer The following current figures should be added to those above if the feature is being used RAM retention– measured at 25ºC 0.9 µA Comparator (low-power mode) 0.8 µA Reduced response time 19.2.2.3 Deep Sleep Mode Mode: Deep sleep mode– measured at 25ºC 60 Min Typ Max 100 JN-DS-JN516x v1.3 Production Unit nA Notes Waiting on chip RESET or I/O event © NXP Laboratories UK 2013 19.2.3 I/O Characteristics VDD = 2.0 to 3.6V, -40 to +125º C, italic +85 ºC Bold +125 ºC Parameter Internal DIO pullup resistors Internal RESETN pullup resistor Min Typ Max Unit 40 50 60 267 325 455 605 410 500 700 930 615. 636 750, 775 1050, 1085 1395, 1441 kΩ kΩ Digital I/O High Input VDD2 x 0.7 VDD2 V Digital I/O low Input -0.3 VDD2 x 0.27 V Digital I/O input hysteresis 200 400 mV 310 Notes VDD2 = 3.6V VDD2 = 3.0V VDD2 = 2.2V VDD2 = 2.0V DIO High O/P (2.7-3.6V) VDD2 x 0.8 VDD2 V With 4mA load DIO Low O/P (2.7-3.6V) 0 0.4 V With 4mA load DIO High O/P (2.2-2.7V) VDD2 x 0.8 VDD2 V With 3mA load DIO Low O/P (2.2-2.7V) 0 0.4 V With 3mA load DIO High O/P (2.0-2.2V) VDD2 x 0.8 VDD2 V With 2.5mA load DIO Low O/P (2.0-2.2V) 0 0.4 V With 2.5mA load mA VDD2 = 2.7V to 3.6V VDD2 = 2.2V to 2.7V VDD2 = 2.0V to 2.2V Current sink/source capability 4 3 2.5 IIL - Input Leakage Current 20, 30 nA Vcc = 3.6V, pin low IIH - Input Leakage Current 20, 60 nA Vcc = 3.6V, pin high 19.3 AC Characteristics 19.3.1 Reset and Supply Voltage Monitor VPOT VDD Internal RESET tSTAB Figure 39: Internal Power-on Reset without Showing Brown-Out © NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 61 tRST VRST RESETN Internal RESET tSTAB Figure 40: Externally Applied Reset VDD = 2.0 to 3.6V, -40 to +125º C Parameter External Reset pulse width to initiate reset sequence (tRST) External Reset threshold voltage (VRST) Min Typ Max Unit Notes 1 µs Assumes internal pullup resistor value of 100K worst case and ~5pF external capacitance VDD2 x 0.7 V Minimum voltage to avoid being reset Internal Power-on Reset threshold voltage (VPOT) Rise/fall time > 10mS 1.44 1.41 V Rising Falling Spike Rejection Square wave pulse 1us Triangular wave pulse 10us 1.2 1.3 V Depth of pulse to trigger reset Reset stabilisation time (tSTAB) 180 µs Note 1 Chip current when held in reset (IRESET) 6 uA Brown-Out Reset Current Consumption 80 nA Supply Voltage Monitor Threshold Voltage (VTH) Supply Voltage Monitor Hysteresis (VHYS) 1 1.86 1.92 2.02 2.11 2.21 2.30 2.59 2.88 1.94 2.00 2.10 2.20 2.30 2.40 2.70 3.00 2.00 2.06 2.16 2.27 2.37 2.47 2.78 3.09 37 38 45 52 58 65 82 100 V Configurable threshold with 8 levels mV Corresponding to the 8 threshold levels Time from release of reset to start of executing of bootloader code from internal flash. An extra 15us is incurred if the BOR circuit has been activated (e.g., if the supply voltage has been ramped up from 0V)". 62 JN-DS-JN516x v1.3 Production © NXP Laboratories UK 2013 DVDD VTH + VHYS VTH VPOT Internal SVM Internal BORest Figure 41 Brown-out Reset Followed By Supply Voltage Montior trigger 19.3.2 SPI Master Timing SS CLK (mode=0,1) tSSH tSSS tCK CLK (mode=2,3) tHI MISO (mode=0,2) tSI tHI MISO (mode=1,3) tSI tVO MOSI (mode=1,3) tVO MOSI (mode=0,2) Figure 42: SPI Master Timing Parameter Symbol Min Max Unit Clock period tCK 62.5 - ns Data setup time tSI 16.7 @ 3.3V 18.2 @ 2.7V 21.0 @ 2.0V - ns Data hold time tHI 0 Data invalid period tVO - 15 ns Select set-up period tSSS 60 - ns Select hold period tSSH 30 (SPICLK = 16MHz) 0 (SPICLK