NXP Semiconductors
Data Sheet: Technical Data
K32L2B3x
Rev. 3, 09/2020
K32 L2B Microcontroller
K32L2B31Vxx0A
K32L2B21Vxx0A
K32L2B11Vxx0A
48 MHz Arm® Cortex®-M0+ and 64/128/256 KB Flash
The K32 L2B series is optimized for cost-sensitive and batterypowered applications requiring low-power USB connectivity and
an optional segment LCD (SLCD). The product offers:
• Optional low power segment LCD up to 24x8 or 28x4
• USB FS 2.0 device without requiring an external crystal
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Down to 54 uA/MHz in very low power run mode and 1.96
uA in deep sleep mode (RAM + RTC retained)
Core Processor
• Arm® Cortex®-M0+ core up to 48 MHz
Memories
• 64/128/256 KB program flash memory
• 32 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and
debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference
clock
• 8 MHz/2 MHz high accuracy (up to 3%) internal
reference clock
• 1 KHz reference clock active under all low-power
modes (except VLLS0)
• 32–40 KHz and 3–32 MHz crystal oscillator
32 QFN
5x5 mm P 0.5 mm
48 QFN
7x7 mm P 0.5 mm
64 LQFP
10x10 mm P 0.5 mm
64 BGA
5x5 mm P 0.5 mm
Peripherals
• SLCD supporting up to 24x8 or 28x4 segments
• USB full-speed 2.0 device controller supporting
crystal-less operation
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1
Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of
additional UART, SPI, I2C, PWM and other serial
modules, etc.
• One 16-bit 461 ksps ADC module with high
accuracy internal voltage reference (Vref) and up to
16 channels
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
• One 12-bit DAC
• 1.2 V internal voltage reference
I/O
• Up to 50 general-purpose input/output pins (GPIO)
and 6 high-drive pad
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
Packages
• 64 LQFP 10mm x 10mm, 0.5 mm pitch, 1.6 mm
thickness
Security and Integrity
• 64 MAPBGA 5mm x 5mm, 0.5 mm pitch, 1.23 mm
• 80-bit unique identification number per chip
thickness
• Advanced flash security
• 48 QFN 7mm x 7mm, 0.5 mm pitch, 0.65 mm thickness
• 32 QFN 5mm x 5mm, 0.5 mm pitch, 0.65 mm thickness
Low Power
• Down to 54 μA/MHz in very low power run mode
• Down to 1.96 μA in VLLS3 mode (RAM + RTC
retained)
• Six flexible static modes
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Selector Guide is a web-based tool that features interactive
application wizards and a dynamic product selector.
Selector Guide
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K32L2B3xRM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for K32L2B_1N71K1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
64-LQFP: 98ASS23234W, 64MAPBGA: 98ASA00420D, 32QFN: 98ASA00615D, 48-QFN:
98ASA00616D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
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NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Table of Contents
1 Ordering information............................................................4
2 Overview............................................................................. 4
2.1 System features........................................................... 5
2.1.1
Arm Cortex-M0+ core.................................... 5
2.1.2
NVIC.............................................................. 6
2.1.3
AWIC............................................................. 6
2.1.4
Memory..........................................................7
2.1.5
Reset and boot.............................................. 7
2.1.6
Clock options................................................. 9
2.1.7
Security..........................................................12
2.1.8
Power management.......................................12
2.1.9
LLWU.............................................................14
2.1.10 Debug controller............................................ 15
2.1.11 COP............................................................... 15
2.2 Peripheral features.......................................................16
2.2.1
Segment LCD (SLCD)................................... 16
2.2.2
BME............................................................... 16
2.2.3
DMA and DMAMUX.......................................16
2.2.4
TPM............................................................... 17
2.2.5
ADC............................................................... 18
2.2.6
VREF............................................................. 19
2.2.7
CMP...............................................................19
2.2.8
DAC............................................................... 20
2.2.9
RTC............................................................... 20
2.2.10 PIT................................................................. 20
2.2.11 LPTMR...........................................................21
2.2.12 UART............................................................. 21
2.2.13 LPUART.........................................................22
2.2.14 SPI................................................................. 23
2.2.15 I2C................................................................. 23
2.2.16 USB............................................................... 24
2.2.17 FlexIO............................................................ 24
2.2.18 Port control and GPIO................................... 25
4.4.7
Human-machine interfaces (HMI)..................42
4.5 K32 L2B LQFP and MAPBGA pinouts.........................43
4.6 K32 L2B QFN Pinouts..................................................45
4.7 Package dimensions....................................................47
5 Electrical characteristics......................................................54
5.1 Ratings.........................................................................54
5.1.1
Thermal handling ratings............................... 54
5.1.2
Moisture handling ratings...............................55
5.1.3
ESD handling ratings..................................... 55
5.1.4
Voltage and current operating ratings............55
5.2 General........................................................................ 56
5.2.1
AC electrical characteristics...........................56
5.2.2
Nonswitching electrical specifications............56
5.2.3
Switching specifications.................................71
5.2.4
Thermal specifications................................... 72
5.3 Peripheral operating requirements and behaviors....... 73
5.3.1
Core modules................................................ 73
5.3.2
System modules............................................ 75
5.3.3
Clock modules............................................... 75
5.3.4
Memories and memory interfaces................. 78
5.3.5
Security and integrity modules.......................80
5.3.6
Analog............................................................80
5.4 Timers.......................................................................... 91
5.5 Communication interfaces........................................... 91
5.5.1
USB electrical specifications..........................91
5.5.2
USB VREG electrical specifications.............. 92
5.5.3
SPI switching specifications...........................92
5.5.4
I2C................................................................. 97
5.5.5
UART............................................................. 98
5.6 Human-machine interfaces (HMI)................................ 99
5.6.1
LCD electrical characteristics........................ 99
6 Design considerations......................................................... 100
6.1 Hardware design considerations..................................100
3 Memory map....................................................................... 26
4 Pinouts................................................................................ 27
4.1 K32 L2B Signal Multiplexing and Pin Assignments
(LQFP and MAPBGA)..................................................27
4.2 K32 L2B Signal Multiplexing and Pin Assignments
(QFN)........................................................................... 30
4.3 Pin properties...............................................................32
4.4 Module Signal Description Tables............................... 37
4.4.1
Core modules................................................ 37
4.4.2
System modules............................................ 37
4.4.3
Clock modules............................................... 38
4.4.4
Analog............................................................38
4.4.5
Timer Modules............................................... 39
4.4.6
Communication interfaces............................. 40
6.1.1
Printed circuit board recommendations......... 100
6.1.2
Power delivery system...................................101
6.1.3
Analog design................................................ 102
6.1.4
Digital design................................................. 102
6.1.5
Crystal oscillator............................................ 105
6.2 Software considerations...............................................107
Part identification.................................................................107
7.1 Description................................................................... 107
7.2 Format..........................................................................108
7.3 Fields........................................................................... 108
7.4 Example....................................................................... 108
Small package marking....................................................... 109
Package marking information..............................................109
Revision History.................................................................. 110
K32 L2B Microcontroller, Rev. 3, 09/2020
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NXP Semiconductors
Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Memory
Package
IO and ADC channel
Serial
Interface
Part number
Flash
(KB)
SRAM
(KB)
Pin
count
Package
GPIOs
GPIOs
(INT/HD)1
ADC
channels
(SE/DP)
SLCD
K32L2B31VLH0A
256
32
64
LQFP
50
31/6
16/2
Yes
K32L2B31VMP0A
256
32
64
MAPBGA
50
31/6
16/2
Yes
K32L2B31VFT0A
256
32
48
QFN
36
24/6
14/1
—
K32L2B31VFM0A
256
32
32
QFN
23
19/6
7/0
—
K32L2B21VLH0A
128
32
64
LQFP
50
31/6
16/2
Yes
K32L2B21VMP0A
128
32
64
MAPBGA
50
31/6
16/2
Yes
K32L2B21VFT0A
128
32
48
QFN
36
24/6
14/1
—
K32L2B21VFM0A
128
32
32
QFN
23
19/6
7/0
—
K32L2B11VLH0A
64
32
64
LQFP
50
31/6
16/2
Yes
K32L2B11VMP0A
64
32
64
MAPBGA
50
31/6
16/2
Yes
K32L2B11VFT0A
64
32
48
QFN
36
24/6
14/1
—
K32L2B11VFM0A
64
32
32
QFN
23
19/6
7/0
—
1. INT: interrupt pin numbers; HD: high drive pin numbers
2 Overview
The following figure shows the system diagram of this device
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NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Overview
GPIOA
GPIOB
Slave
Master
Cortex M0+
GPIOC
GPIOD
GPIOE
CM0+ core
NVIC
M2
DMA
MUX
DMA
M3
FMC
S0
16 KB ROM
S1
32 KB RAM
S2
BME
USB FS Device Only
ADC(16-bit 16-ch)
64/128/256 KB
Flash
CMP
Peripheral Bridge(Bus Clock - Max 24MHZ)
Debug
(SWD)
M0
Crossabar Switch(Platform Clcok - Max 48MHZ)
IOPORT
1.2V Voltage reference
TPM0(6-channel)
TPM1(2-channel)
TPM2(2-channel)
LPTMR
PIT
RTC
LPUART0
LPUART1
UART2
SPI0
SPI1
I2C0
I2C1
FlexIO
Watchdog(COP)
MCG-Lite
OSC
Register File(32 Bytes)
HIRC48M
LLWU
LIRC2M/8M
SMC
RCM
PMC
SLCD
Figure 1. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
2.1 System features
The following sections describe the high-level system features.
K32 L2B Microcontroller, Rev. 3, 09/2020
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NXP Semiconductors
Overview
2.1.1 Arm Cortex-M0+ core
The enhanced Arm Cortex M0+ is the member of the Cortex-M series of processors
targeting microcontroller cores focused on very cost sensitive, low power applications.
It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It
also has hardware debug functionality including support for simple program trace
capability. The processor supports the ARMv6-M instruction set (Thumb) architecture
including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It
is upward compatible with other Cortex-M profile processors.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It
also differs in number of interrupt sources and supports 32 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency to up to 15
clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and
VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous
wake-up events in Stop mode and signal to clock control logic to resume system
clocking. After clock restarts, the NVIC observes the pending interrupt and performs
the normal interrupt or event processing. The AWIC can be used to wake MCU core
from Stop and VLPS modes.
Wake-up sources are listed as below:
Table 2. AWIC stop wake-up sources
Wake-up source
Description
Available system resets
RESET pin when LPO is its clock source
Low-voltage detect
Power management controller—functional in Stop mode
Low-voltage warning
Power management controller—functional in Stop mode
Pin interrupts
Port control module—any enabled pin interrupt is capable of waking the system
ADC
The ADC is functional when using internal clock source or external crystal clock
CMP0
Interrupt in normal or trigger mode
I2Cx
Address match wakeup
Table continues on the next page...
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NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Overview
Table 2. AWIC stop wake-up sources (continued)
Wake-up source
Description
LPUART0 , LPUART1
Any enabled interrupt can be a source as long as the module remains clocked
UART2
Active edge on RXD
RTC
Alarm or seconds interrupt
NMI
NMI pin
TPMx
Any enabled interrupt can be a source as long as the module remains clocked
LPTMR
Any enabled interrupt can be a source as long as the module remains clocked
SPIx
Slave mode interrupt
FlexIO
Any enabled interrupt can be a source as long as the module remains clocked
2.1.4 Memory
This device has the following features:
• 32 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait
states.
• The non-volatile memory is divided into two arrays
• Up to 256 KB of embedded program memory
• 16 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI
interfaces)
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program
flash is 1 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents
from debug port.
• System register file
This device contains a 32-byte register file that is powered in all power modes.
Also, it retains contents during low power modes and is reset only during a
power-on reset.
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Overview
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device.
NOTE
In the following table, Y means the specific module, except
for the registers, bits or conditions mentioned in the footnote,
is reset by the corresponding Reset source. N means the
specific module is not reset by the corresponding Reset
source.
Table 3. Reset source
Reset
sources
Descriptions
POR reset
Power-on reset (POR)
PMC
SIM
SMC
RCM
LLWU
Reset pin
is
negated
RTC
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y1
Y
Y
Y
Y
Y
N
Y
Y
Low leakage wakeup
(LLWU) reset
N
Y2
N
Y
N
Y3
N
N
Y
External pin reset
(RESET)
Y1
Y2
Y4
Y
Y
Y
N
N
Y
Computer operating
properly (COP) watchdog
reset
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
Stop mode acknowledge
error (SACKERR)
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
Software reset (SW)
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
Lockup reset (LOCKUP)
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
MDM DAP system reset
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
Debug reset
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
System resets Low-voltage detect (LVD)
Debug reset
1.
2.
3.
4.
5.
Modules
LPTMR Others
Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
Except SIM_SOPT1
Only if RESET is used to wake from VLLS mode.
Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
Except RCM_RPFC, RCM_RPFW, RCM_FM
The CM0+ core adds support for a programmable Vector Table Offset Register
(VTOR) to relocate the exception vector table after reset. This device supports booting
from:
• internal flash
• ROM
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K32 L2B Microcontroller, Rev. 3, 09/2020
Overview
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains
read-only bits that are loaded from the NVM's option byte in the flash configuration
field. Below is boot flow chart for this device.
POR or Reset
N
RCM[FORCEROM] =00
Y
FOPT[BOOTPIN_OPT]=0
N
Y
BOOTCFG0 pin=0
Y
N
N
FOPT[BOOTSRC
_SEL]=10/11
Y
Boot from ROM
Boot from Flash
Figure 2. Boot flow chart
The blank chip is default to boot from ROM and remaps the vector table to ROM base
address, otherwise, it remaps to flash address.
2.1.6 Clock options
This chip provides a wide range of sources to generate the internal clocks. These
sources include internal resistor capacitor (IRC) oscillators, external oscillators,
external clock sources, and ceramic resonators. These sources can be configured to
provide the required performance and optimize the power consumption.
The IRC oscillators include the high-speed internal resister capacitor (HIRC)
oscillator, the low-speed internal resister capacitor (LIRC) oscillator, and the low
power oscillator (LPO).
The HIRC oscillator generates a 48 MHz clock and synchronizes with the USB clock
in full speed mode to achieve the required accuracy.
The LIRC oscillator generates an 8 MHz or 2 MHz clock, and default to 8 MHz
system clock on reset. The LIRC oscillator cannot be used in any VLLS modes.
The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode.
K32 L2B Microcontroller, Rev. 3, 09/2020
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Overview
The system oscillator supports low frequency crystals (32 kHz to 40 kHz), high
frequency crystals (3 MHz to 32 MHz), and ceramic resonators (3 MHz to 32 MHz). An
external clock source, DC to 48 MHz, can be used as the system clock through the
EXTAL0 pin. The external oscillator also supports a low speed external clock (32.768
kHz) on the RTC_CLKIN pin for use with the RTC.
For more details on the clock operations and configurations, see Reference Manual.
The following figure is a high level block diagram of the clock generation.
Multipurpose Clock
Generator Lite
IRC_TRIMs
System
Integration
HIRC48M
USB
MCGPCLK
USB_EN
MCGIRCLK
CG
LIRC_DIV2
LIRC
8MHz/ 8MHz
2MHz
IRC
2MHz
MCGOUTCLK
FCRDIV
OUTDIV1
CG
Core/Platform/System clock
OUTDIV4
CG
Bus/Flash clock
IRCS
CLKS
System oscillator
EREFS0
EXTAL0
OSCCLK
XTAL_CLK
OSC
logic OSC32KCLK
XTAL0
OSCERCLK
CG
ERCLK32K
RTC_CKLIN
OS32KSEL
RTCCLKOUTSEL
RTC
Counter logic
PMC PMC logic
LPO
RTC_CLKOUT
1Hz
CG — Clock gate
Figure 3. Clock block diagram
In order to provide flexibility, many peripherals can select from multiple clock sources
for operation. This enables the peripheral to select a clock that will always be available
during operation in various operational modes.
The following table summarizes the clocks associated with each module.
Table 4. Module clocks
Module
Bus interface clock
Internal clocks
I/O interface clocks
Core modules
Table continues on the next page...
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K32 L2B Microcontroller, Rev. 3, 09/2020
Overview
Table 4. Module clocks (continued)
Module
Bus interface clock
Internal clocks
I/O interface clocks
Arm Cortex-M0+ core
Platform clock
Core clock
—
NVIC
Platform clock
—
—
DAP
Platform clock
—
SWD_CLK
System modules
DMA
System clock
—
—
DMA Mux
Bus clock
—
—
Port control
Bus clock
—
—
Crossbar Switch
Platform clock
—
—
Peripheral bridges
System clock
Bus clock
—
LLWU, PMC, SIM, RCM
Bus clock
LPO
—
Mode controller
Bus clock
—
—
MCM
Platform clock
—
—
COP watchdog
Bus clock
LPO, Bus Clock, MCGIRCLK,
OSCERCLK
—
Clocks
MCG_Lite
Bus clock
MCGOUTCLK, MCGPCLK,
MCGIRCLK, OSCERCLK,
ERCLK32K
—
OSC
Bus clock
OSCERCLK
—
Memory and memory interfaces
Flash Controller
Platform clock
Flash clock
—
Flash memory
Flash clock
—
—
Analog
ADC
Bus clock
OSCERCLK
—
CMP
Bus clock
—
—
Internal Voltage Reference
(VREF)
Bus clock
—
—
Timers
TPM
Bus clock
TPM clock
TPM_CLKIN0, TPM_CLKIN1
PIT
Bus clock
—
—
LPTMR
Bus clock
LPO, OSCERCLK,
MCGPCLK, ERCLK32K
—
RTC
Bus clock
ERCLK32K
RTC_CLKOUT, RTC_CLKIN
Communication interfaces
USB FS (Device Only)
System clock
USB FS clock
—
SPI0
Bus clock
—
SPI0_SCK
SPI1
System clock
—
SPI1_SCK
I2C0
System Clock
—
I2C0_SCL
I2C1
System Clock
—
I2C1_SCL
Table continues on the next page...
K32 L2B Microcontroller, Rev. 3, 09/2020
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Overview
Table 4. Module clocks (continued)
Module
Bus interface clock
Internal clocks
I/O interface clocks
LPUART0, LPUART1
Bus clock
LPUART0 clock
—
LPUART1 clock
UART2
Bus clock
—
—
FlexIO
Bus clock
FlexIO clock
—
Human-machine interfaces
GPIO
Platform clock
—
—
2.1.7 Security
Security state can be enabled via programming flash configuration field (0x40e). After
enabling device security, the SWD port cannot access the memory resources of the
MCU, and ROM boot loader is also limited to access flash and not allowed to read out
flash information via ROM boot loader commands.
Access interface
Secure state
Unsecure operation
SWD port
Cannot access memory source by SWD The debugger can write to the Flash
interface
Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
ROM boot loader Interface
(UART/I2C/SPI/USB)
Limit access to the flash, cannot read
out flash content
Send “FlashEraseAllUnsecureh"
command or attempt to unlock flash
security using the backdoor key
This device features 80-bit unique identification number, which is programmed in
factory and loaded to SIM register after power-on reset.
2.1.8 Power management
The Power Management Controller (PMC) expands upon Arm’s operational modes of
Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can
be used to optimize current consumption for a wide range of applications. The WFI or
WFE instruction invokes a Wait or a Stop mode, depending on the current
configuration. For more information on Arm’s operational modes, See the Arm®
Cortex User Guide.
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Overview
The PMC provides Run (Run), and Very Low Power Run (VLPR) configurations in
Arm’s Run operation mode. In these modes, the MCU core is active and can access all
peripherals. The difference between the modes is the maximum clock frequency of the
system and therefore the power consumption. The configuration that matches the
power versus performance requirements of the application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
Arm’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop
(LLS), and Very Low Leakage Stop (VLLS) configurations in Arm’s Deep Sleep
operational mode. In these modes, the MCU core and most of the peripherals are
disabled. Depending on the requirements of the application, different portions of the
analog, logic, and memory can be retained or disabled to conserve power.
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are
used to wake up the MCU from low power states. The NVIC is used to wake up the
MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU
core from STOP and VLPS modes. The LLWU is used to wake up the MCU core
from LLS and VLLSx modes.
For additional information regarding operational modes, power management, the
NVIC, AWIC, or the LLWU, please refer to the Reference Manual.
The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Table 6. Peripherals states in different operational modes
Core mode
Run mode
Sleep mode
Device mode
Descriptions
Run
In Run mode, all device modules are operational.
Very Low Power Run
In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Wait
In Wait mode, all peripheral modules are operational. The MCU core is
placed into Sleep mode.
Very Low Power Wait
In VLPW mode, all peripheral modules are operational at a reduced
frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
The MCU core is placed into Sleep mode.
Table continues on the next page...
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Overview
Table 6. Peripherals states in different operational modes (continued)
Core mode
Deep sleep
Device mode
Descriptions
Stop
In Stop mode, most peripheral clocks are disabled and placed in a static
state. Stop mode retains all registers and SRAMs while maintaining Low
Voltage Detection protection. In Stop mode, the ADC, CMP, LPTMR, RTC,
and pin interrupts are operational. The NVIC is disabled, but the AWIC can
be used to wake up from an interrupt.
Very Low Power Stop
In VLPS mode, the contents of the SRAM are retained. The CMP (low
speed), ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, USB, and DMA
are operational, LVD and NVIC are disabled, AWIC is used to wake up from
interrupt.
Low Leakage Stop
In LLS mode, the contents of the SRAM and the 32-byte system register file
are retained. The CMP (low speed), LLWU, LPTMR, and RTC are
operational. The ADC, DMA, FlexIO, I2C, LPUART, MCG-Lite, NVIC, PIT,
SPI, TPM, UART, USB, and COP are static, but retain their programming.
The GPIO, and VREF are static, retain their programming, and continue to
drive their previous values.
Very Low Leakage Stop In VLLS modes, most peripherals are powered off and will resume operation
from their reset state when the device wakes up. The LLWU, LPTMR, and
RTC are operational in all VLLS modes.
In VLLS3, the contents of the SRAM and the 32-byte system register file are
retained. The CMP (low speed), and PMC are operational. The GPIO, and
VREF are not operational but continue driving.
In VLLS1, the contents of the 32-byte system register file are retained. The
CMP (low speed), and PMC are operational. The GPIO, and VREF are not
operational but continue driving.
In VLLS0, the contents of the 32-byte system register file are retained. The
PMC is operational. The GPIO is not operational but continues driving. The
POR detection circuit can be enabled or disabled.
2.1.9 LLWU
The LLWU module is used to wake MCU from low leakage power mode (LLS and
VLLSx) and functional only on entry into a low-leakage power mode. After recovery
from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU
continues to detect wake-up events until the user has acknowledged the wake-up event.
This device uses 8 external wakeup pin inputs and 4 internal modules as wakeup
sources to the LLWU module.
The following is internal peripheral and external pin inputs as wakeup sources to the
LLWU module.
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Overview
Table 7. Wakeup source
LLWU pin
Module source or pin name
LLWU_P5
PTB0
LLWU_P6
PTC1
LLWU_P7
PTC3
LLWU_P8
PTC4
LLWU_P9
PTC5
LLWU_P10
PTC6
LLWU_P14
PTD4
LLWU_P15
PTD6
LLWU_M0IF
LPTMR0
LLWU_M1IF
CMP0
LLWU_M2IF
Reserved
LLWU_M3IF
Reserved
LLWU_M4IF
Reserved
LLWU_M5IF
RTC alarm
LLWU_M6IF
Reserved
LLWU_M7IF
RTC seconds
2.1.10 Debug controller
This device supports standard Arm 2-pin SWD debug port. It provides register and
memory accessibility from the external debugger interface, basic run/halt control plus
2 breakpoints and 2 watchpoints.
It also supports trace function with the Micro Trace Buffer (MTB), which provides a
simple execution trace capability for the Cortex-M0+ processor.
2.1.11 COP
The COP monitors internal system operation and forces a reset in case of failure. It
can run from bus clock, LPO, 8/2 MHz internal oscillator or external crystal oscillator.
Optional window mode can detect deviations in program flow or system frequency.
The COP has the following features:
• Support multiple clock input, 1 kHz clock(LPO), bus clock, 8/2 MHz internal
reference clock, external crystal oscillator
• Can work in Stop/VLPS and Debug mode
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Overview
• Configurable for short and long timeout values, the longest timeout is up to 262
seconds
• Support window mode
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip.
2.2.1 Segment LCD (SLCD)
The SLCD module is a CMOS charge pump voltage inverter that is designed for lowvoltage and low-power operation. SLCD is designed to generate the appropriate
waveforms to drive multiplexed numeric, alphanumeric, or custom segment LCD
panels. SLCD also has several timing and control settings that can be software
configured depending on the application's requirements. Timing and control consists of
registers and control logic for:
• LCD frame frequency
• Duty cycle selection
• Front plane/back plane selection and enabling
• Blink modes and frequency
• Operation in low-power modes
2.2.2 BME
The Bit Manipulation Engine (BME) provides hardware support for atomic readmodify-write memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for
bit-oriented operations to peripheral registers.
The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit,
bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized
data type.
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Overview
2.2.3 DMA and DMAMUX
The DMA controller module enables fast transfers of data, which provides an efficient
way to move blocks of data with minimal processor interaction. The DMA controller
in this device implements four channels which can be routed from up to 63 DMA
request sources through DMA MUX module. Some of the peripheral request sources
have asynchronous DMA capability which can be used to wake MCU from Stop
mode. The peripherals which have such capability include . The DMA channel 0 and
1 can be periodically triggered by PIT via DMA MUX.
Main features are listed below:
• Dual-address transfers via 32-bit master connection to the system bus and data
transfers in 8-, 16-, or 32-bit blocks
• Supports programmable source and destination address and transfer size, optional
modulo addressing from 16 bytes to 256 KB
• Automatic updates of source and destination addresses
• Auto-alignment feature for source or destination accesses allows block transfers
to occur at the optimal size based on the address, byte count,and programmed
size, which significantly improves the speed of block transfer
• Automatic single or double channel linking allows the current DMA channel to
automatically trigger a DMA request to the linked channels without CPU
intervention
For more information on asynchronous DMA, see AN4631.
2.2.4 TPM
This device contains three low power TPM modules (TPM). All TPM modules are
functional in Stop/VLPS mode if the clock source is enabled.
The TPM features include:
• TPM clock mode is selectable from external clock input, internal clock source,
external crystal input clock, MCGIRCLK clock or clocking from MCGFLLCLK
and MCGPLLCLK/2
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare,
edge-aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter
overflow
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• Support selectable trigger input to optionally reset or cause the counter to start or
stop incrementing
• Support the generation of hardware triggers when the counter overflows and per
channel
2.2.5 ADC
This device contains one ADC module. This ADC module supports hardware triggers
from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports
wakeup of MCU in low power mode when using internal clock source or external
crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the
clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-calibration mode
2.2.5.1
Temperature sensor
This device integrates one temperature sensor internally connected to the input channel
of AD26, see for details of the linearity factor.
The sensor provides good linearity, but it has to be calibrated to gain good accuracy, see
also AN3031. We recommend to use internal reference voltage as ADC reference with
long sample time.
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2.2.6 VREF
The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically)
trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage
to external devices or used internally as a reference to analog peripherals such as the
ADC or CMP.
The VREF supports the following programmable buffer modes:
• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled
The VREF voltage output signal, bonded on VREFH for 48 QFN, 64 LQFP and 64
MAPBGA packages and on PTE30 for 32 QFN packages, can be used by both
internal and external peripherals in low and high power buffer mode. A 100 nF
capacitor must always be connected between this pin and VSSA if the VREF is used.
This capacitor must be as close to VREF_OUT pin as possible.
2.2.7 CMP
The device contains one high-speed comparator and two 8-input multiplexers for both
the inverting and non-inverting inputs of the comparator. Each CMP input channel
connects to both muxes.
The CMP includes one 6-bit DAC, which provides a selectable voltage reference for
various user application cases. Besides, the CMP also has several module-to-module
interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: shorter propagation delay at the
expense of higher power and Low power with longer propagation delay
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Overview
•
•
•
•
DMA transfer support
Functional in all modes of operation except in VLLS0 mode
The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes
Integrated 6-bit DAC with selectable supply reference source and can be power
down to conserve power
• Two 8-to-1 channel mux
2.2.8 DAC
The 12-bit Digital-to-Analog Converter (DAC) is a low-power, general-purpose DAC.
The output of the DAC can be placed on an external pin or set as one of the inputs to
the analog comparator, op-amps, or ADC.
The features of the DAC module include:
• On-chip programmable reference generator output. The voltage output range is
from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage.
• Vin can be selected from two reference sources.
• Static operation in Normal Stop mode.
• 2-word data buffer supported with multiple operation modes.
• DMA support.
2.2.9 RTC
The RTC is an always powered-on block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an
external crystal using the oscillator or clock directly from RTC_CLKIN pin.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
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2.2.10 PIT
The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It
has two independent channels and each channel has a 32-bit counter. Both channels
can be chained together to form a 64-bit counter.
Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be
used to periodically trigger DMA channel 1. Either channel can be programmed as an
ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger
DAC.
The PIT module has the following features:
• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC
2.2.11 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
2.2.12 UART
This device contains a basic universal asynchronous receiver/transmitter (UART)
module with DMA function supported. Generally, this module is used in RS-232,
RS-485, and other communications. It also supports LIN slave operation and
ISO7816.
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Overview
The UART module has the following features:
• Full-duplex operation
• 13-bit baud rate selection with /32 fractional divide, based on the module clock
frequency
• Programmable 8-bit or 9-bit data format
• Programmable transmitter output polarity
• Programmable receive input polarity
• Up to 14-bit break character transmission.
• 11-bit break character detection option
• Two receiver wakeup methods with idle line or address mark wakeup
• Address match feature in the receiver to reduce address mark wakeup ISR overhead
• Ability to select MSB or LSB to be the first bit on wire
• Support for ISO 7816 protocol to interface with SIM cards and smart cards
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• DMA interface
2.2.13 LPUART
This product contains two Low-Power UART modules, both of their clock sources are
selectable from IRC48M, IRC8M/2M or external crystal clock, and can work in Stop
and VLPS modes. They also support 4x to 32x data oversampling rate to meet different
applications.
The LPUART module has the following features:
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock and can
be configured independently of the bus clock frequency, support operation in Stop
mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
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• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
2.2.14 SPI
This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes.
FIFO function is available only on SPI1 module.
The SPI modules have the following features:
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA
2.2.15 I2C
This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer
features, and address match to wake MCU from the low power mode.
I2C modules support DMA transfer, and the interrupt condition can trigger DMA
request when DMA function is enabled.
The I2C modules have the following features:
• Support for system management bus (SMBus) specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave
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Overview
•
•
•
•
•
•
•
•
•
•
•
•
Calling address identification interrupt
START and STOP signal generation and detection
Repeated-START signal generation and detection
Acknowledge bit generation and detection
Bus busy detection
General call recognition
10-bit address extension
Programmable input glitch filter
Low power mode wakeup on slave address match
Range slave address support
DMA support
Double buffering support to achieve higher baud rate
2.2.16 USB
This device contains one USB module which implements a USB2.0 full-speed
compliant peripheral and interfaces to the on-chip USBFS transceiver. It implements
keep-alive feature to avoid re-enumerating when exiting from low power modes and
enables HIRC48M to allow crystal-less USB operation.
The USBFS has the following features:
• USB 1.1 and 2.0 compliant full-speed device controller
• 16 bidirectional end points
• DMA or FIFO data stream interfaces
• Low-power consumption
• HIRC48 with clock-recovery is supported to eliminate the 48 MHz crystal. It is
used for USB device-only implementation.
• USB keeps alive in low power mode down to VLPS and is able to wake MCU from
low power mode
2.2.17 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols
including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform
generation. The module supports programmable baud rates independent of bus clock
frequency, with automatic start/stop bit generation.
The FlexIO module has the following features:
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Overview
• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using
remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match
modes, and continuous data transfer
• The timing of the shifter's shift, load and store events are controlled by the highly
flexible 16-bit timer assigned to the shifter
• Two or more shifters can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable
on a variety of internal or external trigger conditions with programmable trigger
polarity
• Flexible pin configuration supporting output disabled, open drain, bidirectional
output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation
2.2.18 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control,
digital filtering, and external interrupt functions. The GPIO data direction and output
data registers control the direction and output data of each pin when the pin is
configured for the GPIO function. The GPIO input data register displays the logic
value on each pin when the pin is configured for any digital function, provided the
corresponding Port Control and Interrupt module for that pin is enabled.
The PORT module has the following features:
• all PIN support interrupt enable
• Configurable edge (rising, falling, or both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable fast and slow slew rates on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
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Memory map
• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. The following figure shows the system memory and
peripheral locations
0x4000_0000
Reserved
0x4000_8000
DMA controller
0x4000_F000
0x4002_0000
0x0000_0000
0x4002_1000
Flash
0x0000_0000
0x07FF_FFFF
Code space
0x07FF_FFFF
0x1C00_0000
0x1C00_0000
ROM
Boot ROM
0x1C00_3FFF
0x1C00_4000
0x1FFF_E000
Data Space
0x2000_5FFF
SRAM_L
0x2000_0000
Reserved
SRAM_U
0x4000_0000
0x2000_5FFF
Public
peripheral
0x4000_0000
0x400F_F000
0x4400_0000
0x6000_0000
0xE000_0000
0xE010_0000
0x4007_FFFF
Reserved
AIPS
peripherals
0x400F_F000
BME
Reserved
0x400F_FFFF
Private
peripheral
GPIO
Reserved
MTB
MTBDWT
Others
Others
ROM Table
MCM
0xFFFF_FFFF
Reserved
IOPORT
Flash memory
DMA Channel Multiplexer
0x4003_7000
PIT
0x4003_8000
LPTPM0
0x4003_9000
LPTPM1
0x4003_A000
LPTPM2
0x4003_B000
ADC0
0x4003_D000
RTC
0x4003_F000
DAC
0x4004_0000
LPTMR
0x4004_1000
0x4004_7000
0x1FFF_E000
GPIO Controller (alias to 0x400F_F000)
System register file
SIM low power logic
0x4004_8000
SIM
0x4004_9000
PORTA
0x4004_A000
PORTB
0x4004_B000
PORTC
0x4004_C000
PORTD
0x4004_D000
PORTE
0x4005_3000
SLCD
0x4005_4000
LPUART0
0x4005_5000
LPUART1
0x4005_F000
FlexIO
0x4006_4000
MCG Lite
0x4006_5000
OSC
0x4006_6000
I2C0
0x4006_7000
I2C1
0x4006_C000
UART2
0x4007_2000
USB
0x4007_3000
CMP
0x4007_4000
VREF
0x4007_6000
SPI0
0x4007_7000
SPI1
0x4007_C000
LLWU
0x4007_D000
PMC
0x4007_E000
SMC
0x4007_F000
RCM
GPIO
0x400F_F000
Figure 4. Memory map
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Pinouts
4 Pinouts
4.1 K32 L2B Signal Multiplexing and Pin Assignments (LQFP
and MAPBGA)
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
VREFH can act as VREF_OUT when VREFV1 module is
enabled.
NOTE
When FTFA_FOPT[RESET_PIN_CONFIG]=0, the PTA20
pin acts as RESET_B function only during the POR. After
POR, this pin cannot be used as the RESET function. Then,
writing to PORTA_PCR20[MUX]=0x1, the PTA20 pin will
act as GPIO function (with setting value of ALT1). When
FTFA_FOPT[RESET_PIN_CONFIG]=1, the PTA20 pin
acts as RESET_B and cannot switch to GPIO function
regardless of PORTA_PCR20[MUX]'s setting value.
64
64
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
A1
1
PTE0
LCD_P48
LCD_P48
PTE0/
CLKOUT32K
SPI1_MISO
LPUART1_TX RTC_CLKOUT CMP0_OUT
I2C1_SDA
LCD_P48
B1
2
PTE1
LCD_P49
LCD_P49
PTE1
SPI1_MOSI
LPUART1_RX
I2C1_SCL
LCD_P49
—
3
VDD
VDD
VDD
C4
4
VSS
VSS
VSS
E1
5
USB0_DP
USB0_DP
USB0_DP
D1
6
USB0_DM
USB0_DM
USB0_DM
E2
7
VOUT33
VOUT33
VOUT33
D2
8
VREGIN
VREGIN
VREGIN
G1
9
PTE20
LCD_P59/
ADC0_DP0/
ADC0_SE0
LCD_P59/
ADC0_DP0/
ADC0_SE0
FXIO0_D4
LCD_P59
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PTE20
TPM1_CH0
SPI1_MISO
LPUART0_TX
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64
64
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LCD_P60
F1
10
PTE21
LCD_P60/
ADC0_DM0/
ADC0_SE4a
LCD_P60/
ADC0_DM0/
ADC0_SE4a
PTE21
TPM1_CH1
LPUART0_RX
FXIO0_D5
G2
11
PTE22
ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
PTE22
TPM2_CH0
UART2_TX
FXIO0_D6
F2
12
PTE23
ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
PTE23
TPM2_CH1
UART2_RX
FXIO0_D7
F4
13
VDDA
VDDA
VDDA
G4
14
VREFH
VREFH
VREFH
G3
15
VREFL
VREFL
VREFL
F3
16
VSSA
VSSA
VSSA
H1
17
PTE29
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
TPM0_CH2
TPM_CLKIN0
H2
18
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
PTE30
TPM0_CH3
TPM_CLKIN1
H3
19
PTE31
DISABLED
PTE31
TPM0_CH4
H4
20
PTE24
DISABLED
PTE24
TPM0_CH0
I2C0_SCL
H5
21
PTE25
DISABLED
PTE25
TPM0_CH1
I2C0_SDA
D3
22
PTA0
SWD_CLK
PTA0
TPM0_CH5
D4
23
PTA1
DISABLED
PTA1
LPUART0_RX TPM2_CH0
E5
24
PTA2
DISABLED
PTA2
LPUART0_TX TPM2_CH1
D5
25
PTA3
SWD_DIO
PTA3
I2C1_SCL
TPM0_CH0
SWD_DIO
G5
26
PTA4
NMI_b
PTA4
I2C1_SDA
TPM0_CH1
NMI_b
USB_CLKIN
TPM0_CH2
LPUART1_TX LPTMR0_
ALT1
SWD_CLK
F5
27
PTA5
DISABLED
PTA5
H6
28
PTA12
DISABLED
PTA12
TPM1_CH0
G6
29
PTA13
DISABLED
PTA13
TPM1_CH1
G7
30
VDD
VDD
VDD
H7
31
VSS
VSS
VSS
H8
32
PTA18
EXTAL0
EXTAL0
PTA18
LPUART1_RX TPM_CLKIN0
G8
33
PTA19
XTAL0
XTAL0
PTA19
LPUART1_TX TPM_CLKIN1
F8
34
PTA20
RESET_b
F7
35
PTB0/
LLWU_P5
LCD_P0/
ADC0_SE8
LCD_P0/
ADC0_SE8
PTB0/
LLWU_P5
I2C0_SCL
TPM1_CH0
LCD_P0
F6
36
PTB1
LCD_P1/
ADC0_SE9
LCD_P1/
ADC0_SE9
PTB1
I2C0_SDA
TPM1_CH1
LCD_P1
E7
37
PTB2
LCD_P2/
ADC0_SE12
LCD_P2/
ADC0_SE12
PTB2
I2C0_SCL
TPM2_CH0
LCD_P2
E8
38
PTB3
LCD_P3/
ADC0_SE13
LCD_P3/
ADC0_SE13
PTB3
I2C0_SDA
TPM2_CH1
LCD_P3
E6
39
PTB16
LCD_P12
LCD_P12
PTB16
SPI1_MOSI
LPUART0_RX TPM_CLKIN0
28
NXP Semiconductors
LPTMR0_
ALT1
SPI1_MISO
LCD_P12
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
64
64
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT4
LPUART0_TX TPM_CLKIN1
ALT5
ALT6
40
PTB17
LCD_P13
LCD_P13
PTB17
D6
41
PTB18
LCD_P14
LCD_P14
PTB18
TPM2_CH0
LCD_P14
C7
42
PTB19
LCD_P15
LCD_P15
PTB19
TPM2_CH1
LCD_P15
D8
43
PTC0
LCD_P20/
ADC0_SE14
LCD_P20/
ADC0_SE14
PTC0
EXTRG_IN
C6
44
PTC1/
LLWU_P6/
RTC_CLKIN
LCD_P21/
ADC0_SE15
LCD_P21/
ADC0_SE15
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
TPM0_CH0
LCD_P21
B7
45
PTC2
LCD_P22/
ADC0_SE11
LCD_P22/
ADC0_SE11
PTC2
I2C1_SDA
TPM0_CH1
LCD_P22
C8
46
PTC3/
LLWU_P7
LCD_P23
LCD_P23
PTC3/
LLWU_P7
SPI1_SCK
LPUART1_RX TPM0_CH2
E3
47
VSS
VSS
VSS
E4
—
VDD
VDD
VDD
C5
48
VLL3
VLL3
VLL3
A6
49
VLL2
VLL2/
LCD_P4
VLL2/
LCD_P4
PTC20
LCD_P4
B5
50
VLL1
VLL1/
LCD_P5
VLL1/
LCD_P5
PTC21
LCD_P5
B4
51
VCAP2
VCAP2/
LCD_P6
VCAP2/
LCD_P6
PTC22
LCD_P6
A5
52
VCAP1
VCAP1/
LCD_P39
VCAP1/
LCD_P39
PTC23
LCD_P39
B8
53
PTC4/
LLWU_P8
LCD_P24
LCD_P24
PTC4/
LLWU_P8
SPI0_SS
LPUART1_TX TPM0_CH3
A8
54
PTC5/
LLWU_P9
LCD_P25
LCD_P25
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
A7
55
PTC6/
LLWU_P10
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6/
LLWU_P10
SPI0_MOSI
EXTRG_IN
SPI0_MISO
LCD_P26
B6
56
PTC7
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
SPI0_MISO
audioUSB_
SOF_OUT
SPI0_MOSI
LCD_P27
C3
57
PTD0
LCD_P40
LCD_P40
PTD0
SPI0_SS
TPM0_CH0
FXIO0_D0
LCD_P40
A4
58
PTD1
LCD_P41/
ADC0_SE5b
LCD_P41/
ADC0_SE5b
PTD1
SPI0_SCK
TPM0_CH1
FXIO0_D1
LCD_P41
C2
59
PTD2
LCD_P42
LCD_P42
PTD2
SPI0_MOSI
UART2_RX
TPM0_CH2
SPI0_MISO
FXIO0_D2
LCD_P42
B3
60
PTD3
LCD_P43
LCD_P43
PTD3
SPI0_MISO
UART2_TX
TPM0_CH3
SPI0_MOSI
FXIO0_D3
LCD_P43
A3
61
PTD4/
LLWU_P14
LCD_P44
LCD_P44
PTD4/
LLWU_P14
SPI1_SS
UART2_RX
TPM0_CH4
FXIO0_D4
LCD_P44
C1
62
PTD5
LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5
SPI1_SCK
UART2_TX
TPM0_CH5
FXIO0_D5
LCD_P45
B2
63
PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
SPI1_MOSI
LPUART0_RX
SPI1_MISO
FXIO0_D6
LCD_P46
A2
64
PTD7
LCD_P47
LCD_P47
PTD7
SPI1_MISO
LPUART0_TX
SPI1_MOSI
FXIO0_D7
LCD_P47
audioUSB_
SOF_OUT
SPI1_MOSI
ALT7
D7
K32 L2B Microcontroller, Rev. 3, 09/2020
SPI1_MISO
ALT3
LCD_P13
CMP0_OUT
LCD_P20
CLKOUT
LCD_P23
LCD_P24
CMP0_OUT
LCD_P25
29
NXP Semiconductors
Pinouts
4.2 K32 L2B Signal Multiplexing and Pin Assignments (QFN)
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
When FTFA_FOPT[RESET_PIN_CONFIG]=0, the PTA20
pin acts as RESET_B function only during the POR. After
POR, this pin cannot be used as the RESET function. Then,
writing to PORTA_PCR20[MUX]=0x1, the PTA20 pin will
act as GPIO function (with setting value of ALT1). When
FTFA_FOPT[RESET_PIN_CONFIG]=1, the PTA20 pin acts
as RESET_B and cannot switch to GPIO function regardless
of PORTA_PCR20[MUX]'s setting value.
32
QFN
48
QFN
Pin Name
Default
ALT0
—
1
VDD
VDD
VDD
—
7
PTE20
ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
PTE20
TPM1_CH0
LPUART0_TX
FXIO0_D4
—
8
PTE21
ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
PTE21
TPM1_CH1
LPUART0_RX
FXIO0_D5
—
10
VREFH
VREFH
VREFH
—
11
VREFL
VREFL
VREFL
—
13
PTE29
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
TPM0_CH2
TPM_CLKIN0
—
15
PTE24
DISABLED
PTE24
TPM0_CH0
I2C0_SCL
—
16
PTE25
DISABLED
PTE25
TPM0_CH1
I2C0_SDA
—
29
PTB2
ADC0_SE12
ADC0_SE12
PTB2
I2C0_SCL
TPM2_CH0
—
30
PTB3
ADC0_SE13
ADC0_SE13
PTB3
I2C0_SDA
TPM2_CH1
—
31
PTB16
DISABLED
PTB16
SPI1_MOSI
LPUART0_RX TPM_CLKIN0
SPI1_MISO
—
32
PTB17
DISABLED
PTB17
SPI1_MISO
LPUART0_TX
TPM_CLKIN1
SPI1_MOSI
—
33
PTC0
ADC0_SE14
EXTRG_IN
audioUSB_
SOF_OUT
CMP0_OUT
—
41
PTD0
DISABLED
—
42
PTD1
ADC0_SE5b
—
43
PTD2
—
44
1
2
ADC0_SE14
ALT1
ALT2
PTC0
ALT3
ALT4
ALT5
ALT6
PTD0
SPI0_SS
TPM0_CH0
FXIO0_D0
PTD1
SPI0_SCK
TPM0_CH1
FXIO0_D1
DISABLED
PTD2
SPI0_MOSI
UART2_RX
TPM0_CH2
SPI0_MISO
FXIO0_D2
PTD3
DISABLED
PTD3
SPI0_MISO
UART2_TX
TPM0_CH3
SPI0_MOSI
FXIO0_D3
—
PTE0
DISABLED
PTE0/
CLKOUT32K
SPI1_MISO
LPUART1_TX
RTC_CLKOUT CMP0_OUT
I2C1_SDA
2
VSS
VSS
30
NXP Semiconductors
ADC0_SE5b
ALT7
VSS
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
32
QFN
48
QFN
Pin Name
Default
ALT0
3
3
USB0_DP
USB0_DP
USB0_DP
4
4
USB0_DM
USB0_DM
USB0_DM
5
5
VOUT33
VOUT33
VOUT33
6
6
VREGIN
VREGIN
VREGIN
7
9
VDDA
VDDA
VDDA
8
12
VSSA
VSSA
VSSA
9
14
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
10
17
PTA0
11
18
12
ALT1
ALT2
ALT3
ALT4
ALT5
TPM_CLKIN1
LPUART1_TX
ALT6
ALT7
PTE30
TPM0_CH3
SWD_CLK
PTA0
TPM0_CH5
PTA1
DISABLED
PTA1
LPUART0_RX TPM2_CH0
19
PTA2
DISABLED
PTA2
LPUART0_TX
TPM2_CH1
13
20
PTA3
SWD_DIO
PTA3
I2C1_SCL
TPM0_CH0
SWD_DIO
14
21
PTA4
NMI_b
PTA4
I2C1_SDA
TPM0_CH1
NMI_b
15
22
VDD
VDD
VDD
16
23
VSS
VSS
VSS
17
24
PTA18
EXTAL0
EXTAL0
PTA18
LPUART1_RX TPM_CLKIN0
18
25
PTA19
XTAL0
XTAL0
PTA19
LPUART1_TX
19
26
PTA20
RESET_b
20
27
PTB0/
LLWU_P5
ADC0_SE8
ADC0_SE8
PTB0/
LLWU_P5
I2C0_SCL
TPM1_CH0
21
28
PTB1
ADC0_SE9
ADC0_SE9
PTB1
I2C0_SDA
TPM1_CH1
22
34
PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_SE15
ADC0_SE15
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
TPM0_CH0
23
35
PTC2
ADC0_SE11
ADC0_SE11
PTC2
I2C1_SDA
TPM0_CH1
24
36
PTC3/
LLWU_P7
DISABLED
PTC3/
LLWU_P7
SPI1_SCK
LPUART1_RX TPM0_CH2
25
37
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_SS
LPUART1_TX
26
38
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
27
39
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_MOSI
EXTRG_IN
SPI0_MISO
28
40
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_MISO
audioUSB_
SOF_OUT
SPI0_MOSI
29
45
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI1_SS
UART2_RX
TPM0_CH4
FXIO0_D4
30
46
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI1_SCK
UART2_TX
TPM0_CH5
FXIO0_D5
31
47
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI1_MOSI
LPUART0_RX
SPI1_MISO
FXIO0_D6
32
48
PTD7
DISABLED
PTD7
SPI1_MISO
LPUART0_TX
SPI1_MOSI
FXIO0_D7
K32 L2B Microcontroller, Rev. 3, 09/2020
LPTMR0_
ALT1
SWD_CLK
TPM_CLKIN1
LPTMR0_
ALT1
CLKOUT
TPM0_CH3
CMP0_OUT
31
NXP Semiconductors
Pinouts
4.3 Pin properties
Pin interrupt
Open drain
Passive pin filter after POR
Slew rate after POR
Pullup/ pulldown setting after POR
Default status after POR
Driver strength
Pin name
64 LQFP
64 MAPBGA
The following table lists the pin properties of 64 LQFP/MAPBGA package.
1
A1
PTE0
ND
Hi-Z
—
SS
N
N
N
2
B1
PTE1
ND
Hi-Z
—
SS
N
N
N
3
—
VDD
—
—
—
—
—
—
—
4
C4
VSS
—
—
—
—
—
—
—
5
E1
USB0_DP
—
—
—
—
—
—
—
6
D1
USB0_DM
—
—
—
—
—
—
—
7
E2
VOUT33
—
—
—
—
—
—
—
8
D2
VREGIN
—
—
—
—
—
—
—
9
G1
PTE20
ND
Hi-Z
—
SS
N
N
N
10
F1
PTE21
ND
Hi-Z
—
SS
N
N
N
11
G2
PTE22
ND
Hi-Z
—
SS
N
N
N
12
F2
PTE23
ND
Hi-Z
—
SS
N
N
N
13
F4
VDDA
—
—
—
—
—
—
—
14
G4
VREFH
—
—
—
—
—
—
—
15
G3
VREFL
—
—
—
—
—
—
—
16
F3
VSSA
—
—
—
—
—
—
—
17
H1
PTE29
ND
Hi-Z
—
SS
N
N
N
18
H2
PTE30
ND
Hi-Z
—
SS
N
N
N
19
H3
PTE31
ND
Hi-Z
—
SS
N
N
N
20
H4
PTE24
ND
Hi-Z
—
SS
N
N
N
21
H5
PTE25
ND
Hi-Z
—
SS
N
N
N
22
D3
PTA0
ND
L
PD
SS
N
N
Y
23
D4
PTA1
ND
Hi-Z
—
SS
N
N
Y
24
E5
PTA2
ND
Hi-Z
—
SS
N
N
Y
Table continues on the next page...
32
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pin interrupt
Open drain
Passive pin filter after POR
Slew rate after POR
Pullup/ pulldown setting after POR
Default status after POR
Driver strength
Pin name
64 LQFP
64 MAPBGA
Pinouts
25
D5
PTA3
ND
H
PU
FS
N
N
Y
26
G5
PTA4
ND
H
PU
SS
N
N
Y
27
F5
PTA5
ND
Hi-Z
—
SS
N
N
Y
28
H6
PTA12
ND
Hi-Z
—
SS
N
N
Y
29
G6
PTA13
ND
Hi-Z
—
SS
N
N
Y
30
G7
VDD
—
—
—
—
—
—
—
31
H7
VSS
—
—
—
—
—
—
—
32
H8
PTA18
ND
Hi-Z
—
SS
N
N
Y
33
G8
PTA19
ND
Hi-Z
—
SS
N
N
Y
34
F8
PTA20
ND
H
PU
SS
Y
Y
Y
35
F7
PTB0/LLWU_P5
HD
Hi-Z
—
SS
N
N
N
36
F6
PTB1
HD
Hi-Z
—
SS
N
N
N
37
E7
PTB2
ND
Hi-Z
—
SS
N
N
N
38
E8
PTB3
ND
Hi-Z
—
SS
N
N
N
39
E6
PTB16
ND
Hi-Z
—
FS
N
N
N
40
D7
PTB17
ND
Hi-Z
—
FS
N
N
N
41
D6
PTB18
ND
Hi-Z
—
SS
N
N
N
42
C7
PTB19
ND
Hi-Z
—
SS
N
N
N
43
D8
PTC0
ND
Hi-Z
—
SS
N
N
Y
44
C6
PTC1/LLWU_P6/
RTC_CLKIN
ND
Hi-Z
—
SS
N
N
Y
45
B7
PTC2
ND
Hi-Z
—
SS
N
N
Y
46
C8
PTC3/LLWU_P7
HD
Hi-Z
—
FS
N
N
Y
47
E3
VSS
—
—
—
—
—
—
—
—
E4
VDD
—
—
—
—
—
—
—
48
C5
VLL3
—
—
—
—
—
—
—
49
A6
VLL2
—
—
—
—
—
—
—
50
B5
VLL1
—
—
—
—
—
—
—
51
B4
VCAP2
—
—
—
—
—
—
—
Table continues on the next page...
K32 L2B Microcontroller, Rev. 3, 09/2020
33
NXP Semiconductors
Pin interrupt
Open drain
Passive pin filter after POR
Slew rate after POR
Pullup/ pulldown setting after POR
Default status after POR
Driver strength
Pin name
64 LQFP
64 MAPBGA
Pinouts
52
A5
VCAP1
—
—
—
—
—
—
—
53
B8
PTC4/LLWU_P8
HD
Hi-Z
—
FS
N
N
Y
54
A8
PTC5/LLWU_P9
ND
Hi-Z
—
FS
N
N
Y
55
A7
PTC6/LLWU_P10
ND
Hi-Z
—
FS
N
N
Y
56
B6
PTC7
ND
Hi-Z
—
FS
N
N
Y
57
C3
PTD0
ND
Hi-Z
—
SS
N
N
Y
58
A4
PTD1
ND
Hi-Z
—
SS
N
N
Y
59
C2
PTD2
ND
Hi-Z
—
SS
N
N
Y
60
B3
PTD3
ND
Hi-Z
—
SS
N
N
Y
61
A3
PTD4/LLWU_P14
ND
Hi-Z
—
FS
N
N
Y
62
C1
PTD5
ND
Hi-Z
—
FS
N
N
Y
63
B2
PTD6/LLWU_P15
HD
Hi-Z
—
FS
N
N
Y
64
A2
PTD7
HD
Hi-Z
—
FS
N
N
Y
—
1
VDD
—
—
—
—
Pin interrupt
Open drain
Passive pin filter after POR
Slew rate after POR
Pullup/ pulldown setting after POR
Default status after POR
Driver strength
Pin name
48 QFN
32 QFN
The following table lists the pin properties of 32/48 QFN package.
—
—
—
Table continues on the next page...
34
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pin interrupt
Open drain
Passive pin filter after POR
Slew rate after POR
Pullup/ pulldown setting after POR
Default status after POR
Driver strength
Pin name
48 QFN
32 QFN
Pinouts
—
7
PTE20
ND
Hi-Z
—
SS
N
N
N
—
8
PTE21
ND
Hi-Z
—
SS
N
N
N
—
10
VREFH
—
—
—
—
—
—
—
—
11
VREFL
—
—
—
—
—
—
—
—
13
PTE29
ND
Hi-Z
—
SS
N
N
N
—
15
PTE24
ND
Hi-Z
—
SS
N
N
N
—
16
PTE25
ND
Hi-Z
—
SS
N
N
N
—
29
PTB2
ND
Hi-Z
—
SS
N
N
N
—
30
PTB3
ND
Hi-Z
—
SS
N
N
S
—
31
PTB16
ND
Hi-Z
—
FS
N
N
N
—
32
PTB17
ND
Hi-Z
—
FS
N
N
N
—
33
PTC0
ND
Hi-Z
—
SS
N
N
Y
—
41
PTD0
ND
Hi-Z
—
SS
N
N
Y
—
42
PTD1
ND
Hi-Z
—
SS
N
N
Y
—
43
PTD2
ND
Hi-Z
—
SS
N
N
Y
—
44
PTD3
ND
Hi-Z
—
SS
N
N
Y
1
—
PTE0
ND
Hi-Z
—
SS
N
N
N
2
2
VSS
—
—
—
—
—
—
—
3
3
USB0_DP
—
—
—
—
—
—
—
4
4
USB0_DM
—
—
—
—
—
—
—
5
5
VOUT33
—
—
—
—
—
—
—
6
6
VREGIN
—
—
—
—
—
—
—
7
9
VDDA
—
—
—
—
—
—
—
8
12
VSSA
—
—
—
—
—
—
—
9
14
PTE30
ND
Hi-Z
—
SS
N
N
N
10
17
PTA0
ND
L
PD
SS
N
N
Y
11
18
PTA1
ND
Hi-Z
—
SS
N
N
Y
12
19
PTA2
ND
Hi-Z
—
SS
N
N
Y
13
20
PTA3
ND
H
PU
FS
N
N
Y
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K32 L2B Microcontroller, Rev. 3, 09/2020
35
NXP Semiconductors
Pin interrupt
Open drain
Passive pin filter after POR
Slew rate after POR
Pullup/ pulldown setting after POR
Default status after POR
Driver strength
Pin name
48 QFN
32 QFN
Pinouts
14
21
PTA4
ND
H
PU
SS
N
N
Y
15
22
VDD
—
—
—
—
—
—
—
16
23
VSS
—
—
—
—
—
—
—
17
24
PTA18
ND
Hi-Z
—
SS
N
N
Y
18
25
PTA19
ND
Hi-Z
—
SS
N
N
Y
19
26
PTA20
ND
H
PU
SS
Y
Y
Y
20
27
PTB0/LLWU_P5
HD
Hi-Z
—
SS
N
N
N
21
28
PTB1
HD
Hi-Z
—
SS
N
N
N
22
34
PTC1/LLWU_P6/
RTC_CLKIN
ND
Hi-Z
—
SS
N
N
Y
23
35
PTC2
ND
Hi-Z
—
SS
N
N
Y
24
36
PTC3/LLWU_P7
HD
Hi-Z
—
FS
N
N
Y
25
37
PTC4/LLWU_P8
HD
Hi-Z
—
FS
N
N
Y
26
38
PTC5/LLWU_P9
ND
Hi-Z
—
FS
N
N
Y
27
39
PTC6/LLWU_P10
ND
Hi-Z
—
FS
N
N
Y
28
40
PTC7
ND
Hi-Z
—
FS
N
N
Y
29
45
PTD4/LLWU_P14
ND
Hi-Z
—
FS
N
N
Y
30
46
PTD5
ND
Hi-Z
—
FS
N
N
Y
31
47
PTD6/LLWU_P15
HD
Hi-Z
—
FS
N
N
Y
32
48
PTD7
HD
Hi-Z
—
FS
N
N
Y
Abbreviation
Descriptions
Properties
Driver strength
Default status after POR
Pullup/ pulldown setting
after POR
ND
Normal drive
HD
High drive
Hi-Z
High impendence
H
High level
L
Low level
PD
Pulldown
PU
Pullup
Table continues on the next page...
36
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
Properties
Abbreviation
Descriptions
FS
Fast slew rate
SS
Slow slew rate
Slew rate after POR
Passive Pin Filter after
POR
N
Disabled
Y
Enabled
Open drain
N
Disabled1
Y
Enabled2
Y
Yes
Pin interrupt
1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or
LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain
configurable.
2. PTA20 is a true open drain pin that must never be pulled above VDD.
4.4 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the module's chapter. They also briefly describe the signal function and direction.
4.4.1 Core modules
Table 9. SWD signal descriptions
Chip signal name
Module signal
name
SWD_DIO
SWD_DIO
Description
I/O
Serial Wire Debug Data Input/Output
The SWD_DIO pin is used by an external debug tool for
communication and device control. This pin is pulled up
internally.
SWD_CLK
SWD_CLK
Serial Wire Clock
Input /
Output
Input
This pin is the clock for debug logic when in the Serial Wire
Debug mode. This pin is pulled down internally.
4.4.2 System modules
Table 10. System signal descriptions
Chip signal name
Module signal
name
NMI
—
Description
Non-maskable interrupt
I/O
I
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37
NXP Semiconductors
Pinouts
Table 10. System signal descriptions (continued)
Chip signal name
Module signal
name
Description
I/O
NOTE: Driving the NMI signal low forces a non-maskable
interrupt, if the NMI function is selected on the
corresponding pin.
RESET
—
Reset bidirectional signal
VDD
—
MCU power
I/O
I
VSS
—
MCU ground
I
Table 11. LLWU signal descriptions
Chip signal name
Module signal
name
LLWU_Pn
LLWU_Pn
Description
I/O
Wakeup inputs
I
4.4.3 Clock modules
Table 12. OSC signal descriptions
Chip signal name
Module signal
name
EXTAL0
EXTAL
XTAL0
XTAL
Description
I/O
External clock/Oscillator input
I
Oscillator output
O
4.4.4 Analog
This table presents the signal descriptions of the ADC0 module.
Table 13. ADC0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
ADC0_DPn
DADP3–DADP0
Differential Analog Channel Inputs
I
ADC0_DMn
DADM3–DADM0
Differential Analog Channel Inputs
I
ADC0_SEn
ADn
Single-Ended Analog Channel Inputs
I
VREFH
VREFSH
Voltage Reference Select High
I
VREFL
VREFSL
Voltage Reference Select Low
I
VDDA
VDDA
Analog Power Supply
I
VSSA
VSSA
Analog Ground
I
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38
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
Table 13. ADC0 signal descriptions (continued)
Chip signal name
Module signal
name
EXTRG_IN
ADHWT
Description
I/O
Hardware trigger
I
This table presents the signal descriptions of the CMP0 module.
Table 14. CMP0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
CMP0_IN[5:0]
IN[5:0]
Analog voltage inputs
I
CMP0_OUT
CMPO
Comparator output
O
Table 15. VREF signal descriptions
Chip signal name
Module signal
name
Description
I/O
VREF_OUT
VREF_OUT
Internally-generated voltage reference output
O
4.4.5 Timer Modules
Table 16. TPM0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
TPM0_CH[5:0]
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
EXTRG_IN
ADHWT
Hardware trigger
I
Table 17. TPM1 signal descriptions
Chip signal name
Module signal
name
Description
I/O
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
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39
NXP Semiconductors
Pinouts
Table 17. TPM1 signal descriptions (continued)
Chip signal name
Module signal
name
TPM1_CH[1:0]
TPM_CHn
EXTRG_IN
ADHWT
Description
I/O
TPM channel (n = 1 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
Hardware trigger
I
Table 18. TPM2 signal descriptions
Chip signal name
Module signal
name
Description
I/O
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
TPM2_CH[1:0]
TPM_CHn
TPM channel (n = 1 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
EXTRG_IN
ADHWT
Hardware trigger
I
Table 19. LPTMR0 signal descriptions
Chip signal name
Module signal
name
Description
LPTMR0_ALT[3:1]
LPTMR0_ALTn
Pulse Counter Input pin
I/O
I
Table 20. RTC signal descriptions
Chip signal name
Module signal
name
Description
I/O
RTC_CLKOUT1
RTC_CLKOUT
1 Hz square-wave output or OSCERCLK
O
1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL]
4.4.6 Communication interfaces
Table 21. USB FS Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
USB0_DM
usb_dm
USB D- analog data signal on the USB bus.
I/O
USB0_DP
usb_dp
USB D+ analog data signal on the USB bus.
I/O
USB_CLKIN
—
40
NXP Semiconductors
Alternate USB clock input
I
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
Table 22. SPI0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
SPI0_MISO
MISO
Master Data In, Slave Data Out
I/O
Master Data Out, Slave Data In
I/O
SPI Serial Clock
I/O
Slave Select
I/O
SPI0_MOSI
MOSI
SPI0_SCLK
SPSCK
SPI0_PCS0
SS
Table 23. SPI1 signal descriptions
Chip signal name
Module signal
name
Description
I/O
SPI1_MISO
MISO
Master Data In, Slave Data Out
I/O
Master Data Out, Slave Data In
I/O
SPI Serial Clock
I/O
Slave Select
I/O
SPI1_MOSI
MOSI
SPI1_SCLK
SPSCK
SPI1_PCS0
SS
Table 24. I2C0 signal descriptions
Chip signal name
Module signal
name
I2C0_SCL
SCL
I2C0_SDA
Description
I/O
Bidirectional serial clock line of the I2C system.
SDA
Bidirectional serial data line of the
I2C
system.
I/O
I/O
Table 25. I2C1 signal descriptions
Chip signal name
Module signal
name
I2C1_SCL
SCL
I2C1_SDA
SDA
Description
I/O
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the
I2C
system.
I/O
I/O
Table 26. LPUART0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
LPUART0_TX
TxD
Transmit data
I/O
LPUART0_RX
RxD
Receive data
I
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41
NXP Semiconductors
Pinouts
Table 27. LPUART1 signal descriptions
Chip signal name
Module signal
name
Description
I/O
LPUART1_TX
TxD
Transmit data
I/O
LPUART1_RX
RxD
Receive data
I
Table 28. UART2 signal descriptions
Chip signal name
Module signal
name
Description
I/O
UART2_TX
TxD
Transmit data
O
UART2_RX
RxD
Receive data
I
Table 29. FlexIO signal descriptions
Chip signal name
Module signal name
Description
I/O
FXIO0_Dx
FXIO_Dn (n=0...7)
Bidirectional FlexIO Shifter
and Timer pin inputs/outputs
I/O
EXTRG_IN
ADHWT
Hardware trigger
I
4.4.7 Human-machine interfaces (HMI)
Table 30. GPIO Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
PTA[20:0]
PORTA20–PORTA0 General-purpose input/output
I/O
PTB[19:0]
PORTB19–PORTB0 General-purpose input/output
I/O
PTD[7:0]
PORTD7–PORTD0 General-purpose input/output
I/O
PTE[31:0]
PORTE31–PORTE0 General-purpose input/output
I/O
Table 31. LCD Signal Descriptions
Chip signal name
LCD_Pn
VLL1, VLL2, VLL3
Module signal
name
Description
I/O
LCD_P[63:0] . 64 Configurable front plane/back plane driver that connects directly to
LCD front plane/back the display. LCD_P[63:0] can operate as GPIO pins
plane
O
VLL1, VLL2, VLL3. LCD LCD bias voltages (requires external capacitors when charge
bias voltages
pump is used).
I/O
Table continues on the next page...
42
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
Table 31. LCD Signal Descriptions (continued)
Chip signal name
Module signal
name
Vcap1, Vcap2
Vcap1, Vcap2. LCD
charge pump
capacitance.
Description
I/O
Charge pump capacitor pins.
O
4.5 K32 L2B LQFP and MAPBGA pinouts
Figure below shows the 64 LQFP pinouts
K32 L2B Microcontroller, Rev. 3, 09/2020
43
NXP Semiconductors
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VCAP1
VCAP2
VLL1
VLL2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pinouts
PTE20
9
40
PTB17
PTE21
10
39
PTB16
PTE22
11
38
PTB3
PTE23
12
37
PTB2
VDDA
13
36
PTB1
VREFH
14
35
PTB0/LLWU_P5
VREFL
15
34
PTA20
VSSA
16
33
PTA19
32
PTB18
PTA18
41
31
8
VSS
VREGIN
30
PTB19
VDD
42
29
7
PTA13
VOUT33
28
PTC0
PTA12
43
27
6
PTA5
USB0_DM
26
PTC1/LLWU_P6/RTC_CLKIN
PTA4
44
25
5
PTA3
USB0_DP
24
PTC2
PTA2
45
23
4
PTA1
VSS
22
PTC3/LLWU_P7
PTA0
46
21
3
PTE25
VDD
20
VSS
PTE24
47
19
2
PTE31
PTE1
18
VLL3
PTE30
48
17
1
PTE29
PTE0
Figure 5. 64 LQFP Pinout diagram
Figure below shows the 64 MAPBGA pinouts
44
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
1
2
3
4
5
6
A
PTE0
PTD7
PTD4/
LLWU_P14
PTD1
VCAP1
VLL2
B
PTE1
PTD6/
LLWU_P15
PTD3
VCAP2
VLL1
PTC7
C
PTD5
PTD2
PTD0
VSS
VLL3
D
USB0_DM
VREGIN
PTA0
PTA1
E
USB0_DP
VOUT33
VSS
F
PTE21
PTE23
G
PTE20
H
7
8
PTC6/
PTC5/
LLWU_P10 LLWU_P9
A
PTC2
PTC4/
LLWU_P8
B
PTC1/
LLWU_P6/
RTC_CLKIN
PTB19
PTC3/
LLWU_P7
C
PTA3
PTB18
PTB17
PTC0
D
VDD
PTA2
PTB16
PTB2
PTB3
E
VSSA
VDDA
PTA5
PTB1
PTB0/
LLWU_P5
PTA20
F
PTE22
VREFL
VREFH
PTA4
PTA13
VDD
PTA19
G
PTE29
PTE30
PTE31
PTE24
PTE25
PTA12
VSS
PTA18
H
1
2
3
4
5
6
7
8
Figure 6. 64 MAPBGA Pinout diagram
4.6 K32 L2B QFN Pinouts
The figure below shows the 32 QFN pinouts.
K32 L2B Microcontroller, Rev. 3, 09/2020
45
NXP Semiconductors
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
32
31
30
29
28
27
26
25
Pinouts
21
PTB1
VOUT33
5
20
PTB0/LLWU_P5
VREGIN
6
19
PTA20
VDDA
7
18
PTA19
VSSA
8
17
PTA18
PTA0
PTE30
16
4
VSS
USB0_DM
15
PTC1/LLWU_P6/RTC_CLKIN
VDD
22
14
3
PTA4
USB0_DP
13
PTC2
PTA3
23
12
2
PTA2
VSS
11
PTC3/LLWU_P7
PTA1
24
10
1
9
PTE0
Figure 7. 32 QFN Pinout diagram (transparent top view)
The figure below shows the 48 QFN pinouts.
46
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
48
47
46
45
44
43
42
41
40
39
38
37
Pinouts
VDD
1
36
PTC3/LLWU_P7
VSS
2
35
PTC2
USB0_DP
3
34
PTC1/LLWU_P6/RTC_CLKIN
USB0_DM
4
33
PTC0
VOUT33
5
32
PTB17
VREGIN
6
31
PTB16
PTE20
7
30
PTB3
PTE21
8
29
PTB2
VDDA
18
19
20
21
22
23
24
PTA2
PTA3
PTA4
VDD
VSS
PTA18
PTA19
PTA1
25
17
12
PTA0
VSSA
16
PTA20
PTE25
26
15
PTB0/LLWU_P5
PTE24
27
11
14
10
VREFL
PTE30
PTB1
13
28
PTE29
9
VREFH
Figure 8. 48 QFN Pinout diagram (transparent top view)
4.7 Package dimensions
The following figures show the dimensions of the package options for the devices
supported by this document.
K32 L2B Microcontroller, Rev. 3, 09/2020
47
NXP Semiconductors
Pinouts
Figure 9. 64-pin LQFP package dimensions 1
48
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
8
(0.22)
B
BASE METAL
B
0.20
0.09
0.16
0.09
8
60X
0.5
0.23
0.17
0.25
X X=A, B OR D
8
PLATING
8
SECTION B-B
DETAIL Y
(0.2)
0° MIN
1.45
1.35
0.05
2X R0.2
0.1
0.25
GAUGE
PLANE
0.15
0.05
(1.00)
(0.5)
0.75
0.45
7°
0°
DETAIL AA
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. DATUMS A, B AND D TO BE DETERMINDE AT DATUM PLANE H.
4. DIMENSIONS TO BE DETERMINED AT SEATING PLANE C.
5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE UPPER LIMIT
BY MORE THAN 0.08 MM AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM.
6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25 MM PER SIDE. THIS DIMENSION IS MAXIMUM PLASTIC BODY SIZE
DIMENSION INCLUDING MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.1 MM AND 0.25 MM FROM THE LEAD TIP.
Figure 10. 64-pin LQFP package dimensions 2
K32 L2B Microcontroller, Rev. 3, 09/2020
49
NXP Semiconductors
Pinouts
5
A1 INDEX AREA
B
64X
C
0.08 A
D
5
A
// 0.2 A
SEATING
PLANE 4
5
0.15
4X
TOP VIEW
D
0.25
7X 0.5
H
G
F
E
D
C
B
A
7X 0.5
0.25
1
2
3
4
5
6
7
8
64X
0.25
0.15
Ø 0.35
0.25 3
Ø0.15 M A B C
Ø0.05 M A
1.23 MAX
A1 INDEX AREA
BOTTOM VIEW
VIEW D-D
NOTES:
1. ALL DIMENSIONS IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE
SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE
OF PACKAGE.
Figure 11. 64-pin MAPBGA package dimension
50
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
Figure 12. 48-pin QFN package dimension 1
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51
NXP Semiconductors
Pinouts
45°
0.25
(0.05)
0.95
1.13
DETAIL F
// 0.1 C
48X
0.65
0.50
0.08 C
0.05
0.00
(0.2)
4
C
SEATING PLANE
(0.5)
DETAIL G
VIEW ROTATED 90℃W
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. THIS IS A NON-JEDEC REGISTERED PACKAGE.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG.
5. MIN. METAL GAP SHOULD BE 0.2 MM.
Figure 13. 48-pin QFN package dimension 2
52
NXP Semiconductors
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Pinouts
Figure 14. 32-pin QFN package dimension 1
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53
NXP Semiconductors
Electrical characteristics
// 0.1 C
32X
0.65
0.50
0.05
0.00
0.08 C
(0.2)
C
SEATING PLANE
(0.5)
DETAIL G
VIEW ROTATED 90℃W
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. THIS IS A NON-JEDEC REGISTERED PACKAGE.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG.
5. MIN. METAL GAP SHOULD BE 0.2 MM.
Figure 15. 32-pin QFN package dimension 2
5 Electrical characteristics
5.1 Ratings
54
NXP Semiconductors
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Electrical characteristics
5.1.1 Thermal handling ratings
Table 32. Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.1.2 Moisture handling ratings
Table 33. Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.1.3 ESD handling ratings
Table 34. ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
–2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
–500
+500
V
2
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.1.4 Voltage and current operating ratings
Table 35. Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
Table continues on the next page...
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Electrical characteristics
Table 35. Voltage and current operating ratings (continued)
Symbol
VIO
ID
Description
Min.
Max.
Unit
IO pin input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
VREGIN
5.2 General
5.2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
Low
High
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 16. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
5.2.2 Nonswitching electrical specifications
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Electrical characteristics
5.2.2.1
Voltage and current operating requirements
Table 36. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-3
—
mA
-25
—
mA
VIH
VIL
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
IO pin negative DC injection current — single pin
1
• VIN < VSS-0.3V
IICcont
Notes
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
2
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
5.2.2.2
Symbol
LVD and POR operating requirements
Table 37. VDD supply LVD and POR operating requirements
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
VLVW1H
• Level 1 falling (LVWV = 00)
VLVW2H
• Level 2 falling (LVWV = 01)
VLVW3H
Notes
1
2.62
2.70
2.78
V
2.72
2.80
2.88
V
2.82
2.90
2.98
V
Table continues on the next page...
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Electrical characteristics
Table 37. VDD supply LVD and POR operating requirements (continued)
Symbol
VLVW4H
Description
• Level 3 falling (LVWV = 10)
Min.
Typ.
Max.
Unit
2.92
3.00
3.08
V
—
±60
—
mV
1.54
1.60
1.66
V
Notes
• Level 4 falling (LVWV = 11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
VLVW1L
• Level 1 falling (LVWV = 00)
VLVW2L
• Level 2 falling (LVWV = 01)
VLVW3L
• Level 3 falling (LVWV = 10)
VLVW4L
• Level 4 falling (LVWV = 11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
1
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±40
—
mV
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low-power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
5.2.2.3
Symbol
VOH
VOH
Voltage and current operating behaviors
Table 38. Voltage and current operating behaviors
Description
Min.
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
—
V
Output high voltage — high drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
—
V
—
100
mA
—
0.5
V
—
0.5
V
VOL
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
Output low voltage — high drive pad
1
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
0.5
V
—
100
mA
Output low current total for all ports
Notes
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
Output high current total for all ports
IOLT
Unit
Output high voltage — normal drive pad
IOHT
VOL
Max.
Table continues on the next page...
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Electrical characteristics
Table 38. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
2
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
2
IIN
Input leakage current (total all pins) for full
temperature range
—
64
μA
2
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
3
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
5.2.2.4
Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 39. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
—
152
166
μs
—
152
166
μs
—
93
104
μs
—
7.5
8
μs
—
7.5
8
μs
—
7.5
8
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
K32 L2B Microcontroller, Rev. 3, 09/2020
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Electrical characteristics
5.2.2.5
Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
Table 40. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable, 24
MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 12
MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
2
—
5.76
6.40
—
6.04
6.68
—
3.21
3.85
—
3.49
4.13
mA
mA
2
—
6.45
7.09
—
6.75
7.39
mA
2
—
3.95
4.59
—
4.23
4.87
mA
2
—
2.68
3.32
—
2.96
3.60
mA
2
—
8.08
8.72
—
8.39
9.03
mA
Table continues on the next page...
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock disable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
3.90
4.54
mA
—
4.21
4.85
—
2.66
3.30
—
2.94
3.58
—
2.03
2.67
—
2.31
2.95
—
5.52
6.16
—
5.83
6.47
—
5.29
5.93
—
5.56
6.20
—
6.91
7.55
—
7.19
7.91
IDD_VLPRCO Very Low Power Run Core Mark in Flash in
Compute Operation mode: Core@4 MHz, Flash
@1 MHz, VDD = 3.0 V
• at 25 °C
—
826
907
μA
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode, 4
MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
405
486
μA
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode, 2
MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
154
235
μA
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock disable,
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock enable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
Notes
mA
mA
mA
mA
mA
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VLPR
Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_WAIT
IDD_WAIT
Min.
Typ.
Max.
Unit
—
108
189
μA
—
39
120
μA
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
249
330
μA
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
337
418
μA
—
416
497
μA
—
494
575
μA
—
166
247
μA
—
50
131
μA
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
208
289
μA
Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.81
1.89
mA
Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.22
1.39
mA
Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
Notes
Table continues on the next page...
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_VLPW Very-low-power wait mode current, core disabled,
4 MHz system/ 1 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
—
172
182
μA
IDD_VLPW Very-low-power wait mode current, core disabled,
2 MHz system/ 0.5 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
—
69
76
μA
IDD_VLPW Very-low-power wait mode current, core disabled,
125 kHz system/ 31.25 kHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
—
36
40
μA
—
1.81
2.06
mA
—
1.00
1.25
mA
—
161.93
171.82
—
181.45
191.96
—
236.29
271.17
—
390.33
465.58
—
3.31
5.14
—
10.43
17.68
—
34.14
61.06
—
104.38
164.44
—
3.21
5.22
—
10.26
17.62
—
33.49
60.19
—
102.92
162.20
—
2.06
3.33
—
4.72
6.85
—
8.13
13.30
—
13.34
24.70
—
41.08
52.43
—
2.46
3.73
Notes
IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12
MHz bus and flash, VDD = 3.0 V
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
IDD_STOP
Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 1.8 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current, all peripheral
disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current with RTC current,
at 3.0 V
μA
μA
μA
μA
μA
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
• at 25 °C and below
—
5.12
7.25
• at 50 °C
—
8.53
11.78
• at 70 °C
—
13.74
18.91
• at 85 °C
—
41.48
52.83
Unit
Notes
• at 105 °C
IDD_LLS
Low-leakage stop mode current with RTC current,
at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
3
—
2.35
2.70
—
4.91
6.75
—
8.32
11.78
—
13.44
18.21
—
40.47
51.85
—
1.45
1.85
—
3.37
4.39
—
5.76
8.48
—
9.72
14.30
—
30.41
37.50
μA
μA
3
—
2.05
2.45
—
3.97
4.99
—
6.36
9.08
—
10.32
14.73
—
31.01
38.10
μA
3
—
1.96
2.36
—
3.86
5.67
—
6.23
8.53
—
10.21
13.37
—
30.25
37.02
—
0.66
0.80
—
1.78
3.87
—
2.55
4.26
μA
μA
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
• at 85°C
—
4.83
6.64
• at 105 °C
—
16.42
20.49
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
• at 25 °C and below
—
1.26
1.40
—
2.38
4.47
—
3.15
4.86
—
5.43
7.24
—
17.02
21.09
1.30
—
1.96
2.28
—
2.78
3.37
—
4.85
6.88
—
15.78
18.81
—
0.35
0.47
• at 50 °C
—
1.25
1.44
• at 70 °C
—
2.53
3.24
• at 85 °C
—
4.40
5.24
• at 105 °C
—
16.09
19.29
—
0.18
0.28
• at 50 °C
—
1.09
1.31
• at 70 °C
—
2.25
2.94
• at 85 °C
—
4.25
5.10
• at 105 °C
—
15.95
19.10
• at 85°C
• at 105 °C
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
• at 25 °C and below
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
• at 25 °C and below
μA
3
1.16
• at 70°C
Notes
3
—
• at 50°C
Unit
μA
μA
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
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Electrical characteristics
Table 41. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIRC8MHz
8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
93
93
93
93
93
93
µA
IIRC2MHz
2 MHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
29
29
29
29
29
29
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
224
230
238
245
253
µA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
• VLLS1
440
490
540
560
570
580
440
490
540
560
570
580
490
490
540
560
570
680
510
560
560
560
610
680
510
560
560
560
610
680
30
30
30
85
100
200
• VLLS3
• LLS
• VLPS
• STOP
ILPTMR
nA
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
nA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare. Includes
6-bit DAC power consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
22
22
22
22
22
22
µA
114
114
114
114
114
114
µA
34
34
34
34
34
34
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Electrical characteristics
Table 41. Low power mode peripheral adders — typical value (continued)
Symbol
ITPM
Description
TPM peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source configured for
output compare generating 100 Hz clock
signal. No load is placed on the I/O
generating the clock signal. Includes
selected clock source and I/O switching
currents.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
Temperature (°C)
Unit
-40
25
50
70
85
105
147
147
147
147
147
147
42
42
42
42
42
42
µA
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx or VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
330
330
330
330
330
330
µA
ILCD
LCD peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by means
of the OSC0_CR[EREFSTEN,
EREFSTEN] bits. VIREG disabled, resistor
bias network enabled, 1/8 duty cycle, 8 x
36 configuration for driving 288 Segments,
32 Hz frame rate, no LCD glass
connected. Includes ERCLK32K (32 kHz
external crystal) power consumption.
4.5
4.5
4.5
4.5
4.5
4.5
µA
5.2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
USB regulator disabled
No GPIOs toggled
Code execution from flash
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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Electrical characteristics
Figure 17. Run mode supply current vs. core frequency
68
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Electrical characteristics
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NXP Semiconductors
Current
ionon
onVDD
VDD
(A)
CurrentC
Consumpt
onsumption
(A)
Electrical characteristics
Figure 18. VLPR mode current vs. core frequency
5.2.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following NXP applications notes, available on nxp.com for advice and
guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
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Electrical characteristics
• AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems
5.2.2.7
Symbol
CIN
Capacitance attributes
Table 42. Capacitance attributes
Description
Input capacitance
Min.
Max.
Unit
—
7
pF
Min.
Max.
Unit
5.2.3 Switching specifications
5.2.3.1
Symbol
Device clock specifications
Table 43. Device clock specifications
Description
Normal run mode
fSYS
System and core clock1
—
48
MHz
fBUS
Bus clock1
—
24
MHz
—
24
MHz
System and core clock when Full Speed USB in operation
20
—
MHz
LPTMR clock
—
24
MHz
fFLASH
fSYS_USB
fLPTMR
Flash
clock1
VLPR and VLPS
modes2
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
fFLASH
Flash clock
—
1
MHz
fLPTMR
LPTMR clock3
—
24
MHz
—
16
MHz
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
—
16
MHz
TPM asynchronous clock
—
8
MHz
LPUART0/1 asynchronous clock
—
8
MHz
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2
fTPM
fLPUART0/1
1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48 MHz is used as the clock source.
2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
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Electrical characteristics
5.2.3.2
General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 44. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
—
36
ns
3
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
5.2.4 Thermal specifications
5.2.4.1
Symbol
Thermal operating requirements
Table 45. Thermal operating requirements
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
5.2.4.2
Thermal attributes
Table 46. Thermal attributes
Board type
Symbol
Single-layer (1S)
RθJA
Four-layer (2s2p)
RθJA
Description
48 QFN
32 QFN
64
LQFP
64
MAPBG
A
Unit
Notes
Thermal resistance, junction
to ambient (natural
convection)
86
101
70
50.3
°C/W
1
Thermal resistance, junction
to ambient (natural
convection)
29
33
51
42.9
°C/W
Table continues on the next page...
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Electrical characteristics
Table 46. Thermal attributes (continued)
Board type
Symbol
Single-layer (1S)
RθJMA
Four-layer (2s2p)
Description
48 QFN
32 QFN
64
LQFP
64
MAPBG
A
Unit
Notes
Thermal resistance, junction
to ambient (200 ft./min. air
speed)
71
84
58
41.4
°C/W
RθJMA
Thermal resistance, junction
to ambient (200 ft./min. air
speed)
24
28
45
38.0
°C/W
—
RθJB
Thermal resistance, junction
to board
12
13
33
39.6
°C/W
2
—
RθJC
Thermal resistance, junction
to case
1.7
1.7
20
27.3
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
2
3
4
0.4
°C/W
4
—
ΨJB
Thermal characterization
parameter, junction to
package bottom (natural
convection)
-
-
-
12.6
°C/W
5
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
5.3 Peripheral operating requirements and behaviors
5.3.1 Core modules
5.3.1.1
Symbol
SWD electricals
Table 47. SWD full voltage range electricals
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
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Electrical characteristics
Table 47. SWD full voltage range electricals (continued)
Symbol
J1
Description
Min.
Max.
Unit
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 19. Serial wire clock input timing
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 20. Serial wire data timing
74
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Electrical characteristics
5.3.2 System modules
There are no specifications necessary for the device's system modules.
5.3.3 Clock modules
5.3.3.1
MCG-Lite specifications
Table 48. IRC48M specification
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD
Supply current
—
400
500
µA
—
fIRC
Output frequency
—
48
—
MHz
—
Δfirc48m_ol_lv
Open loop total deviation of IRC48M
frequency at low voltage
(VDD=1.71V-1.89V) over temperature
—
± 0.5
± 1.5
%firc48m
Δfirc48m_ol_hv
Open loop total deviation of IRC48M
frequency at high voltage
(VDD=1.89V-3.6V) over temperature
—
± 0.5
± 1.0
%firc48m
Tj
Period jitter (RMS)
—
35
150
ps
—
Tsu
Startup time
—
2
3
µs
—
1
1
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean +/-3sigma).
Table 49. IRC8M/2M specification
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_2M
Supply current in 2 MHz mode
—
14
17
µA
—
IDD_8M
Supply current in 8 MHz mode
—
30
35
µA
—
fIRC_2M
Output frequency
—
2
—
MHz
—
fIRC_8M
Output frequency
—
8
—
MHz
—
fIRC_T_2M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
fIRC_T_8M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
Tsu_2M
Startup time
—
—
12.5
µs
—
Tsu_8M
Startup time
—
—
12.5
µs
—
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Electrical characteristics
Figure 21. IRC8M Frequency Drift vs Temperature curve
5.3.3.2
5.3.3.2.1
Oscillator electrical specifications
Oscillator DC electrical specifications
Table 50. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
—
1.2
—
mA
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Electrical characteristics
Table 50. Oscillator DC electrical specifications (continued)
Symbol
Description
• 24 MHz
Min.
Typ.
Max.
Unit
—
1.5
—
mA
Notes
• 32 MHz
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
Cy
XTAL load capacitance
—
—
—
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
RS
2, 3
2, 3
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
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Electrical characteristics
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
5.3.3.2.2
Symbol
Oscillator frequency specifications
Table 51. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
5.3.4 Memories and memory interfaces
5.3.4.1
Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
78
NXP Semiconductors
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Electrical characteristics
5.3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 52. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
—
52
452
ms
1
Unit
Notes
thversblk128k Erase Block high-voltage time for 128 KB
1. Maximum time based on expectations at cycling end-of-life.
5.3.4.1.2
Symbol
Flash timing specifications — commands
Table 53. Flash command timing specifications
Description
Min.
Typ.
Max.
Read 1s Block execution time
trd1blk128k
1
• 128 KB program flash
—
—
1.7
ms
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
Erase Flash Block execution time
tersblk128k
• 128 KB program flash
2
—
88
600
ms
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
tpgmonce
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
175
1300
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tersallu
Erase All Blocks Unsecure execution time
—
175
1300
ms
2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.3.4.1.3
Flash high voltage current behaviors
Table 54. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
Average current adder during high voltage
flash programming operation
Min.
Typ.
Max.
Unit
—
2.5
6.0
mA
Table continues on the next page...
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Electrical characteristics
Table 54. Flash high voltage current behaviors (continued)
Symbol
Description
IDD_ERS
Average current adder during high voltage
flash erase operation
5.3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
—
1.5
4.0
mA
Reliability specifications
Table 55. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.3.6 Analog
5.3.6.1
ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
5.3.6.1.1
16-bit ADC operating conditions
Table 56. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
3
Table continues on the next page...
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Electrical characteristics
Table 56. 16-bit ADC operating conditions (continued)
Symbol
Description
VREFL
ADC reference
voltage low
VADIN
Input voltage
CADIN
RADIN
RAS
Input
capacitance
Min.
Typ.1
Max.
Unit
Notes
VSSA
VSSA
VSSA
V
3
• 16-bit differential mode
VREFL
—
31/32 ×
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
Conditions
Input series
resistance
VREFH
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
24
MHz
5
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
5
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
4
6
20.000
—
1200
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
6
37.037
—
461.467
ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH can act as VREF_OUT when VREFV1 module is enabled.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
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Electrical characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 22. ADC input impedance equivalency diagram
5.3.6.1.2
16-bit ADC electrical characteristics
Table 57. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
IDDA_ADC Supply current
ADC asynchronous
clock source
fADACK
Sample Time
TUE
DNL
INL
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• 3.6 V
3
3.3
3.6
V
2.1
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
• Run mode
• Standby mode
VReg33out
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
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5.5.3 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 66. SPI master mode timing on slew rate disabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x
tperiph
ns
—
Data setup time (inputs)
18
—
ns
—
tHI
Data hold time (inputs)
0
—
ns
—
8
tv
Data valid (after SPSCK edge)
—
15
ns
—
9
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 67. SPI master mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
tHI
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x
tperiph
ns
—
Data setup time (inputs)
96
—
ns
—
Data hold time (inputs)
0
—
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
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Electrical characteristics
Table 67. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol
8
tv
9
Description
Min.
Max.
Unit
Note
Data valid (after SPSCK edge)
—
52
ns
—
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
SS1
(OUTPUT)
3
2
SPSCK
(CPOL=0)
(OUTPUT)
11
10
11
6
7
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
4
5
SPSCK
(CPOL=1)
(OUTPUT)
MISO
(INPUT)
10
5
MSB OUT2
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 29. SPI master mode timing (CPHA = 0)
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Electrical characteristics
SS1
(OUTPUT)
2
3
SPSCK
(CPOL=0)
(OUTPUT)
5
SPSCK
(CPOL=1)
(OUTPUT)
5
6
MISO
(INPUT)
11
10
11
4
7
MSB IN2
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
10
PORT DATA MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 30. SPI master mode timing (CPHA = 1)
Table 68. SPI slave mode timing on slew rate disabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
Enable lead time
1
—
tperiph
—
Enable lag time
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2.5
—
ns
—
tHI
Data hold time (inputs)
3.5
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
31
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
13
1.
2.
3.
4.
38
Description
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
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Table 69. SPI slave mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
Enable lead time
4
tLag
Enable lag time
5
tWSPSCK
6
tSU
7
Frequency of operation
SPSCK period
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
1
—
tperiph
—
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2
—
ns
—
tHI
Data hold time (inputs)
7
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
122
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
13
1.
2.
3.
4.
Description
Clock (SPSCK) high or low time
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
SS
(INPUT)
2
12
13
12
13
4
SPSCK
(CPOL=0)
(INPUT)
5
3
SPSCK
(CPOL=1)
(INPUT)
5
9
8
MISO
(OUTPUT)
see
note
SLAVE MSB
6
MOSI
(INPUT)
10
11
11
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined
Figure 31. SPI slave mode timing (CPHA = 0)
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Electrical characteristics
SS
(INPUT)
4
2
3
SPSCK
(CPOL=0)
(INPUT)
5
SPSCK
(CPOL=1)
(INPUT)
5
see
note
SLAVE
8
MSB OUT
6
MOSI
(INPUT)
13
12
13
11
10
MISO
(OUTPUT)
12
9
BIT 6 . . . 1
SLAVE LSB OUT
BIT 6 . . . 1
LSB IN
7
MSB IN
NOTE: Not defined
Figure 32. SPI slave mode timing (CPHA = 1)
5.5.4 I2C
5.5.4.1
Inter-Integrated Circuit Interface (I2C) timing
Table 70. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
SCL Clock Frequency
fSCL
0
100
0
4001
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
tSU; DAT
2505
—
1003, 6
Data set-up time
Rise time of SDA and SCL signals
tr
—
1000
—
ns
7
300
ns
6
20 +0.1Cb
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
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Electrical characteristics
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high
drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
2
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
Table 71. I 2C 1Mbit/s timing
Characteristic
Symbol
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
fSCL
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
tLOW
0.5
—
HIGH period of the SCL clock
tHIGH
0.26
—
µs
Set-up time for a repeated START condition
tSU; STA
0.26
—
µs
tHD; DAT
0
—
µs
Data set-up time
tSU; DAT
50
—
ns
Rise time of SDA and SCL signals
tr
20 +0.1Cb
120
ns
Fall time of SDA and SCL signals
tf
20 +0.1Cb2
120
ns
Set-up time for STOP condition
tSU; STO
0.26
—
µs
Bus free time between STOP and START condition
tBUF
0.5
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
Data hold time for
I2C
bus devices
µs
1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
SR
tSU; STO
P
S
Figure 33. Timing definition for devices on the I2C bus
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5.5.5 UART
See General switching specifications.
5.6 Human-machine interfaces (HMI)
5.6.1 LCD electrical characteristics
Table 72. LCD electricals
Symbol
fFrame
Description
Min.
Typ.
Max.
Unit
• GCR[FFR]=0
23.3
—
73.1
Hz
• GCR[FFR]=1
46.6
—
146.2
Hz
Notes
LCD frame frequency
CLCD
LCD charge pump capacitance — nominal
value
—
100
—
nF
CBYLCD
LCD bypass capacitance — nominal value
—
100
—
nF
1
CGlass
LCD glass capacitance
—
2000
8000
pF
2
VIREG
VIREG
V
3
• RVTRIM=0000
—
0.91
—
• RVTRIM=1000
—
0.92
—
• RVTRIM=0100
—
0.93
—
• RVTRIM=1100
—
0.94
—
• RVTRIM=0010
—
0.96
—
• RVTRIM=1010
—
0.97
—
• RVTRIM=0110
—
0.98
—
• RVTRIM=1110
—
0.99
—
• RVTRIM=0001
—
1.01
—
• RVTRIM=1001
—
1.02
—
• RVTRIM=0101
—
1.03
—
• RVTRIM=1101
—
1.05
—
• RVTRIM=0011
—
1.06
—
• RVTRIM=1011
—
1.07
—
• RVTRIM=0111
—
1.08
—
• RVTRIM=1111
—
1.09
—
ΔRTRIM
VIREG TRIM resolution
—
—
3.0
% VIREG
IVIREG
VIREG current adder — RVEN = 1
—
1
—
µA
IRBIAS
RBIAS current adder
Table continues on the next page...
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Design considerations
Table 72. LCD electricals (continued)
Symbol
Description
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
RRBIAS
Min.
Typ.
Max.
Unit
—
10
—
µA
—
1
—
µA
—
0.28
—
MΩ
—
2.98
—
MΩ
Notes
RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL1
VLL1 voltage
—
—
VIREG
V
4
VLL2
VLL2 voltage
—
—
2 x VIREG
V
4
VLL3
VLL3 voltage
—
—
3 x VIREG
V
4
VLL1
VLL1 voltage
—
—
VDDA / 3
V
5
VLL2
VLL2 voltage
—
—
VDDA / 1.5
V
5
VLL3
VLL3 voltage
—
—
VDDA
V
5
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump
is enabled (GCR[CPSEL]=1).
5. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = VDDA
through the internal power switch (GCR[VSUPPLY]=0).
• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is
connected to VDDA externally (GCR[VSUPPLY]=1).
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
100
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Design considerations
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital
circuits between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground. Consider to add ferrite bead or
inductor to some sensitive lines.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground
plane directly under LQFP packages; and solder the exposed pad (EP) to ground
directly under QFN packages.
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as
sequential segments.
• Always route the power net as star topology, and make each power trace loop as
minimum as possible.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An
option is to use the internal reference voltage (output 1.2 V typically) as the ADC
reference.
NOTE
The internally-generated Voltage Reference Output
(VREF_OUT) is bonded to the VREFH pin on some
packages and to PTE30 on other packages. When
VREF_OUT is used, a 0.1 μF capacitor is required as a
filter. Do not connect any other supply voltage to the pin
that has VREF_OUT activated.
K32 L2B Microcontroller, Rev. 3, 09/2020
101
NXP Semiconductors
Design considerations
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value
of R must be RAS max if fast sampling and high resolution are
required. The value
of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
MCU
5
Input signal
1
4
2
1
R
ADCx
2
C
OSCILL
MCU
EXTAL
Figure 34. RC circuit for ADC input
1
CRY
2
1
High voltage measurement
circuits require voltage division, current limiting, and overvoltage protection as shown the following figure.
The1 voltage
divider
formed by R1 –
2
ADCx
Analog input
R4 must yield a voltage less than or equal to VREFH. The
current must be limited to
R
less than the injection current limit. Since the ADC pins do notC have diodes to VDD,
external clamp diodes must be included to protect against transient over-voltages.
D
OSCILL
EXTAL
1
2
1
R2
R4
1
2
2
1
ADCx
CRY
2
C
2
R3
R5
2
1
RF
1
1
High voltage input
2
1
MCU
VDD
3
1
R1
BAT54SW
Figure 35. High voltage measurement with an ADC input
MCU
SWD_DIO
SWD_CLK
RESET_b
RESET_b
RESET_b
1
0.1uF
2
HDR_5X2
10k
2
102
NXP Semiconductors
2
2
4
6
8
10
2
0.1uF
1
3
5
7
9
1
1
C
2
1
1
VDD
NOTE
For more details of ADC related usage, refer to AN5250: VDD
How to Increase the Analog-to-Digital
Converter Accuracy in
10k
VDD
an Application.
J1
10k
K32 L2B Microcontroller, Rev. 3, 09/2020
1
1
R
Design considerations
ADCx
Cx
2
2
1
1
C
2
6.1.4 Digital design
OSCILLATOR
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
EXTAL
CAUTION
1
Do not provide power to I/O pins prior to VDD, especiallyRF
the RESET_b pin.
1
1
2
1
CRYSTAL
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
2
C
external RC circuit is recommended to filter noise as shown in the following
figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the
BAT54SW
recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable
digital filter to reject spurious noise.
1
RS
1
1
ADCx
3
R4
Cx
2
2
2
1
2
R5
• RESET_b1 pin
2
2
2
2
EXTAL
XTAL
MCU
VDD
OSC
VDD
HDR_5X2
1
1
2
RESET_b
NMI_b
1
RESET_b
RESET_b
10k
2
10k
SWD_DIO
SWD_CLK
MCU
VDD
0.1uF
2
2
4
6
8
10
1
J1
2
10k
10k
Figure 36. Reset circuit
Active high,
open drain
RS
1
2
1
When an
external supervisor chipVDDis connected MCU
to the RESET_b pin, a series
Supervisor Chip
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
10k
the range of 100 Ω to 1 kΩ depending
on the external reset chip drive strength.
1
2
Select the open-drain
output
from
the supervisor
chip.
OUT
RESET_b
0.1uF
2
1
3
5
7
9
MCU
VDD
1
2
R3
Analog input
1
R2
2
CRYSTAL
2
R1
1
K32 L2B Microcontroller, Rev. 3, 09/2020
103
NXP Semiconductors
2
10k
4
Design considerations
OSCILLATOR
Supervisor Chip
EXTAL
OSCILLATOR
VDD
EXTAL
XTAL
MCU
XTAL
OSCILLATOR
EXTAL
XTAL
1
U
3
1
CRYSTAL
EXTAL
2
EXTAL
XTAL
OSCILLATOR
XTAL
1
2
1
2 reset chip
Figure 37. Reset
signal
connection to external
RF
RF
RS
EXTAL
XTAL
1
2
RF
RS
RS
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
MCU
MCU
VDD
1
1
VDD
10k
RESET_b
NMI_b
1
2
2
10k
2
0.1uF
• Debug interface
Figure 38. NMI pin biasing
MCU
This MCU
uses the standard Arm SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required (SWD_DIO
has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ
pull resistors are recommended for system robustness. The RESET_b pin
RESET_b
recommendations mentioned above must also be considered.
1
VDD
1
2
10k
0.1uF
2
2
2
2
2
1
1
2
2
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level
1
2
1
2
1
on this pin will trigger non-maskable
interrupt. When
this
pin is enabled as the
NMI 3
CRYSTAL
CRYSTAL
function, an external pull-up
resistor (10 kΩ)Cxas shown
in the following
figure is RESONATOR
Cy
recommended for robustness.
2
OSCILLATOR
1
• NMI pin
RESONATOR
RESET_b
1
U
Cy
1
OSCILLATOR
3
0.1uF
2
RS
2
2
CRYSTAL
Cx
1
OUT
1
1
2
2
1
10k
1
2
2
1
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K32 L2B Microcontroller, Rev. 3, 09/2020
NXP Semiconductors
4
1
2
C
2
2
2
1
1
R4
R3
BAT54SW
Design considerations
VDD
1
1
1
10k
2
SWD_DIO
SWD_CLK
RESET_b
RESET_b
RESET_b
0.1uF
1
2
0.1uF
2
4
6
8
10
1
1
3
5
7
9
C
J1
2
10k
VDD
MCU
VDD
2
HDR_5X2
2
10k
Figure 39. SWD debug interface
• Low leakage stop mode wakeup
Supervisor Chip
MCU
1
VDD
OUT
• Unused pin
0.1uF
2
Active high,
open drain
RS
1
2
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the10k
low leakage stop modes (LLS/VLLSx). See the pinout table for pin selection.
1
2
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
B
If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM)
floating.
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators.
An external feedback is required when using high gain (HGO=1) mode.
Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786 kHz)
mode. Use the SCxP bits in the OSC0_CR register to adjust the load capacitance for
the crystal. Typically, values of 10pf to 16 pF are sufficient for 32.768 kHz crystals
that have a 12.5 pF CL specification. The internal load capacitor selection must not be
used for high frequency crystals and resonators.
A
105
K32 L2B Microcontroller, Rev. 3, 09/2020
5
4
NXP Semiconductors
RESET_b
Design considerations
Table 73. External crystal/resonator connections
Oscillator mode
Oscillator mode
Low frequency (32.768 kHz), low power
Diagram 1
Low 4frequency (32.768 kHz), high gain
Diagram 2, Diagram 4
High frequency (3-32 MHz), low power
Diagram 3
High frequency (3-32 MHz), high gain
Diagram 4
EXTAL
EXTAL
XTAL
1
CRYSTAL
CRYSTAL
1
XTAL
2
RF
RF
RS
OSCILLATOR
EXTAL
2
1
CRYSTAL
2
2
1
RF
RESET_b
RF
Cx
1
3
2
2
2
NMI_b
1
2
CRYSTAL
2
2
RS
10k
Cy
RESONATOR
NMI_b
1
2
0.1uF
1
2
2
2
CRYSTAL
1
1
1
SET_b
RESET_b
2
10k
10k
RS
2
2
RS
MCU
2
1
1
XTAL
2
RF
VDDEXTAL
XTAL
2
1
EXTAL
2
10k
VDD
42.
Crystal connection
– Diagram
3
MCU
OSCILLATOR
OSCILLATOR
1
1
RESONATOR
1
XTAL
MCU
EXTAL
1
VDD
Figure
MCU
OSCILLATOR
Cy
1
VDD
3
2
Cx
XTAL
2
CRYSTAL
EXTAL
2
1
2
1
1
Cy
OSCILLATOR
XTAL
1
XTAL
2
1
1
OSCILLATOR
EXTAL
2
Figure 41. Crystal connection – Diagram 2
2
CRYSTAL
CRYSTAL
Cx Cx
3
12
1
CRYSTAL
CRYSTAL
1
1
1
2
22
2
11
RS
RS
2
RS
ADCx
1
1
1
1
RF
EXTAL
2
2
2
RF
0.1uF
K32 L2B Microcontroller, Rev. 3, 09/2020
2
106
NXP Semiconductors
MCU
VDD
MCU
OSC
XTAL
1
1
1
MCU
EXTAL
XTAL
2
1
MCU
Cy
OSCILLATOR
EXTAL
OSCILLATOR XTAL
EXTAL
1
1
OSCILLATOR
OSCILLATOR
EXTAL
Cy
2
CRYSTAL
Cx
Figure 40. Crystal connection – Diagram 1
EXTAL
2
ADCx
XTAL
2
1
Cx
Cx
2
OSC
2
1
EXTAL
XTAL
CRYSTAL
1
1
1
2
2
EXTAL
1
XTAL
OSCILLATOR
OSCILLATOR
MCU
OSCILLATOR
1
MCU
Cx
3
OSCILLATOR
2
4
3
Cy
CRYSTAL
2
1
CRYSTAL
Cy
RESONATOR
2
2
Cx
3
2
1
1
2
1
1
Part identification
OSCILLATOR
EXTAL
XTAL
2
1
RF
1
RF
CRYSTAL
2
Cx
2
2
1
3
1
CRYSTAL
2
RS
Cy
RESONATOR
2
1
1
2
2
RS
2
RS
1
XTAL
2
RF
EXTAL
2
1
1
XTAL
1
EXTAL
OSCILLATOR
1
OSCILLATOR
Figure 43. Crystal connection – Diagram 4
6.2 Software considerations
VDD
MCU
2
1
All K32 L-series ultra-low power Microcontrollers (MCUs), optimized for lowleakage applications, are supported by comprehensive NXP and third-party hardware
10k
and software
enablement solutions, which can reduce development costs and time to
market. Featured software and tools are listed below.
NMI_b
Evaluation and Prototyping Hardware
• NXP Freedom Development Platform: http://www.nxp.com/freedom
• Tower System Development Platform: http://www.nxp.com/tower
IDEs for K32 L2B MCUs
• MCUXpresso: https://mcuxpresso.nxp.com
Run-time Software
• K32 L2B SDK: http://mcuxpresso.nxp.com
For all other partner-developed software and tools, visit http://www.nxp.com/partners.
7 Part identification
K32 L2B Microcontroller, Rev. 3, 09/2020
107
NXP Semiconductors
Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
B PF S FS SPF T PG FR SR PT
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 74. Part number fields descriptions
Field
Description
Values
B
Brand
• K32
PF
Product Family
• L2
S
Sub-family
• A= Sub-family A
• B= Sub-family B
FS
Flash size
•
•
•
•
SPF
Special Feature
• 0 = Dual core
• 1 = Single core
T
Temperature range (°C)
• V = -40 to 105
PG
Package
•
•
•
•
FR
Frequency (MHz)
• 0 = 0 - 50 MHz
SR
Silicon Revision
• A = Initial Mask Set
• B = 1st Major Spin
PT
Packaging Type
• R = Std Reel
108
NXP Semiconductors
1 = 64 KB
2 = 128 KB
3 = 256 KB
4 = 512 KB
FM = 32 QFN
FT = 48 QFN
MP = 64 BGA
LH = 64 LQFP
K32 L2B Microcontroller, Rev. 3, 09/2020
Small package marking
7.4 Example
This is an example part number:
K32L2B31VLH0A
8 Small package marking
In order to save space, small package devices use special marking on the chip.
Q FS FF TP
Field
Description
Values
Q
Qualification status
K=M
FS
Family
L2B=K32L2B family
FF
Program flash memory size
6=64 KB
PK=P
7=128 KB
8=256 KB
TP
Temperature range
V=-40 to 105 for all 4 packages
For example:
KL2B6V = K32L2B11VFM0A
9 Package marking information
The K32L2B 64LQFP package has the following top-side marking:
• First line: aaaaaaaa
• Second line: aaaaa
• Third line: mmmmm
• Fourth line: xxxyywwx
The K32L2B 64MAPBGA package has the following top-side marking:
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx
The K32L2B 48QFN package has the following top-side marking:
K32 L2B Microcontroller, Rev. 3, 09/2020
109
NXP Semiconductors
Revision History
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx
The K32L2B 32QFN package has the following top-side marking:
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx
The detailed code format for these identifiers is show in the table below.
Identifier
Description
a
Part number code, refer to the "Part identification" section.
m
Mask set
y
Work year
w
Work week
x
NXP internal use
10 Revision History
The following table provides a revision history for this document.
Table 75. Revision History
Rev. No.
Date
Substantial Changes
3
September
2020
• Updated value of ADC to 461 ksps from 818 in front page of the Data sheet.
• Removed "RESET_b" from ALT7 column and "PTA20" from ALT1 column
corresponding to PTA20 pin in K32 L2B Signal Multiplexing and Pin Assignments
(LQFP and MAPBGA) and K32 L2B Signal Multiplexing and Pin Assignments (QFN).
Also added the following note: When FTFA_FOPT[RESET_PIN_CONFIG]=0, PTA20
pin acts as RESET_B function only during ............of PORTA_PCR20[MUX]'s setting
value.
• Added Package marking information and Small package marking.
• Removed "OTG/On the Go" references.
2
December
2019
• Added Related Resources table in front page of the Data sheet.
• Corrected description of PD/PU in Table 8 Pin Properties section.
• Updated values in "Default" column for pins 1, 2, 9, 10, 49-52 in K32 L2B Signal
Multiplexing and Pin Assignments (LQFP and MAPBGA).
• Added EXTRG_IN signal in TPM signal descriptions and Table 29.
1
September
2019
Initial public release.
• Removed support of CRC throughout.
• Replaced name of function pin VREFO with VREF_OUT.
• Changed the high drive pin number to 6 for 48 QFN in Ordering information.
• Updated flash and RAM in Figure 1. System diagram in the Overview section.
Table continues on the next page...
110
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Revision History
Table 75. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Added DAC topic to the "Peripheral Features" section.
• Updated memory addresses and peripherals in Memory map.
• Updated 32 QFN and 48 QFN pinouts and diagrams to remove usage of USB_VDD
pin.
• Updated pin names in Pin properties. Split the table into two, each for 64 LQFP/
MAPBGA and 32/48 QFN packages.
• Added thermal attributes for 32 QFN and 48 QFN packages in Thermal attributes.
• Updated part number format and fields in Format and Fields.
0
July 2019
• Initial release (internal).
K32 L2B Microcontroller, Rev. 3, 09/2020
111
NXP Semiconductors
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Document Number K32L2B3x
Revision 3, 09/2020
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