K32W041AMY

NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 32W 41A M K32W041A/K32W041AM IEEE 802.15.4 and Bluetooth LE 5.0 wireless microcontroller Rev. 1.2 — April 2022 Product data sheet 1. General description The K32W041A/K32W041AM are ultra-low power, high performance Arm® Cortex®-M4 based wireless microcontrollers supporting Zigbee 3.0, Thread and Bluetooth Low Energy 5.0 networking stacks to facilitate home and building automation, smart lighting, smart locks and sensor network applications. The K32W041A/K32W041AM includes a 2.4 GHz Bluetooth Low Energy 5 (supporting eight simultaneous connections) compliant transceiver, a 2.4 GHz IEEE 802.15.4 compliant transceiver and a comprehensive mix of analog and digital peripherals. Ultra-low current consumption in both radio receive and transmit modes and also in the power down modes allow use of coin cell batteries. The product has 640 KB embedded Flash, 152 KB RAM memory and extend the radio output power to +15dBm. The K32W041AM has an additional 1 MB Data Flash. The embedded flash can support Over The Air (OTA) code download to applications. The devices include a 10-channel PWM, two timers, one RTC/alarm timer, a Windowed Watchdog Timer (WWDT), two USARTs, two SPI interfaces, two I2C interfaces, a DMIC subsystem including a dual-channel PDM microphone interface with voice activity detector, one 12-bit ADC, temperature sensor and a comparator. The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level support of the block integration. The Arm Cortex-M4 CPU, operates at up to 48 MHz. 2. Features and benefits 2.1 Benefits Very low current solution for long battery life Single chip device to run stack and application System BOM is low in component count and cost Flexible sensor interfacing Package  6 6 mm HVQFN40, 0.5 mm pitch  Lead-free and RoHS compliant  Ambient temperature range: 40 C to +85 C      2.2 Radio features  2.4 GHz IEEE 802.15.4 2011 compliant  2.4 GHz Bluetooth Low Energy 5.0 compliant K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 1 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM                Receiver current: 7.0 mA IEEE 802.15.4 Receiver sensitivity -100 dBm Bluetooth Low Energy 5.0 2 Mb/s high data rate Bluetooth Low Energy Receiver sensitivity -97 dBm for 1 MB/s Improved co-existence with WiFi Configurable transmit power up to  +15 dBm, with 46 dB range Transmit power / current  +15 dBm / 51 mA  +10 dBm / 26 mA  +3 dBm /13 mA  +0 dBm / 10.2 mA Supply voltage  2.4 V to 3.6 V Antenna Diversity control 32 MHz XTAL cell with internal capacitors, able with suitable external XTAL to meet the required accuracy for radio operation over the operating conditions Integrated RF balun Integrated ultra Low-power sleep oscillator Deep Power-down current (with wake-up on IO)  350 nA (K32W041A)  360 nA (K32W041AM) 128-bit, 192-bit or 256-bit AES security processor MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers 2.3 Microcontroller features  Application CPU, Arm Cortex-M4 CPU:  Arm Cortex-M4 processor, running at a frequency of up to 48 MHz.  Arm built-in Nested Vectored Interrupt Controller (NVIC)  Memory Protection Unit (MPU)  Non-maskable Interrupt (NMI) with a selection of sources  Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints  System tick timer  Includes Serial Wire Output for enhanced debug capabilities.  On-Chip memory  640 KB flash, K32W041AM has an additional 1 MB data flash  152 KB SRAM  12 MHz to 48 MHz system clock speed for low-power  2 x I2C-bus interface, operate as either master or slave  10 x PWM on K32W041A and 9 x PWM on K32W041AM  2 x Low-power timers  2 x USART, one with flow control  2 x SPI-bus, master or slave K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 2 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM  1 x PDM digital audio interface with a hardware based voice activity detector to reduce power consumption in voice applications. Support for dual-channel microphone interface, flexible decimators, 16 entry FIFOs and optional DC blocking.  19-channel DMA engine for efficient data transfer between peripherals and SRAM, or SRAM to SRAM. DMA can operate with fixed or incrementing addresses. Operations can be chained together to provide complex functionality with low CPU overhead.  Up to four GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges.  Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states.  32-bit Real Time clock (RTC) with 1 s resolution. A timer in the RTC can be used to wake from Sleep, Deep-sleep and Power-down, with 1 ms resolution  Voltage Brown Out with 8 programmable thresholds  8-input (K32W041A) or 5-input (K32W041AM), 12-bit ADC, 190 ksamples/s (Max.). HW support for continuous operation or single conversions, single or multiple inputs can be sampled within a sequence. DMA operation can be linked to achieve low overhead operation.  1 x analog comparator, for K32W041AM, only one external input can be used to be compared with the internal reference  Battery and temperature sensors  Watchdog timer and POR  Standby power controller  Up to 22 (K32W041A) or 18 (K32W041AM) Digital IOs (DIO)  1 x Quad SPIFI for accessing:  an external series flash device (K32W041A)  an internal flash device (K32W041AM)  Random Number Generator engine  AES engine AES-128 to 256  Hash hardware accelerator supporting SHA-1 and SHA-256  EFuse:  128-bit random AES key  Configuration modes  Trimming  ISO7816 smart card digital interface which with a suitable external analogue device can operate as a smart card reader 2.4 Low power features  Sleep mode supported, the CPU in low power state waiting for interrupt  Deep-sleep mode supported, the CPU in low power state waiting for interrupt, but extra functionality disabled or in low power state compared to sleep mode  Power Down mode, main functionality powered down, wakeup possible from IOs, wakeup possible from some peripherals (I2C, USART, SPI) in a limited function mode and low power timers  Deep -power down, very low power state with option of wake-up triggered by IOs, 350 nA for K32W041A device, or 360 nA for K32W041AM device. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 3 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM  41-bit and 28-bit Low power timers can run in power down mode, clocked by 32 kHz FRO or 32 kHz XTAL. Timers can run for over one year or 2 days  Dedicated low power timer, clocked by 32 kHz XTAL, closely integrated with the Bluetooth Low Energy link layer to maintain the timing reference through power down cycles 3. Applications      Zigbee 3.0, Thread networks Bluetooth Low Energy 5.0 networks Robust and secure low-power wireless applications Smart lighting, door locks, thermostats and home automation Wireless sensor networks 4. Ordering information Table 1. Ordering information Part Number K32W041AZ K32W041AY Package Flash Size SRAM Size 1 MB Data Flash Transmit Power MPQ 40 HVQFN; 6  6  0.85 mm 640 KB 152 KB No +15 dBm 1000 pcs/reel 4000 pcs/reel K32W041AK 2450 pcs/5 trays K32W041AMZ Yes 1000 pcs/reel K32W041AMY 4000 pcs/reel K32W041AMK 2450 pcs/5 trays 5. Marking Table 2. Marking codes Type number Marking code K32W041AZ 32W41A K32W041AY K32W041AK K32W041AMZ 32W41AM K32W041AMY K32W041AMK K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 4 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 6. Block diagram Core System Memories Digital peripherals Cortex-M4 48 MHz Watchdog timer Flash 640 KB 2 × I2 C Serial wire debug POR SRAM 152 KB 2 × SPI RF transceiver Brown-out detectors Analog peripherals 2 × USART Fast antenna diversity 12-bit ADC 8 channels DMA Bluetooth 5 IEEE 802.15.4 2011 Power management controller 1 × Analog comparator 10 × PWM 1 × DMIC DC/DC converter 1 × QSPI Battery sensor Clocks 32 MHz XTAL oscillator Security 32.768 kHz XTAL oscillator Up to 22 × GPIO Temperature sensor HASH Timers 2 × Low power counter/timer 1 × IR modulator 1 × ISO7816 Low frequency free running oscillator AES 128/256 High frequency free running oscillator Random number generator Fig 1. K32W041A/K32W041AM Product data sheet Real time clock 2 × Wakeup timers K32W041A high level hardware block diagram All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 5 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Core System Memories Digital peripherals Cortex-M4 48 MHz Watchdog timer Flash 640 KB 2 × I2 C Serial wire debug POR SRAM 152 KB 2 × SPI RF transceiver Brown-out detectors Data flash 1 MB Fast antenna diversity DMA Analog peripherals Bluetooth 5 IEEE 802.15.4 2011 Power management controller 12-bit ADC 5 channels 1 × Analog comparator 2 × USART 9 × PWM 1 × DMIC Up to 18× GPIO Battery sensor DC/DC converter Clocks 32 MHz XTAL oscillator 1 × IR modulator Temperature sensor Timers 1 × ISO7816 Security 32.768 kHz XTAL oscillator Low frequency free running oscillator AES 128/256 High frequency free running oscillator Random number generator Fig 2. K32W041A/K32W041AM Product data sheet HASH 2 × Low power counter/timer Real time clock 2 × Wakeup timers K32W041AM high level hardware block diagram All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 6 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 7. Pinning information 7.1 K32W041A n.c. VSS(RF) RF_IO VSS(RF) VDD(RADIO) XTAL_32K_N XTAL_32K_P VDD(PMU) FB 38 37 36 35 34 33 32 31 n.c. 39 terminal 1 index area 40 7.1.1 Pinning XTAL_P 1 30 XTAL_N 2 29 LX PIO0 PIO1 3 28 VBAT 4 27 RSTN PIO2 5 26 TRST PIO3 6 25 PIO21/ACM K32W041A VSS(DCDC) 17 18 19 PIO14/ADC0 PIO15/ADC1 PIO16/ADC2 VDDE 20 16 PIO13/SWDIO PIO17/ADC3 15 21 14 10 PIO11 PIO18/ADC4 PIO7 PIO12/SWCLK 22 13 9 PIO10 PIO19/ADC5 PIO6 11 PIO20/ACP 23 12 24 8 PIO8/TXD0 7 PIO9/RXD0 PIO4 PIO5/ISP_ENTRY Transparent top view Fig 3. Pin configuration 7.1.2 Pin description Table 3. Pin descriptions Symbol Pin XTAL_P 1 XTAL_N 2 PIO0 3 Type Default at reset Description System crystal oscillator 32 MHz System crystal oscillator 32 MHz IO GPIO0[1] GPIO0 — General Purpose digital Input/Output 0 USART0_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - synchronous clock USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output PWM0 — Pulse Width Modulator output 0 SPI1_SCK — Serial Peripheral Interface-bus 1 clock input/output PDM0_DATA — Pulse Density Modulation Data input from digital microphone (channel 0) K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 7 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 3. Pin descriptions Symbol Pin Type Default at reset PIO1 4 IO GPIO1[1] Description GPIO1 — General Purpose digital Input/Output 1 USART1_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - receive data input PWM1 — Pulse Width Modulator output 1 SPI1_MISO — Serial Peripheral Interface-bus 1 master data input PDM0_CLK — Pulse Density Modulation Clock output to digital microphone (channel 0) PIO2 5 IO GPIO2[1] GPIO2 — General Purpose digital Input/Output 2 SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output PWM2 — Pulse Width Modulator output 2 SPI1_MOSI — Serial Peripheral Interface-bus 1 master output slave input USART0_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - receive data input ISO7816_RST — RST signal, output, for ISO7816 interface MCLK — External clock, can be provided to DMIC IP PIO3 6 IO GPIO3[1] GPIO3 — General Purpose digital Input/Output 3 SPI0_MISO — Serial Peripheral Interface-bus 0 master input PWM3 — Pulse Width Modulator output 3 SPI1_SSELN0 — Serial Peripheral Interface-bus 1 slave select not 0 USART0_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - transmit data output ISO7816_CLK — Clock output for ISO7816 interface PIO4 7 IO GPIO4[1][2] GPIO4 — General Purpose digital Input/Output 4 SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave input PWM4 — Pulse Width Modulator output 4 SPI1_SSELN1 — Serial Peripheral Interface-bus 1 slave select not 1 USART0_CTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Clear To Send input ISO7816_IO — IO of ISO7816 interface RFTX — Radio Transmit Control Output ISP_SEL — In-System Programming Mode Selection PIO5/ISP_ENT RY 8 IO GPIO5/ISP_ENT RY[1][3] GPIO5/ISP_ENTRY — General Purpose digital Input/Output 5; In-System Programming Entry SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not SPI1_MISO — Serial Peripheral Interface-bus 1 master data input SPI1_SSELN2 — Serial Peripheral Interface-bus 1 slave select not 2 USART0_RTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Request To Send output RFRX — Radio Receiver Control Output K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 8 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 3. Pin descriptions Symbol Pin Type Default at reset PIO6 9 IO GPIO6[1] Description GPIO6 — General Purpose digital Input/Output 6 USART0_RTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Request to Send output CT32B1_MAT0 — 32-bit CT32B1 match output 0 PWM6 — Pulse Width Modulator output 6 I2C1_SCL — I2C-bus 1 master/slave SCL input/output USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output ADE — Antenna Diversity Even output SPI0_SCK — Serial Peripheral Interface 0- synchronous clock PIO7 10 IO GPIO7[1] GPIO7 — General Purpose digital Input/Output 7 USART0_CTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Clear to Send input CT32B1_MAT1 — 32-bit CT32B1 match output 1 PWM7 — Pulse Width Modulator output 7 I2C1_SDA — I2C-bus 1 master/slave SDA input/output USART1_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - receive data input ADO — Antenna Diversity Odd Output SPI0_MISO — Serial Peripheral Interface-bus 0 master input PIO8/TXD0 11 IO GPIO8[1][4] GPIO8 — General Purpose digital Input/Output 8 USART0_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - transmit data output CT32B0_MAT0 — 32-bit CT32B0 match output 0 PWM8 — Pulse Width Modulator output 8 ANA_COMP_OUT — Analog Comparator digital output PDM1_DATA — Pulse Density Modulation Data input from digital microphone (channel 1) SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave input RFTX — Radio Transmit Control Output PIO9/RXD0 12 IO GPIO9[1][5] GPIO9 — General Purpose digital Input/Output 9 USART0_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - receive data input CT32B1_CAP1 — 32-bit CT32B1 capture input 1 PWM9 — Pulse Width Modulator output 9 USART1_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - synchronous clock PDM1_CLK — Pulse Density Modulation Clock output to digital microphone (channel 1) SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not ADO — Antenna Diversity Odd Output K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 9 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 3. Pin descriptions Symbol Pin Type Default at reset PIO10 13 IO GPIO10[1] Description GPIO10 — General Purpose digital Input/Output 10 CT32B0_CAP0 — 32-bit CT32B0 capture input 0 USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output RFTX — Radio Transmit Control Output I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain) SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output PDM0_DATA — Pulse Density Modulation Data input from digital microphone (channel 0) PIO11 14 IO GPIO11[1] GPIO11 — General Purpose digital Input/Output 11 CT32B1_CAP0 — 32-bit CT32B1 capture input 0 USART1_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - receive data input RFRX — Radio Receiver Control Output I2C0_SDA — I2C-bus 0 master/slave SDA input/output (open drain) SPI0_MISO — Serial Peripheral Interface-bus 0 master input slave output PDM0_CLK — Pulse Density Modulation Clock output to digital microphone (channel 0) PIO12/SWCLK 15 IO SWCLK GPIO12 — General Purpose digital Input/Output 12 SWCLK — Serial Wire Debug Clock PWM0 — Pulse Width Modulator output 0 I2C1_SCL — I2C-bus 1 master/slave SCL input/output (open drain) SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave input ANA_COMP_OUT — Analog Comparator digital output IR_BLASTER — Infra-Red Modulator output PIO13/SWDIO 16 IO SWDIO GPIO13 — General Purpose digital Input/Output 13 SPI1_SSELN2 — Serial Peripheral Interface-bus 1, slave select not 2 SWDIO — Serial Wire Debug Input/Output PWM2 — Pulse Width Modulator output 2 I2C1_SDA — I2C-bus 1 master/slave SDA input/output (open drain) SPI0_SSELN — Serial Peripheral Interface-bus 0, slave select not K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 10 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 3. Pin descriptions Symbol Pin Type Default at reset PIO14/ADC0 17 IO GPIO14[1] Description ADC0 — ADC input 0 GPIO14 — General Purpose digital Input/Output 14 SPI1_SSELN1 — Serial Peripheral Interface-bus 1, slave select not 1 CT32B0_CAP1 — 32-bit CT32B0 capture input 1 PWM1 — Pulse Width Modulator output 1 SWO — Serial Wire Output USART0_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - synchronous clock MCLK — External clock, can be provided to DMIC IP RFTX — Radio Transmit Control Output PIO15/ADC1 18 IO GPIO15[1] ADC1 — ADC input 1 GPIO15 — General Purpose digital Input/Output 15 SPI1_SCK — Serial Peripheral Interface-bus 1, clock input/output ANA_COMP_OUT — Analog Comparator digital output PWM3 — Pulse Width Modulator output 3 PDM1_DATA — Pulse Density Modulation Data input from digital microphone (channel 1) I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain) RFRX — Radio Receiver Control Output PIO16/ADC2 19 IO GPIO16[1] ADC2 — ADC input 2 GPIO16 — General Purpose digital Input/Output 16 SPI1_SSELN0 — Serial Peripheral Interface-bus 1, slave select not 0 PWM5 — Pulse Width Modulator output 5 PDM1_CLK — Pulse Density Modulation Clock output to digital microphone (channel 1) SPIFI_CSN — Quad-SPI Chip Select Not, output ISO7816_RST — RST signal, output, for ISO7816 interface I2C0_SDA — I2C-bus 0 master/slave SDA input/output (open drain) VDDE PIO17/ADC3 20 21 P IO VDDE — Supply voltage for IO GPIO17[1] ADC3 — ADC input 3 GPIO17 — General Purpose digital Input/Output 17 SPI1_MOSI — Serial Peripheral Interface-bus 1, master output slave input SWO — Serial Wire Output PWM6 — Pulse Width Modulator output 6 SPIFI_IO3 — Quad-SPI Input/Output 3 ISO7816_CLK — Clock output for ISO7816 interface CLK_OUT — Clock out K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 11 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 3. Pin descriptions Symbol Pin Type Default at reset PIO18/ADC4 22 IO GPIO18[1] Description ADC4 — ADC input 4 GPIO18 — General Purpose digital Input/Output 18 SPI1_MISO — Serial Peripheral Interface-bus 1, master data input CT32B0_MAT1 — 32-bit CT32B0 match output 1 PWM7 — Pulse Width Modulator output 7 SPIFI_CLK — Quad-SPI Clock output ISO7816_IO — IO of ISO7816 interface USART0_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - transmit data output PIO19/ADC5 23 IO GPIO19[1] ADC5 — ADC input 5 GPIO19 — General Purpose digital Input/Output 19 ADO — Antenna Diversity Odd Output PWM4 — Pulse Width Modulator output 4 SPIFI_IO0 — Quad-SPI Input/Output 0 USART1_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - receive data input CLK_IN — External clock USART0_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - receive data input PIO20/ACP 24 IO GPIO20[1] ACP — Analog Comparator Positive input GPIO20 — General Purpose digital Input/Output 20 IR_BLASTER — Infra-Red Modulator output PWM8 — Pulse Width Modulator output 8 RFTX — Radio Transmit Control Output SPIFI_IO2 — Quad-SPI Input/Output 2 USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output PIO21/ACM 25 IO GPIO21[1] ACM — Analog Comparator Negative input GPIO21 — General Purpose digital Input/Output 21 IR_BLASTER — Infra-Red Modulator output PWM9 — Pulse Width Modulator output 9 RFRX — Radio Receiver Control Output SWO — Serial Wire Output SPIFI_IO1 — Quad-SPI Input/Output 1 USART1_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - synchronous clock TRST 26 G TRST — must be connected to GND RSTN 27 I RSTN — Reset Not input VBAT 28 P VBAT — Supply voltage DCDC input G VSS(DCDC) — ground for DCDC section LX 29 VSS(DCDC) 30 FB 31 K32W041A/K32W041AM Product data sheet LX — DCDC filter FB — DCDC Feedback input All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 12 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 3. Pin descriptions Symbol Pin Type Default at reset Description VDD(PMU) 32 P VDD(PMU) — supply voltage for PMU section XTAL_32K_P 33 crystal oscillator 32.768 kHz XTAL_32K_N 34 crystal oscillator 32.768 kHz VDD(RADIO) 35 P VDD(RADIO) — supply voltage for radio section VSS(RF) 36 G VSS(RF) — RF ground RF_IO 37 IO RF_IO — RF antenna, RF pin which can be considered as RF Input/output. The radio transceiver is connected here. VSS(RF) 38 G n.c. 39 not connected n.c. 40 not connected exposed die pad K32W041A/K32W041AM Product data sheet VSS(RF) — RF ground G must be connected to RF ground plane [1] I: input at reset. [2] For standard operation (normal boot or ISP programming mode), this pin should be high during the release of reset. If there is no external driver to this pin, then the internal pull-up will keep this pin high. [3] ISP programming mode: leave pin floating high during reset to avoid entering UART programming mode or hold it low to program. [4] In ISP mode, it is configured to USART0_TXD. [5] In ISP mode, it is configured to USART0_RXD. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 13 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 7.2 K32W041AM n.c. VSS(RF) RF_IO VSS(RF) VDD(RADIO) XTAL_32K_N XTAL_32K_P VDD(PMU) FB 38 37 36 35 34 33 32 31 FLASH_RSTN 39 terminal 1 index area 40 7.2.1 Pinning XTAL_P 1 30 XTAL_N 2 29 LX PIO0 PIO1 3 28 VBAT 4 27 RSTN PIO2 5 26 PIO3 6 25 TRST n.c. K32W041AM VSS(DCDC) 17 18 19 PIO14/ADC0 PIO15/ADC1 FLASH_CSN VDDE 20 16 PIO13/SWDIO PIO17/ADC3 15 21 14 10 PIO11 n.c. PIO7 PIO12/SWCLK 22 13 9 PIO10 n.c. PIO6 11 PIO20/ACP 23 12 24 8 PIO8/TXD0 7 PIO9/RXD0 PIO4 PIO5/ISP_ENTRY Transparent top view Fig 4. Pin configuration 7.2.2 Pin description Table 4. Pin descriptions Symbol Pin XTAL_P 1 XTAL_N 2 PIO0 3 Type Default at reset Description System crystal oscillator 32 MHz System crystal oscillator 32 MHz IO GPIO0[1] GPIO0 — General Purpose digital Input/Output 0 USART0_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - synchronous clock USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output PWM0 — Pulse Width Modulator output 0 SPI1_SCK — Serial Peripheral Interface-bus 1 clock input/output PDM0_DATA — Pulse Density Modulation Data input from digital microphone (channel 0) K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 14 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 4. Pin descriptions Symbol Pin Type Default at reset PIO1 4 IO GPIO1[1] Description GPIO1 — General Purpose digital Input/Output 1 USART1_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - receive data input PWM1 — Pulse Width Modulator output 1 SPI1_MISO — Serial Peripheral Interface-bus 1 master data input PDM0_CLK — Pulse Density Modulation Clock output to digital microphone (channel 0) PIO2 5 IO GPIO2[1] GPIO2 — General Purpose digital Input/Output 2 SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output PWM2 — Pulse Width Modulator output 2 SPI1_MOSI — Serial Peripheral Interface-bus 1 master output slave input USART0_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - receive data input ISO7816_RST — RST signal, output, for ISO7816 interface MCLK — External clock, can be provided to DMIC IP PIO3 6 IO GPIO3[1] GPIO3 — General Purpose digital Input/Output 3 SPI0_MISO — Serial Peripheral Interface-bus 0 master input PWM3 — Pulse Width Modulator output 3 SPI1_SSELN0 — Serial Peripheral Interface-bus 1 slave select not 0 USART0_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - transmit data output ISO7816_CLK — Clock output for ISO7816 interface PIO4 7 IO GPIO4[1][2] GPIO4 — General Purpose digital Input/Output 4 SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave input PWM4 — Pulse Width Modulator output 4 SPI1_SSELN1 — Serial Peripheral Interface-bus 1 slave select not 1 USART0_CTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Clear To Send input ISO7816_IO — IO of ISO7816 interface RFTX — Radio Transmit Control Output ISP_SEL — In-System Programming Mode Selection PIO5/ISP_ENT RY 8 IO GPIO5/ISP_ENT RY[1][3] GPIO5/ISP_ENTRY — General Purpose digital Input/Output 5; In-System Programming Entry SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not SPI1_MISO — Serial Peripheral Interface-bus 1 master data input SPI1_SSELN2 — Serial Peripheral Interface-bus 1 slave select not 2 USART0_RTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Request To Send output RFRX — Radio Receiver Control Output K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 15 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 4. Pin descriptions Symbol Pin Type Default at reset PIO6 9 IO GPIO6[1] Description GPIO6 — General Purpose digital Input/Output 6 USART0_RTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Request to Send output CT32B1_MAT0 — 32-bit CT32B1 match output 0 PWM6 — Pulse Width Modulator output 6 I2C1_SCL — I2C-bus 1 master/slave SCL input/output USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output ADE — Antenna Diversity Even output SPI0_SCK — Serial Peripheral Interface 0- synchronous clock PIO7 10 IO GPIO7[1] GPIO7 — General Purpose digital Input/Output 7 USART0_CTS — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - Clear to Send input CT32B1_MAT1 — 32-bit CT32B1 match output 1 PWM7 — Pulse Width Modulator output 7 I2C1_SDA — I2C-bus 1 master/slave SDA input/output USART1_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - receive data input ADO — Antenna Diversity Odd Output SPI0_MISO — Serial Peripheral Interface-bus 0 master input PIO8/TXD0 11 IO GPIO8[1][4] GPIO8 — General Purpose digital Input/Output 8 USART0_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - transmit data output CT32B0_MAT0 — 32-bit CT32B0 match output 0 PWM8 — Pulse Width Modulator output 8 ANA_COMP_OUT — Analog Comparator digital output PDM1_DATA — Pulse Density Modulation Data input from digital microphone (channel 1) SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave input RFTX — Radio Transmit Control Output PIO9/RXD0 12 IO GPIO9[1][5] GPIO9 — General Purpose digital Input/Output 9 USART0_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - receive data input CT32B1_CAP1 — 32-bit CT32B1 capture input 1 PWM9 — Pulse Width Modulator output 9 USART1_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - synchronous clock PDM1_CLK — Pulse Density Modulation Clock output to digital microphone (channel 1) SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not ADO — Antenna Diversity Odd Output K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 16 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 4. Pin descriptions Symbol Pin Type Default at reset PIO10 13 IO GPIO10[1] Description GPIO10 — General Purpose digital Input/Output 10 CT32B0_CAP0 — 32-bit CT32B0 capture input 0 USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output RFTX — Radio Transmit Control Output I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain) SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output PDM0_DATA — Pulse Density Modulation Data input from digital microphone (channel 0) PIO11 14 IO GPIO11[1] GPIO11 — General Purpose digital Input/Output 11 CT32B1_CAP0 — 32-bit CT32B1 capture input 0 USART1_RXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - receive data input RFRX — Radio Receiver Control Output I2C0_SDA — I2C-bus 0 master/slave SDA input/output (open drain) SPI0_MISO — Serial Peripheral Interface-bus 0 master input slave output PDM0_CLK — Pulse Density Modulation Clock output to digital microphone (channel 0) PIO12/SWCLK 15 IO SWCLK GPIO12 — General Purpose digital Input/Output 12 SWCLK — Serial Wire Debug Clock PWM0 — Pulse Width Modulator output 0 I2C1_SCL — I2C-bus 1 master/slave SCL input/output (open drain) SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave input ANA_COMP_OUT — Analog Comparator digital output IR_BLASTER — Infra-Red Modulator output PIO13/SWDIO 16 IO SWDIO GPIO13 — General Purpose digital Input/Output 13 SPI1_SSELN2 — Serial Peripheral Interface-bus 1, slave select not 2 SWDIO — Serial Wire Debug Input/Output PWM2 — Pulse Width Modulator output 2 I2C1_SDA — I2C-bus 1 master/slave SDA input/output (open drain) SPI0_SSELN — Serial Peripheral Interface-bus 0, slave select not K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 17 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 4. Pin descriptions Symbol Pin Type Default at reset PIO14/ADC0 17 IO GPIO14[1] Description ADC0 — ADC input 0 GPIO14 — General Purpose digital Input/Output 14 SPI1_SSELN1 — Serial Peripheral Interface-bus 1, slave select not 1 CT32B0_CAP1 — 32-bit CT32B0 capture input 1 PWM1 — Pulse Width Modulator output 1 SWO — Serial Wire Output USART0_SCK — Universal Synchronous/Asynchronous Receiver/Transmitter 0 - synchronous clock MCLK — External clock, can be provided to DMIC IP RFTX — Radio Transmit Control Output PIO15/ADC1 18 IO GPIO15[1] ADC1 — ADC input 1 GPIO15 — General Purpose digital Input/Output 15 SPI1_SCK — Serial Peripheral Interface-bus 1, clock input/output ANA_COMP_OUT — Analog Comparator digital output PWM3 — Pulse Width Modulator output 3 PDM1_DATA — Pulse Density Modulation Data input from digital microphone (channel 1) I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain) RFRX — Radio Receiver Control Output FLASH_CSN 19 IO VDDE 20 P PIO17/ADC3 21 IO FLASH_CSN — Chip select of internal serial flash, active low. Requires external pull-up (a 100 kΩ pull-up resistor is recommended). VDDE — Supply voltage for IO GPIO17[1] ADC3 — ADC input 3 GPIO17 — General Purpose digital Input/Output 17 SPI1_MOSI — Serial Peripheral Interface-bus 1, master output slave input SWO — Serial Wire Output PWM6 — Pulse Width Modulator output 6 SPIFI_IO3 — Quad-SPI Input/Output 3 ISO7816_CLK — Clock output for ISO7816 interface CLK_OUT — Clock out n.c. 22 n.c. 23 PIO20/ACP 24 not connected not connected IO GPIO20[1] ACP — Analog Comparator Positive input GPIO20 — General Purpose digital Input/Output 20 IR_BLASTER — Infra-Red Modulator output PWM8 — Pulse Width Modulator output 8 RFTX — Radio Transmit Control Output SPIFI_IO2 — Quad-SPI Input/Output 2 USART1_TXD — Universal Synchronous/Asynchronous Receiver/Transmitter 1 - transmit data output K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 18 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 4. Pin descriptions Symbol Pin n.c. 25 TRST 26 G TRST — must be connected to GND RSTN 27 I RSTN — Reset Not input VBAT 28 P VBAT — Supply voltage DCDC input LX 29 VSS(DCDC) 30 FB 31 Type Default at reset Description not connected LX — DCDC filter G VSS(DCDC) — ground for DCDC section FB — DCDC Feedback input VDD(PMU) 32 XTAL_32K_P 33 crystal oscillator 32.768 kHz XTAL_32K_N 34 crystal oscillator 32.768 kHz VDD(RADIO) 35 P VSS(RF) 36 G VSS(RF) — RF ground RF_IO 37 IO RF_IO — RF antenna, RF pin which can be considered as RF Input/output. The radio transceiver is connected here. VSS(RF) 38 G VSS(RF) — RF ground n.c. 39 FLASH_RSTN 40 P Product data sheet VDD(RADIO) — supply voltage for radio section not connected exposed die pad K32W041A/K32W041AM VDD(PMU) — supply voltage for PMU section IO FLASH_RSTN — Reset signal for the internal flash device, active low. Requires external pull-up (a 100 kΩ pull-up resistor is recommended). G must be connected to RF ground plane [1] I: input at reset. [2] For standard operation (normal boot or ISP programming mode), this pin should be high during the release of reset. If there is no external driver to this pin, then the internal pull-up will keep this pin high. [3] ISP programming mode: leave pin floating high during reset to avoid entering UART programming mode or hold it low to program. [4] In ISP mode, it is configured to USART0_TXD. [5] In ISP mode, it is configured to USART0_RXD. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 19 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 7.3 Pin properties Fast capability Pin interrupt Open drain enable control Open drain enable at reset Passive pin filter after POR Slew rate after POR Pullup/ Pulldown enable after POR Default status after POR Pin No. Pullup/ pulldown selection after POR Pin properties Pin Name Table 5. 1 XTAL_P          2 XTAL_N          3 PIO0 H Y PU SS N N N Y N 4 PIO1 L Y PD SS N N N Y N 5 PIO2 L Y PD SS N N N Y N 6 PIO3 H Y PU SS N N N Y N 7 PIO4 H Y PU SS N N N Y N 8 PIO5/ISP_ENTRY H Y PU SS N N N Y N 9 PIO6 L Y PD SS N N N Y N 10 PIO7 L Y PD SS N N N Y N 11 PIO8/TXD0 H Y PU SS N N N Y N 12 PIO9/RXD0 H Y PU SS N N N Y N 13 PIO10 Hi-Z N[1] EPU[1] SS N N Y Y N EPU[1] SS N N Y Y N PU SS N N N Y N 14 PIO11 Hi-Z N[1] 15 PIO12/SWCLK H Y 16 PIO13/SWDIO H Y PU SS N N N Y N 17 PIO14/ADC0 H Y PU SS N N N Y N 18 PIO15/ADC1 H Y PU SS N N N Y N 19 PIO16/ADC2[2] H Y PU SS N N N Y N 20 VDDE          21 PIO17/ADC3 L Y PD SS N N N Y Y 22 PIO18/ADC4[4] L Y PD SS N N N Y Y 23 PIO19/ADC5[4] L Y PD SS N N N Y Y 24 PIO20/ACP L Y PD SS N N N Y Y 25 PIO21/ACM[4] H Y PU SS N N N Y Y 26 TRST[3] Hi-Z N      N  27 RSTN H Y PU     N  28 VBAT          29 LX          K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 20 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Fast capability Pin interrupt Open drain enable control Open drain enable at reset Passive pin filter after POR Slew rate after POR Default status after POR Pullup/ Pulldown enable after POR Pullup/ pulldown selection after POR Pin properties Pin Name Pin No. Table 5. 30 VSS(DCDC)          31 FB          32 VDD(PMU)          33 XTAL_32K_P          34 XTAL_32K_N          35 VDD(RADIO)          36 VSS_RF          37 RFIN          38 VSS_RF          39 n.c.          40 FLASH_RSTN[5]          [1] External Pullup required [2] On K32W041AM device, this requires external pull-up. [3] Tie to ground for functional mode [4] K32W041A device only. Otherwise n.c. [5] K32W041AM device only. Otherwise n.c. Table 6: Abbreviation used in the Table 6 Properties Abbreviation Default status after POR Hi-Z Product data sheet High impendence H High level L Low level Pullup/ pulldown Enable after Y Enabled POR N Disabled Pullup/ pulldown selection after PU Pullup POR PD Pulldown Slew rate after POR FS Fast slew rate SS Slow slew rate Passive Pin Filter after POR K32W041A/K32W041AM Descriptions N Disabled Y Enabled All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 21 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 6: Abbreviation used in the Table 6 Properties Abbreviation Open drain enable after reset Descriptions N Disabled Y Enabled Open drain enable control N Disabled[1] Y Enabled Pin interrupt N Yes Y No N Not support fast capability Y Support fast capability Fast capability [1] All PIO except 10/11 can do pseudo-open drain 8. Functional description 8.1 Application CPU The Arm Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is dedicated for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slave ports of the matrix to be accessed simultaneously by different bus masters. Note that while the AHB bus itself supports word, halfword, and byte accesses, not all AHB peripherals need or provide that support. APB peripherals are connected to the AHB matrix via two APB buses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller, and also for peripherals on the asynchronous bridge to have a fixed clock that does not track the system clock. Note that APB, by definition, does not directly support byte or halfword accesses. The CPU, AHB and DMA sub-systems are all synchronous and can operate at 48 MHz (FRO), 32 MHz (FRO), 32 MHz (XTAL), 24 MHz (FRO), 16 MHz (XTAL), 12 MHz (FRO). 8.1.1 Arm Cortex-M4 processor The Arm Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high performance and very low-power consumption. The Arm Cortex-M4 offers many features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. A 3-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 22 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 8.1.2 Memory Protection Unit The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data. Access to memory regions can be disabled and also be defined as read-only. It detects unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions, each of which is divided into eight sub-regions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will trigger memory management fault exception. 8.1.3 System Tick Timer (SysTick) The Arm Cortex-M4 core includes a System Tick timer (SysTick) that generates a dedicated SYSTICK exception. The clock source for the SysTick can be the system clock, or a divided version of this. 8.1.4 Nested Vector Interrupt controller (NVIC) The NVIC is an integral part of the Cortex-M4 that efficiently supports many interrupt sources with configurable priority levels. 8.1.4.1 Features • • • • • • • • Nested Vectored Interrupt Controller that is an integral part of the CPU Tightly coupled interrupt controller provides low interrupt latency Controls system exceptions and peripheral interrupts 56 vectored interrupts 8 programmable interrupt priority levels with hardware priority level masking Relocatable vector table using Vector Table Offset Register VTOR Software interrupt generation Support for Non-Maskable Interrupt (NMI) from any interrupt 8.1.4.2 General description The tight coupling of the NVIC to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.2 Memory The K32W041A/K32W041AM incorporates several distinct memory regions. The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus. The system memory map is shown in the following figure. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 23 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 32-bit Words 0xFFFF_FFFF 0xE00F_FFFF 0xE004_0000 0xE003_FFFF 0xE000_0000 32-bit Words Reserved (Do not access) 0x4001_FFFF Private Peripheral Bus (External) Private Peripheral Bus (Internal) Reserved (Do not access) 768 KBytes 0x4001_5000 Reserved (Do not access) 0x4001_4000 0x400B_1FFF IEEE 802.15.4 MAC 0x4001_3000 4 Kbytes 0x400B_1000 0x400B_0FFF 0x4001_2000 IEEE 802.15.4 MODEM 4 Kbytes Bluetooth LE LINK LAYER 64 Kbytes 0x400B_0000 0x400A_FFFF 0x4001_1000 0x400A_0000 0x4001_0000 Reserved (Do not access) 0x4000_F000 32-bit Words 0x4008_FFFF Hash 4 Kbytes SPI 1 4 Kbytes Reserved (Do not access) 0x4008_E000 0x4008_DFFF 0x4002_3000 0x4002_2FFF 4 Kbytes 0x4002_2000 0x4002_1FFF 0x4008_D000 0x4008_CFFF 0x4008_C000 0x4008_BFFF USART 1 4 Kbytes USART 0 4 Kbytes 0x4000_E000 0x4003_FFFF 0x4008_F000 0x4008_EFFF SPI 0 0x4002_1000 0x4002_0FFF 0x4002_0000 CTIMER 1 CTIMER 0 Asynchronous System Configuration 0x4000_D000 116 KBytes 0x4000_C000 4 KBytes 4 KBytes 4 KBytes 0x4000_B000 0x4000_A000 0x4000_9000 0x4000_8000 0x4008_B000 0x4008_AFFF DMIC APB Bridge 1 Memory Map 4 Kbytes 0x4000_7000 0x4008_A000 0x4008_9FFF 0x4008_9000 0x4008_8FFF 0x4008_8000 0x4008_7FFF ADC 4 Kbytes Reserved (Do not access) 4 Kbytes Reserved (Do not access) 0x4008_7000 0x4008_6FFF AES-256 0x4000_6000 0x4000_5000 0x4000_4000 4 Kbytes 0x4000_3000 4 Kbytes SPIFI Registers 4 KBytes General Purpose I/O 16 KBytes 0x4008_4000 4 KBytes 4 KBytes RFP MODEM 4 KBytes PMC 4 KBytes GPIO Group Interrupt (GINT0) GPIO Pattern Interrupt (PINT) IO CONFIG (IOCON) 4 KBytes 4 KBytes 4 KBytes INPUT MUX 4 KBytes Random Number Generator 4 KBytes PWM 4 KBytes RTC 4 KBytes WWDT 4 KBytes Flash Controller 4 KBytes Code Patch Module 4 KBytes IR Modulator 4 KBytes ISO7816 4 KBytes Reserved (do not access ) 4 KBytes I2C 1 4 KBytes I2C 0 4 KBytes 0x4000_1000 0x4000_0000 Synchronous System Configuration 4 KBytes 0x4008_5000 0x4008_4FFF Reserved (Do not access) Bluetooth LE MODEM Reserved (do not access) Reserved (do not access) 0x4000_2000 0x4008_6000 0x4008_5FFF DMA Controller 40 KBytes 0x4001_6000 4 KBytes 4 KBytes 4 KBytes APB Bridge 0 Memory Map 0x4008_3FFF 0x4008_0000 Reserved (Do not access) 0x4003_FFFF 0x4002_0000 0x4001_FFFF 0x4000_0000 128 KBytes APB Bridge 0 (Synchronous) 128 KBytes 0x103F_FFFF Reserved Quad SPIFI or External Flash 0x1000_0000 (Memory-Mapped Space) 0x0402_FFFF Reserved SRAM-CTRL1 0x0402_0000 8-bit Words 0x103F_FFFF APB Bridge 1 (Asynchronous) 3 MBytes 0x1010_0000 0x100F_FFFF 0x100F_0000 4 MBytes 0x0402_FFFF 0x0402_C000 0x0402_BFFF 0x0402_8000 0x0402_7FFF 64 KBytes (4*16KB) 0x0402_4000 0x0402_3FFF 0x0402_0000 Reserved 0x0401_5FFF 0x0400_0000 SRAM-CTRL0 (2*4KB, 2*8KB, 4*16KB) 88 KBytes 0x0401_5FFF 0x0401_5000 0x0401_4FFF 0x0401_4000 0x0401_3FFF Reserved (Do not access) 0x0401_2000 0x0401_1FFF 0x0301_FFFF ROM 128 KBytes 0x0300_0000 0x0401_0000 0x0400_FFFF Reserved (Do not access) 0x0400_C000 0x0400_BFFF 0x0400_8000 0x0400_7FFF 0x0009_FFFF 0x0000_0000 FLASH Memory 640 KBytes 0x0400_4000 0x0400_3FFF 0x0400_0000 Main Memory Map (AHB) Flash Block 15 64 KBytes SRAM 11 (16 KB) SRAM 10 (16 KB) ... SRAM 9 (16 KB) SRAM 8 (16 KB) SRAM 7 (4 KB) SRAM 6 (4 KB) SRAM 5 (8 KB) 0x1001_FFFF 0x1001_0000 0x1000_FFFF 0x1000_0000 Flash Block 1 64 KBytes Flash Block 0 64 KBytes SRAM 4 (8 KB) SRAM 3 (16 KB) External Flash Memory Map SRAM 2 (16 KB) SRAM 1 (16 KB) SRAM 0 (16 KB) SRAMs Memory Map 1) The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers. Fig 5. K32W041AM main memory map K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 24 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 32-bit Words 0xFFFF_FFFF Reserved (Do not access) 0xE00F_FFFF Private Peripheral Bus (External) 0xE004_0000 0xE003_FFFF 0xE000_0000 Private Peripheral Bus (Internal) 32-bit Words 0x4001_FFFF Reserved (Do not access) 768 KBytes 0x4001_5000 Reserved (Do not access) 0x4001_4000 0x400B_1FFF IEEE 802.15.4 MAC 0x4001_3000 4 Kbytes 0x400B_1000 0x400B_0FFF 0x4001_2000 IEEE 802.15.4 MODEM 0x400B_0000 0x400A_FFFF 4 Kbytes 0x4001_1000 Bluetooth LE LINK LAYER 0x400A_0000 64 Kbytes 0x4001_0000 Reserved (Do not access) 0x4000_F000 32-bit Words 0x4008_FFFF Hash 4 Kbytes SPI 1 4 Kbytes Reserved (Do not access) 0x4008_E000 0x4008_DFFF 0x4002_3000 0x4002_2FFF 4 Kbytes 0x4002_2000 0x4002_1FFF 0x4008_D000 0x4008_CFFF 0x4008_C000 0x4008_BFFF USART 1 4 Kbytes USART 0 4 Kbytes 0x4000_E000 0x4003_FFFF 0x4008_F000 0x4008_EFFF SPI 0 0x4002_1000 0x4002_0FFF 0x4002_0000 0x4000_D000 116 KBytes 0x4000_C000 CTIMER 1 4 KBytes CTIMER 0 4 KBytes Asynchronous System Configuration 4 KBytes 0x4000_B000 0x4000_A000 0x4000_9000 0x4000_8000 0x4008_B000 0x4008_AFFF DMIC APB Bridge 1 Memory Map 4 Kbytes 0x4000_7000 0x4008_A000 0x4008_9FFF ADC 0x4008_9000 0x4008_8FFF 0x4008_8000 0x4008_7FFF 0x4008_7000 0x4008_6FFF 0x4000_6000 4 Kbytes 0x4000_5000 Reserved (Do not access) 4 Kbytes Reserved (Do not access) 4 Kbytes AES-256 0x4000_4000 0x4000_3000 SPIFI Registers 4 KBytes General Purpose I/O 16 KBytes 0x4008_4000 4 KBytes 4 KBytes RFP MODEM 4 KBytes PMC 4 KBytes GPIO Group Interrupt (GINT0) GPIO Pattern Interrupt (PINT) IO CONFIG (IOCON) 4 KBytes 4 KBytes 4 KBytes INPUT MUX 4 KBytes Random Number Generator 4 KBytes PWM 4 KBytes RTC 4 KBytes WWDT 4 KBytes Flash Controller 4 KBytes Code Patch Module 4 KBytes IR Modulator 4 KBytes ISO7816 4 KBytes Reserved (do not access ) 4 KBytes I2C 1 4 KBytes I2C 0 4 KBytes 0x4000_1000 0x4000_0000 Synchronous System Configuration 4 KBytes 0x4008_5000 0x4008_4FFF Reserved (Do not access) Bluetooth LE MODEM Reserved (do not access) Reserved (do not access) 0x4000_2000 4 Kbytes 0x4008_6000 0x4008_5FFF DMA Controller 40 KBytes 0x4001_6000 4 KBytes 4 KBytes 4 KBytes APB Bridge 0 Memory Map 0x4008_3FFF 0x4008_0000 Reserved (Do not access) 0x4003_FFFF 0x4002_0000 0x4001_FFFF 0x4000_0000 APB Bridge 1 (Asynchronous) 128 KBytes APB Bridge 0 (Synchronous) 128 KBytes 0x10FF_FFFF Reserved Quad SPIFI or External Flash 0x1000_0000 (Memory-Mapped Space) 0x0402_FFFF Reserved SRAM-CTRL1 16 MBytes 0x0402_FFFF 0x0402_C000 0x0402_BFFF 0x0402_8000 0x0402_7FFF 64 KBytes (4*16KB) 0x0402_0000 0x0402_4000 0x0402_3FFF 0x0402_0000 Reserved 0x0401_5FFF 0x0400_0000 SRAM-CTRL0 (2*4KB, 2*8KB, 4*16KB) 88 KBytes 0x0401_5FFF 0x0401_5000 0x0401_4FFF 0x0401_4000 0x0401_3FFF Reserved (Do not access) 0x0401_2000 0x0401_1FFF 0x0301_FFFF ROM 128 KBytes 0x0300_0000 0x0401_0000 0x0400_FFFF Reserved (Do not access) 0x0400_C000 0x0400_BFFF 0x0400_8000 0x0400_7FFF 0x0009_FFFF 0x0000_0000 FLASH Memory 640 KBytes 0x0400_4000 0x0400_3FFF 0x0400_0000 Main Memory Map (AHB) SRAM 11 (16 KB) SRAM 10 (16 KB) SRAM 9 (16 KB) SRAM 8 (16 KB) SRAM 7 (4 KB) SRAM 6 (4 KB) SRAM 5 (8 KB) SRAM 4 (8 KB) SRAM 3 (16 KB) SRAM 2 (16 KB) SRAM 1 (16 KB) SRAM 0 (16 KB) SRAMs Memory Map 1) The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers. Fig 6. K32W041A main memory map K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 25 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 8.2.1 SRAM The main SRAM is comprised of up to a total 152 KB on-chip static RAM memory. The main SRAM is implemented as several SRAM instances to allow for more control of power usage when less SRAM is required (2 4 KB instances, 2 8 KB instances and 8 16 KB instances). Each SRAM has a separate clock control and power switch. See Table 2 for SRAM size of each parts. 8.2.2 SRAM usage Although always contiguous on all K32W041A/K32W041AM devices, the SRAM instances are divided between two AHB matrix ports. This allows user programs to potentially obtain better performance by dividing RAM usage among the ports. For example, simultaneous access to SRAM0 by the CPU and SRAM1 by the system DMA controller does not result in any bus stalls for either master. Generally speaking, the CPU will read or write all peripheral data at some point, even when all such data is read from or sent to a peripheral by DMA. So, minimizing stalls is likely to involve putting data to/from different peripherals in RAM on each port. Alternatively, sequences of data from the same peripheral could be alternated between RAM on each port. This could be helpful if DMA fills or empties a RAM buffer, then signals the CPU before proceeding on to a second buffer. The CPU would then tend to access the data while the DMA is using RAM on the other port. 8.2.3 FLASH The K32W041A/K32W041AM embeds flash for code and data storage. It is accessed through a flash controller that simplifies the use of the flash. • Embedded 640 KB of Flash, an additional 1 MB Data Flash is available on K32W041AM • Flash sector is 512 bytes • 100 kcycles page endurance guaranteed • Software is provided to manage data storage in the flash and provides wear leveling features • Data retention 10 years 8.2.4 AHB multilayer matrix The K32W041A/K32W041AM uses a multi-layer AHB matrix to connect the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters. 8.3 System clocks The following system clocks are used to drive the on-chip subsystems: • The low power wake timers are driven by a low frequency 32 kHz clock. • The main digital systems are driven from a high frequency clock source. • The system controller state machines are driven from a 1 MHz FRO. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 26 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM These system clocks are used within the device for the digital functionality. Some functional blocks can also source a clock from the interface and this is explained in when the digital blocks are presented. 8.3.1 32 kHz clock There are two possible sources for the 32 kHz clock. There is an internal FRO that gives 32.768 kHz with accuracy of ±2%; this requires no external components. A 32 kHz XTAL is also supported. The XTAL is connected to XTAL_32K_P and XTAL_32K_N pins. The cell has configurable internal capacitors and therefore, except for the XTAL itself, no other external components are typically required. Very accurate XTALs are available. This option is recommended for accurate timings. 8.3.2 High frequency system clock There are two possible sources for the high-speed system clock. There is an internal high speed FRO that supports clock frequencies of 48 MHz, 32 MHz, 24 MHz and 12 MHz. This does not require any external components and has an accuracy of ±2%. A 32 MHz XTAL is also supported. The cell has configurable internal capacitors and therefore, except for the XTAL itself, no other external components are typically required. An accurate XTAL must be used for the radio operation. The system clock can be chosen to be sourced from the FRO or XTAL and this choice is separate to the operation of the radio using the XTAL clock. When selecting the XTAL as the source for the high frequency system clock, it is possible to select 32 MHz or 16 MHz. The high frequency system clock is used for the processor and the system buses. 8.3.3 1 MHz FRO A 1 MHz FRO is used by the core system controller and the state machine involved in the device start-up and shut-down. High accuracy of this clock is not necessary and it has a tolerance of ±15%. 8.4 Resets and brownout A system reset initializes the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the K32W041A/K32W041AM goes through is as follows. When power is first applied or when the external reset is released, the FRO1MHz is started, then the DCDC converter is started. After that, the system power domain is started. When these domains are stable, the flash and main core domain LDOs are enabled. When these are stable, the high speed FRO is enabled and the elements necessary for CPU operation are enabled. Configuration data is read from the flash and the boot process begins. Depending on the configuration and flash contents then the application may be executed, or the device may enter In System Programming (ISP) mode. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 27 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM The initial power-up sequence will not begin if the device power is too low; in this case the Power-on reset module will keep the device in a reset state until there is sufficient voltage. Additionally, the brown-out detect block will keep the device in reset until a safe operating voltage is reached. Once the device is operating, the brownout module can be used to interrupt the processor in case operating voltage changes occur. This allows software to manage a clean response to the event. The brownout threshold is configurable to support a range of applications. Several resets are supported that can affect all or most of the device. These are presented in the following sub-sections. 8.4.1 External reset An external reset is generated by a low level on the RSTN pin. Reset pulses longer than the minimum pulse width will generate a reset during active or power-down modes. Shorter pulses are not guaranteed to generate a reset. The K32W041A/K32W041AM is held in reset while the RSTN pin is low. When the applied signal reaches the reset threshold voltage on its positive edge, the internal reset process starts. The K32W041A/K32W041AM has an internal pull-up resistor connect to the RSTN pin. This pin is the input for an external reset only. 8.4.2 Software reset A system reset can be triggered at any time through software control, causing a full chip reset and invalidating the RAM contents. For example, this can be executed within a user's application upon detection of a system failure. 8.4.3 Watchdog timer The watchdog timer can cause a full chip reset if it reaches its timeout point and it is configured to generate a reset, rather than an interrupt. In normal operation, the software will periodically service the watchdog to prevent this timeout occurring. Typically, a watchdog timeout indicates an unexpected lock-up within the system. 8.4.4 Arm system reset The CPU can cause a reset by requesting a System reset. This reset causes a reset of the CPU and the core digital functionality, digital peripherals and the 32 MHz XTAL. The power domains within the device, such as the DCDC converter and core LDO are unaffected so that the CPU will restart quicker than if a software reset is performed. 8.5 System configuration (SYSCON) The device has many system level features which support the operation of the device, such as clock control. In addition there is functionality provided to allow the software to manage the system, such as controlling wake-up sources. These features include: • • • • K32W041A/K32W041AM Product data sheet System and bus configuration Clock select and control Reset control Wake-up control All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 28 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • Brown-out (BOD) configuration • High-accuracy frequency measurement function for on-chip and off-chip clocks, using a selection of on-chip clocks as reference clock • Device ID register 8.6 Power management This section provides an overview of power related information about K32W041A/K32W041AM devices. These devices include a variety of adjustable regulators, power switches, and clock switches to allow fine tuning power usage to match requirements at different performance levels and reduced power modes. All devices include an on-chip API in the boot ROM to adjust power consumption in reduced power modes, and provide entry to those modes. 8.6.1 Power supply The device is powered by VBAT, which requires a 10 F decoupling capacitor to ground. To give efficient operation, the device has an on-chip DCDC buck converter; it is turned on when the device is in active and sleep modes and, using external connections, it provides the supply voltage to the PMU and Radio. The converter is powered from VBAT and the external output of the DCDC converter, FB, requires a 10 F decoupling capacitor to ground. For the DCDC converter to function correctly, a filtered version of FB must be input to LX, This is achieved with a 2.2 H inductor. The DCDC converter output, FB, must be routed to device pins VDD(radio) and VDD(pmu) so that the whole system is powered correctly. The two VDD power inputs supply the power to most of the device, either directly or via on-chip regulators and power switches. These are used to manage power consumption based on the required mode of operation. There is an always-on power domain which is powered by VBAT and includes the core functions to control device start-up and the functionality required in the very low power modes. This domain always has power as long as sufficient voltage is supplied to VBAT. A further domain is important for supporting the power down mode. It includes the RTC, wake-up timer and some clock, reset and wakeup control. This domain is always has power as long as sufficient voltage is supplied to VDD and provided that the device is not in deep power-down mode. See Figure 10 “Application diagram – battery powered solution” for the power connections. 8.6.2 Power modes A variety of power modes are supported for the optimization of power consumption, including active, sleep, deep-sleep, power-down and deep power-down. Upon power-up or reset, the device enters active mode. After processing is complete, the software puts the chip into sleep mode or power-down mode, to save power consumption. The device is woken up either by a reset or an interrupt trigger like a GPIO interrupt, timer timeout, or other wake-up sources. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 29 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM An API is provided so that software can easily use the power modes. The API performs all the configuration necessary for the different power modes, including setting power domains to the correct state and voltage, shutting down the flash controller safely, enabling the wake up mechanisms. The following sections introduces modes supported in order from highest to lowest power consumption. 8.6.2.1 Active mode The part is in active mode after a Power-On Reset (POR) and when it is fully powered and operational after booting. 8.6.2.2 Sleep mode Sleep mode saves a significant amount of power by stopping CPU execution without affecting peripherals or requiring significant wake-up time. The sleep mode affects the relevant CPU only. The clock to the core is shut off. Peripherals and memories are active and operational. 8.6.2.3 Deep-sleep mode Deep-sleep mode is highly configurable and can reduce power consumption, compared to Sleep mode by turning off more functions. Additionally, core voltages are reduced to save power. Wake-up times are longer than for Sleep mode due to the time needed to restart the functions. The clock to the CPU is shut down. The clock to the peripherals may also be disabled. The SRAM and registers maintain their internal states. Entry to these modes can be accomplished by the CPU using the power profiles API, selected peripherals can be left running for safe operation of the part (e.g. RTC, WWDT and BOD, depending upon the mode). The flash is placed in standby mode and system clocks may be disabled. 8.6.2.4 Power-down mode In Power-down mode the core of the device and the flash is powered down, most clocks are stopped. Power consumption is very low with the cost of a longer wake-up time. The processor and most digital peripherals are powered off. USART0, SPI0 and I2C0 can operate with limited functionality in power down mode and have the ability to wake the device. Low power sleep timers can be enabled to generate a wake-up at a certain time in the future. Wakeup is also possible by GPIOs, analog comparator, RTC, and BOD VBAT. All, or part, of the SRAM can be optionally retained at the cost of extra current consumption. 8.6.2.5 Deep power-down mode Deep Power-down mode shuts down virtually all on-chip power consumption, but requires a significantly longer wake-up time. For maximal power savings, the entire system (CPU, memories and all peripherals) is shut down except for the PMU. Wake-up is possible from reset, and optionally GPIO. On wake-up, the part reboots. 8.6.2.6 Wake-up sources All interrupts to the CPU can be used as a wake-up from sleep. The following table shows the possible wake-up sources from deep-sleep, power-down and deep power-down. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 30 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 7. Power mode wake-up sources Wake-up source Deep sleep WWDT Yes BOD Yes GINT Yes IR Modulator Yes PINT [3:0] Yes SPIFI Yes TIMER [1:0] Yes USART0 Yes USART1 Yes I2C0 Yes I2C1 Yes SPI0 Yes SPI1 Yes PWM[11:0] Yes I2C2 Yes RTC Yes ADC_SEQA Yes ADC_THCMP_OVR Yes DMIC Yes Power-down Yes Yes Yes Yes Yes HWVAD Yes ISO7816 Yes ANA_COMP Yes Yes[1] WAKE_UP_TIMER[1:0] Yes Yes GPIO Yes Yes [1] Deep power-down Yes K32W041A device only. 8.7 Digital I/O 8.7.1 Features • All 22 digital I/Os on K32W041A and 18 digital IOs on K32W041AM can be configured on GPIO ports • • • • GPIO pins can be configured as input or output by software All GPIO pins default to inputs with interrupt disabled at reset Pin registers allow pins to be sensed and set individually Group Interrupt to generate a single interrupt from AND or OR function of the digital IOs. • Pin/ Pattern Interrupt allowing 4 IOs to be able to create an interrupt based on pin values or a combination of the values • 2 IOs supporting true I2C mode or standard digital IO with configurable pull-up and drive strength K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 31 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • 20 standard IO cells on K32W041A and 16 standard IO cells on K32W041AM are configurable for drive strength, pull-up resistor, pull-down resistor, pseudo open-drain 8.7.2 General description The digital IOs have multiplexed functionality, supporting one or more digital peripherals and also a basic General Purpose IO function (GPIO). In GPIO mode it is possible to configure the IO as an input or as an output. As an input it is possible to configure IO wake a device from powerdown and deep powerdown. The input value can also be read. Using the Pin Interrupt/ Pattern Match function (PINT) it is possible to configure up to 4 digital IOs to be able to generate an interrupt based for active high or low functionality. Alternatively the 4 IOs can be combined in various ways to generate an interrupt. These interrupt are able to wake the CPU from sleep mode. Additionally, a Group Interrupt function (GINT) allows any selection of up to all IOs to be combined into a AND or OR function in order to generate the group interrupt. The polarity of each IO used in the function can be configured. Two of the digital IO cells support true I2C functionality and standard digital IO functionality, These support a pull-up resistor, drive strength control. The other digital IOs cells are configurable to support drive strength options, pull-up or pull-down functions and the ability to operate in a pseudo open-drain mode. The output value of each IO can be held during a power-down cycle if required. Two DIO pins can optionally be used to provide control signals for RF circuitry (e.g. switches and PA) in high-power range extenders. PIO4_8_10_14_20/RFTX is asserted when the radio is in the transmit state and similarly, PIO5_11_15_21/RFRX1 is asserted when the radio is in the receiver state. From software and test perspective, it is recommended to PIO4 or PIO20 for RFTX and PIO5D or PIO21 for RFRX. 8.8 DMA controller The DMA controller allows peripheral to memory, memory to peripheral, and memory single source and destination. • 19 channels which are connected to peripheral DMA requests. These come from the USART, SPI-bus, I2C-bus, PDM and SPIFI interfaces. Any otherwise unused channels can also be used for functions such as memory-to-memory moves. • DMA operations can be triggered by on-chip or off-chip events. Each DMA channel can select one trigger input from 18 sources. Trigger sources include ADC interrupts, timer interrupts, pin interrupts, and the SCT DMA request lines • • • • • 1. Priority is user selectable for each channel (up to eight priority levels) Continuous priority arbitration Address cache with four entries (each entry is a pair of addresses) Efficient use of data bus Supports single transfers up to 1,024 words PIO21 is not available on K32W041AM. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 32 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • Address increment options allow packing and/or unpacking data 8.9 PWM The PWM module supports the generation of up to 10 PWM waveforms on K32W041A and up to 9 waveforms on K32W041AM, each with its own prescaler, to support a range of applications. • 1 PWM module with – 10 independent outputs on K32W041A – 9 independent outputs on K32W041AM • Option for 1 channel to drive up to all (10 on K32W041A and 9 on K32W041AM) outputs simultaneously • • • • Programmable 10-bit prescaler for each channel 16-bit auto-reload down counter for each channel 16-bit compare register for each channel (toggling point in 1 full period) Predictable PWM initial output state for each channel (configurable initial waveform polarity – HIGH or LOW) • Configurable level (HIGH or LOW) of PWM output when PWM is disabled • Programmable overflow interrupt generation for each channel 8.10 Timers Within the K32W041A/K32W041AM there are several different timer blocks available. These timers are used in different ways as outlined here. • Counter/Timers: The two blocks are the main functional timers for the application, running off a high speed clock and able to create interrupts from match registers. • Watchdog Timer: slow speed timer with the ability to interrupt the processor or cause device reset. Often used to identify when application software is locked up or taking too long. • Real-time clock: this block has two timers real time clock and high-resolution/wake-up timer. The real time clock has a 1Hz clock is often run continually as a clock. The high-resolution/ wake up timer is a simple counter that can generate an input to wake the device from sleep, deep-sleep and power-down. Maximum timeout is 64 seconds. • Low Power Wake-up Timers: this block has two timers running on a 32kHz clock. Predominantly used to wake the device from power-down, with a maximum time period in excess of one year. • Tick Timer: within the processor this is often used for a regular heart beat to trigger software scheduling. The device has different power modes and the following table shows when the timers can be used. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 33 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 8. Allowed timer usage in different power modes Timer block Active mode Sleep mode Deep-sleep mode Power-down mode Counter/timer X X X Watchdog timer X X X Real-time clock X X X X Low Power wake-up timers X X X X Tick timer X X X Deep power-down mode 8.10.1 Counter/Timers There are two Counter/Timer blocks that support a range of functions such as timers or counting events from an IO pin. The match registers allow for configurable interrupts when the counter reaches certain values. The match events can also be indicated on device pins. 8.10.1.1 Features • 2 counter/timer instances, CT32B0 and CT32B1 • Each is a 32-bit counter/timer with a programmable 32-bit prescaler. Both timers include external capture and match pin connections • Counter or timer operation • For each timer, up to 2 32-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt • The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation • For each timer with pin connections, up to 2 external outputs corresponding to match registers with the following capabilities: Remark: For the K32W041AM device, one timer has only one external match output and the other timer has two external match outputs. For K32W041A device, both timers have two external match outputs. – Set LOW on match – Set HIGH on match – Toggle on match – Do nothing on match – Two match registers can be used to trigger DMA transfers. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 34 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 8.10.1.2 General description Each counter/timer is designed to count cycles of the APB bus clock or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. Capture inputs: The capture signal can be configured to load the capture register with the value in the counter/timer and optionally generate an interrupt. The capture signal is generated by one of the pins with a capture function. Each capture signal is connected to one capture channel of the timer. The counter/timer block can select a capture signal as a clock source instead of the APB bus clock. Match outputs: When a match register equals the Timer Counter (TC), the corresponding match output can either toggle, go LOW, go HIGH, or do nothing. Applications • • • • Interval timer for counting internal events Pulse Width Modulator via match outputs Pulse Width Demodulator via capture input Free running timer 8.10.2 Watchdog timer The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state. When enabled, a watchdog reset is generated if the user program fails to feed (reload) the Watchdog within a predetermined amount of time. When a watchdog window is programmed, an early watchdog feed is also treated as a watchdog event. This allows preventing situations where a system failure may still feed the watchdog. For example, application code could be stuck in an interrupt service that contains a watchdog feed. Setting the window such that this would result in an early feed will generate a watchdog event, allowing for system recovery. • Internally resets chip if not reloaded during the programmable time-out period • Optional windowed operation requires reload to occur between a minimum and maximum time-out period, both programmable • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out • Clock fed to the watchdog function is selectable from 32 kHz clock, 32 MHz clock and FRO 1 MHz clock, This selected clock can be optionally pre-scaled before input to the block. • Programmable 24-bit timer with internal fixed pre-scaler • Selectable time period • “Safe” watchdog operation. Once enabled, requires a hardware reset or a watchdog reset to be disabled K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 35 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • Incorrect feed sequence causes immediate watchdog event if enabled • The watchdog reload value can optionally be protected such that it can only be changed after the “warning interrupt” time is reached • Flag to indicate watchdog reset • The watchdog timer can be configured to run in Deep-sleep mode • Debug mode 8.10.3 Real-Time Clock (RTC) The Real-Time Clock provides two timers that are typically used as a Real-Time clock counter and a higher-resolution timer. 8.10.3.1 Features • The RTC has the following clock inputs generated from the 32 kHz FRO or 32 kHz XTAL: – 1 Hz clock for RTC timing – 1 kHz clock for high-resolution RTC timing • 32-bit, 1 Hz RTC counter and associated match register for alarm generation • Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution giving a maximum time-out period of over one minute. • RTC alarm and high-resolution/wake-up timer time-out each generate independent interrupt requests. Either time-out can wake up the part from Low-power modes (Sleep mode, Deep-sleep mode or Power-down mode) 8.10.3.2 General description The RTC contains two timers: • Real time clock The real-time clock is a 32-bit up-counter which can be cleared or initialized by software. Once enabled, it counts continuously at a 1 Hz clock rate as long as the device is powered up and the RTC remains enabled. The main purpose of the RTC is to count seconds and generate an alarm interrupt to the processor whenever the counter value equals the value programmed into the associated 32-bit match register. If the part is in one of the reduced-power modes (Sleep, Deep-sleep, Power-down) an RTC alarm interrupt can also wake up the part to exit the Power mode and begin normal operation. • High-resolution/wake-up timer The time interval required for many applications, including waking the part up from a Low-power mode, will often demand a greater degree of resolution than the one-second minimum interval afforded by the main RTC counter. For these applications, a higher frequency secondary timer has been provided. This secondary timer is an independent, stand-alone wake-up or general-purpose timer for timing intervals of up to 64 seconds with approximately one millisecond of resolution. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 36 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM The high-resolution/wake-up timer is a 16-bit down counter which is clocked at a 1 kHz rate when it is enabled. Writing any non-zero value to this timer will automatically enable the counter and launch a countdown sequence. When the counter is being used as a wake-up timer, this write can occur just prior to entering a reduced power mode. When a starting count value is loaded, the high-resolution/wake-up timer will turn on, count from the pre-loaded value down to zero, generate an interrupt and/or a wake-up command, and then turn itself off until re-launched by a subsequent software write. 8.10.4 Low Power Wake-up Timers Two low power wake-up timers are available on the K32W041A/K32W041AM, driven from the 32 kHz internal clock. They may run in power-down mode when the majority of the rest of the device is powered down, to time low-power periods or other long period timings that may be required by the application. The wake-up timers do not run during deep power-down and may optionally be disabled in power-down mode through software control. When a wake-up timer expires, it typically generates an interrupt; if the device is in deep sleep or power down mode then the interrupt may be used as an event to end the low power mode. Features include: • 28-bit and 41-bit down counter • Optionally runs during power-down periods • Clocked by 32 kHz system clock; either 32 kHz RC oscillator or 32 kHz XTAL oscillator • Time-out period in excess of 1 year is possible A wake-up timer consists of a 28-bit or 41-bit down counter clocked from the selected 32 kHz clock. An interrupt or wake-up event can be generated when the counter reaches zero. On reaching zero, the counter will continue to count down until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wake-up event is required, the timer interrupt should be enabled before loading the count value for the period. Once the counter value has been loaded and the counter started, the count-down begins. The counter can be stopped at any time through software control - the counter will remain at the value that it contained when it was stopped and no interrupt will be generated. The status of the timers can be read to indicate if the timers are running and/or have expired; this is useful when the timer interrupts are masked. 8.11 USART There are 2 USART interfaces to provide Synchronous and Asynchronous serial communications with external devices. A range of features and flexible baud rate control supports a range of applications. • 2 USART interfaces, 1 with flow control • 7, 8 or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option • Multiprocessor/multidrop (9-bit) mode with software address compare • RS-485 transceiver output enable • Parity generation and checking: odd, even, or none K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 37 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • • • • Software selectable oversampling from 5 to 16 clocks in asynchronous mode • • • • • Break generation and detection One transmit and one receive data buffer The USART function supports separate transmit and receive FIFO with 4 entries each RTS/CTS supported on one USART. This allows for hardware signaling for automatic flow control. Software flow control can be performed using delta CTS detect, transmit disable control, and any GPIO as an RTS output Receive data is 2 of 3 sample "voting". status flag set when one sample differs Built-in baud rate generator with auto-baud function A fractional rate divider is shared among all USARTs Interrupts available for FIFO receive level reached, FIFO transmit level reached, receiver idle, change in receiver break detect, framing error, parity error, overrun, underrun, delta CTS detect, and receiver sample noise detected • Loopback mode for testing of data and flow control • USART transmit and receive functions can operate with the system DMA controller • Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC oscillator as the USART clock. This mode can be used, with USART0, while the device is in Power-down mode and can wake-up the device when a character is received 8.12 Serial Peripheral Interfaces-bus (SPI-bus) The SPI-bus allows high-speed synchronous data transfer between the K32W041A/K32W041AM and peripheral devices. Two SPI-buses are supported which can independently operate as a master or slave to support a range of system configurations. • 2 SPI-bus interfaces: SPI0 and SPI1 can be both configured as master or slave interfaces • Data transmits of 1 to 16 bits supported directly. Larger frames supported by software • The SPI-bus function supports separate transmit and receive FIFOs with 4 16-bit entries each • Support DMA transfers: SPIn transmit and receive functions can operate with the system DMA controller • Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI-bus memory • Up to 3 slave select input/outputs with selectable polarity and flexible usage Remark: Texas Instruments SSI and National Microwire modes are not supported. 8.13 I2C-bus interfaces The K32W041A/K32W041AM supports the industry standard I2C-bus, a 2-wire synchronous serial interface that can operate as a master or slave, providing a simple and efficient method of data exchange between devices. The system uses serial data and clock to perform bidirectional data transfers. • 2 I2C-bus interfaces, one with I2C compliant IO cells K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 38 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • Independent master, slave and monitor functions • Bus speeds supported: – Standard mode, up to 100 kbits/s – Fast-mode, up to 400 kbits/s – Fast-mode Plus, up to 1 Mbits/s (on specific I2C-bus pins) – High speed mode, 3.4 Mbits/s as a slave only (on specific I2C-bus pins) • Supports both multi-master and multi-master with slave functions • Multiple I2C-bus slave addresses supported in hardware • One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C-bus addresses • • • • 10-bit addressing supported with software assist Supports System Management Bus (SMBus) Separate DMA requests for master, slave, and monitor functions No chip clocks are required in order to receive and compare an address as a slave, so this event can wake up the device from Power-down mode with I2C0 • Automatic modes optionally allow less software overhead for some use cases 8.14 DMIC interface The DMIC subsystem supports mono or dual-channel digital PDM microphones Additionally, hardware voice activity detector (HWVAD), is provided to support low power voice applications. • DMIC (dual/stereo digital microphone interface) – PDM (Pulse-Density Modulation) data input for left and/or right channels on 1 or 2 buses. – Flexible decimation. – 16 entry FIFO for each channel. – DC blocking or unaltered DC bias can be selected. – Data can be transferred using DMA • HWVAD (Hardware-based voice activity detector): – Optimized for PCM signals with 16 kHz sampling frequency. – Configurable detection levels. – Noise envelope estimator register output for further software analysis 8.15 12-bit general purpose ADC The K32W041A/K32W041AM has a 12-bit, multi-channel, general purpose ADC. Sampling is controlled by a configurable sequencer that can support a range of sampling options. With connections to the DMA sub-system complex applications using the ADC are possible. • Conversion rate 190 ksamples/s (Max.) for 12-bit resolution • Single-ended analog input mode K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 39 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • 8 input channels on K32W041A, (6 external, 1 internal temperature sensor, 1 internal supply voltage monitoring); 5 input channels on K32W041AM, (3 external, 1 internal temperature sensor, 1 internal supply voltage monitoring) • • • • • • • • • • Selectable (max 32 clock-cycles) sampling time Power-down mode performing minimal power dissipation Peak to peak single-ended input range from 0 V to 3.6 V INL (Integral Non Linearity), full scale: 1.1 LSB typ. DNL (Differential Non Linearity): 0.85 LSB typ. ENOB (Effective Number Of Bit), 10% - 90% full scale, Fin = 25 kHz: 10.5 typ. SNR (Signal to Noise Ratio), Fin = 25 kHz: 65 dB typ. THD (Total Harmonic Distortion), 10% - 90% full scale, Fin = 25 kHz: 70 dB typ. SFDR (Spurious Free Dynamic Range), 10% - 90% full scale, Fin = 25 kHz: 75 dB typ. A sequencer to control use of ADC – Sequencer triggered by software or PINT function, or PWM signal – Sample any combination of the ADC channels – Digital comparator function with two pairs of configurable low and high thresholds – Associate each ADC channel to one pair of low/high thresholds – Single step and bursts – Interrupts for data available, data overrun, threshold events 8.16 Temperature sensor The K32W041A/K32W041AM provides a temperature sensor which is connected to one of the ADC channels. It provides an application with a temperature measurement. • calibrated to give accurate measurement • simple to use with software driver 8.17 Analog comparator The K32W041A/K32W041AM provides an analog comparator that can compare two device pins or one pin against an internal reference. • • • • • • 1 analog comparator with 2 external inputs The negative source of the comparator can be set to an internal bandgap reference Can be enabled/disabled to save power Can be used to wake-up the device, from sleep, deep-sleep or power-down Rail to rail inputs The comparator provides 2 power modes to compromise between speed and power consumption • The external pins can be routed to the + or  inputs of the comparator • Hysteresis can be set to 0 mV or 40 mV • The comparator output can be routed to an GPIO K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 40 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM On K32W041AM device, the comparator has only one external input which has to be routed to the positive input of the comparator. It can be compared to the internal bandgap reference. It is not possible to wake from power-down on this variant because the internal bandgap is not powered in the power-down state. 8.18 Infra-Red Modulator The Infra-red modulator can generate patterns suitable to drive an infra-red source. The modulator is configurable to support several different IR protocols. • • • • • 1 Infra-Red modulator instance Support Phillips RC5, RC6 & RCMM protocols Support SONY SIRC protocol Support 36 kHz sub-carrier frequency Support 40 kHz sub-carrier frequency 8.19 Serial Wire Debug (SWD) Debug and trace functions are integrated into the Arm Cortex-M4. Serial wire debug and trace functions are supported. The Arm Cortex-M4 is configured to support up to 8 breakpoints and 4 watch points. 8.19.1 Features • Supports Arm Serial Wire Debug mode for Cortex-M4 • Trace port provides Cortex-M4 CPU instruction trace capability. Output via a serial wire viewer • Direct debug access to all memories, registers, and peripherals • No target resources are required for the debugging session • Breakpoints: the Cortex-M4 includes 8 instruction breakpoints that can also be used to remap instruction addresses for code patches. Two literal comparators that can also be used to remap addresses for patches to literal values. • Watchpoints: the Cortex-M4 includes 4 data watchpoints that can also be used as triggers • Instrumentation Trace Macrocell allows additional software controlled trace for the Cortex-M4 8.19.2 Basic configuration The serial wire debug pins are enabled by default. 8.20 Wireless transceiver The wireless transceiver comprises a 2.4 GHz radio that supports both the Bluetooth Low Energy and IEEE 802.15.4 radio standards. There is a IEEE802.15.4 compliant modem and baseband processor. There is also a Bluetooth Low Energy 5.0 compliant modem and link layer. These blocks, with IEEE 802.15.4 and Bluetooth Low Energy 5.0 protocol software provided as libraries, implement the standards-based wireless transceiver that transmits and receives data over the air in the unlicensed 2.4 GHz band. To support the IEEE 802.15.4 protocol an AES engine is also provided, in the K32W041A/K32W041AM, K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 41 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM to accelerate the required encryption features. The Bluetooth Low Energy Link layer block contains an internal AES engine to support the requirements of the encryption required for the Bluetooth Low Energy 5.0 standard. RADIO AGC IF AMP LNA ADC CALIBRATION TRANSFORMER REFERENCE AND BIAS DAC PA Fig 7. DIVIDER BY 2 SIGMA DELTA PLL Radio architecture The main features of the radio are: • Single ended shared RF input for receive and transmit operations • Each power domain has its own independent LDO • A low noise PLL serving either the receiver or the transmitter. A 2-point modulation is used in TX The single-ended antenna is connected to the integrated transformer. The integrated transformer has 2 outputs, one for the receive chain one for the TX chain. The RX chain consists in an LNA, a mixer, an IF amplifier, an anti-aliasing filter and an ADC. The LNA has some gain steps that are controlled by the AGC system. The IF amplifier is the first gain stage after the mixer and provides some filtering. It has some gain steps that are controlled by the AGC system. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 42 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM The anti-aliasing filter is the main channel filter. It also provides some gain steps that are controlled by the AGC system. On the transmit side, the PA is built as 2 main blocks: one containing the RF pre-driver, one containing the power amplifier. The power amplifier has its own high power LDO. The 32 MHz crystal oscillator provides the frequency synthesizer with a reference frequency. The synthesizer contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase-Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop characteristic. The radio when enabled is automatically calibrated for optimum performance. 2 DIO pins can optionally be used to provide control signals for RF circuitry (e.g. switches and PA) in high-power range extenders. DIOx/RFTX is asserted when the radio is in the transmit state and similarly, DIOy/RFRX is asserted when the radio is in the receiver state. 8.20.1 Radio features • • • • • • • • • • • • • • 50  single ended input (no external balun required) Flexible output power up to +15 dBm, programmable with 46 dB range Bluetooth Low Energy Sensitivity level -97 dBm IEEE 802.15.4 Sensitivity level -100 dBm Excellent linearity and phase noise to improve co-existence with WiFi interferences Ultra-fast AGC strategy Radio consumption in RX mode: 7.0 mA Radio consumption in TX mode at 0 dBm: 10.2 mA Radio consumption in TX mode at +3 dBm: 13 mA Radio consumption in TX mode at +10 dBm: 26 mA Radio consumption in TX mode at +15 dBm: 51 mA Antenna diversity control; in BLE mode, this is controlled by software. Option to use one or two GPIOs to control external LNA / PA devices Radio PHY ready for 2 Mbps bandwidth (Bluetooth Low Energy) 8.20.2 Modem Bluetooth Low Energy modem The modem provides all the necessary demodulation functions to receive Bluetooth Low Energy 5.0 data. This includes AGC operation in conjunction with radio features to be able to receive the wide range of signal powers. Access Address detection is performed to identify and align to the start of a valid packet. Frequency offset is determined and removed. Then data sampling is performed so that the packet data is presented to the link layer function. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 43 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM IEEE 802.15.4 modem RX gain AGC IF signal Data Conditioning Symbol Detection (Despreading) Demodulation RX data interface TX VCO Modulation Sigma-delta modulator Fig 8. Spreading TX data interface Modem system diagram The modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250 kbits/s in the 2.4 GHz radio frequency band in compliance with the IEEE 802.15.4 standard. Features provided to support network channel selection algorithms include Energy Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel Assessment (CCA). The modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the IEEE802.15.4 ED function and LQI function. The ED and LQI are both related to receiver power. LQI is associated with a received packet, whereas ED is an indication of signal power-on air at a particular moment. The CCA capability of the modem supports all modes of operation defined in the IEEE802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold. 8.20.3 IEEE 802.15.4 baseband processor The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer hardware/software partitioning enables software to implement the sequencing of events required by the protocol and to schedule timed events with millisecond resolution, and the hardware to implement specific events with microsecond timing resolution. The protocol software layer performs the higher-layer aspects of the protocol, sending management and data messages between End Device and Co-ordinator nodes, using the services provided by the baseband processor. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 44 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Baseband Processor Data Converter Modem Data Interface RX PKT Filter FCS Gen/ Check Framing and Auto Ack Gen Memory Controller Packet Store Access AHB Master Bus Timers Supervisor State Machine Control & Status Interrupt CPU Interface AHB Slave Bus Radio Controller Interface Fig 9. Micro Interface Baseband processor system diagram 8.20.3.1 Transmit A transmission is performed by software writing the data to be transferred into the TX frame buffer in RAM, together with parameters such as the destination address and the number of retries allowed, as well as programming one of the protocol timers to indicate the time at which the frame is to be sent. This time will be determined by the software tracking the higher-layer aspects of the protocol such as superframe timing and slot boundaries. Once the packet is prepared and protocol timer set, the supervisor block controls the transmission. When the scheduled time arrives, the supervisor controls the sequencing of the radio and modem to perform the type of transmission required, fetching the packet data directly from RAM. It can perform all the algorithms required by IEEE802.15.4 such as CSMA/CA without processor intervention including retries and random back-offs. When the transmission begins, the header of the frame is constructed from the parameters programmed by the software and sent with the frame data through the serializer to the modem. At the same time, the radio is prepared for transmission. During the passage of the bit-stream to the modem, it passes through a CRC checksum generator that calculates the checksum on-the-fly, and appends it to the end of the frame. 8.20.3.2 Reception During reception, the radio is set to receive on a particular channel. On receipt of data from the modem, the frame is directed into the RX frame buffer in RAM where both header and frame data can be read by the protocol software. An interrupt may be provided on receipt of the frame. An additional interrupt may be provided after the transmission of an acknowledgement frame in response to the received frame, if an acknowledgement frame has been requested and the auto acknowledge mechanism is enabled. As the frame data is being received from the modem, it is passed through a checksum generator; at the end of the reception the checksum result is compared with the checksum at the end of the K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 45 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM message to ensure that the data has been received correctly. During reception, the modem determines the Link Quality, which is made available at the end of the reception as part of the requirements of IEEE 802.15.4. 8.20.3.3 Auto acknowledge Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The baseband processor can automatically construct and send the acknowledgment packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence. The baseband processor can also request an acknowledge for packets being transmitted and handle the reception of acknowledged packets without processor intervention. 8.20.3.4 Security The transmission and reception of secured frames using the Advanced Encryption Standard (AES) algorithm is handled by the stack software. The baseband processor and modem does not perform any encryption or decryption. To transmit an encrypted packet, the data in the packet must be encrypted and written into the RAM and then the baseband processor can be directed to transmit the encrypted data. Similarly, in receive, the encrypted data is written into the RAM by the baseband processor. The stack software must then perform the decryption. The AES engine provided on chip supports hardware accelerated AES operations and can be used by the stack software or the application. 8.20.4 Bluetooth Low Energy link layer The Link Layer supports the time-critical packet functions of the Bluetooth Low Energy 5.0 protocol. Data processing includes whitening and CRC functions. Received packets can be checked against a whitelist. Packet transmission and reception can be scheduled in advance. Then hardware state machines manage enabling the radio at the correct time and interfacing to the system RAM to transfer packet data. Additionally, AES encryption and decryption supported within the link layer. For low power operation, a timer is able to operate in power down mode. Then the device will wake-up at the required time to continue Bluetooth Low Energy activity. 8.20.5 Antenna diversity Support is provided for antenna diversity, which is a technique that maximizes the performance of an antenna system. It allows the radio signal to be switched between two antennas that have very low correlation between their received signals. Typically, this is achieved by spacing two antennae around 0.25 wavelengths apart or by using 2 orthogonal polarizations. It is controlled by software. In IEEE802.15.4 / Zigbee / Thread operation, using transmit diversity mode, if a packet is transmitted and no acknowledgment is received, the radio system can switch to the other antenna for the retry. Alternatively, antenna diversity can be enabled so that antenna switching will occur in receive mode when waiting for a packet. Receive diversity operates a combined HW timer and SW power threshold mode. In general, the antenna is switched every 60 ms. However, if two preamble symbols are detected, then the antenna switching stops; the software will check whether the signal strength exceeds a threshold. If the signal is too weak, then the antenna selected is switched and the automatic switching will K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 46 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM restart. If the signal is strong, the packet reception will continue. The overall system performance depends upon various factors such as the attenuation / isolation between the two antennas, the RF characteristics of the signals received on each antenna. When operating in Bluetooth Low Energy 5.0 mode, the Bluetooth Low Energy application software can select which antenna to use; the selection criteria could be based on RSSI or packet error rate and it is the responsibility of the application to implement the selection mechanism. The same ADO (SELA) and ADE (SELB) outputs are used as in the IEEE 802.15.4 case. When operating in dual mode, it is also possible to configure the Bluetooth Low Energy operations to use the antenna selected by IEEE 802.15.4 hardware mechanism. The K32W041A/K32W041AM provides an output (ADO) on one of PIO7, PIO9 or PIO19 and optionally its complement (ADE) on PIO6 that can be used to control an antenna switch; this enables antenna diversity to be implemented easily (see Figure 9). antenna A antenna B B A ADO ADE SEL RF switch: single-pole, double-throw (SPDT) SELB COM device RF port Fig 10. Simple antenna diversity implementation using external RF switch If two PIO pins cannot be spared, one of the signals (ADE or ADO) from the K32W041A/K32W041AM can be used and its complement can be generated using an inverter on the PCB. 8.20.6 Radio usage The Radio and antenna are shared between the Bluetooth Low Energy 5.0 and IEEE 802.15.4 specific hardware and the two protocol stacks. Software arbitration is required to ensure only one protocol attempts to use the radio at any point. 8.21 AES engine The AES provides an on-chip hardware AES encryption and decryption engine to protect the image content and to accelerate processing for data encryption or decryption, data integrity, and proof of origin. Data can be encrypted or decrypted by the AES engine using the secret encrypted key in the OTP or a software supplied key • • • • K32W041A/K32W041AM Product data sheet 1 instance of Advanced Encryption Standard (AES) Support 128-bit keys for encryption and decryption Support 192-bit keys for encryption and decryption Support 256-bit keys for encryption and decryption All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 47 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM • Support for several protocols – ECB (Electronic Code Book) – CBC (Cipher Block Chaining) – CFB (Cipher Feedback) – OFB (Output Feedback) – CTR (Counter) • DMA support with DMA triggers for input data and output data 8.22 SPI-bus Flash Interface (SPIFI) For K32W041A device, the SPI-bus Flash Interface provides support for a master Quad SPI-bus capable of interfacing to a range of SPI devices for high throughput transfer of data between the K32W041A and an external device, such as a memory device. For the K32W041AM device, this interface is used to communicate to the flash memory device within the package. • Supports 1-bit, 2-bit, and 4-bit bidirectional serial protocols, 4-bit mode only applicable to the K32W041A device. • Half-duplex protocol compatible with various vendors and devices • Operates at up to 32 MHz • DMA support for transferring data to and from the SPIFI module 8.23 Hash module The Hash function creates a fixed size signature from a block of data. It can be used as part of a scheme to check if data corruption has occurred. • Support SHA-1 • Support SHA-256 • DMA support for efficient operation 8.24 ISO7816 smart card interface The ISO smart card interface block, with suitable external analogue device, can support Smart Card reader applications. • • • • • Compliant with ISO7816 standard Support of class A (5 V), Class B (3 V) and Class C (1.8 V) contact smart cards Support of ISO7816 UART interface Supports the asynchronous protocols (T=0 and T=1) in accordance with ISO7816 Supports synchronous cards 8.25 Random number generator The K32W041A/K32W041AM integrates a random number generator (RNG) for security purposes. The RNG generates, with suitable software, true non-deterministic random numbers for generating keys, initialization vectors and other random number requirements. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 48 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 8.26 Data Flash The K32W041AM devices include Data Flash. This is accessed via the SPIFI flash interface and can be used to store data such as software upgrades, received over the air, before they can be written to the internal flash memory or application data. The features of the flash device are: • • • • • • • • Supports single (1-1-1) and dual output operation (1-1-2) 8 Mbit (1M x 8) flash memory 1 x 128-byte factory programmed unique identifier 3 x 128 byte one time programmable security registers Low power modes Operation at up to 33MHz Erase operations support a 4, 32 or 64-KB block erase or full chip erase Non-volatile status register configuration option Connections to the flash device driven actively are QSPI_CS (active low), QSPI_CLK, QSPI_IO0, QSPI_IO1. Additionally, the active low reset signal of the flash is connected to FLASH_RSTN device pin. The QSPI_CSN and FLASH_RSTN must each have a pull-up resistor to the device power supply, VDDE. 9. Application design-in information 9.1 K32W041A/K32W041AM module reference designs For customers wishing to integrate the K32W041A/K32W041AM device directly into their system, NXP provides schematics and design files for the K32W0x Module Upgrade Boards. To ensure the correct performance, it is strongly recommended that where possible the design details provided by the reference designs are used in their exact form for all end designs; this includes component values, pad dimensions, track layouts etc. In order to minimize all risks, it is recommended that the entire layout of the appropriate reference module, if possible, be replicated in the end design. For full details, see web site or Contact technical support. 9.2 Schematic diagram The PCB schematic and layout rules detailed in this data sheet must be followed. Failure to do so will likely result in the K32W041A/K32W041AM failing to meet the performance specification detailed in this data sheet and the worst case may result in the device not functioning in the end application. A schematic diagram of the reference module is shown in Figure 10. Details of component values and PCB layout constraints can be found in Table 9. The paddle should be connected directly to ground. Any pads that require connection to ground should do so by connecting directly to the paddle. The K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 49 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM will enter UART programming mode if IN System Programming Entry (PIO5) pin 8 is low during RESET release. The preferred communication interface is USART0 pins (PIO8/USART0_TXD pin11 and PIO9/USART0_RXD pin12). VBAT 1.9 to 3.6 V C1 10 μF VBAT (Pin 28) C10 100 nF VDDE (Pin 20) C12 47 pF C11 100 nF LX (Pin 29) DC/DC CONVERTER L4 2.2 μH I/O LA (Pin 40) FB (Pin 31) VBAT 10 kΩ C19 10 μF FLASH_CSN (Pin 19) PMU/CPU/ MEMORY VDD_PMU (Pin 32) VDD_RADIO (Pin 35) C13 100 nF C14 47 pF K32W041A K32W041AM RF_IO (Pin 37) RADIO TRANSCEIVER R5 0Ω XTAL_P (Pin 1) C25 2 pF 2.4 GHz antenna C24 1.2 pF 32 kHz OSCILLATOR 32 MHz OSCILLATOR XTAL_N (Pin 2) L2 3.3 nH XTAL_32k_N (Pin 34) C21 NC X2 XTAL_32k_P (Pin 33) C20 NC Y1 Fig 11. Application diagram – battery powered solution For single-ended antennas or connectors, a balun is not required. However, an external filtering is needed. In receiver, the RFIO pin shows a 50  impedance and external filtering (R5, C25, L2, C24) is needed in transmission to filter efficiently harmonics. These components are critical and must be placed close to the K32W041A/K32W041AM pins and analog ground. The reference PCB is designed to present an accurate match to a 50  resistive network as well as provide a DC path to the final output stage or antenna. Users wishing to match to other active devices such as amplifiers must design their networks to match to 50  at the output of the K32W041A/K32W041AM. The paddle must be connected directly to the ground. Any pads that require connection to the ground should do so by connecting directly to the paddle. Table 9. Component descriptions about Figure 10 Component Function Value Note RF C24 RF filtering capacitor 1.2 pF COG type C25 RF filtering capacitor 2 pF COG type L2 RF filtering inductor 3.3 nH K32W041A/K32W041AM Product data sheet MURATA (LQW15AN3N3B) All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 50 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 9. Component descriptions about Figure 10 Component Function R5 Optional RF tuning area Value 0 Note Not needed on ref design. Maybe needed to put an inductor for RF path tuning Power C1 Power source decoupling 10 μF MURATA (GRM21BR71A106KA73L) C10 Power source decoupling 100 nF Locate less than 5mm from U1 pin 28 C12 Power source decoupling 47 pF COG type L4 DC-DC feedback filter inductor 2.2 μH TDK (MLZ2012M2R2HT000) C19 DC-DC feedback filter capacitor 10 μF X7R MURATA (GRM21BR71A106KA73L) C13 Radio and PMU decoupling 100 nF Locate less than 5mm from U1 pins32/35 C14 Radio and PMU decoupling 47 pF COG type C11 DigitL4 and IO power decoupling 100 nF Locate less than 5mm from U1 pin 20 Clock Y1 32 MHz crystal 32 MHz, 6 pF NDK (NX2016SA 32 MHZ EXS00A-CS11213 6 pF) X2 32.768 kHz crystal 32.768 kHz, 6 pF NDK (NX2012SA 32.768 kHZ EXS00A-MU01089 6pF) C20-C21 optional 32.768 kHz crystal load capacitance NC 10. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VBAT Supply voltage DCDC input -0.3 3.96 V VDDE IO supply voltage -0.3 3.96 V VDD(Radio) Radio supply voltage -0.3 1.6 V VDD(PMU) PMU supply voltage -0.3 1.6 V VIO IO pins voltage -0.3 3.96 V VRST RSTN voltage -0.3 3.96 V VRFIO Voltage on pin RFIO -0.3 0 VDC VADC ADC pins voltage -0.3 3.96 V VLx LA and LB pin voltage -0.3 4.6 Vpeak Tstg Storage temperature -40 125 C HBM [2]  3000 V CDM [3]  500 V Ambient temperature: -40 °C [4]  2 V/ms VESD ts Electrostatic discharge voltage Max. VBAT slope [1] VBAT from 0 V up to +3.6 V K32W041A/K32W041AM Product data sheet [1] Primary input of RF transformer connected to the ground. No DC voltage. [2] Testing for HBM discharge is performed as specified in JEDEC Standard JS-001. [3] Testing for CDM discharge is performed as specified in JEDEC Standard JESD22-C101. [4] Risk of physical damage if the VBAT slope is out of this specification All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 51 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM VBAT 0V ts Condition: Ambient temperature: -40 °C, VBAT: 3.6 V Fig 12. Power-up ramp Not measured Fig 13. Minimum VBAT rise time vs temperature K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 52 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Fig 14. Maximum VBAT slope vs temperature 11. Recommended operating conditions Table 11. Operating conditions Symbol Parameter Min Max Unit VBAT DCDC supply voltage 2.4 3.6 V VDDE IO supply voltage 2.4 3.6 V Tamb Ambient temperature -40 85 C 12. Thermal characteristics Table 12. Thermal characteristics Symbol Parameter Min Typ Max Unit Rth(j-a) Rth(j-c) Thermal resistance from junction to ambient  28  K/W Thermal resistance from junction to case  4  K/W Tj(max) Maximum junction temperature   90 C K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 53 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 13. Static characteristics 13.1 Power consumption in Low-power mode Table 13. Typical current consumption in Low-power mode characteristics VBAT = 2.4 V to 3.6 V, Tamb = 25 °C Symbol Parameter Conditions IDD supply current Deep power-down (everything is powered off, wake-up on HW reset only) Min Typ Max Unit  260  nA Deep power-down-IO (everything is powered K32W041A  350  nA off, wake-up on HW reset only or an event on K32W041AM  360  nA Power-down (wake-up on HW reset or an IO event, K32W041A wake-up timer ON, 32 kHz FRO on, no SRAM K32W041AM retention)  800  nA  810  nA Power-down-4K (wake-up on HW reset or an IO K32W041A event, wake-up timer on, 32 kHz FRO on, with 4 KB K32W041AM SRAM retention])  1025  nA  1035  nA any of the GPIOs) Power-down-8K (wake-up on HW reset or an IO K32W041A event, wake-up timer on, 32 kHz FRO on, with 8 KB K32W041AM SRAM retention) [1]  1120  nA [1]  1130  nA Power down - RTC 1 kHz [2]  200  nA Power down - RTC 1 Hz [2]  200  nA Power down - per wake-up timer0 or timer1 / 32 kHz FRO  200  nA Power down - per wake-up timer0 or timer1 / 32 kHz XTAL  200  nA Power down - BOD VBAT [2]  300  nA Power down - wake up on COM interfaces [2] [3]  440  nA [1] Values achieved when application uses the optimized voltage configuration for power down. Any additional 4 KB RAM increases leakage current in typical condition by 105 nA. [2] Will be added to the power down current consumption if used. [3] Need to have retention on RAMBank7 (4 KB). 13.2 Power consumption in Active mode Table 14. Typical current consumption in Active mode characteristics VBAT = 2.4 V to 3.6 V, Tamb = 25 °C. Symbol Parameter Conditions IDD supply current radio in RX mode (IEEE 802.15.4 and Bluetooth Low Energy) radio in TX mode (IEEE 802.15.4 and Bluetooth Low Energy) with the output power of: [1] K32W041A/K32W041AM Product data sheet Min Typ[1] Max Unit  5.6  mA 0 dBm  10.2  mA +3 dBm  13  mA +10 dBm  26  mA +15 dBm  51  mA Typ values are measured in high power mode. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 54 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Note: Infrastructure and CPU current consumption have to be added to Radio supply current. Table 15. Typical CPU and peripherals current consumption characteristics VBAT = 2.4 V to 3.6 V, Tamb = 25 °C. Symbol Parameter Conditions IDD supply current IDD(ADC) ADC supply current IDD(sintf) Min Typ Current consumption measured on VBAT; CPU core running CoreMark from embedded Flash memory, system clock 12 MHz [1]  3.1  mA Current consumption measured on VBAT; CPU core running CoreMark from embedded Flash memory, system clock 32 MHz [1]  4.1  mA Current consumption measured on VBAT; CPU core running CoreMark from embedded Flash memory, system clock 48 MHz [1]  4.7  mA Continuous single channel acquisition at 190 KSps [1]  245.0  A [1]  462.6  A [1]  602.0  A SPI supply SPI bus supply current; continuous transmit at 2 MHz SPI CLK current IDD(DMA) DMA supply current Continuous transfer memory to memory of buffer size 1024 bytes [1] Max Unit Radio and Modem are powered off. FRO at 32 kHz, XO at 32 kHz and XO at 32 MHz are powered off. FRO48M, FRO32M and FRO12M are on. Current consumption including FRO at 1 MHz, FRO at 192 MHz and Flash read access. All unused peripheral clocks are disabled. All unused IOs are in input mode. 13.3 Power consumption in-package Flash memory The following characteristics are only for K32W041AM Table 16. Power consumption characteristics in-package Flash memory VBAT = 2.4 V to 3.6 V , Tamb = 25 °C, unless otherwise specified. Symbol IDD Min Typ[1] Max Unit Standby current  16.6  A Ultra deep power down  10  nA Parameter supply current [1] Conditions Active read current (at 33 MHz)  2.7  mA Program current  4.1  mA Erase current  4  mA Typ Max Unit Typ values are related to data flash low-power mode. 13.4 IO characteristics Table 17. IO characteristics VDDE = 2.4 V to 3.6 V, Tamb = -40 °C to +85 °C, unless otherwise specified. Symbol Parameter Min Rpu(int)(PIO) Internal pull-up resistance on pins PIOx Rpu(int)(RSTN) Internal pull-up resistance on pin RSTN Rpdn(int)(PIO) Internal pull-down resistance on pins PIOx [1] [1] 40 50 60 k 40 50 60 k 40 50 60 k 0.7 * VDDE  VDDE V IO VIH High-level input voltage K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 55 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 17. IO characteristics …continued VDDE = 2.4 V to 3.6 V, Tamb = -40 °C to +85 °C, unless otherwise specified. Symbol Parameter Min Typ Max Unit VIL Low-level input voltage 0.3  0.27 * VDDE V VDD = 3.6 V 3.4  VDDE V VDD = 3.0 V 2.8  VDDE V VDD = 2.4 V 2.2  VDDE V 0  0.4 V VDD = 3.6 V 3.3  VDDE V VDD = 3.0 V 2.65  VDDE V Output on pins PIO LS, with 1 mA load[2][4] VOH VOL High-level output voltage Low-level output voltage Output on pins PIO LS, with 2 mA load[2][4] VOH High-level output voltage 2  VDDE V 0  0.4 V VDD = 3.6 V 3.35  VDDE V VDD = 3.0 V 2.75  VDDE V VDD = 2.4 V 2.1  VDDE V 0  0.4 V VDD = 3.6 V 3.2  VDDE V VDD = 3.0 V 2.6  VDDE V VDD = 2.4 V 2.05  VDDE V 0  0.4 V VDD = 3.6 V 3.45  VDDE V VDD = 3.0 V 2.82  VDDE V VDD = 2.4 V 2.30  VDDE V 0  0.4 V VDD = 3.6 V 3.30  VDDE V VDD = 3.0 V 2.66  VDDE V VDD = 2.4 V VDD = 2.4 V VOL Low-level output voltage Output on pins PIO HS, with 3 mA load[3][4] VOH VOL High-level output voltage Low-level output voltage Output on pins PIO HS, with 5 VOH VOL High-level output voltage Low-level output voltage Output on pins PIO VOH VOL mA load[3][4] I2C, with 1 mA load[4][5] High-level output voltage Low-level output voltage Output on pins PIO I2C, with 2 mA load[4][5] VOH High-level output voltage 2.10  VDDE V Low-level output voltage 0  0.4 V ILIL Low-level input leakage current  4.5  nA ILIH High-level input leakage current  4.5  nA VOL Currents K32W041A/K32W041AM Product data sheet [1] All PIO except RSTN (reset), PIO10 and PIO11 (I2C function). [2] PIO 0 to 9 and 12 to 16. [3] PIO 17 to 21. [4] Values from simulation. [5] PIO 10 and 11. IO cell in GPIO mode. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 56 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 14. Dynamic characteristics 14.1 AC characteristics 14.1.1 Reset and Supply Voltage Monitor Table 18. Externally applied reset VDDE = 2.4 V to 3.6 V, Tamb = -40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit  500  ns trst Reset time External reset pulse width to initiate reset sequence [1] Vrh Reset high voltage External threshold voltage, for reset to be sampled high (inactive) [2] 0.7 x VDDE   V Vrl Reset low voltage External threshold voltage for reset to be low (active) [2]   0.7 x VDDE V Vth(POR) Power-on reset threshold voltage Rise time > 10 ms rising  1.85  V falling  1.75  V tSTAB Stabilisation time Time after release of reset until application runs   1.9 ms IDD Supply current Chip current when held in reset, VDDE = 3 V  132  A Irst(bod vbat) Brownout reset current Chip current when held in reset when voltage is above power-on-reset threshold but below brownout threshold  46  A Vth Threshold voltage Supply (VBAT) threshold voltage monitor 1.69 1.75 1.81 V 1.74 1.8 1.86 V 1.84 1.9 1.96 V 1.94 2 2.06 V 2.03 2.1 2.17 V 2.13 2.2 2.27 V 2.23 2.3 2.37 V 2.32 2.4 2.48 V 2.42 2.5 2.58 V 2.52 2.6 2.68 V 2.61 2.7 2.79 V 2.71 2.8 2.89 V 2.81 2.9 2.99 V 2.91 3 3.09 V 3.00 3.1 3.2 V 3.10 3.2 3.3 V 3.20 3.3 3.4 V K32W041A/K32W041AM Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 57 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 18. Externally applied reset …continued VDDE = 2.4 V to 3.6 V, Tamb = -40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Vhys Hysteresis voltage Supply voltage (VBAT) monitor; configurable in 4 levels [3] Min Typ Max Unit 18.75 25 31.25 mV 37.50 50 62.5 mV 56.25 75 93.75 mV 75.00 100 125 mV [1] Assumes internal pull-up resistor value of 100 k worst case and 5 pF external capacitance. [2] Minimum voltage to avoid being reset. [3] Device setting from reset trst Vrh RST_IN Vrl internal RESET tSTAB tSTAB Fig 15. Reset signal timing 14.1.2 Analog to Digital Converters Table 19. Analog to Digital Converters VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Vi Input voltage switchable 0 FSR Full scale range After calibration Typ 3.56 3.6 Max Unit VBAT V 3.62 IADCx Current on  100  A INL Integral non-linearity  1.1  LSB DNL Differential non-linearity  0.85  LSB EO Offset error -4.5  4.5 mV pins ADCx[1] After calibration EG Gain error After calibration -40 0 20 mV fS Sampling frequency Single channel 78.4 100 190 ksps tconv Conversion time  10  s Ci(a) Analog input capacitance  4  pF SFDR Spurious-free dynamic range  75  dBc [1] For Fin = 25 kHz With x = 0, 1, 2, 3, 4, or 5 for K32W041A; x = 0,1, or 3 for K32W041AM. K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 58 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 14.1.3 Comparator Table 20. Comparator VDDE = 2.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tresp Parameter [1] Min Typ Max Unit Response time -low power mode  2  s Response time - standard mode  1.3  s Vhys Hysteresis voltage  50  mV Vref_ext External reference voltage 0  VDDE V Vref_int Internal reference voltage  0.8  V VI(cm) Common-mode input voltage  0.8  V Min Typ Max Unit [1] Response time to trigger caused by square wave input. 14.1.4 32 kHz free running oscillator Table 21. 32 kHz free running oscillator VDDE = 2.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter freq FRO center frequency  32.768  kHz fffro FRO accuracy -2  2 % IDD FRO current  200  nA Min Typ Max Unit 1  MHz 14.1.5 1 MHz free running oscillator Table 22. 1 MHz free running oscillator VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter freq FRO center frequency  fffro FRO accuracy -15  15 % IDD FRO current  18  A Min Typ Max Unit 14.1.6 32 kHz crystal oscillator Table 23. 32 kHz crystal oscillator VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter freq XTAL center frequency fffro XTAL accuracy tstartup IDD  32.768  kHz -500  500 ppm Start-up time  1  s XTAL current  200  nA K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 59 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 14.1.7 32 MHz crystal oscillator Table 24. 32 MHz crystal oscillator VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter freq Conditions Min Typ Max Unit XTAL center frequency  32  MHz fffro XTAL accuracy -40  40 ppm tstartup Start-up time  150  s IDD XTAL current  82  A Min Typ Max Unit Time to reach 50 ppm accuracy 14.1.8 High-speed free running oscillator Table 25. High-speed free running oscillator VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions freq FRO center frequency 48 MHz clock output  48  MHz 32 MHz clock output  32  MHz 12 MHz clock output  12  MHz -2  2 % fffro FRO accuracy K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 60 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 14.1.9 Temperature sensor Table 26. Temperature sensor VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tsen Sensor temperature range 40  +90 °C Gsen Sensor gain At ADC output after conversion  10.12  LSB/°C TsenSlope Temperature sensor slope After calibration at 25 °C   2.5 % Tsen25 Temperature accuracy at 25°C  2  °C Tsen Sensor temperature accuracy Full range -40 to +90 °C -4.5  4.5 °C TTN Temperature sensor thermal noise After calibration at 25 °C  0.07  °C·RMS 14.2 Flash memory Table 27. Flash memory VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Nendu tret Parameter Conditions Endurance Retention time Min Typ Max Unit Page erase/program [1] 100000   cycles Mass erase/program [1] 100000   cycles Powered 10   year Unpowered 10   year terase Erase time 1 Page (512 Bytes)  1.878  ms tblank Blank status time 1 Page (512 Bytes)  21  s tprog Programming time 1 Page (512 Bytes)  1.09  ms Unit [1] Number of erase/program cycles, for Junction temperature range -40°C to 85°C 14.3 Internal Data Flash on K32W041AM Table 28. Internal serial flash memory VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions tchip_erase Chip erase time tblock_erase Block erase time tret Retention time Min Typ Max 1 Page (512 Bytes)  32  s 4 KB  66  ms 32 KB  515  ms 64 KB  800  ms Powered 10   year Unpowered 10   year tprog Page programming time 1 Page (256 Bytes)  1.5  ms tbype_prog Byte programming time  12  s totp_prog OTP security register programming time  5  ms twrite_prog Write status register time  13  ms Nendu Endurance  100000  cycle tret Retention time  10  year K32W041A/K32W041AM Product data sheet ≤10 K Program/erase All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 61 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 14.4 IO pins Table 29. Dynamic characteristic: I/O pins[1] VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol PIO tR Conditions Rise time Fall time tF PIO Parameter Min Typ Max Unit Slow speed, 3.3 V 12  22 ns Slow speed 1.9 V 14  28 ns Fast speed 3.3 V 1.7  5 ns Fast speed 1.9 V 3.2  7.5 ns Slow speed, 3.3 V 14  29 ns Slow speed 1.9 V 18  34 ns Fast speed 3.3 V 1.1  2.6 ns Fast speed 1.9 V 2  4.7 ns Slow speed, 3.3 V 1.6  4 ns Slow speed 1.9 V 2.4  6 ns Fast speed 3.3 V 0.8  3 ns I2C[2][5] HS[3][5] tR tF Rise time Fall time Fast speed 1.9 V 1.2  4 ns Slow speed, 3.3 V 1.1  3.3 ns Slow speed 1.9 V 1.6  5 ns Fast speed 3.3 V 0.6  3 ns Fast speed 1.9 V 0.9  3.5 ns Slow speed, 3.3 V 2.2  5 ns Slow speed 1.9 V 3.3  7.5 ns PIO LS[4][5] tR tF Rise time Fall time K32W041A/K32W041AM Product data sheet Fast speed 3.3 V 1.6  4 ns Fast speed 1.9 V 2.5  6.5 ns Slow speed, 3.3 V 1.2  3.5 ns Slow speed 1.9 V 1.9  5 ns Fast speed 3.3 V 0.7  3 ns Fast speed 1.9 V 1.1  3.5 ns [1] Simulated data. [2] PIO I2C values are for PIO10 and PIO11. IO cell in GPIO mode. Slow speed is EHS=0; Fast speed is EHS=1 [3] Values are for PIO17-21. Slow speed is SLEW(1:0) = 00b. Fast speed is SLEW(1:0) = 11b [4] Values are for PIO0-9 and PIO12-16. Slow speed is SLEW(1:0) = 00b. Fast speed is SLEW(1:0) = 11b [5] Pin capacitance load = 10 pF [6] The slew rate is configured in the IOCON block. See K32W041A/K32W041AM User Manual. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 62 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM VDDE 80% 80% Output Signal 20% tF 20% GND tR Fig 16. Output timing measurement condition 14.5 Wake-up timing Table 30. Wake-up timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol tstartup twake Parameter Conditions [1] Min Typ Max Unit  1.9  ms CPU startup time Time for CPU to be running application code when VBAT > VBAT_BOD threshold XTAL startup time Time to 32M XTAL ready for radio operation  350  s Sleep wake-up time Time to CPU to be running after wake-up trigger  0.2  s power-down wake-up time Time to CPU to be running after wake-up trigger with RAM held  392  s power-down wake-up time Time to CPU to be running after wake-up trigger without RAM held  836  s deep power-down wake-up Time to CPU to be running after wake-up trigger  936  s [1] Time to start of executing simple application. 14.6 SPI timing Table 31. SPI master timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew = 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge. Symbol Parameter Min Typ Max Unit tDS Data set-up time 10   ns tDH Data hold time 5   ns tV(Q) Data output valid time tcy(SCK) SCK frequency -2  15 ns 0.01  8 MHz Duty cycle tSS tSH 45 50 55 % SSEL low before SCK edge [1] 1   SCK cycles SSEL low after last SCK edge [2] 0.5   SCK cycles [1] K32W041A/K32W041AM Product data sheet Pre-delay can be configured to increase this time in steps of 1 SCK cycle All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 63 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM [2] Post-delay can be configured to increase this time in steps of 1 SCK cycle Table 32. SPI slave timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew = 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge. Symbol Parameter Min Typ Max Unit tDS tDH Data set-up time 12   ns Data hold time 5   ns tV(Q) Data output valid time 0  35 ns tcy(SCK) SCK frequency   8 MHz tSS SSEL low before SCK edge [1] tSH SSEL low after last SCK edge [2] 1   ns 0.5   ns [1] Pre-delay can be configured to increase this time in steps of 1 SCK cycle [2] Post-delay can be configured to increase this time in steps of 1 SCK cycle Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL tSS MOSI (CPHA = 0) tSH tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MOSI (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MISO (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (MSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH DATA VALID Fig 17. SPI master interface timings K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 64 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) t SH t SS SSEL MISO (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID tDS MOSI (CPHA = 0) DATA VALID (MSB) MISO (CPHA = 1) DATA VALID (LSB) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH DATA VALID tv(Q) tv(Q) DATA VALID (MSB) DATA VALID tDS MOSI (CPHA = 1) DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH DATA VALID Fig 18. SPI slave interface timings 14.7 USART timing Table 33. USART master timing (in synchronous mode) VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 30 pF balanced loading on all pins; Input slew = 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge. Symbol Parameter Min Typ Max Unit tSU(D) Data set-up time 45   ns th(D) Data hold time 5   ns tV(Q) Data output valid time 0  25 ns tcy(SCLK) SCLK frequency   5 MHz Table 34. USART slave timing (in synchronous mode) VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 30 pF balanced loading on all pins; Input slew = 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge. Symbol Parameter tSU(D) Data set-up time K32W041A/K32W041AM Product data sheet Min Typ Max Unit 5   ns All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 65 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 34. USART slave timing (in synchronous mode) VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 30 pF balanced loading on all pins; Input slew = 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge. Symbol Parameter Min Typ Max Unit th(D) Data hold time 5   ns tV(Q) Data output valid time 0  55 ns tcy(SCLK) SCLK frequency   5 MHz Tcy(clk) Un_SCLK (CLKPOL = 0) Un_SCLK (CLKPOL = 1) tv(Q) tvQ) START TXD BIT0 BIT1 tsu(D) th(D) START RXD BIT1 BIT0 Fig 19. USART interface timings 14.8 SPIFI timing Table 35. SPIFI timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; EHS=1 for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge; simulated values. Symbol Parameter Min Typ Max Unit tcy(clk) Clock cycle time 30.0   ns tDS Data set-up time 3   ns tDH Data hold time 3   ns tV(Q) Data output valid time   5 ns tH(Q) Data output hold time -10.5   ns Duty cycle 40  60 % tSS SSEL set-up time, time SSEL is low before first SCK edge 0.5   SCK cycles tSH SSEL hold time, time SSEL is low after last SCK 0.5   SCK cycles K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 66 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM SPIFI_SSEL Tcy(clk) tSH tSS SPIFI_SCK tv(Q) DATA VALID SPIFI data out th(Q) DATA VALID tDS DATA VALID SPIFI data in tDH DATA VALID Fig 20. SPIFI interface timings 14.9 PWM timing Table 36. PWM timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew = 1ns; SLEW set to standard mode for all pins; parameters samples at the 90% and 10% level of the rising or falling edge; simulated skew (over process, voltage and temperature) of any two PWM output signals; values guaranteed by design. Symbol Parameter tSK Output skew time Min Typ Max Unit 0  10 ns 14.10 DMIC timing Table 37. DMIC timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew = 1ns; SLEW set to standard mode for all pins; parameters samples at the 90% and 10% level of the rising or falling edge; bypass bit = 0; based on simulated values and for 2.4 V to 3.6 V. Symbol Parameter tcy(SCK) DMIC CLK frequency Duty cycle Conditions CL = 10 pF using 32MHz XTAL clock source Min Typ Max Unit   2 MHz 48  52 % tDS Data set-up time 25   ns tDH Data hold time 1   ns K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 67 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM CLOCK tDH tSU DATA Fig 21. DMIC interface timings 14.11 ISO7816 Table 38. Clock of ISO7816 VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; Tj = −40 °C to +90 °C; unless otherwise specified; guaranteed by design; Not tested in production. Symbol Parameter VOH High-level output voltage 0.7 x VBAT VOL Low-level output voltage 0 Duty cycle 48 CLK frequency 2 Freq Min Typ Max Unit  VBAT V  0.3 x VBAT V  52 %  12 MHz Table 39. Input output of ISO7816 VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; unless otherwise specified; guaranteed by design; Not tested in production. Symbol Parameter Conditions Min VOH High-level output voltage CL = 10 pF 0.7 x VBAT VOL Low-level output voltage CL = 10 pF 0 VIH High-level input voltage 0.75 x VBAT VIL Low-level input voltage Max Unit  VBAT V  0.3 x VBAT V  VBAT + 0.1 V 0  0.3 V IOH IOL High-level output current 10  1000 A Low-level output current 600  1000 A tr(O) Output rise time CL= 30 pF; 10 % to 90 %;   1.2 s tf(O) Output fall time CL= 30 pF; 10 % to 90 %;   1.2 s For VBAT from 0 V to 3.6 V Typ 0 V to VBAT 0 V to VBAT tr(I) Input rise time   100 ns tf(I) Input fall time   100 ns K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 68 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM 14.12 I2C timing Table 40. I2C timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; guaranteed by design. Not tested in production. Symbol Parameter Conditions fSCL SC clock frequency Standard-mode tf tLOW tHIGH tHD;DAT tSU;DAT Min Typ Max Unit 0  100 kHz Fast-mode 0  400 kHz Fast-mode plus 0  1 MHz   300 ns 20 x VDDE/5.5  300 ns Fast-mode plus   120 ns Standard-mode 4.7   s Fast-mode 1.3   s Fast-mode plus 0.5   s Fall time, of both SDA and Standard-mode SCL signals Fast-mode Low period of the SCL clock High period of the SCL clock Data hold time Data setup time K32W041A/K32W041AM Product data sheet [8] 4   s Fast-mode 0.6   s Fast-mode plus 0.26   s Standard-mode 0   ns Fast-mode 0   ns Fast-mode plus 0   ns Standard-mode 250   ns Fast-mode 100   ns Fast-mode plus 50   ns Standard-mode [1] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [2] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [3] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [4] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [5] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [6] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [7] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. [8] Valid for I2C IO cells. When I2C functionality is supported on standard IO cells this Min time is 0. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 69 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf tHIGH 70 % 30 % SCL 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S Fig 22. I2C interface timings 14.13 GPIO pin timing Table 41. GPIO pin timing VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified; Input slew = 1 ns; parameters samples at the 90% and 10% level of the rising or falling edge. Symbol Parameter Conditions GPIO pin interrupt pulse width (digital glitch filter disabled) - Synchronous path [1] GPIO pin interrupt pulse width (digital glitch filterdisabled) Asynchronous path [3] Min Typ Max Unit 1.5   Bus clock cycles 20   ns [2] [1] This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes (Min CPU clock at 12 MHz) [2] The greater of synchronous and asynchronous timing must be met [3] This is the minimum pulse width that is guaranteed to be recognized 14.14 Radio transceiver (IEEE 802.15.4) This K32W041A/K32W041AM meets all the requirements of the IEEE 802.15.4 standard over 2.4 V to 3.6 V and offers the improved RF characteristics shown in Table 43. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, when used with NXP’s Module Reference Designs. Compliant with FCC part 15 rules, IC Canada and ETSI ETS 300-328, refer to the K32W041A/K32W041AM Module Reference Design package on the Wireless Connectivity area of the NXP web site Ref. 2. The PCB schematic and layout rules detailed in Section 9 “Application design-in information” must be followed. Failure to do so will likely result in the K32W041A/K32W041AM failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. Table 42. RF port characteristics Single-ended; Impedance = 50 Ω; VDDE = 2.4 V to 3.6 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Min Typ Max Unit Frange Frequency range 2.4  2.485 GHz K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 70 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 43. Radio transceiver characteristics: +25 °C VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Receiver sensitivity 1 % PER, as per IEEE 802.15.4  99.7  dBm  7.3  dB   10 dBm  -2.1  dB Adjacent -5 MHz  35.6  dB Adjacent +5 MHz  36  dB Alternate -10 MHz  46.3  dB Alternate +10 MHz  46.7  dB -15 MHz  51.5  dB Receiver SRX [1] NF Noise Figure Max gain PinMaxRX Maximum receiver input power 1 % PER, measured as sensitivity Coch Co-channel Interference 1 % PER, with wanted signal 3 dB above rejection sensitivity as per IEEE 802.15.4 Rej-5M Interference rejection, 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[2] Rej+5M Rej-10M Rej+10M Rej-15M Rej+15M RejProp-5M RejProp+5M RejProp-10M RejProp+10M RejProp-15M Proprietary mode interference rejection. 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[3] RejProp+15M RejCW-5M RejCW+5M RejCW-10M RejCW+10M CW interference rejection. 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[4] RejCW-15M [2] +15 MHz  52.3  dB Adjacent -5 MHz  57.1  dB Adjacent +5 MHz  59.6  dB Alternate -10 MHz  62.1  dB Alternate +10 MHz  62.7  dB -15 MHz  58  dB +15 MHz  60.8  dB Adjacent -5 MHz  59  dB Adjacent +5 MHz  59.7  dB Alternate -10 MHz  62  dB Alternate +10 MHz  62.6  dB -15 MHz  61.1  dB +15 MHz  61.5  dB RejOOB Out-of-band rejection 1 % PER with wanted signal 3 dB above sensitivity, CW interferers at 868 MHz (KNX), RF/2, 2100 MHz (WCDMA), 2500 MHz (LTE), or RF/3 (3GPP-Japan)  61.6  dB IMP2,4 Inter-modulation protection 1% PER with wanted signal 3 dB above sensitivity, modulated interferers at 2 and 4 channels separation [5]  44  dB 1% PER with wanted signal 3 dB above sensitivity, modulated interferers at 3 and 6 channels separation [5]  46.5  dB RejCW+15M IMP3,6 K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 71 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 43. Radio transceiver characteristics: +25 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter PinBlockin Blocking input power g Conditions Min Typ Max Unit Desired channel IEEE 802.15.4, level = measured sensitivity + 6dB, channels 11 & 26. Unwanted channel CW at 2380 MHz or 2503.5 MHz  -20.6  dBm Desired channel IEEE 802.15.4, level = measured sensitivity + 6dB, channels 11 & 26. Unwanted channel CW at 2300 MHz, 2330 MHz & 2360 MHz  -19.5  dBm Desired channel IEEE 802.15.4, level = measured sensitivity + 6dB, channels 11 & 26. Unwanted channel CW at 2523.5 MHz, 2553.5 MHZ, 2583.5 MHz, 2613.5 MHz, 2643.5 MHz, 2673.5 MHz  -18.7  dBm  2  dB [6] RSSIvar RSSI variation Desired channel IEEE 802.15.4, over the RSSI range -100 dBm to 8 dBm PspRX Receiver spurious emission, measured conducted into 50 ohms 30 MHz to 1 GHz, 100 kHz RBW, 300 kHz VBW, Filter type 3 dB (Gaussian), Peak detector, Trace Mode Max hold  -87.1  dBm 1 GHz to 12.75 GHz, 1 MHz RBW, 3MHz VBW, Filter type 3dB (Gaussian), Peak detector, Trace mode Max hold  -70.9  dBm  -98  dBm LOLeakRX Local oscillator leakage power WIFI rejection 1% PER, with wanted signal IEEE 802.15.4 -75 dBm 2470 MHz, WIFI signal IEEE 802.11n 2447 MHz (20MHz mode)  55.6  dB PoutMax Maximum output power Measured with Wide Band Power Meter  15.1  dBm Pout Output power in band tilt At +10 dBm  0.3  dB At +15 dBm  0.3  dB  45.7  dB With IEEE 802.15.4 channel at +10 dBm  6.3  % With IEEE 802.15.4 channel at +15 dBm  6.3  % Offset error vector magnitude With IEEE 802.15.4 channel at +10 dBm  0.33  % With IEEE 802.15.4 channel at +15 dBm  0.33  % Error Vector Magnitude With proprietary mode at +10 dBm  23.2  % With proprietary mode at +15 dBm  24.9  % With proprietary mode at +10 dBm  3.2  % With proprietary mode at +15 dBm  3.7  % RejWIFI Transmitter PoutRange Output power control range EVM Error vector magnitude OEVM EVMProp OEVMProp Offset error Vector Magnitude K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 72 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 43. Radio transceiver characteristics: +25 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions PSD Power spectral density PSDProp TXH2 TXH3 Min Typ Max Unit Relative density at greater than 3.5 MHz offset as per IEEE 802.15.4 at +10 dBm  -37.4  dBc Absolute density at greater than 3.5 MHz offset at +10 dBm as per IEEE 802.15.4 at +10 dBm  -38.2  dBm Relative density at greater than 3.5 MHz offset as per IEEE 802.15.4 at +15 dBm  -37.4  dBc Absolute density at greater than 3.5 MHz offset at +10 dBm as per IEEE 802.15.4 at +15 dBm  -33.2  dBm Proprietary mode power Relative density at greater than 3.5 MHz spectral density offset with proprietary mode at +10 dBm  -61.2  dBc Absolute density at greater than 3.5 MHz offset with proprietary mode at +10 dBm  -62.2  dBm Relative density at greater than 3.5 MHz offset with proprietary mode at +15 dBm  -61.2  dBc Absolute density at greater than 3.5 MHz offset with proprietary mode at +15 dBm  -57.5  dBm With IEEE 802.15.4 channel at +10 dBm  -62.4  dBm/ MHz With IEEE 802.15.4 channel at +15 dBm  -54  dBm/ MHz With IEEE 802.15.4 channel at +10 dBm  -73  dBm/ MHz With IEEE 802.15.4 channel at +15 dBm  -61  dBm/ MHz 2nd Harmonic of Transmit Carrier Frequency 3rd Harmonic of Transmit Carrier Frequency K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 73 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 43. Radio transceiver characteristics: +25 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions PspTX Transmitter spurious emission, measured conducted into 50 ohms Transmitter spurious emission, ETSI exceptions K32W041A/K32W041AM Product data sheet Min Typ Max Unit 30 MHz to 1 GHz, Peak detector, RBW=100 kHz  -80  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC at +10 dBm  -22.1  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC with proprietary mode at +10 dBm  -37.1  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI at +10 dBm  -39.8  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI with proprietary mode at +10 dBm  -44  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz, based on FCC at +10 dBm  -27.9  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz with proprietary mode, based on FCC at +10 dBm  -45.3  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC at +15 dBm  -16.9  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC with proprietary mode at +15 dBm  -33  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI at +15 dBm  -39.1  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI with proprietary mode at +15 dBm  -39.2  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz, based on FCC at +15 dBm  -23.7  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz with proprietary mode, based on FCC at +15 dBm  -45.1  dBm 1.8 GHz to 1.9 GHz  -58  dBm 5.15 GHz to 5.3 GHz  -56.4  dBm [1] Considering an integrated BW of 2 MHz, and a minimum SNR of 4 dB for the demodulator. [2] Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a modulated interferer as per IEEE 802.15.4. [3] Proprietary mode interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a proprietary mode interferer. [4] CW Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a CW interferer. [5] The intermodulation protection level is the difference between the wanted channel power and one of the two interferers power. Both interferers are modulated as per IEEE 802.15.4 and have the same power. [6] This RSSI variation over temperature is obtained with the use of the embedded thermometer and the integrated API (see application note). All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 74 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 44. Radio transceiver characteristics: -40 °C VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Receiver sensitivity 1 % PER, as per IEEE 802.15.4  101.3  dBm  5.7  dB   10 dBm  -2  dB Adjacent -5 MHz  35.9  dB Adjacent +5 MHz  35.8  dB Alternate -10 MHz  46.5  dB Alternate +10 MHz  46.6  dB -15 MHz  51.6  dB Receiver SRX [1] NF Noise Figure Max gain PinMaxRX Maximum receiver input power 1 % PER, measured as sensitivity Coch Co-channel Interference 1 % PER, with wanted signal 3 dB, above rejection sensitivity as per IEEE 802.15.4 Rej-5M Interference rejection, 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[2] Rej+5M Rej-10M Rej+10M Rej-15M Rej+15M RejProp-5M RejProp+5M RejProp-10M RejProp+10M RejProp-15M Proprietary mode interference rejection. 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[3] RejProp+15M RejCW-5M RejCW+5M RejCW-10M RejCW+10M CW interference rejection. 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[4] RejCW-15M [2] +15 MHz  52.1  dB Adjacent -5 MHz  56.4  dB Adjacent +5 MHz  60.4  dB Alternate -10 MHz  60.6  dB Alternate +10 MHz  61.3  dB -15 MHz  56.5  dB +15 MHz  59.2  dB Adjacent -5 MHz  56.8  dB Adjacent +5 MHz  60.4  dB Alternate -10 MHz  60.4  dB Alternate +10 MHz  60.9  dB -15 MHz  59.9  dB +15 MHz  60.7  dB RejOOB Out-of-band rejection 1 % PER with wanted signal 3 dB above sensitivity, CW interferers at 868 MHz (KNX), RF/2, 2100 MHz (WCDMA), 2500 MHz (LTE), or RF/3 (3GPP-Japan)  61.7  dB IMP2,4 Inter-modulation protection 1% PER with wanted signal 3 dB above sensitivity, modulated interferers at 2 and 4 channels separation [5]  42.5  dB 1% PER with wanted signal 3 dB above sensitivity, modulated interferers at 3 and 6 channels separation [5]  46.5  dB RejCW+15M IMP3,6 K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 75 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 44. Radio transceiver characteristics: -40 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter PinBlockin Blocking input power g Conditions Min Typ Max Unit Desired channel IEEE 802.15.4, level = measured sensitivity + 6dB, channels 11 & 26. Unwanted channel CW at 2380 MHz or 2503.5 MHz  -22  dBm Desired channel IEEE 802.15.4, level = measured sensitivity + 6dB, channels 11 & 26. Unwanted channel CW at 2300 MHz, 2330 MHz & 2360 MHz  -21.2  dBm Desired channel IEEE 802.15.4, level = measured sensitivity + 6dB, channels 11 & 26. Unwanted channel CW at 2523.5 MHz, 2553.5 MHZ, 2583.5 MHz, 2613.5 MHz, 2643.5 MHz, 2673.5 MHz  -20.4  dBm  2  dB [6] RSSIvar RSSI variation Desired channel IEEE 802.15.4, over the RSSI range -101 dBm to +9 dBm PspRX Receiver spurious emission, measured conducted into 50 ohms 30 MHz to 1 GHz, 100 kHz RBW, 300 kHz VBW, Filter type 3 dB (Gaussian), Peak detector, Trace Mode Max hold  -83.3  dBm 1 GHz to 12.75 GHz, 1 MHz RBW, 3MHz VBW, Filter type 3dB (Gaussian), Peak detector, Trace mode Max hold  -62.7  dBm  -98  dBm LOLeakRX Local oscillator leakage power WIFI rejection 1 % PER, with wanted signal IEEE 802.15.4 -75 dBm 2470 MHz, WIFI signal IEEE 802.11n 2447 MHz (20MHz mode)  53.7  dB PoutMax Maximum output power Measured with Wide Band Power Meter  15.5  dBm Pout Output power in band tilt at +10 dBm  0.3  dB at +15 dBm  0.3  dB  46.6  dB With IEEE 802.15.4 channel at +10 dBm  6.6  % With IEEE 802.15.4 channel at +15 dBm  6.0  % Offset error vector magnitude With IEEE 802.15.4 channel at +10 dBm  0.36  % With IEEE 802.15.4 channel at +15 dBm  0.30  % Error Vector Magnitude With proprietary mode at +10 dBm  22.5  % With proprietary mode at +15 dBm  23.2  % With proprietary mode at +10 dBm  3.1  % With proprietary mode at +15 dBm  3.1  % RejWIFI Transmitter PoutRange Output power control range EVM Error vector magnitude OEVM EVMProp OEVMProp Offset error Vector Magnitude K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 76 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 44. Radio transceiver characteristics: -40 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions PSD Power spectral density PSDProp TXH2 TXH3 Min Typ Max Unit Relative density at greater than 3.5 MHz offset as per IEEE 802.15.4 at +10 dBm  -37.3  dBc Absolute density at greater than 3.5 MHz offset at +10 dBm as per IEEE 802.15.4 at +10 dBm  -37.7  dBm Relative density at greater than 3.5 MHz offset as per IEEE 802.15.4 at +15 dBm  -37.3  dBc Absolute density at greater than 3.5 MHz offset at +10 dBm as per IEEE 802.15.4 at +15 dBm  -32.7  dBm Proprietary mode power Relative density at greater than 3.5 MHz spectral density offset with proprietary mode at +10 dBm  -61.2  dBc Absolute density at greater than 3.5 MHz offset with proprietary mode at +10 dBm  -61.9  dBm Relative density at greater than 3.5 MHz offset with proprietary mode at +15 dBm  -61.2  dBc Absolute density at greater than 3.5 MHz offset with proprietary mode at +15 dBm  -57.3  dBm 2nd Harmonic of Transmit Carrier Frequency With IEEE 802.15.4 channel at +10 dBm  -61.6  dBm/ MHz With IEEE 802.15.4 channel at +15 dBm  -54.5  dBm/ MHz 3rd Harmonic of Transmit Carrier Frequency With IEEE 802.15.4 channel at +10 dBm  -73  dBm/ MHz With IEEE 802.15.4 channel at +15 dBm  -62.5  dBm/ MHz K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 77 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 44. Radio transceiver characteristics: -40 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions PspTX Transmitter spurious emission, measured conducted into 50 ohms Transmitter spurious emission, ETSI exceptions K32W041A/K32W041AM Product data sheet Min Typ Max Unit 30 MHz to 1 GHz, Peak detector, RBW=100kHz  -76.7  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC at +10 dBm  -21.6  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC with proprietary mode at +10 dBm  -37.3  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI at +10 dBm  -39.6  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI with proprietary mode at +10 dBm  -44  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz, based on FCC at +10 dBm  -27.3  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz with proprietary mode, based on FCC at +10 dBm  -46.1  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC at +15 dBm  -17.1  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC with proprietary mode at +15 dBm  -32.5  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI at +15 dBm  -39.1  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI with proprietary mode at +15 dBm  -38.9  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz, based on FCC at +15 dBm  -23.8  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz with proprietary mode, based on FCC at +15 dBm  -45.1  dBm 1.8 GHz to 1.9 GHz  -58.4  dBm 5.15 GHz to 5.3 GHz  -56.8  dBm [1] Considering an integrated BW of 2 MHz, and a minimum SNR of 4 dB for the demodulator. [2] Interference rejection is defined as the value, when 1% PER is seen with the wanted signal 3 dB above sensitivity, with a modulated interferer as per IEEE 802.15.4. [3] Proprietary mode interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a proprietary mode interferer. [4] CW Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a CW interferer. [5] The intermodulation protection level is the difference between the wanted channel power and one of the two interferers power. Both interferers are modulated as per IEEE 802.15.4 and have the same power. [6] This RSSI variation over temperature is obtained with the use of the embedded thermometer and the integrated API (see application note). All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 78 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 45. Radio transceiver characteristics: +85 °C VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions receiver sensitivity 1 % PER, as per IEEE 802.15.4 Min Typ Max Unit  97.1  dBm  9.9  dB   10 dBm  -2.4  dB Receiver SRX [1] NF Noise Figure Max gain PinMaxRX Maximum receiver input power 1 % PER, measured as sensitivity Coch Co-channel Interference rejection 1 % PER, with wanted signal 3 dB, above sensitivity as per IEEE 802.15.4 Rej-5M Interference rejection, 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[2] Adjacent -5 MHz  35.4  dB Adjacent +5 MHz  35.8  dB Alternate -10 MHz  46.3  dB Alternate +10 MHz  46.5  dB -15 MHz  51.7  dB +15 MHz  52.1  dB Adjacent -5 MHz  54.7  dB Adjacent +5 MHz  56.8  dB Alternate -10 MHz  59.9  dB Alternate +10 MHz  63.3  dB -15 MHz  60.3  dB +15 MHz  65.4  dB Adjacent -5 MHz  56.1  dB Adjacent +5 MHz  57.6  dB Alternate -10 MHz  62.9  dB Alternate +10 MHz  64  dB -15 MHz  62.3  dB Rej+5M Rej-10M Rej+10M Rej-15M Rej+15M RejProp-5M RejProp+5M RejProp-10M RejProp+10M RejProp-15M Proprietary mode interference rejection. 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[3] RejProp+15M RejCW-5M RejCW+5M RejCW-10M RejCW+10M CW interference rejection. 1% PER, with wanted signal 3 dB above sensitivity as per IEEE 802.15.4[4] RejCW-15M [2] +15 MHz  65.3  dB RejOOB Out-of-band rejection 1 % PER with wanted signal 3 dB above sensitivity, CW interferers at 868 MHz (KNX), RF/2, 2100 MHz (WCDMA), 2500 MHz (LTE), or RF/3 (3GPP-Japan)  60.8  dB IMP2,4 Inter-modulation protection 1% PER with wanted signal 3 dB above sensitivity, modulated interferers at 2 and 4 channels separation [5]  44.8  dB 1% PER with wanted signal 3 dB above sensitivity, modulated interferers at 3 and 6 channels separation [5]  47  dB RejCW+15M IMP3,6 K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 79 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 45. Radio transceiver characteristics: +85 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit PinBlocking Blocking input power Desired channel IEEE 802.15.4, level = measured sensitivity + 6 dB, channels 11 & 26. Unwanted channel CW at 2380 MHz or 2503.5 MHz  -20  dBm Desired channel IEEE 802.15.4, level = measured sensitivity + 6 dB, channels 11 & 26. Unwanted channel CW at 2300 MHz, 2330 MHz & 2360 MHz  -17.2  dBm Desired channel IEEE 802.15.4, level = measured sensitivity + 6dB, channels 11 & 26. Unwanted channel CW at 2523.5 MHz, 2553.5 MHZ, 2583.5 MHz, 2613.5 MHz, 2643.5 MHz, 2673.5 MHz  -16.3  dBm  2  dB [6] RSSIvar RSSI variation Desired channel IEEE 802.15.4, over the RSSI range -97 dBm to +5 dBm PspRX Receiver spurious emission, Measured conducted into 50 ohms 30 MHz to 1 GHz, 100 kHz RBW, 300 kHz VBW, Filter type 3 dB (Gaussian), Peak detector, Trace Mode Max hold  -87.7  dBm 1 GHz to 12.75 GHz, 1 MHz RBW, 3MHz VBW, Filter type 3dB (Gaussian), Peak detector, Trace mode Max hold  -64.9  dBm  -98  dBm LOLeakRX Local oscillator leakage power RejWIFI WIFI rejection 1 % PER, with wanted signal IEEE 802.15.4 -75 dBm 2470 MHz, WIFI signal IEEE 802.11n 2447 MHz (20MHz mode)  51.1  dB PoutMax Maximum output power Measured with Wide Band Power Meter  14.6  dBm Pout Output power in band tilt At +10 dBm  0.3  dB At +15 dBm  0.3  dB Transmitter PoutRange Output power control range  46.8  dB EVM Error vector magnitude With IEEE 802.15.4 channel at +10 dBm  6.6  % With IEEE 802.15.4 channel at +15 dBm  6.2  % With IEEE 802.15.4 channel at +10 dBm  0.36  % With IEEE 802.15.4 channel at +15 dBm  0.36  % OEVM EVMProp OEVMProp Offset error vector magnitude Error Vector Magnitude With proprietary mode at +10 dBm  23  % With proprietary mode at +15 dBm  23  % With proprietary mode at +10 dBm  3.2  % With proprietary mode at +15 dBm  3.2  % Offset error Vector Magnitude K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 80 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 45. Radio transceiver characteristics: +85 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter PSD PSDProp TXH2 TXH3 Min Typ Max Unit Power spectral density Relative density at greater than 3.5 MHz offset as per IEEE 802.15.4 at +10 dBm  -37.5  dBc Absolute density at greater than 3.5 MHz offset at +10 dBm as per IEEE 802.15.4 at +10 dBm  -39.5  dBm Relative density at greater than 3.5 MHz offset as per IEEE 802.15.4 at +15 dBm  -37.5  dBc Absolute density at greater than 3.5 MHz offset at +10 dBm as per IEEE 802.15.4 at +15 dBm  -33.7  dBm Proprietary mode Relative density at greater than 3.5 power spectral density MHz offset with proprietary mode at +10 dBm  -60.6  dBc Absolute density at greater than 3.5 MHz offset with proprietary mode at +10 dBm  -62.8  dBm Relative density at greater than 3.5 MHz offset with proprietary mode at +15 dBm  -60.6  dBc Absolute density at greater than 3.5 MHz offset with proprietary mode at +15 dBm  -57.4  dBm 2nd Harmonic of Transmit Carrier Frequency With IEEE 802.15.4 channel at +10 dBm  -63.3  dBm/M Hz With IEEE 802.15.4 channel at +15 dBm  -56.4  dBm/M Hz 3rd Harmonic of Transmit Carrier Frequency With IEEE 802.15.4 channel at +10 dBm  -73  dBm/M Hz With IEEE 802.15.4 channel at +15 dBm  -63.6  dBm/M Hz K32W041A/K32W041AM Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 81 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 45. Radio transceiver characteristics: +85 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions PspTX Transmitter spurious emission, measured conducted into 50 ohms Transmitter spurious emission, ETSI exceptions K32W041A/K32W041AM Product data sheet Min Typ Max Unit 30 MHz to 1 GHz, Peak detector, RBW=100kHz  -76.3  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC at +10 dBm  -23.3  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC with proprietary mode at +10 dBm  -39  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI at +10 dBm  -41.3  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI with proprietary mode at +10 dBm  -44.3  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz, based on FCC at +10 dBm  -29.2  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz with proprietary mode, based on FCC at +10 dBm  -46.3  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC at +15 dBm  -18.4  dBm 1 GHz to 26 GHz, Peak detector, RBW 1MHz, based on FCC with proprietary mode at +15 dBm  -35.3  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI at +15 dBm  -42.4  dBm 1 GHz to 12.75 GHz, Peak detector, RBW 1MHz, based on ETSI with proprietary mode at +15 dBm  -42.1  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz, based on FCC at +15 dBm  -25.6  dBm 1 GHz to 26 GHz, Average detector, RBW = 1 MHz with proprietary mode, based on FCC at +15 dBm  -46.9  dBm 1.8 GHz to 1.9 GHz  -57.9  dBm 5.15 GHz to 5.3 GHz  -56.7  dBm [1] Considering an integrated BW of 2 MHz, and a minimum SNR of 4 dB for the demodulator. [2] Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a modulated interferer as per IEEE 802.15.4. [3] Proprietary mode interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a proprietary mode interferer. [4] CW Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, with a CW interferer. [5] The intermodulation protection level is the difference between the wanted channel power and one of the two interferers power. Both interferers are modulated as per IEEE 802.15.4 and have the same power. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 82 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM [6] This RSSI variation over temperature is obtained with the use of the embedded thermometer and the integrated API (see application note). 14.15 Radio transceiver (Bluetooth Low Energy) This K32W041A/K32W041AM meets all the requirements of the Bluetooth Low Energy standard over 2.4 V to 3.6 V and offers the improved RF characteristics shown in Table 43. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, when used with NXP’s Module Reference Designs. Compliant with FCC part 15 rules, IC Canada and ETSI ETS 300-328, refer to the K32W041A/K32W041AM Module Reference Design package on the Wireless Connectivity area of the NXP web site Ref. 2. The PCB schematic and layout rules detailed in Section 9 “Application design-in information” must be followed. Failure to do so will likely result in the K32W041A/K32W041AM failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. Table 46. RF port characteristics Single-ended; Impedance = 50 Ω; VDD = 2.4 V to 3.6 V; Tamb = -40°C to +85°C; unless otherwise specified. Symbol Parameter Min Typ Max Unit Frange Frequency range 2.4  2.485 GHz Table 47. Radio transceiver characteristics: +25 °C VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit  97  dBm  7  dB   10 dBm  -7  dB Channel -1 MHz  2.5  dB Channel +1 MHz  5.2  dB Channel -2 MHz  29  dB Channel +2 MHz  44  dB Channel  -3 MHz  36  dB Channel  +3 MHz  46  dB Receiver Bluetooth Low Energy 1 Mb/s SRX_BLE_1 Receiver sensitivity 0.1% BER M NF_BLE_1 Noise figure M Max gain PinMaxRX_B Maximum receiver input power LE_1M 0.1% BER [1] Coch_BLE_1 Co-channel Interference 0.1% BER, with wanted channel at -67 dBm rejection M Rej-1M_BLE_ Interference rejection, 0.1% BER, with wanted 1M channel at -67 dBm[2] R ej+1M_BLE [2] _1M Rej-2M_BLE_ 1M Rej+2M_BLE _1M Rej-3M_BLE_ 1M Rej+3M_BLE _1M K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 83 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 47. Radio transceiver characteristics: +25 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter RejOOB_BLE Out-of-band blocking _1M Conditions From 30 MHz to 2000 MHz, wanted channel Bluetooth Low Energy 1 Mb/s at -67 dBm, 0.1% BER, CW interferer. From 2003 MHz to 2399 MHz and 2484 MHz to 2999 MHz, wanted signal at -67 dBm, 0.1% BER, CW interferer. [3] From 3000 MHz to 12750 MHz, wanted signal at -67 dBm, 0.1% BER, CW interferer. Min Typ Max Unit  0  dBm  0  dBm  0  dBm With CW interferer at ± 3 MHz and Bluetooth Low Energy interferer 1 Mb/s at ± 6 MHz, wanted channel Bluetooth Low Energy 1 Mb/s at -64 dBm, 0.1% BER [4]  -27  dBm IMP4,8_B LE_1M With CW interferer at ± 4 MHz and Bluetooth Low Energy interferer 1 Mb/s at ± 8 MHz, wanted channel Bluetooth Low Energy 1 Mb/s at -64 dBm, 0.1% BER [4]  -29  dBm IMP5,10_ BLE_1M With CW interferer at ± 5 MHz and Bluetooth Low Energy interferer 1 Mb/s at ± 10 MHz, wanted channel Bluetooth Low Energy 1 Mb/s at -64 dBm, 0.1% BER [4]  -30  dBm Desired channel Bluetooth Low Energy 1 Mb/s, level = measured sensitivity + 6dB. Unwanted channel CW at 2380 MHz, or 2503.5 MHz  -24  dBm Desired channel Bluetooth Low Energy 1 Mb/s, level = measured sensitivity + 6dB, channels 0 and 39. Unwanted channel CW at 2300 MHz, 2330 MHz, or 2360 MHz  -21  dBm Desired channel Bluetooth Low Energy 1 Mb/s, level = measured sensitivity + 6dB, channels 0 and 39. Unwanted channel CW at 2523.5 MHz, 2553.5 MHZ, 2583.5 MHz, 2613.5 MHz, 2643.5 MHz, or 2673.5 MHz  -19  dBm  2  dB 30 MHz to 1 GHz, 100 kHz RBW, 300 kHz VBW, filter type 3 dB (Gaussian), peak detector, trace mode Max hold  -80  dBm 1 GHz to 12.75 GHz, 1 MHz RBW, 3 MHz VBW, filter type 3 dB (Gaussian), peak detector, trace mode Max hold  -67  dBm  -98  dBm  42  dB IMP3,6_B LE_1M PinBlock_ BLE_1M RSSIvar_ BLE_1M Inter-modulation Blocking input power RSSI variation PspRX_BL Receiver spurious E_1M emission, measured conducted into 50 ohms Desired channel Bluetooth Low Energy 1 Mbps, over the RSSI range -97 dBm to +5 dBm LOLeakRX Local oscillator leakage _BLE_1M power RejWIFI_BLE WIFI rejection _1M 0.1% BER, with wanted signal Bluetooth Low Energy 1 Mb/s -67 dBm 2470 MHz, WIFI signal IEEE 802.11n 2447 MHz (20 MHz mode) [5] Transmitter Bluetooth Low Energy 1 Mb/s K32W041A/K32W041AM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — April 2022 © NXP B.V. 2021-2022. All rights reserved. 84 of 115 NXP Semiconductors IEEE 802.15.4 and Bluetooth Low Energy 5.0 wireless MCU K32W041A/K32W041AM Table 47. Radio transceiver characteristics: +25 °C …continued VDDE = 2.4 V to 3.6 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit PoutMax_BL Maximum output power Measured with CMWxxx equipment  14.3  dBm Output power in band tilt At +10 dBm  0.2  dB At +15 dBm  0.2  dB PoutRange_B Output power control range LE_1M  47.3  dB TxAdj2M_ BLE_1M Bluetooth Low Energy adjacent channel transmit Power at 2 MHz offset  -43.7  dBm TxAdj3M_ BLE_1M Bluetooth Low Energy adjacent channel transmit Power at  3 MHz offset  -46.6  dBm f1avg_BL Average frequency E_1M deviation using a 00001111 sequence  249  kHz f299_9_B 99.9% of absolute peak LE_1M frequency deviation using a 10101010 sequence  207  kHz f2avg/Δf1 Ratio of average avg_BLE_ frequency deviation 1M using a 10101010 sequence, and average frequency deviation using a 00001111 sequence  0.9  CFO_BLE Carrier frequency offset _1M  25  kHz FD_BLE_1 Frequency drift M  -12  kHz MaxFD_B LE_1M Maximum drift rate  -1  kHz InitFD_BL E_1M Initial frequency drift  -9.8  kHz TXH2_1M Second harmonic of transmit carrier frequency With Bluetooth Low Energy 1 Mb/s channel at +10 dBm  -61.5  dBm With Bluetooth Low Energy 1 Mb/s channel at +15 dBm  -53.7  dBm With Bluetooth Low Energy 1 Mb/s channel at +10 dBm 