Freescale Semiconductor
Document Number: MPC8272EC
Rev. 3, 09/2011
Technical Data
MPC8272
PowerQUICC II Family
Hardware Specifications
This document contains detailed information about power
considerations, DC/AC electrical characteristics, and AC
timing specifications for .13µm (HiP7) members of the
PowerQUICC II family of integrated communications
processors—the MPC8272, the MPC8248, the MPC8271,
and the MPC8247. They include on a single chip a 32-bit
Power Architecture® core that incorporates memory
management units (MMUs) and instruction and data caches
and that implements the Power Architecture instruction set;
a modified communications processor module (CPM); and
an integrated security engine (SEC) for encryption (the
MPC8272 and the MPC8248 only).
All four devices are collectively referred to throughout this
hardware specification as “the MPC8272” unless otherwise
noted.
© 2011 Freescale Semiconductor, Inc. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 14
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 18
Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 27
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 56
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 58
Document Revision History . . . . . . . . . . . . . . . . . . . 58
Overview
1
Overview
This table shows the functionality supported by each SoC in the MPC8272 family.
Table 1. MPC8272 PowerQUICC II Family Functionality
SoCs
Functionality
MPC8272
MPC8248
Package1
Serial communications controllers (SCCs)
MPC8271
MPC8247
516 PBGA
3
3
3
3
QUICC multi-channel controller (QMC)
Yes
Yes
Yes
Yes
Fast communication controllers (FCCs)
2
2
2
2
I-Cache (Kbyte)
16
16
16
16
D-Cache (Kbyte)
16
16
16
16
Ethernet (10/100)
2
2
2
2
UTOPIA II Ports
1
0
1
0
Multi-channel controllers (MCCs)
0
0
0
0
PCI bridge
Yes
Yes
Yes
Yes
Transmission convergence (TC) layer
—
—
—
—
Inverse multiplexing for ATM (IMA)
—
—
—
—
Universal serial bus (USB) 2.0 full/low rate
1
1
1
1
Yes
Yes
—
—
Security engine (SEC)
1
See Table 2.
Devices in the MPC8272 family are available in two packages—the VR or ZQ package—as shown in .
For package ordering information, see Section 10, “Ordering Information.”
Table 2. MPC8272 PowerQUICC II Device Packages
Code
(Package)
VR
(516 PBGA—Lead free)
ZQ
(516 PBGA—Lead spheres)
MPC8272VR
MPC8272ZQ
MPC8248VR
MPC8248ZQ
MPC8271VR
MPC8271ZQ
MPC8247VR
MPC8247ZQ
Device
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
2
Freescale Semiconductor
Overview
This figure shows the block diagram of the SoC.
16 KB
I-Cache
Security (SEC)1
I-MMU
System Interface Unit
(SIU)
G2_LE Core
16 KB
D-Cache
Bus Interface Unit
D-MMU
60x-to-PCI
Bridge
60x Bus
PCI Bus
32 bits, up to 66 MHz
Memory Controller
Communication Processor Module (CPM)
Timers
Parallel I/O
4 KB
Interrupt
Instruction
Controller
RAM
Serial
DMA
32-bit RISC Microcontroller
and Program ROM
Baud Rate
Generators
FCC1
Clock Counter
16 KB
Data
RAM
FCC2
SCC1
SCC3
System Functions
Virtual
IDMAs
SCC4
SMC1
SMC2
SPI
I2C
USB 2.0
Time Slot Assigner
Serial interface
Serial Interface
2 TDM Ports
2 MII/RMII
Ports
1 8-bit Utopia
Port2
Non-Multiplexed
I/O
Notes:
1 MPC8272/8248 only
2 MPC8272/8271 only
Figure 1. SoC Block Diagram
1.1
Features
The major features of the SoC are as follows:
• Dual-issue integer (G2_LE) core
— A core version of the MPC603e microprocessor
— System core microprocessor supporting frequencies of 266–400 MHz
— Separate 16 KB data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— Power Architecture®-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— Supports bus snooping for cache coherency
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
3
Overview
•
•
•
•
•
•
•
•
— Floating-point unit (FPU) supports floating-point arithmetic
— Support for cache locking
Low-power consumption
Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)
Separate PLLs for G2_LE core and for the communications processor module (CPM)
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,
5.5:1, 6:1, 7:1, 8:1
— Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1
ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs—up to two external masters
— Supports single transfers and burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
– PCI-to-60x address remapping
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Eight bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other
user-definable peripherals
— Byte write enables
— 32-bit address decodes with programmable bank size
— Three user-programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
— Byte selects for 64-bit bus width (60x)
— Dedicated interface logic for SDRAM
Disable CPU mode
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
•
•
•
Integrated security engine (SEC) (MPC8272 and MPC8248 only)
— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms
in hardware
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port
RAM size is 16 KB plus 4 KB dedicated instruction RAM.)
— Microcode tracing capabilities
— Eight CPM trap registers
Universal serial bus (USB) controller
— Supports USB 2.0 full/low rate compatible
— USB host mode
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
— Supports USB slave mode
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Two fast communication controllers (FCCs) supporting the following protocols:
– 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—up to T3 rates (clear channel)
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
5
Overview
—
—
—
—
—
—
—
– One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155
Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0
CBR, VBR, UBR, ABR traffic types, up to 64-K external connections
Three serial communications controllers (SCCs) identical to those on the MPC860 supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BiSync) communications
– Transparent
– QUICC multichannel controller (QMC) up to 64 channels
• Independent transmit and receive routing, frame synchronization.
• Serial-multiplexed (full-duplex) input/output 2048, 1544, and 1536 Kbps PCM
highways
• Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN
basic rate, ISDN primary rate, and user defined.
• Subchanneling on each time slot.
• Independent transmit and receive routing, frame synchronization and clocking
• Concatenation of any not necessarily consecutive time slots to channels independently
for receiver/transmitter
• Supports H1,H11, and H12 channels
• Allows dynamic allocation of channels
– SCC3 in NMSI mode is not usable when USB is enabled.
Two serial management controllers (SMCs), identical to those of the MPC860
– Provides management for BRI devices as general-circuit interface (GCI) controllers in
time-division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
One serial peripheral interface identical to the MPC860 SPI
One I2C controller (identical to the MPC860 I2C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
Up to two TDM interfaces
– Supports one groups of two TDM channels
– 1024 bytes of SI RAM
Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC,
SCC, SMC, and USB serial channels
Four independent 16-bit timers that can be interconnected as two 32-bit timers
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
Operating Conditions
•
2
PCI bridge
— PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI host bridge or peripheral capabilities
— Includes four DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes the configuration registers required by the PCI standard (which are automatically
loaded from the EPROM to configure the MPC8272) and message and doorbell registers
— Supports the I2O standard
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port
Operating Conditions
This table shows the maximum electrical ratings.
Table 3. Absolute Maximum Ratings1
Rating
Symbol
Value
Unit
VDD
–0.3 – 2.25
V
VCCSYN
–0.3 – 2.25
V
I/O supply voltage3
VDDH
–0.3 – 4.0
V
voltage4
VIN
GND(–0.3) – 3.6
V
Tj
120
°C
TSTG
(–55) – (+150)
°C
Core supply voltage2
PLL supply
Input
voltage2
Junction temperature
Storage temperature range
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 4) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended that
VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may
exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.
3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
7
Operating Conditions
This table lists recommended operational voltage conditions.
Table 4. Recommended Operating Conditions1
Rating
Symbol
Value
Unit
Core supply voltage
VDD
1.425 – 575
V
PLL supply voltage
VCCSYN
1.425 – 575
V
I/O supply voltage
VDDH
3.135 – 3.465
V
VIN
GND (–0.3) – 3.465
V
Junction temperature (maximum)
Tj
1052
°C
Ambient temperature
TA
0–702
°C
Input voltage
1
Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions
is not guaranteed.
2 Note that for extended temperature parts the range is (-40) – 105 .
T
Tj
A
This SoC contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or VCC).
This figure shows the undershoot and overshoot voltage of the 60x bus memory interface of the SoC. Note
that in PCI mode the I/O interface is different.
VIH
VIL
4V
GVDD + 5%
GVDD
GND
GND – 0.3 V
GND – 1.0 V
Not to exceed 10%
of tSDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
8
Freescale Semiconductor
DC Electrical Characteristics
3
DC Electrical Characteristics
This table shows DC electrical characteristics.
Table 5. DC Electrical Characteristics1
Characteristic
Input high voltage—all inputs except TCK, TRST and
Input low voltage
3
CLKIN input high voltage
CLKIN input low voltage
Input leakage current, VIN =
VDDH4
Hi-Z (off state) leakage current, VIN = VDDH
2
PORESET2
Symbol
Min
Max
Unit
VIH
2.0
3.465
V
VIL
GND
0.8
V
VIHC
2.4
3.465
V
VILC
GND
0.4
V
IIN
—
10
µA
IOZ
—
10
µA
Signal low input current, V IL = 0.8 V
IL
—
1
µA
Signal high input current, VIH = 2.0 V
IH
—
1
µA
VOH
2.4
—
V
VOL
—
0.5
V
Output high voltage, IOH = –2 mA
except UTOPIA mode, and open drain pins
In UTOPIA mode5 (UTOPIA pins only): IOH = -8.0mA
PA[8–31]
PB[18–31]
PC[0–1,4–29]
PD[7–25, 29–31]
In UTOPIA mode5 (UTOPIA pins only): IOL = 8.0mA
PA[8–31]
PB[18–31]
PC[0–1,4–29]
PD[7–25, 29–31]
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
9
DC Electrical Characteristics
Table 5. DC Electrical Characteristics1 (continued)
Characteristic
IOL = 6.0mA
BR
BG/IRQ6
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG/IRQ7
DBB/IRQ3
D[0–63]
IRQ3/CKSTP_OUT/EXT_BR3
IRQ4/CORE_SRESET/EXT_BG3
IRQ5/TBEN/EXT_DBG3/CINT
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
BADDR31/IRQ5/CINT
CPU_BR/INT_OUT
IRQ0/NMI_OUT
PORESET/PCI_RST
HRESET
SRESET
RSTCONF
Symbol
Min
Max
Unit
VOL
—
0.4
V
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
DC Electrical Characteristics
Table 5. DC Electrical Characteristics1 (continued)
Characteristic
IOL = 5.3mA
CS[0–5]
CS6/BCTL1/SMI
CS7/TLBSYNC
BADDR27/ IRQ1
BADDR28/ IRQ2
ALE/ IRQ4
BCTL0
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4
PSDAMUX/PGPL5
PCI_CFG0 (PCI_HOST_EN)
PCI_CFG1 (PCI_ARB_EN)
PCI_CFG2 (DLL_ENABLE)
MODCK1/RSRV/TC(0)/BNKSEL(0)
MODCK2/CSE0/TC(1)/BNKSEL(1)
MODCK3CSE1/TC(2)/BNKSEL(2)
IOL = 3.2mA
PCI_PAR
PCI_FRAME
PCI_TRDY
PCI_IRDY
PCI_STOP
PCI_DEVSEL
PCI_IDSEL
PCI_PERR
PCI_SERR
PCI_REQ0
PCI_REQ1/ CPI_HS_ES
PCI_GNT0
PCI_GNT1/ CPI_HS_LES
PCI_GNT2/ CPI_HS_ENUM
PCI_RST
PCI_INTA
PCI_REQ2
DLLOUT
PCI_AD(0-31)
PCI_C(0–3)/BE(0-3)
PA[8–31]
PB[18–31]
PC[0–1,4–29]
PD[7–25, 29–31]
TDO
Symbol
Min
Max
Unit
VOL
—
0.4
V
1
The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent
excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs.
2 TCK, TRST and PORESET have min VIH = 2.5V.
3 V for IIC interface does not match IIC standard, but does meet IIC standard for V
IL
OL and should not cause any compatibility
issue.
4
The leakage current is measured for nominal VDDH,VCCSYN, and VDD.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
11
DC Electrical Characteristics
5
MPC8272 and MPC8271 only.
Table 6.
Characteristic
Symbol
Min
Max
Unit
Input high voltage—all inputs except TCK, TRST and PORESET1
VIH
2.0
3.465
V
Input low voltage
VIL
GND
0.8
V
CLKIN input high voltage
VIHC
2.4
3.465
V
CLKIN input low voltage
VILC
GND
0.4
V
Input leakage current, VIN = VDDH2
IIN
—
10
µA
Hi-Z (off state) leakage current, VIN = VDDH2
IOZ
—
10
µA
IL
—
1
µA
Signal low input current, V IL = 0.8
V3
Signal high input current, VIH = 2.0 V
IH
—
1
µA
VOH
2.4
—
V
In UTOPIA mode4 (UTOPIA pins only): IOL = 8.0mA
VOL
—
0.5
V
IOL = 6.0mA
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
//EXT_BR3
//EXT_BG3
/TBEN/EXT_DBG3/CINT
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
BADDR31/IRQ5/CINT
CPU_BR
IRQ0/NMI_OUT
/PCI_RST
HRESET
SRESET
RSTCONF
VOL
—
0.4
V
Output high voltage, IOH = –2 mA
except UTOPIA mode, and open drain pins
In UTOPIA mode4 (UTOPIA pins only): IOH = -8.0mA
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
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Freescale Semiconductor
DC Electrical Characteristics
Table 6.
Characteristic
IOL = 5.3mA
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
LWR
MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0–2]
IOL = 3.2mA
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTAL_A30/REQ2
L_A31
LCL_D[0-31)]/AD[0-31]
LCL_DP[03]/C/BE[0-3]
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
QREQ
Symbol
Min
Max
Unit
VOL
—
0.4
V
1
TCK, TRST and PORESET have min VIH = 2.5V.
The leakage current is measured for nominal VDDH,VCCSYN, and VDD.
3
VIL for IIC interface does not match IIC standard, but does meet IIC standard for VOL and should not cause any compatibility
issue.
2
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
13
Thermal Characteristics
4
MPC8280, MPC8275VR, MPC8275ZQ only.
4
Thermal Characteristics
This table describes thermal characteristics. See Table 2 for information on a given SoC’s package.
Discussions of each characteristic are provided in Section 4.1, “Estimation with Junction-to-Ambient
Thermal Resistance,” through Section 4.7, “References.” For the these discussions, PD = (VDD × IDD) +
PI/O, where PI/O is the power dissipation of the I/O drivers.
Table 7. Thermal Characteristics
Characteristic
Symbol
Value
Unit
27
Air Flow
Natural convection
Junction-to-ambient—
single-layer board1
RθJA
Junction-to-ambient—
four-layer board
RθJA
Junction-to-board2
RθJB
11
°C/W
—
Junction-to-case3
RθJC
8
°C/W
—
Junction-to-package top4
RθJT
2
°C/W
—
21
°C/W
19
16
1 m/s
Natural convection
°C/W
1 m/s
1
Assumes no thermal vias
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
3
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
4 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
2
4.1
Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, in
TJ = TA + (RθJA × PD)
C can be obtained from the following equation:
where:
TA = ambient temperature (ºC)
RθJA = package junction-to-ambient thermal resistance (ºC/W)
PD = power dissipation in package
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity TJ – TA) are possible.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
14
Freescale Semiconductor
Thermal Characteristics
4.2
Estimation with Junction-to-Case Thermal Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (ºC/W)
RθJC = junction-to-case thermal resistance (ºC/W)
RθCA = case-to-ambient thermal resistance (ºC/W)
RθJC is device related and cannot be influenced by the user. The user adjusts the thermal environment to
affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.
4.3
Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a
two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The
junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial
amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit board. It has
been observed that the thermal performance of most plastic packages, especially PBGA packages, is
strongly dependent on the board temperature.
If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:
TJ = TB + (RθJB × PD)
where:
RθJB = junction-to-board thermal resistance (ºC/W)
TB = board temperature (ºC)
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground
plane.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
15
Thermal Characteristics
4.4
Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two-resistor model can be used with the thermal simulation of the application, or a more accurate and
complex model of the package can be used in the thermal simulation.
4.5
Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
ΨJT = thermal characterization parameter
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge
type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is
placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple
wire.
4.6
Layout Practices
Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies.
Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins
drive distinct groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground
using bypass capacitors located as close as possible to the four sides of the package. For filtering high
frequency noise, a capacitor of 0.1uF on each VDD and VDDH pin is recommended. Further, for medium
frequency noise, a total of 2 capacitors of 47uF for VDD and 2 capacitors of 47uF for VDDH are also
recommended. The capacitor leads and associated printed circuit traces connecting to chip VDD, VDDH
and ground should be kept to less than half an inch per capacitor lead. Boards should employ separate inner
layers for power and GND planes.
All output pins on the SoC have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized to minimize overdamped conditions and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data buses. Maximum PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
16
Freescale Semiconductor
Power Dissipation
4.7
References
Semiconductor Equipment and Materials International(415) 964-5111
805 East Middlefield Rd.
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) Specifications800-854-7179 or
(Available from Global Engineering Documents)303-397-7956
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.
212–220.
5
Power Dissipation
This table provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required to ensure the junction temperature does not exceed the maximum
specified value. Also note that the I/O power should be included when determining whether to use a heat
sink. For a complete list of possible clock configurations, see Section 7, “Clock Configuration Modes.”
Table 8. Estimated Power Dissipation for Various Configurations1
PINT(W)2,3
Bus
(MHz)
CPM
Multiplication
Factor
CPM
(MHz)
CPU
Multiplication
Factor
CPU
(MHz)
Vddl 1.5 Volts
Nominal
Maximum
66.67
3
200
4
266
1
1.2
100
2
200
3
300
1.1
1.3
100
2
200
4
400
1.3
1.5
133
2
267
3
400
1.5
1.8
1
Test temperature = 105° C
PINT = IDD x VDD Watts
3 Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:
66.7 MHz = 0.35 W (nominal), 0.4 W (maximum)
83.3 MHz = 0.4 W (nominal), 0.5 W (maximum)
100 MHz = 0.5 W (nominal), 0.6 W (maximum)
133 MHz = 0.7 W (nominal), 0.8 W (maximum)
2
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
17
AC Electrical Characteristics
6
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for 66.67/83.33/100/133 MHz devices. Note that AC timings are based on a 50-pf load for MAX
Delay and 10-pf load for MIN delay. Typical output buffer impedances are shown in this table.
Table 9. Output Buffer Impedances1
Output Buffers
Typical Impedance (Ω)
60x bus
45 or 272
Memory controller
45 or 272
Parallel I/O
45
PCI
27
1
These are typical values at 65° C. Impedance may vary by ±25% with
process and temperature.
2
Impedance value is selected through SIUMCR[20,21]. See the SoC
reference manual.
6.1
CPM AC Characteristics
This table lists CPM output characteristics.
Table 10. AC Characteristics for CPM Outputs1
Spec Number
Value (ns)
Maximum Delay
Characteristic
Max
Min
Minimum Delay
66
MHz
83
MHz
100
MHz
133
MHz
66
MHz
83
MHz
100
MHz
133
MHz
sp36a sp37a FCC outputs—internal clock (NMSI)
6
5.5
5.5
5.5
0.5
0.5
0.5
0.5
sp36b sp37b FCC outputs—external clock (NMSI)
8
8
8
8
2
2
2
2
sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
10
10
10
10
0
0
0
0
sp38b sp39b SCC/SMC/SPI/I2C outputs—external clock (NMSI)
8
8
8
8
2
2
2
2
sp40
sp41
TDM outputs/SI
11
11
11
11
2.5
2.5
2.5
2.5
sp42
sp43
TIMER/IDMA outputs
11
11
11
11
0.5
0.5
0.5
0.5
11
11
11
11
0.5
0.5
0.5
0.5
sp42a sp43a PIO outputs
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
18
Freescale Semiconductor
AC Electrical Characteristics
This table lists CPM input characteristics.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not
exceed 5 ns. This should be enforced especially on clock signals. Rise time
refers to signal transitions from 10% to 90% of VCC; fall time refers to
transitions from 90% to 10% of VCC.
Table 11. AC Characteristics for CPM Inputs1
Spec Number
Value (ns)
Setup
Characteristic
Setup
Hold
Hold
66
MHz
83
MHz
100
MHz
133
MHz
66
MHz
83
MHz
100
MHz
133
MHz
sp16a sp17a FCC inputs—internal clock (NMSI)
6
6
6
6
0
0
0
0
sp16b sp17b FCC inputs—external clock (NMSI)
2.5
2.5
2.5
2.5
2
2
2
2
sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI)
6
6
6
6
0
0
0
0
sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI)
4
4
4
4
2
2
2
2
sp20
sp21
TDM inputs/SI
3
3
3
3
2.5
2.5
2.5
2.5
sp22
sp23
PIO/TIMER/IDMA inputs
8
8
8
8
0.5
0.5
0.5
0.5
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
NOTE
Although the specifications generally reference the rising edge of the clock,
the following AC timing diagrams also apply when the falling edge is the
active edge.
This figure shows the FCC internal clock.
BRG_OUT
sp17a
sp16a
FCC input signals
sp36a/sp37a
FCC output signals
Note: When GFMR[TCI] = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.[TCI] = 1
Figure 3. FCC Internal Clock Diagram
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
19
AC Electrical Characteristics
This figure shows the FCC external clock.
Serial ClKin
sp17b
sp16b
FCC input signals
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 1
Figure 4. FCC External Clock Diagram
This figure shows the SCC/SMC/SPI/I2C external clock.
Serial CLKin
new CLKin
sp18b
sp19b
SCC/SMC/SPI/I2C input signals
(See note)
sp38b/sp39b
SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SPI:
1. Input sampled on the rising edge and output driven on the rising edge.
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge (shown).
4. Input sampled on the falling edge and output driven on the rising edge.
Note: There are two possible timing conditions for SCC/SMC/I2C:
1. Input sampled on the falling edge and output driven on the falling edge (shown).
2. Input sampled on the falling edge and output driven on the rising edge.
Figure 5. SCC/SMC/SPI/I2C External Clock Diagram
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
20
Freescale Semiconductor
AC Electrical Characteristics
This figure shows the SCC/SMC/SPI/I2C internal clock.
BRG_OUT
sp19a
sp18a
SCC/SMC/SPI/I2C input signals
(See note)
sp38a/sp39a
SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram
This figure shows TDM input and output signals.
Serial CLKin
sp20
sp21
TDM input signals
sp40/sp41
TDM output signals
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 7. TDM Signal Diagram
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
21
AC Electrical Characteristics
This figure shows PIO and timer signals.
Sys clk
sp23
sp22
PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23
sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43
IDMA output signals
sp42/sp43
sp42a/sp43a
TIMER(sp42/43)/ PIO(sp42a/sp43a)
output signals
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 8. PIO and Timer Signal Diagram
6.2
SIU AC Characteristics
This table lists SIU input characteristics.
NOTE: CLKIN Jitter and Duty Cycle
The CLKIN input to the SoC should not exceed +/– 150 psec of jitter
(peak-to-peak). This represents total input jitter—the combination of short
term (peak-to-peak) and long term (cumulative). The duty cycle of CLKIN
should not exceed the ratio of 40:60.
NOTE: Spread Spectrum Clocking
Spread spectrum clocking is allowed with 1% input frequency down-spread
at maximum 60 KHz modulation rate regardless of input frequency.
NOTE: PCI AC Timing
The SoC meets the timing requirements of PCI Specification Revision 2.2.
See Section 7, “Clock Configuration Modes,” and “Note: Tval (Output
Hold)” to determine if a specific clock configuration is compliant.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
22
Freescale Semiconductor
AC Electrical Characteristics
NOTE: Conditions
The following conditions must be met in order to operate the MPC8272
family devices with 133 MHz bus: single PowerQUICC II Bus mode must
be used (no external master, BCR[EBM] = 0); data bus must be in Pipeline
mode (BRx[DR] = 1); internal arbiter and memory controller must be used.
For expected load of above 40 pF, it is recommended that data and address
buses be configured to low (25 Ω) impedance (SIUMCR[HLBE0] = 1,
SIUMCR[HLBE1] = 1).
Table 12. AC Characteristics for SIU Inputs1
Spec Number
Value (ns)
Setup
Characteristic
Setup
1
Hold
Hold
66
MHz
83
MHz
100
MHz
133
MHz
66
MHz
83
MHz
100
MHz
133
MHz
sp11
sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/TEA
6
5
3.5
N/A
0.5
0.5
0.5
N/A
sp12
sp10 Data bus in normal mode
5
4
3.5
N/A
0.5
0.5
0.5
N/A
sp13
sp10 Data bus in pipeline mode (without ECC and
PARITY)
N/A
4
2.5
1.5
N/A
0.5
0.5
0.5
sp15
sp10 All other pins
5
4
3.5
N/A
0.5
0.5
0.5
N/A
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
This table lists SIU output characteristics.
Table 13. AC Characteristics for SIU Outputs1
Spec Number
Value (ns)
Maximum Delay
Characteristic
Max
Min
sp31
sp30
sp32
Minimum Delay
66
MHz
83
MHz
100
MHz
133
MHz
66
MHz
83
MHz
100
MHz
133
MHz
PSDVAL/TEA/TA
7
6
5.5
N/A
1
1
1
N/A
sp30
ADD/ADD_atr./BADDR/CI/GBL/WT
8
6.5
5.5
4.52
1
1
1
12
sp33
sp30
Data bus3
6.5
6.5
5.5
4.5
0.8
0.8
0.8
1
sp34
sp30
Memory controller signals/ALE
6
5.5
5.5
4.5
1
1
1
1
sp35
sp30
All other signals
6
5.5
5.5
N/A
1
1
1
N/A
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
2
Value is for ADD only; other sp32/sp30 signals are not applicable.
3 To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
23
AC Electrical Characteristics
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing.
This figure shows the interaction of several bus signals.
CLKin
sp11
sp10
sp11a
sp10
sp12
sp10
sp15
sp10
AACK/TA/TS/
DBG/BG/BR input signals
ARTRY/TEA input signals
DATA bus normal mode
input signal
All other input signals
sp31
sp30
sp32
sp30
PSDVAL/TEA/TA output signals
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
DATA bus output signals
sp33
sp30
sp35
sp30
All other output signals
(except AP)
sp10
sp13
DATA bus pipeline mode
input signal
Figure 9. Bus Signals
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
24
Freescale Semiconductor
AC Electrical Characteristics
This figure shows signal behavior in MEMC mode.
CLKin
V_CLK
sp34/sp30
Memory controller signals
Figure 10. MEMC Mode Diagram
NOTE
Generally, all SoC bus and system output signals are driven from the rising
edge of the input clock (CLKin). Memory controller signals, however,
trigger on four points within a CLKin cycle. Each cycle is divided by four
internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and
T3 at the falling edge, of CLKin. However, the spacing of T2 and T4
depends on the PLL clock ratio selected, as shown in Table 14.
Table 14. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Ratio
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
3/10 CLKin
1/2 CLKin
8/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
11/14 CLKin
This table is a representation of the information in Table 14.
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T2
T3
T4
CLKin
for 1:2.5
T1
T2
T3
T4
for 1:3.5
CLKin
T1
T2
T3
T4
Figure 11. Internal Tick Spacing for Memory Controller Signals
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
25
AC Electrical Characteristics
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
6.3
JTAG Timings
This table lists the JTAG timings.
Table 15. JTAG Timings1
Symbol2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
—
JTAG external clock cycle time
tJTG
30
—
ns
—
tJTKHKL
15
—
ns
—
tJTGR and
tJTGF
0
5
ns
6
tTRST
25
—
ns
3, 6
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
4
—
—
ns
ns
4 7
,
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
ns
ns
4 7
,
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
—
—
10
10
ns
ns
5 7
.
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
1
1
—
—
ns
ns
5 7
,
JTAG external clock to output high impedance
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
1
1
10
10
ns
ns
5 6
,
Parameter
JTAG external clock pulse width measured at 1.4V
JTAG external clock rise and fall times
TRST assert time
Input setup times
4, 7
Input hold times
4, 7
Output valid times
5, 7
Output hold times
1
2
3
4
5
6
7
5, 7
5, 6
All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
Non-JTAG signal input timing with respect to tTCLK.
Non-JTAG signal output timing with respect to tTCLK.
Guaranteed by design.
Guaranteed by design and device characterization.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
26
Freescale Semiconductor
Clock Configuration Modes
7
Clock Configuration Modes
As shown in this table, the clocking mode is set according to two sources:
• PCI_CFG[0]— An input signal. Also defined as “PCI_HOST_EN.” See Chapter 6, “External
Signals,” and Chapter 9, “PCI Bridge,” in the SoC reference manual.
• PCI_MODCK—Bit 27 in the Hard Reset Configuration Word. See Chapter 5, “Reset,” in the SoC
reference manual.
Table 16. SoC Clocking Modes
Pins
1
2
PCI_CFG[0]1
PCI_MODCK2
0
0
0
1
1
0
1
1
Clocking Mode
PCI Clock Frequency Range (MHz)
Reference
PCI host
50–66
Table 17
25–50
Table 18
50–66
Table 19
25–50
Table 20
PCI agent
PCI_HOST_EN
Determines PCI clock frequency range.
Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits
during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to
the selected clock operation mode as described in the following sections.
NOTE
Clock configurations change only after PORESET is asserted.
NOTE: Tval (Output Hold)
The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum
Tval = 1 ns when PCI_MODCK = 0. Therefore, designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
7.1
PCI Host Mode
These tables show configurations for PCI host mode. The frequency values listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does
not exceed the frequency rating of the user’s device. Note that in PCI host mode the input clock is the bus
clock.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
27
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1,2
Mode3
MODCK_HMODCK[1-3]
Bus Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
PCI
Division
Factor6
PCI Clock
(MHz)
Low
High
Default Modes (MODCK_H=0000)
0000_000
60.0
66.7
2
120.0 133.3
2.5
150.0 166.7
2
60.0
66.7
0000_001
50.0
66.7
2
100.0 133.3
3
150.0 200.0
2
50.0
66.7
0000_010
60.0
80.0
2.5
150.0 200.0
3
180.0 240.0
3
50.0
66.7
0000_011
60.0
80.0
2.5
150.0 200.0
3.5
210.0 280.0
3
50.0
66.7
0000_100
60.0
80.0
2.5
150.0 200.0
4
240.0 320.0
3
50.0
66.7
0000_101
50.0
66.7
3
150.0 200.0
3
150.0 200.0
3
50.0
66.7
0000_110
50.0
66.7
3.5
150.0 200.0
3.5
175.0 233.3
3
50.0
66.7
0000_111
50.0
66.7
3
150.0 200.0
4
200.0 266.6
3
50.0
66.7
Full Configuration Modes
0001_000
50.0
66.7
3
150.0 200.0
5
250.0 333.3
3
50.0
66.7
0001_001
50.0
66.7
3
150.0 200.0
6
300.0 400.0
3
50.0
66.7
0001_010
50.0
66.7
3
150.0 200.0
7
350.0 466.6
3
50.0
66.7
0001_011
50.0
66.7
3
150.0 200.0
8
400.0 533.3
3
50.0
66.7
0010_000
50.0
66.7
4
200.0 266.6
5
250.0 333.3
4
50.0
66.7
0010_001
50.0
66.7
4
200.0 266.6
6
300.0 400.0
4
50.0
66.7
0010_010
50.0
66.7
4
200.0 266.6
7
350.0 466.6
4
50.0
66.7
0010_011
50.0
66.7
4
200.0 266.6
8
400.0 533.3
4
50.0
66.7
0010_100
75.0 100.0
4
300.0 400.0
5
375.0 500.0
6
50.0
66.7
0010_101
75.0 100.0
4
300.0 400.0
5.5
412.5 549.9
6
50.0
66.7
0010_110
75.0 100.0
4
300.0 400.0
6
450.0 599.9
6
50.0
66.7
0011_000
50.0
66.7
5
250.0 333.3
5
250.0 333.3
5
50.0
66.7
0011_001
50.0
66.7
5
250.0 333.3
6
300.0 400.0
5
50.0
66.7
0011_010
50.0
66.7
5
250.0 333.3
7
350.0 466.6
5
50.0
66.7
0011_011
50.0
66.7
5
250.0 333.3
8
400.0 533.3
5
50.0
66.7
0100_000
Reserved
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
28
Freescale Semiconductor
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1,2 (continued)
Mode3
Bus Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
MODCK_HMODCK[1-3]
Low
High
0100_001
50.0
66.7
6
300.0 400.0
6
300.0 400.0
0100_010
50.0
66.7
6
300.0 400.0
7
0100_011
50.0
66.7
6
300.0 400.0
0101_000
60.0
66.7
2
0101_001
50.0
66.7
0101_010
50.0
0101_011
Low
High
High
PCI Clock
(MHz)
Low
High
6
50.0
66.7
350.0 466.6
6
50.0
66.7
8
400.0 533.3
6
50.0
66.7
120.0 133.3
2.5
150.0 166.7
2
60.0
66.7
2
100.0 133.3
3
150.0 200.0
2
50.0
66.7
66.7
2
100.0 133.3
3.5
175.0 233.3
2
50.0
66.7
50.0
66.7
2
100.0 133.3
4
200.0 266.6
2
50.0
66.7
0101_100
50.0
66.7
2
100.0 133.3
4.5
225.0 300.0
2
50.0
66.7
0101_101
83.3 111.1
3
250.0 333.3
3.5
291.7 388.9
5
50.0
66.7
0101_110
83.3 111.1
3
250.0 333.3
4
333.3 444.4
5
50.0
66.7
0101_111
83.3 111.1
3
250.0 333.3
4.5
375.0 500.0
5
50.0
66.7
0110_000
60.0
80.0
2.5
150.0 200.0
2.5
150.0 200.0
3
50.0
66.7
0110_001
60.0
80.0
2.5
150.0 200.0
3
180.0 240.0
3
50.0
66.7
0110_010
60.0
80.0
2.5
150.0 200.0
3.5
210.0 280.0
3
50.0
66.7
0110_011
60.0
80.0
2.5
150.0 200.0
4
240.0 320.0
3
50.0
66.7
0110_100
60.0
80.0
2.5
150.0 200.0
4.5
270.0 360.0
3
50.0
66.7
0110_101
60.0
80.0
2.5
150.0 200.0
5
300.0 400.0
3
50.0
66.7
0110_110
60.0
80.0
2.5
150.0 200.0
6
360.0 480.0
3
50.0
66.7
0111_000
Low
PCI
Division
Factor6
Reserved
0111_001
50.0
66.7
3
150.0 200.0
3
150.0 200.0
3
50.0
66.7
0111_010
50.0
66.7
3
150.0 200.0
3.5
175.0 233.3
3
50.0
66.7
0111_011
50.0
66.7
3
150.0 200.0
4
200.0 266.6
3
50.0
66.7
0111_100
50.0
66.7
3
150.0 200.0
4.5
225.0 300.0
3
50.0
66.7
200.0 266.6
4
50.0
66.7
1000_000
1000_001
Reserved
66.7
88.9
3
200.0 266.6
3
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
29
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1,2 (continued)
Mode3
Bus Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
MODCK_HMODCK[1-3]
Low
High
1000_010
66.7
88.9
3
200.0 266.6
3.5
233.3 311.1
1000_011
66.7
88.9
3
200.0 266.6
4
1000_100
66.7
88.9
3
200.0 266.6
1000_101
66.7
88.9
3
1000_110
66.7
88.9
3
Low
High
High
4
50.0
66.7
266.7 355.5
4
50.0
66.7
4.5
300.0 400.0
4
50.0
66.7
200.0 266.6
6
400.0 533.3
4
50.0
66.7
200.0 266.6
6.5
433.3 577.7
4
50.0
66.7
Reserved
1001_001
Reserved
High
PCI Clock
(MHz)
Low
1001_000
Low
PCI
Division
Factor6
1001_010
57.1
76.2
3.5
200.0 266.6
3.5
200.0 266.6
4
50.0
66.7
1001_011
57.1
76.2
3.5
200.0 266.6
4
228.6 304.7
4
50.0
66.7
1001_100
57.1
76.2
3.5
200.0 266.6
4.5
257.1 342.8
4
50.0
66.7
1001_101
85.7 114.3
3.5
300.0 400.0
5
428.6 571.4
6
50.0
66.7
1001_110
85.7 114.3
3.5
300.0 400.0
5.5
471.4 628.5
6
50.0
66.7
1001_111
85.7 114.3
3.5
300.0 400.0
6
514.3 685.6
6
50.0
66.7
1010_000
75.0 100.0
2
150.0 200.0
2
150.0 200.0
3
50.0
66.7
1010_001
75.0 100.0
2
150.0 200.0
2.5
187.5 250.0
3
50.0
66.7
1010_010
75.0 100.0
2
150.0 200.0
3
225.0 300.0
3
50.0
66.7
1010_011
75.0 100.0
2
150.0 200.0
3.5
262.5 350.0
3
50.0
66.7
1010_100
75.0 100.0
2
150.0 200.0
4
300.0 400.0
3
50.0
66.7
1010_101
100.0 133.3
2
200.0 266.6
2.5
250.0 333.3
4
50.0
66.7
1010_110
100.0 133.3
2
200.0 266.6
3
300.0 400.0
4
50.0
66.7
1010_111
100.0 133.3
2
200.0 266.6
3.5
350.0 466.6
4
50.0
66.7
1011_000
Reserved
1011_001
80.0 106.7
2.5
200.0 266.6
2.5
200.0 266.6
4
50.0
66.7
1011_010
80.0 106.7
2.5
200.0 266.6
3
240.0 320.0
4
50.0
66.7
1011_011
80.0 106.7
2.5
200.0 266.6
3.5
280.0 373.3
4
50.0
66.7
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
30
Freescale Semiconductor
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1,2 (continued)
Mode3
MODCK_HMODCK[1-3]
1
2
3
4
5
6
Bus Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
PCI
Division
Factor6
PCI Clock
(MHz)
Low
High
1011_100
80.0 106.7
2.5
200.0 266.6
4
320.0 426.6
4
50.0
66.7
1011_101
80.0 106.7
2.5
200.0 266.6
4.5
360.0 480.0
4
50.0
66.7
1101_000
100.0 133.3
2.5
250.0 333.3
3
300.0 400.0
5
50.0
66.7
1101_001
100.0 133.3
2.5
250.0 333.3
3.5
350.0 466.6
5
50.0
66.7
1101_010
100.0 133.3
2.5
250.0 333.3
4
400.0 533.3
5
50.0
66.7
1101_011
100.0 133.3
2.5
250.0 333.3
4.5
450.0 599.9
5
50.0
66.7
1101_100
100.0 133.3
2.5
250.0 333.3
5
500.0 666.6
5
50.0
66.7
1101_101
125.0 166.7
2
250.0 333.3
3
375.0 500.0
5
50.0
66.7
1101_110
125.0 166.7
2
250.0 333.3
4
500.0 666.6
5
50.0
66.7
1110_000
100.0 133.3
3
300.0 400.0
3.5
350.0 466.6
6
50.0
66.7
1110_001
100.0 133.3
3
300.0 400.0
4
400.0 533.3
6
50.0
66.7
1110_010
100.0 133.3
3
300.0 400.0
4.5
450.0 599.9
6
50.0
66.7
1110_011
100.0 133.3
3
300.0 400.0
5
500.0 666.6
6
50.0
66.7
1110_100
100.0 133.3
3
300.0 400.0
5.5
550.0 733.3
6
50.0
66.7
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
PCI_MODCK determines the PCI clock frequency range. SeeTable 18 for lower range configurations.
MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from
SCCR[PCIDF] as follows:
CPM_CLK/PCI_CLK = (PCIDF + 1) / 2.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
31
Clock Configuration Modes
Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1,2
Mode3
MODCK_HMODCK[1-3]
Bus Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
PCI
Division
Factor6
PCI Clock
(MHz)
Low
High
Default Modes (MODCK_H=0000)
0000_000
60.0 100.0
2
120.0 200.0
2.5
150.0 250.0
4
30.0
50.0
0000_001
50.0 100.0
2
100.0 200.0
3
150.0 300.0
4
25.0
50.0
0000_010
60.0 120.0
2.5
150.0 300.0
3
180.0 360.0
6
25.0
50.0
0000_011
60.0 120.0
2.5
150.0 300.0
3.5
210.0 420.0
6
25.0
50.0
0000_100
60.0 120.0
2.5
150.0 300.0
4
240.0 480.0
6
25.0
50.0
0000_101
50.0 100.0
3
150.0 300.0
3
150.0 300.0
6
25.0
50.0
0000_110
50.0 100.0
3
150.0 300.0
3.5
175.0 350.0
6
25.0
50.0
0000_111
50.0 100.0
3
150.0 300.0
4
200.0 400.0
6
25.0
50.0
Full Configuration Modes
0001_000
50.0 100.0
3
150.0 300.0
5
250.0 500.0
6
25.0
50.0
0001_001
50.0 100.0
3
150.0 300.0
6
300.0 600.0
6
25.0
50.0
0001_010
50.0 100.0
3
150.0 300.0
7
350.0 700.0
6
25.0
50.0
0001_011
50.0 100.0
3
150.0 300.0
8
400.0 800.0
6
25.0
50.0
0010_000
50.0 100.0
4
200.0 400.0
5
250.0 500.0
8
25.0
50.0
0010_001
50.0 100.0
4
200.0 400.0
6
300.0 600.0
8
25.0
50.0
0010_010
50.0 100.0
4
200.0 400.0
7
350.0 700.0
8
25.0
50.0
0010_011
50.0 100.0
4
200.0 400.0
8
400.0 800.0
8
25.0
50.0
0010_100
37.5
75.0
4
150.0 300.0
5
187.5 375.0
6
25.0
50.0
0010_101
37.5
75.0
4
150.0 300.0
5.5
206.3 412.5
6
25.0
50.0
0010_110
37.5
75.0
4
150.0 300.0
6
225.0 450.0
6
25.0
50.0
0011_000
30.0
50.0
5
150.0 250.0
5
150.0 250.0
5
30.0
50.0
0011_001
25.0
50.0
5
125.0 250.0
6
150.0 300.0
5
25.0
50.0
0011_010
25.0
50.0
5
125.0 250.0
7
175.0 350.0
5
25.0
50.0
0011_011
25.0
50.0
5
125.0 250.0
8
200.0 400.0
5
25.0
50.0
0100_000
Reserved
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
32
Freescale Semiconductor
Clock Configuration Modes
Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1,2 (continued)
Mode3
Bus Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
MODCK_HMODCK[1-3]
Low
High
0100_001
25.0
50.0
6
150.0 300.0
6
150.0 300.0
0100_010
25.0
50.0
6
150.0 300.0
7
0100_011
25.0
50.0
6
150.0 300.0
0101_000
60.0 100.0
2
0101_001
50.0 100.0
0101_010
Low
High
High
PCI Clock
(MHz)
Low
High
6
25.0
50.0
175.0 350.0
6
25.0
50.0
8
200.0 400.0
6
25.0
50.0
120.0 200.0
2.5
150.0 250.0
4
30.0
50.0
2
100.0 200.0
3
150.0 300.0
4
25.0
50.0
50.0 100.0
2
100.0 200.0
3.5
175.0 350.0
4
25.0
50.0
0101_011
50.0 100.0
2
100.0 200.0
4
200.0 400.0
4
25.0
50.0
0101_100
50.0 100.0
2
100.0 200.0
4.5
225.0 450.0
4
25.0
50.0
0101_101
42.9
83.3
3
128.6 250.0
3.5
150.0 291.7
5
25.7
50.0
0101_110
41.7
83.3
3
125.0 250.0
4
166.7 333.3
5
25.0
50.0
0101_111
41.7
83.3
3
125.0 250.0
4.5
187.5 375.0
5
25.0
50.0
0110_000
60.0 120.0
2.5
150.0 300.0
2.5
150.0 300.0
6
25.0
50.0
0110_001
60.0 120.0
2.5
150.0 300.0
3
180.0 360.0
6
25.0
50.0
0110_010
60.0 120.0
2.5
150.0 300.0
3.5
210.0 420.0
6
25.0
50.0
0110_011
60.0 120.0
2.5
150.0 300.0
4
240.0 480.0
6
25.0
50.0
0110_100
60.0 120.0
2.5
150.0 300.0
4.5
270.0 540.0
6
25.0
50.0
0110_101
60.0 120.0
2.5
150.0 300.0
5
300.0 600.0
6
25.0
50.0
0110_110
60.0 120.0
2.5
150.0 300.0
6
360.0 720.0
6
25.0
50.0
0111_000
Low
PCI
Division
Factor6
Reserved
0111_001
50.0 100.0
3
150.0 300.0
3
150.0 300.0
6
25.0
50.0
0111_010
50.0 100.0
3
150.0 300.0
3.5
175.0 350.0
6
25.0
50.0
0111_011
50.0 100.0
3
150.0 300.0
4
200.0 400.0
6
25.0
50.0
0111_100
50.0 100.0
3
150.0 300.0
4.5
225.0 450.0
6
25.0
50.0
200.0 400.0
8
25.0
50.0
1000_000
1000_001
Reserved
66.7 133.3
3
200.0 400.0
3
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
33
Clock Configuration Modes
Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1,2 (continued)
Mode3
MODCK_HMODCK[1-3]
Bus Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
PCI
Division
Factor6
PCI Clock
(MHz)
Low
High
1000_010
66.7 133.3
3
200.0 400.0
3.5
233.3 466.7
8
25.0
50.0
1000_011
66.7 133.3
3
200.0 400.0
4
266.7 533.3
8
25.0
50.0
1000_100
66.7 133.3
3
200.0 400.0
4.5
300.0 600.0
8
25.0
50.0
1000_101
66.7 133.3
3
200.0 400.0
6
400.0 800.0
8
25.0
50.0
1000_110
66.7 133.3
3
200.0 400.0
6.5
433.3 866.7
8
25.0
50.0
1001_000
Reserved
1001_001
Reserved
1001_010
57.1 114.3
3.5
200.0 400.0
3.5
200.0 400.0
8
25.0
50.0
1001_011
57.1 114.3
3.5
200.0 400.0
4
228.6 457.1
8
25.0
50.0
1001_100
57.1 114.3
3.5
200.0 400.0
4.5
257.1 514.3
8
25.0
50.0
1001_101
42.9
85.7
3.5
150.0 300.0
5
214.3 428.6
6
25.0
50.0
1001_110
42.9
85.7
3.5
150.0 300.0
5.5
235.7 471.4
6
25.0
50.0
1001_111
42.9
85.7
3.5
150.0 300.0
6
257.1 514.3
6
25.0
50.0
1010_000
75.0 150.0
2
150.0 300.0
2
150.0 300.0
6
25.0
50.0
1010_001
75.0 150.0
2
150.0 300.0
2.5
187.5 375.0
6
25.0
50.0
1010_010
75.0 150.0
2
150.0 300.0
3
225.0 450.0
6
25.0
50.0
1010_011
75.0 150.0
2
150.0 300.0
3.5
262.5 525.0
6
25.0
50.0
1010_100
75.0 150.0
2
150.0 300.0
4
300.0 600.0
6
25.0
50.0
1010_101
100.0 200.0
2
200.0 400.0
2.5
250.0 500.0
8
25.0
50.0
1010_110
100.0 200.0
2
200.0 400.0
3
300.0 600.0
8
25.0
50.0
1010_111
100.0 200.0
2
200.0 400.0
3.5
350.0 700.0
8
25.0
50.0
1011_000
Reserved
1011_001
80.0 160.0
2.5
200.0 400.0
2.5
200.0 400.0
8
25.0
50.0
1011_010
80.0 160.0
2.5
200.0 400.0
3
240.0 480.0
8
25.0
50.0
1011_011
80.0 160.0
2.5
200.0 400.0
3.5
280.0 560.0
8
25.0
50.0
1011_100
80.0 160.0
2.5
200.0 400.0
4
320.0 640.0
8
25.0
50.0
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
34
Freescale Semiconductor
Clock Configuration Modes
Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1,2 (continued)
Mode3
MODCK_HMODCK[1-3]
1
2
3
4
5
Bus Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
PCI
Division
Factor6
PCI Clock
(MHz)
Low
High
1011_101
80.0 160.0
2.5
200.0 400.0
4.5
360.0 720.0
8
25.0
50.0
1101_000
50.0 100.0
2.5
125.0 250.0
3
150.0 300.0
5
25.0
50.0
1101_001
50.0 100.0
2.5
125.0 250.0
3.5
175.0 350.0
5
25.0
50.0
1101_010
50.0 100.0
2.5
125.0 250.0
4
200.0 400.0
5
25.0
50.0
1101_011
50.0 100.0
2.5
125.0 250.0
4.5
225.0 450.0
5
25.0
50.0
1101_100
50.0 100.0
2.5
125.0 250.0
5
250.0 500.0
5
25.0
50.0
1101_101
62.5 125.0
2
125.0 250.0
3
187.5 375.0
5
25.0
50.0
1101_110
62.5 125.0
2
125.0 250.0
4
250.0 500.0
5
25.0
50.0
1110_000
50.0 100.0
3
150.0 300.0
3.5
175.0 350.0
6
25.0
50.0
1110_001
50.0 100.0
3
150.0 300.0
4
200.0 400.0
6
25.0
50.0
1110_010
50.0 100.0
3
150.0 300.0
4.5
225.0 450.0
6
25.0
50.0
1110_011
50.0 100.0
3
150.0 300.0
5
250.0 500.0
6
25.0
50.0
1110_100
50.0 100.0
3
150.0 300.0
5.5
275.0 550.0
6
25.0
50.0
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
PCI_MODCK determines the PCI clock frequency range. See Table 17 for higher range configurations.
MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
35
Clock Configuration Modes
6
7.2
CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 1, the ratio of CPM_CLK/PCI_CLK should be calculated from
PCIDF as follows:
PCIDF = 3 > CPM_CLK/PCI_CLK = 4
PCIDF = 5 > CPM_CLK/PCI_CLK = 6
PCIDF = 7 > CPM_CLK/PCI_CLK = 8
PCIDF = 9 > CPM_CLK/PCI_CLK = 5
PCIDF = B > CPM_CLK/PCI_CLK = 6
PCI Agent Mode
These tables show configurations for PCI agent mode. The frequency values listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does
not exceed the frequency rating of the user’s device. Note that in PCI agent mode the input clock is PCI
clock.
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1,2
Mode3
MODCK_HMODCK[1-3]
PCI Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
Bus
Division
Factor
Bus Clock
(MHz)
Low
High
Default Modes (MODCK_H=0000)
0000_000
60.0
66.7
2
120.0 133.3
2.5
150.0 166.7
2
60.0
66.7
0000_001
50.0
66.7
2
100.0 133.3
3
150.0 200.0
2
50.0
66.7
0000_010
50.0
66.7
3
150.0 200.0
3
150.0 200.0
3
50.0
66.7
0000_011
50.0
66.7
3
150.0 200.0
4
200.0 266.6
3
50.0
66.7
0000_100
50.0
66.7
3
150.0 200.0
3
180.0 240.0
2.5
60.0
80.0
0000_101
50.0
66.7
3
150.0 200.0
3.5
210.0 280.0
2.5
60.0
80.0
0000_110
50.0
66.7
4
200.0 266.6
3.5
233.3 311.1
3
66.7
88.9
0000_111
50.0
66.7
4
200.0 266.6
3
240.0 320.0
2.5
80.0 106.7
Full Configuration Modes
0001_001
60.0
66.7
2
120.0 133.3
5
150.0 166.7
4
30.0
33.3
0001_010
50.0
66.7
2
100.0 133.3
6
150.0 200.0
4
25.0
33.3
0001_011
50.0
66.7
2
100.0 133.3
7
175.0 233.3
4
25.0
33.3
0001_100
50.0
66.7
2
100.0 133.3
8
200.0 266.6
4
25.0
33.3
0010_001
50.0
66.7
3
150.0 200.0
3
180.0 240.0
2.5
60.0
80.0
0010_010
50.0
66.7
3
150.0 200.0
3.5
210.0 280.0
2.5
60.0
80.0
0010_011
50.0
66.7
3
150.0 200.0
4
240.0 320.0
2.5
60.0
80.0
0010_100
50.0
66.7
3
150.0 200.0
4.5
270.0 360.0
2.5
60.0
80.0
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
36
Freescale Semiconductor
Clock Configuration Modes
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1,2 (continued)
Mode3
MODCK_HMODCK[1-3]
PCI Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
0011_000
Reserved
0011_001
Reserved
0011_010
Reserved
0011_011
Reserved
0011_100
Reserved
0100_000
Reserved
CPU Clock
(MHz)
Low
High
Bus
Division
Factor
Bus Clock
(MHz)
Low
High
0100_001
50.0
66.7
3
150.0 200.0
3
150.0 200.0
3
50.0
66.7
0100_010
50.0
66.7
3
150.0 200.0
3.5
175.0 200.0
3
50.0
66.7
0100_011
50.0
66.7
3
150.0 200.0
4
200.0 266.6
3
50.0
66.7
0100_100
50.0
66.7
3
150.0 200.0
4.5
225.0 300.0
3
50.0
66.7
0101_000
50.0
66.7
5
250.0 333.3
2.5
250.0 333.3
2.5
100.0 133.3
0101_001
50.0
66.7
5
250.0 333.3
3
300.0 400.0
2.5
100.0 133.3
0101_010
50.0
66.7
5
250.0 333.3
3.5
350.0 466.6
2.5
100.0 133.3
0101_011
50.0
66.7
5
250.0 333.3
4
400.0 533.3
2.5
100.0 133.3
0101_100
50.0
66.7
5
250.0 333.3
4.5
450.0 599.9
2.5
100.0 133.3
0101_101
50.0
66.7
5
250.0 333.3
5
500.0 666.6
2.5
100.0 133.3
0101_110
50.0
66.7
5
250.0 333.3
5.5
550.0 733.3
2.5
100.0 133.3
0110_000
Reserved
0110_001
50.0
66.7
4
200.0 266.6
3
200.0 266.6
3
66.7
88.9
0110_010
50.0
66.7
4
200.0 266.6
3.5
233.3 311.1
3
66.7
88.9
0110_011
50.0
66.7
4
200.0 266.6
4
266.7 355.5
3
66.7
88.9
0110_100
50.0
66.7
4
200.0 266.6
4.5
300.0 400.0
3
66.7
88.9
0111_000
50.0
66.7
3
150.0 200.0
2
150.0 200.0
2
75.0 100.0
0111_001
50.0
66.7
3
150.0 200.0
2.5
187.5 250.0
2
75.0 100.0
0111_010
50.0
66.7
3
150.0 200.0
3
225.0 300.0
2
75.0 100.0
0111_011
50.0
66.7
3
150.0 200.0
3.5
262.5 350.0
2
75.0 100.0
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
37
Clock Configuration Modes
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1,2 (continued)
Mode3
MODCK_HMODCK[1-3]
PCI Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
1000_000
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
Bus
Division
Factor
Bus Clock
(MHz)
Low
High
Reserved
1000_001
50.0
66.7
3
150.0 200.0
2.5
150.0 166.7
2.5
60.0
80.0
1000_010
50.0
66.7
3
150.0 200.0
3
180.0 240.0
2.5
60.0
80.0
1000_011
50.0
66.7
3
150.0 200.0
3.5
210.0 280.0
2.5
60.0
80.0
1000_100
50.0
66.7
3
150.0 200.0
4
240.0 320.0
2.5
60.0
80.0
1000_101
50.0
66.7
3
150.0 200.0
4.5
270.0 360.0
2.5
60.0
80.0
1001_000
Reserved
1001_001
Reserved
1001_010
Reserved
1001_011
50.0
66.7
4
200.0 266.6
4
200.0 266.6
4
50.0
66.7
1001_100
50.0
66.7
4
200.0 266.6
4.5
225.0 300.0
4
50.0
66.7
1010_000
Reserved
1010_001
50.0
66.7
4
200.0 266.6
3
200.0 266.6
3
66.7
88.9
1010_010
50.0
66.7
4
200.0 266.6
3.5
233.3 311.1
3
66.7
88.9
1010_011
50.0
66.7
4
200.0 266.6
4
266.7 355.5
3
66.7
88.9
1010_100
50.0
66.7
4
200.0 266.6
4.5
300.0 400.0
3
66.7
88.9
1011_000
Reserved
1011_001
50.0
66.7
4
200.0 266.6
2.5
200.0 266.6
2.5
80.0 106.7
1011_010
50.0
66.7
4
200.0 266.6
3
240.0 320.0
2.5
80.0 106.7
1011_011
50.0
66.7
4
200.0 266.6
3.5
280.0 373.3
2.5
80.0 106.7
1011_100
50.0
66.7
4
200.0 266.6
4
320.0 426.6
2.5
80.0 106.7
1011_101
50.0
66.7
4
200.0 266.6
2.5
250.0 333.3
2
100.0 133.3
1011_110
50.0
66.7
4
200.0 266.6
3
300.0 400.0
2
100.0 133.3
1011_111
50.0
66.7
4
200.0 266.6
3.5
350.0 466.6
2
100.0 133.3
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
38
Freescale Semiconductor
Clock Configuration Modes
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1,2 (continued)
Mode3
1
2
3
4
5
PCI Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Bus
Division
Factor
Bus Clock
(MHz)
MODCK_HMODCK[1-3]
Low
High
1100_101
50.0
66.7
6
300.0 400.0
4
400.0 533.3
3
100.0 133.3
1100_110
50.0
66.7
6
300.0 400.0
4.5
450.0 599.9
3
100.0 133.3
1100_111
50.0
66.7
6
300.0 400.0
5
500.0 666.6
3
100.0 133.3
1101_000
50.0
66.7
6
300.0 400.0
5.5
550.0 733.3
3
100.0 133.3
1101_001
50.0
66.7
6
300.0 400.0
3.5
420.0 559.9
2.5
120.0 160.0
1101_010
50.0
66.7
6
300.0 400.0
4
480.0 639.9
2.5
120.0 160.0
1101_011
50.0
66.7
6
300.0 400.0
4.5
540.0 719.9
2.5
120.0 160.0
1101_100
50.0
66.7
6
300.0 400.0
5
600.0 799.9
2.5
120.0 160.0
1110_000
50.0
66.7
5
250.0 333.3
2.5
312.5 416.6
2
125.0 166.7
1110_001
50.0
66.7
5
250.0 333.3
3
375.0 500.0
2
125.0 166.7
1110_010
50.0
66.7
5
250.0 333.3
3.5
437.5 583.3
2
125.0 166.7
1110_011
50.0
66.7
5
250.0 333.3
4
500.0 666.6
2
125.0 166.7
1110_100
50.0
66.7
5
250.0 333.3
4
333.3 444.4
3
83.3 111.1
1110_101
50.0
66.7
5
250.0 333.3
4.5
375.0 500.0
3
83.3 111.1
1110_110
50.0
66.7
5
250.0 333.3
5
416.7 555.5
3
83.3 111.1
1110_111
50.0
66.7
5
250.0 333.3
5.5
458.3 611.1
3
83.3 111.1
Low
High
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
Low
High
Low
High
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
PCI_MODCK determines the PCI clock frequency range. See Table 20 for lower range configurations.
MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
39
Clock Configuration Modes
Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1,2
Mode3
MODCK_HMODCK[1-3]
PCI Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
Bus
Division
Factor
Bus Clock
(MHz)
Low
High
Default Modes (MODCK_H=0000)
0000_000
30.0
50.0
4
120.0 200.0
2.5
150.0 250.0
2
60.0 100.0
0000_001
25.0
50.0
4
100.0 200.0
3
150.0 300.0
2
50.0 100.0
0000_010
25.0
50.0
6
150.0 300.0
3
150.0 300.0
3
50.0 100.0
0000_011
25.0
50.0
6
150.0 300.0
4
200.0 400.0
3
50.0 100.0
0000_100
25.0
50.0
6
150.0 300.0
3
180.0 360.0
2.5
60.0 120.0
0000_101
25.0
50.0
6
150.0 300.0
3.5
210.0 420.0
2.5
60.0 120.0
0000_110
25.0
50.0
8
200.0 400.0
3.5
233.3 466.7
3
66.7 133.3
0000_111
25.0
50.0
8
200.0 400.0
3
240.0 480.0
2.5
80.0 160.0
Full Configuration Modes
0001_001
30.0
50.0
4
120.0 200.0
5
150.0 250.0
4
30.0
50.0
0001_010
25.0
50.0
4
100.0 200.0
6
150.0 300.0
4
25.0
50.0
0001_011
25.0
50.0
4
100.0 200.0
7
175.0 350.0
4
25.0
50.0
0001_100
25.0
50.0
4
100.0 200.0
8
200.0 400.0
4
25.0
50.0
0010_001
25.0
50.0
6
150.0 300.0
3
180.0 360.0
2.5
60.0 120.0
0010_010
25.0
50.0
6
150.0 300.0
3.5
210.0 420.0
2.5
60.0 120.0
0010_011
25.0
50.0
6
150.0 300.0
4
240.0 480.0
2.5
60.0 120.0
0010_100
25.0
50.0
6
150.0 300.0
4.5
270.0 540.0
2.5
60.0 120.0
0011_000
Reserved
0011_001
37.5
50.0
4
150.0 200.0
3
150.0 200.0
3
50.0
66.7
0011_010
32.1
50.0
4
128.6 200.0
3.5
150.0 233.3
3
42.9
66.7
0011_011
28.1
50.0
4
112.5 200.0
4
150.0 266.7
3
37.5
66.7
0011_100
25.0
50.0
4
100.0 200.0
4.5
150.0 300.0
3
33.3
66.7
0100_000
Reserved
0100_001
25.0
50.0
6
150.0 300.0
3
150.0 300.0
3
50.0 100.0
0100_010
25.0
50.0
6
150.0 300.0
3.5
175.0 350.0
3
50.0 100.0
0100_011
25.0
50.0
6
150.0 300.0
4
200.0 400.0
3
50.0 100.0
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
40
Freescale Semiconductor
Clock Configuration Modes
Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1,2 (continued)
Mode3
PCI Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Bus
Division
Factor
Bus Clock
(MHz)
MODCK_HMODCK[1-3]
Low
High
0100_100
25.0
50.0
6
150.0 300.0
4.5
225.0 450.0
3
50.0 100.0
0101_000
30.0
50.0
5
150.0 250.0
2.5
150.0 250.0
2.5
60.0 100.0
0101_001
25.0
50.0
5
125.0 250.0
3
150.0 300.0
2.5
50.0 100.0
0101_010
25.0
50.0
5
125.0 250.0
3.5
175.0 350.0
2.5
50.0 100.0
0101_011
25.0
50.0
5
125.0 250.0
4
200.0 400.0
2.5
50.0 100.0
0101_100
25.0
50.0
5
125.0 250.0
4.5
225.0 450.0
2.5
50.0 100.0
0101_101
25.0
50.0
5
125.0 250.0
5
250.0 500.0
2.5
50.0 100.0
0101_110
25.0
50.0
5
125.0 250.0
5.5
275.0 550.0
2.5
50.0 100.0
Low
High
0110_000
Low
High
Low
High
Reserved
0110_001
25.0
50.0
8
200.0 400.0
3
200.0 400.0
3
66.7 133.3
0110_010
25.0
50.0
8
200.0 400.0
3.5
233.3 466.7
3
66.7 133.3
0110_011
25.0
50.0
8
200.0 400.0
4
266.7 533.3
3
66.7 133.3
0110_100
25.0
50.0
8
200.0 400.0
4.5
300.0 600.0
3
66.7 133.3
0111_000
25.0
50.0
6
150.0 300.0
2
150.0 300.0
2
75.0 150.0
0111_001
25.0
50.0
6
150.0 300.0
2.5
187.5 375.0
2
75.0 150.0
0111_010
25.0
50.0
6
150.0 300.0
3
225.0 450.0
2
75.0 150.0
0111_011
25.0
50.0
6
150.0 300.0
3.5
262.5 525.0
2
75.0 150.0
1000_000
Reserved
1000_001
25.0
50.0
6
150.0 300.0
2.5
150.0 300.0
2.5
60.0 120.0
1000_010
25.0
50.0
6
150.0 300.0
3
180.0 360.0
2.5
60.0 120.0
1000_011
25.0
50.0
6
150.0 300.0
3.5
210.0 420.0
2.5
60.0 120.0
1000_100
25.0
50.0
6
150.0 300.0
4
240.0 480.0
2.5
60.0 120.0
1000_101
25.0
50.0
6
150.0 300.0
4.5
270.0 540.0
2.5
60.0 120.0
1001_000
Reserved
1001_001
Reserved
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
41
Clock Configuration Modes
Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1,2 (continued)
Mode3
MODCK_HMODCK[1-3]
PCI Clock
(MHz)
Low
High
CPM
Multiplication
Factor4
CPM Clock
(MHz)
Low
High
1001_010
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Low
High
Bus
Division
Factor
Bus Clock
(MHz)
Low
High
Reserved
1001_011
25.0
50.0
8
200.0 400.0
4
200.0 400.0
4
50.0 100.0
1001_100
25.0
50.0
8
200.0 400.0
4.5
225.0 450.0
4
50.0 100.0
1010_000
Reserved
1010_001
25.0
50.0
8
200.0 400.0
3
200.0 400.0
3
66.7 133.3
1010_010
25.0
50.0
8
200.0 400.0
3.5
233.3 466.7
3
66.7 133.3
1010_011
25.0
50.0
8
200.0 400.0
4
266.7 533.3
3
66.7 133.3
1010_100
25.0
50.0
8
200.0 400.0
4.5
300.0 600.0
3
66.7 133.3
1011_000
Reserved
1011_001
25.0
50.0
8
200.0 400.0
2.5
200.0 400.0
2.5
80.0 160.0
1011_010
25.0
50.0
8
200.0 400.0
3
240.0 480.0
2.5
80.0 160.0
1011_011
25.0
50.0
8
200.0 400.0
3.5
280.0 560.0
2.5
80.0 160.0
1011_100
25.0
50.0
8
200.0 400.0
4
320.0 640.0
2.5
80.0 160.0
1011_101
25.0
50.0
8
200.0 400.0
2.5
250.0 500.0
2
100.0 200.0
1011_110
25.0
50.0
8
200.0 400.0
3
300.0 600.0
2
100.0 200.0
1011_111
25.0
50.0
8
200.0 400.0
3.5
350.0 700.0
2
100.0 200.0
1100_101
25.0
50.0
6
150.0 300.0
4
200.0 400.0
3
50.0 100.0
1100_110
25.0
50.0
6
150.0 300.0
4.5
225.0 450.0
3
50.0 100.0
1100_111
25.0
50.0
6
150.0 300.0
5
250.0 500.0
3
50.0 100.0
1101_000
25.0
50.0
6
150.0 300.0
5.5
275.0 550.0
3
50.0 100.0
1101_001
25.0
50.0
6
150.0 300.0
3.5
210.0 420.0
2.5
60.0 120.0
1101_010
25.0
50.0
6
150.0 300.0
4
240.0 480.0
2.5
60.0 120.0
1101_011
25.0
50.0
6
150.0 300.0
4.5
270.0 540.0
2.5
60.0 120.0
1101_100
25.0
50.0
6
150.0 300.0
5
300.0 600.0
2.5
60.0 120.0
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
42
Freescale Semiconductor
Pinout
Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1,2 (continued)
Mode3
1
2
3
4
5
8
PCI Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
Bus
Division
Factor
Bus Clock
(MHz)
MODCK_HMODCK[1-3]
Low
High
1110_000
25.0
50.0
5
125.0 250.0
2.5
156.3 312.5
2
62.5 125.0
1110_001
25.0
50.0
5
125.0 250.0
3
187.5 375.0
2
62.5 125.0
1110_010
28.6
50.0
5
142.9 250.0
3.5
250.0 437.5
2
71.4 125.0
1110_011
25.0
50.0
5
125.0 250.0
4
250.0 500.0
2
62.5 125.0
1110_100
25.0
50.0
5
125.0 250.0
4
166.7 333.3
3
41.7
83.3
1110_101
25.0
50.0
5
125.0 250.0
4.5
187.5 375.0
3
41.7
83.3
1110_110
25.0
50.0
5
125.0 250.0
5
208.3 416.7
3
41.7
83.3
1110_111
25.0
50.0
5
125.0 250.0
5.5
229.2 458.3
3
41.7
83.3
Low
High
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
Low
High
Low
High
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
PCI_MODCK determines the PCI clock frequency range. See Table 19 for higher range configurations.
MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
Pinout
This figure and table show the pin assignments and pinout for the 516 PBGA package.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
43
Pinout
This figure shows the pinout of the 516 PBGA package as viewed from the top surface.
1
2
3
4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
A
B
B
C
D
C
D
E
E
F
G
F
G
H
H
J
J
K
L
K
L
M
M
N
N
P
R
P
R
T
U
T
U
V
V
W
Y
W
Y
AA
AA
AB
AB
AC
AD
AC
AD
AE
AE
AF
AF
1
2
3
4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Not to Scale
Figure 12. Pinout of the 516 PBGA Package (View from Top)
This table lists the pins of the MPC8272. Note that the pins in the “MPC8272/8271 Only” column relate
to Utopia functionality.
Table 21. Pinout
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
BR
A19
BG/IRQ6
D2
ABB/IRQ2
C1
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
44
Freescale Semiconductor
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
TS
D1
A0
A3
A1
B5
A2
D8
A3
C6
A4
A4
A5
A6
A6
B6
A7
C7
A8
B7
A9
A7
A10
D9
A11
E11
A12
C9
A13
B9
A14
D11
A15
A9
A16
B10
A17
A10
A18
B11
A19
A11
A20
D12
A21
A12
A22
D13
A23
B13
A24
C13
A25
C14
A26
B14
A27
D14
A28
E14
A29
A14
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
45
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
A30
B15
A31
A15
TT0
B3
TT1
E8
TT2
D7
TT3
C4
TT4
E7
TBST
E3
TSIZ0
E4
TSIZ1
E5
TSIZ2
C3
TSIZ3
D5
AACK
D3
ARTRY
C2
DBG/IRQ7
F16
DBB/IRQ3
D18
D0
AC1
D1
AA1
D2
V3
D3
R5
D4
P4
D5
M4
D6
J4
D7
G1
D8
W6
D9
Y3
D10
V1
D11
N6
D12
P3
D13
M2
D14
J5
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
46
Freescale Semiconductor
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
D15
G3
D16
AB3
D17
Y1
D18
T4
D19
T3
D20
P2
D21
M1
D22
J1
D23
G4
D24
AB2
D25
W4
D26
V2
D27
T1
D28
N5
D29
L1
D30
H1
D31
G5
D32
W5
D33
W2
D34
T5
D35
T2
D36
N1
D37
K3
D38
H2
D39
F1
D40
AA2
D41
W1
D42
U3
D43
R2
D44
N2
D45
L2
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
47
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
D46
H4
D47
F2
D48
AB1
D49
U4
D50
U1
D51
R3
D52
N3
D53
K2
D54
H5
D55
F4
D56
AA3
D57
U5
D58
U2
D59
P5
D60
M3
D61
K4
D62
H3
D63
E1
IRQ3/CKSTP_OUT/EXT_BR3
B16
IRQ4/CORE_SRESET/EXT_BG3
C15
IRQ5/TBEN/EXT_DBG3/CINT
Y4
PSDVAL
C19
TA
AA4
TEA
AB6
GBL/IRQ1
D15
CI/BADDR29/IRQ2
D16
WT/BADDR30/IRQ3
C16
BADDR31/IRQ5/CINT
E17
CPU_BR/INT_OUT
B20
CS0
AE6
CS1
AD7
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
48
Freescale Semiconductor
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
CS2
AF5
CS3
AC8
CS4
AF6
CS5
AD8
CS6/BCTL1/SMI
AC9
CS7/TLBISYNC
AB9
BADDR27/IRQ1
AB8
BADDR28/IRQ2
AC7
ALE/IRQ4
AF4
BCTL0
AF3
PWE0/PSDDQM0/PBS0
AD6
PWE1/PSDDQM1/PBS1
AE5
PWE2/PSDDQM2/PBS2
AE3
PWE3/PSDDQM3/PBS3
AF2
PWE4/PSDDQM4/PBS4
AC6
PWE5/PSDDQM5/PBS5
AC5
PWE6/PSDDQM6/PBS6
AD4
PWE7/PSDDQM7/PBS7
AB5
PSDA10/PGPL0
AE2
PSDWE/PGPL1
AD3
POE/PSDRAS/PGPL2
AB4
PSDCAS/PGPL3
AC3
PGTA/PUPMWAIT/PGPL4
AD2
PSDAMUX/PGPL5
AC2
PCI_MODE1
AD22
PCI_CFG0 (PCI_HOST_EN)
AC21
PCI_CFG1 (PCI_ARB_EN)
AE22
PCI_CFG2 (DLL_ENABLE)
AE23
PCI_ PAR
AF12
PCI_FRAME
AD15
PCI_TRDY
AF16
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
49
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
PCI_IRDY
AF15
PCI_STOP
AE15
PCI_DEVSEL
AE14
PCI_IDSEL
AC17
PCI_PERR
AD14
PCI_SERR
AD13
PCI_REQ0
AE20
PCI_REQ1/CPCI_HS_ES
AF14
PCI_GNT0
AD20
PCI_GNT1/CPCI_HS_LED
AE13
PCI_GNT2/CPCI_HS_ENUM
AF21
PCI_RST
AF22
PCI_INTA
AE21
PCI_REQ2
AB14
DLLOUT
AC22
PCI_AD0
AF7
PCI_AD1
AE10
PCI_AD2
AB10
PCI_AD3
AD10
PCI_AD4
AE9
PCI_AD5
AF8
PCI_AD6
AC10
PCI_AD7
AE11
PCI_AD8
AB11
PCI_AD9
AF10
PCI_AD10
AF9
PCI_AD11
AB12
PCI_AD12
AC12
PCI_AD13
AD12
PCI_AD14
AF11
PCI_AD15
AB13
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
50
Freescale Semiconductor
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
PCI_AD16
AE16
PCI_AD17
AF17
PCI_AD18
AD16
PCI_AD19
AC16
PCI_AD20
AF18
PCI_AD21
AB16
PCI_AD22
AD17
PCI_AD23
AF19
PCI_AD24
AB17
PCI_AD25
AF20
PCI_AD26
AE19
PCI_AD27
AC18
PCI_AD28
AB18
PCI_AD29
AD19
PCI_AD30
AD21
PCI_AD31
AC20
PCI_C0/BE0
AE12
PCI_C1/BE1
AF13
PCI_C2/BE2
AC15
PCI_C3/BE3
AE18
IRQ0/NMI_OUT
A17
TRST2
E21
TCK
B22
TMS
C23
TDI
B24
TDO
A22
TRIS
B23
PORESET2
/PCI_RST
C24
HRESET
D22
SRESET
F22
RSTCONF
A24
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
51
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
MODCK1/RSRV/TC0/BNKSEL0
A20
MODCK2/CSE0/TC1/BNKSEL1
C20
MODCK3/CSE1/TC2/BNKSEL2
A21
CLKIN1
D21
PA8/SMRXD2
AF253
PA9/SMTXD2
AA223
PA10/MSNUM5
FCC1_UT_RXD0
AB233
PA11/MSNUM4
FCC1_UT_RXD1
AD263
PA12/MSNUM3
FCC1_UT_RXD2
AD253
PA13/MSNUM2
FCC1_UT_RXD3
AA243
PA14/FCC1_MII_HDLC_RXD3
FCC1_UT_RXD4
W223
PA15/FCC1_MII_HDLC_RXD2
FCC1_UT_RXD5
Y243
PA16/FCC1_MII_HDLC_RXD1
FCC1_UT_RXD6
T223
PA17/FCC1_MII_HDLC_RXD0/
FCC1_MII_TRAN_RXD/FCC1_RMII_RX
D0
FCC1_UT_RXD7
W263
PA18/FCC1_MII_HDLC_TXD0/FCC1_MII
_TRAN_TXD/
FCC1_RMII_TXD0
FCC1_UT_TXD7
V263
PA19/FCC1_MII_HDLC_TXD1/FCC1_RM
II_TXD1
FCC1_UT_TXD6
R233
PA20/FCC1_MII_HDLC_TXD2
FCC1_UT_TXD5
P253
PA21/FCC1_MII_HDLC_TXD3
FCC1_UT_TXD4
N223
PA22
FCC1_UT_TXD3
N263
PA23
FCC1_UT_TXD2
N233
PA24/MSNUM1
FCC1_UT_TXD1
H263
PA25/MSNUM0
FCC1_UT_TXD0
G253
PA26/FCC1_MII_RMIIRX_ER
FCC1_UT_RXCLAV
L223
PA27/FCC1_MII_RX_DV/FCC1_RMII_CR
S_DV
FCC1_UT_RXSOC
G243
PA28/FCC1_MII_RMII_TX_EN
FCC1_UT_RXENB
G233
PA29/FCC1_MII_TX_ER
FCC1_UT_TXSOC
B263
PA30/FCC1_MII_CRS/FCC1_RTS
FCC1_UT_TXCLAV
A253
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
52
Freescale Semiconductor
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
PA31/FCC1_MII_COL
FCC1_UT_TXENB
G223
PB18/FCC2_MII_HDLC_RXD3
T253
PB19/FCC2_MII_HDLC_RXD2
P223
PB20/FCC2_MII_HDLC_RMII_RXD1
L253
PB21/FCC2_MII_HDLC_RMII_RXD0/FCC2_TRAN_RXD
J263
PB22/FCC2_MII_HDLC_TXD0/FCC2_TRAN_TXD/
FCC2_RMII_TXD0
U233
PB23/FCC2_MII_HDLC_TXD1/FCC2_RMII_TXD1
U263
PB24/FCC2_MII_HDLC_TXD2/L1RSYNCB2
M243
PB25/FCC2_MII_HDLC_TXD3/L1TSYNCB2
M233
PB26/FCC2_MII_CRS/L1RXDB2
H243
PB27/FCC2_MII_COL/L1TXDB2
E253
PB28/FCC2_MII_RMII_RX_ER/FCC2_RTS/TXD1
D263
PB29/FCC2_MII_RMII_TX_EN
K213
PB30/FCC2_MII_RX_DV/FCC2_RMII_CRS_DV
D243
PB31/FCC2_MII_TX_ER
E233
PC0/DREQ3/BRGO7/SMSYN1/L1CLKOA2
AF233
PC1/BRGO6/L1RQA2
AD233
PC4/SMRXD1/SI2_L1ST4/FCC2_CD
AB223
PC5/SMTXD1/SI2_L1ST3/FCC2_CTS
AE243
PC6/FCC1_CD/SI2_L1ST2
FCC1_UT_RXADDR2
AF243
PC7/FCC1_CTS
FCC1_UT_TXADDR2
AE263
PC8/CD4/RTS1/SI2_L1ST2/CTS3
AC243
PC9/CTS4/L1TSYNCA2
AA233
PC10/CD3/USB_RN
AB253
PC11/CTS3/USB_RP/L1TXD3A2
V223
PC12
FCC1_UT_RXADDR1
AA263
PC13/BRGO5
FCC1_UT_TXADDR1
V233
PC14/CD1
FCC1_UT_RXADDR0
W243
PC15/CTS1
FCC1_UT_TXADDR0
U243
PC16/CLK16
T233
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
53
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
PC17/CLK15/BRGO8/DONE2
T263
PC18/CLK14/TGATE2
R263
PC19/CLK13/BRGO7/TGATE1
P243
PC20/CLK12/USBOE
L263
PC21/CLK11/BRGO6/CP_INT
L243
PC22/CLK10/DONE3
FCC1_UT_TXPRTY
L233
PC23/CLK9/BRGO5/DACK3/CD1
K243
PC24/CLK8/TIN3/TOUT4/DREQ2/BRGO1
K233
PC25/CLK7/BRGO4/DACK2/SPISEL
F263
PC26/CLK6/TOUT3/TMCLK
H233
PC27/CLK5/BRGO3/TOUT1
FCC1_UT_RXPRTY
K223
PC28/CLK4/TIN1/TOUT2/SPICLK
D253
PC29/CLK3/TIN2/BRGO2/CTS1
F243
PD7/SMSYN2
FCC1_UT_TXADDR3
AB213
PD14/I2CSCL
AC263
PD15/I2CSDA
Y233
PD16/SPIMISO
FCC1_UT_TXPRTY
AA253
PD17/BRGO2/SPIMOSI
FCC1_UT_RXPRTY
Y263
PD18/SPICLK
FCC1_UT_RXADDR4
W253
PD19/SPISEL/BRGO1
FCC1_UT_TXADDR4
V253
PD20/RTS4/L1RSYNCA2
R243
PD21/TXD4/L1RXD0A2
P233
PD22/RXD4/L1TXD0A2
N253
PD23/RTS3/USB_TP
K263
PD24/TXD3/USB_TN
K253
PD25/RXD3/USB_RXD
J253
PD29/RTS1
FCC1_UT_RXADDR3
C263
PD30/TXD1
E243
PD31/RXD1
B253
VCCSYN
C18
VCCSYN1
K6
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
54
Freescale Semiconductor
Pinout
Table 21. Pinout (continued)
Pin Name
Ball
MPC8272/MPC8248 and
MPC8271/MPC8247
MPC8272/MPC8271 Only
CLKIN2
No
C21
connect4
4
D19 , J34, AD245
I/O power
B4, F3, J2, N4, AD1, AD5, AE8,
AC13, AD18, AB24, AB26, W23, R25,
M25, F25, C25, C22, B17, B12, B8,
E6, F6, H6, L5, L6, P6, T6, U6, V5,
Y5, AA6, AA8, AA10, AA11, AA14,
AA16, AA17, AB19, AB20, W21, U21,
T21, P21, N21, M22, J22, H21, F21,
F19, F17, E16, F14, E13, E12, F10,
E10, E9
Core Power
F5, K5, M5, AA5, AB7, AA13, AA19,
AA21, Y22, AC25, U22, R22, L21,
H22, E22, E20, E15, F13, F11, F8,
L3, V4, W3, AC11, AD11, AB15, U25,
T24, J24, H25, F23, B19, D17, C17,
D10, C10
Ground
E19, E2, K1, Y2, AE1, AE4, AD9,
AC14, AE17, AC19, AE25, V24, P26,
M26, G26, E26, B21, C12, C11, C8,
A8, B18, A18, A2, B1, B2, A5, C5, D4,
D6, G2, L4, P1, R1, R4, AC4, AE7,
AC23, Y25, N24, J23, A23, D23, D20,
E18, A13, A16, K10, K11, K12, K13,
K14, K15, K16, K17, L10, L11, L12,
L13, L14, L15, L16, L17, M10, M11,
M12, M13, M14, M15, M16, M17,
N10, N11, N12, N13, N14, N15, N16,
N17, P10, P11, P12, P13, P14, P15,
P16, P17, R10, R11,R12, R13, R14,
R15, R16, R17, T10, T11, T12, T13,
T14, T15, T16, T17, U10, U11, U12,
U13, U14, U15, U16, U17
1
Must be tied to ground.
Should be tied to VDDH via a 2K Ω external pull-up resistor.
3 The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent
excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs.
4 This pin is not connected. It should be left floating.
5 Must be pulled down or left floating
2
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
55
Package Description
9
Package Description
This figure shows the side profile of the PBGA package to indicate the direction of the top surface view.
Transfer molding compound
Die
attach
Wire bonds
Ball bond
Screen-printed
solder mask
Plated substrate via
Cu substrate traces
DIE
Resin glass epoxy
1 mm pitch
Figure 13. Side View of the PBGA Package Remove
9.1
Package Parameters
This table provides package parameters.
Table 22. Package Parameters
Code
Type
Outline
(mm)
Interconnects
Pitch
(mm)
Nominal Unmounted
Height (mm)
VR, ZQ
PBGA
27 x 27
516
1
2.25
NOTE: Temperature Reflow for the VR Package
In the VR package, sphere composition is lead-free (see Table 2). This
requires higher temperature reflow than what is required for other
PowerQUICC II packages. Consult “Freescale PowerQUICC II Pb-Free
Packaging Information” (MPC8250PBFREEPKG) available on
www.freescale.com.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
56
Freescale Semiconductor
Package Description
9.2
Mechanical Dimensions
This figure provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA
package.
Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
57
Ordering Information
10 Ordering Information
This figure provides an example of the Freescale part numbering nomenclature for the SoC. In addition to
the processor frequency, the part numbering scheme also consists of a part modifier that indicates any
enhancement(s) in the part from the original production design. Each part number also contains a revision
code that refers to the die mask revision number and is specified in the part numbering scheme for
identification purposes only. For more information, contact your local Freescale sales office.
MPC 82XX C VR XXX X
Die revision level
Product code
Device number
Processor frequency
CPU/CPM/Bus in MHz)
B = 66
E = 100
F = 133
I = 200
M = 266
P = 300
T = 400
Temperature range
Blank = 0 to 105 °C
C = –40 to 105 °C
Package
ZQ = 516 PBGA (lead spheres)
VR = 516 PBGA (no lead spheres)
Figure 15. Freescale Part Number Key
11 Document Revision History
This table summarizes changes to this document.
Table 23. Document Revision History
Revision
Date
Substantive Changes
3
09/2011 In Figure 15, “Freescale Part Number Key,” added speed decoding information below processor
frequency information.
2
12/2008
• Modified Figure 5, “SCC/SMC/SPI/I2C External Clock Diagram,” and added second section of
figure notes.
• In Table 12, modified “Data bus in pipeline mode” row and showed 66 MHz as “N/A.”
• In Section 10, “Ordering Information,” added “F = 133” to CPU/CPM/Bus Frequency.
• Added footnote concerning CPM_CLK/PCI_CLK ratio to column “PCI Division Factor” in
Table 17, “Clock Configurations for PCI Host Mode (PCI_MODCK=0),” and Table 18, “Clock
Configurations for PCI Host Mode (PCI_MODCK=1),.”
• Removed overbar from DLL_ENABLE in Table 21, “Pinout.”
1.5
12/2006
• Section 6, “AC Electrical Characteristics,” removed deratings statement and clarified AC
timing descriptions.
1.4
05/2006
• Added row for 133 MHz configurations to Table 8.
1.3
02/2006
• Inserted Section 6.3, “JTAG Timings.”
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
58
Freescale Semiconductor
Document Revision History
Table 23. Document Revision History (continued)
Date
Substantive Changes
1.2
09/2005
• Added 133-MHz to the list of frequencies in the opening sentence of Section 6, “AC Electrical
Characteristics”.
• Added 133 MHz columns to Table 9, Table 11, Table 12, and Table 13.
• Added footnote 2 to Table 13.
• Added the conditions note directly above Table 12.
1.1
01/2005
• Modification for correct display of assertion level (“overbar”) for some signals
1.0
12/2004
•
•
•
•
•
Revision
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier values
Section 2: removed voltage tracking note
Table 3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset
Table 4: Updated VDD and VCCSYN to 1.425 V - 1.575 V
Table 8: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external
pull-up removed.
Section 4.6: Updated description of layout practices
Table 8: Note 3 added regarding IIC compatibility
Table 8: Updated nominal and maximum power dissipation values
Table 9: updated PCI impedance to 27Ω, updated 60x and MEMC values and added note to
reflect configurable impedance
Section 6: Added sentence providing derating factor
Section 6.1: added Note: Rise/Fall Time on CPM Input Pins
Table 9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41,
sp42, sp43, sp42a
Table 11: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22
Section 6.2: added spread spectrum clocking note
Section 6.2: added CLKIN jitter note
Table 12: combined specs sp11 and sp11a
Table 13: sp30 Data Bus minimum delay values changed to 0.8
Section 7: unit of ns added to Tval notes
Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp
devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Section 7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin
of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Table 21: correct superscript of footnote number after pin AD22
Table 21: remove DONE3 from PC12
Table 21: signals referring to TDMs C2 and D2 removed
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
59
Document Revision History
Table 23. Document Revision History (continued)
Revision
0.2
Date
12/2003
Substantive Changes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Table 1: New
Table 2: New
Table 4: Modification of VDD and VCCSYN to 1.45–1.60 V
Table 8: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 8)
Table 8 and Table 21: Addition of muxed signals
CPCI_HS_ES to PCI_REQ1 (AF14)
CPCI_HS_LED to PCI_GNT1 (AE13)
CPCI_HS_ENUM to PCI_GNT2 (AF21)
Table 8 and Table 21: Modification of PCI signal names for consistency with PCI signal names
on other PowerQUICC II devices:
PCI_CFG0 (PCI_HOST_EN) (AC21)
PCI_CFG1 (PCI_ARB_EN) (AE22)
PCI_CFG2 (DLL_ENABLE) (AE23)
PCI_PAR (AF12)
PCI_FRAME (AD15)
PCI_TRDY(AF16)
PCI_IRDY (AF15)
PCI_STOP (AE15)
DEVSEL (AE14)
PCI_IDSEL (AC17)
PCI_PERR (AD14)
PCI_SERR (AD13)
PCI_REQ0–2 (AAE20, AF14, AB14)
PCI_GNT0–2 (AD20, AE13, AF21)
PCI_RST (AF22)
PCI_INTA (AE21)
PCI_C0-3 (AE12, AF13, AC15, AE18)
PCI_AD0-31
Table 8 and Table 21: Corrected assertion level (added “ “) PCI_HOST_EN (AC21) and
PCI_ARB_EN (AE22)
Table 7: Addition of RθJT and note 4
Sections 4.1–4.5 and 4.7 on thermal characteristics: New
Section 7, “Clock Configuration Modes”: Modification to first paragraph. Note that
PCI_MODCK is a bit in the Hard Reset Configuration Word. It is not an input signal as it is in
the MPC8280 Family and MPC8260 Family.
Addition of “Note: Temperature Reflow for the VR Package" on page 56
Table 21: Addition of note 2 to TRST (E21) and PORESET (C24)
Table 21: Removal of Thermal0 (D19) and Thermal1(J3). These pins are now “No connects.”
Note 4 unchanged.
Table 21: Removal of Spare0 (AD24). This pin is now a “No connect.” Note 5 unchanged.
Table 21: Addition of PCI_MODE (AD22). This pin was previously listed as “Ground.” Addition
of note 1.
0.1
9/2003
•
•
•
•
•
Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine)
Table 8: Addition of note 2 to VIH
Table 8: Changed IOL for 60x signals to 6.0 mA
Modification of note 1 for Table 17, Table 18, Table 19, and Table 20
Table 21: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned
to both CS5 and GND. AD8 is only assigned to CS5.
• Table 21: Addition of note 4 to Thermal0 (D19) and Thermal1(J3)
• Addition of ZQ package code to Figure 15
0
5/2003
NDA release
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
60
Freescale Semiconductor
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Document Number: MPC8272EC
Rev. 3
09/2011
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