Freescale Semiconductor
Document Number: MPC885EC
Rev. 7, 07/2010
Technical Data
MPC885/MPC880 PowerQUICC
Hardware Specifications
This hardware specification contains detailed information on
power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MPC885/MPC880. The
MPC885 is the superset device of the MPC885/MPC880
family. The CPU on the MPC885/MPC880 is a 32-bit core
built on Power Architecture™ technology that incorporates
memory management units (MMUs) and instruction and
data caches. For functional characteristics of the
MPC885/MPC880, refer to the MPC885 PowerQUICC
Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC875/MPC870 product summary page on our
website listed on the back cover of this document or, contact
your local Freescale sales office.
© 2010 Freescale Semiconductor, Inc. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 9
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Calculation and Measurement . . . . . . . . . . 12
Power Supply and Power Sequencing . . . . . . . . . . . 15
Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44
CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46
UTOPIA AC Electrical Specifications . . . . . . . . . . . 69
USB Electrical Characteristics . . . . . . . . . . . . . . . . . 71
FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 71
Mechanical Data and Ordering Information . . . . . . . 75
Document Revision History . . . . . . . . . . . . . . . . . . . 85
Overview
1
Overview
The MPC885/MPC880 is a versatile single-chip integrated microprocessor and peripheral combination
that can be used in a variety of controller applications and communications and networking systems. The
MPC885/MPC880 provides enhanced ATM functionality, an additional fast Ethernet controller, a USB,
and an encryption block.
Table 1 shows the functionality supported by MPC885/MPC880.
Table 1. MPC885 Family
Cache (Kbytes)
Ethernet
Part
SCC
SMC
USB
ATM Support
Security
Engine
I Cache
D Cache
10BaseT
10/100
MPC885
8
8
Up to 3
2
3
2
1
Serial ATM and
UTOPIA interface
Yes
MPC880
8
8
Up to 2
2
2
2
1
Serial ATM and
UTOPIA interface
No
2
Features
The MPC885/MPC880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx
core, a system integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC885/MPC880 features:
• Embedded MPC8xx core up to 133 MHz
• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
• Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional
execution.
— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip emulation debug mode
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Freescale Semiconductor
Features
•
•
•
•
•
•
•
Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes
the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell
transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also
supported.)
— Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
— Supports full-duplex UTOPIA master (ATM side) and slave (PHY side) operations using a split
bus
— AAL2/VBR functionality is ROM-resident
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
Thirty-two address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture
Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS
that interface through MII and/or RMII interfaces
System integration unit (SIU)
— Bus monitor
— Software watchdog
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
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Features
•
•
•
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE Std 1149.1™ test access port (JTAG)
Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
IEEE Std 802.11i™, and iSCSI processing. Available on the MPC885, the security engine contains
a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rijndael symmetric key cipher
– ECB, CBC, and counter modes
– 128-, 192-, and 256- bit key lengths
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Crypto-channel supporting multi-command descriptor chains
— Integrated controller managing internal resources and bus mastering
— Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes
Interrupts
— Six external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Several serial DMA (SDMA) channels to support the CPM
— Three parallel I/O registers with open-drain capability
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Freescale Semiconductor
Features
•
•
•
•
•
On-chip 16 × 16 multiply accumulate controller (MAC)
— One operation per clock (two-clock latency, one-clock blockage)
— MAC operates concurrently with other instructions
— FIR loop—Four clocks per four multiplies
Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
Up to three serial communication controllers (SCCs) supporting the following protocols:
— Serial ATM capability on SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE Std 802.3™ optional on the SCC(s) supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
Up to two serial management channels (SMCs) supporting the following protocols:
— UART (low-speed operation)
— Transparent
— General circuit interface (GCI) controller
— Provide management for BRI devices as GCI controller in time-division multiplexed (TDM)
channels
Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host
controller, or both for testing purposes (loop-back diagnostics)
— USB 2.0 full-/low-speed compatible
— The USB function mode has the following features:
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
5
Features
•
•
•
•
•
•
•
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— The USB host controller has the following features:
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loop back mode for diagnostics (12 Mbps only)
Serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
Inter-integrated circuit (I2C) port
— Supports master and slave modes
— Supports a multiple-master environment
Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to four serial channels (two SCCs and two SMCs)
Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC885/MPC880 and other MPC8xx
devices
PCMCIA interface
— Master (socket) interface, release 2.1-compliant
— Supports two independent PCMCIA sockets
— 8 memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally.
Normal high and normal low power modes to conserve power
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Freescale Semiconductor
Features
•
•
1.8-V core and 3.3-V I/O operation
The MPC885/MPC880 comes in a 357-pin ball grid array (PBGA) package
The MPC885 block diagram is shown in Figure 1.
8-Kbyte
Instruction
Instruction Cache
Bus
System Interface Unit (SIU)
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Memory Controller
Unified
Bus
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
System Functions
Data MMU
Load/Store
Bus
32-Entry DTLB
PCMCIA-ATA Interface
Slave/Master IF
Security Engine
Fast Ethernet
Controller
Controller
AESU
DEU
MDEU
Channel
DMAs
DMAs
DMAs
FIFOs
4
Timers
Parallel I/O
10/100
BaseT
Media Access
Control
4 Baud Rate
Generators
MIII/RMII
Parallel Interface
Port
USB
Timers
SCC2
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
SCC3
SCC4/
UTOPIA SMC1
Virtual IDMA
and
Serial DMAs
SMC2
SPI
I2C
Time-Slot Assigner
Serial Interface
Figure 1. MPC885 Block Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
7
Features
The MPC880 block diagram is shown in Figure 2.
Instruction
8-Kbyte
Bus
Instruction Cache
System Interface Unit (SIU)
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Unified
Bus
8-Kbyte
Data Cache
Memory Controller
External
Internal
Bus Interface Bus Interface
Unit
Unit
System Functions
Data MMU
Load/Store
Bus
32-Entry DTLB
PCMCIA-ATA Interface
Slave/Master IF
Fast Ethernet
Controller
DMAs
DMAs
FIFOs
Parallel I/O
10/100
BaseT
Media Access
Control
4 Baud Rate
Generators
MIII/RMII
Parallel Interface
Port
USB
4
Timers
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
Virtual IDMA
and
Serial DMAs
Timers
SCC4/
SCC3 UTOPIA SMC1
SMC2
SPI
I 2C
Time-Slot Assigner
Serial Interface
Figure 2. MPC880 Block Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Freescale Semiconductor
Maximum Tolerated Ratings
3
Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC885/MPC880.
Table 2 displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.
Table 2. Maximum Tolerated Ratings
Rating
Symbol
Value
Unit
VDDH
–0.3 to 4.0
V
VDDL
–0.3 to 2.0
V
VDDSYN
–0.3 to 2.0
V
Difference between VDDL and VDDSYN
100 kHz) timings.
Table 29. I2C Timing (SCL > 100 kHZ)
All Frequencies
Num
1
Characteristic
Expression
Unit
Min
Max
200
SCL clock frequency (slave)
fSCL
0
BRGCLK/48
Hz
200
SCL clock frequency (master)1
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
—
1/(2.2 × fSCL)
—
s
203
Low period of SCL
—
1/(2.2 × fSCL)
—
s
204
High period of SCL
—
1/(2.2 × fSCL)
—
s
205
Start condition setup time
—
1/(2.2 × fSCL)
—
s
206
Start condition hold time
—
1/(2.2 × fSCL)
—
s
207
Data hold time
—
0
—
s
208
Data setup time
—
1/(40 × fSCL)
—
s
209
SDL/SCL rise time
—
—
1/(10 × fSCL)
s
210
SDL/SCL fall time
—
—
1/(33 × fSCL)
s
211
Stop condition setup time
—
1/2(2.2 × fSCL)
—
s
SCL frequency is given by SCL = BrgClk_frequency/((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
Figure 70 shows the I2C bus timing.
SDA
202
203
205
204
208
207
SCL
206
209
210
211
Figure 70. I2C Bus Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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UTOPIA AC Electrical Specifications
13 UTOPIA AC Electrical Specifications
Table 30, Table 31, and Table 32, show the AC electrical specifications for the UTOPIA interface.
Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications
Num
U1
Signal Characteristic
UtpClk rise/fall time (internal clock option)
Direction
Min
Output
Duty cycle
50
Frequency
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (PHREQ
and PHSEL active delay in multi-PHY mode)
U3
U4
Max
Unit
4
ns
50
%
33
MHz
16
ns
Output
2
UTPB, SOC, Rxclav, and Txclav setup time
Input
4
ns
UTPB, SOC, Rxclav, and Txclav hold time
Input
1
ns
Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications
Num
U1
Signal Characteristic
UtpClk rise/fall time (Internal clock option)
Direction
Min
Output
Duty cycle
50
Frequency
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (PHREQ
and PHSEL active delay in multi-PHY mode)
U3
U4
Max
Unit
4
ns
50
%
33
MHz
16
ns
Output
2
UTPB_Aux, SOC_Aux, Rxclav, and Txclav setup time
Input
4
ns
UTPB_Aux, SOC_Aux, Rxclav, and Txclav hold time
Input
1
ns
Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications
Num
U1
Signal Characteristic
UtpClk rise/fall time (external clock option)
Direction
Min
Input
Duty cycle
40
Frequency
U2
UTPB, SOC, Rxclav, and Txclav active delay
U3
U4
Max
Unit
4
ns
60
%
33
MHz
16
ns
Output
2
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time
Input
4
ns
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time
Input
1
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
69
UTOPIA AC Electrical Specifications
Figure 71 shows signal timings during UTOPIA receive operations.
U1
U1
UtpClk
U2
PHREQn
U3
3
U4
4
RxClav
High-Z at MPHY
High-Z at MPHY
U2
2
RxEnb
U3
3
UTPB
SOC
U4
Figure 71. UTOPIA Receive Timing
Figure 72 shows signal timings during UTOPIA transmit operations.
U1
U1
1
UtpClk
U2
5
PHSELn
U3
3
U4
4
TxClav
High-Z at MPHY
High-Z at Multi-PHYPHY
U2
2
TxEnb
U2
5
UTPB
SOC
Figure 72. UTOPIA Transmit Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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USB Electrical Characteristics
14 USB Electrical Characteristics
This section provides the AC timings for the USB interface.
14.1
USB Interface AC Timing Specifications
The USB Port uses the transmit clock on SCC1. Table 33 lists the USB interface timings.
Table 33. USB Interface AC Timing Specifications
All Frequencies
Name
Characteristic
Unit
Min
US1
US4
1
USBCLK frequency of operation1
Low speed
Full speed
Max
6
48
USBCLK duty cycle (measured at 1.5 V)
45
MHz
MHz
55
%
USBCLK accuracy should be ±500 ppm or better. USBCLK may be stopped to conserve power.
15 FEC Electrical Characteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 or
3.3 V.
15.1
MII and Reduced MII Receive Signal Timing
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The
reduced MII (RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of
50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed the MII_RX_CLK frequency – 1%.
Table 34 provides information on the MII and RMII receive signal timing.
Table 34. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
MII_RXD[3:0], MII_RX_DV, MII_RX_ERR to MII_RX_CLK setup
5
—
ns
M2
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
5
—
ns
M3
MII_RX_CLK pulse width high
35%
65%
MII_RX_CLK period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK period
M1_RMII
RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK
setup
4
—
ns
M2_RMII
RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR
hold
2
—
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
71
FEC Electrical Characteristics
Figure 73 shows MII receive signal timing.
M3
MII_RX_CLK (Input)
M4
MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 73. MII Receive Signal Timing Diagram
15.2
MII and Reduced MII Transmit Signal Timing
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. The
RMII transmitter functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%.
There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency – 1%.
Table 35 provides information on the MII and RMII transmit signal timing.
Table 35. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
5
—
ns
M6
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
—
25
ns
M20_RMII
RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup
4
—
ns
M21_RMII
RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
edge
2
—
ns
M7
MII_TX_CLK and RMII_REFCLK pulse width high
35%
65%
MII_TX_CLK or
RMII_REFCLK
period
M8
MII_TX_CLK and RMII_REFCLK pulse width low
35%
65%
MII_TX_CLK or
RMII_REFCLK
period
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Freescale Semiconductor
FEC Electrical Characteristics
Figure 74 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (Input)
RMII_REFCLK
M5
M8
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 74. MII Transmit Signal Timing Diagram
15.3
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 36 provides information on the MII async inputs signal timing.
Table 36. MII Async Inputs Signal Timing
Num
M9
Characteristic
Min
Max
Unit
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK period
Figure 75 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 75. MII Async Inputs Timing Diagram
15.4
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 37 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz.
Table 37. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
0
—
ns
M11
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
—
25
ns
M12
MII_MDIO (input) to MII_MDC rising edge setup
10
—
ns
M13
MII_MDIO (input) to MII_MDC rising edge hold
0
—
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
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FEC Electrical Characteristics
Table 37. MII Serial Management Channel Timing (continued)
Num
Characteristic
Min
Max
Unit
M14
MII_MDC pulse width high
40%
60%
MII_MDC period
M15
MII_MDC pulse width low
40%
60%
MII_MDC period
Figure 76 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (Output)
M10
MII_MDIO (Output)
M11
MII_MDIO (Input)
M12
M13
Figure 76. MII Serial Management Channel Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Mechanical Data and Ordering Information
16 Mechanical Data and Ordering Information
Table 38 identifies the available packages and operating frequencies for the MPC885/MPC880 derivative
devices.
Table 38. Available MPC885/MPC880 Packages/Frequencies
Package Type
Plastic ball grid array
ZP suffix — Leaded
VR suffix — Lead-Free are available as needed
Plastic ball grid array
CZP suffix — Leaded
CVR suffix — Lead-Free are available as needed
Temperature (Tj)
Frequency (MHz)
Order Number
0°C to 95°C
66
KMPC885ZP66
KMPC880ZP66
MPC885ZP66
MPC880ZP66
80
KMPC885ZP80
KMPC880ZP80
MPC885ZP80
MPC880ZP80
133
KMPC885ZP133
KMPC880ZP133
MPC885ZP133
MPC880ZP133
66
KMPC885CZP66
KMPC880CZP66
MPC885CZP66
MPC880CZP66
133
KMPC885CZP133
KMPC880CZP133
MPC885CZP133
MPC880CZP133
-40°C to 100°C
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
75
Mechanical Data and Ordering Information
16.1
Pin Assignments
Figure 77 shows the top-view pinout of the PBGA package. For additional information, see the MPC885
PowerQUICC™ Family Reference Manual.
NOTE: This is the top view of the device.
W
TRST
PA10
PB23
PA8
TMS
PB25
PC11
PB22
PB27
PB14
TCK
PB24
PB29
PC12
TDO
TDI
PC15
PC14
PB26
GND
VDDL
MII_MDIO
PB30
PA14
PA12
VDDH
A2
A1
N/C
PA15
A3
A5
A4
A0
A7
A9
A8
A6
A10
A11
A12
A13
A14
A16
A15
A17
A27
A19
A20
A24
A21
A29
A23
TSIZ0
A25
A30
A22
BSA3
A18
A28
TSIZ1
WE1
A26
A31
BSA0
GPL_AB2
CS6
CS3
WR
BI
BR
IRQ6
IPB1
ALEB
AS
BSA2
BSA1
WE2
CS4
CE2_A
CS1
GPL_A5
TA
BG
BURST
IPB3
IPB2
IRQ4
OP1
BADDR28
WAIT_B VSSSYN1
IPA1
WE3
WE0
GPL_A0
CS7
CE1_A
CS0
GPL_A4
TEA
BB
IRQ2
IPB4
IPB7
ALEA
OP0
BADDR29 HRESET PORESETVDDLSYN
IPA0
OE
GPL_AB3
CS5
CS2
GPL_B4
BDIP
TS
IRQ3
IPB5
IPB0
IPB6
18
17
16
15
14
13
12
11
10
9
8
PC8
PA5
PB17
PA13
PC4
PA11
PE17
PE30
PE15
PD6
PD4
PD7
PA3
PB19
PC7
PB16
PC13
PE21
PE24
PE14
PD5
PE28
PE27
PB31
PE23
PE22
PA6
MII1_COL
PC6
PB15
PE31
PD15
PD14
PD13
PD12
PA4
PA0
PD9
PA1
PB20
PB18
MII1_CRS
PC5
PD3
PE29
PE16
PE19 MII1_TXEN
PA2
PE25
PD10
PE26
PE20
PD8
PD11
IRQ7
IRQ1
D0
D12
D13
V
PB28
PA7
U
PC10
PB21
T
PA9
PC9
R
VDDL
VDDL
VDDL
VDDH
PE18
P
VDDH
VDDH
GND
GND
D8
N
VDDL
GND
IRQ0
D4
M
VDDL
VDDH
D17
D23
D27
D1
D9
D10
D11
D2
D3
D15
L
VDDH
GND
GND
VDDL
K
VDDL
GND
VDDH
D5
D14
J
VDDL
D22
D19
D16
D18
D28
D6
D20
D21
CLKOUT
D26
D24
D25
IPA2
D31
D7
D29
VSSSYN
IPA3
IPA6
D30
IPA7
IPA4
IPA5
H
VDDH
GND
G
VDDL
GND
VDDH
GND
VDDH
F
VDDH
VDDL
VDDL
E
VDDL
VDDL
D
MODCK1 EXTAL RSTCONF
C
TEXP
B
A
19
BADDR30 MODCK2 EXTCLK
7
6
XTAL
5
4
SRESET WAIT_A
3
2
1
Figure 77. Pinout of the PBGA Package
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
76
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39 contains a list of the MPC885 input and output signals and shows multiplexing and pin
assignments.
Table 39. Pin Assignments
Name
Pin Number
Type
A[0:31]
M16, N18, N19, M19, M17, M18, L16, L19, L17, L18, K19, K18, K17, Bidirectional
K16, J19, J17, J18, J16, E19, H18, H17, G19, F17, G17, H16, F19, Three-state
D19, H19, E18, G18, F18, D18
D[0:31]
P2, M1, L1, K2, N1, K4, H3, F2, P1, L4, L3, L2, N3, N2, K3, K1, J2, Bidirectional
M4, J1, J3, H2, H1, J4, M3, G2, G1, G3, M2, H4, F1, E1, F3
Three-state
TSIZ0, REG
G16
Bidirectional
Three-state
TSIZ1
E17
Bidirectional
Three-state
RD/WR
D13
Bidirectional
Three-state
BURST
C10
Bidirectional
Three-state
BDIP, GPL_B5
A13
Output
TS
A12
Bidirectional
Active pull-up
TA
C12
Bidirectional
Active pull-up
TEA
B12
Open-drain
BI
D12
Bidirectional
Active pull-up
IRQ2, RSV
B10
Bidirectional
Three-state
IRQ4, KR, RETRY,
SPKROUT
C7
Bidirectional
Three-state
CR, IRQ3
A11
Input
BR
D11
Bidirectional
BG
C11
Bidirectional
BB
B11
Bidirectional
Active pull-up
FRZ, IRQ6
D10
Bidirectional
IRQ0
N4
Input
IRQ1
P3
Input
IRQ7
P4
Input
CS[0:5]
B14, C14, A15, D14, C16, A16
Output
CS6, CE1_B
D15
Output
CS7, CE2_B
B16
Output
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
77
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
WE0, BS_B0, IORD
B18
Output
WE1, BS_B1, IOWR
E16
Output
WE2, BS_B2, PCOE
C17
Output
WE3, BS_B3, PCWE
B19
Output
BS_A[0:3]
D17, C18, C19, F16
Output
GPL_A0, GPL_B0
B17
Output
OE, GPL_A1, GPL_B1
A18
Output
GPL_A[2:3], GPL_B[2:3],
CS[2:3]
D16, A17
Output
UPWAITA, GPL_A4
B13
Bidirectional
UPWAITB, GPL_B4
A14
Bidirectional
GPL_A5
C13
Output
PORESET
B3
Input
RSTCONF
D4
Input
HRESET
B4
Open-drain
SRESET
A3
Open-drain
XTAL
A4
Analog output
EXTAL
D5
Analog input (3.3 V only)
CLKOUT
G4
Output
EXTCLK
A5
Input (3.3 V only)
TEXP
C4
Output
ALE_A
B7
Output
CE1_A
B15
Output
CE2_A
C15
Output
WAIT_A, SOC_Split1
A2
Input
WAIT_B
C3
Input
UTPB_Split01
B1
Input
IP_A1, UTPB_Split11
C1
Input
IP_A2, IOIS16_A,
UTPB_Split21
F4
Input
IP_A3, UTPB_Split31
E3
Input
IP_A4,
UTPB_Split41
D2
Input
IP_A5,
UTPB_Split51
D1
Input
IP_A6, UTPB_Split61
E2
Input
IP_A7, UTPB_Split71
D3
Input
IP_A0,
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
78
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
ALE_B, DSCK/AT1
D8
Bidirectional
Three-state
IP_B[0:1], IWP[0:1],
VFLS[0:1]
A9, D9
Bidirectional
IP_B2, IOIS16_B, AT2
C8
Bidirectional
Three-state
IP_B3, IWP2, VF2
C9
Bidirectional
IP_B4, LWP0, VF0
B9
Bidirectional
IP_B5, LWP1, VF1
A10
Bidirectional
IP_B6, DSDI, AT0
A8
Bidirectional
Three-state
IP_B7, PTR, AT3
B8
Bidirectional
Three-state
OP0, UtpClk_Split1
B6
Bidirectional
OP1
C6
Output
OP2, MODCK1, STS
D6
Bidirectional
OP3, MODCK2, DSDO
A6
Bidirectional
BADDR30, REG
A7
Output
BADDR[28:29]
C5, B5
Output
AS
D7
Input
PA15, USBRXD
N16
Bidirectional
PA14, USBOE
P17
Bidirectional
(Optional: open-drain)
PA13, RXD2
W11
Bidirectional
PA12, TXD2
P16
Bidirectional
(Optional: open-drain)
PA11, RXD4, MII1-TXD0,
RMII1-TXD0
W9
Bidirectional
(Optional: open-drain)
PA10, MII1-TXER, TIN4,
CLK7
W17
Bidirectional
(Optional: open-drain)
PA9, L1TXDA, RXD3
T15
Bidirectional
(Optional: open-drain)
PA8, L1RXDA, TXD3
W15
Bidirectional
(Optional: open-drain)
PA7, CLK1, L1RCLKA,
BRGO1, TIN1
V14
Bidirectional
PA6, CLK2, TOUT1
U13
Bidirectional
PA5, CLK3, L1TCLKA,
BRGO2, TIN2
W13
Bidirectional
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
79
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PA4, CTS4, MII1-TXD1,
RMII1-TXD1
U4
Bidirectional
PA3, MII1-RXER,
RMII1-RXER, BRGO3
W2
Bidirectional
PA2, MII1-RXDV,
RMII1-CRS_DV, TXD4
T4
Bidirectional
PA1, MII1-RXD0,
RMII1-RXD0, BRGO4
U1
Bidirectional
PA0, MII1-RXD1,
RMII1-RXD1, TOUT4
U3
Bidirectional
PB31, SPISEL,
MII1-TXCLK,
RMII1-REFCLK
V3
Bidirectional
(Optional: open-drain)
PB30, SPICLK
P18
Bidirectional
(Optional: open-drain)
PB29, SPIMOSI
T19
Bidirectional
(Optional: open-drain)
PB28, SPIMISO, BRGO4
V19
Bidirectional
(Optional: open-drain)
PB27, I2CSDA, BRGO1
U19
Bidirectional
(Optional: open-drain)
PB26, I2CSCL, BRGO2
R17
Bidirectional
(Optional: open-drain)
PB25, RXADDR31,
TXADDR3, SMTXD1
V17
Bidirectional
(Optional: open-drain)
PB24, TXADDR31,
RXADDR3, SMRXD1
U16
Bidirectional
(Optional: open-drain)
PB23, TXADDR21,
RXADDR2, SDACK1,
SMSYN1
W16
Bidirectional
(Optional: open-drain)
PB22, TXADDR41,
RXADDR4, SDACK2,
SMSYN2
V15
Bidirectional
(Optional: open-drain)
PB21, SMTXD2,
TXADDR11, BRG01,
RXADDR1, PHSEL[1]
U14
Bidirectional
(Optional: open-drain)
PB20, SMRXD2,
L1CLKOA, TXADDR01,
RXADDR0, PHSEL[0]
T13
Bidirectional
(Optional: open-drain)
PB19, MII1-RXD3, RTS4
V13
Bidirectional
(Optional: open-drain)
PB18, RXADDR41,
TXADDR4, RTS2, L1ST2
T12
Bidirectional
(Optional: open-drain)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
80
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PB17, L1ST3, BRGO2,
RXADDR11, TXADDR1,
PHREQ[1]
W12
Bidirectional
(Optional: open-drain)
PB16, L1RQa, L1ST4,
RTS4, RXADDR01,
TXADDR0, PHREQ[0]
V11
Bidirectional
(Optional: open-drain)
PB15, TXCLAV, BRG03,
RXCLAV
U10
Bidirectional
PB14RXADDR21,
TXADDR2
U18
Bidirectional
PC15, DREQ0, RTS3,
L1ST1, TXCLAV, RXCLAV
R19
Bidirectional
PC14, DREQ1, RTS2,
L1ST2
R18
Bidirectional
PC13, MII1-TXD3,
SDACK1
V10
Bidirectional
PC12, MII1-TXD2, TOUT1
T18
Bidirectional
PC11, USBRXP
V16
Bidirectional
PC10, USBRXN, TGATE1
U15
Bidirectional
PC9, CTS2
T14
Bidirectional
PC8, CD2, TGATE2
W14
Bidirectional
PC7, CTS4, L1TSYNCB,
USBTXP
V12
Bidirectional
PC6, CD4, L1RSYNCB,
USBTXN
U11
Bidirectional
PC5, CTS3, L1TSYNCA,
SDACK2
T10
Bidirectional
PC4, CD3, L1RSYNCA
W10
Bidirectional
PD15, L1TSYNCA, UTPB0 U8
Bidirectional
PD14, L1RSYNCA, UTPB1 U7
Bidirectional
PD13, L1TSYNCB, UTPB2 U6
Bidirectional
PD12, L1RSYNCB, UTPB3 U5
Bidirectional
PD11, RXD3, RXENB
R2
Bidirectional
PD10, TXD3, TXENB
T2
Bidirectional
PD9, TXD4, UTPCLK
U2
Bidirectional
PD8, RXD4, MII-MDC,
RMII-MDC
R3
Bidirectional
PD7, RTS3, UTPB4
W3
Bidirectional
PD6, RTS4, UTPB5
W5
Bidirectional
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
81
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PD5, CLK8, L1TCLKB,
UTPB6
V6
Bidirectional
PD4, CLK4, UTPB7
W4
Bidirectional
PD3, CLK7, TIN4, SOC
T9
Bidirectional
PE31, CLK8, L1TCLKB,
MII1-RXCLK
U9
Bidirectional
(Optional: open-drain)
PE30, L1RXDB,
MII1-RXD2
W7
Bidirectional
(Optional: open-drain)
PE29, MII2-CRS
T8
Bidirectional
(Optional: open-drain)
PE28, TOUT3, MII2-COL
V5
Bidirectional
(Optional: open-drain)
PE27, RTS3, L1RQB,
MII2-RXER, RMII2-RXER
V4
Bidirectional
(Optional: open-drain)
PE26, L1CLKOB,
MII2-RXDV,
RMII2-CRS_DV
T1
Bidirectional
(Optional: open-drain)
PE25, RXD4, MII2-RXD3,
L1ST2
T3
Bidirectional
(Optional: open-drain)
PE24, SMRXD1, BRGO1,
MII2-RXD2
V8
Bidirectional
(Optional: open-drain)
PE23, SMSYN2, TXD4,
MII2-RXCLK, L1ST1
V2
Bidirectional
(Optional: open-drain)
PE22, TOUT2, MII2-RXD1, V1
RMII2-RXD1, SDACK1
Bidirectional
(Optional: open-drain)
PE21, SMRXD2, TOUT1,
MII2-RXD0, RMII2-RXD0,
RTS3
V9
Bidirectional
(Optional: open-drain)
PE20, L1RSYNCA,
SMTXD2, CTS3,
MII2-TXER
R4
Bidirectional
(Optional: open-drain)
PE19, L1TXDB,
MII2-TXEN, RMII2-TXEN
T6
Bidirectional
(Optional: open-drain)
PE18, L1TSYNCA,
SMTXD1, MII2-TXD3
R1
Bidirectional
(Optional: open-drain)
PE17, TIN3, CLK5,
BRGO3, SMSYN1,
MII2-TXD2
W8
Bidirectional
(Optional: open-drain)
PE16, L1RCLKB, CLK6,
TXD3, MII2-TXCLK,
RMII2-REFCLK
T7
Bidirectional
(Optional: open-drain)
PE15, TGATE1,
MII2-TXD1, RMII2-TXD1
W6
Bidirectional
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
82
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PE14, RXD3, MII2-TXD0,
RMII2-TXD0
V7
Bidirectional
TMS
V18
Input
TDI, DSDI
T16
Input
TCK, DSCK
U17
Input
TRST
W18
Input
TDO, DSDO
T17
Output
MII1_CRS
T11
Input
MII_MDIO
P19
Bidirectional
MII1_TXEN, RMII1_TXEN
T5
Output
MII1_COL
U12
Input
VSSSYN1
C2
PLL analog VDD and GND
VSSSYN
E4
Power
VDDLSYN
B2
Power
GND
G6, G7, G8, G9, G10, G11, G12, G13, H7, H8, H9, H10, H11, H12, Power
H13, H14, J7, J8, J9, J10, J11, J12, J13, K7, K8, K9, K10, K11, K12,
K13, L7, L8, L9, L10, L11, L12, L13, M7, M8, M9, M10, M11, M12,
M13, N7, N8, N9, N10, N11, N12, N13, N14, P7, P13, R16
VDDL
E5, E6, E9, E11, E14, G15, H5, J5, J15, K15, L5, M15, N5, R6, R9, Power
R10, R12, R15
VDDH
E7, E8, E10, E12, E13, E15, F5, F6, F7, F8, F9, F10, F11, F12, F13, Power
F14, F15, G5, G14, H6, H15, J6, J14, K5, K6, K14, L6, L14, L15, M5,
M6, M14, N6, N15, P5, P6, P8, P9, P10, P11, P12, P14, P15, R5,
R7, R8, R11, R13, R14
N/C
N17
1
No connect
ESAR mode only.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
83
Mechanical Data and Ordering Information
16.2
Mechanical Dimensions of the PBGA Package
Figure 78 shows the mechanical dimensions of the PBGA package.
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 78. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
84
Freescale Semiconductor
Document Revision History
17 Document Revision History
Table 40 lists significant changes between revisions of this hardware specification.
Table 40. Document Revision History
Revision
Number
Date
7
07/2010
In Table 9, “Bus Operation Timings,” changed the following:
• Updated TRLX condition value for B22a/b/c to “TRLX = [0 or 1]”
• Removed TRLX condition for B23
• Updated condition and equation for B30 to “Invalid GPCM read/write access
(MIN = 0.25 × B1 – 2.00)”
• Updated note 8 to “The timing B30 refers to CS when ACS = 00 and to CS and WE(0:3) when
CSNT = 0.”
6
05/2010
Added minimum load for CLKOUT in Section 10, “Bus Signal Timing.”
5
03/2009
Updated formatting of Table 12 , “PCMCIA Port Timing,” Table 13, “Debug Port Timing,” Table 14,
“Reset Timing,” and Table 15, “JTAG Timing.”
4
08/2007
• On page 1, updated first paragraph and added a second paragraph.
• After Table 2, inserted a new figure showing the undershoot/overshoot voltage (Figure 3) and
renumbered the rest of the figures.
• In Table 9, for reset timings B29f and B29g added footnote indicating that the formula only applies
to bus operation up to 50 MHz.
• In Figure 6, changed all reference voltage measurement points from 0.2 and 0.8 V to 50% level.
• In Table 18, changed num 46 description to read, “TA assertion to rising edge ...”
• In Figure 49, changed TA to reflect the rising edge of the clock.
3.0
7/22/2004
•
•
•
•
2.0
12/2003
•
•
•
•
•
•
•
Changed the maximum operating frequency to 133 MHz.
Put in the orderable part numbers that are orderable.
Put the timing in the 80 MHz column.
Rounded the timings to hundredths in the 80 MHz column.
Put the pin numbers in footnotes by the maximum currents in Table 6.
Changed 22 and 41 in the Timing.
Put in the Thermal numbers.
1.0
9/2003
•
•
•
•
Added the DSP information in the Features list
Fixed table formatting.
Nontechnical edits.
Released to the external web.
0.9
8/2003
Changed the USB description to full-/low-speed compatible.
0.8
8/2003
Added the Reference to USB 2.0 to the Features list and removed 1.1 from USB on the block
diagrams.
0.7
7/2003
Added the RxClav and TxClav signals to PC15.
0.6
6/2003
Changed the pin descriptions per the June 22 spec.
0.5
5/2003
Changed some more typos, put in the phsel and phreq pins. Corrected the USB timing.
Changes
Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values
Added a footnote to Spec 41 specifying that EDM = 1
Added RMII1_EN under M1II_EN in Table 36 Pin Assignments
Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the
I2C Standard
• Put the new part numbers in the Ordering Information Section
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
85
Document Revision History
Table 40. Document Revision History (continued)
Revision
Number
Date
0.4
5/2003
Changed the pin descriptions for PD8 and PD9.
0.3
05/2003
Corrected the signals that had overlines on them.
0.2
05/2003
Made the changes to the RMII Timing, Made sure all the VDDL, VDDH, and GND show up on the
pinout diagram. Changed the SPI Master Timing Specs. 162 and 164.
0.1
04/2003
Added pinout and pinout assignments table. Added the USB timing to Section 14. Added the
Reduced MII to Section 15. Removed the Data Parity. Made some changes to the Features list.
0
02/2003
Initial revision.
Changes
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
86
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Document Number: MPC885EC
Rev. 7
07/2010
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