LD6935L/2828PX

  LD6935 series ') 1  Dual low-dropout regulators, high PSRR, 300 mA Rev. 1 — 29 May 2013 Preliminary data sheet 1. Product profile 1.1 General description The LD6935 series consists of small-size dual Low DropOut regulators (LDO). Each device delivers two times 300 mA with a typical voltage drop of 240 mV at 300 mA for each LDO. Each device offers two individual fixed nominal output voltages (VO(nom)) from 1.2 V to 3.6 V. The LDO has an integrated Soft start to control the inrush current during start-up. The output states when disabled can be high-ohmic 3-state or auto discharge. Optionally a delayed output circuit is available for the second output. The devices are available in DFN1612-8 (SOT1225) plastic package with a height of 0.4 mm. 1.2 Features and benefits          Extremely low standby current in shutdown mode ( 0.1 A) Low quiescent current Low output noise Fast turn-on time High Power Supply Rejection Ratio (PSRR) Auto discharge or high-ohmic mode for output states when disabled Delayed output circuit for second LDO (optional) DFN1612-8 (SOT1225) leadless package 1.6  1.2  0.4 mm Pb-free, Restriction of Hazardous Substances (RoHS) compliant, free of halogen and antimony (Dark Green compliant) 1.3 Applications  Smartphones  Mobile handsets  Digital still cameras  Tablet PCs  Mobile internet devices  Portable media players 1.4 Quick reference data  IO = 300 mA for each LDO  PSRR = 80 dB at 1 kHz  RMS noise Vn(o)RMS = 60 V at 10 Hz to 100 kHz  tstartup(reg) = 150 s  VI = 1.75 V to 5.5 V  VO = 1.2 V to 3.6 V (fixed value)  Dropout voltage Vdo = 240 mV at IO = 300 mA for each LDO  Quiescent current Iq = 2  35 A at IO = 0 mA LD6935 series NXP Semiconductors Dual low-dropout regulators, high PSRR, 300 mA 2. Pinning information 2.1 Pinning WHUPLQDO LQGH[DUHD *1'   (1 287   ,1 287   ,1 *1'   (1 DDD 7UDQVSDUHQWWRSYLHZ Fig 1. Pin configuration for DFN1612-8 (SOT1225) 2.2 Pin description Table 1. Pin description for DFN1612-8 (SOT1225) Symbol Pin Description GND 1 supply ground OUT1 2 regulator 1 output voltage OUT2 3 regulator 2 output voltage GND 4 supply ground EN2 5 regulator 2 enable input IN2 6 regulator 2 supply voltage input IN1 7 regulator 1 supply voltage input EN1 8 regulator 1 enable input i.c. TAB internal connected [1] [1] The TAB is GND level (it is placed on the reverse side of the IC). It is recommended to connect the TAB to GND. Leaving it unconnected is also allowed but it may result in lower thermal performance. 3. Ordering information Table 2. Ordering information Type number Package Name LD6935L LD6935_SER Preliminary data sheet Description Version DFN1612-8 plastic extremely thin small outline package; no leads; SOT1225 8 terminals; body 1.6  1.2  0.4 mm All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 May 2013 © NXP B.V. 2013. All rights reserved. 2 of 24 LD6935 series NXP Semiconductors Dual low-dropout regulators, high PSRR, 300 mA 3.1 Ordering options Further output voltage information available on request; see Section 19 “Contact information”. Table 3. Type number and nominal output voltage of high-ohmic output Type number Nominal output voltage VO(nom) OUT1 OUT2 LD6935L/2828H 2.8 V 2.8 V LD6935L/3318H 3.3 V 1.8 V Table 4. Type number and nominal output voltage of pull-down output Type number Nominal output voltage VO(nom) OUT1 OUT2 LD6935L/1828P 1.8 V 2.8 V LD6935L/2828P 2.8 V 2.8 V LD6935L/3318P 3.3 V 1.8 V LD6935L/3328P 3.3 V 2.8 V LD6935L/3333P 3.3 V 3.3 V Table 5. Type number and nominal output voltage of pull-down output with delay circuit Type number Nominal output voltage VO(nom) LD6935L/3118PD LD6935_SER Preliminary data sheet OUT1 OUT2 3.1 V 1.8 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 May 2013 © NXP B.V. 2013. All rights reserved. 3 of 24 LD6935 series NXP Semiconductors Dual low-dropout regulators, high PSRR, 300 mA 4. Block diagram ,1 287 62)767$57 9UHI *(1(5$725 7+(50$/ 3527(&7,21 '(/$