LH7A404

LH7A404 Preliminary data sheet FEATURES • 32-bit ARM9TDMI™ RISC Core – 16 kB Cache: 8 kB Instruction and 8 kB Data Cache – MMU (Windows CE™ Enabled) – Up to 266 MHz; See Table 1 for speed options • 80 kB On-Chip Static RAM • Vectored Interrupt Controller • External Bus Interface – Up to 133 MHz; See Table 1 for bus speed options – Asynchronous and Synchronous interface RAM, Flash, PC Card and CompactFlash • Clock and Power Management – 32.768 kHz and 14.7456 MHz Oscillators – Programmable PLL • Programmable LCD Controller – Up to 1,024 × 768 Resolution – Supports STN, Color STN, AD-TFT, HR-TFT, TFT – Up to 64 K-Colors and 15 Gray Shades • 9 Channel, 10-bit A/D Converter – Touch Screen Controller – Brownout Detector • DMA (12 Channels) – External DMA Channels – AC97 – MMC – USB • USB 2.0 Full Speed Host (two downstream ports) • USB 2.0 Full Speed Device • Synchronous Serial Port (SSP) – Motorola SPI™, Texas Instruments SSI, National Semiconductor MICROWIRE™ • On-board Boot ROM – Variety of Boot Modes: external ROM, NAND Flash, Serial EEPROM, or XMODEM • PS/2 Keyboard/Mouse Interface (KMI) 32-Bit System-on-Chip • Three Programmable Timers • Three UARTs, one with Classic IrDA (115 kbit/s) • Smart Card Interface (ISO7816) • Four Pulse Width Modulators (PWMs) • MultiMediaCard Interface with Secure Digital (MMC 2.11/SD 1.0) • AC97 Codec Interface • Smart Battery Monitor Interface • Real Time Clock (RTC) • Up to 64 General Purpose I/O Channels • Watchdog Timer • JTAG Debug Interface and Boundary Scan • Operating Voltage – 1.8 V (200 MHz), 2.1 V (266 MHz) Core – 3.3 V Input/Output (Except XTALIN is 1.8 V) • 5 V Tolerant Digital Inputs (excludes oscillator pins) – Oscillator pins T19, T20, Y18, Y19: 1.8 V ± 10 % • Operating Temperature: −40°C to +85°C • 324-Ball LFBGA Package DESCRIPTION The advent of 3G technology opens up a wide range of multimedia applications in mobile information appliances. The LH7A404 is designed from the ground up with a 32-bit ARM922 Core to provide high processing performance, low power consumption, and a high level of integration. Features include 80 kB on-chip SRAM, fully static design, power management unit, low voltage (1.8 V Core, 3.3 V I/O) and on-chip PLL. NOTE: Devices containing lead-free solder formulations have different reflow temperatures than leaded-solder formulations. When using both solder formulations on the same PC board, designers should consider the effect of different reflow temperatures on the overall PCB assembly process. (Refer to www.nxp.com for an application note on recommended soldering practices). Table 1. LH7A404 Versions PART NUMBER1 LH7A404-N0F-092-xx2 LH7A404-N0F-000-xx2 CORE CLOCK BUS CLOCK 266 MHz 200 MHz 133 MHz 100 MHz LOW POWER CURRENT BY MODE Run = 228 mA (Typ.); Halt = 60 mA (Typ.); Standby = 200 µA (Typ.) Run = 147 mA (Typ.); Halt = 41 mA (Typ.); Standby = 70 µA (Typ.) VERSION SOT1021-1 SOT1021-1 NOTES: 1. Where ‘xx’ is a two digit revision number, e.g. B2; refer to www.NXP.com for a list of all the active revisions 2. Lead-free part. Preliminary data sheet 1 LH7A404 NXP Semiconductors 32-Bit System-on-Chip 14.7456 MHz 32.768 kHz LH7A404 ARM 922T OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL REAL TIME CLOCK WATCHDOG TIMER BOOT ROM VECTORED INTERRUPT CONTROLLER TIMER (3) GENERAL PURPOSE I/O (64) SYNCHRONOUS SERIAL PORT BATTERY MONITOR INTERFACE UART (3) IrDA INTERFACE USB DEVICE INTERFACE MULTIMEDIACARD/ SECURE DIGITAL INTERFACE AC97 CODEC INTERFACE SMART CARD INTERFACE (ISO7816) ASYNCHRONOUS MEMORY CONTROLLER EXTERNAL BUS INTERFACE PCMCIA/CF CONTROLLER BOOT CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE SYNCHRONOUS MEMORY CONTROLLER LCD AHB BUS 80KB SRAM COLOR LCD CONTROLLER DMA CONTROLLER ADVANCED LCD INTERFACE (ALI) USB HOST INTERFACE ADVANCED HIGH-PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB) PWM (2) A/D TOUCH SCREEN CONTROLLER PS2 KEYBOARD/MOUSE INTERFACE DC to DC INTERFACE (2) LH7A404-1 Figure 1. LH7A404 Block Diagram 2 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 2. LH7A404 Functional Pin List LFBGA E10 E11 H10 H11 K5 K8 K13 K16 L5 L8 L13 L16 N10 N11 T10 T11 U18 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 T18 E7 E9 E14 G5 G16 P5 P16 T7 T12 T14 VDDC Core Power VSS I/O Ring Ground VDD I/O Ring Power SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE I/O NOTES Preliminary data sheet 3 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA E6 E15 F5 F16 J16 M5 R5 R16 T6 T15 Y17 W17 V16 U15 W16 V13 D2 E1 F3 F4 C1 C5 Y18 Y19 T19 T20 L2 T16 Y13 VDDA Analog Power for PLL1 and PLL2 VSSC Core Ground SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE I/O NOTES VSSA VDDAD VSSAD nPOR nURESET WAKEUP nPWRFL nEXTPWR nRESETOUT XTALIN XTALOUT XTAL32IN XTAL32OUT PGMCLK CLKEN WIDTH0 Analog Ground for PLL1 and PLL2 Analog Power for A/D, Touch Screen Controller Analog Ground for A/D, Touch Screen Controller Power on Reset User Reset Wake Up Power Fail Signal External Power Reset Output to external devices. This pin carries the same state as the internal SoC reset signal. 14.7456 MHz Crystal Oscillator pins. For an external clock source, XTALIN can be used while XTALOUT is left unconnected. XTALIN voltage is 1.8 V nominal. 32.768 kHz Real Time Clock, Crystal Oscillator pins. To drive the device from an external clock source, XTAL32IN can be used while XTAL32OUT is left unconnected. Programmable Clock (14.7456 MHz MAX.) External Oscillator Enable Output Boot Width Pins. Used with the MEDCHG and INTBOOT bits for internal Boot ROM. On power up, the values on these pins are latched to determine the width and type of Boot device. Boot width can be 8-, 16-, or 32-bit. The pins must be pulled HIGH with a 33 kΩ resistor. Media Change bit; used at power on with INTBOOT and WIDTHx pins to determine boot device. When LOW, boot device is selected according to the MEDCHG bit. When HIGH, the lower 64 kB addresses are mapped to the internal Boot ROM. LOW LOW LOW LOW 8 mA 8 mA O I/O Input Input Input Input Input LOW Input Input Input Input Input 12 mA I I I I I O 3 3 3 3 3 Input Input I 3 W13 WIDTH1 E4 MEDCHG Input No Change I 3 Y20 INTBOOT Input No Change I 4 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA N19 P20 N18 N20 M16 M18 L18 L17 L19 J19 K17 J18 H19 G20 G19 H17 F19 E20 E19 D20 E18 C20 D18 B20 C18 A20 B18 C16 B17 A18 A17 B15 P17 N16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A0 A1 Asynchronous Address Bus HIGH LOW 12 mA O Data Bus LOW LOW 12 mA I/O SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE I/O NOTES Preliminary data sheet 5 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA N17 M19 M20 L20 M17 K18 K20 K19 J20 H20 J17 H18 F20 G18 H16 F18 G17 F17 D19 E17 C19 D17 B19 A16 D15 B14 V18 R19 R18 P19 R20 R17 C12 D12 P18 C17 A19 D16 E16 B16 A14 B13 SIGNAL A2/SA0 A3/SA1 A4/SA2 A5/SA3 A6/SA4 A7/SA5 A8/SA6 A9/SA7 A10/SA8 A11/SA9 A12/SA10 A13/SA11 A14/SA12 A15/SA13 A16/SB0 A17/SB1 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 nCS0 nCS1 nCS2 nCS3 nCS6 nCS7 nOE nWE nWAIT nSCS0 nSCS1 nSCS2 nSCS3 nSWE SCKE0 SCKE1_2 Asynchronous Memory Chip Select 0 Asynchronous Memory Chip Select 1 Asynchronous Memory Chip Select 2 Asynchronous Memory Chip Select 3 Asynchronous Memory Chip Select 6 Asynchronous Memory Chip Select 7 Asynchronous Memory Output Enable Asynchronous Memory Write Enable Asynchronous Memory Wait; pull HIGH if unused Synchronous Memory Chip Select 0 Synchronous Memory Chip Select 1 Synchronous Memory Chip Select 2 Synchronous Memory Chip Select 3 Synchronous Memory Write Enable Clock Enable 0 for Synchronous Memory Clock Enable 1 OR 2 for Synchronous Memory HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Input HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH No Change No Change HIGH HIGH No Change HIGH HIGH HIGH HIGH HIGH No Change No Change 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA O O O O O O O O I I/O I/O I/O I/O O O O 4 4 5 Asynchronous Address Bus LOW LOW 12 mA O Asynchronous Address Bus Asynchronous Address Bus LOW LOW 12 mA O • Asynchronous Address Bus • Synchronous Device Bank Address 0 • Asynchronous Address Bus • Synchronous Device Bank Address 1 LOW LOW LOW LOW 12 mA 12 mA O O Asynchronous Address Bus and Synchronous Address Bus LOW LOW 12 mA O DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE I/O NOTES LOW LOW 12 mA O 4 6 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA C14 D14 A13 U9 Y7 C13 C15 A15 D13 E13 B12 A12 M2 L4 M3 M4 M1 N3 N2 N1 N4 P3 P2 P1 R3 N5 SIGNAL SCKE3 SCLK nBLE0 nBLE1 nBLE2 nBLE3 nCAS nRAS DQM0 DQM1 DQM2 DQM3 PA0/ LCDVD16 PA1/ LCDVD17 PA2 PA3 PA4 PA5 PA6 PA7 PB0/UARTRX1 PB1/UARTTX3 PB2/UARTRX3 PB3/UARTCTS3 PB4/UARTDCD3 PB5/UARTDSR3 • GPIO Port A7 • Boot Width Selection (See Table 6) • GPIO Port B0 • UART1 Receive Data Input • GPIO Port B1 • UART3 Transmit Data Out • GPIO Port B2 • UART3 Receive Data In • GPIO Port B3 • UART3 Clear to Send • GPIO Port B4 • UART3 Data Carrier Detect • GPIO Port B5 • UART3 Data Set Ready • GPIO Port B6 • Single Wire Data • Smart Battery Data • GPIO Port B7 • Smart Battery Clock • GPIO Port C0 • UART1 Transmit Data Output PA7: Input PB0: Input PB1: Input PB2: Input PB3: Input PB4: Input PB5: Input No Change No Change No Change No Change No Change No Change No Change 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA I/O I/O I/O I/O I/O I/O I/O 4 GPIO Port A[6:2] PAx: Input No Change 8 mA I/O • GPIO Port A0 • LCD Data pin 16 • GPIO Port A1 • LCD Data pin 17 PA0: Input PA1: Input No Change No Change 8 mA 8 mA I/O I/O Data Mask for Synchronous Memories HIGH No Change 12 mA O DESCRIPTION Clock Enable 3 for Synchronous Memory Synchronous Memory Clock Byte Lane Enable 0 Byte Lane Enable 1 Byte Lane Enable 2 Byte Lane Enable 3 Synchronous Memory Column Address Strobe Synchronous Memory Row Address Strobe RESET STATE Depends on MEDCHG LOW HIGH HIGH HIGH HIGH HIGH HIGH STANDBY STATE LOW No Change HIGH HIGH HIGH HIGH HIGH HIGH OUTPUT DRIVE I/O NOTES 12 mA 20 mA 12 mA 12 mA 12 mA 8 mA 12 mA 12 mA I/O I/O I/O O O O I/O I/O 2 R2 PB6/SWID/SMBD PB6: Input No Change 8 mA I/O R1 P4 T1 T2 T3 R4 U1 U2 PB7/SMBCLK PC0/UARTTX1 PC1 PC2 PC3 PC4 PC5 PC6 PB7: Input PC0: LOW No Change No Change 8 mA 12 mA I/O I/O GPIO Port C[5:1] PCx: LOW No Change 12 mA I/O GPIO Port C6 PC6: LOW No Change 12 mA I/O 4 Preliminary data sheet 7 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA V1 Y11 U10 W12 V11 W11 U11 V12 Y12 Y9 W10 V10 T9 D4 PC7 PD0/LCDVD8 PD1/LCDVD9 PD2/LCDVD10 PD3/LCDVD11 PD4/LCDVD12 PD5/LCDVD13 PD6/LCDVD14 PD7/LCDVD15 PE0/LCDVD4 PE1/LCDVD5 PE2/LCDVD6 PE3/LCDVD7 PE4/SCCLKIN • GPIO Port E4 • Smart Card Push-Pull Mode Clock Input • GPIO Port E5 • Smart Card Push-Pull Mode External Clock Buffer Enable • GPIO Port E6 • Smart Card Push-Pull Mode Data Input • GPIO Port E7 • Smart Card Push-Pull Mode Data Out External Buffer Enable • GPIO Port F0 • Interrupt 0 • GPIO Port F1 • Interrupt 1 • GPIO Port F2 • Interrupt 2 • GPIO Port F3 • Interrupt 3 • GPIO Port F4 • Interrupt 4 • GPIO Port F5 • Interrupt 5 • Smart Card Interface Card Detect Signal • GPIO Port F6 • Interrupt 6 • Ready for Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port F7 • Interrupt 7 • Ready for Card 2 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port G0 • Output Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port G1 • Write Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode PE4: Output • GPIO Port E[3:0] • LCD Video Data Interface PEx: Output LOW if 8-bit LCD enabled; else No Change No Change • GPIO Port D[7:0] • LCD Video Data Interface PDx: LOW LOW if 8-bit LCD enabled; else No Change SIGNAL GPIO Port C7 DESCRIPTION RESET STATE PC7: LOW STANDBY STATE No Change OUTPUT DRIVE I/O NOTES 12 mA I/O 12 mA I/O 12 mA I/O 12 mA I/O C3 PE5/SCCLKEN PE5: Output No Change 12 mA I/O B2 PE6/SCIN PE6: Output No Change 12 mA I/O A1 PE7/SCDATEN PE7: Output No Change 12 mA I/O A9 D9 A8 C8 B8 PF0/INT0 PF1/INT1 PF2/INT2 PF3/INT3 PF4/INT4 PF5/INT5/ SCDETECT PF0: Input PF1: Input PF2: Input PF3: Input PF4: Input No Change No Change No Change No Change No Change 8 mA 8 mA 8 mA 8 mA 8 mA I/O I/O I/O I/O I/O 3 3 3 3 3 D8 PF5: Input No Change 8 mA I/O 3 A7 PF6/INT6/ PCRDY1 PF6: Input No Change 8 mA I/O 3 E8 PF7/INT7/PCRDY2 PF7: Input No Change 8 mA I/O 3 Y2 PG0/nPCOE LOW No Change 8 mA I/O W4 PG1/nPCWE LOW No Change 8 mA I/O 8 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA SIGNAL DESCRIPTION • GPIO Port G2 • I/O Read Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port G3 • I/O Write Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port G4 • Register Memory Access for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port G5 • Card Enable 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal and nPCCE2 are used by the PC Card for decoding low and high byte accesses. • GPIO Port G6 • Card Enable 2 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal and nPCCE1 are used by the PC Card for decoding low and high byte accesses. • GPIO Port G7 • Direction for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port H0 • Reset Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port H1 • Address Bit 8 for PC Card (CompactFlash) in Single Card mode • Reset Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode • GPIO Port H2 • Enable Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal is used for gating other control signals to the appropriate PC Card. • GPIO Port H3 • Address Bit 9 for PC Card (CompactFlash) in Single Card mode • Address Bit 25 for PC Card (PCMCIA) in Single Card mode • Enable Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode. Used for gating other control signals to the appropriate PC Card. • GPIO Port H4 • WAIT Signal for Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port H5 • Address Bit 10 for PC Card (CompactFlash) in Single Card mode • Address Bit 24 for PC Card (PCMCIA) in Single Card mode • WAIT Signal for Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode • GPIO Port H6 • AC97 Reset RESET STATE LOW STANDBY STATE No Change OUTPUT DRIVE I/O NOTES 8 mA I/O Y3 PG2/nPCIOR U5 PG3/nPCIOW LOW No Change 8 mA I/O T5 PG4/nPCREG LOW No Change 8 mA I/O W5 PG5/nPCCE1 LOW No Change 8 mA I/O Y4 PG6/nPCCE2 LOW No Change 8 mA I/O W6 PG7/PCDIR LOW No Change 8 mA I/O V6 PH0/PCRESET1 PHx: Input No Change 8 mA I/O Y5 PH1/CFA8/ PCRESET2 PHx: Input No Change 8 mA I/O W7 PH2/nPCSLOTE1 PHx: Input No Change 8 mA I/O U6 PH3/CFA9/ PCMCIAA25/ nPCSLOTE2 PHx: Input No Change 8 mA I/O W8 PH4/nPCWAIT1 PHx: Input No Change 8 mA I/O Y6 PH5/CFA10/ PCMCIAA24/ nPCWAIT2 PHx: Input No Change 8 mA I/O V7 PH6/nAC97RESET PHx: Input No Change 8 mA I/O Preliminary data sheet 9 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA SIGNAL PH7/ nPCSTATRE LCDFP/LCDSPS LCDLP/ LCDHRLP LCDCLS LCDSPL LCDUBL LCDSPR LCDLBR LCDMOD LCDPS LCDVDDEN LCDREV LCDCLKIN LCDVD0 LCDVD1 LCDVD2 LCDVD3 LCDENAB/ LCDM LCDDCLK USBDCP USBDP USBDN USBHDP0 USBHDN0 USBHDP1 USBHDN1 • LCD TFT Data Enable • LCD STN AC Bias LCD Pixel Clock USB Device Full Speed Pull-up Resistor Control USB Device Data Positive (Differential Pair) USB Device Data Negative (Differential Pair) USB Data Host Positive 0 (Differential Pair) USB Data Host Negative 0 (Differential Pair) USB Data Host Positive 1 (Differential Pair) USB Data Host Negative 1 (Differential Pair) USB Host Power; This pin is connected to the remote USB Host Power Switch’s Enable pin. In response to a fault condition, signalled on the nUSBHOVRCURR pin, the LH7A404 can assert this pin, which causes the power switch shut down. USB Host Overcurrent; The overcurrent input is used to indicate to the host a fault has occurred, resulting in current limiting. The LH7A404 can be programmed to cause the remote power switch to shut off by asserting USBHPWR in response to an nUSBHOVRCURR assertion. DC-DC Converter 0 PWM 0 Enable DC-DC Converter 1 PWM 1 Enable DC-DC Converter 0 Output (Pulse Width Modulated) DC-DC Converter 1 Output (Pulse Width Modulated) PWM Output 2 PWM Output 3 PWM Synchronizing Input for PWM2 LOW LOW Input Input Input Input Input Input Input LOW LOW Input Input Input HIGH LOW Input Input 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA O O I I/O I/O I/O I/O I/O I/O LCD Video Data Interface LOW LOW 12 mA O DESCRIPTION • GPIO Port H7 • Status Read Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • LCD Frame Pulse • ALI Reset Row Driver Counter • LCD Linepulse • ALI Latch Pulse ALI Clock for Row Drivers ALI Start Pulse Left for reverse scanning ALI Up, Down signal for reverse scanning ALI Start Pulse Right for normal scanning ALI Output for reverse scanning ALI MOD Signal used by the row driver ALI Power Save ALI Power Sequence Control ALI Reverse External Clock Input for LCD controller RESET STATE PHx: Input STANDBY STATE No Change LOW if not in ALI mode LOW if not in ALI mode No Change No Change No Change No Change No Change No Change No Change No Change No Change No Change OUTPUT DRIVE I/O NOTES 8 mA I/O U7 T4 V2 U3 V3 U4 W1 V4 W2 V5 Y1 W3 U8 V8 T8 W9 Y8 V9 Y10 U17 U20 U19 W19 W20 V19 V20 LOW LOW LOW LOW LOW LOW HIGH LOW HIGH LOW HIGH Input 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA O O O O O O O O O O O I T17 USBHPWR LOW No Change 12 mA O V17 nUSBHOVRCURR Input Input 12 mA I D11 A10 C11 C10 B9 D10 C9 nPWME0 nPWME1 PWM0 PWM1 PWM2 PWM3 PWMSYNC Input Input LOW LOW LOW LOW Input Input Input Input Input No Change No Change No Change 8 mA 8 mA 8 mA 8 mA 8 mA I/O I/O I/O I/O O O 8 mA I 10 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA C7 B7 A6 B6 A5 D7 C6 B5 A4 B4 F2 F1 G2 G3 G1 H2 G4 K3 L1 L3 K4 J2 H4 H5 J1 J3 J4 J5 K2 E2 D1 U12 H1 H3 K1 Y16 SIGNAL ACBITCLK ACOUT ACSYNC ACIN MMCCLK MMCCMD MMCDATA0 MMCDATA1 MMCDATA2 MMCDATA3 UARTCTS2 UARTDCD2 UARTDSR2 UARTIRTX1 UARTIRRX1 UARTTX2 UARTRX2 SSPCLK SSPRX SSPTX SSPFRM COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 BATOK nBATCHG BATCNTL KMIDAT KMICLK TBUZ AN0/UL/X+ Battery OK Battery Change Battery Control for A/D controller battery monitor Keyboard/Mouse Data Keyboard/Mouse Clock Timer Buzzer Output (254 kHz MAX.) • ADC channel 0 • Touch Screen Controller Upper Left • Touch Screen Controller X-plus • ADC channel 1 • Touch Screen Controller Upper Right • Touch Screen Controller X-minus • ADC channel 2 • Touch Screen Controller Lower Left • Touch Screen Controller Y-plus Input Input LOW Input Input LOW Input Input Input No Change No Change No Change LOW Input 12 mA 12 mA 12 mA 8 mA I I O I/O I/O I/O I 3 3 Keyboard Interface HIGH HIGH 8 mA I/O DESCRIPTION • Audio Codec (AC97) Clock • Audio Codec (ACI) Clock • Audio Codec (AC97) Output • Audio Codec (ACI) Output • Audio Codec (AC97) Synchronization • Audio Codec (ACI) Synchronization • Audio Codec (AC97) Input • Audio Codec (ACI) Input MultiMediaCard Clock (20 MHz MAX.) MultiMediaCard Command MultiMediaCard Data 0 MultiMediaCard Data 1 MultiMediaCard Data 2 MultiMediaCard Data 3 UART2 Clear to Send Signal UART2 Data Carrier Detect Signal UART2 Data Set Ready Signal IrDA Transmit IrDA Receive UART2 Transmit Data Output UART2 Receive Data Input Synchronous Serial Port Clock Synchronous Serial Port Receive Synchronous Serial Port Transmit Synchronous Serial Port Frame Sync RESET STATE Input LOW LOW Input LOW Input Input Input Input Input Input Input Input LOW Input HIGH Input LOW Input Input HIGH STANDBY STATE No Change LOW LOW No Change LOW Input Input Input Input Input Input Input Input No Change Input No Change Input LOW Input Input HIGH OUTPUT DRIVE I/O NOTES 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA I/O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O O Y15 AN1/UR/X- Input Input I W14 AN2/LL/Y+ Input Input I Preliminary data sheet 11 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) LFBGA SIGNAL DESCRIPTION • ADC channel 3 • Touch Screen Controller Lower Right • Touch Screen Controller Y-minus • ADC channel 4 • Wiper input from 5-wire Touch Screen Connect pin to either VSS or VSSA ADC channel 6 ADC channel 7 ADC channel 8 ADC channel 9 Smart Card Interface I/O Smart Card Interface Clock Smart Card Interface Reset Smart Card Interface VCC Enable Counter Timer Clock Input DMA Request 0 DMA Acknowledge 0 DMA End of Transfer 0 DMA Request 1 DMA Acknowledge 1 DMA End of Transfer 1 Test Pin 0. Internal weak pull up to VDD. Status latched at nPOR going HIGH. Pull LOW for JTAG mode. Pull HIGH (or leave open) for Normal mode. See Table 3. Test Pin 1. Internal weak pull up to VDD. Status latched at nPOR going HIGH. Pull HIGH (or leave open) for both JTAG and Normal mode. See Table 3. JTAG Data In. Internal weak pull up to VDD. JTAG Clock. Internal weak pull up to VDD. JTAG Data Out JTAG Test Mode Select. Internal weak pull up to VDD. RESET STATE Input STANDBY STATE Input OUTPUT DRIVE I/O NOTES I U13 AN3/LR/Y- V14 U14 V15 W15 T13 Y14 E12 A11 B11 B10 D6 A3 D5 C4 B3 A2 E5 AN4/WIPER VSS or VSSA AN6 AN7 AN8 AN9 SCIO SCCLK nSCRESET SCVCCEN CTCLKIN DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 Input Input Input Input Input Input LOW LOW LOW LOW Input Input Input Input Input Input Input Input with pull-up Input with pull-up Input Input High Z Input Input Input Input Input Input Input LOW LOW LOW No Change No Change No Change No Change No Change No Change No Change No Change Input with pull-up Input with pull-up No Change No Change No Change No Change 4 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA I I I I I I I/O I/O O O I I I/O I/O I I/O I/O U16 nTEST0 I W18 D3 C2 B1 E3 nTEST1 TDI TCK TDO TMS I I I O I 3 NOTES: 1. Signals beginning with ‘n’ are Active LOW. 2. The SCLK pin can source up to 12 mA and sink up to 20 mA. See ‘DC Characteristics’. 3. Schmitt trigger input; see ’DC Specifications’, page 31 for triggers points and hysteresis. 4. These pins have alternate NAND Flash functions during boot-up when using the internal Boot ROM. Consult the Boot ROM Chapter of the User’s Guide for more information. 5. The nWAIT pin must be pulled HIGH with a 33 kΩ resistor to avoid the possibility of the SMC inadvertently going into WAIT. 6. The internal pullup and pulldown resistance on all digital I/O pins is 50KΩ. Table 3. nTEST Pin Function MODE JTAG Normal nTEST0 0 1 nTEST1 1 1 nURESET 1 x 12 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 4. LCD Controller Pins STN LFBGA PIN RESET STATE LCD SIGNAL MONO 4-BIT SINGLE PANEL DUAL PANEL MONO 8-BIT SINGLE PANEL DUAL PANEL COLOR SINGLE PANEL DUAL PANEL TFT AD-TFT/ HR-TFT L4 M2 Y12 V12 U11 W11 V11 W12 U10 Y11 T9 V10 W10 Y9 Y8 W9 T8 V8 U3 Y10 T4 V2 W2 V5 W3 V3 V4 W1 U4 Y1 U8 V9 PA1 PA0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE3 PE2 PE1 PE0 LCDVD3 LCDVD2 LCDVD1 LCDVD0 LCDCLS LCDDCLK LCDFP LCDLP LCDMOD LCDPS LCDREV LCDSPL LCDLBR LCDSPR LCDUBL LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 LCDCLS LCDDCLK LCDFP/ LCDSPS LCDLP/ LCDHRLP LCDMOD LCDPS LCDREV LCDSPL LCDLBR LCDSPR LCDUBL LCDDCLK LCDFP LCDLP LCDDCLK LCDFP LCDLP LCDDCLK LCDFP LCDLP LCDDCLK LCDFP LCDLP LCDDCLK LCDDCLK LCDFP LCDLP LCDFP LCDLP LCDDCLK LCDFP LCDLP MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN7 MLSTN6 MLSTN5 MLSTN4 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 CLSTN7 CLSTN6 CLSTN5 CLSTN4 CLSTN3 CLSTN2 CLSTN1 CLSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 Intensity BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 RED0 LOW LOW Intensity BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 RED0 LCDCLS LCDDCLK LCDSPS LCDHRLP LCDMOD LCDPS LCDREV LCDSPL LCDLBR LCDSPR LCDUBL LCDVDDEN LCDCLKIN LCDCLKIN LCDCLKIN LCDCLKIN LCDCLKIN LCDCLKIN LCDCLKIN LCDCLKIN LCDM LCDM LCDM LCDM LCDM LCDM LCDENAB LCDVDDEN LCDVDDEN LCDCLKIN LCDENAB LCDCLKIN LCDENAB/ LCDM NOTES: 1. The Intensity bit is identically generated for all three colors. 2. MUSTN = Monochrome Upper Panel MLSTN = Monochrome Lower Panel CUSTN = Color Upper Panel CLSTN = Color Lower Panel Preliminary data sheet 13 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 5. LFBGA Numerical Pin List LFBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 SIGNAL PE7/SCDATEN DACK1 DREQ0 MMCDATA2 MMCCLK ACSYNC PF6/INT6/PCRDY1 PF2/INT2 PF0/INT0 nPWME1 SCCLK DQM3 nBLE0 SCKE0 nRAS A25 D30 D29 nSCS1 D25 TDO PE6/SCIN DREQ1 MMCDATA3 MMCDATA1 ACIN ACOUT PF4/INT4 PWM2 SCVCCEN nSCRESET DQM2 SCKE1_2 A27 D31 nSWE D28 D26 A24 D23 nEXTPWR TCK PE5/SCCLKEN DEOT0 nRESETOUT 95 mV/ns 95 mV/ns 12 mA 12 mA 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 100 mV/ns 95 mV/ns 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 12 mA 12 mA 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 4 mA 12 mA SLEW RATE 95 mV/ns 95 mV/ns OUTPUT DRIVE 12 mA 12 mA Table 5. LFBGA Numerical Pin List (Cont’d) LFBGA C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 SIGNAL MMCDATA ACBITCLK PF3/INT3 PWMSYNC PWM1 PWM0 nOE nBLE3 SCKE3 nCAS D27 nSCS0 D24 A22 D21 nBATCHG nPOR TDI PE4/SCCLKIN DACK0 CTCLKIN MMCCMD PF5/INT5/SCDETECT PF1/INT1 PWM3 nPWME0 nWE DQM0 SCLK A26 nSCS2 A23 D22 A20 D19 nURESET BATOK TMS MEDCHG DEOT1 VSSC VDDC PF7/INT7/PCRDY2 VDDC VDD 110 mV/ns 8 mA 95 mV/ns 12 mA 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 190 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 8 mA 8 mA 8 mA 8 mA 8 mA 12 mA 12 mA 20 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 95 mV/ns 95 mV/ns 12 mA 12 mA 110 mV/ns 110 mV/ns 95 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 8 mA 8 mA 12 mA 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA SLEW RATE 110 mV/ns 110 mV/ns 110 mV/ns OUTPUT DRIVE 8 mA 8 mA 8 mA 14 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 5. LFBGA Numerical Pin List (Cont’d) LFBGA E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G16 G17 G18 G19 G20 H1 H2 H3 H4 H5 H10 H11 H16 H17 H18 H19 H20 J1 J2 J3 VDD SCIO DQM1 VDDC VSSC nSCS3 A21 D20 D18 D17 UARTDCD2 UARTCTS2 WAKEUP nPWRFL VSSC VSSC A19 A17/SBANK1 D16 A14/SA12 UARTIRRX1 UARTDSR2 UARTIRTX1 UARTRX2 VDDC VDDC A18 A15/SA13 D14 D13 KMIDAT UARTTX2 KMICLK COL1 COL2 VDD VDD A16/SBANK0 D15 A13/SA11 D12 A11/SA9 COL3 COL0 COL4 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 100 mV/ns 100 mV/ns 100 mV/ns 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 95 mV/ns 100 mV/ns 100 mV/ns 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA 12 mA 8 mA 8 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 8 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 95 mV/ns 95 mV/ns 12 mA 12 mA SIGNAL SLEW RATE OUTPUT DRIVE Table 5. LFBGA Numerical Pin List (Cont’d) LFBGA J4 J5 J9 J10 J11 J12 J16 J17 J18 J19 J20 K1 K2 K3 K4 K5 K8 K9 K10 K11 K12 K13 K16 K17 K18 K19 K20 L1 L2 L3 L4 L5 L8 L9 L10 L11 L12 L13 L16 L17 L18 L19 L20 M1 M2 COL5 COL6 VSS VSS VSS VSS VSSC A12/SA10 D11 D9 A10/SA8 TBUZ COL7 SSPCLK SSPFRM VDD VDD VSS VSS VSS VSS VDD VDD D10 A7/SA5 A9/SA7 A8/SA6 SSPRX PGMCLK SSPTX PA1/LCDVD17 VDD VDD VSS VSS VSS VSS VDD VDD D7 D6 D8 A5/SA3 PA4 PA0/LCDVD16 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 8 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 100 mV/ns 110 mV/ns 110 mV/ns 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 8 mA SIGNAL SLEW RATE 100 mV/ns 100 mV/ns OUTPUT DRIVE 8 mA 8 mA Preliminary data sheet 15 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 5. LFBGA Numerical Pin List (Cont’d) LFBGA M3 M4 M5 M9 M10 M11 M12 M16 M17 M18 M19 M20 N1 N2 N3 N4 N5 N10 N11 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P16 P17 P18 P19 P20 R1 R2 R3 R4 R5 R16 R17 R18 R19 R20 T1 PA2 PA3 VSSC VSS VSS VSS VSS D4 A6/SA4 D5 A3/SA1 A4/SA2 PA7 PA6 PA5 PB0/UARTRX1 PB5/UARTDSR3 VDD VDD A1 A2/SA0 D2 D0 D3 PB3/UARTCTS3 PB2/UARTRX3 PB1/UARTTX3 PC0/UARTTX1 VDDC VDDC A0 nWAIT nCS3 D1 PB7/SMBCLK PB6/SWID/SMBD PB4/UARTDCD3 PC4 VSSC VSSC nCS7 nCS2 nCS1 nCS6 PC1 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 12 mA 12 mA 12 mA 12 mA 12 mA 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 95 mV/ns 12 mA 12 mA 8 mA 8 mA 8 mA 12 mA 95 mV/ns 12 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 95 mV/ns 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 12 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 8 mA 8 mA SIGNAL SLEW RATE 110 mV/ns 110 mV/ns OUTPUT DRIVE 8 mA 8 mA Table 5. LFBGA Numerical Pin List (Cont’d) LFBGA T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 PC2 PC3 LCDFP/LCDSPS PG4/nPCREG VSSC VDDC LCDVD1 PE3/LCDVD7 VDD VDD VDDC AN8 VDDC VSSC CLKEN USBHPWR VSS XTAL32IN XTAL32OUT PC5 PC6 LCDCLS LCDUBL PG3/nPCIOW PH3/CFA9/PCMCIAA25/ nPCSLOTE2 PH7/nPCSTATRE LCDCLKIN nBLE1 PD1/LCDVD9 PD5/LCDVD13 BATCTL AN3/LR/YVSS or VSSA VSSA nTEST0 USBDCP VDD USBDN USBDP PC7 LCDLP/LCDHRLP LCDSPL LCDLBR LCDPS 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 12 mA 12 mA 12 mA 12 mA 12 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 12 mA 12 mA 12 mA 12 mA 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 12 mA 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 110 mV/ns 95 mV/ns 8 mA 12 mA 95 mV/ns 95 mV/ns 12 mA 12 mA SIGNAL SLEW RATE 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns OUTPUT DRIVE 12 mA 12 mA 12 mA 8 mA 16 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 5. LFBGA Numerical Pin List (Cont’d) LFBGA V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 SIGNAL PH0/PCRESET1 PH6/nAC97RESET LCDVD0 LCDENAB/LCDM PE2/LCDVD6 PD3/LCDVD11 PD6/LCDVD14 VSSAD AN4/WIPER AN6 VSSA nUSBHOVRCURR nCS0 USBHDP1 USBHDN1 LCDSPR LCDMOD LCDREV PG1/nPCWE PG5/nPCCE1 PG7/PCDIR PH2/nPCSLOTE1 PH4/nPCWAIT1 LCDVD2 PE1/LCDVD5 PD4/LCDVD12 PD2/LCDVD10 95 mV/ns 95 mV/ns 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 12 mA 12 mA 12 mA 8 mA 8 mA 8 mA 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA 95 mV/ns 12 mA SLEW RATE 110 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns OUTPUT DRIVE 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA Table 5. LFBGA Numerical Pin List (Cont’d) LFBGA W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 WIDTH1 AN2/LL/Y+ AN7 VDDAD VDDA nTEST1 USBHDP0 USBHDN0 LCDVDDEN PG0/nPCOE PG2/nPCIOR PG6/nPCCE2 PH1/CFA8/PCRESET2 PH5/CFA10/PCMCIAA24/ nPCWAIT2 nBLE2 LCDVD3 PE0/LCDVD4 LCDDCLK PD0/LCDVD8 PD7/LCDVD15 WIDTH0 AN9 AN1/UR/XAN0/UL/X+ VDDA XTALIN XTALOUT INTBOOT 95 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 110 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 95 mV/ns 12 mA 8 mA 8 mA 8 mA 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA SIGNAL SLEW RATE OUTPUT DRIVE Preliminary data sheet 17 LH7A404 NXP Semiconductors 32-Bit System-on-Chip ROM FLASH 1 4 7 2 5 8 0 3 6 9 # * SMART CARD STN/TFT/ AD-TFT SSP UART SCI MULTIMEDIA CARD SRAM GPIO SDRAM TOUCH SCREEN CONTR. MMC/SD LH7A404 COMPACT FLASH DMA CODEC AC97 PC CARD PCMCIA IR DEVICE HOST USB HOST BATTERY BMI DC to DC VOLTAGE GENERATION CIRCUITRY LH7A404-2 Figure 2. Application Diagram SYSTEM DESCRIPTIONS ARM922T Processor The LH7A404 microcontroller features the ARM922T cached core with an Advanced High-performance Bus (AHB) interface. The processor is a member of the ARM9T family of processors. For more information, see the ARM document, ‘ARM922T Technical Reference Manual’, available on ARM’s website at www.arm.com. The 32.768 kHz clock provides the source for the Real Time Clock tree and power-down logic. This clock is used for the power state control and is the only clock in the LH7A404 that runs continuously. The 32.768 kHz clock is divided down to 1 Hz for the Real Time Clock counter using a ripple divider to save power. The 14.7456 MHz source is used to generate the main system clocks for the LH7A404. It is the source for PLL1 and PLL2, the primary clock for the peripherals, and the source clock to the programmable clock (PGM) divider. PLL1 provides the main clock tree for the chip. It generates the following clocks: FCLK, HCLK, and PCLK. FCLK is the clock that drives the ARM922T core. HCLK is the main bus (AHB) clock, as such it clocks all memory interfaces, bus arbitrators and the AHB peripherals. HCLK is generated by dividing FCLK by 1, 2, 3, or 4. HCLK can be gated by the system to enable low power operation. PCLK is the peripheral bus (APB) clock. It is generated by dividing HCLK by either 2, 4, or 8. PLL2 generates a fixed 48 MHz clock signal for the USB peripheral. Clock and State Controller The clocking scheme in the LH7A404 is based around two primary oscillator inputs. These are the 14.7456 MHz input crystal and the 32.768 kHz real time clock oscillator; see Figure 3. The 14.7456 MHz oscillator supplies the main system clock domains for the LH7A404. The 32.768 kHz oscillator controls the power-down operations and real time clock peripheral. The clock and state controller provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and rest of the system. The amount of clock gating that actually takes place depends on the power saving mode selected. 18 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Power Modes The LH7A404 has three operational states: Run, Halt, and Standby. During Run all clocks are hardware enabled and the processor is clocked. In the Halt mode the device is functioning, but the processor clock is halted while it waits for an event such as a key press. Standby equates to the computer being switched ‘off’, i.e. no display (LCD disabled) and the main oscillator is shut down. Data Paths The data paths in the LH7A404 are: • The AMBA AHB bus • The AMBA APB bus • The External Bus Interface • The LCD AHB bus • The DMA busses. AMBA AHB BUS The Advanced Microprocessor Bus Architecture AHB (AMBA AHB) is a high speed 32-bit-wide data bus. The AMBA AHB is for high-performance, high-clock-frequency system modules. LH7A404 peripherals and memory with high bandwidth requirements are connected to the ARM922T processor and other bus masters using a multi-master AHB bus. These peripherals include the external memory interfaces, on-chip SRAM, LCD Controller (bus master), DMA Controller (bus master), and USB Host (bus master). Remaining peripherals reside on the lower bandwidth Advanced Peripheral Bus (APB), which is accessed from the AHB via the APB Bridge. The APB Bridge is the only master on the APB, and its operation is transparent to the user as it converts AHB accesses into slower APB accesses automatically. Reset Modes Three external signals can generate resets to the LH7A404: nPOR (power on reset), nPWRFL (power failure) and nURESET (user reset). If any of these are active, a system reset is internally generated. An nPOR reset performs a full system reset. The nPWRFL and nURESET resets perform a full system reset except for the SDRAM refresh control, SDRAM Global Configuration, SDRAM Device Configuration, and the RTC peripheral registers. The SDRAM controller issues a self-refresh command to external SDRAM before the system enters an nPWRFL and nURESET reset. This allows the system to maintain its Real Time Clock and SDRAM contents. Upon release of Reset, the chip enters Standby mode. Once in the Run mode the PWRSR register can be interrogated to determine the nature of the reset and the trigger source, after which software can then take appropriate actions. PLL1 14.7456 MHz ƒIN DIVIDE BY PREDIV+2 VCO MUST BE BETWEEN 80 and 400 MHz GATE DIVIDE BY 2PS GCLK HCLKDIV GATE FCLK HCLK_CPU HCLK 500 kHz MIN. 32.768 kHz RTC OSC MAIN DIVIDER 1: MAIN DIVIDER 2: DIVIDE BY MAINDIV1+2 DIVIDE BY MAINDIV2+2 RTC 32.768 kHz PCLKDIV PCLK LH7A404-6 Figure 3. Clock and State Controller Block Diagram Preliminary data sheet 19 LH7A404 NXP Semiconductors 32-Bit System-on-Chip AMBA APB BUS The AMBA APB provides a lower-bandwidth bus for peripherals accessed less frequently. This reduces the loading on the AHB, allowing it to run faster to maximize system performance, while the APB can operate at a lower clock rate to conserve power. The APB Bridge is the only master on the APB. All AHB masters can access APB peripherals via the ABP Bridge. The APB clock frequency can be selected by software to divide the clock speed of the AHB bus by 2, 4, or 8. EXTERNAL BUS INTERFACE (EBI) The External Bus Interface (EBI) provides a 32-bitwide, high speed gateway to external memory devices. The supported memory devices include: • Asynchronous RAM/ROM/Flash • Synchronous DRAM/Flash • PCMCIA interfaces • CompactFlash interfaces. The EBI can be controlled by either the Asynchronous Memory Controller or Synchronous Memory Controller. There is an arbiter on the EBI input, with priority given to the Synchronous Memory Controller interface. LCD BUS The LCD controller has its own local memory bus that connects it to the system’s embedded memory and external SDRAM. The function of this local data bus is to allow the LCD controller to perform its video refresh function without congesting the main AHB bus. This leads to better system performance and lower power consumption. There is an arbiter on both the embedded memory and the synchronous memory controller. In both cases the LCD bus is given priority. DMA BUSES The LH7A404 has a DMA system that connects the higher speed/higher data volume APB peripherals (MMC, USB Device and AC97) to the AHB bus. This enables the efficient transfer of data between these peripherals and external memory without the intervention of the ARM922T core. USB HOST CONTROLLER DMA BUS The USB Host Controller has its own DMA controller. It acts as another bus master on the AHB bus. It does not interact with the non-USB DMA controller except in bus arbitration. Memory Map The LH7A404 system has a 32-bit-wide address bus, allowing addressing up to 4GB of memory. This memory space is subdivided into a number of memory banks, shown in Figure 4. Four of these banks (each 256MB) are allocated to the Synchronous Memory Controller. Eight banks (each 256MB) are allocated to the Asynchronous Memory Controller. Two of these eight banks are designed for PCMCIA systems. Part of the remaining memory space is allocated to the embedded SRAM, and to the control registers of the AHB and APB. The rest of the memory space is not used. The LH7A404 can boot from both internal and external devices. The selection is determined by the value of five pins at power-on reset as shown in Table 6. If booting is from an external device (with INTBOOT = 0), refer to Table 7. When booting from external synchronous memory, bank 4 (nSCS3) is mapped into memory location zero. When booting from external asynchronous memory, memory bank 0 (nSCS0) is mapped into memory location zero. Figure 4 shows the memory map of the LH7A404 system for the two boot modes. Once the LH7A404 has booted, the boot code can configure the ARM922T MMU to remap the low memory space to a location in RAM. This allows the user to set the interrupt vector table. 20 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 6. Internal Boot Modes BOOT DEVICE External device 8-bit interface, 3-byte address NAND Flash 8-bit interface, 4-byte address NAND Flash 8-bit interface, 5-byte address NAND Flash 16-bit interface, 3-byte address NAND Flash 16-bit interface, 4-byte address NAND Flash 16-bit interface, 5-byte address NAND Flash XMODEM using UART2 I C EEPROM 2 GPIO PA7 LATCHED MEDCHG LATCHED WIDTH1 See Table 7 LATCHED WIDTH0 LATCHED INTBOOT 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 x 0 1 0 0 1 0 0 1 1 1 1 x 1 1 1 1 1 1 1 1 1 1 1 1 Undefined Table 7. External Boot Modes BOOT MODE 8-bit ROM 16-bit ROM 32-bit ROM Invalid: Do not allow this condition. 16-bit SynchFlash (Initializes device MODE Register) 16-bit SROM (Initializes device MODE Register) 32-bit SynchFlash (Initializes device MODE Register) 32-bit SROM (Initializes device MODE Register) Boot from internal Boot ROM; see Table 6 MEDCHG 0 0 0 0 1 1 1 1 x WIDTH1 0 0 1 1 0 0 1 1 x WIDTH0 0 1 0 1 0 1 0 1 x INTBOOT 0 0 0 0 0 0 0 0 1 Preliminary data sheet 21 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Vectored Interrupt Controller (VIC) The LH7A404 has two VICs working together to manage interrupt requests from on-chip and off-chip sources. Each VIC performs these primary functions: • Determine if an interrupt source is disabled or can generate an FIQ or IRQ to the ARM core • Prioritize up to 16 separate interrupt sources for simultaneous and nested processing • Obtain the address of the interrupt handler (vector) for up to 16 interrupt sources • Provide a default vector and a set of status registers for up to 16 non-vectored sources. Software determines the priority of these interrupts. Two VICs are daisy-chained together to support up to 64 different interrupts, 32 of which are vectored. The VIC supports both FIQ and IRQ interrupts. FIQ interrupts have a higher priority than IRQ interrupts. If two interrupts with the same priority become active at the same time, the priority must be resolved in software. When an interrupt becomes active, the VIC generates an FIQ or IRQ if the corresponding mask bit is set. Interrupts are not latched in the VIC, but may latch on a particular peripheral when applicable. After a power-on reset, all mask register bits are cleared, masking all interrupts. They must be set by software after power-on reset to enable interrupts. A vectored interrupt has improved latency as it provides direct information about where its service routine is located and eliminates software arbitration needed with a simple interrupt controller. The VICs continue to operate in Halt and Standby modes, so external interrupts may bring the chip out of these low power modes. External Bus Interface The ARM922T, LCD controller, and DMA engine have access to an external memory system. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in Synchronous Memory for large displays. The processor and DMA engine share the main system bus, providing access to all external memory devices and the embedded SRAM frame buffer. An arbitration unit ensures that control over the External Bus Interface (EBI) is only granted when an existing access has been completed. See Figure 4. INTERNAL TO THE LH7A404 EXTERNAL TO THE LH7A404 ARM922T DMA CONTROLLER ASYNCHRONOUS MEMORY CONTROLLER (SMC) SDRAM SRAM SYSTEM AHB BUS SDRAM LCD CONTROLLER EMBEDDED SRAM 80KB USB HOST SYNCHRONOUS MEMORY CONTROLLER (SDMC) ROM LCD MMU/DMA LCD AHB BUS LH7A404-8 Figure 4. External Bus Interface Block Diagram 22 ARBITER DATA EXTERNAL BUS ADDRESS/ INTERFACE CONTROL (EBI) Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Embedded SRAM T he LH7A404 incorporates 80 kB of embedded SRAM. This embedded memory is used for storing code, data, or LCD frame data and is contiguous with external SDRAM. The 80 kB is large enough to store a QVGA frame (320 × 240) at 8 bits per pixel, equivalent to 70 kB of information. Locating the frame buffer on chip reduces the overall power consumed by LH7A404 applications. Normally, the system performs external accesses to acquire this data. The LCD controller automatically uses an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any 4 kB page boundary in SDRAM, allowing software to set the MMU (in the LCD controller) page tables so the two memory areas appear contiguous, allowing byte, half-word, and word accesses. SDRAM (Synchronous) Memory Controller The SDRAM (Synchronous) Memory Controller provides a high speed memory interface to a wide variety of synchronous memory devices, including Synchronous DRAM, Synchronous Flash and Synchronous ROMs. The key features of the controller are: • LCD DMA port for high bandwidth • Up to four Synchronous Memory banks can be independently set up • Includes special configuration bits for Synchronous ROM operation • Includes ability to program Synchronous Flash devices using write and erase commands • On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset • Data is transferred between the controller and the Synchronous DRAM in four-word bursts. Longer transfers within the same page are concatenated, forming a seamless burst • Programmable for 16- or 32-bit data bus size • Two reset domains enable Synchronous DRAM contents to be preserved over a ‘soft’ reset • Power saving Synchronous Memory SCKE and external clock modes provided. Static Memory Controller (SMC) The asynchronous Static Memory Controller (SMC) provides an interface between the AMBA AHB system bus and external (off-chip) memory devices. The SMC simultaneously supports up to eight independently configurable memory banks. Each memory bank can support: • SRAM • ROM • Flash EPROM • Burst ROM memory. Each memory bank may use devices with either 8-, 16-, or 32-bit external memory data paths. The memory controller is configured to support little-endian operation only. The memory banks can be configured to support: • Non-burst read and write accesses only to highspeed CMOS static RAM • Non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. The SMC has six main functions: • • • • • • Memory bank select Access sequencing Wait state generation Byte lane write control External bus interface CompactFlash or PCMCIA interfacing. Secure Digital/MultiMediaCard (MMC) The SD Memory Card is a flash-based memory card that meets the security, capacity, performance, and environment requirements inherent in electronic devices. The SD Memory Card host supports MultiMediaCard (MMC) operation as well, and is compatible with MMC Cards. The SD/MMC controller can be used as an MMC card controller or as an SD Card controller, and supports the full SD/MMC bus protocol as defined in the MMC system specification 2.11 provided by the MMC Association and the ‘SD Memory Card Spec v1.0’ from the SD Association. Preliminary data sheet 23 LH7A404 NXP Semiconductors 32-Bit System-on-Chip SD/MMC INTERFACE DESCRIPTION The SD/MMC controller uses the three-wire signal bus (clock, command, and data) to input and output data to and from the MMC, and to configure and acquire status information from the card. The SD controller differs in that it has four data lines instead of one. The SD/MMC bus lines can be divided into three groups: • Power supply: VSS1, VSS2, and VDD • Data transfer group: MMCCMD, MMCDATA0, MMCDATA1, MMCDATA2, MMCDATA3 (for MMC, do not use MMCDATA1, MMCDATA2, MMCDATA3) • Clock: MMCCLK MMC CONTROLLER The MMC controller implements MMC-specific functions, serves as the bus master for the MMC Bus and implements the standard interface to the MMC (card initialization, CRC generation and validation, command/response transactions, etc.). PROGRAMMABLE PARAMETERS • Smart Card clock frequency • Communication baud rate • Protocol convention • Card activation/deactivation time • Maximum time for first character of Answer to Reset (ATR) reception checking • Maximum ATR character stream duration checking • Maximum time of receipt of first character of data stream checking • Maximum time allowed between characters checking • Character guard time • Block guard time • • Transmit/receive character retry. Direct Memory Access Controller (DMA) The DMA Controller can be used to interface streams from 20 internal peripherals to the system memory using 10 fully-independent programmable channels which consist of five M2P (transmit) channels and five P2M (receive) channels. The following peripherals may be allocated to the 10 channels: • USB Device • USB Host • SD/MMC • AC97 • UART1 • UART2 • UART3 Each of the above peripherals contain one Tx and one Rx channel, except the AC97, which contains three Tx and Rx channels. These peripherals also have their own bi-directional DMA bus, capable of simultaneously transferring data in both directions. All memory transfers take place via the main system AHB bus. The DMA Controller can also be used to interface streams from memory-to-memory (M2M) or memoryto-external peripheral (M2P) using two dedicated M2M channels. External handshake signals are available to support memory-to-/from-external peripheral (M2P/P2M) transfers. A software trigger is available for M2M transfers only. Smart Card Interface (SCI) The SCI (ISO7816) connects to an external Smart Card reader. The SCI can autonomously control data transfer to and from the Smart Card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES • Supports asynchronous T0 and T1 transmission protocols • Supports clock rate conversion factor F = 372, with bit rate adjustment factors of D = 1, 2, or 4 • Eight-character-deep buffered Tx and Rx paths • Direct interrupts for Tx and Rx FIFO level monitoring • Interrupt status register • Hardware-initiated card deactivation sequence on detection of card removal • Software-initiated card deactivation sequence on transaction complete • Limited support for synchronous smart cards via registered input/output. 24 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 The DMA Controller features: • Two dedicated channels for M2M and external M2P/P2M • Ten fully independent, programmable DMA controller internal M2P/P2M channels (5 Tx and 5 Rx) • Channels assignable to one of a number of different peripherals • Independent source and destination address registers. Source and destination can be programmed to auto-increment or not auto-increment for M2M channels • Two buffer descriptors per M2P and M2M channel to avoid potential data under/over-flow due to software introduced latency. A buffer refers to the area in system memory that is characterized by a buffer descriptor, i.e., a start address and the length of the buffer in bytes • No AMBA wrapping bursts for DMA channels; only incrementing bursts are supported • Buffer size independent of the peripheral’s packet size for the internal M2P channels. Transfers can automatically switch between buffers • Maskable interrupt generation • Internal arbitration between DMA channels, plus support for an AHB bus arbiter • DMA data transfer sizes, byte, word and quad-word data transfers are supported using a 16-byte data. Maximum data transfer size per M2M channel is programmable • Per-channel clock gating reducing power in channels that have not been enabled by software. See the ‘Clock and State Controller’ section. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. System interrupts are generated when any/all of the DMA channels wish to inform the processor to update the buffer descriptor. The DMA controller can service 10 out of 20 possible peripherals using the ten DMA channels, each with its own peripheral DMA bus capable of simultaneously transferring data in both directions. The SD/MMC, UART[3:1], USB Device, and USB Host peripherals can each use two DMA channels, one for transmit and one for receive. The AC97 peripheral can use six DMA channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overhead. The DMA controller includes an M2M transfer feature allowing block moves of data from one memory address space to another with minimum of program effort and time. An M2M software trigger capability is provided. The DMA controller can also fill a block of memory with data from a single location. The DMA controller’s M2M channels can also be used in M2P/P2M mode. A set of external handshake signals, DREQ, DACK and TC/DEOT are provided for each of two M2M channels. DREQ (input) can be programmed edge or level active, and active HIGH or LOW. The peripheral may hold DREQ active for the duration of the block transfers or may assert/deassert on each transfer. DACK (output) can be programmed active HIGH or LOW. DACK will assert and return to de-asserted with each Read or Write, the timing coinciding with nOE or nWE from the EBI. TC/DEOT is a bidirectional signal with programmable direction and active polarity. When configured as an Output, the DMA will assert Terminal Count (TC) on the final transfer to coincide with the DACK, typically when the byte count has expired. When configured as an Input, the peripheral must assert DEOT concurrent with DREQ for the final transfer in the block. Transfer is terminated when DEOT is asserted by the external peripheral or when the byte count expires, whichever occurs first. Status bits indicate if the actual byte count is equal to the programmed limit, and if the count was terminated by peripheral asserting DEOT. Terminating the transfer causes a DMA interrupt on that channel and rollover to the ‘other’ buffer if so configured. USB Device The features of the USB are: • Compliant with USB 2.0 Full Speed specification • Provides a high-level interface that removes the USB protocol details from firmware • Compatible with both OpenHCI and Intel UHCI standards • Supports full-speed (12 Mbit/s) functions • Supports Suspend and Resume signalling. USB Host Controller The features of the USB Host Controller are: • Open Host Controller Interface Specification (OpenHCI) Rev. 1.0 Compliant • Universal Serial Bus Specification 2.0 Full Speed compatible • Supports Low Speed and High Speed USB devices • Root Hub has two Downstream Ports • DMA functionality. Preliminary data sheet 25 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Color LCD Controller The LH7A404’s LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A404’s LCD Controller saves an external timing ASIC by incorporating the timing conversion logic for thin LCD modules such as AD-TFT and HR-TFT. The Color LCD Controller features support for: • Up to 1,024 × 768 Resolution • 16-bit Video Bus • 16 bits-per-pixel (bpp) 5:5:5:1 or 5:6:5 direct color or on-chip color palette for 1, 2, 4, and 8 bpp resolution • STN, Color STN, AD-TFT, HR-TFT, TFT panels – Single and Dual Scan STN panels – Up to 15 Gray Shades (mono STN) – Up to 3375 colors (color STN) – Up to 64 k-Colors – An on-chip SRAM frame buffer conserves bus bandwidth and saves active power. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACBITCLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchronization output signal that is coincident with the bit clock. Pulse Width Modulator (PWM) The Pulse Width Modulator features: • Configurable dual output • Separate input clocks for each PWM output • 16-bit resolution • Programmable synchronous mode support allows external input to start PWM • Programmable pulse width (duty cycle), interval (frequency), and polarity – Static programming: when the PWM is stopped – Dynamic programming: when the PWM is running – Updates duty cycle, frequency, and polarity at end of a PWM cycle The PWM is a configurable dual-output, dual-clockinput AMBA slave module, and connects to the APB. AC97 Codec Controller The AC97 Codec controller includes a 5-pin serial interface to an external audio codec. The AC97 link is a bi-directional, fixed rate, serial Pulse Code Modulated (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit resolution per sample. The AC97 controller contains logic that controls the AC97 link to the audio codec and an interface to the AMBA APB. • • • • Its main features include: Serial-to-parallel conversion for data received from the external codec Parallel-to-serial conversion for data transmitted to the external codec Reception/transmission of control and status information via the AMBA APB interface Support for up to 4 simultaneous codec sampling rates with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored independently in both transmit and receive modes. Three of the outgoing FIFOs can be written via either the APB interface or with DMA channels 1-3. Synchronous Serial Port (SSP) The SSP is a master-only interface for synchronous serial communication with peripheral devices that have either Motorola SPI, National Semiconductor MICROWIRE, or Texas Instruments Synchronous Serial Interfaces. The SSP performs serial-to-parallel conversion on data received from a peripheral. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A404 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usually be determined by peripheral device’s capability. Audio Codec Interface (ACI) The ACI provides: • A digital serial interface to an off-chip 8-bit codec • All the necessary clocks and timing pulses to perform serialization or de-serialization of the data stream to, or from the codec device. 26 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 UART/IrDA The LH7A404 contains three UARTs; UART1, UART2, and UART3. The UART performs: • Serial-to-Parallel conversion on data received from the peripheral device • Parallel-to-Serial conversion on data transmitted to the peripheral device. The transmit and receive paths can both be routed through the DMA separately or simultaneously, and are buffered with internal FIFO memories. This allows up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: • Four individually maskable interrupts from the receive, transmit, and modem status logic blocks • A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity or break error occurs during reception, the appropriate error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is prevented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. FREE-RUNNING MODE In free-running mode, the timer wraps around to 0xFFFF when it underflows and continues counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a programmable frequency to drive the buzzer or generate a periodic interrupt. Real Time Clock (RTC) The RTC provides a basic alarm function or long time-base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in onesecond intervals is achieved by use of a 1 Hz clock input to the RTC. Keyboard and Mouse Interface (KMI) The Keyboard and Mouse Interface has the following features: • IBM PS/2 or AT-compatible keyboard or mouse interface • Half-duplex, bidirectional synchronous serial interface using open-drain outputs for clock and data. • Programmable 4-bit reference clock divider • Polled or interrupt-driven mode • Separately maskable transmit and receive interrupts • Single combined interrupt output • Odd parity generation and checking • Register bits for override of keyboard clock and data lines. Additional test registers and modes are implemented for functional verification and manufacturing test. Timers The LH7A404 includes three programmable timers. Each of the timers can operate in two modes: free running and pre-scale. The timers are programmed using four registers; Load, Value, Control, and Clear. Two identical timers, Timer 1 (TC1) and Timer 2 (TC2), use clock sources of either 508 kHz or 2 kHz. The clock source and mode are selectable by writing to the appropriate bits in the system control register. Each timer has a 16-bit read/write data register and a control register. The timer is immediately loaded with the value written to the data register. This value is then decremented on the next active clock edge to arrive after the write. When the timer underflows, it immediately asserts its appropriate interrupt. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. Once the timer has been enabled and written to, it decrements on the next rising edge of the 7.3728 MHz clock after the data register has been updated. A/D Converter with Brownout Detector and Touch Screen Controller The LH7A404 includes an A/D Converter (ADC) with integrated Touch Screen Controller (TSC) and brownout detector. The TSC is a complete interface to a Touch Screen for portable personal devices. It combines the front-end biasing and control circuitry with A/D conversion, reference generation, and digital interface functions to completely replace external ICs used to implement this interface. The ADC features: • A 10-bit A/D converter with integrated sample-andhold, fully differential, high impedance signal and reference inputs • Active matrix for bias and control circuits necessary for connection to external 4-, 5-, 7-, and 8-wire touch panels, including pen pressure implementation Preliminary data sheet 27 LH7A404 NXP Semiconductors 32-Bit System-on-Chip • Battery voltage sense in addition to normal direct voltage inputs • A 9-channel multiplexer for routing user-selected inputs to A/D • A 16 × 16 FIFO for 10-bit digital output of A/D • A pen-down sensor to generate interrupts to the host • Low-power circuitry and power control modes to minimize on-chip power dissipation • Conversion automation for flexibility while minimizing CPU management and interrupt overhead • A brownout detector with separate interrupt DC-to-DC Converter The features of the DC-DC Converter interface are: • Dual-drive PWM outputs with independent closed loop feedback • Software programmable configuration of one of 8 output frequencies (each being a fixed division of the input clock). • Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. • Hardware-configured output polarity (for positive or negative voltage generation) during power-on reset via the polarity select inputs • Dynamically switched PWM outputs to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. Battery Monitor Interface (BMI) The BMI is a serial communication interface specified for two types of battery monitors/gas gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, implementing the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface has priority. SINGLE WIRE INTERFACE The Single Wire Interface performs: • Serial-to-parallel conversion on data received from the peripheral device • Parallel-to-serial conversion on data transmitted to the peripheral device • Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol in which the host initiates a data transfer by sending a WriteData/Command word to the battery monitor. SMART BATTERY INTERFACE The Smart Battery Interface performs: • Serial-to-parallel conversion on data received from the peripheral device • Parallel-to-serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multimaster bus (the SMBus), allowing multiple bus masters to be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data provided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism by relying on the wired-AND connection of all SMBus interfaces to the SMBus. Watchdog Timer (WDT) The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause an FIQ interrupt. Failure to service the FIQ interrupt generates a system reset. Features of the WDT: • Timing derived from the system clock • 16 programmable time-out periods: 216 through 231 clock cycles • Generates a system reset (resets LH7A404) or a FIQ interrupt whenever a time-out period is reached • Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes • Protection mechanism guards against interruptservice-failure: – The first WDT time-out triggers FIQ and asserts nWDFIQ status flag – If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a system reset. General Purpose I/O (GPIO) The GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE[2:1], and the GPIOFEOI registers control edge-triggered Interrupts on Port F. The PINMUX register controls which signals are from Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and Port H. 28 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 ELECTRICAL SPECIFICATIONS IMPORTANT: The LH7A404 is an electrostatic discharge (ESD) sensitive device. ESD protection circuitry internal to the LH7A404 has been added to reduce ESD susceptibility. Appropriate ESD precautions are still required during handling to prevent degradation or failure due to high electrostatic discharges. System design practices should be evaluated to prevent LH7A404 ESD voltages from exceeding the maximum rated voltage as specified in this data sheet. Absolute maximum ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) DC Analog Supply Voltage (VDDAD) MINIMUM MAXIMUM −0.3 V −0.3 V −0.3 V −0.3 V −0.5 V 2.4 V 4.6 V 2.4 V 4.6 V 5.5 V 2 kV 1 kV −55°C 125°C 5 V Tolerant Digital Input Pin Voltage ESD, Human Body Model (Analog pins AN0 - AN9 rated at 500 V) ESD, Charged Device Model Storage Temperature NOTE: These stress ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended operating conditions for LH7A404-N0E-000-xx/LH7A404-N0F-000-xx PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) DC A/D and TSC Supply Voltage (VDDAD) Clock Frequency Bus Clock Frequency External Clock Input (XTALIN) External Clock Input (XTALIN) Voltage Operating Temperature 14 MHz 1.71 V −40°C 14.7456 MHz 1.8 V 25°C MINIMUM 1.71 V 3.0 V 1.71 V 3.0 V 10 MHz TYPICAL 1.8 V 3.3 V 1.8 V 3.3 V MAXIMUM NOTES 1.89 V 3.6 V 1.89 V 3.6 V 200 MHz 100 MHz 20 MHz 1.89 V +85°C 2 1 NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See “Power Supply Sequencing” on page 31. 2. Many of the peripherals do not operate properly at clock speeds other than 14.7456 MHz. Some (such as USB) function only at 14.7456 MHz. Preliminary data sheet 29 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Recommended Operating Conditions for LH7A404-N0E-092-xx/LH7A404-N0F-092-xx PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) DC A/D and TSC Supply Voltage (VDDAD) Clock Frequency Bus Clock Frequency External Clock Input (XTALIN) External Clock Input (XTALIN) Voltage Operating Temperature 14 MHz 1.71 V −40°C 14.7456 MHz 1.8 V 25°C MINIMUM 2.0 V 3.14 V 2.0 V 3.0 V 10 MHz TYPICAL 2.1 V 3.3 V 2.1 V 3.3 V MAXIMUM NOTES 2.2 V 3.6 V 2.2 V 3.6 V 266 MHz 133 MHz 20 MHz 1.89 V +85°C 2 1 NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See “Power Supply Sequencing” on page 31. 2. Many blocks do not operate properly at speeds other than 14.7456 MHz. Some (such as USB) function only at 14.7456 MHz. Table 8. Clock Frequency vs. Voltages (VDD) vs. Temperature* PARAMETER 25°C 70°C 85°C Clock Frequency (FCLK) Clock Period (1/FCLK) Clock Frequency (FCLK) Clock Period (1/FCLK) Clock Frequency (FCLK) Clock Period (1/FCLK) 1.71 V 213 MHz 4.69 ns 205 MHz 4.88 ns 200 MHz 5.00 ns 1.80 V 227 MHz 4.41 ns 220 MHz 4.46 ns 212 MHz 4.72 ns 1.89 V 253 MHz 3.95 ns 236 MHz 2.36 ns 232 MHz 4.24 ns NOTE: *LH7A404-N0E-000-xx and LH7A404-N0F-000-xx only. Table 8 is representative of a typical device. Guaranteed values are in the Recommended Operating Conditions table. 255 250 245 240 FREQUENCY (MHz) 235 1.89 V (+5%) 230 225 220 215 210 205 200 25 35 45 55 TEMP (°C) LH7A404-182 1.80 V 65 75 1.71 V (-5%) 85 Figure 5. Temperature/Voltage/Speed Chart (LH7A404-N0E-000-xx and LH7A404-N0F-000-xx Only) 30 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Power Supply Sequencing NXP recommends that the 1.8 V power supply be energized before the 3.3 V supply. If this is not possible, the 1.8 V supply may not lag the 3.3 V supply by more than 100 µs. If longer delay time is needed, it is recommended that the voltage difference between the two power supplies be within 1.5 V during power supply ramp up. To avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered-on as described above. DC/AC SPECIFICATIONS The DC and AC specifications appears in the table below. Parameters apply to all part numbers except where noted. DC Specifications SYMBOL VIH VIL VHST PARAMETER CMOS/Schmitt Trigger Input HIGH Voltage CMOS/Schmitt Trigger Input LOW Voltage Schmitt Trigger Hysteresis CMOS Output HIGH Voltage, Output Drive 1 VOH Output Drive 2 Output Drive 3 Output Drive 4 and 5 CMOS Output LOW Voltage, Output Drive 1 Output Drive 2 VOL Output Drive 3 Output Drive 4 Output Drive 5 IIN IOZ ISTARTUP CIN COUT IACTIVE IHALT ISTANDBY IACTIVE IHALT IHALT Input Leakage Current Input Leakage Current, with pullup resistors Output Tri-state Leakage Current Startup Current Input Capacitance Output Capacitance Active Current (Operating Current) Halt Current Standby Current Active Current (Operating Current) Halt Current Standby Current 147 41 70 228 60 200 370 -10 -95 -10 0.25 2.6 2.6 2.6 2.6 0.4 0.4 0.4 0.4 0.4 10 10 10 50 4 4 238 45 MIN. 2.0 0.8 TYP. MAX. UNIT V V V V V V V V V V V V µA µA µA µA pF pF mA mA µA mA mA µA 3 4 5 3 4 5 VIL to VIH IOH = -2 mA IOH = -4 mA IOH = -8 mA IOH = -12 mA IOL = 2 mA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 20 mA VIN = VDD or GND VOUT = VDD or GND 2 1 1 CONDITIONS NOTE LH7A404-N0E-000-XX AND LH7A404-N0F-000-XX ONLY LH7A404-N0E-092-XX AND LH7A404-N0F-092-XX ONLY NOTES: 1. Output Drive 5 can sink 20 mA of current, but sources 12 mA of current. 2. Current consumption until oscillators are stabilized. 3. See ’Current Consumption by Operating Mode’, page 34 for operating conditions. 4. Both oscillators running, LCD Active; all other peripherals stopped. 5. 32 kHz oscillator running; all other peripherals stopped. Preliminary data sheet 31 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Analog-To-Digital Converter Electrical Characteristics Table 9 shows the derated specifications for extended temperature operation. See Figure 6 for the ADC transfer characteristics. Table 9. ADC Electrical Characteristics PARAMETER A/D Resolution Throughput Conversion Acquisition Time Data Format Clk Frequency Differential Non-Linearity (DNL) Integral Non-Linearity (INL) Offset Error Gain Error Reference Voltage Output VREFVREF+ Crosstalk between channels Analog Input Voltage Range Analog Input Current Reference Input Current Analog Input capacitance Operating Supply Voltage Operating Current, VDDAD Standby Current, VDDAD Stop Current, VDDAD Brownout Trip Point (falling point) Brownout Hysteresis Operating Temperature −40 2.36 3.0 590 180 1 2.63 120 85 2.9 0 500 -0.99 -4.5 +35 -4.0 1.85 VSSA (VREF-) +1.0 2.0 VSSA VREF -60 VDDAD 5 5 15 3.6 1000 MIN. 10 17 3 binary 5,000 +4.5 +4.5 +50 4.0 2.15 (VREF+) -1.0 VDDAD ns LSB LSB mV LSB V V V dB V µA µA pF V µA µA µA V mV °C 8 7 6 6 3 4 5 TYP. MAX. 10 UNITS Bits CLK Cycles CLK Cycles 2 1 NOTES NOTES: 1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion, plus 1 × A2DCLK cycles to be made available in the PCLK domain. An additional 3 × PCLK cycles are required before being available on the APB. 2. Data out = 0000000000 when the analog input equals the negative reference. Data out = 1111111111 when the analog input equals the positive reference. 3. Guaranteed monotonic. 4. INL calculated as deviation from ‘best fit’ line after subtracting offset/gain errors over the center 90 % of full scale output range. 5. DC voltage error for the transition voltage from code 511 (0x1FF) to 512 (0x200) 6. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer, alternative low impedance (RS < 500) voltages can be selected as reference voltages. The range of voltages allowed are specified above. 7. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC. 8. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down. 32 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 OFFSET GAIN ERROR ERROR 1024 1023 1022 1021 1020 1019 1018 IDEAL TRANSFER CURVE 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 CENTER OF A STEP OF THE ACTUAL TRANSFER CURVE ACTUAL TRANSFER CURVE INTEGRAL NON-LINEARITY OFFSET ERROR LSB DNL LH7A404-154 Figure 6. ADC Transfer Characteristics AC Test Conditions PARAMETER DC I/O Supply Voltage (VDD) DC Core Supply Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels RATING 3.0 to 3.6 1.7 to 1.9 VSS to 3 2 VDD/2 UNIT V V V ns V Preliminary data sheet 33 LH7A404 NXP Semiconductors 32-Bit System-on-Chip CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make these data more usable, the values presented in Table 11 were derived under the conditions described here. Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: • All IP blocks either operating or enabled at maximum frequency and size configuration • Core operating at maximum power configuration • All voltages at maximum specified values • Nominal specified ambient temperature. Typical The values in the TYPICAL column were determined using a ‘typical’ application under ‘typical’ environmental conditions and the following operating characteristics: • LINUX operating system running from SDRAM • UART and AC97 peripherals operating; all other peripherals as needed by the OS • LCD enabled with 320 × 240 × 16-bit color, 60 Hz refresh rate, data in SDRAM • I/O loads at nominal • Cache enabled • FCLK = 200; HCLK = 100; PCLK = 50 MHz • All voltages at typical values • Nominal case temperature. PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 10 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the peripheral clock running at 200 MHz, typical conditions, and no I/O loads. This current is supplied by the 1.8 V power supply. Table 10. Peripheral Current Consumption PERIPHERAL AC97 UART (each) RTC Timers (each) LCD (+I/O) MMC SCI PWM (each) BMI-SWI BMI-SBus SDRAM (+I/O) USB Device (+PLL) ACI VIC KMI USB Host ADC/TSC TYPICAL 1.3 1.0 0.005 0.1 5.4 (+1.0) 0.6 23 45 1.0 1.0 1.5 (+14.8) 5.6 (+3.3) 0.8 610 38 715 590 UNITS mA mA mA mA mA mA mA µA mA mA mA mA mA µA µA µA µA Table 11. Current Consumption by Mode SYMBOL PARAMETER FCLK = 200 MHz (TYP.) FCLK = 266 MHz (TYP.) UNITS RUN MODE ICORE IIO ICORE IIO ICORE IIO Core Current I/O Current Core Current I/O Current Core Current I/O Current 132 15 HALT MODE (All Peripherals Disabled) 40 1 66 4 58 2 200 4 mA mA µA µA 199 29 mA mA STANDBY MODE (Typical Conditions Only) NOTES: 1. FCLK = 200 MHZ pertains to LH7A404-N0E-000-xx and LH7A404-N0F-000-xx 2. FCLK = 266 MHz pertains to LH7A404-N0E-092-xx and LH7A404-N0F-092-xx. 34 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 AC Specifications All signals described in Table 12 relate to transitions following an internal reference clock signal. The illustration in Figure 7 represents all cases of these sets of measurement parameters. The reference clock signals in this design are: • HCLK, internal System Bus clock (‘C’ in timing data) • PCLK, the Peripheral Bus clock • SSPCLK, the Synchronous Serial Port clock • UARTCLK, the UART Interface clock • LCDDCLK, the LCD Data clock from the LCD Controller • ACBITCLK, the AC97 and ACI clock • SCLK, the Synchronous Memory clock. All signal transitions are measured from the 50 % point of the clock to the 50 % point of the signal. For outputs from the LH7A404, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX are shown in Table 12. The signal tOHXXX (e.g. tOHA) represents the amount of time the output must be held valid after the rising edge of the reference clock signal. Minimum requirements for tOHXXX are listed in Table 12. For inputs, tISXXX (e.g. tISD) represents the amount of setup time the input signal must be valid after a valid address bus, or rising edge of the peripheral clock. Maximum requirements for tISXXX are shown in Table 12. The signal tIHXXX (e.g. tIHD) represents the amount of time the output must be held valid following the rising edge of the reference clock signal. Minimum requirements are shown in Table 12. REFERENCE CLOCK tOVXXX tOHXXX OUTPUT SIGNAL (O) tISXXX tIHXXX INPUT SIGNAL (I) LH7A404-9 Figure 7. LH7A404 Signal Timing Preliminary data sheet 35 LH7A404 NXP Semiconductors 32-Bit System-on-Chip Table 12. AC Signal Characteristics SIGNAL TYPE Output A[27:0] Output — LOAD 50 pF 50 pF — SYMBOL tRC tWC tWS tDVWE Output 50 pF tDHWE tDVBE tDHBE D[31:0] Input — tDSCS tDHCS tDSOE tDHOE tDSBE tDHBE tCS nCS[7:0] Output 50 pF tAVCS tAHCS tWE nWE Output 50 pF tAVWE tCSHWE tOE nOE Output 50 pF tAVOE tAHOE tBEW nBLE (Write) Output 50 pF tAVBE tCSHBE tBER nBLE (Read) Output 50 pF tAVBE tAHBE tOVA tOHA tOVB tOHD tOVD tISD tIHD tOVCA tOHCA tOVRA tOHRA tOVSDW tOHSDW tOVC0 tOVDQ tOVSC tOHSC tOVDREG tOHDREG MIN. MAX. DESCRIPTION NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states × HCLK period]) 4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Read Cycle Time 4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Write Cycle Time tHCLK ns tHCLK – 6.0 ns tHCLK – 7.0 ns tHCLK – 5.0 ns tHCLK – 7.0 ns 15 ns 0 ns 15 ns 0 ns 15 ns 0 ns tHCLK – 4.0 ns tHCLK tHCLK – 2.0 ns tHCLK – 4.0 ns tHCLK – 1.0 ns tHCLK – 4.0 ns tHCLK tHCLK – 5.0 ns tHCLK – 2.0 ns tHCLK tHCLK – 2.0 ns tHCLK — 1.5/1.5 ns — 1.5ns 2 ns 1.5/2.5 ns 1.0/1.5 ns 2 ns 1.5/2 ns 2 ns 1.5/2 ns 2 ns 1.5/2 ns 2 ns 2 ns 2 ns 1.5/2 ns — 4 × tHCLK – 5 ns tHCLK ns tHCLK – 2.0 ns tHCLK + 2.0 ns tHCLK – 1.0 ns tHCLK + 3.0 ns — — — — — — tHCLK tHCLK + 4.5 ns tHCLK + 1.0 ns tHCLK ns tHCLK + 2.0 ns tHCLK tHCLK + 4.5 ns tHCLK tHCLK tHCLK + 3.0 ns tHCLK tHCLK + 4.5 ns 5.5/7.5 ns — 5.5/7.5 ns — 5.5/7.5 ns — — 5.5/7.5 ns — 5.5/7.5 ns — 5.5/7.5 ns — 5.5/7.5 ns 5.5/7.5 ns 5.5/7.5 ns — tHCLK + 5 ns — Wait State Width Data Valid to Write Edge (nWE invalid) Data Hold after Write Edge (nWE invalid) Data Valid to nBLE Invalid Data Hold after nBLE Invalid Data Setup to nCSx Invalid Data Hold to nCSx Invalid Data Setup to nOE Invalid Data Hold to nOE Invalid Data Setup to nBLE Invalid Data Hold to nBLE Invalid Address Valid to nCSx Valid Address Hold after nCSx Invalid nWE Width Address Valid to nWE Valid nCSx Hold after nWE Invalid Address Valid to nOE Valid Address Hold after nOE Invalid nBLE Width Address Valid to nBLE Valid nCSx Hold after nBLE Invalid Address Valid to nBLE Valid Address Hold after nBLE Invalid Address Valid Address Hold Bank Select Valid Data Hold Data Valid Data Setup Data Hold CAS Valid CAS Hold RAS Valid RAS Hold Write Enable Valid Write Enable Hold Clock Enable Valid Data Mask Valid Synchronous Chip Select Valid Synchronous Chip Select Hold nREG Valid nREG Hold 2 × tHCLK – 3.0 ns 2 × tHCLK + 3.0 ns nCSx Width 2 × tHCLK – 3.0 ns 2 × tHCLK + 3.0 ns nOE Width 2 × tHCLK – 5.0 ns 2 × tHCLK + 3.0 ns nBLE Width SYNCHRONOUS MEMORY INTERFACE SIGNALS (‘-092’ parts/’-000’ parts) SA[13:0] A[17:16]/ SB[1:0] Output Output Output D[31:0] Input nCAS nRAS nSWE SCKE[1:0] DQM[3:0] nSCS[3:0] Output Output Output Output Output Output — 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF PCMCIA INTERFACE SIGNALS (+ [wait states × HCLK period]) nPCREG Output 50 pF 36 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Table 12. AC Signal Characteristics (Cont’d) SIGNAL TYPE Output D[31:0] Input nPCCE1 nPCCE2 nPCOE nPCWE PCDIR Output Output Output Output Output — 50 pF 50 pF 50 pF 50 pF 50 pF LOAD 50 pF SYMBOL tOVD tOHD tISD tIHD tOVCE1 tOHCE1 tOVCE2 tOHCE2 tOVOE tOHOE tOVWE tOHWE tOVPCD tOHPCD tOVCMD tOHCMD tOVDAT tOHDAT tISDAT tIHDAT tISCMD tIHCMD tOVAC97 tOHAC97 tISAC97 tIHAC97 tOVAC97 tOHAC97 tOVFRM tOHFRM tOVTX tOHTX tISRX tIHRX tCLK tOVD tOHD tIS tIH 50 pF tOV 5 ns 14 ns 14 ns 8.819 ms — 10 ns 10 ns 2.5 ns — MIN. — 4 × tHCLK – 6 ns — 4 × tHCLK – 5 ns — 4 × tHCLK – 5 ns — 4 × tHCLK – 5 ns — 3 × tHCLK – 5 ns — 3 × tHCLK – 5 ns — 4 × tHCLK – 5 ns — ½tcyc + 3 ns — ½tcyc + 3 ns 5 ns 5 ns 5 ns 5 ns — ½tcyc + 10 ns 2.5 ns 2.5 ns — ½tcyc + 10 ns — 5 ns MAX. tHCLK + 5 ns — tHCLK - 10 ns — tHCLK + 5 ns — tHCLK + 5 ns — tHCLK + 5 ns — n × tHCLK + 5 ns — tHCLK + 5 ns — ½tcyc – 3 ns — ½tcyc – 3 ns — — — — — ½tcyc – 10 ns — — — ½tcyc – 10 ns — 10 ns — 10 ns — — — 271 ns 15 ns — — — 3 ns Data Valid Data Hold Data Setup Time Data Hold Time Chip Enable 1 Valid Chip Enable 1 Hold Chip Enable 2 Valid Chip Enable 2 Hold Output Enable Valid Output Enable Hold Write Enable Valid Write Enable Hold Card Direction Valid Card Direction Hold MMC Command Valid MMC Command Hold MMC Data Valid MMC Data Hold MMC Data Setup MMC Data Hold MMC Command Setup MMC Command Hold AC97 Output Valid AC97 Output Hold AC97 Input Setup AC97 Input Hold AC97 Synchronization Valid AC97 Synchronization Hold SSP Frame Output Valid SSP Frame Output Hold SSP Transmit Valid SSP Transmit Hold SSP Receive Setup SSP Receive Hold SSP Clock Period ACOUT delay from rising clock edge ACOUT Hold ACIN Setup ACIN Hold LCD Data Clock to Data Valid 4 4 4 4 3 3 3 3 DESCRIPTION NOTES MMC INTERFACE SIGNALS MMCCMD MMCDATA MMCDATA MMCCMD Output Output Input Input 50 pF 50 pF — — AC97 INTERFACE SIGNALS ACOUT ACIN ACSYNC Output Input Output 50 pF — 50 pF SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPTX SSPRX SSPCLK Output Output Input Output 50 pF 50 pF — 50 pF AUDIO CODEC INTERFACE (ACI) ACOUT ACIN Output Input 50 pF COLOR LCD CONTROLLER LCDVD [17:0] Output NOTES: 1. Register BCRx:WST1 = 0b000 2. The ‘x/x’ in the MIN./MAX. indicates (LH7A404-N0E-092-xx and H7A404-N0F-092-xx)/ (LH7A404-N0E-000-xx and LH7A404-N0F-000-xx), respectively. 3. ‘tcyc’ is the period of one MMC Clock 4. ‘tcyc’ is the period of one AC97 Clock 5. ‘nC’ in the MIN./MAX. columns indicates the number of system clock (HCLK) periods after valid address 6. For Output Drive strength specifications, refer to Table 2 Preliminary data sheet 37 LH7A404 NXP Semiconductors 32-Bit System-on-Chip SMC Waveforms Figure 8 and Figure 9 show waveforms and timing for an external asynchronous memory Write. Figure 10 and Figure 11 show the waveforms and timing for an external asynchronous memory Read. 0 HCLK 1 2 3 4 tWC A[27:0] VALID ADDRESS tDVWE, tDVBE tDHWE, tDHBE D[31:0] VALID DATA tAVCS tCS tAHCS nCSx tAVWE tWE nCS Valid tCSHWE nWE nWE Valid WRITE EDGE tAVBE tBEW tCSHBE nBLE nBLE Valid LH7A404-10 Figure 8. External Asynchronous Memory Write, Zero Wait States (BCRx:WST1 = 0b000) 38 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 0 HCLK 1 2 3 4 5 6 7 8 A[27:0] VALID ADDRESS D[31:0] VALID DATA nCSx nCSx Valid WRITE EDGE nWE nWE Valid nBLE nBLE Valid WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 0 WAIT STATE tWS tWS tWS tWS LH7A404-189 Figure 9. External Asynchronous Memory Write, Four Wait States (BCRx:WST1 = 0b100) Preliminary data sheet 39 LH7A404 NXP Semiconductors 32-Bit System-on-Chip 0 HCLK 1 2 3 4 tRC tAHCS, tAHOE, tAHBE A[27:0] VALID ADDRESS D[31:0] VALID DATA tDSCS tAVCS tCS DATA LATCHED HERE tDHCS nCSx nCS Valid tDSOE tAVOE tOE tDHOE nOE nOE Valid tDSBE tAVBE tBER tDHBE nBLE nBLE Valid LH7A404-190 Figure 10. External Asynchronous Memory Read, Zero Wait States (BCRx:WST1 = 0b000) 40 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 0 HCLK 1 2 3 4 5 6 7 8 9 10 A[27:0] VALID ADDRESS nCS[3:0, CS[7:6] nCSx Valid nOE nOE Valid nBLE nBLE Valid D[31:0] VALID DATA 0 WAIT STATE, DATA WOULD BE LATCHED HERE WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 tWS tWS tWS tWS 4 WAIT STATES, DATA LATCHED HERE LH7A404-12 Figure 11. External Asynchronous Memory Read, Four Wait States (BCRx:WST1 = 0b100) Preliminary data sheet 41 LH7A404 NXP Semiconductors 32-Bit System-on-Chip TIMING FOR nWAIT SIGNALLING In addition to being able to program the number of Wait States, the SMC also can use nWAIT signalling to extend transactions. When the nWAIT input is asserted, the current transaction is held in suspense until nWAIT is released, allowing slow memory or memory-mapped peripherals time to complete the action. Figure 12 through Figure 17 illustrate nWAIT timing using different WST register settings and circumstances. tDD_nWAIT_nCS(x) tDA_nCS(x)_nWAIT tDD_nWAIT_nOE nCS(x) nOE tA_nWAIT nWAIT SQ-4 SQ-3 SQ-2 SQ-1 SQ-0 HCLK Transaction Sequence WSD-2 DELAY WSD-1 DELAY SQ-4 WSD-0 nWAIT DELAY DELAY SQ-3 nWAIT DELAY SQ-2 nWAIT DELAY SQ-1 nWAIT DELAY SQ-0 nWAIT DELAY END CYCLE NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored LH7A404-203 Figure 12. nWAIT Read Sequence (BCRx:WST1 = 2); Minimum Wait State Example PARAMETER tDA_nCS(x)_nWAIT tDD_nWAIT_nCS(x) tDD_nWAIT_nOE tA_nWAIT DESCRIPTION Delay from nCS(x) assertion to nWAIT assertion Delay from nWAIT deassertion to nCS(x) deassertion Delay from nWAIT deassertion to nOE deassertion Assertion time of nWAIT 2 MIN. 0 MAX. 29 4 4 UNIT 1 HCLK periods HCLK periods HCLK periods HCLK periods NOTES: 1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O condtioning will cause these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions. 2. The Bank Configuration Register (BCRx:WST1) must have Read Wait States set to a minimum of 2. 3. The number of HCLK periods that nWAIT lags assertion of nCSx must be added to the minimum value for BCRx:WST1. For example, if nWAIT lags nCSx by 3 HCLK periods, the minimum setting of BCRx:WST1 is 2 + 3, or a total of 5 as the minimum value for BCRx:WST1. 4. No nWAIT delay cycles are added for any nWAIT assertions that occur prior to the beginning of the WSD-2 delay. These nWAIT assertions are ignored. 5. Once the WSD-2 delay begins, one HCLK cycle is added to the transaction each time nWAIT is sampled and queued (SQ-x). The nWAIT cycles begin being added after the Wait State Countdown reaches WSD-0. 6. Once nWAIT is sampled HIGH (de-asserted), the current memory transaction is queued to complete. 7. Since static and dynamic memory cannot be accessed at the same time, prolonged extension of an SMC transaction by either Wait States or nWAIT delays can cause refresh failure for the SDRAM, and may cause SDRAM data loss. 42 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 tDD_nWAIT_nCS(x) tDA_nCS(x)_nWAIT tDD_nWAIT_nOE) nCS(x) nOE tA_nWAIT nWAIT SI SI SQ-4 SQ-3 SQ-2 SQ-1 SQ-0 HCLK Transaction Sequence WSD-4 DELAY WSD-3 DELAY WSD-2 DELAY WSD-1 DELAY WSD-0 DELAY SQ-4 nWAIT DELAY SQ-3 nWAIT DELAY SQ-2 nWAIT DELAY SQ-1 nWAIT DELAY SQ-0 nWAIT DELAY END CYCLE NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored LH7A404-204 Figure 13. nWAIT Read Sequence (BCRx:WST1 = 4); Ignored and Queued nWAIT Delays tDA_nCS(x)_nWAIT nCS(x) nOE tA_nWAIT nWAIT SI SI HCLK Transaction Sequence WSD-4 DELAY WSD-3 DELAY WSD-2 DELAY WSD-1 DELAY WSD-0 DELAY END CYCLE NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored LH7A404-205 Figure 14. nWAIT Read Sequence (BCRx:WST1 = 4); nWAIT Has No Effect On Current Transaction Preliminary data sheet 43 LH7A404 NXP Semiconductors 32-Bit System-on-Chip tDD_nWAIT_nCS(x) tDA_nCS(x)_nWAIT tDD_nWAIT_nWE nCS(x) nWE tA_nWAIT nWAIT SQ-4 SQ-3 SQ-2 SQ-1 SQ-0 HCLK Transaction Sequence WSD-2 DELAY WSD-1 DELAY WSD-0 DELAY SQ-4 nWAIT DELAY SQ-3 nWAIT DELAY SQ-2 nWAIT DELAY SQ-1 nWAIT DELAY SQ-0 nWAIT DELAY END CYCLE NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored LH7A404-206 Figure 15. nWAIT Write Sequence (BCRx:WST1 = 2); Minimum Wait State Example PARAMETER tIDA_nCS(x)_nWAIT tDD_nWAIT_nCS(x) tDD_nWAIT_nWE tA_nWAIT DESCRIPTION Delay from nCS(x) assertion to nWAIT assertion Delay from nWAIT deassertion to nCS(x) deassertion Delay from nWAIT deassertion to nWE deassertion Assertion time of nWAIT 2 MIN. 0 MAX. 29 4 3 UNIT1 HCLK periods HCLK periods HCLK periods HCLK periods NOTES: 1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O condtioning will cause these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions. 2. The Bank Configuration Register (BCRx:WST1) must have Write Wait States set to a minimum of 2. 3. The number of HCLK periods that nWAIT lags assertion of nCSx must be added to the minimum value for BCRx:WST1. For example, if nWAIT lags nCSx by 3 HCLK periods, the minimum setting of BCRx:WST1 is 2 + 3, or a total of 5 as the minimum value for BCRx:WST1. 4. No nWAIT delay cycles are added for any nWAIT assertions that occur prior to the beginning of the WSD-2 delay. These nWAIT assertions are ignored. 5. Once the WSD-2 delay begins, one HCLK cycle is added to the transaction each time nWAIT is sampled and queued (SQ-x). The nWAIT cycles begin being added after the Wait State Countdown reaches WSD-0. 6. Once nWAIT is sampled HIGH (de-asserted), the current memory transaction is queued to complete. 7. Since static and dynamic memory cannot be accessed at the same time, prolonged extension of an SMC transaction by either Wait States or nWAIT delays can cause refresh failure for the SDRAM, and may cause SDRAM data loss. 44 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 tDD_nWAIT_nCS(x) tDA_nCS(x)_nWAIT tDD_nWAIT_nWE nCS(x) nWE tA_nWAIT nWAIT SI SI SQ-4 SQ-3 SQ-2 SQ-1 SQ-0 HCLK Transaction Sequence WSD-4 DELAY WSD-3 DELAY WSD2 DELAY WSD-1 DELAY WSD-0 DELAY SQ-4 nWAIT DELAY SQ-3 nWAIT DELAY SQ-2 nWAIT DELAY SQ-1 nWAIT DELAY SQ-0 nWAIT DELAY END CYCLE NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored LH7A404-207 Figure 16. nWAIT Write Sequence (BCRx:WST1 = 4); Ignored and Queued nWAIT Delays Preliminary data sheet 45 LH7A404 NXP Semiconductors 32-Bit System-on-Chip tDA_nCS(x)_nWAIT nCS(x) nWE tA_nWAIT nWAIT SI SI HCLK Transaction Sequence NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored WSD-4 DELAY WSD-3 DELAY WSD-2 DELAY WSD-1 DELAY WSD-0 DELAY END CYCLE LH7A404-208 Figure 17. nWAIT Write Sequence (BCRx:WST1 = 4); nWAIT Has No Effect On Current Transaction 46 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Synchronous Memory Controller Waveforms Figure 18 shows the waveform and timing for a Synchronous Burst Read (page already open). Figure 19 shows the waveform and timing for synchronous memory to activate a bank and Write. SCLK tOHXXX SDRAMcmd READ tOVB tOVXXX SA[13:0], SBANK[1:0] tOVA D[31:0] NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is static LOW. 5. SDCKE is static HIGH. BANK, COLUMN tISD tIHD DATA n + 2 DATA n DATA n + 1 DATA n + 3 LH7A404-13 Figure 18. Synchronous Burst Read SSPCLK SSPFRM SSPTXD/ SSPRXD MSB 4 to 16 BITS LSB LH7A404-24 Figure 19. Synchronous Bank Activate and Write Preliminary data sheet 47 LH7A404 NXP Semiconductors 32-Bit System-on-Chip SSP Waveforms The Synchronous Serial Port (SSP) supports three data frame formats: • Texas Instruments SSI • Motorola SPI • National Semiconductor MICROWIRE Each frame format is between 4 and 16 bits in length, depending upon the programmed data size. Each data frame is transmitted beginning with the Most Significant Bit (MSB) i.e. ‘big endian’. For all three formats, the SSP serial clock is held LOW (inactive) while the SSP is idle. The SSP serial clock transitions only during active transmission of data. The SSPFRM signal marks the beginning and end of a frame. Figure 20 and Figure 21 show Texas Instruments synchronous serial frame format, Figure 22 through Figure 29 show the Motorola SPI format, and Figure 30 and Figure 31 show National Semiconductor’s MICROWIRE data frame format. For Texas Instruments SSI format, the SSPFRM pin is pulsed prior to each frame’s transmission for one serial clock period beginning at its rising edge. For this frame format, both the SSP and the external slave device drive their output data on the rising edge of the clock and latch data from the other device on the falling edge. See Figure 20 and Figure 21. SSPCLK SSPFRM SSPTXD/ SSPRXD MSB 4 to 16 BITS LSB LH7A404-24 Figure 20. Texas Instruments Synchronous Serial Frame Format (Single Transfer) SSPCLK SSPFRM SSPTXD/ SSPRXD MSB 4 to 16 BITS LH7A404-25 LSB Figure 21. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) 48 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 For Motorola SPI, the serial frame pin (SSPFRM) is active LOW. The SPO and SPH bits in SSP Control Register 0 determine SSPCLK and SSPFRM operation in single and continuous modes. See Figures 22 through 29. SSPCLK nSSPFRM SSPRXD MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A404-26 Figure 22. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A404-27 Figure 23. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A404-28 Figure 24. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 1 Preliminary data sheet 49 LH7A404 NXP Semiconductors 32-Bit System-on-Chip SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A404-29 Figure 25. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A404-30 Figure 26. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1 SSPCLK nSSPFRM SSPRXD MSB LSB Q 4 to 16 BITS SSPTXD MSB LSB NOTE: Q is undefined. LH7A404-31 Figure 27. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0 50 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 SSPCLK nSSPFRM SSPTXD/ SSPRXD LSB MSB LSB MSB 4 to 16 BITS LH7A404-32 Figure 28. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A404-33 Figure 29. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1 Preliminary data sheet 51 LH7A404 NXP Semiconductors 32-Bit System-on-Chip For National Semiconductor MICROWIRE format, the serial frame pin (SSPFRM) is active LOW. Both the SSP and external slave device drive their output data on the falling edge of the clock, and latch data from the other device on the rising edge of the clock. Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor MICROWIRE format utilizes a master-slave messaging technique that operates in half-duplex. When a frame begins in this mode, an 8-bit control message is transmitted to the off-chip slave. During this transmission no incoming data is received by the SSP. After the message has been sent, the external slave device decodes the message. After waiting one serial clock period after the last bit of the 8bit control message was received it responds by returning the requested data. The returned data can be 4 to 16 bits in length, making the total frame length between 13 to 25 bits. See Figure 30 and Figure 31. SSPCLK nSSPFRM SSPTXD MSB LSB 8-BIT CONTROL SSPRXD 0 MSB LSB 4 to 16 BITS OUTPUT DATA LH7A404-34 Figure 30. MICROWIRE Frame Format (Single Transfer) SSPCLK nSSPFRM SSPTXD LSB MSB LSB 8-BIT CONTROL SSPRXD 0 MSB LSB MSB 4 to 16 BITS OUTPUT DATA LH7A404-35 Figure 31. MICROWIRE Frame Format (Continuous Transfers) 52 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 tCLK SSPCLK (Programmable CLOCK phase) CLOCK PHASE 1 CLOCK PHASE 2 tOVTX tOHTX SSPTX BITn OUTPUT BITn-1 OUTPUT tISRX tIHRX SSPRX tOVFRM BITn INPUT BITn-1 INPUT tOHFRM SSPFRM (Programmable FRAME phase and duration) LH7A404-199 Figure 32. General SSP Timing Preliminary data sheet 53 LH7A404 NXP Semiconductors 32-Bit System-on-Chip PC Card (PCMCIA) Waveforms Figure 33 shows the waveforms for PCMCIA Read transactions and Figure 34 shows the waveforms and timing for Write transactions. Figure 35 shows the precharge, access, and hold timing relationships. PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1) HCLK A[25:0] ADDRESS nPCREG tOVDREG tOHDREG nPCCEx (See Note 2) tOVCEx tOHCEx PCDIR tOVPCD tOHPCD D[31:0] tISD tIHD nPCOE/ nPCIOR tOVOE tOHOE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None LH7A404-15 DATA Figure 33. PCMCIA Read Transfer 54 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1) HCLK A[25:0] ADDRESS nPCREG tOVDREG tOHDREG nPCCEx (See Note 2) tOVCEx tOHCEx PCDIR tOVPCD D[15:0] tOVD DATA tOHD nPCWE/ nPCIOW tOVWE tOHWE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None LH7A404-16 Figure 34. PCMCIA Write Transfer ACCESS nPCWE, nPCOE, nPCIOW, nPCIOR PRECHARGE HOLD nCSx LH7A404-194 Figure 35. PCMCIA Precharge, Access, and Hold Waveform Preliminary data sheet 55 LH7A404 NXP Semiconductors 32-Bit System-on-Chip MMC Interface Waveforms Figure 36 shows the waveforms and timing for an MMC command or data Write. Figure 37 shows the waveforms and timing for an MMC command or data Read. AC97 Interface Waveforms Figure 38 shows the waveforms and timing for the AC97 interface Data Setup and Hold. MMCCLK tMMCCLK MMCCMD tOVCMD MMCDATA tOVDAT tOHDAT LH7A404-19 tOHCMD Figure 36. MMC Command/Data Write MMCCLK MMCCMD tISCMD tIHCMD MMCDATA tISDAT tIHDAT LH7A404-20 Figure 37. MMC Command/Data Read tACBITCLK ACBITCLK tOVAC97 ACOUT/ACSYNC tISAC97 tIHAC97 ACIN LH7A404-21 tOHAC97 Figure 38. AC97 Data Setup and Hold 56 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Audio Codec Interface (ACI) Timing The timing for the Audio Codec Interface are shown in Figure 39 and Figure 40. Transmit data is clocked on the rising edge of ACBITCLK (whether transmitted by the LH7A404 ACI or by the external codec chip); receive data is clocked on the falling edge. This allows full-speed, full duplex operation. Color LCD Controller Waveforms Figure 41 shows the Valid Output Setup Time for LCD data. Timing diagrams for each CLCDC mode are represented in Figure 42 through Figure 47. ACBITCLK tOVD tOHD ACSYNC/ACOUT ACIN tIS tIH LH7A404-178 Figure 39. ACI Signal Timing ACBITCLK ACSYNC BIT ACIN 7 6 5 4 3 2 1 0 7 6 ACIN SAMPLED ON FALLING EDGE LH7A404-153 Figure 40. ACI Data Stream LCDDCLK tOV LCDVD (SoC Output) DATA VALID LH7A404-198 Figure 41. CLCDC Valid Output Data Time Preliminary data sheet 57 58 1 STN HORIZONTAL LINE TIMING0:HSW LCDDCLK IS SUPPRESSED DURING LCDLLP TIMING0:HBP 16 × (TIMING0:PPL+1) LH7A404 CLCDC CLOCK (INTERNAL) TIMING2: CSEL TIMING2: BCD V2 LCDLP (LINE SYNC PULSE) TIMING2:IHS Y10 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL NXP Semiconductors Figure 42. STN Horizontal Timing HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... TIMING0:HFP DNNN LCDVD (LCD DATA) (See Note 1) HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS' NOTES: 1. The active data lines will vary with the type of STN panel: 4-bit, 8-bit, Color or Mono. 2. Circled numbers are LH7A404 pin numbers. LH7A404-98 32-Bit System-on-Chip Preliminary data sheet Preliminary data sheet DISPLAY-DEPENDENT TURN-ON DELAY 1 STN FRAME DISPLAY-DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE AC BIAS ACTIVE LCDTiming1: VSW = 0 LCDTiming1: VBP = 0 LCDTiming1: LPP LCDTiming1: VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'STN HORIZONTAL TIMING DIAGRAM' LH7A404-97 32-Bit System-on-Chip VDD VSS Y1 LCDVDDEN (DISPLAY ENABLE) Y10 LCDDCLK (PANEL DATA CLOCK) LCDTiming2:PCD LCDTiming2: BCD LCDTiming2: IPC NXP Semiconductors Figure 43. STN Vertical Timing V9 LCDENAB (AC BIAS) LCDTiming2:ACB LCDTiming2: IOE T4 LCDFP (FRAME PULSE) LCDTiming1: IVS PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES: 1. Signal polarities may vary for some displays. 2. Circled numbers are LH7A404 pin numbers. LH7A404 59 60 1 TFT HORIZONTAL LINE LCDTiming0:HSW LCDTiming0:HBP LCDTiming0:PPL LCDTiming0:HFP HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... DNNN HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS' LH7A404-96 LH7A404 CLCDC CLOCK (INTERNAL) LCDTiming2: CSEL LCDTiming2: BCD V2 LCDLP (HORIZ. SYNC PULSE) LCDTiming2:IHS NXP Semiconductors Figure 44. TFT Horizontal Timing Y10 LCDDCLK (PANEL DATA CLOCK) LCDTiming2:PCD LCDTiming2:BCD LCDTiming2:IPC LCDTiming2:CPL LCDVD (LCD DATA) GPIO PINMUX:PDOCON GPIO PINMUX:PEOCON GPIO PEDDR 32-Bit System-on-Chip Preliminary data sheet NOTE: Circled numbers are LH7A404 pin numbers. Preliminary data sheet DISPLAY-DEPENDENT TURN-ON DELAY 1 TFT FRAME DISPLAY DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE DATA ENABLE LCDTiming1: VSW LCDTiming1: VBP LCDTiming1: LPP LCDTiming1: VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'TFT HORIZONTAL TIMING DIAGRAM' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' LH7A404-95 32-Bit System-on-Chip VDD See Note 2 VSS Y1 LCDVDDEN (DISPLAY ENABLE FOR HIGH-VOLTAGE SUPPLIES) Y10 LCDDCLK (PANEL DATA CLOCK) LCDTiming2:PCD LCDTiming2: BCD LCDTiming2: IPC NXP Semiconductors Figure 45. TFT Vertical Timing V9 LCDENAB (DATA ENABLE) LCDTiming2:ACB LCDTiming2: IOE T4 LCDFP (VERTICAL SYNC PULSE) LCDTiming1: IVS PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES: 1. Signal polarties may vary for some displays. 2. The use of HR-CLP for high-voltage power control is optional on some TFT panels. 3. Circled numbers are LH7A404 pin numbers. LH7A404 61 LH7A404 NXP Semiconductors 32-Bit System-on-Chip 1 AD-TFT or HR-TFT HORIZONTAL LINE CLCDC CLOCK (INTERNAL) PERIPHCLKSEL2:LCSRC PERIPHCLKCTRL2:LCDCLK LCDCLKPRESCALE:LCDPSVAL (SHOWN FOR REFERENCE) LCDLP (HORIZONTAL SYNC PULSE) INPUTS TO THE ALI FROM THE CLCDC LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL TIMING0:HSW LCDVD[17:0] 16 × (TIMING0:PPL+1) TIMING0:HSW + TIMING0:HBP LCDENAB (INTERNAL DATA ENABLE) 001 002 003 004 005 006 007 008 PIXEL DATA 320 Y10 LCDDCLK (DELAYED FOR HR-TFT) LCDVD[17:0] (DELAYED FOR HR-TFT) 001 002 003 004 005 006 317 318 319 320 1 LCDDCLK ALITIMING2:SPLDEL OUTPUTS FROM THE ALI TO THE PANEL V3 LCDSPL (LINE START PULSE LEFT) 1 LCDDCLK V2 LCDLP (HORIZONTAL SYNC PULSE) ALITIMING1:LPDEL ALITIMING1:PSCLS ALITIMING2:PS2CLS2 U3 LCDCLS V5 LCDPS ALITIMING1:REVDEL W3 LCDREV NOTE: Circled numbers are LH7A404 pin numbers. LH7A404-188 Figure 46. AD-TFT and HR-TFT Horizontal Timing LCDTiming1:VSW LCDSPS (Vertical Sync) 1.5 µs - 4 µs LCDHRLP (Horizontal Sync) LCDVD (LCD Data) 2x H-LINE V3 LCDSPL T4 V2 LH7A404-78 Figure 47. AD-TFT and HR-TFT Timing 62 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Clock and State Controller (CSC) Waveforms Figure 48 shows the behavior of the LH7A404 when coming out of Reset or Power-On. Table 13 gives the timing parameters. At Power-On, nPOR must be held LOW until the 32.768 kHz oscillator is stable, and must be deasserted at least two 1 Hz clock periods before the WAKEUP signal is asserted. Once the 14.7456 MHz oscillator is stable, the PLLs require 250 µs to lock. On transition from Standby to Run (including a Cold Boot), the Wakeup pin must not be asserted for two 1 Hz clock periods after assertion of nPOR to allow time for sampling BATOK and nEXTPWR. The delay prevents a false ‘battery good’ indication caused by alkaline battery recovery that can immediately follow a battery-low switch off. nRESETOUT Timing Sequence Timing for the nRESETOUT sequence is shown for each of the three reset triggers (nPOR, nURESET, and nPWRFL) in Figure 49 through Figure 51, and timing values are presented in Table 14 through Table 16. Table 13. Reset AC Timing PARAMETER tOSC32 (32 kHz) tOSC14 (14 MHz) DESCRIPTION 32.768 kHz Oscillator Stabilization Time after Power On* 14.7456 MHz Oscillator Stabilization Time after WAKEUP MIN. MAX. 550 2.5 UNIT ms ms NOTE: *VDDC = VDDCmin VDDCmin VDDC XTAL32 tOSC32 WAKEUP tOSC14 XTAL14 nPOR LH7A404-22 Figure 48. PLL Start-up NOTE: *The timing relationship is specified as a cycle-based timing. Due to variations in crystal input clock jitter, power rail noise and I/O conditioning these timings will vary marginally. It is recommended that designers Preliminary data sheet 63 LH7A404 NXP Semiconductors 32-Bit System-on-Chip tDD_nPOR_WKUP tDA_nPOR_CLKEN tDA_nPOR_nRSTO tA_WKUP tDD_nPOR_nRSTO tDA_WKUP_CLKEN nPOR TRIGGER POINT WAKEUP nRESETOUT CLKEN LH7A404-202 Figure 49. nRESETOUT Timing for nPOR Trigger Table 14. nRESETOUT Timing Values for nPOR Trigger SIGNAL tDA_nPOR_nRSTO tDD_nPOR_nRSTO tDD_nPOR_WKUP tA_WKUP tDA_nPOR_CLKEN tDA_WKUP_CLKEN 2 2 4 30 4 MIN. TYP. MAX. 30 30 UNITS ns ns 1 Hz Periods* XTAL32 Periods* ns XTAL32 Periods* DESCRIPTION nPOR to nRESETOUT assertion delay nPOR to nRESETOUT deassertion delay nPOR deassertion to WAKEUP assert delay WAKEUP assertion time nURESET assertion to CLKEN deassertion delay WAKEUP to CLKEN assertion delay add some timing margin to avoid any possible corner case condition. NOTE: *The timing relationship is specified as a cycle-based timing. Due to variations in crystal input clock jitter, power rail noise and I/O conditioning these timings will vary marginally. It is recommended that designers 64 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 tA_nURESET tDA_nURESET_CLKEN tDA_nURESET_nRSTO tDD_nURESET_WKUP tA_WKUP tDD_nURESET_nRSTO tDA_WKUP_CLKEN nURESET TRIGGER POINT WAKEUP nRESETOUT CLKEN LH7A404-201 Figure 50. nRESETOUT Timing for nURESET Trigger Table 15. nRESETOUT Timing Values for nURESET Trigger SIGNAL tDA_nURESET_nRSTO tDD_nURESET_nRSTO tA_nURESET tDD_nURESET_WKUP tA_WKUP tDA_nURESET_CLKEN tDA_WKUP_CLKEN MIN. 2 0 4 2 4 2 2 4 4 TYP. MAX. 4 2 UNITS XTAL32 Periods* XTAL32 Periods* XTAL32 Periods* XTAL32 Periods* XTAL32 Periods* XTAL32 Periods* XTAL32 Periods* DESCRIPTION nURESET to nRESETOUT assertion delay nURESET to nRESETOUT deassertion delay nURESET assertion time nURESET deassertion to WAKEUP assertion delay WAKEUP assertion time nURESET assertion to CLKEN deassertion delay WAKEUP to CLKEN assertion delay add some timing margin to avoid any possible corner case condition. NOTE: *The timing relationship is specified as a cycle-based timing. Due to variations in crystal input clock jitter, power rail noise and I/O conditioning these timings will vary marginally. It is recommended that designers Preliminary data sheet 65 LH7A404 NXP Semiconductors 32-Bit System-on-Chip tA_nPWRFL tDA_nPWRFL_CLKEN tDA_nPWRFL_nRSTO tDD_nPWRFL_WKUP tA_WKUP tA_nRSTO tDA_WKUP_CLKEN nPWRFL TRIGGER POINT WAKEUP nRESETOUT CLKEN LH7A404-200 Figure 51. nRESETOUT Timing for nPWRFL Trigger Table 16. nRESETOUT Timing Values for nPWRFL Trigger SIGNAL tDA_nPWRFL_nRSTO tA_nRSTO tA_nPWRFL tDD_nPWRFL_WKUP tA_WKUP tDA_nPWRFL_CLKEN tDA_WKUP_CLKEN 4 2 4 2 2 4 4 MIN. 2 2 TYP. MAX. 4 UNITS* XTAL32 Periods XTAL32 Periods XTAL32 Periods 1 Hz Periods XTAL32 Periods XTAL32 Periods XTAL32 Periods DESCRIPTION nPWRFL to nRESETOUT assertion delay nRESETOUT assertion time nPWRFL assertion time nPWRFL deassertion to WAKEUP assertion delay WAKEUP assertion time nPWRFL assertion to CLKEN deassertion delay WAKEUP to CLKEN assertion delay add some timing margin to avoid any possible corner case condition. 66 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Reference Oscillator Circuit Design Figure 52 and Figure 53 show a reference oscillator design for both the 32.768 kHz and 14.7456 MHz clocks. Increased switching noise generated by faster switching circuits could affect the overall system stability. The amount of switching noise is directly affected by the application executed on the SoC. NXP suggests that users implementing a system to meet the full −40°C to +85°C specification use an external oscillator rather than a crystal to drive the system clock input of the System-on-Chip. This change from crystal to oscillator will increase the robustness (ie, noise immunity of the clock input to the SoC). Low Operating Temperatures and Noise Immunity The junction temperature, Tj, is the operating temperature of the transistors in the integrated circuit. The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating temperature, the faster the CMOS circuits will switch. ENABLE INTERNAL TO THE LH7A404 EXTERNAL TO THE LH7A404 XTALIN XTALOUT Y1 32.768 kHz R1 18 MΩ C1 15 pF GND NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is ≤ 5%. C2 18 pF GND REFERENCE CRYSTAL SPECIFICATIONS PARAMETER 32.768 kHz Crystal Tolerance Aging Load Capacitance ESR (MAX.) Drive Level Reference crystal DESCRIPTION Parallel Mode ±30 ppm ±3 ppm 12.5 pF 50 kΩ 1.0 µW (MAX.) MTRON SX1555 or equivalent LH7A404-168 Figure 52. 32.768 kHz External Oscillator Components and Schematic Preliminary data sheet 67 LH7A404 NXP Semiconductors 32-Bit System-on-Chip ENABLE INTERNAL TO THE LH7A404 EXTERNAL TO THE LH7A404 XTALIN XTALOUT Y1 14.7456 MHz R1 1 MΩ C1 18 pF GND C2 22 pF GND REFERENCE CRYSTAL SPECIFICATIONS NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 18 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is ≤ 5%. PARAMETER 14.7456 MHz Crystal Tolerance Stability Aging Load Capacitance ESR (MAX.) Drive Level Reference crystal DESCRIPTION (AT-Cut) Parallel Mode ±50 ppm ±100 ppm ±5 ppm 18 pF 40 Ω 100 µW (MAX.) MTRON SX2050 or equivalent LH7A404-167 Figure 53. 14.7456 MHz External Oscillator Components and Schematic 68 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 Printed Circuit Board Layout Practices LH7A404 POWER SUPPLY DECOUPLING The LH7A404 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power to the core logic, and VDDA/VSSA supply analog power to the PLLs. Each of the VDD and VDDC pins must be provided with a low impedance path to the corresponding board power supply. Likewise, the VSS and VSSC pins must be provided with a low impedance path to the board ground. Each power supply must be decoupled to ground using at least one 0.1 µ F high frequency capacitor located as close as possible to a VDDx-VSSx pin pair on each of the four sides of the chip. If room on the circuit board allows, add one 0.01 µ F high frequency capacitor near each VDDx-VSSx pair on the chip. To be effective, the capacitor leads and associated circuit board traces connecting to the chip VDDx-VSSx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. There must be one bulk 10 µ F capacitor for each power supply placed near one side of the chip. REFERENCE PLL, VDDA, VSSA FILTER The VDDA pins supply power to the chip PLL circuitry. VSSA is the ground return path for the PLL circuit. NXP recommends a low-pass filter attached as shown in Figure 54. The values of the inductor and capacitors are not critical. The low-pass filter prevents high frequency noise from adversely affecting the PLL circuits. The distance from the IC pin to the high frequency capacitor should be as short as possible. UNUSED INPUT SIGNAL CONDITIONING Floating input signals can cause excessive power consumption. Unused inputs without internal pull-up or pull-down resistors should be pulled up or down externally, to tie the signal to its inactive state. NXP recommends using no larger than 33 kΩ. Some GPIO signals may default to inputs. If the pins that carry these signals are unused, software can program these signals as outputs, eliminating the need for pull-ups or pull-downs. Power consumption may be higher than expected until software completes programming the GPIO. Some LH7A404 inputs have internal pull-ups or pull-downs. If unused, these inputs do not require external conditioning. OTHER CIRCUIT BOARD LAYOUT PRACTICES All outputs have fast rise and fall times. Printed circuit trace interconnection length must therefore be reduced to minimize overshoot, undershoot and reflections caused by transmission line effects of these fast output switching times. This recommendation particularly applies to the address and data buses. When considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. Capacitance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. Attention to power supply decoupling and printed circuit board layout becomes more critical in systems with higher capacitive loads. As these capacitive loads increase, transient currents in the power supply and ground return paths also increase. VDDC (SOURCE) VDDC LH7A404 10 µH VDDAx + 22 µF 0.1 µF VSSAx LH7A404-169 Figure 54. VDDA, VSSA Filter Circuit Preliminary data sheet 69 LH7A404 NXP Semiconductors 32-Bit System-on-Chip PACKAGE SPECIFICATIONS LFBGA324: plastic low profile fine-pitch ball grid array package; 324 balls SOT1021-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 e b ∅v ∅w M M CAB C C y1 C y Y W V U T R P N M L K J H G F E D C B A e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.7 A1 0.4 0.3 A2 1.35 1.15 b 0.5 0.4 D 17.1 16.9 E 17.1 16.9 e 0.8 e1 15.2 e2 15.2 v 0.15 w 0.08 y 0.12 y1 0.1 OUTLINE VERSION SOT1021-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 07-07-07 07-07-07 Figure 55. Package outline SOT1021-1 (LFBGA324) 70 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A404 REVISION HISTORY Table 17. Revision history Document ID LH7A404_N_1 Modifications: • First NXP version based on the LH7A404 data sheet of 20061201 Release date Data sheet status 20070716 Preliminary data sheet Change notice Supersedes LH7A404 V1-5 12-1-2006 Preliminary data sheet 71 LH7A404 NXP Semiconductors 32-Bit System-on-Chip 1. Legal information 1.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 1.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 1.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 1.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com © NXP B.V. 2007. All rights reserved. IMPORTANT NOTICE Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright © (year) by SHARP Corporation. is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document. NXP Semiconductors ANNEX A: Disclaimers (11) 1. t001dis100.fm: General (DS, AN, UM) General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 7. t001dis106.fm: No offer to sell or license (DS) No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable) Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: Bare die (DS; if applicable) Bare die (if applicable) — Products indicated as Bare Die are subject to separate specifications and are not tested in accordance with standard testing procedures. Product warranties and guarantees as stated in this document are not applicable to Bare Die Products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by NXP Semiconductors and customer. 10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable) AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. 11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if applicable) Suitability for use in automotive applications only — This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.