LPC1112FDH20/102:5

LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 microcontroller; up to 64 kB flash and 8 kB SRAM Rev. 9.2 — 26 March 2014 Product data sheet 1. General description The LPC1110/11/12/13/14/15 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC1110/11/12/13/14/15 operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC1110/11/12/13/14/15 includes up to 64 kB of flash memory, up to 8 kB of data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins. Remark: The LPC111x series consists of the LPC1100 series (parts LPC111x/101/201/301), LPC1100L series (parts LPC111x/002/102/202/302), and the LPC1100XL series (parts LPC111x/103/203/303/323/333). The LPC1100L and LPC1100XL series include the power profiles, a windowed watchdog timer, and a configurable open-drain mode. For related documentation, see Section 16 “References”. 2. Features and benefits  System:  ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.  ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).  Non-Maskable Interrupt (NMI) input selectable from several input sources (LPC1100XL series only).  Serial Wire Debug.  System tick timer.  Memory:  64 kB (LPC1115), 56 kB (LPC1114/333), 48 kB (LPC1114/323), 32 kB (LPC1114/102/201/202/203/301/302/303), 24 kB (LPC1113), 16 kB (LPC1112), 8 kB (LPC1111), or 4 kB (LPC1110) on-chip flash programming memory.  256 byte page erase function (LPC1100XL series only)  8 kB, 4 kB, 2 kB, or 1 kB SRAM.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. NXP Semiconductors LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 microcontroller  Digital peripherals:  Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. In addition, a configurable open-drain mode is supported on the LPC1100L and LPC1100XL series.  GPIO pins can be used as edge and level sensitive interrupt sources.  High-current output driver (20 mA) on one pin.  High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus (not on LPC1112FDH20/102).  Four general purpose counter/timers with up to eight capture inputs and up to 13 match outputs.  Programmable WatchDog Timer (WDT) the LPC1100 series only.  Programmable windowed WDT on the LPC1100L and LPC1100XL series only.  Analog peripherals:  10-bit ADC with input multiplexing among 5, 6, or 8 pins depending on package size.  Serial interfaces:  UART with fractional baud rate generation, internal FIFO, and RS-485 support.  Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LPC1100 and LPC1100L series LQFP48 package only).  I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode (not on LPC1112FDH20/102).  Clock generation:  12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.  Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock.  Power control:  Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes.  Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. (LPC1100L and LPC1100XL series only.)  Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.  Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins.  Power-On Reset (POR).  Brownout detect with up to four separate thresholds for interrupt and forced reset.  Unique device serial number for identification.  Single power supply (1.8 V to 3.6 V).  Available as LQFP48 package, HVQFN33 package, and TFBGA48 package. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller  LPC1100L series available as TSSOP28 package, DIP28 package, TSSOP20 package, and SO20 package.  Extended temperature (40 C to +105 C) for selected parts (see Table 2). 3. Applications  eMetering  Alarm systems  Lighting  White goods 4. Ordering information Table 1. Ordering information Type number Package Name Description Version SO20, TSSOP20, TSSOP28, and DIP28 packages LPC1110FD20 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC1111FDH20/002 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 LPC1112FD20/102 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC1112FDH20/102 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 LPC1112FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 LPC1114FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 LPC1114FN28/102 DIP28 DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1 HVQFN24/33, LQFP48, and TFBGA48 packages LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1111FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1111FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1111FHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1111JHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1111FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1111JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1112FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1112FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 1. Ordering information …continued Type number Package Name Description Version LPC1112FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1112FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1112FHN24/202 HVQFN24 HVQFN24: plastic thermal enhanced very thin quad flat package; no SOT616-3 leads; 24 terminals; body 4 x 4 x 0.85 mm LPC1112FHI33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1112FHI33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1112FHI33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1112JHI33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1112FHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1112JHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1112JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1112FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113FHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113JHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 1. Ordering information …continued Type number Package Name Description Version LPC1114FHI33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1114FHI33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1114JHI33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1114FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114FHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114JHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114FHN33/333 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1114JHN33/333 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1113FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1113FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1113JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/323 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114JBD48/323 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/333 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114JBD48/333 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1115FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 1. Ordering information …continued Type number Package Name Description Version LPC1115JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1115FET48/303 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5  4.5 SOT1155-2  0.7 mm LPC1115JET48/303 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5  4.5 SOT1155-2  0.7 mm 4.1 Ordering options Table 2. Ordering options Series Flash Total Power UART I2C/ SPI ADC GPIO Package SRAM profiles Fast+ channel Temp[1] LPC1100L 4 kB 1 kB yes 1 1 1 5 16 SO20 F LPC1111FDH20/002 LPC1100L 8 kB 2 kB yes 1 1 1 5 16 TSSOP20 F LPC1111FHN33/101 LPC1100 8 kB 2 kB no 1 1 1 8 28 HVQFN33 F LPC1111FHN33/102 LPC1100L 8 kB 2 kB yes 1 1 1 8 28 HVQFN33 F LPC1111FHN33/103 LPC1100XL 8 kB 2 kB yes 1 1 2 8 28 HVQFN33 F LPC1111JHN33/103 LPC1100XL 8 kB 2 kB yes 1 1 2 8 28 HVQFN33 J LPC1111FHN33/201 LPC1100 8 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1111FHN33/202 LPC1100L 8 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1111FHN33/203 LPC1100XL 8 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1111JHN33/203 LPC1100XL 8 kB 4 kB yes 1 1 2 8 28 HVQFN33 J 1 5 16 SO20 Type number LPC1110 LPC1110FD20 LPC1111 LPC1112 LPC1112FD20/102 LPC1100L 16 kB 4 kB yes 1 1 F LPC1112FDH20/102 LPC1100L 16 kB 4 kB yes 1 - 1 5 14 TSSOP20 F LPC1112FDH28/102 LPC1100L 16 kB 4 kB yes 1 1 1 6 22 TSSOP28 F LPC1112FHN24/202 LPC1100L 16 kB 4 kB yes 1 1 1 6 19 HVQFN24 F LPC1112FHN33/101 LPC1100 16 kB 2 kB no 1 1 1 8 28 HVQFN33 F LPC1112FHN33/102 LPC1100L 16 kB 2 kB yes 1 1 1 8 28 HVQFN33 F LPC1112FHN33/103 LPC1100XL 16 kB 2 kB yes 1 1 2 8 28 HVQFN33 F LPC1112JHN33/103 LPC1100XL 16 kB 2 kB yes 1 1 2 8 28 HVQFN33 J LPC1112FHN33/201 LPC1100 16 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1112FHN33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1112FHN33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1112JHN33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC1112FHI33/102 2 kB yes 1 1 1 8 28 HVQFN33 F LPC1100L 16 kB LPC1112FHI33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1112FHI33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1112JHI33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 2. Ordering options …continued Type number Series Flash Total Power UART I2C/ SPI ADC GPIO Package SRAM profiles Fast+ channel Temp[1] LPC1113 LPC1113FHN33/201 LPC1100 24 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1113FHN33/202 LPC1100L 24 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1113FHN33/203 LPC1100XL 24 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1113JHN33/203 LPC1100XL 24 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC1113FHN33/301 LPC1100 24 kB 8 kB no 1 1 1 8 28 HVQFN33 F LPC1113FHN33/302 LPC1100L 24 kB 8 kB yes 1 1 1 8 28 HVQFN33 F LPC1113FHN33/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1113JHN33/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1113FBD48/301 LPC1100 24 kB 8 kB no 1 1 2 8 42 LQFP48 F LPC1113FBD48/302 LPC1100L 24 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1113FBD48/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1113JBD48/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1114 LPC1114FDH28/102 LPC1100L 32 kB 4 kB yes 1 1 1 6 22 TSSOP28 F LPC1114FN28/102 32 kB 4 kB yes 1 1 1 6 22 DIP28 LPC1114FHN33/201 LPC1100 32 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1114FHN33/202 LPC1100L LPC1100L F 32 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1114FHN33/203 LPC1100XL 32 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHN33/203 LPC1100XL 32 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FHN33/301 LPC1100 32 kB 8 kB no 1 1 1 8 28 HVQFN33 F LPC1114FHN33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 28 HVQFN33 F LPC1114FHN33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHN33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FHN33/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHN33/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FHI33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 28 HVQFN33 F LPC1114FHI33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHI33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FBD48/301 LPC1100 32 kB 8 kB no 1 1 2 8 42 LQFP48 F LPC1114FBD48/302 LPC1100L 32 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114FBD48/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114JBD48/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1114FBD48/323 LPC1100XL 48 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114JBD48/323 LPC1100XL 48 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1114FBD48/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114JBD48/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 42 LQFP48 J 8 kB yes 1 1 2 8 42 LQFP48 F LPC1115 LPC1115FBD48/303 LPC1100XL 64 kB LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 2. Ordering options …continued Total Power UART I2C/ SPI ADC GPIO Package SRAM profiles Fast+ channel Temp[1] LPC1115JBD48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1115FET48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 TFBGA48 F LPC1115JET48/303 8 kB yes 1 1 2 8 42 TFBGA48 J Type number [1] Series Flash LPC1100XL 64 kB F = 40 C to +85 C, J = 40 C to +105 C. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5. Block diagram XTALIN XTALOUT(3) SWD RESET LPC1110/11/12/13/14 IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS POR ARM CORTEX-M0 clocks and controls FLASH 4/8/16/24/32 kB system bus slave GPIO ports PIO0/1/2/3 CLKOUT SRAM 1/2/4/8 kB slave ROM slave slave HIGH-SPEED GPIO AHB-LITE BUS slave AHB TO APB BRIDGE RXD TXD DTR, DSR, CTS(5), DCD, RI, RTS(5) CT32B0_MAT[3:0](3) CT32B0_CAP0(3) CT32B1_MAT[3:0](3) CT32B1_CAP0(3) CT16B0_MAT[2:0](3) CT16B0_CAP0(3) CT16B1_MAT[1:0](3) CT16B1_CAP0(3) UART AD[7:0](4) 10-bit ADC SPI0 SCK0, SSEL0 MISO0, MOSI0 SPI1(1) SCK1, SSEL1 MISO1, MOSI1 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 SCL SDA I2C-BUS(2) 16-bit COUNTER/TIMER 0 WDT 16-bit COUNTER/TIMER 1 IOCONFIG SYSTEM CONTROL PMU 002aae696 (1) LQFP48 packages only. (2) Not on LPC1112FDH20/102. (3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages. CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages. CT16B1_MAT[1:0], CT32B0_CAP0 not available on the HVQFN24 package. XTALOUT not available on LPC1112FHN24. (4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28 packages. AD[4:0] available on TSSOP20/SO20 packages. (5) All pins available on LQFP48 packages. RXD, TXD, DTR, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS available on TSSOP28/DIP28 packages. RXD, TXD, CTS available on HVQFN24 packages. RXD, TXD available on TSSOP20/SO20 packages. Fig 1. LPC1100/LPC1100L series block diagram LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller XTALIN XTALOUT RESET SWD LPC1111/12/13/14/15XL IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS POR ARM CORTEX-M0 system bus clocks and controls FLASH 8/16/24/32/ 48/56/64 kB slave GPIO ports PIO0/1/2/3 CLKOUT SRAM 2/4/8 kB slave ROM slave slave HIGH-SPEED GPIO AHB-LITE BUS slave AHB TO APB BRIDGE RXD TXD DTR, DSR(1), CTS, DCD(1), RI(1), RTS CT32B0_MAT[3:0] CT32B0_CAP[1:0] CT32B1_MAT[3:0] CT32B1_CAP[1:0] CT16B0_MAT[2:0] CT16B0_CAP[1:0] CT16B1_MAT[1:0] CT16B1_CAP[1:0] UART AD[7:0] 10-bit ADC SPI0 SCK0, SSEL0 MISO0, MOSI0 SPI1 SCK1, SSEL1 MISO1, MOSI1 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 SCL SDA I2C-BUS 16-bit COUNTER/TIMER 0 WWDT 16-bit COUNTER/TIMER 1 IOCONFIG SYSTEM CONTROL PMU 002aag780 (1) LQFP48 and TFBGA48 only. Fig 2. LPC1100XL series block diagram LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 6.1 Pinning Table 3. LPC111X Product data sheet Pin description overview Part Pin description table Pinning diagram LPC1110FD20 Table 4 Figure 8 LPC1111FDH20/002 Table 4 Figure 9 LPC1112FD20/102 Table 4 Figure 10 LPC1112FDH20/102 Table 5 Figure 9 LPC1112FHN24/202 Table 6 Figure 11 LPC1112FDH28/102 Table 7 Figure 12 LPC1114FDH28/102 Table 7 Figure 13 LPC1114FN28/102 Table 7 Figure 13 LPC1111FHN33/101 Table 9 Figure 6 LPC1111FHN33/102 Table 9 Figure 6 LPC1111JHN33/103 Table 11 Figure 7 LPC1111FHN33/103 Table 11 Figure 7 LPC1111FHN33/201 Table 9 Figure 6 LPC1111FHN33/202 Table 9 Figure 6 LPC1111FHN33/203 Table 11 Figure 7 LPC1111JHN33/203 Table 11 Figure 7 LPC1112FHN33/101 Table 9 Figure 6 LPC1112FHN33/102 Table 9 Figure 6 LPC1112FHN33/103 Table 11 Figure 7 LPC1112JHN33/103 Table 11 Figure 7 LPC1112FHN33/201 Table 9 Figure 6 LPC1112FHN33/202 Table 9 Figure 6 LPC1112FHN33/203 Table 11 Figure 7 LPC1112JHN33/203 Table 11 Figure 7 LPC1112FHI33/202 Table 9 Figure 6 LPC1112FHI33/203 Table 11 Figure 7 LPC1112JHI33/203 Table 11 Figure 7 LPC1113FHN33/201 Table 9 Figure 6 LPC1113FHN33/202 Table 9 Figure 6 LPC1113FHN33/203 Table 11 Figure 7 LPC1113JHN33/203 Table 11 Figure 7 LPC1113FHN33/301 Table 9 Figure 6 LPC1113FHN33/302 Table 9 Figure 6 LPC1113FHN33/303 Table 11 Figure 7 LPC1113JHN33/303 Table 11 Figure 7 LPC1114FHN33/201 Table 9 Figure 6 LPC1114FHN33/202 Table 9 Figure 6 All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC111X Product data sheet Pin description overview Part Pin description table Pinning diagram LPC1114FHN33/203 Table 11 Figure 7 LPC1114JHN33/203 Table 11 Figure 7 LPC1114FHN33/301 Table 9 Figure 6 LPC1114FHN33/302 Table 9 Figure 6 LPC1114JHN33/303 Table 11 Figure 7 LPC1114FHN33/303 Table 11 Figure 7 LPC1114FHN33/333 Table 11 Figure 7 LPC1114JHN33/333 Table 11 Figure 7 LPC1114FHI33/302 Table 9 Figure 6 LPC1114FHI33/303 Table 11 Figure 7 LPC1114JHI33/303 Table 11 Figure 7 LPC1113FBD48/301 Table 8 Figure 3 LPC1113FBD48/302 Table 8 Figure 3 LPC1113FBD48/303 Table 10 Figure 4 LPC1113JBD48/303 Table 10 Figure 4 LPC1114FBD48/301 Table 8 Figure 3 LPC1114FBD48/302 Table 8 Figure 3 LPC1114FBD48/303 Table 10 Figure 4 LPC1114JBD48/303 Table 10 Figure 4 LPC1114FBD48/323 Table 10 Figure 4 LPC1114JBD48/323 Table 10 Figure 4 LPC1114FBD48/333 Table 10 Figure 4 LPC1114JBD48/333 Table 10 Figure 4 LPC1115FBD48/303 Table 10 Figure 4 LPC1115JBD48/303 Table 10 Figure 4 LPC1115FET48/303 Table 10 Figure 5 LPC1115JET48/303 Table 10 Figure 5 All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 37 PIO3_1/DSR 38 PIO2_3/RI/MOSI1 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO1_11/AD7 43 PIO3_2/DCD 44 VDD 45 PIO1_5/RTS/CT32B0_CAP0 46 PIO1_6/RXD/CT32B0_MAT0 PIO2_6 1 36 PIO3_0/DTR PIO2_0/DTR/SSEL1 2 35 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 R/PIO1_0/AD1/CT32B1_CAP0 VSS 5 XTALIN 6 XTALOUT 7 VDD 8 PIO1_8/CT16B1_CAP0 9 28 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 10 27 PIO0_8/MISO0/CT16B0_MAT0 32 R/PIO0_11/AD0/CT32B0_MAT3 LPC1113FBD48/301 LPC1113FBD48/302 LPC1114FBD48/301 LPC1114FBD48/302 31 PIO2_11/SCK0 30 PIO1_10/AD6/CT16B1_MAT1 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO2_9 24 PIO0_7/CTS 23 PIO0_6/SCK0 22 PIO3_5 21 PIO2_5 20 PIO2_4 19 PIO3_4 18 PIO1_9/CT16B1_MAT0 17 PIO0_5/SDA 16 25 PIO2_10 PIO0_4/SCL 15 26 PIO2_2/DCD/MISO1 PIO2_8 12 PIO0_3 14 PIO2_7 11 PIO2_1/DSR/SCK1 13 Fig 3. 47 PIO1_7/TXD/CT32B0_MAT1 48 PIO3_3/RI 32-bit ARM Cortex-M0 microcontroller 002aae697 LPC1100 and LPC1100L series pin configuration LQFP48 package LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 37 PIO3_1/DSR/CT16B0_MAT1/RXD 38 PIO2_3/RI/MOSI1 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO1_11/AD7/CT32B1_CAP1 43 PIO3_2/DCD/CT16B0_MAT2/SCK1 44 VDD 45 PIO1_5/RTS/CT32B0_CAP0 46 PIO1_6/RXD/CT32B0_MAT0 PIO2_6/CT32B0_MAT1 1 36 PIO3_0/DTR/CT16B0_MAT0/TXD PIO2_0/DTR/SSEL1 2 35 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 R/PIO1_0/AD1/CT32B1_CAP0 VSS 5 32 R/PIO0_11/AD0/CT32B0_MAT3 XTALIN 6 XTALOUT 7 30 PIO1_10/AD6/CT16B1_MAT1/MISO1 VDD 8 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 9 28 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 10 27 PIO0_8/MISO0/CT16B0_MAT0 31 PIO2_11/SCK0/CT32B0_CAP1 LPC1113, LPC1114, LPC1115 PIO2_9/CT32B0_CAP0 24 PIO0_7/CTS 23 PIO0_6/SCK0 22 PIO3_5/CT16B1_CAP1/TXD 21 PIO2_5/CT32B0_MAT0 20 PIO2_4/CT16B1_MAT1/SSEL1 19 PIO3_4/CT16B0_CAP1/RXD 18 PIO1_9/CT16B1_MAT0/MOSI1 17 PIO0_5/SDA 16 25 PIO2_10 PIO0_4/SCL 15 26 PIO2_2/DCD/MISO1 PIO2_8/CT32B0_MAT3/TXD 12 PIO0_3 14 PIO2_7/CT32B0_MAT2/RXD 11 PIO2_1/DSR/SCK1 13 Fig 4. 47 PIO1_7/TXD/CT32B0_MAT1 48 PIO3_3/RI/CT16B0_CAP0 32-bit ARM Cortex-M0 microcontroller 002aag781 LPC1100XL series pin configuration LQFP48 package LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller ball A1 index area LPC1115 1 2 3 4 5 6 7 8 A B C D E F G H aaa-008364 Transparent top view VDD PIO3_2 PIO1_11/AD7 PIO1_4/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO1_3/AD4/CT32B1_MAT2 27 26 25 PIO1_5/RTS/CT32B0_CAP0 28 PIO1_6/RXD/CT32B0_MAT0 30 29 PIO1_7/TXD/CT32B0_MAT1 31 terminal 1 index area 32 LPC1100XL series pin configuration TFBGA48 package PIO2_0/DTR 1 24 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 3 22 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 4 21 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20 PIO1_10/AD6/CT16B1_MAT1 VDD 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 7 18 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0 9 10 11 12 13 14 15 16 PIO0_4/SCL PIO0_5/SDA PIO1_9/CT16B1_MAT0 PIO3_4 PIO3_5 PIO0_6/SCK0 PIO0_7/CTS 33 VSS PIO0_3 Fig 5. 002aae698 Transparent top view Fig 6. LPC1100 and LPC1100L series pin configuration HVQFN33 7x7 and 5x5 packages LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors PIO1_7/TXD/CT32B0_MAT1 PIO1_6/RXD/CT32B0_MAT0 PIO1_5/RTS/CT32B0_CAP0 VDD PIO3_2/CT16B0_MAT2/SCK1 PIO1_11/AD7/CT32B1_CAP1 PIO1_4/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO1_3/AD4/CT32B1_MAT2 31 30 29 28 27 26 25 terminal 1 index area 32 32-bit ARM Cortex-M0 microcontroller PIO2_0/DTR/SSEL1 1 24 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 3 22 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 4 21 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20 PIO1_10/AD6/CT16B1_MAT1/MISO1 VDD 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 7 PIO0_2/SSEL0/CT16B0_CAP0 8 9 10 11 12 13 14 15 16 PIO0_3 PIO0_4/SCL PIO0_5/SDA PIO1_9/CT16B1_MAT0/MOSI1 PIO3_4/CT16B0_CAP1/RXD PIO3_5/CT16B1_CAP1/TXD PIO0_6/SCK0 PIO0_7/CTS 33 VSS 18 PIO0_9/MOSI0/CT16B0_MAT1 17 PIO0_8/MISO0/CT16B0_MAT0 002aag782 Transparent top view Fig 7. LPC1100XL series pin configuration HVQFN33 PIO0_8/MISO0/CT16B0_MAT0 1 20 PIO0_4/SCL PIO0_9/MOSI0/CT16B0_MAT1 2 19 PIO0_2/SSEL0/CT16B0_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 18 PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 4 PIO0_5/SDA 5 17 RESET/PIO0_0 LPC1110FD20 LPC1112FD20/ 16 VSS 15 VDD 102 PIO0_6/SCK0 6 R/PIO1_0/AD1/CT32B1_CAP0 7 14 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 8 13 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 9 12 PIO1_7/TXD/CT32B0_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 10 11 PIO1_6/RXD/CT32B0_MAT0 002aag595 Fig 8. LPC1100L series pin configuration SO20 package LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_8/MISO0/CT16B0_MAT0 1 20 PIO0_4/SCL PIO0_9/MOSI0/CT16B0_MAT1 2 19 PIO0_2/SSEL0/CT16B0_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 18 PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 4 17 RESET/PIO0_0 PIO0_5/SDA 5 PIO0_6/SCK0 6 16 VSS 15 VDD LPC1111FDH20/002 R/PIO1_0/AD1/CT32B1_CAP0 7 14 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 8 13 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 9 12 PIO1_7/TXD/CT32B0_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 10 11 PIO1_6/RXD/CT32B0_MAT0 002aag596 Fig 9. LPC1100L series pin configuration TSSOP20 package with I2C-bus pins PIO0_8/MISO0/CT16B0_MAT0 1 20 PIO0_3 PIO0_9/MOSI0/CT16B0_MAT1 2 19 PIO0_2/SSEL0/CT16B0_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 18 PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 4 17 RESET/PIO0_0 VDDA 5 VSSA 6 R/PIO1_0/AD1/CT32B1_CAP0 7 14 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 8 13 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 9 12 PIO1_7/TXD/CT32B0_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 10 11 PIO1_6/RXD/CT32B0_MAT0 16 VSS LPC1112FDH20/102 15 VDD 002aag597 19 PIO1_3 20 PIO1_4 21 VSS 22 VDD terminal 1 index area 23 PIO1_6 24 PIO1_7 Fig 10. LPC1100L series pin configuration TSSOP20 package with VDDA and VSSA pins RESET/PIO0_0 1 18 PIO1_2 PIO0_1 2 17 PIO1_1 VSS 3 XTALIN 4 VDD 5 14 PIO0_10 PIO1_8 6 13 PIO0_9 PIO0_8 12 9 PIO0_5 PIO0_7 11 8 PIO0_4 PIO0_6 10 7 PIO0_2 LPC1112FHN24 16 PIO1_0 15 PIO0_11 002aah173 Transparent top view Fig 11. LPC1100L series pin configuration HVQFN24 package LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_8/MISO0/CT16B0_MAT0 1 28 PIO0_7/CTS PIO0_9/MOSI0/CT16B0_MAT1 2 27 PIO0_4/SCL SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 26 PIO0_3 R/PIO0_11/AD0/CT32B0_MAT3 4 25 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_5/SDA 5 24 PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_6/SCK0 6 VDDA 7 VSSA 8 R/PIO1_0/AD1/CT32B1_CAP0 9 23 RESET/PIO0_0 LPC1112FDH28/102 LPC1114FDH28/102 22 VSS 21 VDD 20 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 10 19 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 11 18 PIO1_9/CT16B1_MAT0 SWDIO/PIO1_3/AD4/CT32B1_MAT2 12 17 PIO1_8/CT16B1_CAP0 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 13 16 PIO1_7/TXD/CT32B0_MAT1 PIO1_5/RTS/CT32B0_CAP0 14 15 PIO1_6/RXD/CT32B0_MAT0 002aag598 Fig 12. LPC1100L pin configuration TSSOP28 package PIO0_8/MISO0/CT16B0_MAT0 1 28 PIO0_7/CTS PIO0_9/MOSI0/CT16B0_MAT1 2 27 PIO0_4/SCL SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 26 PIO0_3 R/PIO0_11/AD0/CT32B0_MAT3 4 25 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_5/SDA 5 24 PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_6/SCK0 6 23 RESET/PIO0_0 VDDA 7 VSSA 8 R/PIO1_0/AD1/CT32B1_CAP0 9 LPC1114FN28/ 102 22 VSS 21 VDD 20 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 10 19 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 11 18 PIO1_9/CT16B1_MAT0 SWDIO/PIO1_3/AD4/CT32B1_MAT2 12 17 PIO1_8/CT16B1_CAP0 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 13 16 PIO1_7/TXD/CT32B0_MAT1 PIO1_5/RTS/CT32B0_CAP0 14 15 PIO1_6/RXD/CT32B0_MAT0 002aag599 Fig 13. LPC1100L series pin configuration DIP28 package LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 18 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description LPC1100L series: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I2C-bus pins) Symbol Start Type Reset Description logic state [1] input Pin SO20/ TSSOP20 Table 4. PIO0_0 to PIO0_11 RESET/PIO0_0 I/O 17 [2] yes I Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 PIO0_4/SCL PIO0_5/SDA PIO0_6/SCK0 PIO0_8/MISO0/ CT16B0_MAT0 PIO0_9/MOSI0/ CT16B0_MAT1 SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 LPC111X Product data sheet 18 19 20 5 [3] [3] [4] [4] 6 [3] 1 [3] 2 3 [3] [3] yes yes yes yes yes yes yes yes I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. I I; PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 19 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1100L series: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I2C-bus pins) …continued Symbol Pin SO20/ TSSOP20 Table 4. R/PIO0_11/ AD0/CT32B0_MAT3 4 Start Type Reset Description logic state [1] input [5] yes PIO1_0 to PIO1_7 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_6/RXD/ CT32B0_MAT0 I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I/O 7 8 9 10 11 [5] [5] [5] [5] [3] [3] yes no no no no no PIO1_7/TXD/ CT32B0_MAT1 12 VDD 15 XTALIN 14 [6] - XTALOUT 13 [6] - VSS 16 I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O LPC111X Product data sheet - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. O - Output from the oscillator amplifier. - Ground. - - Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 20 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) Symbol Start logic input Pin TSSOP20 Table 5. PIO0_0 to PIO0_11 RESET/PIO0_0 Type Reset Description state [1] I/O 17 [2] yes I Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 PIO0_3 PIO0_8/MISO0/ CT16B0_MAT0 PIO0_9/MOSI0/ CT16B0_MAT1 LPC111X Product data sheet 18 19 [3] [3] yes yes 20 [3] yes 1 [3] yes 2 [3] yes I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. I/O I; PU PIO0_3 — General purpose digital input/output pin. I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 21 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) …continued Symbol Pin TSSOP20 Table 5. SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 3 R/PIO0_11/ AD0/CT32B0_MAT3 4 [3] [4] Start logic input Type yes I I; PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. yes PIO1_0 to PIO1_7 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_6/RXD/ CT32B0_MAT0 PIO1_7/TXD/ CT32B0_MAT1 VDD LPC111X Product data sheet Reset Description state [1] I/O 7 8 9 10 11 12 15 [4] [4] [4] [4] [3] [3] yes no no no no no - I Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I - 3.3 V supply voltage to the internal regulator and the external rail. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 22 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) …continued Pin TSSOP20 Table 5. Symbol Start logic input VDDA 5 - XTALIN 14 [5] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 13 [5] - O - Output from the oscillator amplifier. VSS 16 - I - Ground. VSSA 6 - I - Analog ground. [1] Type Reset Description state I - 3.3 V supply voltage to the ADC. Also used as the ADC reference voltage. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51). [5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 6. LPC1100L series: LPC1112 (HVQFN24 package) Symbol RESET/PIO0_0 HVQFN Start pin logic input Type 1[2] I yes Reset Description state [1] I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 PIO0_4/SCL LPC111X Product data sheet 2[3] 7[3] 8[4] yes yes yes I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 23 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. LPC1100L series: LPC1112 (HVQFN24 package) …continued Symbol PIO0_5/SDA PIO0_6/SCK0 HVQFN Start pin logic input Type 9[4] I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). 10[3] yes yes Reset Description state [1] PIO0_7/CTS 11[3] yes I/O I - CTS — Clear To Send input for UART. PIO0_8/MISO0/ CT16B0_MAT0 12[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ CT16B0_MAT1 13[3] I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 14[3] I I; PU SWCLK — Serial wire clock. R/PIO0_11/ AD0/CT32B0_MAT3 15[5] R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 LPC111X Product data sheet 16[5] 17[5] 18[5] yes yes yes yes no no I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 24 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. LPC1100L series: LPC1112 (HVQFN24 package) …continued Symbol SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP PIO1_6/RXD/ CT32B0_MAT0 HVQFN Start pin logic input Type 19[5] I/O 20[5] 23[3] PIO1_7/TXD/ CT32B0_MAT1 24[3] PIO1_8/ CT16B1_CAP0 6[3] XTALIN 4[6] VDD VSS no no no no Reset Description state [1] I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. 5; 22 - I - 1.8 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. 3; 21 - I - Ground. no [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the reset pad configuration. [3] Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled (see Figure 51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 25 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) Symbol Start Type Reset Description logic state [1] input Pin TSSOP28/ DIP28 Table 7. PIO0_0 to PIO0_11 RESET/PIO0_0 I/O 23 [2] yes I Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 24 [3] [3] yes yes I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. PIO0_2/SSEL0/ CT16B0_CAP0 25 I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 26 [3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 27 [4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. PIO0_5/SDA PIO0_6/SCK0 PIO0_7/CTS PIO0_8/MISO0/ CT16B0_MAT0 PIO0_9/MOSI0/ CT16B0_MAT1 LPC111X Product data sheet 5 [4] 6 [3] 28 [3] 1 [3] 2 [3] yes yes yes yes yes All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 26 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) …continued Symbol Pin TSSOP28/ DIP28 Table 7. SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 3 R/PIO0_11/ AD0/CT32B0_MAT3 4 Start Type Reset Description logic state [1] input [3] [5] yes yes PIO1_0 to PIO1_9 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP LPC111X Product data sheet I I; PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I/O 9 10 11 12 13 [5] [5] [5] [5] [5] yes no no no no I Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 27 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) …continued Symbol Pin TSSOP28/ DIP28 Table 7. PIO1_5/RTS/ CT32B0_CAP0 14 PIO1_6/RXD/ CT32B0_MAT0 15 PIO1_7/TXD/ CT32B0_MAT1 16 Start Type Reset Description logic state [1] input [3] [3] [3] no no no I/O I; PU PIO1_5 — General purpose digital input/output pin. O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. I/O I; PU PIO1_9 — General purpose digital input/output pin. O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. - 3.3 V supply voltage to the internal regulator and the external rail. PIO1_8/ CT16B1_CAP0 17 [3] PIO1_9/ CT16B1_MAT0 18 [3] VDD 21 - VDDA 7 - - - 3.3 V supply voltage to the ADC. Also used as the ADC reference voltage. XTALIN 20 [6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 19 [6] - O VSS 22 - VSSA 8 - no no - - Output from the oscillator amplifier. - Ground. - Analog ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 28 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 RESET/PIO0_0 Type Reset Description state [1] I/O 3[2] yes I Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 4[3] PIO0_2/SSEL0/ CT16B0_CAP0 10[3] PIO0_3 14[3] PIO0_4/SCL 15[4] PIO0_5/SDA 16[4] PIO0_6/SCK0 22[3] PIO0_7/CTS 23[3] PIO0_8/MISO0/ CT16B0_MAT0 27[3] PIO0_9/MOSI0/ CT16B0_MAT1 LPC111X Product data sheet 28[3] yes yes I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. yes I/O I; PU PIO0_3 — General purpose digital input/output pin. yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. yes yes yes yes yes All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 29 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued Symbol Pin SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 29[3] R/PIO0_11/ AD0/CT32B0_MAT3 32[5] Start logic input Type yes I I; PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. yes PIO1_0 to PIO1_11 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP PIO1_5/RTS/ CT32B0_CAP0 LPC111X Product data sheet Reset Description state [1] I/O 33[5] 34[5] 35[5] 39[5] 40[5] 45[3] yes no no no no no Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I/O I; PU PIO1_5 — General purpose digital input/output pin. O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 30 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued Symbol PIO1_6/RXD/ CT32B0_MAT0 Pin 46[3] Start logic input Type no I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. I/O I; PU PIO1_9 — General purpose digital input/output pin. O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. I/O I; PU PIO1_10 — General purpose digital input/output pin. I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O I; PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. PIO1_7/TXD/ CT32B0_MAT1 47[3] PIO1_8/ CT16B1_CAP0 9[3] PIO1_9/ CT16B1_MAT0 17[3] no PIO1_10/AD6/ CT16B1_MAT1 30[5] no PIO1_11/AD7 42[5] no no no PIO2_0 to PIO2_11 PIO2_0/DTR/SSEL1 PIO2_1/DSR/SCK1 PIO2_2/DCD/MISO1 PIO2_3/RI/MOSI1 Reset Description state [1] I/O 2[3] 13[3] 26[3] 38[3] no no no no Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I/O I; PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O - SSEL1 — Slave Select for SPI1. I/O I; PU PIO2_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O - SCK1 — Serial clock for SPI1. I/O I; PU PIO2_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. I/O - MISO1 — Master In Slave Out for SPI1. I/O I; PU PIO2_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. I/O - MOSI1 — Master Out Slave In for SPI1. PIO2_4 19[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin. PIO2_5 20[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin. PIO2_6 1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin. PIO2_7 11[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin. PIO2_8 12[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin. PIO2_9 24[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin. PIO2_10 25[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin. PIO2_11/SCK0 31[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 31 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued Symbol Pin Start logic input PIO3_0 to PIO3_5 Type Reset Description state [1] I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. PIO3_0/DTR 36[3] no PIO3_1/DSR 37[3] no PIO3_2/DCD 43[3] no PIO3_3/RI 48[3] no PIO3_4 18[3] PIO3_5 21[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin. VDD 8; 44 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 6[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 7[6] - O - Output from the oscillator amplifier. VSS 5; 41 - I - Ground. no I/O I; PU PIO3_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O I; PU PIO3_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O I; PU PIO3_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. I/O I; PU PIO3_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. I/O I; PU PIO3_4 — General purpose digital input/output pin. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for LPC111x/101/201/301, pins pulled up to full VDD level on LPC111x/002/102/202/302 (VDD = 3.3 V)); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 32 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start Type logic input Reset Description state [1] PIO0_0 to PIO0_11 RESET/PIO0_0 Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 3[3] 8[3] yes yes I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I;PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clock out pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I;PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 10[4] yes I/O I;IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I;IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I;PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I;PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. I/O I;PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. PIO0_5/SDA 11[4] PIO0_6/SCK0 15[3] PIO0_7/CTS 16[3] PIO0_8/MISO0/ CT16B0_MAT0 17[3] PIO0_9/MOSI0/ CT16B0_MAT1 18[3] SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 19[3] LPC111X Product data sheet yes yes yes yes yes yes O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I;PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. I I;PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 33 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol R/PIO0_11/AD0/ CT32B0_MAT3 Pin 21[5] Start Type logic input Reset Description state yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. [1] PIO1_0 to PIO1_11 R/PIO1_0/AD1/ CT32B1_CAP0 R/PIO1_1/AD2/ CT32B1_MAT0 R/PIO1_2/AD3/ CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. 22[5] 23[5] 24[5] 25[5] 26[5] PIO1_5/RTS/ CT32B0_CAP0 30[3] PIO1_6/RXD/ CT32B0_MAT0 31[3] LPC111X Product data sheet yes no no no no no no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I;PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I;PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I/O I;PU PIO1_5 — General purpose digital input/output pin. O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. I/O I;PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 34 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol PIO1_7/TXD/ CT32B0_MAT1 Pin 32[3] PIO1_8/ CT16B1_CAP0 7[3] PIO1_9/ CT16B1_MAT0 12[3] PIO1_10/AD6/ CT16B1_MAT1 20[5] PIO1_11/AD7 27[5] Start Type logic input Reset Description state no I;PU PIO1_7 — General purpose digital input/output pin. no no no no I/O [1] O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I;PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. I/O I;PU PIO1_9 — General purpose digital input/output pin. O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. I/O I;PU PIO1_10 — General purpose digital input/output pin. I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O I;PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. PIO2_0 PIO2_0/DTR Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available. 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. PIO3_0 to PIO3_5 Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available. PIO3_2 28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin. PIO3_4 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin. PIO3_5 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin. VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5[6] - O - Output from the oscillator amplifier. VSS 33 - - - Thermal pad. Connect to ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for LPC111x/101/201/301, pins pulled up to full VDD level on LPC111x/002/102/202/302 (VDD = 3.3 V)); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 51). LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 35 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) Symbol TFBGA48 Table 10. LQFP48 [6] Start logic input PIO0_0 to PIO0_11 RESET/PIO0_0 Type Reset Description state [1] I/O 3[2] C1[2] yes I Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 4[3] C2[3] - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_2/SSEL0/ CT16B0_CAP0 10[3] PIO0_3 14[3] H2[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 15[4] G3[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. PIO0_5/SDA 16[4] F1[3] yes I/O H3[4] yes yes PIO0_6/SCK0 22[3] H6[3] yes PIO0_7/CTS 23[3] G7[3] yes LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 36 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller TFBGA48 LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued LQFP48 Table 10. Symbol Start logic input PIO0_8/MISO0/ CT16B0_MAT0 27[3] F8[3] yes PIO0_9/MOSI0/ CT16B0_MAT1 28[3] SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 29[3] R/PIO0_11/ AD0/CT32B0_MAT3 32[5] F7[3] E7[3] D8[5] yes yes yes PIO1_0 to PIO1_11 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 LPC111X Product data sheet Type Reset Description state I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. [1] I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. I I; PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I/O 33[5] 34[5] 35[5] 39[5] C7[5] C8[5] B7[5] B6[5] yes no no no Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 37 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Symbol PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP TFBGA48 LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued LQFP48 Table 10. Start logic input 40[5] A6[5] no PIO1_5/RTS/ CT32B0_CAP0 45[3] A3[3] PIO1_6/RXD/ CT32B0_MAT0 46[3] PIO1_7/TXD/ CT32B0_MAT1 47[3] PIO1_8/ CT16B1_CAP0 9[3] F2[3] no PIO1_9/ CT16B1_MAT0/ MOSI1 17[3] G4[3] no PIO1_10/AD6/ CT16B1_MAT1/ MISO1 30[5] PIO1_11/AD7/ CT32B1_CAP1 42[5] B3[3] B2[3] E8[5] A5[5] no no no no no PIO2_0 to PIO2_11 PIO2_0/DTR/SSEL1 PIO2_1/DSR/SCK1 LPC111X Product data sheet Type I/O Reset Description state [1] I; PU I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I/O I; PU PIO1_5 — General purpose digital input/output pin. O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. I/O I; PU PIO1_9 — General purpose digital input/output pin. O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. I/O - MOSI1 — Master Out Slave In for SPI1. I/O I; PU PIO1_10 — General purpose digital input/output pin. I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O - MISO1 — Master In Slave Out for SPI1. I/O I; PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. I - CT32B1_CAP1 — Capture input 1 for 32-bit timer 1. I/O 2[3] 13[3] B1[3] H1[3] no no PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I; PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O - SSEL1 — Slave Select for SPI1. I/O I; PU PIO2_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O - SCK1 — Serial clock for SPI1. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 38 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Symbol PIO2_2/DCD/MISO1 PIO2_3/RI/MOSI1 TFBGA48 LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued LQFP48 Table 10. Start logic input 26[3] G8[3] no 38[3] A7[3] PIO2_4/ CT16B1_MAT1/ SSEL1 19[3] G5[3] PIO2_5/ CT32B0_MAT0 20[3] H5[3] PIO2_6/ CT32B0_MAT1 1[3] A1[3] PIO2_7/ CT32B0_MAT2/RXD 11[3] PIO2_8/ CT32B0_MAT3/TXD 12[3] PIO2_9/ CT32B0_CAP0 24[3] PIO2_10 25[3] H8[3] PIO2_11/SCK0/ CT32B0_CAP1 31[3] D7[3] G2[3] G1[3] H7[3] no no no no no no no PIO3_1/DSR/ CT16B0_MAT1/RXD LPC111X Product data sheet Reset Description state I/O I; PU PIO2_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. I/O - MISO1 — Master In Slave Out for SPI1. [1] I/O I; PU PIO2_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. I/O - MOSI1 — Master Out Slave In for SPI1. I/O I; PU PIO2_4 — General purpose digital input/output pin. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. O - SSEL1 — Slave Select for SPI1. I/O I; PU PIO2_5 — General purpose digital input/output pin. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO2_6 — General purpose digital input/output pin. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I; PU PIO2_7 — General purpose digital input/output pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I - RXD — Receiver input for UART. I/O I; PU PIO2_8 — General purpose digital input/output pin. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. O - TXD — Transmitter output for UART. I/O I; PU PIO2_9 — General purpose digital input/output pin. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. no I/O I; PU PIO2_10 — General purpose digital input/output pin. no I/O I; PU PIO2_11 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I - CT32B0_CAP1 — Capture input for 32-bit timer 0. PIO3_0 to PIO3_5 PIO3_0/DTR/ CT16B0_MAT0/TXD Type I/O 36[3] 37[3] B8[3] A8[3] no no I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. I; PU PIO3_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. O - TXD — Transmitter Output for UART. I/O I; PU PIO3_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. I - RXD — Receiver input for UART. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 39 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller TFBGA48 LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued LQFP48 Table 10. Symbol Start logic input PIO3_2/DCD/ CT16B0_MAT2/ SCK1 43[3] A4[3] no PIO3_3/RI/ CT16B0_CAP0 48[3] PIO3_4/ CT16B0_CAP1/RXD 18[3] PIO3_5/ CT16B1_CAP1/TXD 21[3] A2[3] H4[3] G6[3] no no no Type Reset Description state I/O I; PU PIO3_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I/O - SCK1 — Serial clock for SPI1. I/O I; PU PIO3_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. [1] I/O I; PU PIO3_4 — General purpose digital input/output pin. I - CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. I - RXD — Receiver input for UART I/O I; PU PIO3_5 — General purpose digital input/output pin. I - CT16B1_CAP1 — Capture input 1 for 16-bit timer 1. O - TXD — Transmitter output for UART VDD 8; 44 E2; B4 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 6[6] D1[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 7[6] E1[6] - O - Output from the oscillator amplifier. VSS 5; 41 D2; B5 - I - Ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level (VDD = 3.3 V)); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 40 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start Type logic input Reset Description state [1] PIO0_0 to PIO0_11 RESET/PIO0_0 Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 3[3] 8[3] yes yes I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I;PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clock out pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I;PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 10[4] yes I/O I;IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I;IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I;PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I;PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. I/O I;PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. PIO0_5/SDA 11[4] PIO0_6/SCK0 15[3] PIO0_7/CTS 16[3] PIO0_8/MISO0/ CT16B0_MAT0 17[3] PIO0_9/MOSI0/ CT16B0_MAT1 18[3] SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 19[3] LPC111X Product data sheet yes yes yes yes yes yes O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I;PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. I I;PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 41 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol R/PIO0_11/AD0/ CT32B0_MAT3 Pin 21[5] Start Type logic input Reset Description state yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. [1] PIO1_0 to PIO1_11 R/PIO1_0/AD1/ CT32B1_CAP0 R/PIO1_1/AD2/ CT32B1_MAT0 R/PIO1_2/AD3/ CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. 22[5] 23[5] 24[5] 25[5] 26[5] PIO1_5/RTS/ CT32B0_CAP0 30[3] PIO1_6/RXD/ CT32B0_MAT0 31[3] LPC111X Product data sheet yes no no no no no no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I;PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I;PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. In Deep power-down mode, this pin serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I/O I;PU PIO1_5 — General purpose digital input/output pin. O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. I/O I;PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 42 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol PIO1_7/TXD/ CT32B0_MAT1 Pin 32[3] PIO1_8/ CT16B1_CAP0 7[3] PIO1_9/ CT16B1_MAT0/ MOSI1 12[3] PIO1_10/AD6/ CT16B1_MAT1/ MISO1 20[5] PIO1_11/AD7/ CT32B1_CAP1 27[5] Start Type logic input Reset Description state no I;PU PIO1_7 — General purpose digital input/output pin. no no no no I/O [1] O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I;PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. I/O I;PU PIO1_9 — General purpose digital input/output pin. O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. I/O - MOSI1 — Master Out Slave In for SPI1 I/O I;PU PIO1_10 — General purpose digital input/output pin. I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O - MISO1 — Master In Slave Out for SPI1 I/O I;PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. I - CT32B1_CAP1 — Capture input 1 for 32-bit timer 1. PIO2_0 PIO2_0/DTR/SSEL1 Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available. 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O - PIO3_0 to PIO3_5 PIO3_2/ CT16B0_MAT2/ SCK1 28[3] PIO3_4/ CT16B0_CAP1/RXD 13[3] PIO3_5/ CT16B1_CAP1/TXD 14[3] LPC111X Product data sheet SSEL1 — Slave Select for SPI1. Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available. no no no I/O I;PU PIO3_2 — General purpose digital input/output pin. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I/O - SCK1 — Serial clock for SPI1. I/O I;PU PIO3_4 — General purpose digital input/output pin. I - CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. I - RXD — Receiver input for UART. I/O I;PU PIO3_5 — General purpose digital input/output pin. I - CT16B1_CAP1 — Capture input 1 for 16-bit timer 1. O - TXD — Transmitter output for UART. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 43 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol Pin Start Type logic input Reset Description state [1] VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5[6] - O - Output from the oscillator amplifier. VSS 33 - - - Thermal pad. Connect to ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level (VDD = 3.3 V)); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 44 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC1110/11/12/13/14/15 contain 64 kB (LPC1115), 56 kB (LPC1114/333), 48 kB (LPC1114/323), 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), 8 kB (LPC1111) or 4 kB (LPC1110) of on-chip flash memory. 7.3 On-chip SRAM The LPC1110/11/12/13/14/15 contain a total of 8 kB, 4 kB, 2 kB, or 1 kB on-chip static RAM memory. 7.4 Memory map The LPC1110/11/12/13/14/15 incorporate several distinct memory regions, shown in the following figures. Figure 14 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 45 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller AHB peripherals LPC1110/11/12/13/14 4 GB 0x5020 0000 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 127-16 reserved 0xE000 0000 0x5004 0000 reserved 0x5020 0000 AHB peripherals 0x5000 0000 12-15 GPIO PIO3 8-11 GPIO PIO2 4-7 GPIO PIO1 0-3 GPIO PIO0 reserved APB peripherals 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 31-23 reserved 0x4005 C000 0x4008 0000 APB peripherals 1 GB SPI1(1) 22 0x4000 0000 0x4005 8000 21-19 reserved 0x4004 C000 reserved 0x2000 0000 0.5 GB 18 system control 17 IOCONFIG 16 15 SPI0 flash controller 14 PMU reserved 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 13-10 reserved 0x1FFF 4000 16 kB boot ROM 0x4002 8000 0x1FFF 0000 reserved 0x1000 2000 8 kB SRAM (LPC1113/14/301/302) 0x1000 1000 4 kB SRAM (LPC1111/12/13/14/201/102/202) 2 kB SRAM (LPC1111/12/101/002/102) 1 kB SRAM (LPC1110) 0x1000 0800 0x1000 0400 0x1000 0000 reserved 0x0000 8000 32 kB on-chip flash (LPC1114) 24 kB on-chip flash (LPC1113) 16 kB on-chip flash (LPC1112) 8 kB on-chip flash (LPC1111) 0 GB 0x4004 8000 4 kB on-chip flash (LPC1110) 0x0000 6000 9 reserved 8 reserved 0x4002 0000 7 ADC 0x4001 C000 6 32-bit counter/timer 1 0x4001 8000 5 32-bit counter/timer 0 0x4001 4000 4 16-bit counter/timer 1 0x4001 0000 3 16-bit counter/timer 0 0x4000 C000 2 UART 0x4000 8000 1 0 WDT 0x4000 4000 I2C-bus(2) 0x4000 0000 0x4002 4000 0x0000 4000 0x0000 2000 0x0000 1000 0x0000 00C0 active interrupt vectors 0x0000 0000 0x0000 0000 002aae699 (1) LQFP48 package only. (1) Not on part LPC1112FDH20/102. Fig 14. LPC1100 and LPC1100L series memory map LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 46 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller AHB peripherals LPC1111/12/13/14/15XL 4 GB 0x5020 0000 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 127-16 reserved 0xE000 0000 0x5004 0000 reserved 0x5020 0000 AHB peripherals 0x5000 0000 12-15 GPIO PIO3 8-11 GPIO PIO2 4-7 GPIO PIO1 0-3 GPIO PIO0 reserved APB peripherals 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 31-23 reserved 0x4005 C000 0x4008 0000 APB peripherals 1 GB SPI1 22 0x4000 0000 0x4005 8000 21-19 reserved 0x4004 C000 reserved 0x2000 0000 0.5 GB reserved 18 system control 17 IOCONFIG 16 15 SPI0 flash controller 14 PMU 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x1FFF 4000 16 kB boot ROM 13-10 reserved 0x1FFF 0000 0x4002 8000 reserved 8 kB SRAM (LPC1113/14/15/303/323/333) 0x1000 2000 9 reserved 0x1000 1000 8 reserved 0x4002 0000 7 ADC 0x4001 C000 0x1000 0800 6 32-bit counter/timer 1 0x4001 8000 0x1000 0000 5 32-bit counter/timer 0 0x4001 4000 4 16-bit counter/timer 1 0x4001 0000 3 16-bit counter/timer 0 0x4000 C000 2 UART 0x4000 8000 1 0 WWDT 0x4000 4000 I2C-bus 0x4000 0000 4 kB SRAM (LPC1111/12/13/14/203) 2 kB SRAM (LPC1111/12/103) reserved 0x0001 0000 64 kB on-chip flash (LPC1115) 56 kB on-chip flash (LPC1114/333) 48 kB on-chip flash (LPC1114/323) 32 kB on-chip flash (LPC1114) 24 kB on-chip flash (LPC1113) 16 kB on-chip flash (LPC1112) 8 kB on-chip flash (LPC1111) 0 GB 0x0000 E000 0x0000 C000 0x4002 4000 0x0000 8000 0x0000 6000 0x0000 4000 0x0000 00C0 0x0000 2000 active interrupt vectors 0x0000 0000 002aag788 0x0000 0000 Fig 15. LPC1100XL series memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 47 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • In the LPC1110/11/12/13/14/15, the NVIC supports 32 vectored interrupts including up to 13 inputs to the start logic from individual GPIO pins. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC1110/11/12/13/14/15 use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. • Entire port value can be written in one instruction. Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features • Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. • Direction control of individual bits. • All I/O default to inputs with pull-ups enabled after reset with the exception of the I2C-bus pins PIO0_4 and PIO0_5. • Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin (except for pins PIO0_4 and PIO0_5). • On the LPC1100, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 2.6 V (VDD = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 48 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • On the LPC1100L and LPC1100XL series, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block. • Programmable open-drain mode for series LPC1100L and LPC1100XL. 7.8 UART The LPC1110/11/12/13/14/15 contain one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features • • • • • Maximum UART data bit rate of 3.125 MBit/s. 16 Byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit mode. • Support for modem control. 7.9 SPI serial I/O controller The LPC1100 and LPC1100L series contain two SPI controllers on the LQFP48 package and one SPI controller on the HVQFN33/TSSOP28/DIP28/TSSOP20/SO20 packages (SPI0). The LPC1100XL series contain two SPI controllers. Both SPI controllers support SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.9.1 Features • Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 49 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame 7.10 I2C-bus serial I/O controller The LPC1110/11/12/13/14/15 contain one I2C-bus controller. Remark: Part LPC1112FDH20/102 does not contain the I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 Features • The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s. • • • • • Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.11 10-bit ADC The LPC1110/11/12/13/14/15 contain one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.11.1 Features • • • • • • LPC111X Product data sheet 10-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 V to VDD. 10-bit conversion time  2.44 s (up to 400 kSamples/s). Burst conversion mode for single or multiple inputs. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 50 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. 7.12 General purpose external event counter/timers The LPC1110/11/12/13/14/15 include two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes up to two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.12.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • Up to two capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 7.13 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.14 Watchdog timer (LPC1100 series, LPC111x/101/201/301) Remark: The watchdog timer without windowed features is available on parts LPC111x/101/201/301. The purpose of the watchdog is to reset the microcontroller within a selectable time period. 7.14.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 51 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. 7.15 Windowed WatchDog Timer (LPC1100L and LPC1100XL series) Remark: The windowed watchdog timer is available on the LPC1100L and LPC1100XL series only. The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.15.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). This gives a wide range of potential timing choices of watchdog operation under different power conditions. 7.16 Clocking and power control 7.16.1 Crystal oscillators The LPC1110/11/12/13/14/15 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 52 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Following reset, the LPC1110/11/12/13/14/15 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 16 for an overview of the LPC1110/11/12/13/14/15 clock generation. SYSTEM CLOCK DIVIDER AHB clock 0 (system) system clock 18 AHB clocks 1 to 18 (memories and peripherals) SYSAHBCLKCTRL[1:18] (AHB clock enable) IRC oscillator SPI0 PERIPHERAL CLOCK DIVIDER SPI0 UART PERIPHERAL CLOCK DIVIDER UART SPI1 PERIPHERAL CLOCK DIVIDER SPI1 WDT CLOCK DIVIDER WDT main clock watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator IRC oscillator SYSPLLCLKSEL (system PLL clock select) watchdog oscillator WDTUEN (WDT clock update enable) IRC oscillator system oscillator watchdog oscillator CLKOUTUEN (CLKOUT update enable) CLKOUT PIN CLOCK DIVIDER CLKOUT pin 002aae514 Fig 16. LPC1110/11/12/13/14/15 clock generation block diagram 7.16.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1110/11/12/13/14/15 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.16.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 53 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 7.16.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and temperature is 40 %. 7.16.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The PLL output frequency must be lower than 100 MHz. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.16.3 Clock output The LPC1110/11/12/13/14/15 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.16.4 Wake-up process The LPC1110/11/12/13/14/15 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.16.5 Power control The LPC1110/11/12/13/14/15 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.16.5.1 Power profiles (LPC1100L and LPC1100XL series only) The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC1110/11/12/13/14/15 for one of the following power modes: LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 54 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Default mode corresponding to power configuration after reset. • CPU performance mode corresponding to optimized processing capability. • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. 7.16.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.16.5.3 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings. Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip from Deep-sleep mode. Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free. 7.16.5.4 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1110/11/12/13/14/15 can wake up from Deep power-down mode via the WAKEUP pin. A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode. When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from floating while in Deep power-down mode. 7.17 System control 7.17.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in Table 8 to Table 9 as input to the start logic has an individual interrupt in the NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 55 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller The start logic must be configured in the system configuration block and in the NVIC before being used. 7.17.2 Reset Reset has four sources on the LPC1110/11/12/13/14/15: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. An external pull-up resistor is required on the RESET pin if Deep power-down mode is used. 7.17.3 Brownout detection The LPC1110/11/12/13/14/15 includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. 7.17.4 Code security (Code Read Protection - CRP) This feature of the LPC1110/11/12/13/14/15 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details see the LPC111x user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the UART. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 56 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC111x user manual. 7.17.5 APB interface The APB peripherals are located on one APB bus. 7.17.6 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.17.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs serve as external interrupts (see Section 7.17.1). 7.18 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 57 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit [2] 0.5 +4.6 V 5 V tolerant I/O pins; only valid when the VDD supply voltage is present [2][3] 0.5 +5.5 V 5 V tolerant open-drain pins PIO0_4 and PIO0_5 [2][4] 0.5 +5.5 V [2][5] 0.5 4.6 V supply voltage (core and external rail) VDD input voltage VI VIA analog input voltage pin configured as analog input IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); - 100 mA Tstg storage temperature non-operating 65 +150 C Tj(max) maximum junction temperature - 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins - +6500 V Tj < 125 C [1] [6] [7] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 16. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 16) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Including voltage on outputs in 3-state mode. [4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [5] See Table 18 for maximum operating voltage. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 58 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 13. Thermal characteristics Symbol Parameter Tj(max) maximum junction temperature Table 14. Conditions Min Typ Max Unit - - 125 C LPC111x/x01 Thermal resistance value (C/W): ±15 % HVQFN33 LQFP48 ja ja JEDEC (4.5 in  4 in) JEDEC (4.5 in  4 in) 0 m/s 40.4 0 m/s 82.1 1 m/s 32.7 1 m/s 73.7 2.5 m/s 28.3 2.5 m/s 68.2 Single-layer (4.5 in  3 in) 8-layer (4.5 in  3 in) 0 m/s 84.8 0 m/s 115.2 1 m/s 61.6 1 m/s 94.7 2.5 m/s 53.1 2.5 m/s 86.3 jc 20.3 jc 29.6 jb 1.1 jb 34.2 LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 59 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 15. LPC111x/x02 Thermal resistance value (C/W): ±15 % HVQFN33 LQFP48 ja ja JEDEC (4.5 in  4 in) JEDEC (4.5 in  4 in) 0 m/s 40.8 0 m/s 83.3 1 m/s 33.1 1 m/s 74.9 2.5 m/s 28.7 2.5 m/s 69.4 0 m/s 85.2 0 m/s 116.3 1 m/s 62 1 m/s 96 2.5 m/s 53.5 2.5 m/s 87.5 Single-layer (4.5 in  3 in) 8-layer (4.5 in  3 in) jc 17.9 jc 28.3 jb 1.5 jb 35.5 LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 60 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Static characteristics 10.1 LPC1100, LPC1100L series Table 16. Static characteristics (LPC1100, LPC1100L series) Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) Min Typ[1] Max Unit 1.8 3.3 3.6 V - 3 - mA - 9 - mA - 2 - mA [2][3][8] - 6 - A [2][9] - 220 - nA Conditions LPC1100 series (LPC111x/101/201/301) power consumption IDD supply current Active mode; code while(1){} executed from flash system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Sleep mode; system clock = 12 MHz [2][3][4] [5][6] [2][3][5] [6][7] [2][3][4] [5][6] VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V Deep power-down mode; VDD = 3.3 V LPC1100L series (LPC111x/002/102/202/302) power consumption in low-current mode[11] IDD supply current Active mode; code while(1){} executed from flash system clock = 1 MHz VDD = 3.3 V system clock = 6 MHz VDD = 3.3 V system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Sleep mode; system clock = 12 MHz - 840 - A - 1 - mA - 2 - mA - 7 - mA - 1 - mA - 5 - mA [2][3][8] - 2 - A [2][9] - 220 - nA [2][3][5] [6][10] [2][3][5] [6][10] [2][3][4] [5][6] [2][3][5] [6][7] [2][3][4] [5][6] VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V Deep power-down mode; VDD = 3.3 V LPC111X Product data sheet [2][3][4] [5][6] All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 61 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 16. Static characteristics (LPC1100, LPC1100L series) …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V 0 - VDD V 0.7VDD - - V [12][13] [14] VO output voltage VIH HIGH-level input voltage VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 4 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 3 mA VDD  0.4 - - V 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V VOH = VDD  0.4 V; 4 - - mA 3 - - mA 4 - - mA VOL IOH LOW-level output voltage HIGH-level output current output active 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V IOL LOW-level output current VOL = 0.4 V 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V 3 - - mA - - 45 mA - - 50 mA IOHS HIGH-level short-circuit VOH = 0 V output current [15] IOLS LOW-level short-circuit output current VOL = VDD [15] Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 15 50 85 A 10 50 85 A 0 0 0 A 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V VDD < VI < 5 V High-drive output pin (PIO0_7) IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current - 0.5 10 nA LPC111X Product data sheet VI = VDD; on-chip pull-down resistor disabled All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 62 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 16. Static characteristics (LPC1100, LPC1100L series) …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V 0 - VDD V [12][13] [14] VO output voltage VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 20 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 12 mA VDD  0.4 - - V 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 12 - - mA VOL = 0.4 V 4 - - mA 3 - - mA - - 50 mA VOL LOW-level output voltage HIGH-level output current IOH LOW-level output current IOL output active 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V [15] IOLS LOW-level short-circuit output current VOL = VDD Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V 15 50 85 A 10 50 85 A 0 0 0 A 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V VDD < VI < 5 V I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V 3.5 - - mA 3 - - IOL LOW-level output current I2C-bus VOL = 0.4 V; pins configured as standard mode pins 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 63 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 16. Static characteristics (LPC1100, LPC1100L series) …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IOL Parameter LOW-level output current Conditions I2C-bus VOL = 0.4 V; pins configured as Fast-mode Plus pins Min Typ[1] Max Unit 20 - - mA 16 - - 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V input leakage current ILI VI = VDD VI = 5 V [16] - 2 4 A - 10 22 A Oscillator pins Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V pins configured for analog function - - 7.1 pF I2C-bus pins (PIO0_4 and PIO0_5) - - 2.5 pF pins configured as GPIO - - 2.8 pF Pin capacitance input/output capacitance Cio [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Tamb = 25 C. [3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] BOD disabled. [6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [7] IRC disabled; system oscillator enabled; system PLL enabled. [8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [9] WAKEUP pin and RESET pin are pulled HIGH externally. [10] System oscillator enabled; IRC disabled; system PLL disabled. [11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [12] Including voltage on outputs in 3-state mode. [13] VDD supply voltage must be present. [14] 3-state outputs go into 3-state mode in Deep power-down mode. [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] To VSS. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 64 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.2 LPC1100XL series Table 17. Static characteristics (LPC1100XL series) Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) Conditions Min Typ[1] Max Unit 1.8 3.3 3.6 V LPC1100XL series (LPC111x/103/203/303/323/333) power consumption in low-current mode[2] IDD supply current Active mode; code while(1){} executed from flash system clock = 3 MHz VDD = 3.3 V system clock = 6 MHz VDD = 3.3 V system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Sleep mode; system clock = 12 MHz [3][4][5] - 600 - A - 850 - A - 1.4 - mA - 5.8 - mA - 700 - A - 2.2 - mA - 1.8 15 A - - 50 A [6][7] [3][4][5] [6][7] [3][4][6] [7][8] [3][4][6] [7][9] [3][4][6] [7][8] VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V; 25 C [3][4][6] [7][8] [3][4] [10] Deep-sleep mode; VDD = 3.3 V; 105 C [4][10] Deep power-down mode; VDD = 3.3 V; 25 C [3][12] - 220 1000 nA Deep power-down mode; VDD = 3.3 V; 105 C [11][12] - - 3 A [11] Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V 0 - VDD V 0.7VDD - - V VO output voltage VIH HIGH-level input voltage LPC111X Product data sheet [13][14] output active [15] All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 65 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Static characteristics (LPC1100XL series) …continued Tamb = 40 C to +105 C, unless otherwise specified. Min Typ[1] Max Unit LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 4 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 3 mA VDD  0.4 - - V 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V VOH = VDD  0.4 V; 4 - - mA 3 - - mA 4 - - mA Symbol Parameter VIL VOL IOH LOW-level output voltage HIGH-level output current Conditions 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V IOL LOW-level output current VOL = 0.4 V 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V 3 - - mA - - 45 mA - - 50 mA IOHS HIGH-level short-circuit VOH = 0 V output current [16] IOLS LOW-level short-circuit output current VOL = VDD [16] Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 15 50 85 A 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V VDD < VI < 5 V 10 50 85 A 0 0 0 A High-drive output pin (PIO0_7) IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V 0 - VDD V 0.7VDD - - V [13][14] VO output voltage VIH HIGH-level input voltage VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V LPC111X Product data sheet output active [15] All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 66 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Static characteristics (LPC1100XL series) …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 20 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 12 mA VDD  0.4 - - V 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 20 - - mA VOL LOW-level output voltage IOH HIGH-level output current 1.8 V  VDD < 2.5 V 12 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOLS LOW-level short-circuit output current VOL = VDD Ipd pull-down current Ipu pull-up current 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V 3 - - mA - - 50 mA VI = 5 V 10 50 150 A VI = 0 V 15 50 85 A 10 50 85 A 0 0 0 A 0.7VDD - - V [16] 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V VDD < VI < 5 V I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V 3.5 - - mA 3 - - 20 - - 16 - - - 2 4 A - 10 22 A IOL LOW-level output current I2C-bus VOL = 0.4 V; pins configured as standard mode pins 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V IOL LOW-level output current I2C-bus VOL = 0.4 V; pins configured as Fast-mode Plus pins mA 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V ILI input leakage current VI = VDD VI = 5 V LPC111X Product data sheet [17] All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 67 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Static characteristics (LPC1100XL series) …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator pins Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V pins configured for analog function - - 7.1 pF I2C-bus pins (PIO0_4 and PIO0_5) - - 2.5 pF pins configured as GPIO - - 2.8 pF Pin capacitance input/output capacitance Cio [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [3] Tamb = 25 C. [4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [5] System oscillator enabled; IRC disabled; system PLL disabled. [6] BOD disabled. [7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [8] IRC enabled; system oscillator disabled; system PLL disabled. [9] IRC disabled; system oscillator enabled; system PLL enabled. [10] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [11] 105 C spec applies only to parts with the J designator (e.g. LPC1115JET48). [12] WAKEUP pin and RESET pin are pulled HIGH externally. [13] Including voltage on outputs in 3-state mode. [14] VDD supply voltage must be present. [15] 3-state outputs go into 3-state mode in Deep power-down mode. [16] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [17] To VSS. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 68 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.3 ADC static characteristics Table 18. ADC static characteristics Tamb = 40 C to +105 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage Cia analog input capacitance ED differential linearity error Conditions Min Typ Max Unit 0 - VDD V - - 1 pF [1][2] - - 1 LSB integral non-linearity [3] - -  1.5 LSB offset error [4] - -  3.5 LSB EG gain error [5] - - 0.6 % ET absolute error [6] - - 4 LSB Rvsi voltage source interface resistance - - 40 k Ri input resistance - - 2.5 M EL(adj) EO [7][8] [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 17. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 17. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 17. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 17. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 17. [7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia). LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 69 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 70 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.4 BOD static characteristics Table 19. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 1 Min Typ Max Unit assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V assertion - 1.46 - V de-assertion - 1.63 - V interrupt level 2 interrupt level 3 reset level 0 reset level 1 assertion - 2.06 - V de-assertion - 2.15 - V assertion - 2.35 - V de-assertion - 2.43 - V assertion - 2.63 - V de-assertion - 2.71 - V reset level 2 reset level 3 [1] LPC111X Product data sheet Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 71 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.5 Power consumption LPC1100 series (LPC111x/101/201/301) Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. 002aaf390 12 IDD (mA) 48 MHz(2) 8 36 MHz(2) 24 MHz(2) 4 12 MHz(1) 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 18. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies (for LPC111x/101/201/301) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 72 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf391 12 IDD (mA) 48 MHz(2) 8 36 MHz(2) 24 MHz(2) 4 0 −40 12 MHz(1) −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 19. Active mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111x/101/201/301) 002aaf392 8 IDD (mA) 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 20. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111x/101/201/301) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 73 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf394 40 IDD (μA) 30 3.6 V 3.3 V 2.0 V 1.8 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 21. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/101/201/301) 002aaf457 0.8 IDD (μA) 0.6 VDD = 3.6 V 3.3 V 2.0 V 1.8 V 0.4 0.2 0 −40 −15 10 35 60 85 temperature (°C) Fig 22. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/101/201/301) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 74 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.6 Power consumption LPC1100L series (LPC111x/002/102/202/302) Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. 002aaf980 10 IDD (mA) 8 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 23. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies (for LPC111x/002/102/202/302) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 75 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf981 10 IDD (mA) 8 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 24. Active mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111x/002/102/202/302) 002aaf982 6 IDD (mA) 48 MHz(2) 4 36 MHz(2) 24 MHz(2) 2 12 MHz(1) 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 25. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111x/002/102/202/302) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 76 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf977 5.5 IDD (μA) 4.5 3.5 VDD = 3.3 V, 3.6 V 1.8 V 2.5 1.5 −40 −15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 26. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/002/102/202/302) 002aaf978 0.8 IDD (μA) VDD = 3.6 V 3.3 V 1.8 V 0.6 0.4 0.2 0 −40 −15 10 35 60 85 temperature (°C) Fig 27. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111x/002/102/202/302) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 77 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.7 Power consumption LPC1100XL series (LPC111x/103/203/303/323/333) Table 20. Power consumption at very low frequencies using the watchdog oscillator Symbol Parameter Conditions[1] IDD supply current Active mode; code Min Typ[2] Max Unit while(1){} executed from flash system clock = 8.8 kHz - 275 - A system clock = 257 kHz - 305 - A system clock = 515 kHz - 335 - A system clock = 784 kHz - 368 - A system clock = 1028 kHz - 396 - A system clock = 2230 kHz - 538 - A Sleep mode; [1] system clock = 8.8 kHz - 274 - A system clock = 257 kHz - 285 - A system clock = 515 kHz - 295 - A system clock = 784 kHz - 309 - A system clock = 1028 kHz - 317 - A system clock = 2230 kHz - 368 - A WDT OSC enabled, VDD = 3.3 V, Temp = 25 C. Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled, IRC disabled, System Oscillator disabled, System PLL disabled, BOD disabled. All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 78 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. DDD  0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] ,'' ,'' P$          9''9  Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled. 12 MHz: IRC enabled; system oscillator, PLL disabled. 24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled. Fig 28. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies (for LPC111xXL) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 79 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller DDD  0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] ,'' ,'' P$            WHPSHUDWXUHƒ&  Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled. 12 MHz: IRC enabled; system oscillator, PLL disabled. 24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled. Fig 29. Active mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111xXL) DDD  ,'' ,'' P$ 0+] 0+] 0+] 0+] 0+] 0+] 0+]           WHPSHUDWXUHƒ&  Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled. 12 MHz: IRC enabled; system oscillator, PLL disabled. 24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled. Fig 30. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies (for LPC111xXL) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 80 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah553 20 IDD (μA) 15 VDD = 3.6 V 3.3 V 1.8 V 10 5 0 -40 -10 20 50 80 temperature (°C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 31. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111xXL) 002aah554 2 IDD (μA) 1.5 VDD = 3.6 V 3.3 V 1.8 V 1 0.5 0 -40 -10 20 50 80 temperature (°C) 110 Fig 32. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (for LPC111xXL) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 81 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.8 CoreMark data Remark: All CoreMark data were taken with the Keil uVision v. 4.6 tool. DDD  &0 LWHUDWLRQVV0+]  HIILFLHQF\ FSX GHIDXOWORZFXUUHQW          IUHTXHQF\0+]  VDD = 3.3 V; T = 25 °C; active mode; typical samples. Fig 33. CoreMark score for different Power API modes DDD  ,'' ,'' P$  FSX GHIDXOW HIILFLHQF\ ORZFXUUHQW          IUHTXHQF\0+]  VDD = 3.3 V; T = 25 °C; active mode; typical samples. System oscillator enabled; main clock derived from external clock signal; PLL and SYSAHBCLKDIV enabled for frequencies > 20 MHz. Fig 34. CoreMark current consumption for different power modes using external clock LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 82 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller DDD  ,'' ,'' P$  GHIDXOW FSX HIILFLHQF\ ORZFXUUHQW          IUHTXHQF\0+]  VDD = 3.3 V; T = 25 °C; active mode; typical samples. IRC enabled; main clock derived from IRC; PLL and SYSAHBCLKDIV enabled as needed. Fig 35. CoreMark current consumption for different power modes using IRC LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 83 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.9 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz. Table 21. Power consumption for individual analog and digital blocks Peripheral LPC111X Product data sheet Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.004 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.051 - - Independent of main clock frequency. Main PLL - 0.21 - ADC - 0.08 0.29 CLKOUT - 0.12 0.47 CT16B0 - 0.02 0.06 CT16B1 - 0.02 0.06 CT32B0 - 0.02 0.07 CT32B1 - 0.02 0.06 GPIO - 0.23 0.88 IOCONFIG - 0.03 0.10 I2C - 0.04 0.13 ROM - 0.04 0.15 SPI0 - 0.12 0.45 SPI1 - 0.12 0.45 UART - 0.22 0.82 WDT/WWDT - 0.02 0.06 Main clock divided by 4 in the CLKOUTDIV register. GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. Main clock selected as clock source for the WDT. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 84 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.10 Electrical pin characteristics 002aah548 3.6 T = 105°C 85 °C 25 °C -40 °C VOH (V) 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 36. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aah549 60 T = 105°C 85 °C 25 °C -40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 37. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 85 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah550 15 T = 105°C 85 °C 25 °C -40 °C IOL (mA) 10 5 0 0.2 0 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 38. Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aah551 3.6 VOH (V) T = 105 °C 85 °C 25 °C -40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 39. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 86 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah552 10 Ipu (μA) -10 -30 T = 105 °C 85 °C 25 °C -40 °C -50 -70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 40. Typical pull-up current Ipu versus input voltage VI 002aah547 80 T = 105 °C 85 °C 25 °C -40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 41. Typical pull-down current Ipd versus input voltage VI LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 87 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Dynamic characteristics 11.1 Power-up ramp conditions Table 22. Power-up characteristics[1] Tamb = 40 C to +85 C. Symbol Parameter tr rise time twait wait time VI input voltage Conditions Min at t = t1: 0 < VI 400 mV [2] [2][3] at t = t1 on pin VDD Typ Max Unit 0 - 500 ms 12 - - s 0 - 400 mV [1] Does not apply to the LPC1100XL series (LPC111x/103/203/303/323/333). [2] See Figure 42. [3] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up. tr VDD 400 mV 0 twait t = t1 002aag001 Condition: 0 < VI 400 mV at start of power-up (t = t1) Fig 42. Power-up ramp 11.2 Flash memory Table 23. Flash characteristics Tamb = 40 C to +105 C, unless otherwise specified. Tamb = 85 C for flash programming. Symbol Parameter LPC111X Product data sheet Conditions [1] Min Typ Max Unit 10000 100000 - cycles - years Nendu endurance tret retention time powered 10 - unpowered 20 - - years ter erase time sector or multiple consecutive sectors 95 100 105 ms tprog programming time 0.95 1 1.05 ms [2] [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Flash programming operation temperature must not exceed Tamb = 85 C. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 88 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.3 External clock Table 24. Dynamic characteristic: external clock Tamb = 40 C to +105 C; VDD over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Symbol Parameter fosc Conditions Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 43. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 89 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.4 Internal oscillators Table 25. Dynamic characteristic: internal oscillators Tamb = 40 C to +105 C; 2.7 V  VDD  3.6 V.[1] Symbol Parameter Conditions fosc(RC) internal RC oscillator frequency - Min Typ[2] Max Unit 11.88 12 12.12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 002aaf403 12.15 f (MHz) 12.05 VDD = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V 11.95 11.85 −40 −15 10 35 60 85 temperature (°C) Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 44. Internal RC oscillator frequency versus temperature (F parts) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 90 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah597 12.15 fosc(RC) (MHz) 12.1 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V 12.05 12 11.95 11.9 11.85 -50 -10 30 70 temperature (°C) 110 Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb = 40 C to +105 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 45. Internal RC oscillator frequency versus temperature (J parts) LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 91 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 26. Dynamic characteristics: Watchdog oscillator Min Typ[1] Max Unit internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; [2][3] - 9.4 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 2300 - kHz Symbol Parameter fosc(int) Conditions [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %. [3] See the LPC111x user manual. 11.5 I/O pins Table 27. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +105 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] LPC111X Product data sheet Applies to standard port pins and RESET pin. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 92 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.6 I2C-bus Table 28. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [4][5][6][7] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Standard-mode tLOW tHIGH tHD;DAT tSU;DAT [1] LOW period of the SCL clock HIGH period of the SCL clock data hold time data set-up time [3][4][8] [9][10] Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 93 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 46. I2C-bus pins clock timing 11.7 SPI interfaces Table 29. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit - - ns - - SPI master (in SPI mode) Tcy(clk) full-duplex mode [1] 50 when only transmitting [1] 40 in SPI mode [2] 15 2.0 V  VDD < 2.4 V [2] 20 1.8 V  VDD < 2.0 V [2] 24 - - ns in SPI mode [2] 0 - - ns data output valid time in SPI mode [2] - - 10 ns data output hold time in SPI mode [2] 0 - - ns clock cycle time data set-up time tDS ns ns 2.4 V  VDD  3.6 V data hold time tDH tv(Q) th(Q) ns SPI slave (in SPI mode) Tcy(PCLK) PCLK cycle time data set-up time tDS 20 - - ns in SPI mode [3][4] 0 - - ns tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - ns tv(Q) data output valid time in SPI mode [3][4] - - 3  Tcy(PCLK) + 11 ns th(Q) data output hold time in SPI mode [3][4] - - 2  Tcy(PCLK) + 5 ns [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = 40 C to 105 C. [3] Tcy(clk) = 12  Tcy(PCLK). [4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V. LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 94 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI DATA VALID th(Q) DATA VALID tDH tDS MISO DATA VALID CPHA = 1 CPHA = 0 DATA VALID 002aae829 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 47. SPI master timing in SPI mode LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 95 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 48. SPI slave timing in SPI mode LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 96 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Application information 12.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 18: • The ADC input trace must be short and as close as possible to the LPC1110/11/12/13/14/15 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered. • To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion. 12.2 Use of ADC input trigger signals For applications that use trigger signals to start conversions and require a precise sample frequency, ensure that the period of the trigger signal is an integral multiple of the period of the ADC clock. 12.3 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV (RMS) is needed. LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 49. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 49), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 50 and in Table 30 and Table 31. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 97 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 50 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 30). LPC1xxx L XTALIN XTALOUT CL = CP XTAL RS CX2 CX1 002aaf424 Fig 50. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 30. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF 5 MHz to 10 MHz Table 31. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF 20 MHz to 25 MHz LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 98 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.4 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of CX1 and CX2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 12.5 Standard I/O pad configuration Figure 51 shows the possible pin modes for standard I/O pins with analog input function: • • • • • • LPC111X Product data sheet Digital output driver Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Digital output: Pseudo open-drain mode enable/disabled Analog input All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 99 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller VDD VDD open-drain enable pin configured as digital output driver strong pull-up output enable ESD data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable weak pull-down repeater mode enable pin configured as digital input pull-down enable data input select analog input pin configured as analog input analog input 002aah159 Open-drain mode available on series LPC1100L and LPC1100XL. Fig 51. Standard I/O pad configuration 12.6 Reset pad configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 52. Reset pad configuration LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 100 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.7 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1114FBD48/302 in Table 32. Table 32. ElectroMagnetic Compatibility (EMC) for part LPC1114FBD48/302 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C. Parameter Frequency band System clock = Unit 12 MHz 24 MHz 48 MHz 150 kHz to 30 MHz 7 5 7 dBV 30 MHz to 150 MHz 2 1 10 dBV 150 MHz to 1 GHz 4 8 16 dBV - O N M - 7 7 dBV Input clock: IRC (12 MHz) maximum peak level IEC level[1] Input clock: crystal oscillator (12 MHz) maximum peak level IEC level[1] [1] LPC111X Product data sheet 150 kHz to 30 MHz 7 30 MHz to 150 MHz 2 1 8 dBV 150 MHz to 1 GHz 4 7 14 dBV - O N M - IEC levels refer to Appendix D in the IEC61967-2 Specification. All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 101 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.8 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure 53. ADC Block Source ADC COMPARATOR Rmux Rsw LPC111X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9.2 — 26 March 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 126 of 127 LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.8 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 ADC effective input impedance . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 103 112 120 120 121 124 124 124 124 125 125 126 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 March 2014 Document identifier: LPC111X