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LPC1114LVFHN24/303

LPC1114LVFHN24/303

  • 厂商:

    NXP(恩智浦)

  • 封装:

    VFQFN24_EP

  • 描述:

    IC MCU 32BIT 32KB FLASH 24HVQFN

  • 数据手册
  • 价格&库存
LPC1114LVFHN24/303 数据手册
LPC111xLV/LPC11xxLVUK 32-bit ARM Cortex-M0 MCU; up to 32 kB flash, 8 kB SRAM; 8-bit ADC Rev. 2 — 10 October 2012 Product data sheet 1. General description The LPC111xLV/LPC11xxLVUK is an ARM Cortex-M0-based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC111xLV/LPC11xxLVUK operate at CPU frequencies of up to 50 MHz. The peripherals of the LPC111xLV/LPC11xxLVUK include up to 32 kB of flash memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I2C-bus interface, one SSP/SPI interface, one UART, four general-purpose counter/timers, an 8-bit ADC, and up to 27 general-purpose I/O pins. 2. Features and benefits  System:  ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.  ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).  Serial Wire Debug.  System tick timer.  Memory:  Up to 32 kB on-chip flash programming memory with a 256 byte page erase function.  Up to 8 kB SRAM.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.  Digital peripherals:  Up to 27 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors and a configurable open-drain mode.  GPIO pins can be used as edge and level sensitive interrupt sources.  High-current output driver on one pin.  High-current sink drivers on two I2C-bus pins in Fast-mode Plus.  Four general-purpose counter/timers with up to 7 capture inputs and 13 match outputs.  Programmable windowed WDT.  Analog peripherals: 8-bit ADC with input multiplexing among up to 8 pins.  Serial interfaces: LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller       UART with fractional baud rate generation and internal FIFO.  One SPI controller with SSP features and with FIFO and multi-protocol capabilities.  I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. Clock generation:  12 MHz internal RC oscillator trimmed to 2.5 % accuracy for Tamb = -20 °C to +85 °C and to 5 % accuracy for Tamb = -40 °C to -20 °C. The IRC can optionally be used as a system clock.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.  Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. Power control:  Two reduced power modes: Sleep and Deep-sleep mode.  Ultra-low power consumption in Deep-sleep mode ( 1.6 A).  5 s wake-up time from Deep-sleep mode.  Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins.  Power-On Reset (POR).  Brown-Out Detection (BOD) causing a forced reset. Unique device serial number for identification. Single power supply (1.65 V to 1.95 V) Available as WLCSP25, HVQFN24, and HVQFN33 package. Other package options are available for high-volume customers. 3. Applications  Mobile phones  Mobile accessories  Cameras  Tablets/Ultra books  Active cables  Portable medical electronics 4. Ordering information Table 1. Ordering information Type number Package Name Description Version WLCSP25 wafer level chip-size package; 25 bumps; 2.17  2.32  0.56 mm - LPC1102LVUK WLCSP25 wafer level chip-size package; 25 bumps; 2.17  2.32  0.56 mm - LPC1112LVFHN24/003 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-3 LPC1114LVFHN24/103 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-3 LPC1101LVUK LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 2 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 1. Ordering information …continued Type number Package Name Description Version LPC1114LVFHN24/303 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-3 LPC1112LVFHI33/103 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC1114LVFHI33/303 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a 4.1 Ordering options Table 2. LPC111XLV_LPC11XXLVUK Product data sheet Ordering options Type number Flash Total SPI/ in kB SRAM in SSP kB I2C UART ADC GPI O pins Package LPC1101LVUK 32 2 1 1 1 6-channel 21 WLCSP25 LPC1102LVUK 32 8 1 1 1 6-channel 21 WLCSP25 LPC1112LVFHN24/003 16 2 1 1 1 6-channel 20 HVQFN24 LPC1114LVFHN24/103 32 4 1 1 1 6-channel 20 HVQFN24 LPC1114LVFHN24/303 32 8 1 1 1 6-channel 20 HVQFN24 LPC1112LVFHI33/103 16 4 1 1 1 8-channel 27 HVQFN33 LPC1114LVFHI33/303 32 8 1 1 1 8-channel 27 HVQFN33 All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 3 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5. Block diagram XTALIN XTALOUT RESET SWD LPC110xLVUK LPC111xLV IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS POR ARM CORTEX-M0 clocks and controls FLASH 16/32 kB system bus slave GPIO ports HIGH-SPEED GPIO CLKOUT SRAM 2/4/8 kB slave ROM slave slave AHB-LITE BUS slave AHB TO APB BRIDGE RXD TXD DSR(3), RTS, CTS(3), DTR(3) CT32B0_MAT[3:0] CT32B0_CAP0 CT32B1_MAT[3:0] CT32B1_CAP[1:0](1) CT16B0_MAT[2:0] CT16B0_CAP[1:0](1) CT16B1_MAT[1:0](1) CT16B1_CAP[1:0](1) 10-bit/8-bit ADC(2) UART AD[7:0] SCK0, SSEL0 MISO0, MOSI0 SPI0 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 SCL SDA I2C-BUS 16-bit COUNTER/TIMER 0 WWDT 16-bit COUNTER/TIMER 1 IOCON SYSTEM CONTROL 002aag851 (1) CT16B1_MAT1, CT32B1_CAP1, CT1B0_CAP1, CT16B1_CAP1 available on HVQFN33 only. CT16B1_MAT0 available on HVQFN33 and WLCSP25 packages only. (2) 6 channels on WLCSP25 and HVQFN24 packages. 8 channels on HVQFN33 packages. (3) DSR on WLCSP25 package only. DTR on HVQFN33 package only. CTS on HVQFN24 and HVQFN33 packages only. Fig 1. LPC111xLV/LPC11xxLVUK block diagram LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 4 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 6.1 Pinning ball A1 index area LPC1101/02LVUK 1 2 3 4 5 A B C D E 002aag852 Transparent top view Fig 2. LPC111XLV_LPC11XXLVUK Product data sheet Pin configuration WLCSP25 package All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 5 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 19 SWDIO/PIO1_3/AD4/CT32B1_MAT2 20 PIO1_4/AD5/CT32B1_MAT3 21 VSS 22 VDD terminal 1 index area 23 PIO1_5/RTS/CT32B0_CAP0 24 PIO1_6/RXD/CT32B0_MAT0 32-bit ARM Cortex-M0 microcontroller 14 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 6 13 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_8/MISO0/CT16B0_MAT0 12 5 PIO0_7/CTS 11 15 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT PIO0_6/SCK0 10 4 9 16 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN PIO0_5/SDA 3 8 17 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 7 18 R/PIO1_2/AD3/CT32B1_MAT1 2 PIO0_4/SCL 1 RESET/PIO0_0 PIO0_2/SSEL0/CT16B0_CAP0 PIO1_7/TXD/CT32B0_MAT1 002aag849 Transparent top view For parts LPC1112LVFHN24/003, LPC1114LVFHN24/103, LPC1114LVFHN24/303. Fig 3. LPC111XLV_LPC11XXLVUK Product data sheet Pin configuration HVQFN24 package All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 6 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors PIO1_7/TXD/CT32B0_MAT1 PIO1_6/RXD/CT32B0_MAT0 PIO1_5/RTS/CT32B0_CAP0 VDD VDD(IO) PIO1_11/AD7/CT32B1_CAP1 PIO1_4/AD5/CT32B1_MAT3 SWDIO/PIO1_3/AD4/CT32B1_MAT2 31 30 29 28 27 26 25 terminal 1 index area 32 32-bit ARM Cortex-M0 microcontroller PIO2_0/DTR 1 24 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 3 22 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 4 21 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20 PIO1_10/AD6/CT16B1_MAT1 VDD(IO) 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 7 PIO0_2/SSEL0/CT16B0_CAP0 8 9 10 11 12 13 14 15 16 PIO0_3 PIO0_4/SCL PIO0_5/SDA PIO1_9/CT16B1_MAT0 PIO3_4/CT16B0_CAP1/RXD PIO3_5/CT16B1_CAP1/TXD PIO0_6/SCK0 PIO0_7/CTS 33 VSS 18 PIO0_9/MOSI0/CT16B0_MAT1 17 PIO0_8/MISO0/CT16B0_MAT0 002aag850 Transparent top view For parts LPC1112LVFHI33/103 and LPC1114LVFHI33/303. Fig 4. LPC111XLV_LPC11XXLVUK Product data sheet Pin configuration HVQFN33 package All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 7 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description RESET/PIO0_0 PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 PIO0_3 PIO0_4/SCL PIO0_5/SDA PIO0_6/SCK0 PIO0_7/CTS PIO0_8/MISO0/ CT16B0_MAT0 PIO0_9/MOSI0/ CT16B0_MAT1 LPC111XLV_LPC11XXLVUK Product data sheet HVQFN33 Symbol HVQFN24 LPC110xLVUK/LPC111xLV pin description table WLCSP25 Table 3. D1 2 2 C3 B2 A2 A3 A4 - A5 B5 3 7 8 9 10 11 12 13 3 8 [2] [3] [3] Start logic input Type yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. yes yes Reset Description state [1] 9 [3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin. 10 [4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. 11 15 16 17 18 [4] [3] [3] [3] [3] yes yes yes yes yes O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 8 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 R/PIO0_11/ AD0/CT32B0_MAT3 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3 PIO1_5/RTS/ CT32B0_CAP0 PIO1_6/RXD/ CT32B0_MAT0 LPC111XLV_LPC11XXLVUK Product data sheet HVQFN33 Symbol HVQFN24 LPC110xLVUK/LPC111xLV pin description table WLCSP25 Table 3. B4 14 19 C5 C4 D5 D4 E5 D3 E2 D2 15 16 17 18 19 20 23 24 21 22 23 24 25 26 30 31 [3] [5] [5] [5] [5] [5] [5] [3] [3] Start logic input Type yes I I; PU SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCON block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCON block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCON block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCON block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I/O I; PU PIO1_5 — General purpose digital input/output pin. O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. yes yes no no no no no no Reset Description state [1] All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 9 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO1_7/TXD/ CT32B0_MAT1 PIO1_8/ CT16B1_CAP0 HVQFN33 Symbol HVQFN24 LPC110xLVUK/LPC111xLV pin description table WLCSP25 Table 3. E1 1 32 B1 PIO1_9/ CT16B1_MAT0 B3 PIO1_10/AD6/ CT16B1_MAT1 - PIO1_11/AD7/ CT32B0_MAT3 - PIO2_0/DTR PIO2_1/DSR A1 PIO3_4/ CT16B0_CAP1/RXD PIO3_5/ CT16B1_CAP1/TXD - 6 - - - - [3] 7 [3] 12 [3] 20 27 1 [5] [5] [3] - [3] 13 [3] 14 [3] Start logic input Type no I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. no no no no no no no Reset Description state [1] I/O I; PU PIO1_9 — General purpose digital input/output pin. O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. I/O I;PU PIO1_10 — General purpose digital input/output pin. I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O I;PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I/O I;PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O I; PU PIO2_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O I;PU PIO3_4 — General purpose digital input/output pin. I - CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. I - RXD — Receiver input for UART. I/O I;PU PIO3_5 — General purpose digital input/output pin. I - CT16B1_CAP1 — Capture input 1 for 16-bit timer 1. O - TXD — Transmitter output for UART. - - - 1.8 V supply voltage to the core, the external rail, and the ADC. Also used as the ADC reference voltage. no VDD E3 22 29; 6; 28 XTALIN C1 4 4 [6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT C2 5 5 [6] - O - Output from the oscillator amplifier. VSS E4 21 33 - - - Ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level 0; IA = inactive, no pull-up/down enabled. [2] See Figure 28 for the reset pad configuration. [3] Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 27). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [5] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as an ADC input, digital section of the pad is disabled (see Figure 27). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 10 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC111xLV/LPC11xxLVUK contains up to 32 kB of on-chip flash memory. The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages. Individual pages of 256 byte each can be erased using the IAP erase page command. 7.3 On-chip SRAM The LPC111xLV/LPC11xxLVUK contains up to 8 kB on-chip static RAM memory. 7.4 Memory map The LPC111xLV/LPC11xxLVUK incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 11 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC110xLVUK LPC111xLV 4 GB AHB peripherals 0x5020 0000 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 127-16 reserved 0xE000 0000 0x5004 0000 reserved 0x5020 0000 AHB peripherals 0x5000 0000 15-12 GPIO PIO3 11-8 GPIO PIO2 7-4 GPIO PIO1 3-0 GPIO PIO0 reserved APB peripherals 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 31-23 reserved 0x4005 C000 0x4008 0000 APB peripherals 1 GB 22 0x4000 0000 reserved 0x4005 8000 21-19 reserved 0x4004 C000 reserved 0x2000 0000 0.5 GB reserved 18 system control 17 IOCON 16 15 SPI0 flash controller 14 reserved 0x1FFF 4000 16 kB boot ROM 0x1FFF 0000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 13-10 reserved 0x4002 8000 reserved 0x1000 2000 8 kB SRAM LPC1114LV/303, LPC1102LVUK 0x1000 1000 4 kB SRAM LPC1114LV/103, LPC1112LV/103 0x1000 0800 2 kB SRAM LPC1101LVUK, LPC1112LV/003 0x1000 0000 reserved 0x0000 8000 32 kB on-chip flash LPC1101LVUK, LPC1102LVUK LPC1114LV 9 reserved 8 reserved 0x4002 0000 7 ADC 0x4001 C000 6 32-bit counter/timer 1 0x4001 8000 5 32-bit counter/timer 0 0x4001 4000 4 16-bit counter/timer 1 0x4001 0000 3 16-bit counter/timer 0 0x4000 C000 2 UART 0x4000 8000 1 0 WDT 0x4000 4000 I2C-bus 0x4000 0000 0x0000 4000 16 kB on-chip flash LPC1112LV 0 GB 0x4004 8000 0x4002 4000 0x0000 00C0 active interrupt vectors 0x0000 0000 0x0000 0000 002aag853 Fig 5. LPC111xLV/LPC11xxLVUK memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 12 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • In the LPC111xLV/LPC11xxLVUK, the NVIC supports 32 vectored interrupts including up to 13 inputs to the start logic from individual GPIO pins. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 18 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC111xLV/LPC11xxLVUK use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. • Entire port value can be written in one instruction. Additionally, any GPIO pin (total of up to 18 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features • Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. • Direction control of individual bits. • All I/O default to inputs with pull-ups enabled after reset with the exception of the I2C-bus pins PIO0_4 and PIO0_5. • Pull-up/pull-down resistor configuration can be programmed through the IOCON block for each GPIO pin (except for pins PIO0_4 and PIO0_5). • All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 1.8 V (VDD = 1.8 V) if their pull-up resistor is enabled in the IOCON block (single power supply). • Programmable open-drain mode. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 13 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.8 UART The LPC111xLV/LPC11xxLVUK contains one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features • • • • • Maximum UART data bit rate of 3.125 MBit/s. 16 Byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit mode. • Support for modem control. 7.9 SPI serial I/O controller The LPC111xLV/LPC11xxLVUK contains one SPI controller. The SPI controller is capable of operation on an SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full-duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.9.1 Features • Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame 7.10 I2C-bus serial I/O controller The LPC111xLV/LPC11xxLVUK contains one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 14 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 Features • The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s. • • • • • Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.11 ADC The LPC111xLV/LPC11xxLVUK contains one ADC. It is a single 8-bit successive approximation ADC with up to eight channels. Remark: ADC specifications are valid for Tamb = -40 °C to +85 °C on HVQFN33 and WLCSP25 packages. ADC specifications are valid for Tamb = -10 °C to 85 °C on the HVQFN24 package. 7.11.1 Features • • • • • • • • • LPC111XLV_LPC11XXLVUK Product data sheet 8-bit successive approximation ADC. Input multiplexing among 6 pins (WLCSP25 and HVQFN24 packages). Input multiplexing among 8 pins (HVQFN33 packages). Power-down mode. Measurement range 0 V to VDD. 8-bit sampling rate of up to 10 kSamples/s. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or timer match signal. Individual result registers for each ADC channel to reduce interrupt overhead. All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 15 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.12 General purpose external event counter/timers The LPC111xLV/LPC11xxLVUK includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.12.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • Up to two capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 7.13 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.14 Windowed WatchDog Timer The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.14.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 16 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). This gives a wide range of potential timing choices of watchdog operation under different power conditions. 7.15 Clocking and power control 7.15.1 Crystal oscillators The LPC111xLV/LPC11xxLVUK include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC111xLV/LPC11xxLVUK will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 6 for an overview of the LPC111xLV/LPC11xxLVUK clock generation. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 17 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SYSTEM CLOCK DIVIDER AHB clock 0 (system) system clock 18 AHB clocks 1 to 18 (memories and peripherals) SYSAHBCLKCTRL[1:18] (AHB clock enable) IRC oscillator SPI0 PERIPHERAL CLOCK DIVIDER SPI0 UART PERIPHERAL CLOCK DIVIDER UART WWDT CLOCK DIVIDER WDT main clock watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator IRC oscillator SYSPLLCLKSEL (system PLL clock select) watchdog oscillator WDTUEN (WDT clock update enable) IRC oscillator system oscillator watchdog oscillator CLKOUTUEN (CLKOUT update enable) Fig 6. CLKOUT PIN CLOCK DIVIDER CLKOUT pin 002aag859 LPC111xLV/LPC11xxLVUK clock generation block diagram 7.15.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 2.5 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC111xLV/LPC11xxLVUK use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.15.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 18 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.15.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and temperature is 40 %. 7.15.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The PLL output frequency must be lower than 100 MHz. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.15.3 Clock output The LPC111xLV/LPC11xxLVUK features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.15.4 Wake-up process The LPC111xLV/LPC11xxLVUK begin operation at power-up by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.15.5 Power control The LPC111xLV/LPC11xxLVUK support a variety of power control features. There are two special modes of processor power reduction: Sleep mode, and Deep-sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine-tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.15.5.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 19 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.15.5.2 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the IRC, the BOD, and the watchdog timer/watchdog oscillator running for self-timed wake-up. Deep-sleep mode allows for additional power savings. Up to 13 pins can serve as external wake-up pins to the start logic to wake up the chip from Deep-sleep mode. Unless the watchdog oscillator or the IRC are selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free. 7.16 System control 7.16.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in Table 3 as input to the start logic is connected to an individual interrupt in the NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is in Active mode. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down. The start logic must be configured in the system configuration block and in the NVIC before being used. 7.16.2 Reset Reset has four sources on the LPC111xLV/LPC11xxLVUK: the RESET pin, the Watchdog reset, the BrownOut Detection (BOD) circuit, and Power-On Reset (POR). The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.16.3 BrownOut Detection (BOD) The LPC111xLV/LPC11xxLVUK includes a BOD circuit which monitors the voltage level on the VDD pin. If this voltage falls below a fixed level (see Table 8), the BOD asserts a chip reset. 7.16.4 Code security (Code Read Protection - CRP) This feature of the LPC111xLV/LPC11xxLVUK allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details see the LPC111xLV user manual. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 20 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the UART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled (NO_ISP mode). For details see the LPC111xLV user manual. 7.16.5 APB interface The APB peripherals are located on one APB bus. 7.16.6 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.16.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs serve as external interrupts (see Section 7.16.1). 7.17 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 21 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions VDD supply voltage (core and external rail) input voltage VI only valid when the VDD supply voltage is present [2] Min Max Unit 1.65 1.95 V 0.5 +3.0 V 1.65 V  VDD < 1.8 V 0.5 +5.0 V IDD supply current per supply pin VDD  1.8 V - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); - 100 mA 65 +150 C - 150 C - 1.5 W 6500 +6500 V Tj < 125 C Tstg storage temperature Tj(max) maximum junction temperature Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption VESD electrostatic discharge voltage human body model; all pins [1] non-operating [3] [4] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Refer to the JEDEC spec (J-STD-033B.1) for further details. [4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 22 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics 9.1 Static characteristics Table 5. Static characteristics (single power supply Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) Conditions Min Typ[1] Max Unit 1.65 1.8 1.95 V - 2 - mA - 8 - mA - 0.8 - mA - 1.6 - A Power consumption IDD supply current Active mode; code while(1){} executed from flash system clock = 12 MHz [2][3][4] [5] VDD = 1.8 V system clock = 50 MHz VDD = 1.8 V Sleep mode; [2][3] [5][6] [2][3][4] [5] system clock = 12 MHz VDD = 1.8 V Deep-sleep mode; VDD = 1.8 V [2][3][7] Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function; VO output voltage output active VIH [8][9] VDD = 1.8 V 0 - 3.0 V 0 - VDD V HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 1.65 V  VDD  1.95 V; IOH = 3 mA VDD  0.4 - - V VOL LOW-level output voltage 1.65 V  VDD  1.95 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 3 - - mA IOL LOW-level output current VOL = 0.4 V 3 - - mA LPC111XLV_LPC11XXLVUK Product data sheet 1.65 V  VDD  1.95 V 1.65 V  VDD  1.95 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 23 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics (single power supply …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit - - 45 mA - - 50 mA IOHS HIGH-level short-circuit VOH = 0 V output current [10] IOLS LOW-level short-circuit output current VOL = VDD [10] Ipd pull-down current VI = 1.8 V (VDD = 1.8 V) 10 29 90 A Ipu pull-up current VI = 0 V; 3 13 85 A 0 0 0 A 1.65 V  VDD  1.95 V VDD < VI < 3.0 V High-drive output pin (PIO0_7) IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function; VO output voltage output active VIH [8][9] VDD = 1.8 V 0 - 3.0 V 0 - VDD V HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 1.65 V  VDD  1.95 V; IOH = 10 mA VDD  0.4 - - V VOL LOW-level output voltage 1.65 V  VDD  1.95 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 10 - - mA IOL LOW-level output current VOL = 0.4 V 3 - - mA IOLS LOW-level short-circuit output current VOL = VDD - - 50 mA Ipd pull-down current VI = 1.8 V 10 29 90 A Ipu pull-up current VI = 0 V; 3 13 85 A 0 0 0 A 1.65 V  VDD  1.95 V 1.65 V  VDD  1.95 V [10] 1.65 V  VDD  1.95 V VDD < VI < 3.0 V LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 24 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics (single power supply …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter I2C-bus pins (PIO0_4 and PIO0_5) Conditions Min Typ[1] Max Unit VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V 2.5 - - mA 15 - - mA - 2 4 A LOW-level output current IOL I2C-bus VOL = 0.4 V; pins configured as standard mode pins 1.65 V  VDD  1.95 V IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as Fast-mode Plus pins ILI input leakage current VI = VDD 1.65 V  VDD  1.95 V; [11] Oscillator pins Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Tamb = 25 C. [3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. BOD disabled for all measurements. [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0 disabled in system configuration block. [6] IRC disabled; system oscillator enabled; system PLL enabled. [7] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [8] Including voltage on outputs in 3-state mode. [9] VDD supply voltage must be present. [10] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] To VSS. 9.1.1 Analog characteristics Remark: ADC specifications are valid for Tamb = -40 °C to +85 °C on HVQFN33 and WLCSP25 packages. ADC specifications are valid for Tamb = -10 °C to +85 °C on the HVQFN24 package. Table 6. 8-bit ADC static characteristics Tamb = 40 C to +85 C for HVQFN33 and WLCSP25 packages. Tamb = 10 C to +85 C for the HVQFN24 package. VDD = 1.8 V  5 %; 8-bit resolution. Symbol Parameter VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF DNL differential non-linearity [1][2] - - 1 LSB integral non-linearity [3] - -  1.5 LSB offset error [4] - - 1 LSB INL EO LPC111XLV_LPC11XXLVUK Product data sheet Min All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 Typ Max Unit © NXP B.V. 2012. All rights reserved. 25 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. 8-bit ADC static characteristics …continued Tamb = 40 C to +85 C for HVQFN33 and WLCSP25 packages. Tamb = 10 C to +85 C for the HVQFN24 package. VDD = 1.8 V  5 %; 8-bit resolution. Symbol LPC111XLV_LPC11XXLVUK Product data sheet Parameter [5] Min Typ Max Unit - - 2 LSB EG gain error fclk(ADC) ADC clock frequency - - 110 kHz fs sampling rate - - 10 kSamples/s Rvsi voltage source interface resistance - - 40 k Ri input resistance - - 2.5 M [6][7] [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 7. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 7. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 7. [6] Tamb = 25 C; maximum sampling frequency fs = 10 kSamples/s and analog input capacitance Cia = 1 pF. [7] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia). All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 26 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 255 254 253 252 251 250 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 250 251 252 253 254 255 256 VIA (LSBideal) offset error EO 1 LSB = VDD - VSS 256 002aag903 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 27 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.2 Electrical pin characteristics 002aah391 2 VOH (V) -40 °C + 25 °C + 85 °C 1.8 1.6 1.4 1.2 0 4 8 12 16 20 IOH (mA) Conditions: high-drive pin PIO0_7; VDD = 1.8 V. Fig 8. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aah392 30 -40 °C + 25 °C + 85 °C IOL (mA) 24 18 12 6 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: I2C-bus pins PIO0_4 and PIO0_5; VDD = 1.8 V; configured for Fast mode plus in the IOCON PIO0_4 and PIO0_5 registers. Fig 9. LPC111XLV_LPC11XXLVUK Product data sheet I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 28 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah387 2 VOH (V) 1.8 -40 °C + 25 °C + 85 °C 1.6 1.4 1.2 0 1 2 3 4 5 IOH (mA) 6 Conditions: standard port pins; VDD = 1.8 V. Fig 10. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aah388 8 IOL (mA) -40 °C +25 °C + 85 °C 6 4 2 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: standard port pins; VDD = 1.8 V. Fig 11. Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 29 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah394 10 Ipu p (μA) 5 +85 °C +25 °C -40 °C 0 -5 -10 -15 -20 0 0.6 1.2 1.8 2.4 3 3.6 VI (V) Conditions: standard port pins; VDD = 1.8 V. Fig 12. Typical pull-up current Ipu versus input voltage VI 002aah393 40 Ipd p (μA) 32 -40 °C +25 °C +85 °C 24 16 8 0 0 0.6 1.2 1.8 2.4 3 3.6 VI (V) Conditions: standard port pins; VDD = 1.8 V. Fig 13. Typical pull-down current Ipd versus input voltage VI LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 30 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.3 Power consumption 002aah297 1 IDD (mA) 6 MHz 0.8 0.6 4 MHz 0.4 2 MHz 0.2 0 1.65 1.7 1.75 1.8 1.85 1.9 VDD (V) 1.95 Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; System oscillator, system PLL, IRC, BOD disabled; system clock provided by external clock. Fig 14. Active mode (2 MHz to 6 MHz): Typical supply current IDD versus supply voltage VDD for different clock frequencies 002aah296 1 IDD (mA) 6 MHz 0.8 0.6 4 MHz 0.4 2 MHz 0.2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD = 1.8 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; System oscillator, system PLL, IRC, BOD disabled; system clock provided by external clock. Fig 15. Active mode (2 MHz to 6 MHz): Typical supply current IDD versus temperature for different clock frequencies LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 31 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah299 8 IDD (mA) 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 1.65 1.7 1.75 1.8 1.85 1.9 VDD (V) 1.95 Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 16. Active mode: Typical supply current IDD versus supply voltage for different system clock frequencies 002aah298 8 IDD (mA) 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD = 1.8 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 17. Active mode: Typical supply current IDD versus temperature for different system clock frequencies LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 32 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag770 0.6 6 MHz IDD (mA) 4 MHz 0.5 2 MHz 0.4 0.3 1.65 1.75 1.85 1.95 VDD (V) Conditions: Tamb = 25 C; Sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; System oscillator and system PLL disabled; IRC disabled; system clock provided by external clock. Fig 18. Sleep mode (2 MHz to 6 MHz): Typical supply current IDD versus supply voltage VDD for different clock frequencies 002aag769 3 48 MHz(2) IDD (mA) 36 MHz(2) 2 24 MHz(2) 12 MHz(1) 1 0 1.65 1.75 1.85 1.95 VDD (V) Conditions: Tamb = 25 C; Sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 19. Sleep mode (12 MHz to 48 MHz): Typical supply current IDD versus supply voltage VDD for different clock frequencies LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 33 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah295 3 IDD (mA) 2.5 48 MHz(2) 36 MHz(2) 2 1.5 24 MHz(2) 1 12 MHz(1) 0.5 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: Tamb = 25 C; VDD = 1.8 V; Sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 20. Sleep mode (12 MHz to 48 MHz): Typical supply current IDD versus temperature for different clock frequencies 002aah294 15 IDD (μA) 12 9 6 1.95 V 1.8 V 1.65 V 3 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 21. Deep-sleep mode: Typical supply current IDD versus temperature LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 34 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.4 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz. Table 7. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.26 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.18 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.004 - - System oscillator running; PLL off; independent of main clock frequency. Main PLL - 0.061 - ADC - 0.08 0.29 CLKOUT - 0.18 0.45 CT16B0 - 0.02 0.06 CT16B1 - 0.02 0.06 CT32B0 - 0.02 0.07 CT32B1 - 0.02 0.06 GPIO - 0.23 0.88 IOCON - 0.03 0.10 I2C - 0.04 0.13 ROM - 0.04 0.15 SPI0 - 0.12 0.45 UART - 0.22 0.82 WWDT - 0.02 0.06 Main clock divided by 4 in the CLKOUTDIV register. GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. Main clock selected as clock source for the WWDT. 9.5 BOD static characteristics Table 8. BOD static characteristics Tamb = 25 C. LPC111XLV_LPC11XXLVUK Product data sheet Symbol Parameter Conditions Min Typ Max Unit Vth threshold voltage reset level 0 assertion - 1.46 - V de-assertion - 1.63 - V All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 35 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min [1] Nendu endurance tret retention time ter erase time tprog programming time Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.05 ms [2] [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock Table 10. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Symbol Parameter fosc Conditions Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 22. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 36 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.3 Internal oscillators Table 11. Dynamic characteristic: internal oscillators VDD 1.65V to 1.95 V. Symbol Parameter Conditions internal RC oscillator frequency fosc(RC) Typ[2] Max Min Unit -20 C  Tamb  +85 C 12 - 2.5 % 12 12 + 2.5 % MHz -40 C  Tamb < -20 C 12 + 5 % 12 - 5 % 12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 002aah435 12.6 f (MHz) VDD = 1.95 V VDD = 1.8 V VDD = 1.65 V 12.3 12 11.7 11.4 -40 -15 10 35 60 temperature (°C) 85 Fig 23. Typical internal RC oscillator frequency for different supply voltages VDD Table 12. Dynamic characteristics: Watchdog oscillator Min Typ[1] Max Unit internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; [2][3] - 9.4 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 2300 - kHz Symbol Parameter fosc(int) Conditions [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %. [3] See the LPC111xLV user manual. 10.4 I2C-bus Table 13. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] LPC111XLV_LPC11XXLVUK Product data sheet Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 37 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 13. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol tf Parameter [4][5][6][7] fall time Conditions Min Max Unit of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Standard-mode tLOW tHIGH tHD;DAT tSU;DAT LOW period of the SCL clock HIGH period of the SCL clock data hold time data set-up time [3][4][8] [9][10] Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 38 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 24. I2C-bus pins clock timing 10.5 SPI interface Table 14. Symbol Dynamic characteristics of SPI pins in SPI mode Parameter Conditions Min Typ Max Unit SPI master (in SPI mode) Tcy(clk) clock cycle time data set-up time tDS full-duplex mode [1] 50 - - ns when only transmitting [1] 40 - - ns in SPI mode [2] 24 - - ns 1.8 V  VDD < 1.95 V tDH data hold time in SPI mode [2] 0 - - ns tv(Q) data output valid time in SPI mode [2] - - 10 ns data output hold time in SPI mode [2] 0 - - ns th(Q) [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = 40 C to 85 C. LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 39 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI DATA VALID th(Q) DATA VALID tDH tDS MISO DATA VALID CPHA = 1 CPHA = 0 DATA VALID 002aae829 Fig 25. SPI master timing in SPI mode LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 40 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) tclk(H) tclk(L) tDS tDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 26. SPI slave timing in SPI mode LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 41 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6: • The ADC input trace must be short and as close as possible to the LPC111xLV/LPC11xxLVUK chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered. • To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion. 11.2 Standard I/O pad configuration Figure 27 shows the possible pin modes for standard I/O pins with analog input function: • • • • • LPC111XLV_LPC11XXLVUK Product data sheet Digital output driver with configurable open-drain output Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 42 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller VDD VDD open-drain enable pin configured as digital output driver strong pull-up output enable ESD data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable weak pull-down repeater mode enable pin configured as digital input pull-down enable data input 10 ns RC GLITCH FILTER select data inverter select glitch filter select analog input pin configured as analog input analog input 002aaf695 Fig 27. Standard I/O pad configuration 11.3 Reset pad configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 28. Reset pad configuration LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 43 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline WLCSP25: wafer level chip-size package; 25 bumps; 2.17 x 2.32 x 0.56 mm B D WLCSP25217X232 A ball A1 index area A2 A E A1 detail X e1 e C C A B C Øv Øw b y E e D e2 C B A ball A1 index area 1 2 3 4 5 X 0 2 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A2 b D E max 0.615 0.23 0.385 0.29 2.21 2.36 nom 0.560 0.20 0.360 0.26 2.17 2.32 min 0.505 0.17 0.335 0.23 2.13 2.28 e e1 e2 0.4 1.6 1.6 v w y 0.15 0.05 0.05 wlcsp25_217x232_po Outline version References IEC JEDEC JEITA European projection Issue date 11-05-04 12-02-13 WLCSP25217X232 Fig 29. Package outline (WLCSP25) LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 44 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm A B D SOT616-3 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 7 12 y y1 C v M C A B w M C b L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.1 3.9 2.75 2.45 4.1 3.9 2.75 2.45 0.5 2.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT616-3 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 04-11-19 05-03-10 Fig 30. Package outline (HVQFN24) LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 45 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B A terminal 1 index area A A1 E c detail X C e1 e 9 y1 C C A B C v w 1/2 e b y 16 L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 Dimensions (mm are the original dimensions) Unit(1) mm A(1) A1 b max 0.05 0.30 nom 0.85 min 0.00 0.18 c D(1) Dh E(1) Eh 5.1 3.75 5.1 3.75 0.2 4.9 5 mm scale 3.45 4.9 e e1 e2 0.5 3.5 3.5 L v w y y1 0.5 0.1 0.05 0.05 0.1 0.3 3.45 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC JEITA hvqfn33f_po European projection Issue date 11-10-11 11-10-17 MO-220 Fig 31. Package outline (HVQFN33) LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 46 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Soldering Footprint information for reflow soldering of HVQFN24 package SOT616-3 Hx Gx D P 0.025 0.025 C (0.105) SPx nSPx Hy SPy tot SPy Gy SLy nSPy By Ay SPx tot SLx Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area nSPx nSPy 2 2 Dimensions in mm P Ax Ay Bx By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy 0.500 5.000 5.000 3.200 3.200 0.900 0.240 2.500 2.500 1.500 1.500 0.550 0.550 4.300 4.300 5.250 5.250 Issue date 07-05-07 09-06-15 sot616-3_fr Fig 32. Reflow soldering for the HVQFN24 package LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 47 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of HVQFN33 package Hx Gx see detail X P nSPx By Hy Gy SLy Ay nSPy C D SLx Bx Ax 0.60 solder land 0.30 solder paste detail X occupied area Dimensions in mm P Ax Ay Bx By C D Gx Gy Hx Hy SLx SLy nSPx nSPy 0.5 5.95 5.95 4.25 4.25 0.85 0.27 5.25 5.25 6.2 6.2 3.75 3.75 3 3 Issue date 11-11-15 11-11-20 002aag766 Fig 33. Reflow soldering for the HVQFN33 (5x5) package LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 48 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations Table 15. LPC111XLV_LPC11XXLVUK Product data sheet Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD Brown-Out Detect GPIO General-Purpose Input/Output JEDEC Joint Electron Devices Engineering Council NVM Non-Volatile Memory PLL Phase-Locked Loop SPI Serial Peripheral Interface SSI Serial Synchronous Interface TTL Transistor-Transistor Logic USART Universal Synchronous Asynchronous Receiver/Transmitter All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 49 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC111XLV_LPC11XXLVUK v.2 20121010 Product data sheet - LPC111XLV_LPC11XXLVUK v.1 Modifications: LPC111XLV_LPC11XXLVUK v.1 LPC111XLV_LPC11XXLVUK Product data sheet • • • • • Functions CT16B0_CAP1/RXD added to pin PIO3_4. Functions CT16B1_CAP1/TXD added to pin PIO3_5. Function CT32B1_CAP1 added to pin PIO1_11. Capture/clear functionality added to counter/timers. See Section 7.12. Figure 21 “Deep-sleep mode: Typical supply current IDD versus temperature” updated. • Electrical pin characteristics data combined in Section 9.2 for dual and single power supplies. • SSP timing characteristics in slave mode removed for single power supply parts in Table 14. • • • Table 11 “Dynamic characteristic: internal oscillators” and Figure 23 updated. • • Removed 10-bit ADC. Only the 8-bit ADC is available. • • BOD interrupt level 0 removed in Table 8. • Data sheet status changed to Product data sheet. Figure 33 corrected. Removed dual-power supply option. All parts use a single 1.8 V +/- 10 % power supply. Temperature range for ADC characteristics on the HVQFN24 package restricted to Tamb = -10 °C to +85 °C. IRC accuracy updated to 2.5 % accuracy for Tamb = -20 °C to +85 °C and to 5 % accuracy for Tamb = -40 °C to -20 °C. 20120621 Objective data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 - © NXP B.V. 2012. All rights reserved. 50 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 16. Legal information 17. Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. LPC111XLV_LPC11XXLVUK Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 51 of 53 LPC111xLV/LPC11xxLVUK NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC111XLV_LPC11XXLVUK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 October 2012 © NXP B.V. 2012. All rights reserved. 52 of 53 NXP Semiconductors LPC111xLV/LPC11xxLVUK 32-bit ARM Cortex-M0 microcontroller 19. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.11 7.11.1 7.12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 11 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 11 On-chip flash program memory . . . . . . . . . . . 11 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 Nested Vectored Interrupt Controller (NVIC) . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 13 Fast general purpose parallel I/O . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 14 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C-bus serial I/O controller . . . . . . . . . . . . . . 14 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 16 7.14 Windowed WatchDog Timer . . . . . . . . . . . . . 16 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.15 Clocking and power control . . . . . . . . . . . . . . 17 7.15.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 17 7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 18 7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 18 7.15.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 19 7.15.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 19 7.15.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.5.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 20 7.16 System control . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.1 Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.3 BrownOut Detection (BOD) . . . . . . . . . . . . . . 20 7.16.4 Code security (Code Read Protection - CRP) 20 7.16.5 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.7 External interrupt inputs . . . . . . . . . . . . . . . . . 21 7.17 Emulation and debugging . . . . . . . . . . . . . . . 21 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Static characteristics . . . . . . . . . . . . . . . . . . . 23 9.1 Static characteristics . . . . . . . . . . . . . . . . . . . 23 9.1.1 Analog characteristics . . . . . . . . . . . . . . . . . . 25 9.2 Electrical pin characteristics. . . . . . . . . . . . . . 28 9.3 Power consumption . . . . . . . . . . . . . . . . . . . . 31 9.4 Peripheral power consumption . . . . . . . . . . . 35 9.5 BOD static characteristics . . . . . . . . . . . . . . . 35 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 36 10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 37 10.4 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 Application information . . . . . . . . . . . . . . . . . 42 11.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 42 11.2 Standard I/O pad configuration . . . . . . . . . . . 42 11.3 Reset pad configuration . . . . . . . . . . . . . . . . . 43 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 44 13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 50 16 Legal information . . . . . . . . . . . . . . . . . . . . . . 51 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 17.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 17.2 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 17.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 18 Contact information . . . . . . . . . . . . . . . . . . . . 52 19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 October 2012 Document identifier: LPC111XLV_LPC11XXLVUK
LPC1114LVFHN24/303 价格&库存

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