LPC112x
32-bit ARM Cortex-M0 microcontroller; 64 kB flash and 8 kB
SRAM; 12-bit ADC
Rev. 1 — 24 February 2015
Product data sheet
1. General description
The LPC112x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC112x operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC112x includes 64 kB of flash memory, 8 kB of data
memory, one Fast-mode Plus I2C-bus interface, three RS-485/EIA-485 UARTs, two SSP
interfaces, four general purpose counter/timers, a 12-bit ADC, and up to 38 general
purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) input selectable from several input sources.
Serial Wire Debug.
System tick timer.
Memory:
64 kB on-chip flash programming memory.
256 byte page erase function.
8 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Digital peripherals:
Up to 38 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors. A configurable open-drain mode is supported.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current output driver (20 mA) on one pin.
High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.
Four general purpose counter/timers with up to six capture inputs and up to 13
match outputs.
Programmable windowed WDT.
Analog peripherals:
12-bit ADC with 2 Msamples/s and eight channels.
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Serial interfaces:
Three UARTs with fractional baud rate generation, internal FIFO, and RS-485
support. One UART with modem control.
Two SSP controllers with FIFO and multi-protocol capabilities.
I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy for 25 C Tamb +85 C
that can optionally be used as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, and the Watchdog clock.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
13 of the functional pins.
Power-On Reset (POR).
Brownout detect with up to four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single power supply (1.8 V to 3.6 V).
Available as LQFP48 package.
3. Applications
eMetering
Alarm systems
Lighting
White goods
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
LPC1125JBD48/303
LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 SOT313-2
1.4 mm
LPC1124JBD48/303
LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 SOT313-2
1.4 mm
LPC112x
Product data sheet
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Rev. 1. — 24 February 2015
Version
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
Table 2.
Ordering options
Type number
Flash
Total
SRAM
UART
RS-485
I2C/
Fast+
SSP
ADC
channels
GPIO
Package
LPC1125JBD48/303
64 kB
8 kB
3
1
2
8
38
LQFP48
LPC1124JBD48/303
32 kB
8 kB
3
1
2
8
38
LQFP48
LPC112x
Product data sheet
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Rev. 1. — 24 February 2015
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
XTALIN
SWD
XTALOUT
CLOCK
GENERATION
POWER CONTROL,
SYSTEM
FUNCTIONS
IRC
LPC112x
POR
TEST/DEBUG
INTERFACE
RESET
CLKOUT
clocks and controls
ARM
CORTEX-M0
system
bus
GPIO ports
PIO0/1/2/3
HIGH-SPEED
GPIO
SRAM
8 kB
FLASH
64 kB
slave
ROM
slave
slave
slave
AHB-LITE BUS
slave
U0_RXD
U0_TXD
U0_DTR,
U0_DSR,
U0_CTS,
U0_DCD,
U0_RI, U0_RTS
U1_TXD
U1_RXD
AHB TO APB
BRIDGE
UART0
ADC_[8:1]
12-bit ADC
SSP0_SCK,
SSP0_SSEL,
SSP0_MISO,
SSP0_MOSI
SSP1_SCK,
SSP1_SSEL,
SSP1_MISO,
SSP1_MOSI
SSP0
UART1
SSP1
U2_TXD
U2_RXD
UART2
I2C0_SCL
I2C0_SDA
I2C
CT32B0_MAT[3:0]
CT32B0_CAP0
CT32B1_MAT[3:0]
CT32B1_CAP0
CT16B0_MAT[2:0]
CT16B0_CAP[1:0]
CT16B1_MAT[1:0]
CT16B1_CAP[1:0]
32-bit COUNTER/TIMER 0
WWDT
32-bit COUNTER/TIMER 1
IOCON
16-bit COUNTER/TIMER 0
SYSTEM CONTROL
16-bit COUNTER/TIMER 1
PMU
aaa-016082
Fig 1.
LPC112x block diagram
6. Pinning information
6.1 Pinning
LPC112x
Product data sheet
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LPC112x
NXP Semiconductors
25 PIO2_2
26 PIO0_8
27 PIO0_9
28 SWCLK/PIO0_10
29 PIO1_10
30 R/PIO0_11
31 R/PIO1_0
32 R/PIO1_1
33 VREFP
34 VREFN
35 R/PIO1_2
36 PIO3_0
32-bit ARM Cortex-M0 microcontroller
PIO2_3 37
24 PIO2_9
SWDIO/PIO1_3 38
23 PIO0_7
PIO1_4/WAKEUP 39
22 PIO0_6
VSSA 40
21 PIO3_5
VSS 41
20 PIO2_5
PIO1_11 42
19 PIO2_4
LPC112x
VDDA 43
PIO2_8 12
PIO0_2 10
PIO2_7 11
VDD 8
PIO1_8 9
13 PIO2_1
XTALIN 6
14 PIO0_3
PIO3_3 48
XTALOUT 7
PIO1_7 47
VSS 5
15 PIO0_4
PIO0_1 4
16 PIO0_5
PIO1_6 46
PIO2_0 2
PIO1_5 45
RESET/PIO0_0 3
17 PIO1_9
PIO2_6 1
Fig 2.
18 PIO3_4
VDD 44
aaa-016083
LQFP48 package
LPC112x
Product data sheet
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Rev. 1. — 24 February 2015
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3.
Pin description
Reset
state
LQFP48
Symbol
RESET/PIO0_0
PIO0_1
PIO0_2
PIO0_3
PIO0_4
PIO0_5
PIO0_6
PIO0_7
PIO0_8
LPC112x
Product data sheet
3
[8]
4
[6]
10
14
[6]
[6]
15
16
22
23
26
Type Description
[1]
Start
logic
wake-up
pin
I; PU
yes
I
RESET — External reset input: A LOW-going pulse as
short as 50 ns on this pin resets the device, causing
I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
I/O
PIO0_0 — General purpose port 0 input/output 0.
I/O
PIO0_1 — General purpose port 0 input/output 1. A
LOW level on this pin during reset starts the ISP
command handler.
O
CLKOUT — Clock output.
O
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
I/O
PIO0_2 — General purpose port 0 input/output 2.
I/O
SSP0_SSEL — Slave select for SSP0.
I
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
I
ADC_PIN_TRIG0 — ADC pin trigger input 0.
I/O
PIO0_3 — General purpose port 0 input/output 3.
-
R — Reserved.
-
R — Reserved.
I
U2_RXD — Receiver input for UART2.
I/O
PIO0_4 — General purpose port 0 input/output 4.
I/O
I2C0_SCL — I2C-bus, open-drain clock input/output.
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
I/O
PIO0_5 — General purpose port 0 input/output 5.
I/O
I2C0_SDA — I2C-bus, open-drain data input/output.
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
I/O
PIO0_6 — General purpose port 0 input/output 6.
-
R — Reserved.
I/O
SSP0_SCK — Serial clock for SSP0.
O
U1_TXD — Transmitter output for UART1.
I/O
PIO0_7 — General purpose port 0 input/output 7.
High-current output driver.
I
U0_CTS — Clear To Send input for UART0.
I
ADC_PIN_TRIG1 — ADC pin trigger input 1.
I
U1_RXD — Receiver input for UART1.
I; PU
I; PU
I; PU
I; IA
[7]
[6]
[5]
[6]
I; IA
I; PU
I; PU
I; PU
yes
yes
yes
yes
yes
yes
yes
yes
I/O
PIO0_8 — General purpose port 0 input/output 8.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
O
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
-
R — Reserved.
I
ADC_PIN_TRIG2 — ADC pin trigger input 2.
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Rev. 1. — 24 February 2015
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description
Reset
state
LQFP48
Symbol
PIO0_9
SWCLK/PIO0_10
R/PIO0_11
R/PIO1_0
R/PIO1_1
R/PIO1_2
SWDIO/PIO1_3
LPC112x
Product data sheet
27
28
30
31
32
35
38
[1]
[6]
[6]
[3]
[3]
[3]
[3]
[3]
I; PU
yes
I; PU
yes
I; PU
yes
I; PU
yes
O; PU
I; PU
I; PU
Start
logic
wake-up
pin
no
no
no
Type Description
I/O
PIO0_9 — General purpose port 0 input/output 9.
I/O
SSP0_MOSI — Master Out Slave In for SSP0.
O
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
-
R — Reserved.
I
ADC_PIN_TRIG3 — ADC pin trigger input 3.
I/O
SWCLK — Serial wire clock.
I/O
PIO0_10 — General purpose port 0 input/output 10.
I/O
SSP0_SCK — Serial clock for SSP0.
O
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I
R — Reserved. Configure for an alternate function in
the IOCON block.
I/O
PIO0_11 — General purpose port 0 input/output 11.
AI
ADC_7 — A/D converter, input 7.
O
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
I
R — Reserved. Configure for an alternate function in
the IOCON block.
I/O
PIO1_0 — General purpose port 1 input/output 0.
AI
ADC_6 — A/D converter, input 6.
I
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
O
R — Reserved. Configure for an alternate function in
the IOCON block.
I/O
PIO1_1 — General purpose port 1 input/output 1.
AI
ADC_5 — A/D converter, input 5.
O
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
I
R — Reserved. Configure for an alternate function in
the IOCON block.
I/O
PIO1_2 — General purpose port 1 input/output 2.
AI
ADC_4 — A/D converter, input 4.
O
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
I/O
SWDIO — Serial Wire Debug I/O. SWDIO is enabled
by default on this pin.
I/O
PIO1_3 — General purpose port 1 input/output 3.
AI
ADC_3 — A/D converter, input 3.
O
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
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Rev. 1. — 24 February 2015
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7 of 63
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description
Reset
state
LQFP48
Symbol
PIO1_4/
WAKEUP
PIO1_5
PIO1_6
PIO1_7
PIO1_8
PIO1_9
PIO1_10
PIO1_11
PIO2_0
PIO2_1
LPC112x
Product data sheet
39
45
46
47
9
17
29
42
2
13
[1]
[4]
[6]
[6]
[6]
[6]
[6]
[3]
[3]
[6]
[6]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
Start
logic
wake-up
pin
Type Description
no
IO
PIO1_4 — General purpose port 1 input/output 4.
General-purpose digital input/output pin. This pin also
serves as the Deep power-down mode wake-up pin
with 20 ns glitch filter. Pull this pin HIGH externally
before entering Deep power-down mode. Pull this pin
LOW to exit Deep power-down mode. A LOW-going
pulse as short as 50 ns wakes up the part.
AI
ADC_2 — A/D converter, input 2.
no
no
no
no
no
no
no
no
no
O
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
I/O
PIO1_5 — General purpose port 1 input/output 5.
O
U0_RTS — Request To Send output for UART0.
I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
I/O
PIO1_6 — General purpose port 1 input/output 6.
I
U0_RXD — Receiver input for UART0. In ISP mode,
connect to UART.
O
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
I/O
PIO1_7 — General purpose port 1 input/output 7.
O
U0_TXD — Transmitter output for UART0. In ISP
mode, connect to UART.
O
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
I/O
PIO1_8 — General purpose port 1 input/output 8.
I
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
-
R — Reserved.
O
U2_TXD — Transmitter output for U2.
I/O
PIO1_9 — General purpose port 1 input/output 9.
O
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I/O
SSP1_MOSI — Master Out Slave In for SSP1.I
I/O
PIO1_10 — General purpose port 1 input/output 10.
AI
ADC_8 — A/D converter, input 8.
O
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I/O
SSP1_MISO — Master In Slave Out for SSP1.
I/O
PIO1_11 — General purpose port 1 input/output 11.
AI
ADC_1 — A/D converter, input 1.
I
CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
IO
PIO2_0 — General purpose port 2 input/output 0.
O
U0_DTR — Data Terminal Ready output for UART0.
I/O
SSP1_SSEL — Slave Select for SSP1.
I
ADC_PIN_TRIG4 — ADC pin trigger input 4.
I/O
PIO2_1 — General purpose port 2 input/output 1.
I
U0_DSR — Data Set Ready input for UART0.
I/O
SSP1_SCK — Serial clock for SSP1.
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Rev. 1. — 24 February 2015
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8 of 63
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description
Reset
state
LQFP48
Symbol
PIO2_2
PIO2_3
PIO2_4
25
37
19
[1]
[6]
[6]
[6]
I; PU
I; PU
I; PU
Start
logic
wake-up
pin
no
no
no
20
[6]
PIO2_6
1
[6]
I; PU
no
PIO2_7
11
[6]
I; PU
no
PIO2_5
PIO2_8
12
[6]
I; PU
I; PU
no
no
Type Description
I/O
PIO2_2 — General purpose port 2 input/output 2.
I
U0_DCD — Data Carrier Detect input for UART0.
I/O
SSP1_MISO — Master In Slave Out for SSP1.
I/O
PIO2_3 — General purpose port 2 input/output 3.
I
U0_RI — Ring Indicator input for UART0.
I/O
SSP1_MOSI — Master Out Slave In for SSP1.
I/O
PIO2_4 — General purpose port 2 input/output 4.
O
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I/O
SSP1_SSEL — Slave Select for SSP1.
I/O
PIO2_5 — General purpose port 2 input/output 5.
O
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
I/O
PIO2_6 — General purpose port 2 input/output 6.
O
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
I/O
PIO2_7 — General purpose port 2 input/output 7.
O
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
I
U0_RXD — Receiver input for UART0.
I/O
PIO2_8 — General purpose port 2 input/output 8.
I
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
O
U0_TXD — Transmitter output for UART0.
I/O
PIO2_9 — General purpose port 2 input/output 9.
PIO2_9
24
[6]
I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO2_10
-
[6]
I: PU
no
I/O
PIO2_10 — General purpose port 2 input/output 10.
36
[6]
I; PU
no
I/O
PIO3_0 — General purpose port 3 input/output 0.
O
U0_DTR — Data Terminal Ready output for UART0.
O
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
O
U0_TXD — Transmitter Output for UART0.
I/O
PIO3_2 — General purpose port 3 input/output 2.
I
U0_DCD — Data Carrier Detect input for UART0.
O
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I/O
SSP1_SCK — Serial clock for SSP1.
I/O
PIO3_3 — General purpose port 3 input/output 3.
I
U0_RI — Ring Indicator input for UART0.
I
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
I/O
PIO3_4 — General purpose port 3 input/output 4.
I
CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.
I
U0_RXD — Receiver input for UART0.
PIO3_0
PIO3_2
PIO3_3
PIO3_4
PIO3_5
LPC112x
Product data sheet
-
48
18
21
[6]
[6]
[6]
[6]
I; PU
no
I; PU
I; PU
I; PU
I; PU
no
no
no
no
I/O
PIO3_5 — General purpose port 3 input/output 5.
I
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
O
U0_TXD — Transmitter output for UART0.
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Rev. 1. — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 63
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description
Reset
state
LQFP48
Symbol
[1]
Start
logic
wake-up
pin
Type Description
XTALIN
6
[2]
-
-
-
Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed
1.8 V.
XTALOUT
7
[2]
-
-
-
Output from the oscillator amplifier.
VREFP
33
-
-
-
Positive reference voltage for the ADC.
VREFN
34
-
-
-
Negative reference voltage for the ADC.
VDD
8;
44
-
-
-
3.3 V supply voltage to the internal regulator and the
external rail.
VDDA
43
-
-
-
Analog supply voltage.
VSSA
40
-
-
-
Analog ground.
VSS
5;
41
-
-
-
Ground.
[1]
Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD
level (VDD = 3.3 V)); IA = inactive, no pull-up/down enabled.
[2]
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 27).
[4]
Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When
configured as a ADC input, digital section of the pad is disabled (see Figure 27). In deep power-down mode, this pin serves as the
wake-up pin.
[5]
High-current output driver. Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis
(see Figure 27).
[6]
Standard digital I/O pin. Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
Figure 27).
[7]
I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires
an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[8]
5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 28 for the
reset pad configuration.
LPC112x
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1. — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 63
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7. Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.2 On-chip flash program memory
The LPC112x contain up to 64 kB of on-chip flash memory.
7.3 On-chip SRAM
The LPC112x contain a total of 8 kB on-chip static RAM memory.
7.4 Memory map
The LPC112x incorporate several distinct memory regions, shown in the following figures.
Figure 3 shows the overall map of the entire address space from the user program
viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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AHB peripherals
LPC112x
4 GB
0x5020 0000
0xFFFF FFFF
reserved
0xE010 0000
private peripheral bus
127-16 reserved
0xE000 0000
0x5004 0000
reserved
0x5020 0000
AHB peripherals
0x5000 0000
12-15
GPIO PIO3
8-11
GPIO PIO2
4-7
GPIO PIO1
0-3
GPIO PIO0
reserved
APB peripherals
0x5003 0000
0x5002 0000
0x5001 0000
0x5000 0000
0x4008 0000
31-23 reserved
0x4005 C000
0x4008 0000
APB peripherals
1 GB
SSP1
22
0x4000 0000
0x4005 8000
21-19 reserved
0x4004 C000
reserved
0x2000 0000
0.5 GB
reserved
18
system control
0x4004 8000
17
IOCON
0x4004 4000
16
SSP0
0x4004 0000
15
flash controller
14
PMU
0x4003 C000
0x4003 8000
0x1FFF 4000
16 kB boot ROM
13-10 reserved
0x1FFF 0000
0x4002 8000
reserved
0x1000 2000
8 kB SRAM
0x1000 0000
reserved
0x0001 0000
64 kB on-chip flash
(LPC1125)
9
UART2
0x4002 4000
8
UART1
0x4002 0000
7
12-bit ADC
0x4001 C000
6
32-bit counter/timer 1
0x4001 8000
5
32-bit counter/timer 0
0x4001 4000
4
16-bit counter/timer 1
0x4001 0000
3
16-bit counter/timer 0
0x4000 C000
2
UART0
0x4000 8000
1
WWDT
0x4000 4000
0
I2C-bus
0x4000 0000
0x0000 E000
32 kB on-chip flash
(LPC1124)
0x0000 00C0
active interrupt vectors
0x0000 0000
0 GB
Fig 3.
0x0000 0000
aaa-016174
LPC112x memory map
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
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• On the LPC112x, the NVIC supports 32 vectored interrupts including up to 13 inputs
to the start logic from individual GPIO pins.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 40 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
7.6 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.7 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC112x use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of 38 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.7.1 Features
• Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
• Direction control of individual bits.
• All I/O default to inputs with pull-ups enabled after reset with the exception of the
I2C-bus pins PIO0_4 and PIO0_5.
• Pull-up/pull-down resistor configuration can be programmed through the IOCON block
for each GPIO pin (except for pins PIO0_4 and PIO0_5).
• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their
pull-up resistor is enabled in the IOCON block.
• Programmable open-drain mode.
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7.8 UART
The LPC112x contain three UARTs.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.8.1 Features
•
•
•
•
•
Maximum UART data bit rate of 3.125 MBit/s.
16 Byte Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• FIFO control mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
7.9 SSP controller
The LPC112x contains two SSP controllers.
The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.9.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode).
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses.
•
•
•
•
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
4-bit to 16-bit frame.
7.10 I2C-bus serial I/O controller
The LPC112x contains one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
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capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.10.1 Features
• The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The
I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
•
•
•
•
•
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.11 Analog-to-Digital Converter (ADC)
The ADC supports a resolution of 12 bit and fast conversion rates of up to 2 Msamples/s.
Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible
trigger sources are internal connections to the 16-bit timer match outputs, five external
pins, and the ARM TXEV interrupt.
The ADC includes a hardware threshold compare function with zero-crossing detection.
7.11.1 Features
•
•
•
•
•
•
•
12-bit successive approximation analog to digital converter.
12-bit conversion rate of 2 Msamples/s.
Input multiplexing among 8 pins.
Two configurable conversion sequences with independent triggers.
Optional automatic high/low threshold comparison and zero-crossing detection.
Power-down mode and low-power operating mode.
Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage
level).
• Burst conversion mode for single or multiple inputs.
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7.12 General purpose external event counter/timers
The LPC112x include two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes up to two capture inputs to trap the
timer value when an input signal transitions, optionally generating an interrupt.
7.12.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
7.13 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.14 Windowed WatchDog Timer
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.14.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
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•
•
•
•
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). This gives a wide range of potential timing choices of
watchdog operation under different power conditions.
7.15 Clocking and power control
7.15.1 Crystal oscillators
The LPC112x include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC112x will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
See Figure 4 for an overview of the LPC112x clock generation.
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ARM
CORTEX-M0
SYSTEM CLOCK
DIVIDER
system clock
AHB clocks
1 to 18
(memories
and peripherals)
18
SYSAHBCLKDIV
SYSAHBCLKCTRL[1:18]
IRC oscillator
SSP0 PERIPHERAL
CLOCK DIVIDER
main clock
watchdog oscillator
UART0 PERIPHERAL
CLOCK DIVIDER
sys_pllclkin
UART0_PCLK
MAINCLKSEL
(main clock select)
SSP1 PERIPHERAL
CLOCK DIVIDER
sys_pllclkout
UART1 PERIPHERAL
CLOCK DIVIDER
UART1_PCLK
UART2 PERIPHERAL
CLOCK DIVIDER
UART2_PCLK
IRC oscillator
system oscillator
SSP0_PCLK
SSP1_PCLK
SYSTEM PLL
SYSPLLCLKSEL
(system PLL clock select)
IRC oscillator
WDT CLOCK
DIVIDER
WDCLK
watchdog oscillator
WDTUEN
(WDT clock update enable)
IRC oscillator
system oscillator
watchdog oscillator
CLKOUT PIN CLOCK
DIVIDER
CLKOUTUEN
(CLKOUT update enable)
Fig 4.
CLKOUT pin
aaa-016177
LPC112x clock generation block diagram
7.15.1.1
Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up or any chip reset, the LPC112x use the IRC as the clock source. Software
may later switch to one of the other available clock sources.
7.15.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
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7.15.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and
temperature is 40 %.
7.15.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The PLL
output frequency must be lower than 100 MHz. The output divider may be set to divide by
2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 s.
7.15.3 Clock output
The LPC112x features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.15.4 Wake-up process
The LPC112x begin operation at power-up and when awakened from Deep power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the system oscillator or the PLL is needed by the application,
software will need to enable these features and wait for them to stabilize before they are
used as a clock source.
7.15.5 Power control
The LPC112x support a variety of power control features. There are three special modes
of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down
mode. The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a
trade-off of power versus processing speed based on application requirements. In
addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
7.15.5.1
Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC112x for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
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• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.15.5.2
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.15.5.3
Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the watchdog oscillator and the
BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows
for additional power savings.
Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip
from Deep-sleep mode.
Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source
should be switched to IRC before entering Deep-sleep mode, because the IRC can be
switched on and off glitch-free.
7.15.5.4
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC112x can wake up from Deep power-down mode via the WAKEUP
pin.
A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
7.16 System control
7.16.1 Start logic
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin
shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt
vector table. The start logic pins can serve as external interrupt pins when the chip is
running. In addition, an input signal on the start logic pins can wake up the chip from
Deep-sleep mode when all clocks are shut down.
The start logic must be configured in the system configuration block and in the NVIC
before being used.
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7.16.2 Reset
Reset has four sources on the LPC112x: the RESET pin, the Watchdog reset, Power-On
Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
7.16.3 Brownout detection
The LPC112x includes up to four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC
in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register. Four threshold levels can be selected to cause a forced reset of
the chip.
7.16.4 Code security (Code Read Protection - CRP)
This feature of the LPC112x allows user to enable different levels of security in the system
so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and
In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC111x user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
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CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC112x user manual.
7.16.5 APB interface
The APB peripherals are located on one APB bus.
7.16.6 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
7.16.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see Section 7.16.1).
7.17 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
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8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Min
Max
Unit
supply voltage (core and external rail)
[2]
0.5
+4.6
V
VDDA
analog supply voltage
[2]
0.5
+4.6
V
Vref
reference voltage
0.5
+4.6
V
5 V tolerant I/O
pins; only valid
when the VDD
supply voltage is
present
[5][2]
0.5
+5.5
V
5 V tolerant
open-drain pins
PIO0_4 and
PIO0_5
[2][4]
0.5
+5.5
V
[2]
0.5
4.6
V
VDD
Parameter
Conditions
on pin VREFP
input voltage
VI
VIA
analog input voltage
pin configured as
analog input
[3]
IDD
supply current
per supply pin
-
100
mA
ISS
ground current
per ground pin
-
100
mA
Ilatch
I/O latch-up current
(0.5VDD) < VI <
(1.5VDD);
-
100
mA
65
+150
C
-
150
C
-
1.5
W
+6500
V
Tj < 125 C
Tstg
storage temperature
non-operating
Tj(max)
maximum junction temperature
Ptot(pack)
total power dissipation (per package)
based on package
heat transfer, not
device power
consumption
VESD
electrostatic discharge voltage
human body
model; all pins
[1]
[6]
[7]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 6.
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 6) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3]
See Table 6 for maximum operating voltage.
[4]
VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[5]
Including voltage on outputs in 3-state mode.
[6]
The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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32-bit ARM Cortex-M0 microcontroller
9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = T amb + P D R th j – a
(1)
• Tamb = ambient temperature (C)
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 5.
Thermal resistance value (C/W): ±15 %
LQFP48
ja
JEDEC (4.5 in 4 in)
0 m/s
82.1
1 m/s
73.7
2.5 m/s
68.2
8-layer (4.5 in 3 in)
LPC112x
Product data sheet
0 m/s
115.2
1 m/s
94.7
2.5 m/s
86.3
jc
29.6
jb
34.2
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
10. Static characteristics
Table 6.
Static characteristics
Tamb = 40 C to +105 C, unless otherwise specified.
Min
Typ[1]
Max
Unit
supply voltage (core
and external rail)
1.8
3.3
3.6
V
VDDA
analog supply voltage
2.4
3.3
3.6
V
Vref
reference voltage
2.4
-
VDDA
V
-
0.7
-
mA
-
1.0
-
mA
-
1.5
-
mA
-
6.0
-
mA
-
0.8
-
mA
-
2.4
-
mA
-
1.8
8
A
-
-
65
A
Symbol
Parameter
VDD
Power consumption in low-current
IDD
supply current
Conditions
on pin VREFP
mode[11]
Active mode; code
while(1){}
executed from flash
system clock = 1 MHz
[2][3][5][6][7]
VDD = 3.3 V
system clock = 6 MHz
[2][3][5]
[6][7]
VDD = 3.3 V
system clock = 12 MHz
[2][3][4]
[6][7]
VDD = 3.3 V
system clock = 50 MHz
[2][3][6]
[7][8]
VDD = 3.3 V
Sleep mode;
[2][3][4]
[6][7]
system clock = 12 MHz
VDD = 3.3 V
system clock = 50 MHz
[2][3][4]
[6][7]
VDD = 3.3 V
IDD
supply current
Deep-sleep mode;
VDD = 3.3 V;
[2][3][9]
Tamb = 25 C
Tamb = 105 C
IDD
supply current
Deep power-down mode;
VDD = 3.3 V;
[2][10]
Tamb = 25 C
-
220
900
nA
Tamb = 105 C
-
-
3.5
A
Standard port pins, RESET
IIL
LOW-level input
current
VI = 0 V; on-chip pull-up
resistor disabled
-
0.5
10[17]
nA
IIH
HIGH-level input
current
VI = VDD; on-chip
pull-down resistor
disabled
-
0.5
10[17]
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD;
on-chip pull-up/down
resistors disabled
-
0.5
10[17]
nA
VI
input voltage
pin configured to provide
a digital function;
VDD 1.8 V
0
-
5.0
V
LPC112x
Product data sheet
[12]
[14]
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VDD = 0 V
0
-
3.6
V
output active
0
-
VDD
V
VO
output voltage
VIH
HIGH-level input
voltage
0.7 VDD
-
-
V
VIL
LOW-level input
voltage
-
-
0.3VDD
V
Vhys
hysteresis voltage
-
0.4
VOH
HIGH-level output
voltage
-
V
2.5 V VDD 3.6 V;
IOH = 4 mA
VDD 0.4 -
-
V
1.8 V VDD < 2.5 V;
IOH = 3 mA
VDD 0.4 -
-
V
2.5 V VDD 3.6 V;
IOL = 4 mA
-
-
0.4
V
1.8 V VDD < 2.5 V;
IOL = 3 mA
-
-
0.4
V
HIGH-level output
current
VOH = VDD 0.4 V;
3
-
-
mA
LOW-level output
current
VOL = 0.4 V
3
-
-
mA
IOHS
HIGH-level
short-circuit output
current
VOH = 0 V
[15]
-
-
45
mA
IOLS
LOW-level
short-circuit output
current
VOL = VDD
[15]
-
-
50
mA
Ipd
pull-down current
VI = 5 V
10
50
150
A
Ipu
pull-up current
VI = 0 V;
15
50
85
A
10
50
85
A
VDD < VI < 5 V
0
0
0
A
VOL
IOH
IOL
LOW-level output
voltage
1.8 V VDD 3.6 V
1.8 V VDD 3.6 V
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
High-drive output pin (PIO0_7)
IIL
LOW-level input
current
VI = 0 V; on-chip pull-up
resistor disabled
-
0.5
10[17]
nA
IIH
HIGH-level input
current
VI = VDD; on-chip
pull-down resistor
disabled
-
0.5
10[17]
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD;
on-chip pull-up/down
resistors disabled
-
0.5
10[17]
nA
VI
input voltage
pin configured to provide
a digital function;
VDD 1.8 V
0
-
5.0
V
VDD = 0 V
0
-
3.6
V
output active
0
-
VDD
V
VO
LPC112x
Product data sheet
output voltage
[12]
[14]
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Min
Typ[1]
Max
Unit
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input
voltage
-
-
0.3VDD
V
Vhys
hysteresis voltage
0.4
-
-
V
VOH
HIGH-level output
voltage
2.5 V VDD 3.6 V;
IOH = 20 mA
VDD 0.5 -
-
V
1.8 V VDD < 2.5 V;
IOH = 12 mA
VDD 0.5 -
-
V
2.5 V VDD 3.6 V;
IOL = 4 mA
-
-
0.4
V
1.8 V VDD < 2.5 V;
IOL = 3 mA
-
-
0.4
V
VOH = VDD 0.5 V;
2.5 V VDD 3.6 V
20
-
-
mA
1.8 V VDD < 2.5 V
12
-
-
mA
VOL = 0.4 V
4
-
-
mA
3
-
-
mA
-
-
50
mA
Symbol
Parameter
VIH
LOW-level output
voltage
VOL
IOH
HIGH-level output
current
LOW-level output
current
IOL
Conditions
2.5 V VDD 3.6 V
1.8 V VDD < 2.5 V
[15]
IOLS
LOW-level
short-circuit output
current
VOL = VDD
Ipd
pull-down current
VI = 5 V
10
50
150
A
Ipu
pull-up current
VI = 0 V
15
50
85
A
10
50
85
A
0
0
0
A
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
VDD < VI < 5 V
I2C-bus
pins (PIO0_4 and PIO0_5)
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input
voltage
-
-
0.3VDD
V
Vhys
hysteresis voltage
-
0.05VDD
-
V
IOL
LOW-level output
current
3.5
-
-
mA
3
-
-
20
-
-
16
-
-
VOL = 0.4 V; I2C-bus pins
configured as standard
mode pins
2.5 V VDD 3.6 V
1.8 V VDD < 2.5 V
IOL
LOW-level output
current
I2C-bus
VOL = 0.4 V;
pins
configured as Fast-mode
Plus pins
mA
2.5 V VDD 3.6 V
1.8 V VDD < 2.5 V
LPC112x
Product data sheet
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
ILI
Parameter
input leakage current
Conditions
VI = VDD
VI = 5 V
[16]
Min
Typ[1]
Max
Unit
-
2
4
A
-
10
22
A
Oscillator pins
Vi(xtal)
crystal input voltage
0.5
1.8
1.95
V
Vo(xtal)
crystal output voltage
0.5
1.8
1.95
V
LPC112x
Product data sheet
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
input/output
capacitance
pins configured for analog
function
-
-
7.1
pF
I2C-bus pins (PIO0_4 and
PIO0_5)
-
-
2.5
pF
pins configured as GPIO
-
-
2.8
pF
Pin capacitance
Cio
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2]
Tamb = 25 C.
[3]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4]
IRC enabled; system oscillator disabled; system PLL disabled.
[5]
System oscillator enabled; IRC disabled; system PLL disabled.
[6]
BOD disabled.
[7]
All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SSP0/1 disabled in system configuration
block.
[8]
IRC disabled; system oscillator enabled; system PLL enabled.
[9]
All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.
[10] WAKEUP pin pulled HIGH externally.
[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[12] Including voltage on outputs in 3-state mode.
[13] VDD supply voltage must be present.
[14] 3-state outputs go into 3-state mode in Deep power-down mode.
[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To VSS.
[17] Characterized on samples. Not tested in production.
LPC112x
Product data sheet
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Rev. 1. — 24 February 2015
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
10.1 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC112x user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
aaa-016554
7
48MHz
36MHz
24MHz
12MHz
6MHz
1MHz
IDD
(mA)
6
4
3
1
0
-40
-10
20
50
80
Temperature (°C)
110
Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz - 48 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 5.
LPC112x
Product data sheet
Active mode: Typical supply current IDD versus temperature for different system
clock frequencies
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
aaa-016555
2.5
IDD
(mA)
48MHz
36MHz
24MHz
12MHz
6MHz
1MHz
2
1.5
1
0.5
0
-40
-10
20
50
80
Temperature (°C)
110
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz - 48 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 6.
LPC112x
Product data sheet
Sleep mode: Typical supply current IDD versus temperature for different system
clock frequencies
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
DDD
,''
$
9
9
9
7HPSHUDWXUH &
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 7.
Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD
DDD
,''
$
9
9
9
Fig 8.
7HPSHUDWXUH &
Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD
10.2 CoreMark data
Remark: All CoreMark data were taken with the Keil uVision v. 5.1.0 tool.
LPC112x
Product data sheet
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Rev. 1. — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
32 of 63
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
aaa-016556
2
CM
((iterations/s)/MHz)
1.6
1.2
0.8
CPU performance
Efficiency
Default
Low Power
0.4
0
0
10
20
30
40
Frequency (MHz)
50
VDD = 3.3 V; T = 25 °C; active mode; typical samples.
Fig 9.
CoreMark score for different Power API modes
aaa-016557
12
IDD
(mA)
10
Default
CPU performance
Efficiency
Low Power
8
6
4
2
0
0
10
20
30
40
Frequency (MHz)
50
VDD = 3.3 V; T = 25 °C; active mode; typical samples. System oscillator enabled; main clock
derived from external clock signal; PLL and SYSAHBCLKDIV enabled for frequencies > 20 MHz.
Fig 10. CoreMark current consumption for different power modes using external clock
LPC112x
Product data sheet
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
10.3 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
Table 7.
Power consumption for individual analog and digital blocks
Peripheral
LPC112x
Product data sheet
Typical supply current in
mA
Notes
n/a
12 MHz
48 MHz
IRC
0.212
-
-
System oscillator running; PLL off; independent
of main clock frequency.
System oscillator
at 12 MHz
0.1928
-
-
IRC running; PLL off; independent of main clock
frequency.
Watchdog
oscillator at
500 kHz/2
0.002
-
-
System oscillator running; PLL off; independent
of main clock frequency.
BOD
0.051
-
-
Independent of main clock frequency.
Main PLL
-
0.0686
-
ADC
-
0.0532
0.2074
CLKOUT
-
0.0104
0.0392
CT16B0
-
0.0266
0.1028
CT16B1
-
0.025
0.0956
CT32B0
-
0.026
0.0998
CT32B1
-
0.0246
0.0956
GPIO
-
0.2252
0.8754
IOCON
-
0.0324
0.1262
I2C
-
0.0384
0.1484
ROM
-
0.017
0.0658
SSP0
-
0.0482
0.187
SSP1
-
0.048
0.1862
UART0
-
0.0862
0.334
UART1
-
0.0836
0.3236
UART2
-
0.0818
0.3176
WWDT
-
0.039
0.1964
Main clock divided by 4 in the CLKOUTDIV
register.
GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
Main clock selected as clock source for the
WDT.
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
10.4 Electrical pin characteristics
aaa-013973
1.8
VOH
OL
(V)
1.7
aaa-013974
3.5
VOH
OL
(V)
3.2
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
1.6
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
2.9
1.5
2.6
1.4
2.3
1.3
1.2
2
0
4
8
12
16
20
IOH (mA)
24
Conditions: VDD = 1.8 V; on pin PIO0_7.
0
20
40
60
IOH (mA)
80
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 11. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH
aaa-013964
40
IOL
(mA)
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
30
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
45
20
30
10
15
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
Conditions: VDD = 1.8 V; on pins PIO0_4 and PIO0_5.
Fig 12.
aaa-013972
60
IOL
(mA)
I2C-bus
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage
VOL
LPC112x
Product data sheet
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
aaa-013975
10
IOL
(mA)
aaa-013976
15
IOL
(mA)
8
12
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
6
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
9
4
6
2
3
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
Conditions: VDD = 1.8 V; standard port pins and
high-drive pin PIO0_7.
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
Conditions: VDD = 3.3 V; standard port pins and
high-drive pin PIO0_7.
Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL
aaa-013977
1.8
VOH
(V)
1.7
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
aaa-013978
3.5
VOH
(V)
3.2
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
1.6
2.9
1.5
2.6
1.4
2.3
1.3
1.2
2
0
1.5
3
4.5
IOH (mA)
Conditions: VDD = 1.8 V; standard port pins.
6
0
8
16
IOH (mA)
24
Conditions: VDD = 3.3 V; standard port pins.
Fig 14. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH
LPC112x
Product data sheet
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Rev. 1. — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
36 of 63
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
aaa-013979
0
Ipu
(μA)
(uA)
aaa-013980
0
Ipu
(μA)
(uA)
-14
-4
-28
-40 °C
C
105 °C
C
90 °C
C
25 °C
C
-8
-42
105 °C
C
-40 °C
C
90 °C
C
25 °C
C
-12
-56
-16
-70
0
0.7
1.4
2.1
2.8
VI (V)
3.5
Conditions: VDD = 1.8 V; standard port pins.
0
1
2
3
4
VI (V)
5
Conditions: VDD = 3.3 V; standard port pins.
Fig 15. Typical pull-up current IPU versus input voltage VI
aaa-013981
35
Ipd
pu
(μA)
(uA)
aaa-013982
80
Ipd
(μA)
(uA)
28
60
21
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
14
-40 °C
C
25 °C
C
90 °C
C
105 °C
C
40
20
7
0
0
0
0.7
1.4
2.1
2.8
VI (V)
3.5
Conditions: VDD = 1.8 V; standard port pins.
0
1
2
3
4
VI (V)
5
Conditions: VDD = 3.3 V; standard port pins.
Fig 16. Typical pull-down current IPD versus input voltage VI
LPC112x
Product data sheet
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32-bit ARM Cortex-M0 microcontroller
11. Dynamic characteristics
11.1 Flash memory
Table 8.
Flash characteristics
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Nendu
endurance
tret
retention time
ter
erase time
tprog
programming
time
Conditions
Min
[1]
Typ
Max
Unit
10000
100000
-
cycles
powered
10
-
-
years
unpowered
20
-
-
years
sector or multiple
consecutive
sectors
95
100
105
ms
0.95
1
1.05
ms
[2]
[1]
Number of program/erase cycles.
[2]
Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
11.2 External clock
Table 9.
Dynamic characteristic: external clock
Tamb = 40 C to +105 C; VDD over specified ranges.[1]
Symbol
Parameter
Min
Typ[2]
Max
Unit
fosc
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk) 0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk) 0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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11.3 Internal oscillators
Table 10. Dynamic characteristics: IRC
Tamb = 40 C to +105 C; 2.7 V VDD 3.6 V[1].
Typ[2]
Max
Unit
12
12 + 1 %
MHz
40 C Tamb < 25 C 12 - 2.5 % 12
12 + 1 %
MHz
85 C < Tamb 105 C
12 + 1.5 % MHz
Symbol
Parameter
Conditions
Min
fosc(RC)
internal RC oscillator frequency
25 C Tamb +85 C 12 - 1 %
12 - 1.5 % 12
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply
voltages.
DDD
I
0+]
9
9
9
9
WHPSHUDWXUH &
Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for
2.7 V VDD 3.6 V and Tamb = 25 C to +85 C. Variations between parts may cause the IRC to
fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 18. Typical Internal RC oscillator frequency versus temperature
LPC112x
Product data sheet
Table 11.
Dynamic characteristics: WatchDog oscillator
Symbol
Parameter
Conditions
fosc(int)
internal oscillator
frequency
DIVSEL = 0x1F, FREQSEL = 0x1
in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
Min
Typ[1] Max Unit
[2][3]
-
9.4
-
kHz
[2][3]
-
2300
-
kHz
[1]
Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2]
The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.
[3]
See the LPC112x user manual.
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11.4 I/O pins
Table 12. Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +105 C; 3.0 V VDD 3.6 V.
Symbol
Parameter
Conditions
tr
rise time
tf
fall time
[1]
LPC112x
Product data sheet
Min
Typ
Max
Unit
pin configured 3.0
as output
-
5.0
ns
pin configured 2.5
as output
-
5.0
ns
Applies to standard port pins and RESET pin.
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11.5 I2C-bus
Table 13. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +105 C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock
frequency
Standard-mode
0
100
kHz
[4][5][6][7]
fall time
tf
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
of both SDA and
SCL signals
-
300
ns
Fast-mode
20 + 0.1 Cb
300
ns
Fast-mode Plus
-
120
ns
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
Standard-mode
4.0
-
s
Standard-mode
tLOW
tHIGH
tHD;DAT
tSU;DAT
[1]
LOW period of
the SCL clock
HIGH period of
the SCL clock
data hold time
data set-up
time
[3][4][8]
[9][10]
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
See the I2C-bus specification UM10204 for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF.
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement
tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must
meet this set-up time.
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32-bit ARM Cortex-M0 microcontroller
tf
SDA
tSU;DAT
70 %
30 %
70 %
30 %
tHD;DAT
tf
70 %
30 %
SCL
tVD;DAT
tHIGH
70 %
30 %
70 %
30 %
70 %
30 %
tLOW
S
1 / fSCL
002aaf425
Fig 19. I2C-bus pins clock timing
11.6 SSP interfaces
Table 14.
Dynamic characteristics of SSP pins in SPI mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
ns
-
-
SSP master (in SPI mode)
Tcy(clk)
full-duplex mode
[1]
50
when only transmitting
[1]
40
in SPI mode
[2]
20
2.0 V VDD < 2.4 V
[2]
25
1.8 V VDD < 2.0 V
[2]
29
-
-
ns
in SPI mode
[2]
0
-
-
ns
data output valid time in SPI mode
[2]
-
-
10
ns
data output hold time in SPI mode
[2]
0
-
-
ns
clock cycle time
data set-up time
tDS
ns
ns
2.4 V VDD 3.6 V
data hold time
tDH
tv(Q)
th(Q)
ns
SSP slave (in SPI mode)
Tcy(PCLK)
PCLK cycle time
data set-up time
tDS
20
-
-
ns
in SPI mode
[3][4]
0
-
-
ns
tDH
data hold time
in SPI mode
[3][4]
3 Tcy(PCLK) + 4
-
-
ns
tv(Q)
data output valid time in SPI mode
[3][4]
-
-
3 Tcy(PCLK) + 11
ns
th(Q)
data output hold time in SPI mode
[3][4]
-
-
2 Tcy(PCLK) + 5
ns
[1]
Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SSP bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = 40 C to 105 C.
[3]
Tcy(clk) = 12 Tcy(PCLK).
[4]
Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
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Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
tv(Q)
th(Q)
DATA VALID
MOSI
DATA VALID
tDS
DATA VALID
MISO
tDH
DATA VALID
tv(Q)
MOSI
th(Q)
DATA VALID
DATA VALID
tDH
tDS
MISO
CPHA = 1
DATA VALID
CPHA = 0
DATA VALID
002aae829
Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.
Fig 20. SSP master timing in SPI mode
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Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
tDS
MOSI
DATA VALID
tDH
DATA VALID
tv(Q)
MISO
th(Q)
DATA VALID
tDS
MOSI
DATA VALID
tDH
DATA VALID
tv(Q)
MISO
DATA VALID
CPHA = 1
DATA VALID
th(Q)
CPHA = 0
DATA VALID
002aae830
Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.
Fig 21. SSP slave timing in SPI mode
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12. Analog characteristics
12.1 BOD static characteristics
Table 15. BOD static characteristics[1]
Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage
interrupt level 1
assertion
-
2.22
-
V
de-assertion
-
2.35
-
V
assertion
-
2.52
-
V
de-assertion
-
2.66
-
V
assertion
-
2.80
-
V
de-assertion
-
2.90
-
V
assertion
-
1.46
-
V
de-assertion
-
1.63
-
V
assertion
-
2.06
-
V
de-assertion
-
2.15
-
V
assertion
-
2.35
-
V
de-assertion
-
2.43
-
V
assertion
-
2.63
-
V
de-assertion
-
2.71
-
V
interrupt level 2
interrupt level 3
reset level 0
reset level 1
reset level 2
reset level 3
[1]
LPC112x
Product data sheet
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x
user manual.
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12.2 12-bit ADC
Table 16. 12-bit ADC static characteristics
Tamb = 40 C to +105 C; VDD = 2.4 V to 3.6 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA.
Symbol
Parameter
Conditions
VIA
analog input voltage
Cia
analog input capacitance
fclk(ADC)
ADC clock frequency
fs
sampling frequency
Min
[1]
Typ
0
-
Max
Unit
VDDA
V
2.5
pF
VDDA 2.7 V
[8]
50
MHz
VDDA 2.4 V
[9]
25
MHz
VDDA 2.7 V
[8]
-
2
Msamples/s
VDDA 2.4 V
[9]
-
1
Msamples/s
ED
differential linearity error
[2]
-
+/- 2
-
LSB
EL(adj)
integral non-linearity
[3]
-
+/- 2
-
LSB
offset error
[4]
-
+/- 3
-
LSB
full-scale error voltage
[5]
-
+/- 0.12
-
%
+/- 0.07
-
%
-
M
EO
Verr(fs)
2 Msamples/s
1 Msamples/s
Zi
input impedance
LPC112x
Product data sheet
fs = 2 Msamples/s
[6][7]
0.1
[1]
The input resistance of ADC channel 0 is higher than for all other channels.
[2]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
See Figure 22.
[3]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 22.
[4]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 22.
[5]
The full-scale error voltage or gain error (EG) is the difference between the straight line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See
Figure 22.
[6]
Tamb = 25 C; maximum sampling frequency fs = 2 Msamples/s and analog input capacitance Cia = 0.32 pF.
[7]
Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including
Cia and Cio: Zi 1 / (fs Ci). See Table 6 for Cio.
[8]
In the ADC TRM register, set VRANGE = 0 (default).
[9]
In the ADC TRM register, set VRANGE = 1.
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offset
error
EO
gain
error
EG
4095
4094
4093
4092
4091
4090
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
4090
4091
4092
4093
4094
4095
4096
VIA (LSBideal)
offset error
EO
1 LSB =
VREFP - VREFN
4096
aaa-016908
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 22. 12-bit ADC characteristics
LPC112x
Product data sheet
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ADC
R1 = 0.25 kΩ...2.5 kΩ
ADCn_0
Rsw = 5 Ω...25 Ω
Cio
ADCn_[1:11]
DAC
Cia
Cio
aaa-016869
Fig 23. ADC input impedance
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13. Application information
13.1 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6:
• The ADC input trace must be short and as close as possible to the LPC112x chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
13.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV (RMS) is needed.
LPC1xxx
XTALIN
Ci
100 pF
Cg
002aae788
Fig 24. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 24), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 25 and in
Table 17 and Table 18. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 25 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer (see Table 17).
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LPC1xxx
L
XTALIN
XTALOUT
CL
=
CP
XTAL
RS
CX2
CX1
002aaf424
Fig 25. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 17.
Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
1 MHz to 5 MHz
10 pF
< 300
18 pF, 18 pF
20 pF
< 300
39 pF, 39 pF
5 MHz to 10 MHz
10 MHz to 15 MHz
15 MHz to 20 MHz
Table 18.
30 pF
< 300
57 pF, 57 pF
10 pF
< 300
18 pF, 18 pF
20 pF
< 200
39 pF, 39 pF
30 pF
< 100
57 pF, 57 pF
10 pF
< 160
18 pF, 18 pF
20 pF
< 60
39 pF, 39 pF
10 pF
< 80
18 pF, 18 pF
Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
15 MHz to 20 MHz
10 pF
< 180
18 pF, 18 pF
20 pF
< 100
39 pF, 39 pF
20 MHz to 25 MHz
10 pF
< 160
18 pF, 18 pF
20 pF
< 80
39 pF, 39 pF
13.3 XTAL Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case
of third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
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order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of CX1 and CX2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
13.4 Connecting power, clocks, and debug functions
Figure 26 shows the basic board connections used to power the LPC112x and provide
debug capabilities via the serial wire port.
LPC112x
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3.3 V
3.3 V
SWD connector
~10 kΩ - 100 kΩ
Note 4
SWDIO/PIO1_3
1
2
3
4
5
6
n.c.
7
8
n.c.
9
10
SWCLK/PIO0_10
XTALIN
~10 kΩ - 100 kΩ
C1
n.c.
Note 1
DGND
C2
XTALOUT
RESET/PIO0_0
DGND
VSS
DGND
DGND
Note 2
VDD (2 pins)
VSSA
3.3 V
LPC112x
0.01 μF
0.1 μF
AGND
DGND
PIO0_1
ISP select pin
Note 5
ADC_0
Note 3
VREFP
0.1 μF
3.3 V
10 μF
0.1 μF
VREFN
AGND
AGND
DGND
AGND
aaa-014718
(1) See Section 13.2 “XTAL input” for the values of C1 and C2.
(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the VDD pin. Add one set of decoupling
capacitors to each VDD pin.
(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and VDD pins. The 10 μF bypass capacitor
filters the power line. Tie VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used.
(4) Uses the ARM 10-pin interface for SWD.
(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see
Ref. 4.
Fig 26. Power, clock, and debug connections
LPC112x
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32-bit ARM Cortex-M0 microcontroller
13.5 Termination of unused pins
Table 19 shows how to terminate pins that are not used in the application. In many cases,
unused pins may should be connected externally or configured correctly by software to
minimize the overall power consumption of the part.
Unused pins with GPIO function should be configured as outputs set to LOW with their
internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the
GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0
to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.
In addition, it is recommended to configure all GPIO pins that are not bonded out on
smaller packages as outputs driven LOW with their internal pull-up disabled.
Table 19.
Termination of unused pins
Pin
Default
state[1]
Recommended termination of unused pins
RESET/PIO0_0
I; PU
In an application that does not use the RESET pin or its GPIO function, the
termination of this pin depends on whether Deep power-down mode is used:
•
Deep power-down used: Connect an external pull-up resistor and keep pin in
default state (input, pull-up enabled) during all other power modes.
•
Deep power-down not used and no external pull-up connected: can be left
unconnected if internal pull-up is disabled and pin is driven LOW and
configured as output by software.
all PIOn_m (not
open-drain)
I; PU
Can be left unconnected if driven LOW and configured as GPIO output with pull-up
disabled by software.
PIOn_m (I2C open-drain)
IA
Can be left unconnected if driven LOW and configured as GPIO output by software.
VREFP
-
Tie to VDD.
VREFN
-
Tie to VSS.
[1]
I = Input, O = Output, IA = Inactive (no pull-up/pull-down enabled), F = floating, PU = Pull-Up.
13.6 Pin states in different power modes
Table 20.
Pin states in different power modes
Pin
Active
Sleep
Deep-sleep/Powerdown
PIOn_m pins (not As configured in the IOCON[1]. Default: internal pull-up
enabled.
I2C)
Deep power-down
Floating.
PIO0_4, PIO0_5
(open-drain
I2C-bus pins)
As configured in the IOCON[1].
Floating.
RESET
Reset function enabled. Default: input, internal pull-up
enabled.
Reset function disabled; floating; if the part
is in deep power-down mode, the RESET
pin needs an external pull-up to reduce
power consumption.
PIO1_4/
WAKEUP
As configured in the IOCON[1]. WAKEUP function inactive. Wake-up function enabled; can be disabled
by software.
[1]
Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes.
LPC112x
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32-bit ARM Cortex-M0 microcontroller
13.7 Standard I/O pad configuration
Figure 27 shows the possible pin modes for standard I/O pins with analog input function:
•
•
•
•
•
•
Digital output driver.
Digital input: Pull-up enabled/disabled.
Digital input: Pull-down enabled/disabled.
Digital input: Repeater mode enabled/disabled.
Digital output: Pseudo open-drain mode enable/disabled.
Analog input.
VDD
VDD
open-drain enable
pin configured
as digital output
driver
strong
pull-up
output enable
ESD
data output
PIN
strong
pull-down
ESD
VSS
VDD
weak
pull-up
pull-up enable
pin configured
as digital input
weak
pull-down
repeater mode
enable
pull-down enable
data input
select analog input
pin configured
as analog input
analog input
002aah159
Fig 27. Standard I/O pad configuration
LPC112x
Product data sheet
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LPC112x
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32-bit ARM Cortex-M0 microcontroller
13.8 Reset pad configuration
VDD
VDD
VDD
Rpu
reset
ESD
20 ns RC
GLITCH FILTER
PIN
ESD
VSS
002aaf274
Fig 28. Reset pad configuration
LPC112x
Product data sheet
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LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
14. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7o
o
0
0.95
0.55
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 29. LQFP48 package outline
LPC112x
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LPC112x
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32-bit ARM Cortex-M0 microcontroller
15. Soldering
Footprint information for reflow soldering of LQFP48 package
SOT313-2
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
0.500
0.560
Ax
Ay
10.350 10.350
Bx
By
C
D1
D2
Gx
7.350
7.350
1.500
0.280
0.500
7.500
Gy
Hx
Hy
7.500 10.650 10.650
sot313-2_fr
Fig 30. Reflow soldering of the LQFP48 package
LPC112x
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32-bit ARM Cortex-M0 microcontroller
16. Abbreviations
Table 21.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
APB
Advanced Peripheral Bus
BOD
BrownOut Detection
GPIO
General Purpose Input/Output
PLL
Phase-Locked Loop
RC
Resistor-Capacitor
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
SSP
Synchronous Serial Port
TEM
Transverse ElectroMagnetic
UART
Universal Asynchronous Receiver/Transmitter
17. References
LPC112x
Product data sheet
[1]
User manual UM10839.
[2]
Errata sheet ES_LPC112x.
[3]
I2C-bus specification UM10204.
[4]
Technical note ADC design guidelines:
http://www.nxp.com/documents/technical_note/TN00009.pdf
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LPC112x
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32-bit ARM Cortex-M0 microcontroller
18. Revision history
Table 22.
Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
LPC112x v.1.0
20150224
Product data sheet
-
LPC112x
Product data sheet
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-
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
LPC112x
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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32-bit ARM Cortex-M0 microcontroller
21. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 11
ARM Cortex-M0 processor . . . . . . . . . . . . . . . 11
On-chip flash program memory . . . . . . . . . . . 11
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Nested Vectored Interrupt Controller
(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.5.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.5.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13
7.6
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.7
Fast general purpose parallel I/O . . . . . . . . . . 13
7.7.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.8
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.8.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.9
SSP controller. . . . . . . . . . . . . . . . . . . . . . . . . 14
7.9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.10
I2C-bus serial I/O controller . . . . . . . . . . . . . . 14
7.10.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.11
Analog-to-Digital Converter
(ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.11.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.12
General purpose external event
counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.12.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.13
System tick timer . . . . . . . . . . . . . . . . . . . . . . 16
7.14
Windowed WatchDog Timer . . . . . . . . . . . . . 16
7.14.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.15
Clocking and power control . . . . . . . . . . . . . . 17
7.15.1
Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 17
7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 18
7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 18
7.15.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 19
7.15.2
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.15.3
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.15.4
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 19
7.15.5
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.15.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 19
7.15.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.15.5.3
7.15.5.4
7.16
7.16.1
7.16.2
7.16.3
7.16.4
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . .
Deep power-down mode . . . . . . . . . . . . . . . .
System control . . . . . . . . . . . . . . . . . . . . . . . .
Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Brownout detection . . . . . . . . . . . . . . . . . . . .
Code security
(Code Read Protection - CRP) . . . . . . . . . . .
7.16.5
APB interface . . . . . . . . . . . . . . . . . . . . . . . . .
7.16.6
AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16.7
External interrupt inputs . . . . . . . . . . . . . . . . .
7.17
Emulation and debugging . . . . . . . . . . . . . . .
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
9
Thermal characteristics . . . . . . . . . . . . . . . . .
10
Static characteristics . . . . . . . . . . . . . . . . . . .
10.1
Power consumption . . . . . . . . . . . . . . . . . . .
10.2
CoreMark data . . . . . . . . . . . . . . . . . . . . . . . .
10.3
Peripheral power consumption . . . . . . . . . . .
10.4
Electrical pin characteristics. . . . . . . . . . . . . .
11
Dynamic characteristics. . . . . . . . . . . . . . . . .
11.1
Flash memory . . . . . . . . . . . . . . . . . . . . . . . .
11.2
External clock. . . . . . . . . . . . . . . . . . . . . . . . .
11.3
Internal oscillators . . . . . . . . . . . . . . . . . . . . .
11.4
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6
SSP interfaces . . . . . . . . . . . . . . . . . . . . . . . .
12
Analog characteristics . . . . . . . . . . . . . . . . . .
12.1
BOD static characteristics . . . . . . . . . . . . . . .
12.2
12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Application information . . . . . . . . . . . . . . . . .
13.1
ADC usage notes. . . . . . . . . . . . . . . . . . . . . .
13.2
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3
XTAL Printed Circuit Board (PCB) layout
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4
Connecting power, clocks, and debug
functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5
Termination of unused pins . . . . . . . . . . . . . .
13.6
Pin states in different power modes . . . . . . . .
13.7
Standard I/O pad configuration . . . . . . . . . . .
13.8
Reset pad configuration . . . . . . . . . . . . . . . . .
14
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
15
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
17
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Revision history . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
21
21
21
22
22
22
22
23
24
25
30
32
34
35
38
38
38
39
40
41
42
45
45
46
49
49
49
50
51
53
53
54
55
56
57
58
58
59
continued >>
LPC112x
Product data sheet
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Rev. 1. — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
62 of 63
LPC112x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
19
19.1
19.2
19.3
19.4
20
21
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 February 2015
Document identifier: LPC112x
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