LPC11C12

D D D R A FT D R A FT D R A FT R R A FT A FT LPC11C12/C14 Rev. 00.05 — 6 May 2010 D 32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN D R R A A FT FT D D R R A FT D R D R A FT D R A FT D FT D A A FT D Preliminary data sheet FT D R R A R A FT D R A FT D R A F A FT D R D R 1. General description The LPC11C12/C14 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11C12/C14 operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC11C12/C14 includes 16/32 kB of flash memory, 8 kB of data memory, one C_CAN controller, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 UART, two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and 40 general purpose I/O pins. On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included. A FT D R A 2. Features and benefits System: ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug. System tick timer. Memory: 32 kB (LPC11C14) or 16 kB (LPC11C12) on-chip flash programming memory. 8 kB SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash ISP commands can be issued via UART or C_CAN. Digital peripherals: 40 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. GPIO pins can be used as edge and level sensitive interrupt sources. High-current output driver (20 mA) on one pin. High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus. Four general purpose counter/timers with a total of four capture inputs and 13 match outputs. Programmable WatchDog Timer (WDT). Analog peripherals: 10-bit ADC with input multiplexing among 8 pins. D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A A FT FT D D R R A FT D Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities. I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. C_CAN controller. On-chip C_CAN drivers included. Clock generation: 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. Clock output function with divider that can reflect the system oscillator, IRC, CPU clock, or the Watchdog clock. Power control: Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes. Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Processor wake-up from Deep-sleep mode via a dedicated start logic using 13 of the GPIO pins. Power-On Reset (POR). Brownout detect with four separate thresholds for interrupt and forced reset. Unique device serial number for identification. Single 3.3 V power supply (1.8 V to 3.6 V). Available as 48-pin LQFP package. R A FT D R A FT D D R A D R A R R A D R A FT D R A A FT A FT D R D R A F R A FT D FT D R A FT 3. Applications eMetering Elevator systems Industrial and sensor based networks White goods 4. Ordering information Table 1. Ordering information Package Name LPC11C12FBD48/301 LPC11C14FBD48/301 LQFP48 LQFP48 Description Version LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2 1.4 mm Type number LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 2 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 4.1 Ordering options Table 2. Ordering options Flash 16 kB 32 kB Total SRAM 8 kB 8 kB UART RS-485 1 1 I2C/ Fast+ 1 1 SPI 2 2 C_CAN 1 1 ADC channels 8 8 Type number LPC11C12FBD48/301 LPC11C14FBD48/301 D R R LQFP48 LQFP48 R A Package A FT D R A A F R A FT D FT D FT D R A FT D R A 5. Block diagram XTALIN XTALOUT RESET SWD LPC11C12/C14 IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls FLASH 16/32 kB slave GPIO ports PIO0/1/2/3 HIGH-SPEED GPIO slave AHB-LITE BUS SRAM 8 kB slave slave CLKOUT POR ARM CORTEX-M0 system bus ROM slave AHB TO APB BRIDGE RXD TXD DTR, DSR, CTS, DCD, RI, RTS CT32B0_MAT[3:0] CT32B0_CAP0 CT32B1_MAT[3:0] CT32B1_CAP0 CT16B0_MAT[2:0] CT16B0_CAP0 CT16B1_MAT[1:0] CT16B1_CAP0 CAN_TXD CAN_RXD UART 10-bit ADC AD[7:0] SCK0, SSEL0 MISO0, MOSI0 SCK1, SSEL1 MISO1, MOSI1 SCL SDA SPI0 32-bit COUNTER/TIMER 0 SPI1 32-bit COUNTER/TIMER 1 I2C-BUS 16-bit COUNTER/TIMER 0 16-bit COUNTER/TIMER 1 WDT IOCONFIG C_CAN SYSTEM CONTROL PMU 002aaf265 Fig 1. LPC11C12_C14_0 LPC11C12/C14 block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 3 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 6. Pinning information 6.1 Pinning 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP D R R A FT D R R A F D R A FT A FT A FT D R A D FT 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 D R A 46 PIO1_6/RXD/CT32B0_MAT0 47 PIO1_7/TXD/CT32B0_MAT1 45 PIO1_5/RTS/CT32B0_CAP0 38 PIO2_3/RI/MOSI1 42 PIO1_11/AD7 43 PIO3_2/DCD PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 VSS XTALIN XTALOUT VDD PIO1_8/CT16B1_CAP0 1 2 3 4 5 6 7 8 9 37 PIO3_1/DSR 36 PIO3_0/DTR 35 R/PIO1_2/AD3/CT32B1_MAT1 34 R/PIO1_1/AD2/CT32B1_MAT0 33 R/PIO1_0/AD1/CT32B1_CAP0 32 R/PIO0_11/AD0/CT32B0_MAT3 31 PIO2_11/SCK0 30 PIO1_10/AD6/CT16B1_MAT1 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 28 PIO0_9/MOSI0/CT16B0_MAT1 27 PIO0_8/MISO0/CT16B0_MAT0 26 PIO2_2/DCD/MISO1 25 PIO2_10 PIO2_9 24 002aaf266 48 PIO3_3/RI 44 VDD LPC11C12FBD48/301 LPC11C14FBD48/301 PIO0_2/SSEL0/CT16B0_CAP0 10 PIO2_7 11 PIO2_8 12 PIO2_1/DSR/SCK1 13 PIO0_3 14 PIO0_4/SCL 15 PIO0_5/SDA 16 PIO1_9/CT16B1_MAT0 17 PIO2_4 18 CAN_RXD 19 CAN_TXD 20 PIO2_5 21 PIO0_6/SCK0 22 PIO0_7/CTS 23 Fig 2. Pin configuration LQFP48 package LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. 41 VSS © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 4 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 6.2 Pin description Table 3. Symbol PIO0_0 to PIO0_11 LPC11C14 pin description table (LQFP48 package) Pin Type I/O Description D R Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET — External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. PIO0_0 — General purpose digital input/output pin. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A RESET/PIO0_0 3[1][2] I I/O PIO0_1/CLKOUT/ CT32B0_MAT2 4[3][2] I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the flash ISP command handler via UART (if PIO0_3 is HIGH) or via C_CAN (if PIO0_3 is LOW). CLKOUT — Clockout pin. CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2 — General purpose digital input/output pin. SSEL0 — Slave Select for SPI0. CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 — General purpose digital input/output pin. This pin is monitored during reset: Together with a LOW level on pin PIO0_1, a LOW level starts the flash ISP command handler via C_CAN and a HIGH level starts the flash ISP command handler via UART. PIO0_4 — General purpose digital input/output pin (open-drain). SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5 — General purpose digital input/output pin (open-drain). SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6 — General purpose digital input/output pin. SCK0 — Serial clock for SPI0. PIO0_7 — General purpose digital input/output pin (high-current output driver). CTS — Clear To Send input for UART. PIO0_8 — General purpose digital input/output pin. MISO0 — Master In Slave Out for SPI0. CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9 — General purpose digital input/output pin. MOSI0 — Master Out Slave In for SPI0. CT16B0_MAT1 — Match output 1 for 16-bit timer 0. SWCLK — Serial wire clock. PIO0_10 — General purpose digital input/output pin. SCK0 — Serial clock for SPI0. CT16B0_MAT2 — Match output 2 for 16-bit timer 0. O O PIO0_2/SSEL0/ CT16B0_CAP0 10[3][2] I/O O I PIO0_3 14[3][2] I/O PIO0_4/SCL 15[4][2] I/O I/O PIO0_5/SDA 16[4][2] I/O I/O PIO0_6/SCK0 PIO0_7/CTS 22[3][2] 23[3][2] I/O I/O I/O I PIO0_8/MISO0/ CT16B0_MAT0 27[3][2] I/O I/O O PIO0_9/MOSI0/ CT16B0_MAT1 28[3][2] I/O I/O O SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 29[3][2] I I/O I/O O LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 5 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT Table 3. Symbol LPC11C14 pin description table (LQFP48 package) …continued Pin 32[5][2] Type I I/O I O Description PIO0_11 — General purpose digital input/output pin. AD0 — A/D converter, input 0. CT32B0_MAT3 — Match output 3 for 32-bit timer 0. D R R A FT D R A F D A FT R/PIO0_11/ AD0/CT32B0_MAT3 R — Reserved. Configure for an alternate function in the IOCONFIG block. R R A A FT D R A FT D R A FT D PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R — Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_0 — General purpose digital input/output pin. AD1 — A/D converter, input 1. CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R — Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_1 — General purpose digital input/output pin. AD2 — A/D converter, input 2. CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R — Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_2 — General purpose digital input/output pin. AD3 — A/D converter, input 3. CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO — Serial wire debug input/output. PIO1_3 — General purpose digital input/output pin. AD4 — A/D converter, input 4. CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_4 — General purpose digital input/output pin. AD5 — A/D converter, input 5. CT32B1_MAT3 — Match output 3 for 32-bit timer 1. WAKEUP — Deep power-down mode wake-up pin. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. PIO1_5 — General purpose digital input/output pin. RTS — Request To Send output for UART. CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. PIO1_6 — General purpose digital input/output pin. RXD — Receiver input for UART. CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_7 — General purpose digital input/output pin. TXD — Transmitter output for UART. CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_8 — General purpose digital input/output pin. CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO1_9 — General purpose digital input/output pin. CT16B1_MAT0 — Match output 0 for 16-bit timer 1. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. R/PIO1_0/ AD1/CT32B1_CAP0 33[5][2] I I/O I I R/PIO1_1/ AD2/CT32B1_MAT0 34[5] O I/O I O R/PIO1_2/ AD3/CT32B1_MAT1 35[5] I I/O I O SWDIO/PIO1_3/AD4/ CT32B1_MAT2 39[5] I/O I/O I O PIO1_4/AD5/ 40[5] CT32B1_MAT3/WAKEUP I/O I O I PIO1_5/RTS/ CT32B0_CAP0 45[3] I/O O I PIO1_6/RXD/ CT32B0_MAT0 46[3] I/O I O PIO1_7/TXD/ CT32B0_MAT1 47[3] I/O O O PIO1_8/CT16B1_CAP0 PIO1_9/CT16B1_MAT0 9[3] 17[3] I/O I I/O O LPC11C12_C14_0 Preliminary data sheet Rev. 00.05 — 6 May 2010 6 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT Table 3. Symbol LPC11C14 pin description table (LQFP48 package) …continued Pin 30[5] Type I/O I O 42[5] I/O I I/O Description PIO1_10 — General purpose digital input/output pin. AD6 — A/D converter, input 6. CT16B1_MAT1 — Match output 1 for 16-bit timer 1. PIO1_11 — General purpose digital input/output pin. AD7 — A/D converter, input 7. D R R A FT D R A F D A FT PIO1_10/AD6/ CT16B1_MAT1 R R A FT D R A FT D A FT PIO1_11/AD7 PIO2_0 to PIO2_11 D R A Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. PIO2_0 — General purpose digital input/output pin. DTR — Data Terminal Ready output for UART. SSEL1 — Slave Select for SPI1. PIO2_1 — General purpose digital input/output pin. DSR — Data Set Ready input for UART. SCK1 — Serial clock for SPI1. PIO2_2 — General purpose digital input/output pin. DCD — Data Carrier Detect input for UART. MISO1 — Master In Slave Out for SPI1. PIO2_3 — General purpose digital input/output pin. RI — Ring Indicator input for UART. MOSI1 — Master Out Slave In for SPI1. PIO2_4 — General purpose digital input/output pin. PIO2_5 — General purpose digital input/output pin. PIO2_6 — General purpose digital input/output pin. PIO2_7 — General purpose digital input/output pin. PIO2_8 — General purpose digital input/output pin. PIO2_9 — General purpose digital input/output pin. PIO2_10 — General purpose digital input/output pin. PIO2_11 — General purpose digital input/output pin. SCK0 — Serial clock for SPI0. Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. PIO3_0 — General purpose digital input/output pin. DTR — Data Terminal Ready output for UART. PIO3_1 — General purpose digital input/output pin. DSR — Data Set Ready input for UART. PIO3_2 — General purpose digital input/output pin. DCD — Data Carrier Detect input for UART. PIO3_3 — General purpose digital input/output pin. RI — Ring Indicator input for UART. CAN_RXD — C_CAN receive data input. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. PIO2_0/DTR/SSEL1 2[3] I/O O O PIO2_1/DSR/SCK1 13[3] I/O I I/O PIO2_2/DCD/MISO1 26[3] I/O I I/O PIO2_3/RI/MOSI1 38[3] I/O I I/O PIO2_4 PIO2_5 PIO2_6 PIO2_7 PIO2_8 PIO2_9 PIO2_10 PIO2_11/SCK0 PIO3_0 to PIO3_5 18[3] 21[3] 1[3] 11[3] 12[3] 24[3] 25[3] 31[3] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PIO3_0/DTR PIO3_1/DSR PIO3_2/DCD PIO3_3/RI CAN_RXD LPC11C12_C14_0 36[3] 37[3] 43[3] 48[3] 19[6] I/O O I/O I I/O I I/O I I Preliminary data sheet Rev. 00.05 — 6 May 2010 7 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT Table 3. Symbol CAN_TXD VDD XTALIN XTALOUT VSS [1] [2] [3] [4] [5] [6] [7] LPC11C14 pin description table (LQFP48 package) …continued Pin 20[6] 8;44 6[7] 7[7] 5; 41 Type O I I O I Description CAN_TXD — C_CAN transmit data output. D R Supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. Output from the oscillator amplifier. Ground. See Figure 25 for reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. Serves as Deep-sleep wake-up input pin to the start logic independently of selected pin function (see the LPC111x/11C1x user manual). 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 24). I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 24). 5 V tolerant digital I/O pad without pull-up/pull-down resistors. When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 8 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 7. Functional description 7.1 ARM Cortex-M0 processor D R The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 7.2 On-chip flash program memory The LPC11C12/C14 contain 32 kB (LPC11C14) or 16 kB (LPC11C12) of on-chip flash memory. 7.3 On-chip SRAM The LPC11C12/C14 contain a total of 8 kB on-chip static RAM memory. 7.4 Memory map The LPC11C12/C14 incorporates several distinct memory regions, shown in the following figures. Figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 9 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A AHB peripherals 0xFFFF FFFF 127- 4 reserved reserved 0x5004 0000 3 0x5020 0000 2 1 0 reserved GPIO PIO3 GPIO PIO2 GPIO PIO1 GPIO PIO0 APB peripherals 23 - 31 reserved 0x4005 C000 0x4008 0000 22 SPI1 reserved 0x4005 4000 20 C_CAN reserved reserved 18 17 system control IOCONFIG SPI0 flash controller PMU 10 - 13 reserved 0x4002 8000 9 8 reserved 7 6 0x1000 2000 5 4 3 2 reserved 1 0 0x0000 8000 + 512 byte active interrupt vectors reserved reserved ADC 32-bit counter/timer 1 32-bit counter/timer 0 16-bit counter/timer 1 16-bit counter/timer 0 UART WDT I2C-bus 0x0000 0200 0x0000 0000 002aaf268 D R A D R A FT D R A FT R R A D R A FT D R A FT D R A FT A FT A FT D R D R A F FT 4 GB LPC11C12/C14 0x5020 0000 D D R A FT D 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 R A FT D A FT D R A R AHB peripherals 0x5000 0000 0x4005 8000 1 GB APB peripherals 0x4000 0000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0.5 GB reserved 0x2000 0000 16 15 14 0x1FFF 4000 16 kB boot ROM 0x1FFF 0000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 8 kB SRAM 0x1000 0000 32 kB on-chip flash (LPC11C14) 0 GB 16 kB on-chip flash (LPC11C12) 0x0000 4000 0x0000 0000 Fig 3. LPC11C12/C14 memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. • In the LPC11C12/C14, the NVIC supports 32 vectored interrupts including 13 inputs to the start logic from individual GPIO pins. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 10 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A A FT FT D D R R A FT D • Four programmable interrupt priority levels, with hardware priority level masking. • Relocatable vector table. • Software interrupt generation. FT D R D R A D R A R R A D R A R A FT D D A FT A FT A FT D R D R A F R A FT D FT 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of 40 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. R A FT D R A 7.6 IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC11C12/C14 use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. • Entire port value can be written in one instruction. Additionally, any GPIO pin (total of 40 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features • Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. • Direction control of individual bits. • All GPIO pins default to inputs with pull-ups enabled after reset except for the I2C-bus true open-drain pins PIO0_4 and PIO0_5. • Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin (except PIO0_4 and PIO0_5). 7.8 UART The LPC11C12/C14 contain one UART. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 11 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A A FT FT D D R R A FT D Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. FT D R A D R A D R A R R A D R A R A FT D D R A FT A FT A FT D R D R A F R A FT D FT FT 7.8.1 Features D R A • • • • • Maximum UART data bit rate of 3.125 MBit/s. 16 Byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit mode. • Support for modem control. 7.9 SPI serial I/O controller The LPC11C12/C14 contain two SPI controllers. Both SPI controllers support SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.9.1 Features • Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame 7.10 I2C-bus serial I/O controller The LPC11C12/C14 contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 12 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A A FT FT D D R R A FT D receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. R A FT D R A FT D R A D R A R R A D R A FT D A FT A FT D R D R A F R A FT FT 7.10.1 Features I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s. D • The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The • • • • • Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus. • Serial clock synchronization allows devices with different bit rates to communicate via • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.11 C_CAN controller Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security. On-chip C_CAN drivers provide an API for initialization and communication using CAN and CANopen standards. D R A FT D R A 7.11.1 Features • • • • • • • Conforms to protocol version 2.0 parts A and B. Supports bit rate of up to 1 Mbit/s. Supports 32 Message Objects. Each Message Object has its own identifier mask. Provides programmable FIFO mode (concatenation of Message Objects). Provides maskable interrupts. Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. • Provides programmable loop-back mode for self-test operation. • The C_CAN API includes the following functions: – C_CAN set-up and initialization – C_CAN send and receive messages LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 13 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT – C_CAN status – CANopen object dictionary – CANopen SDO expedited communication – CANopen SDO segmented communication primitives – CANopen SDO fall-back handler D R R A FT D R R A F D R A FT A FT A FT D R A D FT D • Flash ISP programming via C_CAN supported. 7.12 10-bit ADC The LPC11C12/C14 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. R A 7.12.1 Features • • • • • • • • 10-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 V to VDD. 10-bit conversion time ≥ 2.44 μs. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or timer match signal. Individual result registers for each ADC channel to reduce interrupt overhead. 7.13 General purpose external event counter/timers The LPC11C12/C14 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.13.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 14 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT – Do nothing on match. D R R A FT D R A F D A FT 7.14 System tick timer R The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). D R A FT R A FT D FT D R A 7.15 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a selectable time period. A 7.15.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in multiples of Tcy(WDCLK) × 4. (IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator 7.16 Clocking and power control 7.16.1 Crystal oscillators The LPC11C12/C14 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11C12/C14 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 4 for an overview of the LPC11C12/C14 clock generation. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 15 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT AHB clock 0 (system) D R A D R A FT D R A D R A FT R R A D R A FT D R A FT D R A FT D D R A FT A FT D R D R A F R FT SYSTEM CLOCK DIVIDER system clock A A FT D R FT D 18 AHB clocks 1 to 18 (memories and peripherals) A FT D R A AHBCLKCTRL[1:18] (AHB clock enable) IRC oscillator SPI0 PERIPHERAL CLOCK DIVIDER main clock UART PERIPHERAL CLOCK DIVIDER SPI1 PERIPHERAL CLOCK DIVIDER SPI0 watchdog oscillator UART SPI1 MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator IRC oscillator SYSPLLCLKSEL (system PLL clock select) WDT CLOCK DIVIDER watchdog oscillator WDTUEN (WDT clock update enable) IRC oscillator system oscillator watchdog oscillator WDT CLKOUT PIN CLOCK DIVIDER CLKOUT pin CLKOUTUEN (CLKOUT update enable) 002aae514 Fig 4. LPC11C12/C14 clock generation block diagram 7.16.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC11C12/C14 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.16.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 16 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 7.16.1.3 Watchdog oscillator D R The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is ±40 % (see Table 11). D R A FT D R A FT R A F D R A FT D FT R A A FT 7.16.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 μs. D R A 7.16.3 Clock output The LPC11C12/C14 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.16.4 Wake-up process The LPC11C12/C14 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.16.5 Power control The LPC11C12/C14 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.16.5.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 17 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 7.16.5.2 Deep-sleep mode D R In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks can be shut down for increased power savings. The user can configure the Deep-sleep mode to a large extent, selecting any of the oscillators, the PLL, BOD, the ADC, and the flash to be shut down or remain powered during Deep-sleep mode. The user can also select which of the oscillators and analog blocks will be powered up after the chip exits from Deep-sleep mode. D R A FT D The GPIO pins (13 pins total: PIO0_0 to PIO0_11 and PIO1_1) serve as external wake-up pins to a dedicated start logic to wake up the chip from Deep-sleep mode. The timing of the wake-up process from Deep-sleep mode depends on which blocks are selected to be powered down during deep-sleep. For lowest power consumption, the clock source should be switched to IRC before entering Deep-sleep mode, all oscillators and the PLL should be turned off during deep-sleep, and the IRC should be selected as clock source when the chip wakes up from deep-sleep. The IRC can be switched on and off glitch-free and provides a clean clock signal after start-up. If power consumption is not a concern, any of the oscillators and/or the PLL can be left running in Deep-sleep mode to obtain short wake-up times when waking up from deep-sleep. 7.16.5.3 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC11C12/C14 can wake up from Deep power-down mode via the WAKEUP pin. R A FT R A F D R A FT D FT D R A R A A FT 7.17 System control 7.17.1 Reset Reset has four sources on the LPC11C12/C14: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.17.2 Brownout detection The LPC11C12/C14 includes four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 18 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 7.17.3 Code security (Code Read Protection - CRP) D R This feature of the LPC11C12/C14 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details see the LPC11Cx user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. D R A FT D 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the UART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC11Cx user manual. R A FT R A F D R A FT D FT D R A R A A FT 7.17.4 Boot loader The boot loader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. The boot loader code is executed every time the part is reset or powered up. The loader can either execute the user application code or the ISP command handler via UART or C_CAN. A LOW level during reset applied to the PIO0_1 pin is considered as an external hardware request to start the ISP command handler. The state of PIO0_3 at reset determines whether the UART (PIO0_3 HIGH) or the C_CAN (PIO0_3 LOW) interface will be used. The C_CAN ISP command handler uses the CANopen protocol and data organization method. C_CAN ISP commands have the same functionality as UART ISP commands. 7.17.5 APB interface The APB peripherals are located on one APB bus. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 19 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 7.17.6 AHBLite D R The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. D R A FT D R A FT R A F D R A FT D A FT 7.17.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. R A FT D R A 7.17.8 Memory mapping control The Cortex-M0 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address space. The vector table must be located on a 128 word (512 byte) boundary. 7.18 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 20 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD VI Parameter supply voltage (core and external rail) input voltage 5 V tolerant I/O pins; only valid when the VDD supply voltage is present per supply pin per ground pin −(0.5VDD) < VI < (1.5VDD); Tj < 125 °C Tstg Tj(max) Ptot(pack) storage temperature maximum junction temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model; all pins [5] [4] [2] D R R A FT D R R A F D R A FT A FT A FT D D Conditions Min 1.8 −0.5 Max 3.6 +5.5 Unit V V R A FT D R A IDD ISS Ilatch supply current ground current I/O latch-up current [3] [3] - 100 100 100 mA mA mA −65 - +150 150 1.5 °C °C W VESD electrostatic discharge voltage −5000 +5000 V [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] [3] [4] [5] Including voltage on outputs in 3-state mode. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 21 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 9. Static characteristics Table 5. Static characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol VDD IDD Parameter supply voltage (core and external rail) supply current Active mode; code Conditions Min 1.8 Typ[1] 3.3 D R Max 3.6 R A FT D R R A F D R A FT A FT A Unit V FT D R A D FT D R A while(1){} executed from flash system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.3 V Sleep mode; system clock = 12 MHz VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V Deep power-down mode; VDD = 3.3 V Standard port pins, RESET IIL IIH LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage 2.0 V ≤ VDD ≤ 3.6 V; IOH = −4 mA 1.8 V ≤ VDD < 2.0 V; IOH = −3 mA VOL LOW-level output voltage 2.0 V ≤ VDD ≤ 3.6 V; IOL = 4 mA 1.8 V ≤ VDD < 2.0 V; IOL = 3 mA [14] [2][3][5] [9] [2][10] [2][3][4] [5][6][7] [2][3][6] [5][7][8] [2][3][4] [5][6][7] - 3 9 2 - mA mA mA - 6 220 - μA nA - 0.5 0.5 10 10 nA nA VI = VDD; on-chip pull-down resistor disabled VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled pin configured to provide a digital function output active [11][12] [13] IOZ - 0.5 10 nA VI VO VIH VIL Vhys VOH 0 0 0.7VDD VDD − 0.4 VDD − 0.4 - 0.4 - 5.0 VDD 0.3VDD 0.4 0.4 V V V V V V V V V [14] [14] [14] LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 22 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT Table 5. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol IOH Parameter HIGH-level output current Conditions VOH = VDD − 0.4 V; 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V IOL LOW-level output current VOL = 0.4 V 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V IOHS IOLS Ipd Ipu HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD VI = 5 V VI = 0 V; 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V VDD < VI < 5 V High-drive output pin (PIO0_7) IIL IIH LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage 2.0 V ≤ VDD ≤ 3.6 V; IOH = −4 mA 1.8 V ≤ VDD < 2.0 V; IOH = −3 mA VOL LOW-level output voltage 2.0 V ≤ VDD ≤ 3.6 V; IOL = 4 mA 1.8 V ≤ VDD < 2.0 V; IOL = 3 mA IOH IOL HIGH-level output current LOW-level output current VOH = VDD − 0.4 V; VDD ≥ 2.5 V VOL = 0.4 V 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V LPC11C12_C14_0 D R R A FT R A F A FT Min [14] Typ[1] 50 −50 −50 0 0.5 0.5 Max −45 50 150 −85 −85 0 10 10 Unit mA mA mA mA mA mA μA μA μA μA nA nA D D R R A A −4 −3 4 3 10 −15 −10 0 - FT D R A FT FT D [14] [14] D R A [14] [15] [15] VI = VDD; on-chip pull-down resistor disabled VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled pin configured to provide a digital function output active [11][12] [13] IOZ - 0.5 10 nA VI VO VIH VIL Vhys VOH 0 0 0.7VDD 0.4 - 5.0 VDD 0.3VDD 0.4 0.4 - V V V V V V V V V mA mA mA [14] VDD − 0.4 VDD − 0.4 20 4 3 [14] [14] [14] [14] [14] [14] All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 23 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT Table 5. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol IOHS IOLS Ipd Ipu Parameter Conditions [15] D R R A FT R A F A FT Min 10 −15 −10 0 0.7VDD - Typ[1] 50 −50 −50 0 0.5VDD - Max −45 50 150 −85 −85 0 0.3VDD - Unit mA D D R R A A HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD VI = 5 V VI = 0 V 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V VDD < VI < 5 V FT D R A FT D [15] mA μA μA μA μA V V V mA FT D R A I2C-bus pins (PIO0_4 and PIO0_5) VIH VIL Vhys IOL HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output current VOL = 0.4 V; pins configured as standard mode pins 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V IOL LOW-level output current VOL = 0.4 V; pins configured as Fast-mode Plus pins 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V ILI Oscillator pins Vi(xtal) Vo(xtal) [1] [2] [3] [4] [5] [6] [7] [8] [9] [14] [16] [14] [14] I2C-bus [14] 4 3 20 - mA I2C-bus 16 −0.5 −0.5 2 10 1.8 1.8 4 22 1.95 1.95 μA μA V V input leakage current VI = VDD VI = 5 V crystal input voltage crystal output voltage Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. Tamb = 25 °C. IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. IRC enabled; system oscillator disabled; system PLL disabled. Pin CAN_RXD pulled LOW externally. BOD disabled. All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. IRC disabled; system oscillator enabled; system PLL enabled. All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0xFFFF FDFF. [10] WAKEUP pin pulled HIGH externally. [11] Including voltage on outputs in 3-state mode. [12] VDD supply voltage must be present. [13] 3-state outputs go into 3-state mode in Deep power-down mode. [14] Accounts for 100 mV voltage drop in all supply lines. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 24 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] To VSS. D R R A FT D R R A F D R A FT A FT A Table 6. ADC static characteristics Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol VIA Cia ED EL(adj) EO EG ET Rvsi Ri [1] [2] [3] [4] [5] [6] [7] [8] FT D R A D Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance input resistance Conditions Min 0 [1][2] [3] [4] [5] [6] Typ - Max VDD 1 ±1 ± 1.5 ± 3.5 0.6 ±4 40 2.5 Unit V pF LSB LSB LSB % LSB kΩ MΩ FT D R A - [7][8] - The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 5. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 5. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 5. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 5. Tamb = 25 °C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF. Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs × Cia). LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 25 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R offset error EO D R A A D R A FT D R A FT D R A gain error EG R R A D R A FT D R A FT D R A FT D D R A FT D FT A FT A FT D R D R A F R A FT D FT 1023 R A FT D 1022 R A 1021 1020 1019 1018 (2) 7 code out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024 0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 5. ADC characteristics LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 26 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 9.1 BOD static characteristics Table 7. BOD static characteristics[1] Tamb = 25 °C. Symbol Vth Parameter threshold voltage Conditions interrupt level 0 assertion de-assertion interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion reset level 1 assertion de-assertion reset level 2 assertion de-assertion reset level 3 assertion de-assertion [1] D R R A FT D R R A F D R A FT A FT A FT Min - Typ 1.65 1.80 2.22 2.35 2.52 2.66 2.80 2.90 1.46 1.63 2.06 2.15 2.35 2.43 2.63 2.71 Max - Unit V V V V V V V V V V V V V V V V D Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11Cx user manual. D R A FT D R A 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC11Cx user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 27 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R 002aaf390 D R A A D R A FT D R A FT D R A FT R R A D R A FT D R A FT D R A FT A FT A FT D R D R A F FT 12 IDD (mA) 8 D D R A FT D R A FT D 48 MHz(2) 36 MHz(2) 24 MHz(2) 4 12 MHz(1) R A FT D R A 0 1.8 2.4 3.0 VDD (V) 3.6 Conditions: Tamb = 25 °C; active mode entered executing code w hile(1){} from flash; all peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 6. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies 12 IDD (mA) 8 002aaf391 48 MHz(2) 36 MHz(2) 24 MHz(2) 4 12 MHz(1) 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; active mode entered executing code w hile(1){} from flash; all peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 7. Active mode: Typical supply current IDD versus temperature for different system clock frequencies LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 28 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R 002aaf392 D R A A D R A FT D R A FT D R A FT R R A D R A FT D R A FT D R A FT A FT A FT D R D R A F FT 8 IDD (mA) 6 36 MHz(2) 4 D D R A FT R A FT 48 MHz(2) D D R A FT D R A 24 MHz(2) 12 MHz(1) 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 8. Sleep mode: Typical supply current IDDversus temperature for different system clock frequencies 40 IDD (μA) 30 3.6 V 3.3 V 2.0 V 1.8 V 002aaf394 20 10 0 −40 −15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0xFFFF FDFF); pin CAN_RXD pulled LOW externally. Fig 9. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 29 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R 002aaf457 D R A A D R A FT D R A FT D R A FT R R A D R A FT D R A FT D R A FT A FT A FT D R D R A F FT 0.8 IDD (μA) 0.6 VDD = 3.6 V 3.3 V 2.0 V 1.8 V D D R A FT D R A FT D A FT D R A R 0.4 0.2 0 −40 −15 10 35 60 85 temperature (°C) Fig 10. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD 9.3 Electrical pin characteristics 3.6 VOH (V) 3.2 T = 85 °C 25 °C −40 °C 002aae990 2.8 2.4 2 0 10 20 30 40 50 IOH (mA) 60 Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 11. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 30 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R 002aaf019 D R A A D R A FT D R A FT D R A FT R R A D R A FT D R A FT D R A FT A FT A FT D R D R A F FT 60 IOL (mA) 40 T = 85 °C 25 °C −40 °C D D R A FT D R A FT D A FT D R A R 20 0 0 0.2 0.4 VOL (V) 0.6 Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 12. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL 15 IOL (mA) 10 T = 85 °C 25 °C −40 °C 002aae991 5 0 0 0.2 0.4 VOL (V) 0.6 Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 31 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R 002aae992 D R A A D R A FT D R A FT D R A FT R R A D R A FT D R A FT D R A FT A FT A FT D R D R A F FT 3.6 VOH (V) 3.2 D D R A FT R A FT T = 85 °C 25 °C −40 °C D D R A FT D R A 2.8 2.4 2 0 8 16 IOH (mA) 24 Conditions: VDD = 3.3 V; standard port pins. Fig 14. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 10 Ipu (μA) −10 002aae988 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 15. Typical pull-up current Ipu versus input voltage VI LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 32 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R 002aae989 D R A A D R A FT D R A FT D R A FT R R A D R A FT D R A FT D R A FT A FT A FT D R D R A F FT 80 Ipd (μA) 60 T = 85 °C 25 °C −40 °C D D R A FT D R A FT D A FT D R A R 40 20 0 0 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 16. Typical pull-down current Ipd versus input voltage VI LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 33 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 10. Dynamic characteristics 10.1 Flash memory Table 8. Flash characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Nendu tret ter Parameter endurance retention time erase time powered unpowered sector or multiple consecutive sectors [2] D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R Conditions [1] Min 10000 10 20 95 Typ 100 Max 105 Unit cycles years years ms A tprog [1] [2] programming time 0.95 1 1.05 ms Number of program/erase cycles. Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock Table 9. Dynamic characteristic: external clock Tamb = −40 °C to +85 °C; VDD over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL [1] [2] Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time Conditions Min 1 40 Tcy(clk) × 0.4 Tcy(clk) × 0.4 - Typ[2] - Max 25 1000 5 5 Unit MHz ns ns ns ns ns Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. tCHCL tCLCX Tcy(clk) tCHCX tCLCH 002aaa907 Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 34 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 10.3 Internal oscillators Table 10. Dynamic characteristic: internal oscillators Tamb = −40 °C to +85 °C; 2.7 V ≤ VDD ≤ 3.6 V.[1] Symbol fosc(RC) [1] [2] D R R A FT D R Typ[2] 12 R A F D R A FT A FT A FT Parameter Conditions Min 11.88 Max 12.12 Unit D D R A internal RC oscillator frequency - MHz FT D Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. R A 12.15 f (MHz) 12.05 002aaf403 VDD = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V 11.95 11.85 −40 −15 10 35 60 85 temperature (°C) Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for 2.7 V ≤ VDD ≤ 3.6 V and Tamb = −40 °C to +85 °C. Variations between parts may cause the IRC to fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V. Fig 18. Internal RC oscillator frequency vs. temperature Table 11. fosc Dynamic characteristics: Watchdog oscillator Conditions [2][3] Symbol Parameter Min - Typ[1] 7.8 1700 Max - Unit kHz kHz internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] [1] [2] [3] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. The typical frequency spread over processing and temperature (Tamb = −40 °C to +85 °C) is ±40 %. See the LPC11Cx user manual. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 35 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 10.4 I/O pins Table 12. Dynamic characteristic: I/O pins[1] Tamb = −40 °C to +85 °C; 1.8 V ≤ VDD ≤ 3.6 V. Symbol tr Parameter rise time Conditions pin configured as output pin configured as output Min 3.0 Typ - D R Max 5.0 R A FT D R R A F D R A FT A FT Unit ns A FT D R A D FT D R A tf fall time 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 10.5 I2C-bus Table 13. Dynamic characteristic: I2C-bus pins[1] Tamb = −40 °C to +85 °C.[2] Symbol fSCL Parameter SCL clock frequency Conditions Standard-mode Fast-mode Fast-mode Plus tf fall time [4][5][6][7] Min 0 0 0 - Max 100 400 1 300 Unit kHz kHz MHz ns of both SDA and SCL signals Standard-mode Fast-mode Fast-mode Plus 20 + 0.1 × Cb 4.7 1.3 0.5 4.0 0.6 0.26 0 0 0 250 100 50 300 120 - ns ns μs μs μs μs μs μs μs μs μs ns ns ns tLOW LOW period of the SCL clock Standard-mode Fast-mode Fast-mode Plus Standard-mode Fast-mode Fast-mode Plus [3][4][8] tHIGH HIGH period of the SCL clock tHD;DAT data hold time Standard-mode Fast-mode Fast-mode Plus tSU;DAT data set-up time [9][10] Standard-mode Fast-mode Fast-mode Plus [1] [2] [3] [4] [5] See the I2C-bus specification UM10204 for details. Parameters are valid over operating temperature range unless otherwise specified. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 36 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. D R R R A A A FT D R FT F D R [7] [8] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. A A FT D A FT D R A FT D R [9] [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. tf SDA 70 % 30 % tf 70 % 30 % 70 % 30 % tHD;DAT tSU;DAT tVD;DAT tHIGH SCL 70 % 30 % 70 % 30 % tLOW 70 % 30 % S 1 / fSCL 002aaf425 Fig 19. I2C-bus pins clock timing 10.6 SPI interfaces Table 14. Symbol Tcy(PCLK) Tcy(clk) tDS Dynamic characteristics of SPI pins in SPI mode Parameter PCLK cycle time clock cycle time data set-up time in SPI mode 2.0 V ≤ VDD ≤ 3.6 V 1.8 V ≤ VDD < 2.0 V tDH tv(Q) th(Q) tDS data hold time in SPI mode [2] [2] [2] [1] Conditions Min 20 40 27 36 0 0 0 Typ - Max 10 - Unit ns ns ns ns ns ns ns ns SPI master (in SPI mode) [2] data output valid time in SPI mode data output hold time in SPI mode data set-up time in SPI mode SPI slave (in SPI mode) [3][4] LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 37 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT Table 14. Symbol tDH tv(Q) th(Q) [1] Dynamic characteristics of SPI pins in SPI mode Parameter data hold time Conditions in SPI mode [3][4] [3][4] [3][4] D R R A R A A Min 3 × Tcy(PCLK) + 4 - Typ - Max - Unit ns FT D R A data output valid time in SPI mode data output hold time in SPI mode 3 × Tcy(PCLK) + 11 2 × Tcy(PCLK) + 5 Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). Tamb = −40 °C to 85 °C. Tcy(clk) = 12 × Tcy(PCLK). Tamb = 25 °C; for normal voltage supply range: VDD = 3.3 V. FT D R F A FT FT ns ns D D R A FT D R A [2] [3] [4] Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID CPHA = 1 th(Q) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID th(Q) CPHA = 0 002aae829 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 20. SPI master timing in SPI mode LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 38 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A A FT FT D D R R A FT D D R A D R A FT R R A D R A R A FT A FT A FT D R D R A F FT Tcy(clk) tclk(H) tclk(L) D D R A R A FT SCK (CPOL = 0) FT D R A D FT SCK (CPOL = 1) tDS MOSI DATA VALID tv(Q) MISO DATA VALID DATA VALID tDH DATA VALID th(Q) CPHA = 1 D R A tDS MOSI DATA VALID tv(Q) MISO DATA VALID tDH DATA VALID th(Q) DATA VALID CPHA = 0 002aae830 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 21. SPI slave timing in SPI mode LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 39 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 11. Application information 11.1 ADC usage notes D R The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6: chip. • The ADC input trace must be short and as close as possible to the LPC11C12/C14 • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered. • To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 22. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 22), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 23 and in Table 15 and Table 16. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 23 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 15). LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 40 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A A FT FT D D R R A FT D D R A D R A FT R R A D R A R A FT D D R A FT A FT D R D R A F R FT LPC1xxx L A A FT D R A FT D XTALIN XTALOUT = XTAL CL CP FT D R A RS CX1 CX2 002aaf424 Fig 23. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 15. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Crystal load capacitance CL 10 pF 20 pF 30 pF 5 MHz - 10 MHz 10 pF 20 pF 30 pF 10 MHz - 15 MHz 15 MHz - 20 MHz Table 16. 10 pF 20 pF 10 pF Maximum crystal series resistance RS < 300 Ω < 300 Ω < 300 Ω < 300 Ω < 200 Ω < 100 Ω < 160 Ω < 60 Ω < 80 Ω External load capacitors CX1, CX2 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF Fundamental oscillation frequency FOSC 1 MHz - 5 MHz Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Crystal load capacitance CL 10 pF 20 pF 10 pF 20 pF Maximum crystal series resistance RS < 180 Ω < 100 Ω < 160 Ω < 80 Ω External load capacitors CX1, CX2 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF 39 pF, 39 pF Fundamental oscillation frequency FOSC 15 MHz - 20 MHz 20 MHz - 25 MHz 11.3 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 41 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT D R A A FT FT D D R R A FT D order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. FT D D R A D R A R R A D R A R A FT D FT R A A FT A FT D R D R A F R A FT D FT 11.4 Standard I/O pad configuration • • • • • Digital output driver Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input Figure 24 shows the possible pin modes for standard I/O pins with analog input function: D R A FT D R A VDD output enable pin configured as digital output driver output ESD PIN ESD VDD weak pull-up pull-up enable repeater mode enable pull-down enable weak pull-down VSS pin configured as digital input data input select analog input pin configured as analog input analog input 002aaf304 Fig 24. Standard I/O pad configuration LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 42 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 11.5 Reset pad configuration VDD VDD VDD Rpu D R R A FT D R ESD R A F D R A FT A FT A FT D R A D FT D R A reset 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 25. Reset pad configuration LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 43 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm D R R A FT D R R A F D R A FT A FT A FT D R A SOT313-2 D FT D R A c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) θ Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 26. Package outline SOT313-2 (LQFP48) LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 44 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 13. Abbreviations Table 17. Acronym ADC AHB AMBA APB API BOD CAN GPIO PLL RC SDO SPI SSI SSP TTL UART Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Application Programming Interface BrownOut Detection Controller Area Network General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Service Data Object Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 45 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 14. Revision history Table 18. Revision history Release date Data sheet status Preliminary data sheet Change notice Supersedes Document ID LPC11C12_C14_0.06 Modifications: D R R A FT D R R A F D R A FT A FT A FT D R A D FT • • Corrected pin description: PIO2_4 on pin 18, PIO2_5 on pin 21; PIO3_4 and PIO3_5 are not available. Deep-sleep wake-up pins described in Table note 2 and Section 7.16.5.2. Preliminary data sheet - D R A LPC11C12_C14_0.05 LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 46 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] D R R A FT D R R A F D R A FT A FT A FT D R D Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. A FT D R A Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. © NXP B.V. 2010. All rights reserved. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 00.05 — 6 May 2010 47 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. D R A D R A FT D R A D R A D R A FT D R A FT R R A D R R A FT D R A FT A FT A FT D R FT Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) D D D R R R A A A FT D R A R A FT FT F D R A FT D FT D 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. D R A 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 00.05 — 6 May 2010 48 of 49 D D D R A FT NXP Semiconductors LPC11C12/C14 FT FT FT D D D R R R A A FT D R A FT A FT FT D D R R A FT D D D R A D R A R R A D R A A FT A FT D R FT 17. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.11 7.11.1 7.12 7.12.1 7.13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 9 ARM Cortex-M0 processor . . . . . . . . . . . . . . . . 9 On-chip flash program memory . . . . . . . . . . . . 9 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Nested Vectored Interrupt Controller (NVIC) . 10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 11 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 11 Fast general purpose parallel I/O . . . . . . . . . . 11 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-bus serial I/O controller . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 C_CAN controller . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.14 System tick timer . . . . . . . . . . . . . . . . . . . . . . 14 7.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 14 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.16 Clocking and power control . . . . . . . . . . . . . . 15 7.16.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 15 7.16.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 16 7.16.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 16 7.16.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 17 7.16.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.16.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.16.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 17 7.16.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.16.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.16.5.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 18 D R 7.16.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 7.17 System control . . . . . . . . . . . . . . . . . . . . . . . . 7.17.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.17.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 7.17.3 Code security (Code Read Protection - CRP) 7.17.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 7.17.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.17.6 External interrupt inputs . . . . . . . . . . . . . . . . . 7.17.7 Memory mapping control . . . . . . . . . . . . . . . . 7.18 Emulation and debugging . . . . . . . . . . . . . . . 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9 Static characteristics . . . . . . . . . . . . . . . . . . . 9.1 BOD static characteristics . . . . . . . . . . . . . . . 9.2 Power consumption . . . . . . . . . . . . . . . . . . . 9.3 Electrical pin characteristics. . . . . . . . . . . . . . 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . 11.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 XTAL Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Standard I/O pad configuration . . . . . . . . . . . 11.5 Reset pad configuration . . . . . . . . . . . . . . . . . 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information . . . . . . . . . . . . . . . . . . . . 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. R A FT D R R A F D R A FT D FT D R A A FT 18 18 18 18 19 19 19 19 19 20 21 22 27 27 30 34 34 34 35 36 36 37 40 40 40 41 42 43 44 45 46 47 47 47 47 48 48 49 A FT D R A © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 May 2010 Document identifier: LPC11C12_C14_0