LPC11D14FBD100/302

LPC11D14 32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM; 40 segment x 4 LCD driver Rev. 2 — 23 July 2012 Product data sheet 1. General description The LPC11D14 is a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11D14 is a dual-chip module consisting of a LPC1114 single-chip microcontroller combined with a PCF8576D Universal LCD driver in a low-cost 100-pin package. The LCD driver provides 40 segments and supports from one to four backplanes. Display overhead is minimized by an on-chip display RAM with auto-increment addressing. The LPC11D14 operates at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC11D14 includes 32 kB of flash memory, 8 kB of data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins. Remark: For a functional description of the LPC1114 microcontroller see the LPC1111/12/13/14 data sheet. For a detailed description of the LCD driver see the PCF8576D data sheet. Both data sheets are available on the NXP web site. 2. Features and benefits  LCD driver  40 segments.  One to four backplanes.  On-chip display RAM with auto-increment addressing.  System:  ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.  ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).  Serial Wire Debug.  System tick timer.  Memory:  32 kB on-chip flash programming memory.  8 kB SRAM.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller  Digital peripherals:  42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. In addition, a configurable open-drain mode is supported.  GPIO pins can be used as edge and level sensitive interrupt sources.  High-current output driver (20 mA) on one pin.  High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.  Four general purpose counter/timers with a total of four capture inputs and 13 match outputs.  Programmable windowed WatchDog Timer (WDT).  Analog peripherals:  10-bit ADC with input multiplexing among 8 pins.  Serial interfaces:  UART with fractional baud rate generation, internal FIFO, and RS-485 support.  Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities.  I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.  Clock generation:  12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.  Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock.  Power control:  Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes.  Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call.  Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.  Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins.  Power-On Reset (POR).  Brownout detect with four separate thresholds for interrupt and forced reset.  Unique device serial number for identification.  Single power supply (1.8 V to 3.6 V).  Available as 100-pin LQFP100 package. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 3. Applications     Industrial applications (e.g. thermostats) White goods Human interface Sensors 4. Ordering information Table 1. Ordering information Type number Package Name Description LPC11D14FBD100/302 LQFP100 Version plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 4.1 Ordering options Table 2. Ordering options Type number Flash Total SRAM Power profiles UART RS-485 I2C/ Fast+ SPI ADC channels Package LPC11D14FBD100/302 32 kB 8 kB yes 1 1 2 8 LQFP100 5. Block diagram S[39:0] PIO0, PIO1, PIO2, PIO3 BP[3:0] PCF8576D LPC1114 LCD CONTROLLER MCU VLCD Fig 1. LPC11D14 Product data sheet LCD_SCL, LCD_SDA SCL, SDA 002aag449 LPC11D14 block diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller XTALIN XTALOUT RESET SWD LPC1114 IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS POR ARM CORTEX-M0 system bus clocks and controls FLASH 32 kB slave GPIO ports PIO0/1/2/3 CLKOUT SRAM 8 kB slave ROM slave slave HIGH-SPEED GPIO AHB-LITE BUS slave AHB TO APB BRIDGE RXD TXD DTR, DSR, CTS, DCD, RI, RTS CT32B0_MAT[3:0] CT32B0_CAP0 CT32B1_MAT[3:0] CT32B1_CAP0 CT16B0_MAT[2:0] CT16B0_CAP0 CT16B1_MAT[1:0] CT16B1_CAP0 UART AD[7:0] 10-bit ADC SPI0 SCK0, SSEL0 MISO0, MOSI0 SPI1 SCK1, SSEL1 MISO1, MOSI1 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 SCL SDA I2C-BUS 16-bit COUNTER/TIMER 0 WDT 16-bit COUNTER/TIMER 1 IOCONFIG SYSTEM CONTROL PMU 002aag448 Fig 2. LPC1114 block diagram LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 4 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller BP0 BP2 BP1 S0 to S39 BP3 40 VLCD DISPLAY SEGMENT OUTPUTS BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY REGISTER OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROLLER LCD BIAS GENERATOR VSS(LCD) CLK SYNC VSS(LCD) CLOCK SELECT AND TIMING OSC OSCILLATOR DISPLAY RAM 40 x 4-BIT PCF8576D BLINKER TIMEBASE POWER-ON RESET COMMAND DECODER WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT VDD(LCD) LCD_SCL LCD_SDA INPUT FILTERS I2C-BUS CONTROLLER SA0 SUBADDRESS COUNTER A0 VSS(LCD) A1 A2 VSS(LCD) 002aag451 Fig 3. PCF8576D block diagram LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 77 S31 76 S30 78 S32 79 S33 80 PIO2_2 81 PIO0_8 82 PIO0_9 83 SWCLK/PIO0_10 84 PIO1_10 85 PIO2_11 86 R/PIO0_11 87 R/PIO1_0 88 R/PIO1_1 89 R/PIO1_2 90 PIO3_0 91 PIO3_1 92 PIO2_3 93 SWDIO/PIO1_3 94 PIO1_4 95 VSS 96 PIO1_11 97 PIO3_2 98 VDD 99 PIO1_5 100 PIO1_6 6.1 Pinning PIO1_7 1 75 S29 PIO3_3 2 74 S28 n.c. 3 73 S27 PIO2_6 4 72 S26 PIO2_0 5 71 S25 RESET/PIO0_0 6 70 S24 PIO0_1 7 69 S23 VSS 8 68 S22 XTALIN 9 67 S21 XTALOUT 10 66 S20 VDD 11 65 S19 PIO1_8 12 64 S18 LPC11D14FBD100/302 PIO0_2 13 62 S16 PIO2_8 15 61 S15 PIO2_1 16 60 S14 PIO0_3 17 59 S13 PIO0_4 18 58 S12 PIO0_5 19 57 S11 PIO1_9 20 56 S10 PIO3_4 21 55 S9 PIO2_4 22 54 S8 S4 50 S3 49 S2 48 S1 47 S0 46 BP3 45 BP1 44 BP2 43 BP0 42 VLCD 41 VSS(LCD) 40 VDD(LCD) 39 CLK 38 SYNC 37 LCD_ SCL 36 LCD_ SDA 35 S39 34 S38 33 S37 32 S36 31 51 S5 S35 30 PIO0_6 25 S34 29 52 S6 PIO2_10 28 53 S7 PIO3_5 24 PIO2_9 27 PIO2_5 23 PIO0_7 26 Fig 4. 63 S17 PIO2_7 14 002aag450 Pin configuration LQFP100 package LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3. LPC11D14 pin description table (LQFP100 package) Symbol Pin Start logic input Type Reset state Description [1] Microcontroller pins PIO0_0 to PIO0_11 RESET/PIO0_0 PIO0_1/CLKOUT/ CT32B0_MAT2 PIO0_2/SSEL0/ CT16B0_CAP0 I/O 6[2] 7[3] 13[3] yes yes yes Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I/O I; PU PIO0_2 — General purpose digital input/output pin. I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 17[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 18[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. I/O I; PU PIO0_8 — General purpose digital input/output pin. I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. I/O I; PU PIO0_9 — General purpose digital input/output pin. I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. PIO0_5/SDA 19[4] PIO0_6/SCK0 25[3] PIO0_7/CTS 26[3] PIO0_8/MISO0/ CT16B0_MAT0 81[3] PIO0_9/MOSI0/ CT16B0_MAT1 82[3] LPC11D14 Product data sheet yes yes yes yes yes All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 7 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC11D14 pin description table (LQFP100 package) …continued Symbol Pin SWCLK/PIO0_10/ SCK0/ CT16B0_MAT2 83[3] R/PIO0_11/ AD0/CT32B0_MAT3 86[5] Start logic input Type yes I yes PIO1_0 to PIO1_11 R/PIO1_0/ AD1/CT32B1_CAP0 R/PIO1_1/ AD2/CT32B1_MAT0 R/PIO1_2/ AD3/CT32B1_MAT1 SWDIO/PIO1_3/ AD4/CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP LPC11D14 Product data sheet Reset state [1] I; PU 88[5] 89[5] 93[5] 94[5] yes no no no no SWCLK — Serial wire clock. I/O - PIO0_10 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I/O 87[5] Description Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. O I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output. I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch filter. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. I - WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 8 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC11D14 pin description table (LQFP100 package) …continued Symbol PIO1_5/RTS/ CT32B0_CAP0 Pin 99[3] PIO1_6/RXD/ CT32B0_MAT0 100[3] PIO1_7/TXD/ CT32B0_MAT1 1[3] PIO1_8/ CT16B1_CAP0 12[3] PIO1_9/ CT16B1_MAT0 20[3] PIO1_10/AD6/ CT16B1_MAT1 84[5] PIO1_11/AD7 96[5] Start logic input Type no I/O no no no no no no PIO2_0 to PIO2_11 PIO2_0/DTR/SSEL1 PIO2_1/DSR/SCK1 PIO2_2/DCD/MISO1 PIO2_3/RI/MOSI1 Reset state [1] I; PU 16[3] 80[3] 92[3] no no no no PIO1_5 — General purpose digital input/output pin. O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. I/O I; PU PIO1_6 — General purpose digital input/output pin. I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. I/O I; PU PIO1_8 — General purpose digital input/output pin. I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. I/O I; PU PIO1_9 — General purpose digital input/output pin. O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. I/O I; PU PIO1_10 — General purpose digital input/output pin. I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O I; PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. I/O 5[3] Description Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I/O I; PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O - SSEL1 — Slave Select for SPI1. I/O I; PU PIO2_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O - SCK1 — Serial clock for SPI1. I/O I; PU PIO2_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. I/O - MISO1 — Master In Slave Out for SPI1. I/O I; PU PIO2_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. I/O - MOSI1 — Master Out Slave In for SPI1. PIO2_4 22[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin. PIO2_5 23[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin. PIO2_6 4[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin. PIO2_7 14[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin. PIO2_8 15[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin. PIO2_9 27[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC11D14 pin description table (LQFP100 package) …continued Symbol Pin Start logic input Type I/O PIO2_10 28[3] no PIO2_11/SCK0 85[3] no PIO3_0 to PIO3_5 Reset state [1] I; PU PIO2_10 — General purpose digital input/output pin. I/O I; PU PIO2_11 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. I/O PIO3_0/DTR 90[3] PIO3_1/DSR 91[3] PIO3_2/DCD 97[3] PIO3_3/RI 2[3] no no no no Description Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. I/O I; PU PIO3_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O I; PU PIO3_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O I; PU PIO3_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. I/O I; PU PIO3_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. PIO3_4 21[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin. PIO3_5 24[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin. VDD 11; 98 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 9[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 10[6] - O - Output from the oscillator amplifier. VSS 8; 95 - I - Ground. S0 46 - O VLCD[7] LCD segment output. S1 47 - O VLCD[7] LCD segment output. S2 48 - O VLCD[7] LCD segment output. S3 49 - O VLCD[7] LCD segment output. S4 50 - O VLCD[7] LCD segment output. S5 51 - O VLCD[7] LCD segment output. S6 52 - O VLCD[7] LCD segment output. S7 53 - O VLCD[7] LCD segment output. S8 54 - O VLCD[7] LCD segment output. S9 55 - O VLCD[7] LCD segment output. S10 56 - O VLCD[7] LCD segment output. S11 57 - O VLCD[7] LCD segment output. S12 58 - O VLCD[7] LCD segment output. S13 59 - O VLCD[7] LCD segment output. S14 60 - O VLCD[7] LCD segment output. S15 61 - O VLCD[7] LCD segment output. S16 62 - O VLCD[7] LCD segment output. LCD display pins LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 10 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC11D14 pin description table (LQFP100 package) …continued Symbol Pin Start logic input Type Reset state Description [1] S17 63 - O VLCD[7] LCD segment output. S18 64 - O VLCD[7] LCD segment output. S19 65 - O VLCD[7] LCD segment output. S20 66 - O VLCD[7] LCD segment output. S21 67 - O VLCD[7] LCD segment output. S22 68 - O VLCD[7] LCD segment output. S23 69 - O VLCD[7] LCD segment output. S24 70 - O VLCD[7] LCD segment output. S25 71 - O VLCD[7] LCD segment output. S26 72 - O VLCD[7] LCD segment output. S27 73 - O VLCD[7] LCD segment output. S28 74 - O VLCD[7] LCD segment output. S29 75 - O VLCD[7] LCD segment output. S30 76 - O VLCD[7] LCD segment output. S31 77 - O VLCD[7] LCD segment output. S32 78 - O VLCD[7] LCD segment output. S33 79 - O VLCD[7] LCD segment output. S34 29 - O VLCD[7] LCD segment output. S35 30 - O VLCD[7] LCD segment output. S36 31 - O VLCD[7] LCD segment output. S37 32 - O VLCD[7] LCD segment output. S38 33 - O VLCD[7] LCD segment output. S39 34 - O VLCD[7] LCD segment output. BP0 42 - O VLCD[7] LCD backplane output. BP1 44 - O VLCD[7] LCD backplane output. BP2 43 - O VLCD[7] LCD backplane output. BP3 45 - O VLCD[7] LCD backplane output. LCD_SDA 35 - I/O [7] I2C-bus serial data input/output. LCD_SCL 36 - I/O [7] I2C-bus serial clock input. SYNC 37 - I/O [7] Cascade synchronization input/output. CLK 38 - I/O [7] External clock input/output. VDD(LCD) 39 - - - 1.8 V to 5.5 V power supply: Power supply voltage for the PCF8576D. VSS(LCD) 40 - - - LCD ground. The PCF8576 input signals A0, A1, A2, SA0, and OSC are internally hard-wired to VSS(LCD). VLCD 41 - - - LCD power supply; LCD voltage. n.c. 3 - - - Not connected. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level (VDD = 3.3 V)); IA = inactive, no pull-up/down enabled. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [2] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. [7] See Section 7.2.3. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 12 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 LPC1114 microcontroller See Ref. 1 for a detailed functional description of the LPC1114 microcontroller. 7.2 LCD driver See Ref. 2 for a detailed functional description of the PCF8576D LCD driver. 7.2.1 General description The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily cascaded for larger LCD applications. The PCF8576D communicates via the two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). Please refer to PCF8576D data sheet for electrical data. 7.2.2 Functional description The PCF8576D is a versatile peripheral device interfacing the LPC1114 microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The possible display configurations of the PCF8576D depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. The integration of the LPC1114 microcontroller with the PCF8576D is shown in Figure 1. Table 4. Selection of display configurations Number of Digits/Characters Backplanes Segments 7-segment 14-segment Dot matrix/Elements 4 160 20 10 160 (4  40) 3 120 15 7 120 (3  40) 2 80 10 5 64 (2  40) 1 40 5 2 40 (1  40) 7.2.3 Reset state of the LCD controller and pins After power-on, the LCD controller resets to the following starting conditions: • • • • • • • LPC11D14 Product data sheet All backplane and segment outputs are set to VLCD. The selected drive mode is 1:4 multiplex with 1/3 bias. Blinking is switched off. Input and output bank selectors are reset. The I2C-bus interface is initialized. The data pointer and the subaddress counter are cleared (set to logic 0). The display is disabled. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 13 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2.4 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS(LCD). The middle resistor can be bypassed to provide a 1/2 bias voltage level for the 1:2 multiplex configuration. The LCD voltage can be temperature compensated externally using the supply to pin VLCD. 7.2.5 Oscillator 7.2.5.1 Internal clock The internal logic of the PCF8576D and the LCD drive signals are timed by the internal oscillator. The internal oscillator is always enabled. The output from pin CLK can be used as the clock signal for several PCF8576Ds in the system that are connected in cascade. 7.2.6 Timing The PCF8576D timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCF8576D in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency (ffr) is a fixed division of the clock frequency (fclk) from either the internal or an external clock: ffr = fclk/24. 7.2.7 Display register A display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs, and each column of the display RAM. 7.2.8 Segment outputs The LCD drive section includes 40 segment outputs S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 7.2.9 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 14 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.2.10 Display RAM The display RAM is a static 40  4-bit RAM which stores LCD data. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. For details, see Ref. 2. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 15 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions VDD supply voltage (core and external rail) [2] Min Max Unit 1.8 3.6 V 0.5 +5.5 V VI input voltage 5 V tolerant I/O pins; only valid when the VDD supply voltage is present IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); - 100 mA 65 +150 C - 150 C - 1.5 W 6500 +6500 V Tj < 125 C Tstg storage temperature non-operating Tj(max) maximum junction temperature Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption VESD electrostatic discharge voltage human body model; all pins [1] [3] [4] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 16 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 6. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) Min Typ[1] Max Unit 1.8 3.3 3.6 V - 2 - mA - 7 - mA - 1 - mA [2][3][8] - 2 - A [2][9] - 220 - nA Conditions Power consumption in low-current mode[10] IDD supply current Active mode; code while(1){} executed from flash system clock = 12 MHz [2][3][4] [5][6] VDD = 3.3 V system clock = 50 MHz [2][3][5] [6][7] VDD = 3.3 V Sleep mode; [2][3][4] [5][6] system clock = 12 MHz VDD = 3.3 V Deep-sleep mode; VDD = 3.3 V Deep power-down mode; VDD = 3.3 V Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V [11][12] VO output voltage 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage VOH HIGH-level output voltage VOL LPC11D14 Product data sheet LOW-level output voltage output active [13] - 0.4 - V 2.5 V  VDD  3.6 V; IOH = 4 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 3 mA VDD  0.4 - - V 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 17 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOH HIGH-level output current VOH = VDD  0.4 V; 4 - - mA 3 - - mA 4 - - mA 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V IOL LOW-level output current VOL = 0.4 V 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V 3 - - mA - - 45 mA - - 50 mA IOHS HIGH-level short-circuit VOH = 0 V output current [14] IOLS LOW-level short-circuit output current VOL = VDD [14] Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 15 50 85 A 10 50 85 A 0 0 0 A 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V VDD < VI < 5 V High-drive output pin (PIO0_7) IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V 0 - VDD V [11][12] [13] VO output voltage VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V VDD 3.6 V; IOH = 20 mA VDD  0.4 - - V 1.8 V VDD < 2.5 V; IOH = 12 mA VDD  0.4 - - V 2.5 V VDD 3.6 V; IOL = 4 mA - - 0.4 V 1.8 V VDD < 2.5 V; IOL = 3 mA - - 0.4 V VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 12 - - mA VOL IOH LPC11D14 Product data sheet LOW-level output voltage HIGH-level output current output active All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 18 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL LOW-level output current VOL = 0.4 V 4 - - mA 3 - - mA - - 50 mA 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V [14] IOLS LOW-level short-circuit output current VOL = VDD Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V 15 50 85 A 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V VDD < VI < 5 V I2C-bus 10 50 85 A 0 0 0 A pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V 3.5 - - mA LOW-level output current IOL I2C-bus VOL = 0.4 V; pins configured as standard mode pins 2.5 V  VDD  3.6 V LOW-level output current IOL 1.8 V  VDD < 2.5 V 3 - - VOL = 0.4 V; I2C-bus pins configured as Fast-mode Plus pins 20 - - 16 - - - 2 4 A - 10 22 A mA 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V input leakage current ILI VI = VDD VI = 5 V [15] Oscillator pins Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Tamb = 25 C. [3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] BOD disabled. [6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [7] IRC disabled; system oscillator enabled; system PLL enabled. [8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [9] WAKEUP pin pulled HIGH externally. [10] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [11] Including voltage on outputs in 3-state mode. [12] VDD supply voltage must be present. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 19 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [13] 3-state outputs go into 3-state mode in Deep power-down mode. [14] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [15] To VSS. Table 7. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage Cia analog input capacitance Conditions Min Typ Max Unit 0 - VDD V pF - - 1 [1][2] ED differential linearity error - - 1 LSB EL(adj) integral non-linearity [3] - -  1.5 LSB EO offset error [4] - -  3.5 LSB gain error [5] - - 0.6 % [6] EG ET absolute error Rvsi voltage source interface resistance Ri input resistance [7][8] - - 4 LSB - - 40 k - - 2.5 M [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 5. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 5. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 5. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 5. [7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia). LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 20 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 5. ADC characteristics LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 21 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics Table 8. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion - 1.65 - V de-assertion - 1.80 - V assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V interrupt level 1 interrupt level 2 interrupt level 3 reset level 0 assertion - 1.46 - V de-assertion - 1.63 - V assertion - 2.06 - V de-assertion - 2.15 - V assertion - 2.35 - V de-assertion - 2.43 - V assertion - 2.63 - V de-assertion - 2.71 - V reset level 1 reset level 2 reset level 3 [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 22 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf980 10 IDD (mA) 8 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 6. Active mode: Typical supply current IDD versus supply voltage VDD for different system clock frequencies 002aaf981 10 IDD (mA) 8 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 7. LPC11D14 Product data sheet Active mode: Typical supply current IDD versus temperature for different system clock frequencies All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 23 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf982 6 IDD (mA) 48 MHz(2) 4 36 MHz(2) 24 MHz(2) 2 12 MHz(1) 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 8. LPC11D14 Product data sheet Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 24 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf977 5.5 IDD (μA) 4.5 3.5 VDD = 3.3 V, 3.6 V 1.8 V 2.5 1.5 −40 −15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 9. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD 002aaf978 0.8 IDD (μA) VDD = 3.6 V 3.3 V 1.8 V 0.6 0.4 0.2 0 −40 −15 10 35 60 85 temperature (°C) Fig 10. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 25 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz. Table 9. Power consumption for individual analog and digital blocks Peripheral LPC11D14 Product data sheet Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.004 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.051 - - Independent of main clock frequency. Main PLL - 0.21 - ADC - 0.08 0.29 CLKOUT - 0.12 0.47 CT16B0 - 0.02 0.06 CT16B1 - 0.02 0.06 CT32B0 - 0.02 0.07 CT32B1 - 0.02 0.06 GPIO - 0.23 0.88 IOCONFIG - 0.03 0.10 I2C - 0.04 0.13 ROM - 0.04 0.15 SPI0 - 0.12 0.45 SPI1 - 0.12 0.45 UART - 0.22 0.82 WDT - 0.02 0.06 Main clock divided by 4 in the CLKOUTDIV register. GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. Main clock selected as clock source for the WDT. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 26 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.4 Electrical pin characteristics 002aae990 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 11. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aaf019 60 T = 85 °C 25 °C −40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 12. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 27 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae991 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 14. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 28 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 15. Typical pull-up current Ipu versus input voltage VI 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 16. Typical pull-down current Ipd versus input voltage VI LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 29 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Power-up ramp conditions Table 10. Power-up characteristics Tamb = 40 C to +85 C. Symbol Parameter tr rise time twait wait time VI input voltage Conditions Min at t = t1: 0 < VI 400 mV [1] [1][2] at t = t1 on pin VDD Typ Max Unit 0 - 500 ms 12 - - s 0 - 400 mV [1] See Figure 17. [2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up. tr VDD 400 mV 0 twait t = t1 002aag001 Condition: 0 < VI 400 mV at start of power-up (t = t1) Fig 17. Power-up ramp 10.2 Flash memory Table 11. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol LPC11D14 Product data sheet Parameter Conditions Min [1] Nendu endurance tret retention time ter erase time tprog programming time Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.05 ms [2] [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 30 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.3 External clock Table 12. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Symbol Parameter fosc Conditions Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 18. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 31 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.4 Internal oscillators Table 13. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V.[1] Symbol Parameter Conditions fosc(RC) internal RC oscillator frequency - Min Typ[2] Max Unit 11.88 12 12.12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 002aaf403 12.15 f (MHz) VDD = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V 12.05 11.95 11.85 −40 −15 10 35 60 85 temperature (°C) Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 19. Internal RC oscillator frequency versus temperature Table 14. Dynamic characteristics: Watchdog oscillator Min Typ[1] Max Unit internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; [2][3] - 9.4 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 2300 - kHz Symbol Parameter fosc(int) LPC11D14 Product data sheet Conditions [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %. [3] See the LPC111x user manual. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 32 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.5 I/O pins Table 15. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 10.6 I2C-bus Table 16. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns 20 + 0.1  Cb 300 ns [4][5][6][7] fall time tf Standard-mode Fast-mode Fast-mode Plus tLOW tHIGH tHD;DAT tSU;DAT [1] LPC11D14 Product data sheet LOW period of the SCL clock HIGH period of the SCL clock data hold time data set-up time [3][4][8] [9][10] - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 33 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 20. I2C-bus pins clock timing 10.7 SPI interfaces Table 17. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit - - ns SPI master (in SPI mode) Tcy(clk) tDS clock cycle time data set-up time full-duplex mode [1] 50 when only transmitting [1] 40 in SPI mode [2] 15 2.0 V  VDD < 2.4 V [2] 20 1.8 V  VDD < 2.0 V [2] 24 - - ns ns - - ns 2.4 V  VDD  3.6 V ns tDH data hold time in SPI mode [2] 0 - - ns tv(Q) data output valid time in SPI mode [2] - - 10 ns data output hold time in SPI mode [2] 0 - - ns th(Q) LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 34 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI slave (in SPI mode) Tcy(PCLK) PCLK cycle time data set-up time tDS 20 - - ns in SPI mode [3][4] 0 - - ns tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - ns tv(Q) data output valid time in SPI mode [3][4] - - 3  Tcy(PCLK) + 11 ns th(Q) data output hold time in SPI mode [3][4] - - 2  Tcy(PCLK) + 5 ns [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = 40 C to +85 C. [3] Tcy(clk) = 12  Tcy(PCLK). [4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V. Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI DATA VALID th(Q) DATA VALID tDH tDS MISO DATA VALID CPHA = 1 CPHA = 0 DATA VALID 002aae829 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 21. SPI master timing in SPI mode LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 35 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) tclk(H) tclk(L) tDS tDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 22. SPI slave timing in SPI mode LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 36 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 7: • The ADC input trace must be short and as close as possible to the LPC11D14 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered. • To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion. 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV (RMS) is needed. LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 23. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 23), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 24 and in Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 24 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 18). LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 37 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1xxx L XTALIN XTALOUT = CL CP XTAL RS CX2 CX1 002aaf424 Fig 24. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz - 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 19. 30 pF < 300  57 pF, 57 pF 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 10 pF < 80  18 pF, 18 pF Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz - 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz - 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF 11.3 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 38 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of CX1 and CX2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 11.4 Standard I/O pad configuration Figure 25 shows the possible pin modes for standard I/O pins with analog input function: • • • • • Digital output driver Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input VDD VDD open-drain enable pin configured as digital output driver strong pull-up output enable ESD data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable pin configured as digital input weak pull-down repeater mode enable pull-down enable data input select analog input pin configured as analog input analog input 002aah159 Fig 25. Standard I/O pad configuration LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 39 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.5 Reset pad configuration VDD VDD VDD Rpu ESD 20 ns RC GLITCH FILTER reset PIN ESD VSS 002aaf274 Fig 26. Reset pad configuration 11.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC 61967-2 standard using the TEM-cell method are shown for the LPC1114FBD48/302 in Table 20. Table 20. ElectroMagnetic Compatibility (EMC) for part LPC1114FBD48/302 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C. Parameter Frequency band System clock = Unit 12 MHz 24 MHz 48 MHz 150 kHz - 30 MHz 7 5 7 dBV 30 MHz - 150 MHz 2 1 10 dBV Input clock: IRC (12 MHz) maximum peak level IEC level[1] 150 MHz - 1 GHz 4 8 16 dBV - O N M - Input clock: crystal oscillator (12 MHz) maximum peak level LPC11D14 Product data sheet 150 kHz - 30 MHz 7 7 7 dBV 30 MHz - 150 MHz 2 1 8 dBV 150 MHz - 1 GHz 4 7 14 dBV - O N M - IEC level[1] [1] IEC levels refer to Appendix D in the IEC 61967-2 Specification. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 40 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT407-1 136E20 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Fig 27. Package outline (LQFP100) LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 41 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Soldering Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.550 sot407-1 Fig 28. Reflow soldering of the LQFP100 package LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 42 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations Table 21. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter 15. References LPC11D14 Product data sheet [1] LPC1111/12/13/14 Data sheet [2] PCF8576D Data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 43 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 16. Revision history Table 22. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11D14 v.2 20120723 Product data sheet - LPC11D14 v.1 Modifications: LPC11D14 v.1 LPC11D14 Product data sheet • • • • • Figure 3 updated. • For parameters IOL, VOL, IOH, VOH, changed conditions to 1.8 V  VDD < 2.5 V and 2.5 V  VDD  3.6 V in Table 6. • • Figure 25 updated for parts with configurable open-drain mode. Internal oscillator description updated (Section 7.2.5). Description of the VSS(LCD) pin updated in Table 3. Data sheet status changed to Product data sheet. Remove table note “The peak current is limited to 25 times the corresponding maximum current” in Table 5. WDOSc frequency range corrected. 20110928 Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 - © NXP B.V. 2012. All rights reserved. 44 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. LPC11D14 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 45 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC11D14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 23 July 2012 © NXP B.V. 2012. All rights reserved. 46 of 47 LPC11D14 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 19. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.5.1 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 8 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 11 11.1 11.2 11.3 11.4 11.5 11.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 13 LPC1114 microcontroller. . . . . . . . . . . . . . . . . 13 LCD driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General description . . . . . . . . . . . . . . . . . . . . 13 Functional description. . . . . . . . . . . . . . . . . . . 13 Reset state of the LCD controller and pins . . . 13 LCD bias generator . . . . . . . . . . . . . . . . . . . . 14 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Display register . . . . . . . . . . . . . . . . . . . . . . . . 14 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 BOD static characteristics. . . . . . . . . . . . . . . . 22 Power consumption . . . . . . . . . . . . . . . . . . . . 22 Peripheral power consumption . . . . . . . . . . . . 26 Electrical pin characteristics . . . . . . . . . . . . . . 27 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 Power-up ramp conditions . . . . . . . . . . . . . . . 30 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 30 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 31 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 32 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 34 Application information. . . . . . . . . . . . . . . . . . 37 ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 37 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 XTAL Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Standard I/O pad configuration . . . . . . . . . . . . 39 Reset pad configuration . . . . . . . . . . . . . . . . . 40 ElectroMagnetic Compatibility (EMC) . . . . . . . 40 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 42 43 43 44 45 45 45 45 46 46 47 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 July 2012 Document identifier: LPC11D14