LPC1756FBD80

UM10360 LPC17xx User manual Rev. 01 — 4 January 2010 User manual Document information Info Keywords Content LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller LPC17xx user manual Abstract NXP Semiconductors UM10360 LPC17xx user manual Revision history Rev 1 Date 20100104 Description LPC17xx user manual revision. Modifications: • • • • • • “Draft” status removed. Editorial updates and typographical corrections throughout the user manual. LPC1758, LPC1767, and LPC1768 have been added to the keywords list on the front cover, the ordering information in section Section 1–4, and the part identification number table in Section 32–7.11. The note about DMA operation in Sleep mode was removed from Section 4–8.1. In Table 8–81, the CLKOUT function was removed from the description of P1.25. In section the Ethernet chapter, in Section 10–16.1 and Section 10–17.2, it has been noted that the external PHY must be initialized and PHY clocks received by the Ethernet block prior to further initialization of the Ethernet block. Also, in Section 10–17.1, under the heading "Ownership of descriptors", the sentence about AHB arbitration was removed. A general and more correct discussion of the subject was added in Section 2–5. The UART fractional baud rate generator is disabled in auto baud mode (see Section 14–14.4.10.1 and Section 15–4.14). In section Section 14–4.12 and Section 15–4.16, the description of the value of the DLL register has been is corrected to read "the value of the DLL register must be greater than 2". *** Motor Control PWM *** The description of RPM calculation in the QEI chapter (see Section 26–4.3), definitions for the formula values are added, and the description improved. The description of the position and index compare registers incorrectly indicated that the less than,equal to, and greater than compare could be selected. It is changed to only indicate “equal to”. A description of Flash signature generation has been added in Section 32–10. • • • • • Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 2 of 835 UM10360 Chapter 1: LPC17xx Introductory information Rev. 01 — 4 January 2010 User manual 1. Introduction The LPC17xx is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a next generation core that offers system enhancements such as modernized debug features and a higher level of support block integration. High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches. The peripheral complement of the LPC17xx includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, a USB interface that can be configured as either Host, Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C interfaces, 2-input plus 2-output I2S interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70 general purpose I/O pins. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 3 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 2. Features Refer to Section 1–4.1 for details of features on specific part numbers. • ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory Protection Unit (MPU) supporting eight regions is included. • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). • Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash. • Up to 64 kB on-chip SRAM includes: – Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. – Up to two 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose instruction and data storage. • Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers. • Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time. • Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy. • Serial interfaces: – Ethernet MAC with RMII interface and dedicated DMA controller. – USB 2.0 full-speed controller that can be configured for either device, Host, or OTG operation with an on-chip PHY for device and Host functions and a dedicated DMA controller. – Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support. – Two-channel CAN controller. – Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. – SPI controller with synchronous, serial, full duplex communication and programmable data length. SPI is included as a legacy peripheral and can be used instead of SSP0. – Three enhanced I2C-bus interfaces, one with an open-drain output supporting the full I2C specification and Fast mode plus with data rates of 1Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 4 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information – I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S interface can be used with the GPDMA. The I2S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output. • Other peripherals: – 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access, and support Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt. – 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. – 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. – Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. – One motor control PWM with support for three-phase motor control. – Quadrature encoder interface that can monitor one external quadrature encoder. – One standard PWM/timer block with external count input. – Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V Lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode. – Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. – Cortex-M3 system tick timer, including an external clock input option. – Repetitive interrupt timer provides programmable and repeating timed interrupts. • Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire Trace Port options. • Emulation trace module supports real-time trace. • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. • Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C. • Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources. • Non-maskable Interrupt (NMI) input. • Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, or the USB clock. • The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 5 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI). • • • • • Each peripheral has its own clock divider for further power savings. Brownout detect with separate threshold for interrupt and forced reset. On-chip Power-On Reset (POR). On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz. 4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock. for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. • An on-chip PLL allows CPU operation up to the maximum CPU rate without the need • A second, dedicated PLL may be used for the USB interface in order to allow added flexibility for the Main PLL settings. • Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions. • Available as 100-pin LQFP (14 x 14 x 1.4 mm) and 80-pin LQFP (12 x 12 x 1.4 mm) packages. 3. Applications • • • • • • eMetering Lighting Industrial networking Alarm systems White goods Motor control UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 6 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 4. Ordering information Table 1. Ordering information Package Name LPC1769FBD100 LPC1768FBD100 LPC1767FBD100 LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1759FBD80 LPC1758FBD80 LPC1756FBD80 LPC1754FBD80 LPC1752FBD80 LPC1751FBD80 LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm SOT315-1 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 Description Version Type number 4.1 Part options summary Table 2. Ordering options for LPC17xx parts Max. CPU speed 120 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 120 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz Flash 512 kB 512 kB 512 kB 256 kB 256 kB 128 kB 512 kB 512 kB 256 kB 128 kB 64 kB 32 kB Total SRAM 64 kB 64 kB 64 kB 64 kB 64 kB 32 kB 64 kB 64 kB 32 kB 32 kB 16 kB 8 kB Ethernet yes yes yes yes no yes no yes no no no no USB Device/Host/OTG Device/Host/OTG no Device/Host/OTG Device/Host/OTG Device Device/Host/OTG Device/Host/OTG Device/Host/OTG Device/Host/OTG Device Device CAN 2 2 no 2 2 2 2 2 2 1 1 1 I2S yes yes yes yes yes no yes yes yes no no no DAC yes yes yes yes yes no yes yes yes yes no no Package 100 pin 100 pin 100 pin 100 pin 100 pin 100 pin 80 pin 80 pin 80 pin 80 pin 80 pin 80 pin Type number LPC1769FBD100 LPC1768FBD100 LPC1767FBD100 LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1759FBD80 LPC1758FBD80 LPC1756FBD80 LPC1754FBD80 LPC1752FBD80 LPC1751FBD80 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 7 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 5. Simplified block diagram Ethernet PHY interface Xtalin Trace Port JTAG interface USB interface Trace Module Test/Debug Interface ARM Cortex-M3 D-code bus I-code bus DMA controller Ethernet 10/100 MAC USB device, host, OTG Clocks and Controls Clock Generation, Power Control, Brownout Detect, and other system functions Flash Accelerator High Speed GPIO Multilayer AHB Matrix SRAM 64 kB ROM 8 kB AHB to APB bridge APB slave group 0 SSP1 UARTs 0 & 1 CAN 1 & 2 I2C 0 & 1 SPI0 Capture/Compare Timers 0 & 1 Watchdog Timer AHB to APB bridge APB slave group 1 SSP0 UARTs 2 & 3 I2S I2C2 Repetitive Interrupt Timer Capture/Compare Timers 2 & 3 External Interrupts PWM1 DAC 12-bit ADC System Control Pin Connect Block Motor Control PWM GPIO Interrupt Ctl Quadrature Encoder 32 kHz oscillator Real Time Clock 20 bytes of backup registers RTC Power Domain Note: shaded peripheral blocks support General Purpose DMA Fig 1. LPC1768 simplified block diagram UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 Xtalout Flash 512 kB RST System bus 8 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 6. Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. Details of the multilayer matrix connections are shown in Figure 1–2. APB peripherals are connected to the CPU via two APB busses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller. The APB bus bridges are configured to buffer writes so that the CPU or DMA controller can write to APB devices without always waiting for APB write completion. 7. ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with Wakeup Interrupt Controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is appended to this manual. 7.1 Cortex-M3 Configuration Options The LPC17xx uses the r2p0 version of the Cortex-M3 CPU, which includes a number of configurable options, as noted below. System options: • The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the SYSTICK timer. • The Wakeup Interrupt Controller (WIC) is included. The WIC allows more powerful options for waking up the CPU from reduced power modes. • A Memory Protection Unit (MPU) is included. • A ROM Table in included. The ROM Table provides addresses of debug components to external debug systems. Debug related options: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 9 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information • A JTAG debug interface is included. • Serial Wire Debug is included. Serial Wire Debug allows debug operations using only 2 wires, simple trace functions can be added with a third wire. • The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction trace capabilities. • The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data address or data value matches to be trace information or trigger other events. The DWT includes 4 comparators and counters for certain internal events. • An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in order to send messages to the trace port. • The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides trace information to the outside world. This can be on the Serial Wire Viewer pin or the 4-bit parallel trace port. • A Flash Patch and Breakpoint (FPB) is included. The FPB can generate hardware breakpoints and remap specific addresses in code space to SRAM as a temporary method of altering non-volatile code. The FPB include 2 literal comparators and 6 instruction comparators. 8. On-chip flash memory system The LPC17xx contains up to 512 kB of on-chip flash memory. A new two-port flash memory accelerator maximizes performance for use with the two fast AHB-Lite buses. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. 9. On-chip Static RAM The LPC17xx contains up to 64 kB of on-chip static RAM memory. Up to 32 kB of SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus. Devices containing more than 32 kB SRAM have two additional 16 kB SRAM blocks, each situated on separate slave ports on the AHB multilayer matrix. This architecture allows the possibility for CPU and DMA accesses to be separated in such a way that there are few or no delays for the bus masters. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 10 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 10. Block diagram JTAG interface TEST/DEBUG INTERFACE Ethernet PHY interface USB interface Xtalin X32Kin Debug Port EMULATION TRACE MODULE DMA controller ARM Cortex-M3 I-code bus D-code bus Ethernet 10/100 MAC USB device, host, OTG clocks and controls internal power clock generation, CLK power control, OUT and other system functions Vdd voltage regulator System bus Flash Accelerator SRAM 32 kB SRAM 16 kB SRAM 16 kB DMAC regs USB regs Ethernet regs HS GPIO Flash 512 kB ROM 8 kB Multilayer AHB Matrix APB slave group 0 SSP1 UARTs 0 & 1 CAN 1 & 2 I2C 0 & 1 SPI0 Capture/compare timers 0 & 1 Watchdog timer PWM1 12-bit ADC Pin connect block GPIO interrupt control 32 kHz oscillator Real Time Clock AHB to APB bridge AHB to APB bridge APB slave group 1 SSP0 UARTs 2 & 3 I2S I2C2 Capture/compare timers 2 & 3 Repetitive interrupt timer External interrupts DAC System control Motor control PWM Quadrature encoder Note: shaded peripheral blocks support General Purpose DMA Vbat ultra-low power Backup registers regulator (20 bytes) RTC Power Domain Fig 2. LPC1768 block diagram, CPU and buses UM10360_1 X32Kout Xtalout User manual Rev. 01 — 4 January 2010 RST © NXP B.V. 2010. All rights reserved. 11 of 835 UM10360 Chapter 2: LPC17xx Memory map Rev. 01 — 4 January 2010 User manual 1. Memory map and peripheral addressing The ARM Cortex-M3 processor has a single 4 GB address space. The following table shows how this space is used on the LPC17xx. Table 3. LPC17xx memory usage and details General Use Address range details and description Address range 0x0000 0000 to 0x1FFF FFFF On-chip non-volatile memory 0x0000 0000 - 0x0007 FFFF 0x0000 0000 - 0x0003 FFFF 0x0000 0000 - 0x0001 FFFF 0x0000 0000 - 0x0000 FFFF 0x0000 0000 - 0x0000 7FFF For devices with 512 kB of flash memory. For devices with 256 kB of flash memory. For devices with 128 kB of flash memory. For devices with 64 kB of flash memory. For devices with 32 kB of flash memory. For devices with 32 kB of local SRAM. For devices with 16 kB of local SRAM. For devices with 8 kB of local SRAM. 8 kB Boot ROM with flash services. AHB SRAM - bank 0 (16 kB), present on devices with 32 kB or 64 kB of total SRAM. AHB SRAM - bank 1 (16 kB), present on devices with 64 kB of total SRAM. GPIO. APB0 Peripherals, up to 32 peripheral blocks, 16 kB each. APB1 Peripherals, up to 32 peripheral blocks, 16 kB each. DMA Controller, Ethernet interface, and USB interface. Cortex-M3 related functions, includes the NVIC and System Tick Timer. On-chip SRAM 0x1000 0000 - 0x1000 7FFF 0x1000 0000 - 0x1000 3FFF 0x1000 0000 - 0x1000 1FFF Boot ROM 0x2000 0000 to 0x3FFF FFFF On-chip SRAM (typically used for peripheral data) GPIO 0x4000 0000 to 0x5FFF FFFF APB Peripherals 0x1FFF 0000 - 0x1FFF 1FFF 0x2007 C000 - 0x2007 FFFF 0x2008 0000 - 0x2008 3FFF 0x2009 C000 - 0x2009 FFFF 0x4000 0000 - 0x4007 FFFF 0x4008 0000 - 0x400F FFFF AHB peripherals 0xE000 0000 to 0xE00F FFFF Cortex-M3 Private Peripheral Bus 0x5000 0000 - 0x501F FFFF 0xE000 0000 - 0xE00F FFFF 2. Memory maps The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 2–3 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 12 of 835 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx User manual Rev. 01 — 4 January 2010 © NXP B.V. 2010. All rights reserved. UM10360_1 NXP Semiconductors 0x4010 0000 0x400F C000 0x400C 0000 0x400B C000 0x400B 8000 0x400B 4000 0x400B 0000 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 0x4009 C000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 C000 0x4008 8000 0x4008 0000 15 14 13 11 10 9 8 7 6 5 4 3 2 31 APB1 peripherals system control 30 - 16 reserved QEI motor control PWM reserved reserved I2S reserved I2C2 UART3 UART2 Timer 3 Timer 2 DAC SSP0 1 - 0 reserved 4 GB LPC1768 memory space 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus reserved 0x5020 0000 AHB periherals reserved 0x4400 0000 peripheral bit band alias addressing reserved APB1 peripherals 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 23 0x2400 0000 AHB SRAM bit band alias addressing 0x2200 0000 reserved GPIO 0x2009 C000 reserved 0x2008 4000 0x2007 C000 0x1FFF 2000 0x1FFF 0000 0x1000 8000 0x1000 0000 AHB SRAM (2 blocks of 16 kB) reserved 8 kB boot ROM reserved 0x200A 0000 18 17 16 15 14 13 12 11 10 9 8 7 6 0x0008 0000 5 4 3 2 1 0 APB0 peripherals 31 - 24 reserved I2C1 22 - 19 reserved CAN2 CAN1 CAN common CAN AF registers CAN AF RAM ADC SSP1 pin connect GPIO interrupts RTC + backup registers SPI I2C0 PWM1 reserved UART1 UART0 TIMER1 TIMER0 WDT 0x5000 0000 2 1 0 0xE000 0000 3 AHB peripherals 127- 4 reserved USB controller reserved GPDMA controller Ethernet controller 0x5000 C000 0x5000 8000 0x5000 4000 0x5000 0000 0x5020 0000 12 repetitive interrupt timer 0x4008 0000 0x4006 0000 0x4005 C000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 1 GB APB0 peripherals reserved 0.5 GB I-code/D-code memory space 32 kB local static RAM Chapter 2: LPC17xx Memory map reserved 0x0000 0100 0x0000 0000 active interrupt vectors 0 GB 512 kB on-chip flash + 256 byte 0x0000 0000 UM10360 Fig 3. LPC17xx system memory map 13 of 835 NXP Semiconductors UM10360 Chapter 2: LPC17xx Memory map Figure 2–3 and Table 2–4 show different views of the peripheral address space. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately. 3. APB peripheral addresses The following table shows the APB0/1 address maps. No APB peripheral uses all of the 16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple locations within each 16 kB range. Table 4. APB0 peripherals and base addresses Base address Peripheral name APB0 peripheral 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 to 22 23 24 to 31 0x4000 0000 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 4000 0x4001 8000 0x4001 C000 0x4002 0000 0x4002 4000 0x4002 8000 0x4002 C000 0x4003 0000 0x4003 4000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 to 0x4005 8000 0x4005 C000 0x4006 0000 to 0x4007 C000 Watchdog Timer Timer 0 Timer 1 UART0 UART1 reserved PWM1 I2C0 SPI RTC GPIO interrupts Pin Connect Block SSP1 ADC CAN Acceptance Filter RAM CAN Acceptance Filter Registers CAN Common Registers CAN Controller 1 CAN Controller 2 reserved I2C1 reserved UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 14 of 835 NXP Semiconductors UM10360 Chapter 2: LPC17xx Memory map APB1 peripherals and base addresses Base address Peripheral name Table 5. APB1 peripheral 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 30 31 0x4008 0000 0x4008 4000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 to 0x400F 8000 0x400F C000 reserved reserved SSP0 DAC Timer 2 Timer 3 UART2 UART3 I2C2 reserved I2S reserved Repetitive interrupt timer reserved Motor control PWM Quadrature Encoder Interface reserved System control 4. Memory re-mapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the Cortex-M3. Refer to Section 6–4 and Section 34–4.3.5 of the Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset feature. Boot ROM re-mapping Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is normally transparent to the user. However, if execution is halted immediately after reset by a debugger, it should correct the mapping for the user. See Section 33–6. 5. AHB arbitration The Multilayer AHB Matrix arbitrates between several masters. By default, the Cortex-M3 D-code bus has the highest priority, followed by the I-Code bus. All other masters share a lower priority. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 15 of 835 NXP Semiconductors UM10360 Chapter 2: LPC17xx Memory map 6. Bus fault exceptions The LPC17xx generates Bus Fault exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are areas of the memory map that are not implemented for a specific derivative. These include all spaces marked “reserved” in Figure 2–3. For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Bus Fault exception is generated for any instruction fetch that maps to an AHB or APB peripheral address. Within the address space of an existing APB peripheral, an exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0x4000 D000 (an undefined address within the UART0 space) may result in an access to the register defined at address 0x4000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC17xx documentation and are not a supported feature. If software executes a write directly to the flash memory, the flash accelerator will generate a Bus Fault exception. Flash programming must be accomplished by using the specified flash programming interface provided by the Boot Code. Note that the Cortex-M3 core stores the exception flag along with the associated instruction in the pipeline and processes the exception only if an attempt is made to execute the instruction fetched from the disallowed address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 16 of 835 UM10360 Chapter 3: LPC17xx System control Rev. 01 — 4 January 2010 User manual 1. Introduction The system control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: • • • • • Reset Brown-Out Detection External Interrupt Inputs Miscellaneous System Controls and Status Code Security vs. Debugging Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses 2. Pin description Table 3–6 shows pins that are associated with System Control block functions. Table 6. Pin name Pin summary Pin direction Pin description External Interrupt Input 0 - An active low/high level or falling/rising edge general purpose interrupt input. This pin may be used to wake up the processor from Sleep, Deep-sleep, or Power-down modes. External Interrupt Input 1 - See the EINT0 description above. External Interrupt Input 2 - See the EINT0 description above. External Interrupt Input 3 - See the EINT0 description above. External Reset input - A LOW on this pin resets the chip, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000. EINT0 Input EINT1 EINT2 EINT3 RESET Input Input Input Input UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 17 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 3. Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 7. Name Summary of system control registers Description Access Reset value Address External Interrupts EXTINT EXTMODE EXTPOLAR Reset External Interrupt Flag Register External Interrupt Mode register External Interrupt Polarity Register Reset Source Identification Register System Control and Status R/W R/W R/W R/W R/W 0 0 0 see Table 3–8 0 0x400F C140 0x400F C148 0x400F C14C 0x400F C180 0x400F C1A0 RSID SCS Syscon Miscellaneous Registers 4. Reset Reset has 4 sources on the LPC17xx: the RESET pin, Watchdog Reset, Power On Reset (POR), and Brown Out Detect (BOD). The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in Section 4–9 “Wake-up timer” in this chapter), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. The reset logic is shown in the following block diagram (see Figure 3–4). UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 18 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control external reset watchdog reset POR BOD C Q S Reset to the on-chip circuitry Reset to PCON.PD WAKE-UP TIMER START power-down COUNT 2 n internal RC oscillator write “1” from APB reset APB read of PDBIT in PCON FOSC to other blocks C Q S EINT0 wake-up EINT1 wake-up EINT2 wake-up EINT3 wake-up RTC wake-up BOD wake-up Ethernet MAC wake-up USB need_clk wake-up CAN wake-up GPIO0 port wake-up GPIO2 port wake-up Fig 4. Reset block diagram including the wake-up timer On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset, External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time (maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the reset signal is latched and synchronized on the IRC clock. Then the following two sequences start simultaneously: 1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times out. The boot code performs the boot tasks and may jump to the flash. If the flash is not ready to access, the Flash Accelerator will insert wait cycles until the flash is ready. 2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it times out, the flash initialization sequence is started, which takes about 250 cycles. When it’s done, the Flash Accelerator will be granted access to the flash. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Figure 3–5 shows an example of the relationship between the RESET, the IRC, and the processor status when the LPC17xx starts up after reset. See Section 4–3.2 “Main oscillator” for start-up of the main oscillator if selected by the user code. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 19 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control IRC starts IRC stable IRC status RESET VDD(REG)(3V3) valid threshold GND 60 μs 1 μs; IRC stability count boot time boot code executing processor status boot code execution finishes; user code starts user code supply ramp-up time Fig 5. Example of start-up after reset UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 20 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 4.1 Reset Source Identification Register (RSID - 0x400F C180) This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below. Table 8. Bit Reset Source Identification register (RSID - address 0x400F C180) bit description Reset value Symbol Description 0 POR Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset. See text 1 2 EXTR WDTR Assertion of the RESET signal sets this bit. This bit is cleared by POR, but See is not affected by WDT or BOD reset. text This bit is set when the Watchdog Timer times out and the WDTRESET bit See in the Watchdog Mode Register is 1. It is cleared by any of the other text sources of Reset. This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is not affected by External Reset nor Watchdog Reset. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not. 3 BODR See text 31:4 - Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 21 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 5. Brown-out detection The LPC17xx includes a Brown-Out Detector (BOD) that provides 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below the BOD interrupt trip level (typically 2.2 V under nominal room temperature conditions), the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading the Raw Interrupt Status Register. The second stage of low-voltage detection asserts Reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). This Reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the Power-On Reset circuitry maintains the overall Reset. Both the BOD reset interrupt level and the BOD reset trip level thresholds include some hysteresis. In normal operation, this hysteresis allows the BOD reset interrupt level detection to reliably interrupt, or a regularly-executed event loop to sense the condition. But when Brown-Out Detection is enabled to bring the LPC17xx out of Power-down mode (which is itself not a guaranteed operation -- see Section 4–8.7 “Power Mode Control register (PCON - 0x400F C0C0)”), the supply voltage may recover from a transient before the wake-up timer has completed its delay. In this case, the net result of the transient BOD is that the part wakes up and continues operation after the instructions that set Power-down mode, without any interrupt occurring and with the BOD bit in the RSID being 0. Since all other wake-up conditions have latching flags (see Section 3–6.2 “External Interrupt flag register (EXTINT - 0x400F C140)” and Section 27–6.2), a wake-up of this type, without any apparent cause, can be assumed to be a Brown-Out that has gone away. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 22 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 6. External interrupt inputs TheLPC17xx includes four External Interrupt Inputs as selectable pin functions. The logic of an individual external interrupt is represented in Figure 3–6. In addition, external interrupts have the ability to wake up the CPU from Power-down mode. Refer to Section 4–8.8 “Wake-up from Reduced Power Modes” for details. wakeup enable (one bit of EXTWAKE) APB Read of EXTWAKE APB Bus Data D Q EINTi to wakeup timer1 EINTi GLITCH FILTER PCLK EXTPOLARi interrupt flag (one bit of EXTINT) 1 D S Q S Q R S Q R APB read of EXTINT to VIC EXTMODEi PCLK reset write 1 to EXTINTi PCLK Fig 6. External interrupt logic UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 23 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 6.1 Register description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters. Table 9. Name External Interrupt registers Description Access Reset Address value[1] EXTINT The External Interrupt Flag Register contains interrupt flags for EINT0, EINT1, EINT2 and EINT3. See Table 3–10. The External Interrupt Mode Register controls whether each pin is edge- or level-sensitive. See Table 3–11. R/W 0x00 0x400F C140 EXTMODE R/W 0x00 0x400F C148 EXTPOLAR The External Interrupt Polarity Register controls R/W which level or edge on each pin will cause an interrupt. See Table 3–12. 0x00 0x400F C14C [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 6.2 External Interrupt flag register (EXTINT - 0x400F C140) When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in this register. This asserts the corresponding interrupt request to the NVIC, which will cause an interrupt if interrupts from the pin are enabled. Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive state. Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise event that was just triggered by activity on the EINT pin will not be recognized in future. Important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the EXTINT register must be cleared! For details see Section 3–6.3 “External Interrupt Mode register (EXTMODE - 0x400F C148)” and Section 3–6.4 “External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)”. For example, if a system wakes up from Power-down using low level on external interrupt 0 pin, its post wake-up code must reset EINT0 bit in order to allow future entry into the Power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke Power-down mode will fail. The same goes for external interrupt handling. More details on Power-down mode will be discussed in the following chapters. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 24 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control External Interrupt Flag register (EXTINT - address 0x400F C140) bit description Reset value Table 10. Bit Symbol Description 0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 0 1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 0 2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 0 3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1] 0 31:4 [1] Reserved, user software should not write ones to reserved bits. The value NA read from a reserved bit is not defined. Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high. 6.3 External Interrupt Mode register (EXTMODE - 0x400F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see Section 8–5) and enabled in the appropriate NVIC register) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). Note: Software should only change a bit in this register when its interrupt is disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the mode and not having the EXTINT cleared. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 25 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control External Interrupt Mode register (EXTMODE - address 0x400F C148) bit description Value Description Reset value Table 11. Bit Symbol 0 1 2 3 EXTMODE0 EXTMODE1 EXTMODE2 EXTMODE3 0 1 0 1 0 1 0 1 - Level-sensitivity is selected for EINT0. EINT0 is edge sensitive. Level-sensitivity is selected for EINT1. EINT1 is edge sensitive. Level-sensitivity is selected for EINT2. EINT2 is edge sensitive. Level-sensitivity is selected for EINT3. EINT3 is edge sensitive. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 0 0 NA 31:4 - 6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C) In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are selected for the EINT function (see Section 8–5) and enabled in the appropriate NVIC register) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). Note: Software should only change a bit in this register when its interrupt is disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the polarity and not having the EXTINT cleared. Table 12. Bit External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description Value Description Reset value Symbol 0 EXTPOLAR0 0 1 EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0). EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1). EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1). EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2). EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2). 0 1 EXTPOLAR1 0 1 0 2 EXTPOLAR2 0 1 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 26 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description Value Description Reset value Table 12. Bit Symbol 3 EXTPOLAR3 0 1 EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 31:4 - - NA UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 27 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 7. Other system controls and status flags Some aspects of controlling LPC17xx operation that do not fit into peripheral or other registers are grouped here. 7.1 System Controls and Status register (SCS - 0x400F C1A0) The SCS register contains several control/status bits related to the main oscillator. Since chip operation always begins using the Internal RC Oscillator, and the main oscillator may not be used at all in some applications, it will only be started by software request. This is accomplished by setting the OSCEN bit in the SCS register, as described in Table 3-13. The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that software can determine when the oscillator is running and stable. At that point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. Table 13. Bit System Controls and Status register (SCS - address 0x400F C1A0) bit description Value Description Access Reset value Symbol 3:0 - - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. Main oscillator range select. R/W The frequency range of the main oscillator is 1 MHz to 20 MHz. The frequency range of the main oscillator is 15 MHz to 25 MHz. Main oscillator enable. R/W NA 4 OSCRANGE 0 1 0 5 OSCEN 0 1 0 The main oscillator is disabled. The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. Main oscillator status. RO 0 The main oscillator is not ready to be used as a clock source. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit. Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 6 OSCSTAT 0 1 31:7 - - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 28 of 835 UM10360 Chapter 4: LPC17xx Clocking and power control Rev. 01 — 4 January 2010 User manual 1. Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC17xx and options of clock source selection, as well as power control and wake-up from reduced power modes. Functions described in the following subsections include: • • • • • • • • Oscillators Clock source selection PLLs Clock dividers APB dividers Power control Wake-up timer External clock output USB PLL settings (PLL1...) USB PLL select (PLL1CON) USB PLL (PLL1) main PLL settings (PLL0...) CPU PLL select (PLL0CON) usb_clk USB Clock Divider USB clock divider setting USBCLKCFG[3:0] osc_clk rtc_clk irc_osc sysclk Main PLL (PLL0) ` pllclk CPU Clock Divider cclk system clock select CLKSRCSEL[1:0] CPU clock divider setting CCLKCFG[7:0] Peripheral Clock Divider pclk1 pclk2 pclk4 pclk8 wd_clk watchdog clock select WDCLKSEL[1:0] PCLK_WDT Fig 7. Clock generation for the LPC17xx UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 29 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 2. Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 14. Name Summary of system control registers Description Access Reset value Address Clock source selection CLKSRCSEL PLL0CON PLL0CFG PLL0STAT PLL0FEED PLL1CON PLL1CFG PLL1STAT PLL1FEED Clock dividers Clock Source Select Register PLL0 Control Register PLL0 Configuration Register PLL0 Status Register PLL0 Feed Register PLL1 Control Register PLL1 Configuration Register PLL1 Status Register PLL1 Feed Register CPU Clock Configuration Register USB Clock Configuration Register Peripheral Clock Selection register 0. Peripheral Clock Selection register 1. Power Control Register Power Control for Peripherals Register Clock Output Configuration Register R/W R/W R/W RO WO R/W R/W RO WO R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 NA 0 0 0 NA 0 0 0 0 0 0x03BE 0 0x400F C10C 0x400F C080 0x400F C084 0x400F C088 0x400F C08C 0x400F C0A0 0x400F C0A4 0x400F C0A8 0x400F C0AC 0x400F C104 0x400F C108 0x400F C1A8 0x400F C1AC 0x400F C0C0 0x400F C0C4 0x400F C1C8 Phase Locked Loop (PLL0, Main PLL) Phase Locked Loop (PLL1, USB PLL) CCLKCFG USBCLKCFG PCLKSEL0 PCLKSEL1 Power control PCON PCONP Utility CLKOUTCFG UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 30 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 3. Oscillators The LPC17xx includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. This can be seen in Figure 4–7. Following Reset, the LPC17xx will operate from the Internal RC Oscillator until switched by software. This allows systems to operate without any external crystal, and allows the boot loader code to operate at a known frequency. 3.1 Internal RC oscillator The Internal RC Oscillator (IRC) may be used as the clock source for the watchdog timer, and/or as the clock that drives PLL0 and subsequently the CPU. The precision of the IRC does not allow for use of the USB interface, which requires a much more precise time base in order to comply with the USB specification. Also, the IRC should not be used with the CAN1/2 block if the CAN baud rate is higher than 100 kbit/s.The nominal IRC frequency is 4 MHz. Upon power-up or any chip reset, the LPC17xx uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 3.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using PLL0. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the Main PLL (PLL0). The oscillator output is called OSC_CLK. The clock selected as the PLL0 input is PLLCLKIN and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL0 is active and connected. Refer to Section 4–5 “PLL0 (Phase Locked Loop 0)” for details. The on-board oscillator in the LPC17xx can operate in one of two modes: slave mode and oscillation mode. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (CC in Figure 4–8, drawing a), with an amplitude between 200 mVrms and 1000 mVrms. This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 4–8, drawings b and c, and in Table 4–15 and Table 4–16. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 4–8, drawing c, represents the parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the crystal manufacturer. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 31 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control LPC17xx LPC17xx XTAL1 XTAL2 XTAL1 XTAL2 L CC Xtal Clock CX1 CX2 CL RS CP a) b) c) Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for CX1/X2 evaluation Table 15. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode (OSCRANGE = 0, see Table 3–13) Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 Fundamental oscillation frequency FOSC 1 MHz - 5 MHz 10 pF 20 pF 30 pF < 300 Ω < 300 Ω < 300 Ω < 300 Ω < 200 Ω < 100 Ω < 160 Ω < 60 Ω < 80 Ω 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF 5 MHz - 10 MHz 10 pF 20 pF 30 pF 10 MHz - 15 MHz 15 MHz - 20 MHz Table 16. 10 pF 20 pF 10 pF Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) high frequency mode (OSCRANGE = 1, see Table 3–13) Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 Fundamental oscillation frequency FOSC 15 MHz - 20 MHz 20 MHz - 25 MHz 10 pF 20 pF 10 pF 20 pF < 180 Ω < 100 Ω < 160 Ω < 80 Ω 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF 39 pF, 39 pF Since chip operation always begins using the Internal RC Oscillator, and the main oscillator may not be used at all in some applications, it will only be started by software request. This is accomplished by setting the OSCEN bit in the SCS register, as described in Table 3–13. The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that software can determine when the oscillator is running and stable. At that UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 32 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. 3.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be used as the clock source for PLL0 and CPU and/or the watchdog timer. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 33 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 4. Clock source selection multiplexer Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip peripheral devices. The clock sources available are the main oscillator, the RTC oscillator, and the Internal RC oscillator. The clock source selection can only be changed safely when PLL0 is not connected. For a detailed description of how to change the clock source in a system using PLL0 see Section 4–5.13 “PLL0 setup sequence”. Note the following restrictions regarding the choice of clock sources: • The IRC oscillator should not be used (via PLL0) as the clock source for the USB subsystem. • The IRC oscillator should not be used (via PLL0) as the clock source for the CAN controllers if the CAN baud rate is higher than 100 kbit/s. 4.1 Clock Source Select register (CLKSRCSEL - 0x400F C10C) The CLKSRCSEL register contains the bits that select the clock source for PLL0. Table 17. Bit Clock Source Select register (CLKSRCSEL - address 0x400F C10C) bit description Value Description Reset value Symbol 1:0 CLKSRC 00 01 10 11 Selects the clock source for PLL0 as follows: Selects the Internal RC oscillator as the PLL0 clock source (default). Selects the main oscillator as the PLL0 clock source. Selects the RTC oscillator as the PLL0 clock source. Reserved, do not use this setting. 0 Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. 31:2 - 0 Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 34 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 5. PLL0 (Phase Locked Loop 0) PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock source is selected in the CLKSRCSEL register (see Section 4–4). The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem has its own dedicated PLL (see Section 4–6). PLL0 can produce a clock up to the maximum allowed for the CPU, which is 120 MHz on high speed versions (LPC1769 and LPC1759), and 100 MHz on other versions. 5.1 PLL0 operation The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value "N", which may be in the range of 1 to 256. This input division provides a greater number of possibilities in providing a wide range of output frequencies from the same input frequency. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the range of 6 through 512, plus additional values listed in Table 4–21. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. There are additional dividers at the output of PLL0 to bring the frequency down to what is needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output dividers are described in the Clock Dividers section following the PLL0 description. A block diagram of PLL0 is shown in Figure 4–9 PLL activation is controlled via the PLL0CON register. PLL0 multiplier and divider values are controlled by the PLL0CFG register. These two registers are protected in order to prevent accidental alteration of PLL0 parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, could be dependent on PLL0 if so configured (for example when it is providing the chip clock), accidental changes to the PLL0 setup values could result in unexpected or fatal behavior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLL0FEED register. PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 must be configured, enabled, and connected to the system by software. It is important that the setup procedure described in Section 4–5.13 “PLL0 setup sequence” is followed or PLL0 might not operate at all! 5.1.1 PLL0 and startup/boot code interaction When there is no valid user code (determined by the checksum word) in the user flash or the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the boot code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is disabled when the user opens a debug session to debug the application code. The user startup code must follow the steps described in this chapter to disconnect the PLL. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 35 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 5.2 PLL0 register description PLL0 is controlled by the registers shown in Table 4–18. More detailed descriptions follow. Warning: Improper setting of PLL0 values may result in incorrect operation of the device! Table 18. Name PLL0 registers Description Access Reset Address value[1] PLL0CON PLL0 Control Register. Holding register for R/W updating PLL0 control bits. Values written to this register do not take effect until a valid PLL0 feed sequence has taken place. PLL0 Configuration Register. Holding register for R/W updating PLL0 configuration values. Values written to this register do not take effect until a valid PLL0 feed sequence has taken place. PLL0 Status Register. Read-back register for RO PLL0 control and configuration information. If PLL0CON or PLL0CFG have been written to, but a PLL0 feed sequence has not yet occurred, they will not reflect the current PLL0 state. Reading this register provides the actual values controlling the PLL0, as well as the PLL0 status. PLL0 Feed Register. This register enables loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG registers into the shadow registers that actually affect PLL0 operation. WO 0 0x400F C080 PLL0CFG 0 0x400F C084 PLL0STAT 0 0x400F C088 PLL0FEED NA 0x400F C08C [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. PLLC PLLE PLOCK pd refclk pllclkin NSEL [7:0] MSEL [14:0] N-DIVIDER PHASEFREQUENCY DETECTOR FILTER CCO pllclk M-DIVIDER /2 Fig 9. PLL0 block diagram 5.3 PLL0 Control register (PLL0CON - 0x400F C080) The PLL0CON register contains the bits that enable and connect PLL0. Enabling PLL0 allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting PLL0 causes the processor and most chip functions to run from the PLL0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 36 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control output clock. Changes to the PLL0CON register do not take effect until a correct PLL0 feed sequence has been given (see Section 4–5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”). Table 19. Bit PLL Control register (PLL0CON - address 0x400F C080) bit description Description Reset value Symbol 0 PLLE0 PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate 0 PLL0 and allow it to lock to the requested frequency. See PLL0STAT register, Table 4–22. PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register, Table 4–22. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 1 PLLC0 31:2 - NA PLL0 must be set up, enabled, and Lock established before it may be used as a clock source. When switching from the oscillator clock to the PLL0 output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. Hardware does not insure that PLL0 is locked before it is connected or automatically disconnect PLL0 if lock is lost during operation. In the event of loss of lock on PLL0, it is likely that the oscillator clock has become unstable and disconnecting PLL0 will not remedy the situation. 5.4 PLL0 Configuration register (PLL0CFG - 0x400F C084) The PLL0CFG register contains PLL0 multiplier and divider values. Changes to the PLL0CFG register do not take effect until a correct PLL feed sequence has been given (see Section 4–5.8 “PLL0 Feed register (PLL0FEED - 0x400F C08C)”). Calculations for the PLL frequency, and multiplier and divider values are found in the Section 4–5.10 “PLL0 frequency calculation”. Table 20. Bit PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description Description Reset value Symbol 14:0 MSEL0 PLL0 Multiplier value. Supplies the value "M" in PLL0 frequency calculations. The value stored here is M - 1. Supported values for M are 6 through 512 and those listed in Table 4–21. Note: Not all values of M are needed, and therefore some are not supported by hardware. For details on selecting values for MSEL0 see Section 4–5.10 “PLL0 frequency calculation”. 0 15 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 23:16 NSEL0 PLL0 Pre-Divider value. Supplies the value "N" in PLL0 frequency 0 calculations. The value stored here is N - 1. Supported values for N are 1 through 32. Note: For details on selecting the right value for NSEL0 see Section 4–5.10 “PLL0 frequency calculation”. 31:24 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 37 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Multiplier values for PLL0 with a 32 kHz input Pre-divide (N) FCCO Multiplier (M) Pre-divide (N) FCCO Table 21. Multiplier (M) 4272 4395 4578 4725 4807 5127 5188 5400 5493 5859 6042 6075 6104 6409 6592 6750 6836 6866 6958 7050 7324 7425 7690 7813 7935 8057 8100 8545 8789 9155 9613 10254 10376 10986 11719 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 279.9698 288.0307 300.0238 309.6576 315.0316 336.0031 340.0008 353.8944 359.9892 383.9754 395.9685 398.1312 400.0317 420.0202 432.0133 442.3680 448.0041 449.9702 455.9995 462.0288 479.9857 486.6048 503.9718 512.0328 520.0282 528.0236 530.8416 280.0026 287.9980 299.9910 314.9988 336.0031 340.0008 359.9892 384.0082 12085 12207 12817 12817 13184 13184 13672 13733 13733 13916 14099 14420 14648 15381 15381 15564 15625 15869 16113 16479 17578 18127 18311 19226 19775 20508 20599 20874 21149 21973 23071 23438 23804 24170 2 2 2 3 2 3 2 2 3 2 2 3 2 2 3 3 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 396.0013 399.9990 419.9875 279.9916 432.0133 288.0089 448.0041 450.0029 300.0020 455.9995 461.9960 315.0097 479.9857 504.0046 336.0031 340.0008 512.0000 519.9954 527.9908 359.9892 383.9973 395.9904 400.0099 419.9984 431.9915 448.0041 449.9920 455.9995 462.0070 480.0075 503.9937 512.0109 520.0063 528.0017 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 38 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 5.5 PLL0 Status register (PLL0STAT - 0x400F C088) The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in PLL0CON and PLL0CFG because changes to those registers do not take effect until a proper PLL0 feed has occurred (see Section 4–5.8 “PLL0 Feed register (PLL0FEED 0x400F C08C)”). Table 22. Bit PLL Status register (PLL0STAT - address 0x400F C088) bit description Description Reset value Symbol 14:0 15 MSEL0 - Read-back for the PLL0 Multiplier value. This is the value currently 0 used by PLL0, and is one less than the actual multiplier. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider. NA 0 23:16 NSEL0 24 PLLE0_STAT Read-back for the PLL0 Enable bit. This bit reflects the state of the 0 PLEC0 bit in PLL0CON (see Table 4–19) after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered. 25 PLLC0_STAT Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON (see Table 4–19) after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered. 0 26 PLOCK0 Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 31:27 - NA 5.6 PLL0 Interrupt: PLOCK0 The PLOCK0 bit in the PLL0STAT register reflects the lock status of PLL0. When PLL0 is enabled, or parameters are changed, PLL0 requires some time to establish lock under the new conditions. PLOCK0 can be monitored to determine when PLL0 may be connected for use. The value of PLOCK0 may not be stable when the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed. This time is 500 μs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz PLOCK0 is connected to the interrupt controller. This allows for software to turn on PLL0 and continue with other functions without having to wait for PLL0 to achieve lock. When the interrupt occurs, PLL0 may be connected, and the interrupt disabled. PLOCK0 appears as interrupt 32 in Table 6–50. Note that PLOCK0 remains asserted whenever PLL0 is locked, so if the interrupt is used, the interrupt service routine must disable the PLOCK0 interrupt prior to exiting. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 39 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 5.7 PLL0 Modes The combinations of PLLE0 and PLLC0 are shown in Table 4–23. Table 23. PLL control bit combinations PLLC0 PLLE0 PLL Function 0 0 1 1 0 1 0 1 PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input. PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is asserted. Same as 00 combination. This prevents the possibility of PLL0 being connected without also being enabled. PLL0 is active and has been connected as the system clock source. 5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C) A correct feed sequence must be written to the PLL0FEED register in order for changes to the PLL0CON and PLL0CFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLL0FEED. 2. Write the value 0x55 to PLL0FEED. The two writes must be in the correct sequence, and there must be no other register access in the same address space (0x400F C000 to 0x400F FFFF) between them. Because of this, it may be necessary to disable interrupts for the duration of the PLL0 feed operation, if there is a possibility that an interrupt service routine could write to another register in that space. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLL0CON or PLL0CFG register will not become effective. Table 24. Bit PLL Feed register (PLL0FEED - address 0x400F C08C) bit description Description Reset value Symbol 7:0 31:8 PLL0FEED The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x00 NA 5.9 PLL0 and Power-down mode Power-down mode automatically turns off and disconnects PLL0. Wake-up from Power-down mode does not automatically restore PLL0 settings, this must be done in software. Typically, a routine to activate PLL0, wait for lock, and then connect PLL0 can be called at the beginning of any interrupt service routine that might be called due to the wake-up. It is important not to attempt to restart PLL0 by simply feeding it when execution resumes after a wake-up from Power-down mode. This would enable and connect PLL0 at the same time, before PLL lock is established. 5.10 PLL0 frequency calculation PLL0 equations use the following parameters: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 40 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control PLL frequency parameter Description Table 25. Parameter FIN FCCO N M FREF the frequency of PLLCLKIN from the Clock Source Selection Multiplexer. the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator) PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG NSEL0 field + 1). N is an integer from 1 through 32. PLL0 Multiplier value from the MSEL0 bits in the PLL0CFG register (PLL0CFG MSEL0 field + 1). Not all potential values are supported. See below. PLL internal reference frequency, FIN divided by N. The PLL0 output frequency (when PLL0 is both active and connected) is given by: FCCO = (2 × M × FIN) / N PLL inputs and settings must meet the following: • FIN is in the range of 32 kHz to 50 MHz. • FCCO is in the range of 275 MHz to 550 MHz. The equation can be solved for other PLL parameters: M = (FCCO × N) / (2 × FIN) N = (2 × M × FIN) / FCCO FIN = (FCCO × N) / (2 × M) Allowed values for M: At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are allowed. This supports the entire useful range of both the main oscillator and the IRC. For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65 additional M values have been selected for supporting baud rate generation, CAN/USB operation, and obtaining integer MHz frequencies. These values are shown in Table 4–26. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 41 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Additional Multiplier Values for use with a Low Frequency Clock Input Low Frequency PLL Multipliers Table 26. 4272 5127 6042 6750 7324 8057 9613 12085 13733 15381 16479 19775 21973 4395 5188 6075 6836 7425 8100 10254 12207 13916 15564 17578 20508 23071 4578 5400 6104 6866 7690 8545 10376 12817 14099 15625 18127 20599 23438 4725 5493 6409 6958 7813 8789 10986 13184 14420 15869 18311 20874 23804 4807 5859 6592 7050 7935 9155 11719 13672 14648 16113 19226 21149 24170 5.11 Procedure for determining PLL0 settings PLL0 parameter determination can be simplified by using a spreadsheet available from NXP. To determine PLL0 parameters by hand, the following general procedure may be used: 1. Determine if the application requires use of the USB interface, and whether it will be clocked from PLL0. The USB requires a 50% duty cycle clock of 48 MHz within a very small tolerance, which means that FCCO must be an even integer multiple of 48 MHz (i.e. an integer multiple of 96 MHz), within a very small tolerance. 2. Choose the desired processor operating frequency (CCLK). This may be based on processor throughput requirements, need to support a specific set of UART baud rates, etc. Bear in mind that peripheral devices may be running from a lower clock frequency than that of the processor (see Section 4–7 “Clock dividers” on page 55 and Section 4–8 “Power control” on page 59). Find a value for FCCO that is close to a multiple of the desired CCLK frequency, bearing in mind the requirement for USB support in [1] above, and that lower values of FCCO result in lower power dissipation. 3. Choose a value for the PLL input frequency (FIN). This can be a clock obtained from the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support, the main oscillator should be used. Bear in mind that if PLL1 rather than PLL0 is used to clock the USB subsystem, this affects the choice of the main oscillator frequency. 4. Calculate values for M and N to produce a sufficiently accurate FCCO frequency. The desired M value -1 will be written to the MSEL0 field in PLL0CFG. The desired N value -1 will be written to the NSEL0 field in PLL0CFG. In general, it is better to use a smaller value for N, to reduce the level of multiplication that must be accomplished by the CCO. Due to the difficulty in finding the best values in some cases, it is recommended to use a spreadsheet or similar method to show many possibilities at once, from which an overall best choice may be selected. A spreadsheet is available from NXP for this purpose. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 42 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 5.12 Examples of PLL0 settings The following table gives a summary of examples that illustrate selecting PLL0 values based on different system requirements. Table 27. Example Summary of PLL0 examples Description 1 • The PLL0 clock source is 10 MHz. • PLL0 is not used as the USB clock source, or the USB interface is not used. • The desired CPU clock is 100 MHz. 2 • The PLL0 clock source is 4 MHz. • PLL0 is used as the USB clock source. • The desired CPU clock is 60 MHz. 3 • The PLL0 clock source is the 32.768 kHz RTC clock. • PLL0 is not used as the USB clock source, or the USB interface is not used. • The desired CPU clock is 72 MHz. Example 1 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 100 MHz. • An external 10 MHz crystal or clock source will be used as the system clock source. Calculations: M = (FCCO × N) / (2 × FIN) A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M), both result in better PLL operational stability and lower output jitter. Lower values of FCCO also save power. So, the process of determining PLL setup parameters involves looking for the smallest N and M values giving the lowest FCCO value that will support the required CPU and/or USB clocks. It is usually easier to work backward from the desired output clock rate and determine a target FCCO rate, then find a way to obtain that FCCO rate from the available input clock. Potential precise values of FCCO are integer multiples of the desired CPU clock. In this example, it is clear that the smallest frequency for FCCO that can produce the desired CPU clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz (3 × 100 MHz). Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives M = ((300 × 106 × 1) / (2 × 10 × 106) = 300 / 20 = 15. Since the result is an integer, there is no need to look any further for a good set of PLL0 configuration values. The value written to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E). The PLL output must be further divided in order to produce the CPU clock. This is accomplished using a separate divider that is described later in this chapter, see Section 4–7.1. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 43 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Example 2 Assumptions: • The USB interface will be used in the application and will be clocked from PLL0. • The desired CPU rate is 60 MHz. • An external 4 MHz crystal or clock source will be used as the system clock source. This clock source could be the Internal RC oscillator (IRC). Calculations: M = (FCCO × N) / (2 × FIN) Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that need must be addressed first. Potential precise values of FCCO are integer multiples of the 2 × the 48 MHz USB clock. The 2 × insures that the clock has a 50% duty cycle, which would not be the case for a division of the PLL output by an odd number. The possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480 MHz. The smallest frequency for FCCO that can produce a valid USB clock rate and is within the PLL0 operating range is 288 MHz (3 × 2 × 48 MHz). Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So, M = ((288 × 106) × 1) / (2 × (4 × 106)) = 288 / 8 = 36. The result is an integer, which is necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23). The potential CPU clock rate can be determined by dividing FCCO by the desired CPU frequency: 288 × 106 / 60 × 106 = 4.8. The nearest integer value for the CPU Clock Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate. If it is important to obtain exactly 60 MHz, an FCCO rate must be found that can be divided down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0 settings for 480 MHz are N = 1 and M = 60. The PLL output must be further divided in order to produce both the CPU clock and the USB clock. This is accomplished using separate dividers that are described later in this chapter. See Section 4–7.1 and Section 4–7.2. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 44 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Example 3 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 72 MHz • The 32.768 kHz RTC clock source will be used as the system clock source Calculations: M = (FCCO × N) / (2 × FIN) The smallest integer multiple of the desired CPU clock rate that is within the PLL0 operating range is 288 MHz (4 × 72 MHz). Using the equation above and assuming that N = 1, M = ((288 × 106) × 1) / (2 × 32,768) = 4,394.53125. This is not an integer, so the CPU frequency will not be exactly 72 MHz with this setting. Since this example is less obvious, it may be useful to make a table of possibilities for different values of N (see below). Table 28. N M Potential values for PLL example M Rounded FREF in Hz (FIN / N) FCCO in MHz (FREF x M) CCLK in MHz % Error (FCCO / 4) (CCLK-72) / 72 1 2 3 4 5 4394.53125 8789.0625 13183.59375 17578.125 21972.65625 4395 8789 13184 17578 21973 32768 16384 10922.67 8192 6553.6 288.0307 287.9980 288.0089 287.9980 288.0045 72.0077 71.9995 72.0022 71.9995 72.0011 0.0107 -0.0007 0.0031 -0.0007 0.0016 Beyond N = 5, the value of M is out of range or not supported, so the table stops at that point. In the third column of the table, the calculated M value is rounded to the nearest integer. If this results in CCLK being above the maximum operating frequency, it is allowed if it is not more than 1/2 % above the maximum frequency. In general, larger values of FREF result in a more stable PLL when the input clock is a low frequency. Even the first table entry shows a very small error of just over 1 hundredth of a percent, or 107 parts per million (ppm). If that is not accurate enough in the application, the second case gives a much smaller error of 7 ppm. There are no allowed combinations that give a smaller error than that. Remember that when a frequency below about 1 MHz is used as the PLL0 clock source, not all multiplier values are available. As it turns out, all of the rounded M values found in Table 4–28 of this example are supported, which may be confirmed in Table 4–26. If PLL0 calculations suggest use of unsupported multiplier values, those values must be disregarded and other values examined to find the best fit. The value written to PLL0CFG for the second table entry would be 0x12254 (N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254). The PLL output must be further divided in order to produce the CPU clock. This is accomplished using a separate divider that is described later in this chapter, see Section 4–7.1. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 45 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 5.13 PLL0 setup sequence The following sequence must be followed step by step in order to have PLL0 initialized and running: 1. Disconnect PLL0 with one feed sequence if PLL0 is already connected. 2. Disable PLL0 with one feed sequence. 3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired. 4. Write to the Clock Source Selection Control register to change the clock source if needed. 5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG can only be updated when PLL0 is disabled. 6. Enable PLL0 with one feed sequence. 7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do this before connecting PLL0. 8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register, or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz. 9. Connect PLL0 with one feed sequence. It is very important not to merge any steps above. For example, do not update the PLL0CFG and enable PLL0 simultaneously with the same feed sequence. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 46 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 6. PLL1 (Phase Locked Loop 1) PLL1 receives its clock input from the main oscillator only and can be used to provide a fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the possibility of generating the USB clock from PLL0. PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz through that route. If PLL1 is enabled and connected via the PLL1CON register (see Section 4–6.2), it is automatically selected to drive the USB subsystem (see Figure 4–7). PLL1 activation is controlled via the PLL1CON register. PLL1 multiplier and divider values are controlled by the PLL1CFG register. These two registers are protected in order to prevent accidental alteration of PLL1 parameters or deactivation of PLL1. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLL1FEED register. PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up to the range of 48 MHz for the USB clock using a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (for USB, the multiplier value cannot be higher than 4. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while PLL1 is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the output of PLL1 has a 50% duty cycle. A block diagram of PLL1 is shown in Figure 4–10. 6.1 PLL1 register description PLL1 is controlled by the registers shown in Table 4–29. More detailed descriptions follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic zero. Warning: Improper setting of PLL1 values may result in incorrect operation of the USB subsystem! Table 29. Name PLL1 registers Description Access Reset Address value[1] PLL1CON PLL1 Control Register. Holding register for R/W updating PLL1 control bits. Values written to this register do not take effect until a valid PLL1 feed sequence has taken place. 0 0x400F C0A0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 47 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control PLL1 registers Description Access Reset Address value[1] Table 29. Name PLL1CFG PLL1 Configuration Register. Holding register for updating PLL1 configuration values. Values written to this register do not take effect until a valid PLL1 feed sequence has taken place. R/W 0 0x400F C0A4 PLL1STAT PLL1 Status Register. Read-back register for RO PLL1 control and configuration information. If PLL1CON or PLL1CFG have been written to, but a PLL1 feed sequence has not yet occurred, they will not reflect the current PL1L state. Reading this register provides the actual values controlling PLL1, as well as PLL1 status. PLL1 Feed Register. This register enables loading of PLL1 control and configuration information from the PLL1CON and PLL1CFG registers into the shadow registers that actually affect PLL1 operation. WO 0 0x400F C0A8 PLL1FEED NA 0x400F C0AC [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 48 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control PLLC CLOCK SYNCHRONIZATION 0 PSEL[1:0] direct PD PLLE 0 bypass PD FOSC PHASEFREQUENCY DETECTOR CCO FCCO 1 0 CD 0 0 1 1 CCLK PLOCK /2P PD FOUT CD DIV-BY-M MSEL MSEL[4:0] Fig 10. PLL1 block diagram 6.2 PLL1 Control register (PLL1CON - 0x400F C0A0) The PLL1CON register contains the bits that enable and connect PLL1. Enabling PLL1 allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting PLL1 causes the USB subsystem to run from the PLL1 output clock. Changes to the PLL1CON register do not take effect until a correct PLL feed sequence has been given (see Section 4–6.6 and Section 4–6.3). UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 49 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description Description Reset value Table 30. Bit Symbol 0 PLLE1 PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency. See PLL1STAT register, Table 4–32. PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register, Table 4–32. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 1 PLLC1 0 31:2 - NA PLL1 must be set up, enabled, and lock established before it may be used as a clock source for the USB subsystem. The hardware does not insure that the PLL is locked before it is connected nor does it automatically disconnect the PLL if lock is lost during operation. 6.3 PLL1 Configuration register (PLL1CFG - 0x400F C0A4) The PLL1CFG register contains the PLL1 multiplier and divider values. Changes to the PLL1CFG register do not take effect until a correct PLL1 feed sequence has been given (see Section 4–6.6). Calculations for the PLL1 frequency, and multiplier and divider values are found in Section 4–6.9. Table 31. Bit PLL Configuration register (PLL1CFG - address 0x400F C0A4) bit description Description Reset value Symbol 4:0 MSEL1 PLL1 Multiplier value. Supplies the value "M" in the PLL1 frequency calculations. Note: For details on selecting the right value for MSEL1 see Section 4–5.10. 0 6:5 PSEL1 PLL1 Divider value. Supplies the value "P" in the PLL1 frequency calculations. Note: For details on selecting the right value for PSEL1 see Section 4–5.10. 0 31:7 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 6.4 PLL1 Status register (PLL1STAT - 0x400F C0A8) The read-only PLL1STAT register provides the actual PLL1 parameters that are in effect at the time it is read, as well as the PLL1 status. PLL1STAT may disagree with values found in PLL1CON and PLL1CFG because changes to those registers do not take effect until a proper PLL1 feed has occurred (see Section 4–6.6 “PLL1 Feed register (PLL1FEED - 0x400F C0AC)”). UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 50 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description Description Reset value Table 32. Bit Symbol 4:0 6:5 7 8 MSEL1 PSEL1 - Read-back for the PLL1 Multiplier value. This is the value currently 0 used by PLL1. Read-back for the PLL1 Divider value. This is the value currently used by PLL1. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA 0 PLLE1_STAT Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated. 9 PLLC1_STAT Read-back for the PLL1 Connect bit. When PLLC and PLLE are 0 both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated. PLOCK1 Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA 10 31:11 - 6.4.1 PLL1 modes The combinations of PLLE1 and PLLC1 are shown in Table 4–33. Table 33. PLLC1 PLL1 control bit combinations PLLE1 PLL1 Function 0 0 1 1 0 1 0 1 PLL1 is turned off and disconnected. PLL1 is active, but not yet connected. PLL1 can be connected after PLOCK1 is asserted. Same as 00 combination. This prevents the possibility of PLL1 being connected without also being enabled. PLL1 is active and has been connected. The clock for the USB subsystem is sourced from PLL1. 6.5 PLL1 Interrupt: PLOCK1 The PLOCK1 bit in the PLL1STAT register reflects the lock status of PLL1. When PLL1 is enabled, or parameters are changed, the PLL requires some time to establish lock under the new conditions. PLOCK1 can be monitored to determine when the PLL may be connected for use. PLOCK1 is connected to the interrupt controller. This allows for software to turn on the PLL and continue with other functions without having to wait for the PLL to achieve lock. When the interrupt occurs, the PLL may be connected, and the interrupt disabled. PLOCK1 appears as interrupt 48 in Table 6–50. Note that PLOCK1 remains asserted whenever PLL1 is locked, so if the interrupt is used, the interrupt service routine must disable the PLOCK1 interrupt prior to exiting. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 51 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC) A correct feed sequence must be written to the PLL1FEED register in order for changes to the PLL1CON and PLL1CFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLL1FEED. 2. Write the value 0x55 to PLL1FEED. The two writes must be in the correct sequence, and there must be no other register access in the same address space (0x400F C000 to 0x400F FFFF) between them. Because of this, it may be necessary to disable interrupts for the duration of the PLL feed operation, if there is a possibility that an interrupt service routine could write to another register in that space. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLL1CON or PLL1CFG register will not become effective. Table 34. Bit PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description Description Reset value Symbol 7:0 31:8 PLL1FEED - The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x00 NA 6.7 PLL1 and Power-down mode Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up from Power-down mode does not automatically restore PLL settings, this must be done in software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wake-up. It is important not to attempt to restart a PLL by simply feeding it when execution resumes after a wake-up from Power-down mode. This would enable and connect the PLL at the same time, before PLL lock is established. If activity on the USB data lines is not selected to wake the microcontroller from Power-down mode (see Section 4–8.8 for details of wake up from reduced modes), both the Main PLL (PLL0) and the USB PLL (PLL1) will be automatically be turned off and disconnected when Power-down mode is invoked, as described above. However, if the USB activity interrupt is enabled and USB_NEED_CLK = 1 (see Table 11–190 for a description of USB_NEED_CLK), it is not possible to go into Power-down mode and any attempt to set the PD bit will fail, leaving the PLLs in the current state. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 52 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 6.8 PLL1 frequency calculation The PLL1 equations use the following parameters: Table 35. Element Elements determining PLL frequency Description FOSC FCCO USBCLK M P the frequency from the crystal oscillator the frequency of the PLL1 current controlled oscillator the PLL1 output frequency (48 MHz for USB) PLL1 Multiplier value from the MSEL1 bits in the PLL1CFG register PLL1 Divider value from the PSEL1 bits in the PLL1CFG register The PLL1 output frequency (when the PLL is both active and connected) is given by: USBCLK = M × FOSC or USBCLK = FCCO / (2 × P) The CCO frequency can be computed as: FCCO = USBCLK × 2 × P or FCCO = FOSC × M × 2 × P The PLL1 inputs and settings must meet the following criteria: • FOSC is in the range of 10 MHz to 25 MHz. • USBCLK is 48 MHz. • FCCO is in the range of 156 MHz to 320 MHz. 6.9 Procedure for determining PLL1 settings The PLL1 configuration for USB may be determined as follows: 1. The desired PLL1 output frequency is USBCLK = 48 MHz. 2. Choose an oscillator frequency (FOSC). USBCLK must be the whole (non-fractional) multiple of FOSC meaning that the possible values for FOSC are 12 MHz, 16 MHz, and 24 MHz. 3. Calculate the value of M to configure the MSEL1 bits. M = USBCLK / FOSC. In this case, the possible values for M = 2, 3, or 4 (FOSC = 24 MHz, 16 MHz, or 12 MHz). The value written to the MSEL1 bits in PLL1CFG is M − 1 (see Table 4–37). 4. Find a value for P to configure the PSEL1 bits, such that FCCO is within its defined frequency limits of 156 MHz to 320 MHz. FCCO is calculated using FCCO = USBCLK × 2 × P. It follows that P = 2 is the only P value to yield FCCO in the allowed range. The value written to the PSEL1 bits in PLL1CFG is ‘01’ for P = 2 (see Table 4–36). UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 53 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Table 36. PLL1 Divider values Values allowed for using PLL1 with USB are highlighted. PSEL1 Bits (PLL1CFG bits [6:5]) Value of P 00 01 1 2 10 11 4 8 Table 37. PLL1 Multiplier values Values allowed for using PLL1 with USB are highlighted. MSEL1 Bits (PLL1CFG bits [4:0]) Value of M 00000 00001 00010 00011 1 2 3 4 ... 11110 11111 ... 31 32 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 54 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 7. Clock dividers The output of the PLL0 must be divided down for use by the CPU and the USB subsystem (if used with PLL0, see Section 4–6). Separate dividers are provided such that the CPU frequency can be determined independently from the USB subsystem, which always requires 48 MHz with a 50% duty cycle for proper operation. USB PLL settings (PLL1...) USB PLL select (PLL1CON) osc_clk USB PLL (PLL1) main PLL settings (PLL0...) CPU PLL select (PLL0CON) usb_clk USB Clock Divider USB clock divider setting USBCLKCFG[3:0] CPU Clock Divider CPU clock divider setting CCLKCFG[7:0] sysclk Main PLL (PLL0) pllclk cclk Fig 11. PLLs and clock dividers 7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104) The CCLKCFG register controls the division of the PLL0 output before it is used by the CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the output must be divided in order to bring the CPU clock frequency (CCLK) within operating limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low rate for temporary power savings without turning off PLL0. Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in order to support internal operations of the USB subsystem. Table 38. Bit CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit description Value Description Reset value Symbol 7:0 CCLKSEL 0 to 1 2 3 4 : 255 Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. Not allowed, the CPU clock will always be greater than 100 MHz. PLL0 output is divided by 3 to produce the CPU clock. PLL0 output is divided by 4 to produce the CPU clock. PLL0 output is divided by 5 to produce the CPU clock. : PLL0 output is divided by 256 to produce the CPU clock. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x00 31:8 - NA UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 55 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having CCLKSEL = 1 results in CCLK being one half the PLL0 output, CCLKSEL = 3 results in CCLK being one quarter of the PLL0 output, etc. 7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108) This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB subsystem. If PLL1 is not connected, the USB subsystem will be driven by PLL0 via the USB clock divider. The USBCLKCFG register controls the division of the PLL0 output before it is used by the USB subsystem.The PLL0 output must be divided in order to bring the USB clock frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL operating range. Remark: The Internal RC oscillator should not be used to drive PLL0 when the USB is using PLL0 as a clock source because a more precise clock is needed for USB specification compliance (see Table 4–17). Table 39. Bit USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit description Value Description Reset value Symbol 3:0 USBSEL Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 0 5 7 9 31:4 - PLL0 output is divided by 6. PLL0 output must be 288 MHz. PLL0 output is divided by 8. PLL0 output must be 384 MHz. PLL0 output is divided by 10. PLL0 output must be 480 MHz. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 0x400F C1A8 and PCLKSEL1 - 0x400F C1AC) A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal that will be supplied to the corresponding peripheral as specified in Table 4–40, Table 4–41 and Table 4–42. Remark: The peripheral clock for the RTC block is fixed at CCLK/8. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 56 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit description Description Reset value Table 40. Bit Symbol 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 [1] PCLK_WDT PCLK_TIMER0 PCLK_TIMER1 PCLK_UART0 PCLK_UART1 PCLK_PWM1 PCLK_I2C0 PCLK_SPI PCLK_SSP1 PCLK_DAC PCLK_ADC PCLK_CAN1 PCLK_CAN2 PCLK_ACF Peripheral clock selection for WDT. Peripheral clock selection for TIMER0. Peripheral clock selection for TIMER1. Peripheral clock selection for UART0. Peripheral clock selection for UART1. Reserved. Peripheral clock selection for PWM1. Peripheral clock selection for I2C0. Peripheral clock selection for SPI. Reserved. Peripheral clock selection for SSP1. Peripheral clock selection for DAC. Peripheral clock selection for ADC. Peripheral clock selection for Peripheral clock selection for CAN1.[1] CAN2.[1] 00 00 00 00 00 NA 00 00 00 NA 00 00 00 00 00 00 Peripheral clock selection for CAN acceptance filtering.[1] PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. Table 41. Bit Peripheral Clock Selection register 1 (PCLKSEL1 - address 0x400F C1AC) bit description Description Reset value Symbol 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 PCLK_QEI PCLK_GPIOINT PCLK_PCB PCLK_I2C1 PCLK_SSP0 PCLK_TIMER2 PCLK_TIMER3 PCLK_UART2 PCLK_UART3 PCLK_I2C2 PCLK_I2S PCLK_RIT PCLK_SYSCON PCLK_MC Peripheral clock selection for the Quadrature Encoder Interface. Peripheral clock selection for GPIO interrupts. Peripheral clock selection for the Pin Connect block. Peripheral clock selection for I2C1. Reserved. Peripheral clock selection for SSP0. Peripheral clock selection for TIMER2. Peripheral clock selection for TIMER3. Peripheral clock selection for UART2. Peripheral clock selection for UART3. Peripheral clock selection for I2C2. Peripheral clock selection for Reserved. Peripheral clock selection for Repetitive Interrupt Timer. Peripheral clock selection for the System Control block. Peripheral clock selection for the Motor Control PWM. I2S. 00 00 00 00 NA 00 00 00 00 00 00 00 NA 00 00 00 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 57 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Peripheral Clock Selection register bit values Reset value Table 42. PCLKSEL0 and PCLKSEL1 Function individual peripheral’s clock select options 00 01 10 11 PCLK_peripheral = CCLK/4 PCLK_peripheral = CCLK PCLK_peripheral = CCLK/2 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6. 00 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 58 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 8. Power control The LPC17xx supports a variety of power control features: Sleep mode, Deep Sleep mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Entry to any reduced power mode begins with the execution of either a WFI (Wait For Interrupt) or WFE (Wait For Exception) instruction by the Cortex-M3. The Cortex-M3 internally supports two reduced power modes: Sleep and Deep Sleep. These are selected by the SLEEPDEEP bit in the cortex-M3 System Control Register. Power-down and Deep Power-down modes are selected by bits in the PCON register. See Table 4–44. The same register contains flags that indicate whether entry into each reduced power mode actually occurred. The LPC17xx also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the Real Time Clock. Reduced power modes have some limitation during debug, see Section 33–5 for more information. 8.1 Sleep mode Note: Sleep mode on the LPC17xx corresponds to the Idle mode on LPC2xxx series devices. The name is changed because ARM has incorporated portions of reduced power mode control into the Cortex-M3. LPC17xx documentation uses the Cortex-M3 terminology where applicable. When Sleep mode is entered, the clock to the core is stopped, and the SMFLAG bit in PCON is set, see Table 4–44.Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or an interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. 8.2 Deep Sleep mode Note: Deep Sleep mode on the LPC17xx corresponds to the Sleep mode on LPC23xx and LPC24xx series devices. The name is changed because ARM has incorporated portions of reduced power mode control into the Cortex-M3. LPC17xx documentation uses the Cortex-M3 terminology where applicable. When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 4–44. The IRC remains running and can be configured to drive the Watchdog Timer, allowing the UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 59 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC interrupts may be used as a wake-up source. The flash is left in the standby mode allowing a quick wake-up. The PLLs are automatically turned off and disconnected. The CCLK and USBCLK clock dividers automatically get reset to zero. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep Sleep mode and the logic levels of chip pins remain static. The Deep Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep Sleep mode reduces chip power consumption to a very low value. On the wake-up of Deep Sleep mode, if the IRC was used before entering Deep Sleep mode, a 2-bit IRC timer starts counting and the code execution and peripherals activities will resume after the timer expires (4 cycles). If the main external oscillator was used, the 12-bit main oscillator timer starts counting and the code execution will resume when the timer expires (4096 cycles). The user must remember to re-configure any required PLLs and clock dividers after the wake-up. Wake-up from Deep Sleep mode can be brought about by NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a Watchdog Timer timeout, a USB input pin transition (USB activity interrupt), or a CAN input pin transition, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs. 8.3 Power-down mode Power-down mode does everything that Deep Sleep mode does, but also turns off the flash memory. Entry to Power-down mode causes the PDFLAG bit in PCON to be set, see Table 4–44. This saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and disconnected. The CCLK and USBCLK clock dividers automatically get reset to zero. Upon wake-up from Power-down mode, if the IRC was used before entering Power-down mode, after IRC-start-up time (about 60 μs), the 2-bit IRC timer starts counting and expiring in 4 cycles. Code execution can then be resumed immediately following the expiration of the IRC timer if the code was running from SRAM. In the meantime, the flash wake-up timer measures flash start-up time of about 100 μs. When it times out, access to the flash is enabled. The user must remember to re-configure any required PLLs and clock dividers after the wake-up. Wake-up from Power-down mode can be brought about by NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), or a CAN input pin transition, when the related interrupt is enabled. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 60 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 8.4 Deep Power-down mode In Deep Power-down mode, power is shut off to the entire chip with the exception of the Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep Power-down mode causes the DPDFLAG bit in PCON to be set, see Table 4–44. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn off power to the on-chip regulator via the VDD(REG)(3V3) pins after entering Deep Power-down mode.Power to the on-chip regulator must be restored before device operation can be restarted. Wake-up from Deep Power-down mode will occur when an external reset signal is applied, or the RTC interrupt is enabled and an RTC interrupt is generated. 8.5 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. This is detailed in the description of the PCONP register. 8.6 Register description The Power Control function uses registers shown in Table 4–43. More detailed descriptions follow. Table 43. Name Power Control registers Description Access Reset value[1] Address PCON Power Control Register. This register contains control bits that enable some reduced power operating modes of the LPC17xx. See Table 4–44. Power Control for Peripherals Register. This register contains control bits that enable and disable individual peripheral functions, allowing elimination of power consumption by peripherals that are not needed. R/W 0x00 0x400F C0C0 PCONP R/W 0x400F C0C4 [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 61 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 8.7 Power Mode Control register (PCON - 0x400F C0C0) Controls for some reduced power modes and other power related controls are contained in the PCON register, as described in Table 4–44. Table 44. Bit Power Mode Control register (PCON - address 0x400F C0C0) bit description Description Reset value Symbol 0 1 2 PM0 PM1 BODRPM Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 4–8.7.1 below for details. Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 4–8.7.1 below for details. 0 0 Brown-Out Reduced Power Mode. When BODRPM is 1, the 0 Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection. 3 BOGD Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. 0 4 BORD Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3–5 for details of Brown-Out detection. 0 7:3 8 9 10 11 SMFLAG DSFLAG PDFLAG Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit. NA 0 [1][2] Deep Sleep entry flag. Set when the Deep Sleep mode is successfully 0 [1][2] entered. Cleared by software writing a one to this bit. Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit. 0 [1][2] 0 [1][3] NA DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 31:12 [1] [2] [3] Only one of these flags will be valid at a specific time. Hardware reset only for a power-up of core power or by a brownout detect event. Hardware reset only for a power-up event on Vbat. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 62 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 8.7.1 Encoding of Reduced Power Modes The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Sleep and Power-down modes. Table 4–45 below shows the encoding for the three reduced power modes supported by the LPC17xx. Table 45. PM1, PM0 Encoding of reduced power modes Description 00 01 10 11 Execution of WFI or WFE enters either Sleep or Deep Sleep mode as defined by the SLEEPDEEP bit in the Cortex-M3 System Control Register. Execution of WFI or WFE enters Power-down mode if the SLEEPDEEP bit in the Cortex-M3 System Control Register is 1. Reserved, this setting should not be used. Execution of WFI or WFE enters Deep Power-down mode if the SLEEPDEEP bit in the Cortex-M3 System Control Register is 1. 8.8 Wake-up from Reduced Power Modes Any enabled interrupt can wake up the CPU from Sleep mode. Certain interrupts can wake up the processor if it is in either Deep Sleep mode or Power-down mode. Interrupts that can occur during Deep Sleep or Power-down mode will wake up the CPU if the interrupt is enabled. After wake-up, execution will continue to the appropriate interrupt service routine. These interrupts are NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, Ethernet Wake-on-LAN interrupt, Brownout Detect, RTC Alarm, CAN Activity Interrupt, and USB Activity Interrupt. In addition, the watchdog timer can wake up the part from Deep Sleep mode if the watchdog timer is being clocked by the IRC oscillator. For the wake-up process to take place the corresponding interrupt must be enabled in the NVIC. For pin-related peripheral functions, the related functions must also be mapped to pins. The CAN Activity Interrupt is generated by activity on the CAN bus pins, and the USB Activity Interrupt is generated by activity on the USB bus pins. These interrupts are only useful to wake up the CPU when it is on Deep Sleep or Power-down mode, when the peripheral functions are powered up, but not active. Typically, if these interrupts are used, their flags should be polled just before enabling the interrupt and entering the desired reduced power mode. This can save time and power by avoiding an immediate wake-up. Upon wake-up, the interrupt service can turn off the related activity interrupt, do any application specific setup, and exit to await a normal peripheral interrupt. 8.9 Power Control for Peripherals register (PCONP - 0x400F C0C4) The PCONP register allows turning off selected peripheral functions for the purpose of saving power. This is accomplished by gating off the clock source to the specified peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer, the Pin Connect block, and the System Control block). Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 63 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Each bit in PCONP controls one peripheral as shown in Table 4–46. If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the I2C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled. Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register! Table 46. Bit Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description Description Reset value Symbol 0 1 2 3 4 5 6 7 8 9 10 11 12 PCTIM0 PCTIM1 PCUART0 PCUART1 PCPWM1 PCI2C0 PCSPI PCRTC PCSSP1 PCADC Reserved. Timer/Counter 0 power/clock control bit. Timer/Counter 1 power/clock control bit. UART0 power/clock control bit. UART1 power/clock control bit. Reserved. PWM1 power/clock control bit. The I2C0 interface power/clock control bit. The SPI interface power/clock control bit. The RTC power/clock control bit. The SSP 1 interface power/clock control bit. Reserved. A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. NA 1 1 1 1 NA 1 1 1 1 1 NA 0 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PCCAN1 PCCAN2 PCRIT PCQEI PCI2C1 PCSSP0 PCTIM2 PCTIM3 PCUART2 PCUART3 PCI2C2 PCI2S - CAN Controller 1 power/clock control bit. CAN Controller 2 power/clock control bit. Reserved. Repetitive Interrupt Timer power/clock control bit. Quadrature Encoder Interface power/clock control bit. The I2C1 interface power/clock control bit. Reserved. The SSP0 interface power/clock control bit. Timer 2 power/clock control bit. Timer 3 power/clock control bit. UART 2 power/clock control bit. UART 3 power/clock control bit. I2C I2S interface 2 power/clock control bit. interface power/clock control bit. 0 0 NA 0 0 0 1 NA 1 0 0 0 0 1 0 NA PCMCPWM Motor Control PWM Reserved. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 64 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description Description Reset value Table 46. Bit Symbol 29 30 31 PCGPDMA PCENET PCUSB GPDMA function power/clock control bit. Ethernet block power/clock control bit. USB interface power/clock control bit. 0 0 0 Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC, its output must be selected to appear on the related pin, P0.26, by configuring the PINSEL1 register. See Section 8–5.2 “Pin Function Select Register 1 (PINSEL1 0x4002 C004)”. 8.10 Power control usage notes After every reset, the PCONP register contains the value that enables selected interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’s application might have to access the PCONP in order to start using some of the on-board peripherals. Power saving oriented systems should have 1s in the PCONP register only in positions that match peripherals really used in the application. All other bits, declared to be "Reserved" or dedicated to the peripherals not used in the current application, must be cleared to 0. 8.11 Power domains The LPC17xx provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the Real Time Clock. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. Whenever the device core power is present, that power is used to operate the RTC, causing no power drain from a battery when main power is available. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 65 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 9. Wake-up timer The LPC17xx begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to begin quickly. If the main oscillator or one or both PLLs are needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power-on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(REG)(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. Once a clock is detected, the Wake-up Timer counts a fixed number of clocks (4,096), then sets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator is ready for use. Software can then switch to the main oscillator and start any required PLLs. Refer to the Main Oscillator description in this chapter for details. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 66 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 10. External clock output pin For system test and development purposes, any one of several internal clocks may be brought out on the CLKOUT function available on the P1.27 pin, as shown in Figure 4–12. Clocks that may be observed via CLKOUT are the CPU clock (cclk), the main oscillator (osc_clk), the internal RC oscillator (irc_osc), the USB clock (usb_clk), and the RTC clock (rtc_clk). CLKOUTCFG[3:0] cclk osc_clk irc_osc usb_clk rtc_clk 000 001 010 011 100 CLKOUTCFG[7:4] CLKOUTCFG[8] CLKOUT Divider Clock Enable Syncronizer CLKOUT CLKOUTCFG[9] Fig 12. CLKOUT selection 10.1 Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) The CLKOUTCFG register controls the selection of the internal clock that appears on the CLKOUT pin and allows dividing the clock by an integer value up to 16. The divider can be used to produce a system clock that is related to one of the on-chip clocks. For most clock sources, the division may be by 1. When the CPU clock is selected and is higher than approximately 50 MHz, the output must be divided in order to bring the frequency within the ability of the pin to switch with reasonable logic levels. Note: The CLKOUT multiplexer is designed to switch cleanly, without glitches, between the possible clock sources. The divider is also designed to allow changing the divide value without glitches. Table 47. Bit Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Value Description Reset value Symbol 3:0 CLKOUTSEL 0000 0001 0010 0011 0100 Selects the clock source for the CLKOUT function. Selects the CPU clock as the CLKOUT source. Selects the main oscillator as the CLKOUT source. Selects the Internal RC oscillator as the CLKOUT source (default). Selects the USB clock as the CLKOUT source. Selects the RTC oscillator as the CLKOUT source. 0 others Reserved, do not use these settings. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 67 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Value Description Reset value Table 47. Bit Symbol 7:4 CLKOUTDIV 0000 0001 0010 ... 1111 Integer value to divide the output clock by, minus one. Clock is divided by 1. Clock is divided by 2. Clock is divided by 3. ... Clock is divided by 16. 0 8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT 0 source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. Used in concert with the CLKOUT_EN bit below. CLKOUT activity indication. Reads as 1 when CLKOUT is 0 enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. 9 CLKOUT_ACT 31:10 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 68 of 835 UM10360 Chapter 5: LPC17xx Flash accelerator Rev. 01 — 4 January 2010 User manual 1. Introduction The flash accelerator block in the LPC17xx allows maximization of the performance of the Cortex-M3 processor when it is running code from flash memory, while also saving power. The flash accelerator also provides speed and power improvements for data accesses to the flash memory. 2. Flash accelerator blocks The flash accelerator is divided into several functional blocks: • AHB-Lite bus interface, accessible by the Cortex-M3 I-code and D-code buses, as well as by the General Purpose DMA Controller • An array of eight 128-bit buffers • Flash accelerator control logic, including address compare and flash control • A flash memory interface Figure 5–13 shows a simplified diagram of the flash accelerator blocks and data paths. DCode bus Cortex-M3 CPU ICode bus Bus Matrix Combined AHB Flash Accelerator AHB-Lite bus interface Buffer Array Flash Interface Flash Memory DMA General Master Port Purpose DMA Controller Flash Accelerator Control Fig 13. Simplified block diagram of the flash accelerator showing potential bus connections In the following descriptions, the term “fetch” applies to an explicit flash read request from the CPU. “Prefetch” is used to denote a flash read of instructions beyond the current processor fetch address. 2.1 Flash memory bank There is one bank of flash memory controlled by the LPC17xx flash accelerator. Flash programming operations are not controlled by the flash accelerator, but are handled as a separate function. A Boot ROM contains flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow programming of the flash memory. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 69 of 835 NXP Semiconductors UM10360 Chapter 5: LPC17xx Flash accelerator 2.2 Flash programming Issues Since the flash memory does not allow accesses during programming and erase operations, it is necessary for the flash accelerator to force the CPU to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation. Under some conditions, this delay could result in a Watchdog time-out. The user will need to be aware of this possibility and take steps to insure that an unwanted Watchdog reset does not cause a system failure while programming or erasing the flash memory. In order to preclude the possibility of stale data being read from the flash memory, the LPC17xx flash accelerator buffers are automatically invalidated at the beginning of any flash programming or erase operation. Any subsequent read from a flash address will cause a new fetch to be initiated after the flash operation has completed. 3. Register description The flash accelerator is controlled by the register shown in Table 5–48. More detailed descriptions follow. Table 48. Name Summary of flash accelerator registers Description Access Reset Address value[1] FLASHCFG [1] Flash Accelerator Configuration Register. R/W Controls flash access timing. See Table 5–49. 0x303A 0x400F C000 Reset Value reflects the data stored in defined bits only. It does not include reserved bits content. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 70 of 835 NXP Semiconductors UM10360 Chapter 5: LPC17xx Flash accelerator 4. Flash Accelerator Configuration register (FLASHCFG - 0x400F C000) Configuration bits select the flash access time, as shown in Table 5–49. The lower bits of FLASHCFG control internal flash accelerator functions and should not be altered. Following reset, flash accelerator functions are enabled and flash access timing is set to a default value of 4 clocks. Changing the FLASHCFG register value causes the flash accelerator to invalidate all of the holding latches, resulting in new reads of flash information as required. This guarantees synchronization of the flash accelerator to CPU operation. Table 49. Bit Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description Value Description Reset value Symbol 11:0 - - Reserved, user software should not change these bits from the reset value. 0x03A 15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used 0x3 for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Important Note: Frequency values shown below are estimates at this time. 0000 0001 0010 0011 0100 0101 Other 31:16 - Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions. Intended for potential future higher speed devices. Reserved. The value read from a reserved bit is not defined. NA 5. Operation Simply put, the flash accelerator attempts to have the next Cortex-M3 instruction that will be needed in its latches in time to prevent CPU fetch stalls. The LPC17xx uses one bank of flash memory. The flash accelerator includes an array of eight 128-bit buffers to store both instructions and data in a configurable manner. Each 128-bit buffer in the array can include four 32-bit instructions, eight 16-bit instructions or some combination of the two. During sequential code execution, a buffer typically contains the current instruction and the entire flash line that contains that instruction, or one flash line of data containing a previously requested address. Buffers are marked according to how they are used (as instruction or data buffers), and when they have been accessed. This information is used to carry out the buffer replacement strategy. The Cortex-M3 provides a separate bus for instruction access (I-code) and data access (D-code) in the code memory space. These buses, plus the General Purpose DMA Controllers’s master port, are arbitrated by the AHB multilayer matrix. Any access to the flash memory’s address space is presented to the flash accelerator. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 71 of 835 NXP Semiconductors UM10360 Chapter 5: LPC17xx Flash accelerator If a flash instruction fetch and a flash data access from the CPU occur at the same time, the multilayer matrix gives precedence to the data access. This is because a stalled data access always slows down execution, while a stalled instruction fetch often does not. When the flash data access is concluded, any flash fetch or prefetch that had been in progress is re-initiated. Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. Buffer replacement strategy in the flash accelerator attempts to maximize the chances that potentially reusable information is retained until it is needed again. If an attempt is made to write directly to the flash memory without using the normal flash programming interface (via Boot ROM function calls), the flash accelerator generates an error condition. The CPU treats this error as a data abort. The GPDMA handles error conditions as described in Section 31–4.1.6.3. When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the CPU is stalled for a shorter time since the required flash access is already in progress. Typically, a flash prefetch is begun whenever an access is made to a just prefetched address, or to a buffer whose immediate successor is not already in another buffer. A prefetch in progress may be aborted by a data access, in order to minimize CPU stalls. A prefetched flash line is latched within the flash memory, but the flash accelerator does not capture the line in a buffer until the CPU presents an address that is contained within the prefetched flash line. If the core presents an instruction address that is not already buffered and is not contained in the prefetched flash line, the prefetched line will be discarded. Some special cases include the possibility that the CPU will request a data access to an address already contained in an instruction buffer. In this case, the data will be read from the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction address that can be satisfied from an existing data buffer, causes the instruction to be supplied from the data buffer, and the buffer to be changed into an instruction buffer. This causes the buffer to be handled differently when the flash accelerator is determining which buffer is to be overwritten next. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 72 of 835 UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Rev. 01 — 4 January 2010 User manual 1. Features • • • • • • • • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3 Tightly coupled interrupt controller provides low interrupt latency Controls system exceptions and peripheral interrupts In the LPC17xx, the NVIC supports 35 vectored interrupts 32 programmable interrupt priority levels, with hardware priority level masking Relocatable vector table Non-Maskable Interrupt Software interrupt generation 2. Description The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. Refer to the Cortex-M3 User Guide Section 34–4.2 for details of NVIC operation. 3. Interrupt sources Table 6–50 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source, as noted. Exception numbers relate to where entries are stored in the exception vector table. Interrupt numbers are used in some other contexts, such as software interrupts. In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to operate from an external signal, the NMI function must be connected to the related device pin (P2.10 / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be processed. For details, refer to the Cortex-M3 User Guide that is an appendix to this User Manual. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 73 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Flag(s) Interrupt Exception Vector Function ID Number Offset 0 1 2 3 4 5 16 17 18 19 20 21 0x40 0x44 0x48 0x4C 0x50 0x54 WDT Timer 0 Timer 1 Timer 2 Timer 3 UART0 Watchdog Interrupt (WDINT) Match 0 - 1 (MR0, MR1) Capture 0 - 1 (CR0, CR1) Match 0 - 2 (MR0, MR1, MR2) Capture 0 - 1 (CR0, CR1) Match 0-3 Capture 0-1 Match 0-3 Capture 0-1 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 6 22 0x58 UART1 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Control Change End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 7 23 0x5C UART 2 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 8 24 0x60 UART 3 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) End of Auto-Baud (ABEO) Auto-Baud Time-Out (ABTO) 9 10 11 12 13 25 26 27 28 29 0x64 0x68 0x6C 0x70 0x74 PWM1 I2C0 I2C1 I2C2 SPI Match 0 - 6 of PWM1 Capture 0-1 of PWM1 SI (state change) SI (state change) SI (state change) SPI Interrupt Flag (SPIF) Mode Fault (MODF) UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 74 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Flag(s) Interrupt Exception Vector Function ID Number Offset 14 30 0x78 SSP0 Tx FIFO half empty of SSP0 Rx FIFO half full of SSP0 Rx Timeout of SSP0 Rx Overrun of SSP0 15 31 0x7C SSP 1 Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun 16 17 18 19 20 21 22 23 24 25 26 27 28 32 33 34 35 36 37 38 39 40 41 42 43 44 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 PLL0 (Main PLL) RTC External Interrupt External Interrupt External Interrupt External Interrupt ADC BOD USB CAN GPDMA I2S Ethernet PLL0 Lock (PLOCK0) Counter Increment (RTCCIF) Alarm (RTCALF) External Interrupt 0 (EINT0) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2) External Interrupt 3 (EINT3). Note: EINT3 channel is shared with GPIO interrupts A/D Converter end of conversion Brown Out detect USB_INT_REQ_LP, USB_INT_REQ_HP, USB_INT_REQ_DMA CAN Common, CAN 0 Tx, CAN 0 Rx, CAN 1 Tx, CAN 1 Rx IntStatus of DMA channel 0, IntStatus of DMA channel 1 irq, dmareq1, dmareq2 WakeupInt, SoftInt, TxDoneInt, TxFinishedInt, TxErrorInt, TxUnderrunInt, RxDoneInt, RxFinishedInt, RxErrorInt, RxOverrunInt. RITINT IPER[2:0], IPW[2:0], ICAP[2:0], FES INX_Int, TIM_Int, VELC_Int, DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int, POS2_Int, REV_Int, POS0REV_Int, POS1REV_Int, POS2REV_Int PLL1 Lock (PLOCK1) 29 30 31 45 46 47 0xB4 0xB8 0xBC Repetitive Interrupt Timer Motor Control PWM Quadrature Encoder 32 33 34 48 49 50 0xC0 0xC4 0xC8 PLL1 (USB PLL) USB Activity Interrupt USB_NEED_CLK CAN Activity Interrupt CAN1WAKE, CAN2WAKE UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 75 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 4. Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table should be located on a 256 word (1024 byte) boundary to insure alignment on LPC17xx family devices. Refer to Section 34–4.3.5 of the Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset feature. ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code or SRAM. For simplicity, this bit can be thought as simply part of the address offset since the split between the “code” space and the “SRAM” space occurs at the location corresponding to bit 29 in a memory address. Examples: To place the vector table at the beginning of the “local” static RAM, starting at address 0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address 0x1000 0000 in the code space, since bit 29 of the VTOR equals 0. To place the vector table at the beginning of the AHB static RAM, starting at address 0x2007 C000, place the value 0x2007 C000 in the VTOR register. This indicates address 0x2007 C000 in the SRAM space, since bit 29 of the VTOR equals 1. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 76 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5. Register description The following table summarizes the registers in the NVIC as implemented in the LPC17xx. The Cortex-M3 User Guide Section 34–4.2 provides a functional description of the NVIC. Table 51. Name NVIC register map Description Access Reset value Address ISER0 to Interrupt Set-Enable Registers. These 2 registers allow enabling ISER1 interrupts and reading back the interrupt enables for specific peripheral functions. ICER0 to Interrupt Clear-Enable Registers. These 2 registers allow disabling ICER1 interrupts and reading back the interrupt enables for specific peripheral functions. ISPR0 to Interrupt Set-Pending Registers. These 2 registers allow changing ISPR1 the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. ICPR0 to Interrupt Clear-Pending Registers. These 2 registers allow ICPR1 changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. IABR0 to Interrupt Active Bit Registers. These 2 registers allow reading the IABR1 current interrupt active state for specific peripheral functions. IPR0 to IPR8 Interrupt Priority Registers. These 9 registers allow assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. RW 0 ISER0 - 0xE000 E100 ISER1 - 0xE000 E104 RW 0 ICER0 - 0xE000 E180 ICER1 - 0xE000 E184 RW 0 ISPR0 - 0xE000 E200 ISPR1 - 0xE000 E204 RW 0 ICPR0 - 0xE000 E280 ICPR1 - 0xE000 E284 RO RW 0 0 IABR0 - 0xE000 E300 IABR1 - 0xE000 E304 IPR0 - 0xE000 E400 IPR1 - 0xE000 E404 IPR2 - 0xE000 E408 IPR3 - 0xE000 E40C IPR4 - 0xE000 E410 IPR5 - 0xE000 E414 IPR6 - 0xE000 E418 IPR7 - 0xE000 E41C IPR8 - 0xE000 E420 STIR Software Trigger Interrupt Register. This register allows software to WO generate an interrupt. 0 STIR - 0xE000 EF00 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 77 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100) The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are enabled via the ISER1 register (Section 6–5.2). Disabling interrupts is done through the ICER0 and ICER1 registers (Section 6–5.3 and Section 6–5.4). Table 52. Bit Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100) Function Name 0 ISE_WDT Watchdog Timer Interrupt Enable. Write: writing 0 has no effect, writing 1 enables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ISE_TIMER0 ISE_TIMER1 ISE_TIMER2 ISE_TIMER3 ISE_UART0 ISE_UART1 ISE_UART2 ISE_UART3 ISE_PWM ISE_I2C0 ISE_I2C1 ISE_I2C2 ISE_SPI ISE_SSP0 ISE_SSP1 ISE_PLL0 ISE_RTC ISE_EINT0 ISE_EINT1 ISE_EINT2 ISE_EINT3 ISE_ADC ISE_BOD ISE_USB ISE_CAN ISE_DMA ISE_I2S ISE_ENET ISE_RIT ISE_MCPWM ISE_QEI Timer 0 Interrupt Enable. See functional description for bit 0. Timer 1. Interrupt Enable. See functional description for bit 0. Timer 2 Interrupt Enable. See functional description for bit 0. Timer 3 Interrupt Enable. See functional description for bit 0. UART0 Interrupt Enable. See functional description for bit 0. UART1 Interrupt Enable. See functional description for bit 0. UART2 Interrupt Enable. See functional description for bit 0. UART3 Interrupt Enable. See functional description for bit 0. PWM1 Interrupt Enable. See functional description for bit 0. I2C0 Interrupt Enable. See functional description for bit 0. I2C1 Interrupt Enable. See functional description for bit 0. I2C2 Interrupt Enable. See functional description for bit 0. SPI Interrupt Enable. See functional description for bit 0. SSP0 Interrupt Enable. See functional description for bit 0. SSP1 Interrupt Enable. See functional description for bit 0. PLL0 (Main PLL) Interrupt Enable. See functional description for bit 0. Real Time Clock (RTC) Interrupt Enable. See functional description for bit 0. External Interrupt 0 Interrupt Enable. See functional description for bit 0. External Interrupt 1 Interrupt Enable. See functional description for bit 0. External Interrupt 2 Interrupt Enable. See functional description for bit 0. External Interrupt 3 Interrupt Enable. See functional description for bit 0. ADC Interrupt Enable. See functional description for bit 0. BOD Interrupt Enable. See functional description for bit 0. USB Interrupt Enable. See functional description for bit 0. CAN Interrupt Enable. See functional description for bit 0. GPDMA Interrupt Enable. See functional description for bit 0. I2S Interrupt Enable. See functional description for bit 0. Ethernet Interrupt Enable. See functional description for bit 0. Repetitive Interrupt Timer Interrupt Enable. See functional description for bit 0. Motor Control PWM Interrupt Enable. See functional description for bit 0. Quadrature Encoder Interface Interrupt Enable. See functional description for bit 0. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 78 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ICER0 and ICER1 registers (Section 6–5.3 and Section 6–5.4). Table 53. Bit Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) Function Name 0 ISE_PLL1 PLL1 (USB PLL) Interrupt Enable. Write: writing 0 has no effect, writing 1 enables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 2 ISE_USBACT ISE_CANACT USB Activity Interrupt Enable. See functional description for bit 0. CAN Activity Interrupt Enable. See functional description for bit 0. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 31:3 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 79 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1 register (Section 6–5.4). Enabling interrupts is done through the ISER0 and ISER1 registers (Section 6–5.1 and Section 6–5.2). Table 54. Bit Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) Function Name 0 ICE_WDT Watchdog Timer Interrupt Disable. Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ICE_TIMER0 ICE_TIMER1 ICE_TIMER2 ICE_TIMER3 ICE_UART0 ICE_UART1 ICE_UART2 ICE_UART3 ICE_PWM ICE_I2C0 ICE_I2C1 ICE_I2C2 ICE_SPI ICE_SSP0 ICE_SSP1 ICE_PLL0 ICE_RTC ICE_EINT0 ICE_EINT1 ICE_EINT2 ICE_EINT3 ICE_ADC ICE_BOD ICE_USB ICE_CAN ICE_DMA ICE_I2S ICE_ENET ICE_RIT ICE_MCPWM ICE_QEI Timer 0 Interrupt Disable. See functional description for bit 0. Timer 1. Interrupt Disable. See functional description for bit 0. Timer 2 Interrupt Disable. See functional description for bit 0. Timer 3 Interrupt Disable. See functional description for bit 0. UART0 Interrupt Disable. See functional description for bit 0. UART1 Interrupt Disable. See functional description for bit 0. UART2 Interrupt Disable. See functional description for bit 0. UART3 Interrupt Disable. See functional description for bit 0. PWM1 Interrupt Disable. See functional description for bit 0. I2C0 Interrupt Disable. See functional description for bit 0. I2C1 Interrupt Disable. See functional description for bit 0. I2C2 Interrupt Disable. See functional description for bit 0. SPI Interrupt Disable. See functional description for bit 0. SSP0 Interrupt Disable. See functional description for bit 0. SSP1 Interrupt Disable. See functional description for bit 0. PLL0 (Main PLL) Interrupt Disable. See functional description for bit 0. Real Time Clock (RTC) Interrupt Disable. See functional description for bit 0. External Interrupt 0 Interrupt Disable. See functional description for bit 0. External Interrupt 1 Interrupt Disable. See functional description for bit 0. External Interrupt 2 Interrupt Disable. See functional description for bit 0. External Interrupt 3 Interrupt Disable. See functional description for bit 0. ADC Interrupt Disable. See functional description for bit 0. BOD Interrupt Disable. See functional description for bit 0. USB Interrupt Disable. See functional description for bit 0. CAN Interrupt Disable. See functional description for bit 0. GPDMA Interrupt Disable. See functional description for bit 0. I2S Interrupt Disable. See functional description for bit 0. Ethernet Interrupt Disable. See functional description for bit 0. Repetitive Interrupt Timer Interrupt Disable. See functional description for bit 0. Motor Control PWM Interrupt Disable. See functional description for bit 0. Quadrature Encoder Interface Interrupt Disable. See functional description for bit 0. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 80 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Enabling interrupts is done through the ISER0 and ISER1 registers (Section 6–5.1 and Section 6–5.2). Table 55. Bit Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) Function Name 0 ICE_PLL1 PLL1 (USB PLL) Interrupt Disable. Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 2 ICE_USBACT ICE_CANACT USB Activity Interrupt Disable. See functional description for bit 0. CAN Activity Interrupt Disable. See functional description for bit 0. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 31:3 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 81 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200) The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state set via the ISPR1 register (Section 6–5.6). Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 6–5.7 and Section 6–5.8). Table 56. Bit Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200) Function Name 0 ISP_WDT Watchdog Timer Interrupt Pending set. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ISP_TIMER0 ISP_TIMER1 ISP_TIMER2 ISP_TIMER3 ISP_UART0 ISP_UART1 ISP_UART2 ISP_UART3 ISP_PWM ISP_I2C0 ISP_I2C1 ISP_I2C2 ISP_SPI ISP_SSP0 ISP_SSP1 ISP_PLL0 ISP_RTC ISP_EINT0 ISP_EINT1 ISP_EINT2 ISP_EINT3 ISP_ADC ISP_BOD ISP_USB ISP_CAN ISP_DMA ISP_I2S ISP_ENET ISP_RIT ISP_MCPWM ISP_QEI Timer 0 Interrupt Pending set. See functional description for bit 0. Timer 1. Interrupt Pending set. See functional description for bit 0. Timer 2 Interrupt Pending set. See functional description for bit 0. Timer 3 Interrupt Pending set. See functional description for bit 0. UART0 Interrupt Pending set. See functional description for bit 0. UART1 Interrupt Pending set. See functional description for bit 0. UART2 Interrupt Pending set. See functional description for bit 0. UART3 Interrupt Pending set. See functional description for bit 0. PWM1 Interrupt Pending set. See functional description for bit 0. I2C0 Interrupt Pending set. See functional description for bit 0. I2C1 Interrupt Pending set. See functional description for bit 0. I2C2 Interrupt Pending set. See functional description for bit 0. SPI Interrupt Pending set. See functional description for bit 0. SSP0 Interrupt Pending set. See functional description for bit 0. SSP1 Interrupt Pending set. See functional description for bit 0. PLL0 (Main PLL) Interrupt Pending set. See functional description for bit 0. Real Time Clock (RTC) Interrupt Pending set. See functional description for bit 0. External Interrupt 0 Interrupt Pending set. See functional description for bit 0. External Interrupt 1 Interrupt Pending set. See functional description for bit 0. External Interrupt 2 Interrupt Pending set. See functional description for bit 0. External Interrupt 3 Interrupt Pending set. See functional description for bit 0. ADC Interrupt Pending set. See functional description for bit 0. BOD Interrupt Pending set. See functional description for bit 0. USB Interrupt Pending set. See functional description for bit 0. CAN Interrupt Pending set. See functional description for bit 0. GPDMA Interrupt Pending set. See functional description for bit 0. I2S Interrupt Pending set. See functional description for bit 0. Ethernet Interrupt Pending set. See functional description for bit 0. Repetitive Interrupt Timer Interrupt Pending set. See functional description for bit 0. Motor Control PWM Interrupt Pending set. See functional description for bit 0. Quadrature Encoder Interface Interrupt Pending set. See functional description for bit 0. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 82 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 6–5.7 and Section 6–5.8). Table 57. Bit Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) Function Name 0 ISP_PLL1 PLL1 (USB PLL) Interrupt Pending set. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 2 ISP_USBACT ISP_CANACT USB Activity Interrupt Pending set. See functional description for bit 0. CAN Activity Interrupt Pending set. See functional description for bit 0. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 31:3 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 83 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state cleared via the ICPR1 register (Section 6–5.8). Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6–5.5 and Section 6–5.6). Table 58. Bit Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) Function Name 0 ICP_WDT Watchdog Timer Interrupt Pending clear. Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ICP_TIMER0 ICP_TIMER1 ICP_TIMER2 ICP_TIMER3 ICP_UART0 ICP_UART1 ICP_UART2 ICP_UART3 ICP_PWM ICP_I2C0 ICP_I2C1 ICP_I2C2 ICP_SPI ICP_SSP0 ICP_SSP1 ICP_PLL0 ICP_RTC ICP_EINT0 ICP_EINT1 ICP_EINT2 ICP_EINT3 ICP_ADC ICP_BOD ICP_USB ICP_CAN ICP_DMA ICP_I2S ICP_ENET ICP_RIT ICP_MCPWM ICP_QEI Timer 0 Interrupt Pending clear. See functional description for bit 0. Timer 1. Interrupt Pending clear. See functional description for bit 0. Timer 2 Interrupt Pending clear. See functional description for bit 0. Timer 3 Interrupt Pending clear. See functional description for bit 0. UART0 Interrupt Pending clear. See functional description for bit 0. UART1 Interrupt Pending clear. See functional description for bit 0. UART2 Interrupt Pending clear. See functional description for bit 0. UART3 Interrupt Pending clear. See functional description for bit 0. PWM1 Interrupt Pending clear. See functional description for bit 0. I2C0 Interrupt Pending clear. See functional description for bit 0. I2C1 Interrupt Pending clear. See functional description for bit 0. I2C2 Interrupt Pending clear. See functional description for bit 0. SPI Interrupt Pending clear. See functional description for bit 0. SSP0 Interrupt Pending clear. See functional description for bit 0. SSP1 Interrupt Pending clear. See functional description for bit 0. PLL0 (Main PLL) Interrupt Pending clear. See functional description for bit 0. Real Time Clock (RTC) Interrupt Pending clear. See functional description for bit 0. External Interrupt 0 Interrupt Pending clear. See functional description for bit 0. External Interrupt 1 Interrupt Pending clear. See functional description for bit 0. External Interrupt 2 Interrupt Pending clear. See functional description for bit 0. External Interrupt 3 Interrupt Pending clear. See functional description for bit 0. ADC Interrupt Pending clear. See functional description for bit 0. BOD Interrupt Pending clear. See functional description for bit 0. USB Interrupt Pending clear. See functional description for bit 0. CAN Interrupt Pending clear. See functional description for bit 0. GPDMA Interrupt Pending clear. See functional description for bit 0. I2S Interrupt Pending clear. See functional description for bit 0. Ethernet Interrupt Pending clear. See functional description for bit 0. Repetitive Interrupt Timer Interrupt Pending clear. See functional description for bit 0. Motor Control PWM Interrupt Pending clear. See functional description for bit 0. Quadrature Encoder Interface Interrupt Pending clear. See functional description for bit 0. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 84 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284) The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6–5.5 and Section 6–5.6). Table 59. Bit Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) Function Name 0 ICP_PLL1 PLL1 (USB PLL) Interrupt Pending clear. Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 2 ICP_USBACT ICP_CANACT USB Activity Interrupt Pending clear. See functional description for bit 0. CAN Activity Interrupt Pending clear. See functional description for bit 0. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 31:3 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 85 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. The remaining interrupts can have their active state read via the IABR1 register (Section 6–5.10). Table 60. Bit Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) Function Name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IAB_WDT IAB_TIMER0 IAB_TIMER1 IAB_TIMER2 IAB_TIMER3 IAB_UART0 IAB_UART1 IAB_UART2 IAB_UART3 IAB_PWM IAB_I2C0 IAB_I2C1 IAB_I2C2 IAB_SPI IAB_SSP0 IAB_SSP1 IAB_PLL0 IAB_RTC IAB_EINT0 IAB_EINT1 IAB_EINT2 IAB_EINT3 IAB_ADC IAB_BOD IAB_USB IAB_CAN IAB_DMA IAB_I2S IAB_ENET IAB_RIT IAB_MCPWM IAB_QEI Watchdog Timer Interrupt Active. Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. Timer 0 Interrupt Active. See functional description for bit 0. Timer 1. Interrupt Active. See functional description for bit 0. Timer 2 Interrupt Active. See functional description for bit 0. Timer 3 Interrupt Active. See functional description for bit 0. UART0 Interrupt Active. See functional description for bit 0. UART1 Interrupt Active. See functional description for bit 0. UART2 Interrupt Active. See functional description for bit 0. UART3 Interrupt Active. See functional description for bit 0. PWM1 Interrupt Active. See functional description for bit 0. I2C0 Interrupt Active. See functional description for bit 0. I2C1 Interrupt Active. See functional description for bit 0. I2C2 Interrupt Active. See functional description for bit 0. SPI Interrupt Active. See functional description for bit 0. SSP0 Interrupt Active. See functional description for bit 0. SSP1 Interrupt Active. See functional description for bit 0. PLL0 (Main PLL) Interrupt Active. See functional description for bit 0. Real Time Clock (RTC) Interrupt Active. See functional description for bit 0. External Interrupt 0 Interrupt Active. See functional description for bit 0. External Interrupt 1 Interrupt Active. See functional description for bit 0. External Interrupt 2 Interrupt Active. See functional description for bit 0. External Interrupt 3 Interrupt Active. See functional description for bit 0. ADC Interrupt Active. See functional description for bit 0. BOD Interrupt Active. See functional description for bit 0. USB Interrupt Active. See functional description for bit 0. CAN Interrupt Active. See functional description for bit 0. GPDMA Interrupt Active. See functional description for bit 0. I2S Interrupt Active. See functional description for bit 0. Ethernet Interrupt Active. See functional description for bit 0. Repetitive Interrupt Timer Interrupt Active. See functional description for bit 0. Motor Control PWM Interrupt Active. See functional description for bit 0. Quadrature Encoder Interface Interrupt Active. See functional description for bit 0. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 86 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. Table 61. Bit Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) Function Name 0 1 2 IAB_PLL1 IAB_USBACT IAB_CANACT PLL1 (USB PLL) Interrupt Active. Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. USB Activity Interrupt Active. See functional description for bit 0. CAN Activity Interrupt Active. See functional description for bit 0. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 31:3 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 87 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400) The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 62. Bit Interrupt Priority Register 0 (IPR0 - 0xE000 E400) Function Name 2:0 7:3 10:8 Unimplemented IP_WDT Unimplemented These bits ignore writes, and read as 0. Watchdog Timer Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. Timer 0 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. Timer 1 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. Timer 2 Interrupt Priority. See functional description for bits 7-3. 15:11 IP_TIMER0 18:16 Unimplemented 23:19 IP_TIMER1 26:24 Unimplemented 31:27 IP_TIMER2 5.12 Interrupt Priority Register 1 (IPR1 - 0xE000 E404) The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 63. Bit Interrupt Priority Register 1 (IPR1 - 0xE000 E404) Function Name 2:0 7:3 10:8 Unimplemented IP_TIMER3 Unimplemented These bits ignore writes, and read as 0. Timer 3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. UART0 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. UART1 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. UART2 Interrupt Priority. See functional description for bits 7-3. 15:11 IP_UART0 18:16 Unimplemented 23:19 IP_UART1 26:24 Unimplemented 31:27 IP_UART2 5.13 Interrupt Priority Register 2 (IPR2 - 0xE000 E408) The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 64. Bit Interrupt Priority Register 2 (IPR2 - 0xE000 E408) Function Name 2:0 7:3 10:8 Unimplemented IP_UART3 Unimplemented These bits ignore writes, and read as 0. UART3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. PWM Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. I2C0 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. I2C1 Interrupt Priority. See functional description for bits 7-3. 15:11 IP_PWM 18:16 Unimplemented 23:19 IP_I2C0 26:24 Unimplemented 31:27 IP_I2C1 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 88 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 65. Bit Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) Function Name 2:0 7:3 10:8 Unimplemented IP_I2C2 Unimplemented These bits ignore writes, and read as 0. I2C2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. SPI Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. SSP0 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. SSP1 Interrupt Priority. See functional description for bits 7-3. 15:11 IP_SPI 18:16 Unimplemented 23:19 IP_SSP0 26:24 Unimplemented 31:27 IP_SSP1 5.15 Interrupt Priority Register 4 (IPR4 - 0xE000 E410) The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 66. Bit Interrupt Priority Register 4 (IPR4 - 0xE000 E410) Function Name 2:0 7:3 10:8 Unimplemented IP_PLL0 Unimplemented These bits ignore writes, and read as 0. PLL0 (Main PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. Real Time Clock (RTC) Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. External Interrupt 0 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. External Interrupt 1 Interrupt Priority. See functional description for bits 7-3. 15:11 IP_RTC 18:16 Unimplemented 23:19 IP_EINT0 26:24 Unimplemented 31:27 IP_EINT1 5.16 Interrupt Priority Register 5 (IPR5 - 0xE000 E414) The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 67. Bit Interrupt Priority Register 5 (IPR5 - 0xE000 E414) Function Name 2:0 7:3 10:8 Unimplemented IP_EINT2 Unimplemented These bits ignore writes, and read as 0. External Interrupt 2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. External Interrupt 3 Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. ADC Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. BOD Interrupt Priority. See functional description for bits 7-3. 15:11 IP_EINT3 18:16 Unimplemented 23:19 IP_ADC 26:24 Unimplemented 31:27 IP_BOD UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 89 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418) The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 68. Bit Interrupt Priority Register 6 (IPR6 - 0xE000 E418) Function Name 2:0 7:3 10:8 Unimplemented IP_USB Unimplemented These bits ignore writes, and read as 0. USB Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. CAN Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. GPDMA Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. I2S Interrupt Priority. See functional description for bits 7-3. 15:11 IP_CAN 18:16 Unimplemented 23:19 IP_DMA 26:24 Unimplemented 31:27 IP_I2S 5.18 Interrupt Priority Register 7 (IPR7 - 0xE000 E41C) The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 69. Bit Interrupt Priority Register 7 (IPR7 - 0xE000 E41C) Function Name 2:0 7:3 10:8 Unimplemented IP_ENET Unimplemented These bits ignore writes, and read as 0. Ethernet Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. Repetitive Interrupt Timer Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. Motor Control PWM Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. Quadrature Encoder Interface Interrupt Priority. See functional description for bits 7-3. 15:11 IP_RIT 18:16 Unimplemented 23:19 IP_MCPWM 26:24 Unimplemented 31:27 IP_QEI 5.19 Interrupt Priority Register 8 (IPR8 - 0xE000 E420) The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 70. Bit Interrupt Priority Register 8 (IPR8 - 0xE000 E420) Function Name 2:0 7:3 10:8 Unimplemented IP_PLL1 Unimplemented These bits ignore writes, and read as 0. PLL1 (USB PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. These bits ignore writes, and read as 0. USB Activity Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. CAN Activity Interrupt Priority. See functional description for bits 7-3. These bits ignore writes, and read as 0. 15:11 IP_USBACT 18:16 Unimplemented 23:19 IP_CANACT 31:24 Unimplemented UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 90 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00) The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions. By default, only privileged software can write to the STIR register. Unprivileged software can be given this ability if privileged software sets the USERSETMPEND bit in the CCR register (see Section 34–4.3.8). Table 71. Bit Software Trigger Interrupt Register (STIR - 0xE000 EF00) Function Name 8:0 31:9 INTID - Writing a value to this field generates an interrupt for the specified the interrupt number (see Table 6–50). The range allowed for the LPC17xx is 0 to 111. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 91 of 835 UM10360 Chapter 7: LPC17xx Pin configuration Rev. 01 — 4 January 2010 User manual 1. LPC17xx pin configuration 100 1 76 75 51 50 61 60 41 40 002aae158 002aad945_1 25 26 Fig 14. LPC176x LQFP100 pin configuration 1 20 21 Fig 15. LPC175x LQFP80 pin configuration 1.1 LPC17xx pin description I/O pins on the LPC17xx are 5V tolerant and have input hysteresis unless indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In addition, when pins are selected to be A to D converter inputs, they are no longer 5V tolerant and must be limited to the voltage at the ADC positive reference pin (VREFP). UM10360_1 80 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 92 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description LQFP 100 LQFP 80 Type Description P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0] — General purpose digital input/output pin. RD1 — CAN1 receiver input. TXD3 — Transmitter output for UART3. SDA1 — I2C1 data input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details). P0[1] — General purpose digital input/output pin. TD1 — CAN1 transmitter output. RXD3 — Receiver input for UART3. SCL1 — I2C1 clock input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details). P0[2] — General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled. TXD0 — Transmitter output for UART0. AD0[7] — A/D converter 0, input 7. P0[3] — General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled. RXD0 — Receiver input for UART0. AD0[6] — A/D converter 0, input 6. P0[4] — General purpose digital input/output pin. I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. RD2 — CAN2 receiver input. CAP2[0] — Capture input for Timer 2, channel 0. P0[5] — General purpose digital input/output pin. I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. TD2 — CAN2 transmitter output. CAP2[1] — Capture input for Timer 2, channel 1. P0[6] — General purpose digital input/output pin. I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. SSEL1 — Slave Select for SSP1. MAT2[0] — Match output for Timer 2, channel 0. P0[7] — General purpose digital input/output pin. I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. SCK1 — Serial Clock for SSP1. MAT2[1] — Match output for Timer 2, channel 1. P0[0] / RD1 / TXD3 / SDA1 46 37 I/O I O I/O P0[1] / TD1 / RXD3 / SCL1 47 38 I/O O I I/O P0[2] / TXD0 / AD0[7] 98 79 I/O O I P0[3] / RXD0 / AD0[6] 99 80 I/O I I P0[4] / I2SRX_CLK / RD2 / CAP2[0] 81 - I/O I/O I I P0[5] / I2SRX_WS / 80 TD2 / CAP2[1] - I/O I/O O I P0[6] / I2SRX_SDA / SSEL1 / MAT2[0] 79 64 I/O I/O I/O O P0[7] / I2STX_CLK / SCK1 / MAT2[1] 78 63 I/O I/O I/O O UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 93 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description P0[8] / I2STX_WS / 77 MISO1 / MAT2[2] 62 I/O I/O P0[8] — General purpose digital input/output pin. I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. MISO1 — Master In Slave Out for SSP1. MAT2[2] — Match output for Timer 2, channel 2. P0[9] — General purpose digital input/output pin. I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. MOSI1 — Master Out Slave In for SSP1. MAT2[3] — Match output for Timer 2, channel 3. P0[10] — General purpose digital input/output pin. TXD2 — Transmitter output for UART2. SDA2 — I2C2 data input/output (this is not an open-drain pin). MAT3[0] — Match output for Timer 3, channel 0. P0[11] — General purpose digital input/output pin. RXD2 — Receiver input for UART2. SCL2 — I2C2 clock input/output (this is not an open-drain pin). MAT3[1] — Match output for Timer 3, channel 1. P0[15] — General purpose digital input/output pin. TXD1 — Transmitter output for UART1. SCK0 — Serial clock for SSP0. SCK — Serial clock for SPI. P0[16] — General purpose digital input/output pin. RXD1 — Receiver input for UART1. SSEL0 — Slave Select for SSP0. SSEL — Slave Select for SPI. P0[17] — General purpose digital input/output pin. CTS1 — Clear to Send input for UART1. MISO0 — Master In Slave Out for SSP0. MISO — Master In Slave Out for SPI. P0[18] — General purpose digital input/output pin. DCD1 — Data Carrier Detect input for UART1. MOSI0 — Master Out Slave In for SSP0. MOSI — Master Out Slave In for SPI. P0[19] — General purpose digital input/output pin. DSR1 — Data Set Ready input for UART1. SDA1 — I2C1 data input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details). I/O O P0[9] / I2STX_SDA / MOSI1 / MAT2[3] 76 61 I/O I/O I/O O P0[10] / TXD2 / SDA2 / MAT3[0] 48 39 I/O O I/O O P0[11] / RXD2 / SCL2 / MAT3[1] 49 40 I/O I I/O O P0[15] / TXD1 / SCK0 / SCK 62 47 I/O O I/O I/O P0[16] / RXD1 / SSEL0 / SSEL 63 48 I/O I I/O I/O P0[17] / CTS1 / MISO0 / MISO 61 46 I/O I I/O I/O P0[18] / DCD1 / MOSI0 / MOSI 60 45 I/O I I/O I/O P0[19] / DSR1 / SDA1 59 - I/O I I/O UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 94 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description P0[20] / DTR1 / SCL1 58 - I/O O I/O P0[20] — General purpose digital input/output pin. DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. SCL1 — I2C1 clock input/output (this pin is not fully compliant with the I2C-bus specification, see Section 19–4 for details). P0[21] — General purpose digital input/output pin. RI1 — Ring Indicator input for UART1. RD1 — CAN1 receiver input. P0[22] — General purpose digital input/output pin. RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. TD1 — CAN1 transmitter output. P0[23] — General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled. AD0[0] — A/D converter 0, input 0. I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. CAP3[0] — Capture input for Timer 3, channel 0. P0[24] — General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled. AD0[1] — A/D converter 0, input 1. I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. CAP3[1] — Capture input for Timer 3, channel 1. P0[25] — General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled. AD0[2] — A/D converter 0, input 2. I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. TXD3 — Transmitter output for UART3. P0[26] — General purpose digital input/output pin. When configured as an ADC input or DAC output, the digital section of the pad is disabled. AD0[3] — A/D converter 0, input 3. AOUT — D/A converter output. RXD3 — Receiver input for UART3. P0[27] — General purpose digital input/output pin. Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus specifications for 100 kHz standard mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). USB_SDA — USB port I2C serial data (OTG transceiver). © NXP B.V. 2010. All rights reserved. P0[21] / RI1 / RD1 57 - I/O I I P0[22] / RTS1 / TD1 56 44 I/O O O P0[23] / AD0[0] / I2SRX_CLK / CAP3[0] 9 - I/O I I/O I P0[24] / AD0[1] / I2SRX_WS / CAP3[1] 8 - I/O I I/O I P0[25] / AD0[2] / I2SRX_SDA / TXD3 7 7 I/O I I/O O P0[26] / AD0[3] / AOUT / RXD3 6 6 I/O I O I P0[27] / SDA0 / USB_SDA 25 I/O I/O I/O UM10360_1 User manual Rev. 01 — 4 January 2010 95 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description P0[28] / SCL0 / USB_SCL 24 - I/O P0[28] — General purpose digital input/output pin. Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus specifications for 100 kHz standard mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). USB_SCL — USB port I2C serial clock (OTG transceiver). P0[29] — General purpose digital input/output pin. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). USB_D+ — USB bidirectional D+ line. P0[30] — General purpose digital input/output pin. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). USB_D− — USB bidirectional D− line. Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0] — General purpose digital input/output pin. ENET_TXD0 — Ethernet transmit data 0. P1[1] — General purpose digital input/output pin. ENET_TXD1 — Ethernet transmit data 1. P1[4] — General purpose digital input/output pin. ENET_TX_EN — Ethernet transmit data enable. P1[8] — General purpose digital input/output pin. ENET_CRS — Ethernet carrier sense. P1[9] — General purpose digital input/output pin. ENET_RXD0 — Ethernet receive data. P1[10] — General purpose digital input/output pin. ENET_RXD1 — Ethernet receive data. P1[14] — General purpose digital input/output pin. ENET_RX_ER — Ethernet receive error. P1[15] — General purpose digital input/output pin. ENET_REF_CLK — Ethernet reference clock. P1[16] — General purpose digital input/output pin. ENET_MDC — Ethernet MIIM clock. P1[17] — General purpose digital input/output pin. ENET_MDIO — Ethernet MIIM data input and output. I/O I/O P0[29] / USB_D+ 29 22 I/O I/O P0[30] / USB_D− 30 23 I/O I/O P1[0] to P1[31] I/O P1[0] / ENET_TXD0 P1[1] / ENET_TXD1 P1[4] / ENET_TX_EN P1[8] / ENET_CRS P1[9] / ENET_RXD0 P1[10] / ENET_RXD1 P1[14] / ENET_RX_ER P1[15] / ENET_REF_CLK P1[16] / ENET_MDC P1[17] / ENET_MDIO 95 94 93 92 91 90 89 88 87 86 76 75 74 73 72 71 70 69 - I/O O I/O O I/O O I/O I I/O I I/O I I/O I I/O I I/O O I/O I/O - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 96 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description P1[18] / 32 USB_UP_LED / PWM1[1] / CAP1[0] 25 I/O O P1[18] — General purpose digital input/output pin. USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. PWM1[1] — Pulse Width Modulator 1, channel 1 output. CAP1[0] — Capture input for Timer 1, channel 0. P1[19] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. USB_PPWR — Port Power enable signal for USB port. CAP1[1] — Capture input for Timer 1, channel 1. P1[20] — General purpose digital input/output pin. MCI0 — Motor control PWM channel 0 input. Also Quadrature Encoder Interface PHA input. PWM1[2] — Pulse Width Modulator 1, channel 2 output. SCK0 — Serial clock for SSP0. P1[21] — General purpose digital input/output pin. MCABORT — Motor control PWM, active low fast abort. PWM1[3] — Pulse Width Modulator 1, channel 3 output. SSEL0 — Slave Select for SSP0. P1[22] — General purpose digital input/output pin. MCOB0 — Motor control PWM channel 0, output B. USB_PWRD — Power Status for USB port (host power switch). MAT1[0] — Match output for Timer 1, channel 0. P1[23] — General purpose digital input/output pin. MCI1 — Motor control PWM channel 1 input. Also Quadrature Encoder Interface PHB input. PWM1[4] — Pulse Width Modulator 1, channel 4 output. MISO0 — Master In Slave Out for SSP0. P1[24] — General purpose digital input/output pin. MCI2 — Motor control PWM channel 2 input. Also Quadrature Encoder Interface INDEX input. PWM1[5] — Pulse Width Modulator 1, channel 5 output. MOSI0 — Master Out Slave in for SSP0. P1[25] — General purpose digital input/output pin. MCOA1 — Motor control PWM channel 1, output A. MAT1[1] — Match output for Timer 1, channel 1. P1[26] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B. PWM1[6] — Pulse Width Modulator 1, channel 6 output. CAP0[0] — Capture input for Timer 0, channel 0. O I P1[19] / MCOA0 / USB_PPWR / CAP1[1] 33 26 I/O O O I P1[20] / MCI0 / PWM1[2] / SCK0 34 27 I/O I O I/O P1[21] / MCABORT / PWM1[3] / SSEL0 35 - I/O O O I/O P1[22] / MCOB0 / USB_PWRD / MAT1[0] 36 28 I/O O I O P1[23] / MCI1 / PWM1[4] / MISO0 37 29 I/O I O I/O P1[24] / MCI2 / PWM1[5] / MOSI0 38 30 I/O I O I/O P1[25] / MCOA1 / MAT1[1] 39 31 I/O O O P1[26] / MCOB1 / 40 PWM1[6] / CAP0[0] 32 I/O O O I UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 97 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description P1[27] / CLKOUT / USB_OVRCR / CAP0[1] 43 - I/O O I I P1[27] — General purpose digital input/output pin. CLKOUT — Clock output pin. USB_OVRCR — USB port Over-Current status. CAP0[1] — Capture input for Timer 0, channel 1. P1[28] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A. PCAP1[0] — Capture input for PWM1, channel 0. MAT0[0] — Match output for Timer 0, channel 0. P1[29] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. PCAP1[1] — Capture input for PWM1, channel 1. MAT0[1] — Match output for Timer 0, channel 0. P1[30] — General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled. VBUS — Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. AD0[4] — A/D converter 0, input 4. P1[31] — General purpose digital input/output pin. When configured as an ADC input, digital section of the pad is disabled. SCK1 — Serial Clock for SSP1. AD0[5] — A/D converter 0, input 5. Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0] — General purpose digital input/output pin. PWM1[1] — Pulse Width Modulator 1, channel 1 output. TXD1 — Transmitter output for UART1. P2[1] — General purpose digital input/output pin. PWM1[2] — Pulse Width Modulator 1, channel 2 output. RXD1 — Receiver input for UART1. P2[2] — General purpose digital input/output pin. PWM1[3] — Pulse Width Modulator 1, channel 3 output. CTS1 — Clear to Send input for UART1. TRACEDATA[3] — Trace data, bit 3. P2[3] — General purpose digital input/output pin. PWM1[4] — Pulse Width Modulator 1, channel 4 output. DCD1 — Data Carrier Detect input for UART1. TRACEDATA[2] — Trace data, bit 2. P1[28] / MCOA2 / 44 PCAP1[0] / MAT0[0] 35 I/O O I O P1[29] / MCOB2 / PCAP1[1] / MAT0[1] 45 36 I/O O I O P1[30] / VBUS / AD0[4] 21 18 I/O I I P1[31] / SCK1 / AD0[5] 20 17 I/O I/O I P2[0] to P2[31] I/O P2[0] / PWM1[1] / TXD1 75 60 I/O O O P2[1] / PWM1[2] / RXD1 74 59 I/O O I P2[2] / PWM1[3] / CTS1 / TRACEDATA[3] 73 58 I/O O I O P2[3] / PWM1[4] / DCD1 / TRACEDATA[2] 70 55 I/O O I O UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 98 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description P2[4] / PWM1[5] / DSR1 / TRACEDATA[1] 69 54 I/O O I O P2[4] — General purpose digital input/output pin. PWM1[5] — Pulse Width Modulator 1, channel 5 output. DSR1 — Data Set Ready input for UART1. TRACEDATA[1] — Trace data, bit 1. P2[5] — General purpose digital input/output pin. PWM1[6] — Pulse Width Modulator 1, channel 6 output. DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. TRACEDATA[0] — Trace data, bit 0. P2[6] — General purpose digital input/output pin. PCAP1[0] — Capture input for PWM1, channel 0. RI1 — Ring Indicator input for UART1. TRACECLK — Trace Clock. P2[7] — General purpose digital input/output pin. RD2 — CAN2 receiver input. RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8] — General purpose digital input/output pin. TD2 — CAN2 transmitter output. TXD2 — Transmitter output for UART2. ENET_MDC — Ethernet MIIM clock. P2[9] — General purpose digital input/output pin. USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature. RXD2 — Receiver input for UART2. ENET_MDIO — Ethernet MIIM data input and output. P2[10] — General purpose digital input/output pin. 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. Note: A LOW on this pin while RESET is LOW forces the on-chip bootloader to take over control of the part after a reset and go into ISP mode. See Section 32–1. P2[5] / PWM1[6] / DTR1 / TRACEDATA[0] 68 53 I/O O O O P2[6] / PCAP1[0] / RI1 / TRACECLK 67 52 I/O I I O P2[7] / RD2 / RTS1 66 51 I/O I O P2[8] / TD2 / 65 TXD2 / ENET_MDC 50 I/O O O O P2[9] / USB_CONNECT / RXD2 / ENET_MDIO 64 49 I/O O I I/O P2[10] / EINT0 / NMI 53 41 I/O I I P2[11] / EINT1 / I2STX_CLK 52 I/O I I/O EINT0 — External interrupt 0 input. NMI — Non-maskable interrupt input. P2[11] — General purpose digital input/output pin. 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. EINT1 — External interrupt 1 input. I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 99 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description P2[12] / EINT2 / I2STX_WS 51 - I/O I I/O P2[12] — General purpose digital input/output pin. 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. EINT2 — External interrupt 2 input. I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. P2[13] — General purpose digital input/output pin. 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. EINT3 — External interrupt 3 input. I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25] — General purpose digital input/output pin. MAT0[0] — Match output for Timer 0, channel 0. PWM1[2] — Pulse Width Modulator 1, output 2. P3[26] — General purpose digital input/output pin. STCLK — System tick timer clock input. MAT0[1] — Match output for Timer 0, channel 1. PWM1[3] — Pulse Width Modulator 1, output 3. Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28] — General purpose digital input/output pin. RX_MCLK — I2S receive master clock. MAT2[0] — Match output for Timer 2, channel 0. TXD3 — Transmitter output for UART3. P4[29] — General purpose digital input/output pin. TX_MCLK — I2S transmit master clock. MAT2[1] — Match output for Timer 2, channel 1. RXD3 — Receiver input for UART3. TDO — Test Data out for JTAG interface. SWO — Serial wire trace output. TDI — Test Data in for JTAG interface. TMS — Test Mode Select for JTAG interface. SWDIO — Serial wire debug data input/output. TRST — Test Reset for JTAG interface. TCK — Test Clock for JTAG interface. SWDCLK — Serial wire clock. RTCK — JTAG interface control signal. © NXP B.V. 2010. All rights reserved. P2[13] / EINT3 / I2STX_SDA 50 - I/O I I/O P3[0] to P3[31] I/O P3[25] / MAT0[0] / PWM1[2] 27 - I/O O O P3[26] / STCLK / 26 MAT0[1] / PWM1[3] - I/O I O O P4[0] to P4[31] I/O P4[28] / RX_MCLK / MAT2[0] / TXD3 82 65 I/O I O O P4[29] TX_MCLK / MAT2[1] / RXD3 85 68 I/O I O I TDO / SWO TDI TMS / SWDIO TRST TCK / SWDCLK RTCK UM10360_1 1 2 3 4 5 100 1 2 3 4 5 O O I I I/O I I I I/O - User manual Rev. 01 — 4 January 2010 100 of 835 NXP Semiconductors UM10360 Chapter 7: LPC17xx Pin configuration Table 72. Symbol Pin description …continued LQFP 100 LQFP 80 Type Description RSTOUT RESET 14 17 11 14 O I RSTOUT — This is a 3.3 V pin. A LOW on this pin indicates that the LPC17xx is in a Reset state. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This is a 5 V tolerant pad with a 20 ns glitch filter, TTL levels and hysteresis. XTAL1 XTAL2 RTCX1 RTCX2 VSS 22[1] 23[1] 16[1] 18[1] 19[1] 20[1] 13[1] 15[1] I O I O Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Input to the RTC oscillator circuit. Output from the RTC oscillator circuit. ground: 0 V reference. 31, 41, 24, 33, I 55, 72, 43, 57, 83, 97[1] 66, 78[1] 11[1] 9[1] I VSSA VDD(3V3) VDD(REG)(3V3) VDDA analog ground: 0 V reference. This should be the same voltage as VSS, but should be isolated to minimize noise and error. 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the Vbat domain. 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. analog 3.3 V pad supply voltage: This can be connected to the same supply as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Note: this pin should be tied to 3.3v if the ADC and DAC are not used. ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. The voltage level on this pin is used as a reference for ADC and DAC. Note: this pin should be tied to 3.3v if the ADC and DAC are not used. ADC negative reference voltage: This should be the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. RTC domain power supply: 3.3 V on this pin supplies the power to the RTC peripheral. 28, 54, 21, 42, I 71, 96[1] 56, 77[1] 42, 84[1] 34, 67[1] I 10[1] 8[1] I VREFP 12[1] 10[1] I VREFN 15[1] 12[1] I VBAT n.c. [1] 19[1] 13 16[1] - I - not connected Pad provides special analog functionality. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 101 of 835 UM10360 Chapter 8: LPC17xx Pin connect block Rev. 01 — 4 January 2010 User manual 1. How to read this chapter Table 8–73 shows the functions of the PINSEL registers in the LPC17xx. Table 73. Register Summary of PINSEL registers Controls Table PINSEL0 PINSEL1 PINSEL2 PINSEL3 PINSEL4 PINSEL5 PINSEL6 PINSEL7 PINSEL8 PINSEL9 PINSEL10 P0[15:0] P0 [31:16] P1 [15:0] (Ethernet) P1 [31:16] P2 [15:0] P2 [31:16] P3 [15:0] P3 [31:16] P4 [15:0] P4 [31:16] Trace port enable Table 8–78 Table 8–79 Table 8–80 Table 8–81 Table 8–82 not used not used Table 8–83 not used Table 8–84 Table 8–85 2. Description The pin connect block allows most pins of the microcontroller to have more than one potential function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Selection of a single function on a port pin excludes other peripheral functions available on the same pin. However, the GPIO input stays connected and may be read by software or used to contribute to the GPIO interrupt feature. 3. Pin function select register values The PINSEL registers control the functions of device pins as shown below. Pairs of bits in these registers correspond to specific device pins. Table 74. Pin function select register bits Value after Reset PINSEL0 to Function PINSEL9 Values 00 01 10 11 UM10360_1 Primary (default) function, typically GPIO port First alternate function Second alternate function Third alternate function 00 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 102 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block The direction control bit in the GPIO registers is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet. Multiple connections Since a particular peripheral function may be allowed on more than one pin, it is in principle possible to configure more than one pin to perform the same function. If a peripheral output function is configured to appear on more than one pin, it will in fact be routed to those pins. If a peripheral input function is configured to appear on more than one pin for some reason, the peripheral will receive its input from the lowest port number. For instance, any pin of port 0 will take precedence over any pin of a higher numbered port, and pin 0 of any port will take precedence over a higher numbered pin of the same port. 4. Pin mode select register values The PINMODE registers control the input mode of all ports. This includes the use of the on-chip pull-up/pull-down resistor feature and a special open drain operating mode. The on-chip pull-up/pull-down resistor can be selected for every port pin regardless of the function on this pin with the exception of the I2C pins for the I2C0 interface and the USB pins (see Section 8–5.10). Three bits are used to control the mode of a port pin, two in a PINMODE register, and an additional one in a PINMODE_OD register. Bits are reserved for unused pins as in the PINSEL registers. Table 75. Pin Mode Select register Bits Value after Reset PINMODE0 to Function PINMODE9 Values 00 01 10 11 Pin has an on-chip pull-up resistor enabled. Repeater mode (see text below). Pin has neither pull-up nor pull-down resistor enabled. Pin has an on-chip pull-down resistor enabled. 00 Repeater mode enables the pull-up resistor if the pin is at a logic high and enables the pull-down resistor if the pin is at a logic low. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the Deep Power-down mode. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven. The PINMODE_OD registers control the open drain mode for ports. The open drain mode causes the pin to be pulled low normally if it is configured as an output and the data value is 0. If the data value is 1, the output drive of the pin is turned off, equivalent to changing the pin direction. This combination simulates an open drain output. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 103 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Open Drain Pin Mode Select register Bits Value after Reset Table 76. PINMODE_OD0 to Function PINMODE_OD4 Values 0 1 Pin is in the normal (not open drain) mode. Pin is in the open drain mode. 00 Function of PINMODE in open drain mode Normally the value of PINMODE applies to a pin only when it is in the input mode. When a pin is in the open drain mode, caused by a 1 in the corresponding bit of one of the PINMODE_OD registers, the input mode still does not apply when the pin is outputting a 0. However, when the pin value is 1, PINMODE applies since this state turns off the pin’s output driver. For example, this allows for the possibility of configuring a pin to be open drain with an on-chip pullup. A pullup in this case which is only on when the pin is not being pulled low by the pin’s own output. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 104 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block 5. Register description The Pin Control Module contains 11 registers as shown in Table 8–77 below. Table 77. Name Pin Connect Block Register Map Description Access Reset Value[1] Address PINSEL0 PINSEL1 PINSEL2 PINSEL3 PINSEL4 PINSEL7 PINSEL8 PINSEL9 PINSEL10 PINMODE0 PINMODE1 PINMODE2 PINMODE3 PINMODE4 PINMODE5 PINMODE6 PINMODE7 PINMODE9 PINMODE_OD0 PINMODE_OD1 PINMODE_OD2 PINMODE_OD3 PINMODE_OD4 I2CPADCFG [1] Pin function select register 0. Pin function select register 1. Pin function select register 2. Pin function select register 3. Pin function select register 4 Pin function select register 7 Pin function select register 8 Pin function select register 9 Pin function select register 10 Pin mode select register 0 Pin mode select register 1 Pin mode select register 2 Pin mode select register 3. Pin mode select register 4 Pin mode select register 5 Pin mode select register 6 Pin mode select register 7 Pin mode select register 9 Open drain mode control register 0 Open drain mode control register 1 Open drain mode control register 2 Open drain mode control register 3 Open drain mode control register 4 I2C Pin Configuration register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x4002 C000 0x4002 C004 0x4002 C008 0x4002 C00C 0x4002 C010 0x4002 C01C 0x4002 C020 0x4002 C024 0x4002 C028 0x4002 C040 0x4002 C044 0x4002 C048 0x4002 C04C 0x4002 C050 0x4002 C054 0x4002 C058 0x4002 C05C 0x4002 C064 0x4002 C068 0x4002 C06C 0x4002 C070 0x4002 C074 0x4002 C078 0x4002 C07C Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Pin control module register reset values On external reset, watchdog reset, power-on-reset (POR), and BOD reset, all registers in this module are reset to '0'. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 105 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block 5.1 Pin Function Select register 0 (PINSEL0 - 0x4002 C000) The PINSEL0 register controls the functions of the lower half of Port 0. The direction control bit in FIO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, the direction is controlled automatically. Table 78. Pin function select register 0 (PINSEL0 - address 0x4002 C000) bit description Function when Function when 01 00 Function when 10 Function when 11 Reset value PINSEL0 Pin name 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 29:24 31:30 [1] P0.0 P0.1 P0.2 P0.3 P0.4[1] P0.5[1] P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.15 GPIO Port 0.0 GPIO Port 0.1 GPIO Port 0.2 GPIO Port 0.3 GPIO Port 0.4 GPIO Port 0.5 GPIO Port 0.6 GPIO Port 0.7 GPIO Port 0.8 GPIO Port 0.9 GPIO Port 0.10 GPIO Port 0.11 Reserved GPIO Port 0.15 RD1 TD1 TXD0 RXD0 I2SRX_CLK I2SRX_WS I2SRX_SDA I2STX_CLK I2STX_WS I2STX_SDA TXD2 RXD2 Reserved TXD1 TXD3 RXD3 AD0.7 AD0.6 RD2 TD2 SSEL1 SCK1 MISO1 MOSI1 SDA2 SCL2 Reserved SCK0 SDA1 SCL1 Reserved Reserved CAP2.0 CAP2.1 MAT2.0 MAT2.1 MAT2.2 MAT2.3 MAT3.0 MAT3.1 Reserved SCK 00 00 00 00 00 00 00 00 00 00 00 00 0 00 Not available on 80-pin package. 5.2 Pin Function Select Register 1 (PINSEL1 - 0x4002 C004) The PINSEL1 register controls the functions of the upper half of Port 0. The direction control bit in the FIO0DIR register is effective only when the GPIO function is selected for a pin. For other functions the direction is controlled automatically. Table 79. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description Function when 10 Function when 11 Reset value PINSEL1 Pin name Function when Function 00 when 01 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 UM10360_1 P0.16 P0.17 P0.18 P0.19[1] P0.20[1] P0.21[1] P0.22 P0.23[1] P0.24[1] P0.25 P0.26 P0.27[1][2] P0.28[1][2] GPIO Port 0.16 GPIO Port 0.17 GPIO Port 0.18 GPIO Port 0.19 GPIO Port 0.20 GPIO Port 0.21 GPIO Port 0.22 GPIO Port 0.23 GPIO Port 0.24 GPIO Port 0.25 GPIO Port 0.26 GPIO Port 0.27 GPIO Port 0.28 RXD1 CTS1 DCD1 DSR1 DTR1 RI1 RTS1 AD0.0 AD0.1 AD0.2 AD0.3 SDA0 SCL0 SSEL0 MISO0 MOSI0 Reserved Reserved Reserved Reserved I2SRX_CLK I2SRX_WS I2SRX_SDA AOUT USB_SDA USB_SCL SSEL MISO MOSI SDA1 SCL1 RD1 TD1 CAP3.0 CAP3.1 TXD3 RXD3 Reserved Reserved 00 00 00 00 00 00 00 00 00 00 00 00 00 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 106 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description Function when 10 Function when 11 Reset value Table 79. PINSEL1 Pin name Function when Function 00 when 01 27:26 29:28 31:30 [1] [2] P0.29 P0.30 - GPIO Port 0.29 GPIO Port 0.30 Reserved USB_D+ USB_D− Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00 00 00 Not available on 80-pin package. Pins P027] and P0[28] are open-drain for I2C-bus compliance. 5.3 Pin Function Select register 2 (PINSEL2 - 0x4002 C008) The PINSEL2 register controls the functions of the lower half of Port 1, which contains the Ethernet related pins. The direction control bit in the FIO1DIR register is effective only when the GPIO function is selected for a pin. For other functions, the direction is controlled automatically. Table 80. Pin function select register 2 (PINSEL2 - address 0x4002 C008) bit description Function when Function when 00 01 Function when 10 Function when 11 Reset value PINSEL2 Pin name 1:0 3:2 7:4 9:8 15:10 17:16 19:18 21:20 27:22 29:28 31:30 P1.0 P1.1 P1.4 P1.8 P1.9 P1.10 P1.14 P1.15 GPIO Port 1.0 GPIO Port 1.1 Reserved GPIO Port 1.4 Reserved GPIO Port 1.8 GPIO Port 1.9 GPIO Port 1.10 Reserved GPIO Port 1.14 GPIO Port 1.15 ENET_TXD0 ENET_TXD1 Reserved ENET_TX_EN Reserved ENET_CRS ENET_RXD0 ENET_RXD1 Reserved ENET_RX_ER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00 00 0 00 0 00 00 00 0 00 00 ENET_REF_CLK Reserved 5.4 Pin Function Select Register 3 (PINSEL3 - 0x4002 C00C) The PINSEL3 register controls the functions of the upper half of Port 1. The direction control bit in the FIO1DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 81. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description Function when Function when 00 01 Function when 10 Function when 11 Reset value PINSEL3 Pin name 1:0 3:2 5:4 7:6 9:8 11:10 13:12 UM10360_1 P1.16[1] P1.17[1] P1.18 P1.19 P1.20 P1.21[1] P1.22 GPIO Port 1.16 ENET_MDC GPIO Port 1.17 ENET_MDIO GPIO Port 1.18 USB_UP_LED GPIO Port 1.19 MCOA0 GPIO Port 1.20 MCI0 GPIO Port 1.21 MCABORT GPIO Port 1.22 MCOB0 Reserved Reserved PWM1.1 USB_PPWR PWM1.2 PWM1.3 USB_PWRD Reserved Reserved CAP1.0 CAP1.1 SCK0 SSEL0 MAT1.0 00 00 00 00 00 00 00 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 107 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description Function when Function when 00 01 Function when 10 Function when 11 Reset value Table 81. PINSEL3 Pin name 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 [1] P1.23 P1.24 P1.25 P1.26 P1.27[1] P1.28 P1.29 P1.30 P1.31 GPIO Port 1.23 MCI1 GPIO Port 1.24 MCI2 GPIO Port 1.25 MCOA1 GPIO Port 1.26 MCOB1 GPIO Port 1.27 CLKOUT GPIO Port 1.28 MCOA2 GPIO Port 1.29 MCOB2 GPIO Port 1.30 Reserved GPIO Port 1.31 Reserved PWM1.4 PWM1.5 Reserved PWM1.6 PCAP1.0 PCAP1.1 VBUS SCK1 MISO0 MOSI0 MAT1.1 CAP0.0 MAT0.0 MAT0.1 AD0.4 AD0.5 00 00 00 00 00 00 00 00 00 USB_OVRCR CAP0.1 Not available on 80-pin package. 5.5 Pin Function Select Register 4 (PINSEL4 - 0x4002 C010) The PINSEL4 register controls the functions of the lower half of Port 2. The direction control bit in the FIO2DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 82. Pin function select register 4 (PINSEL4 - address 0x4002 C010) bit description Function when Function when 01 Function 00 when 10 Function when Reset 11 value PINSEL4 Pin name 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 31:28 [1] [2] P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11[1] P2.12[1] P2.13[1] - GPIO Port 2.0 GPIO Port 2.1 GPIO Port 2.2 GPIO Port 2.3 GPIO Port 2.4 GPIO Port 2.5 GPIO Port 2.6 GPIO Port 2.7 GPIO Port 2.8 GPIO Port 2.9 GPIO Port 2.10 GPIO Port 2.11 GPIO Port 2.12 GPIO Port 2.13 Reserved PWM1.1 PWM1.2 PWM1.3 PWM1.4 PWM1.5 PWM1.6 PCAP1.0 RD2 TD2 USB_CONNECT EINT0 EINT1 EINT2 EINT3 Reserved TXD1 RXD1 CTS1 DCD1 DSR1 DTR1 RI1 RTS1 TXD2 RXD2 NMI Reserved Reserved Reserved Reserved Reserved Reserved Reserved [2] Reserved [2] Reserved Reserved Reserved ENET_MDC ENET_MDIO Reserved I2STX_CLK I2STX_WS I2STX_SDA Reserved [2] [2] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 Reserved [2] Not available on 80-pin package. These pins support a debug trace function when selected via a development tool or by writing to the PINSEL10 register. See Section 8–5.8 “Pin Function Select Register 10 (PINSEL10 - 0x4002 C028)” for details. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 108 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block 5.6 Pin Function Select Register 7 (PINSEL7 - 0x4002 C01C) The PINSEL7 register controls the functions of the upper half of Port 3. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 83. Pin function select register 7 (PINSEL7 - address 0x4002 C01C) bit description Function when Function 00 when 01 Function when 10 Function when 11 Reset value PINSEL7 Pin name 17:0 19:18 21:20 31:22 [1] P3.25[1] P3.26[1] - Reserved GPIO Port 3.25 GPIO Port 3.26 Reserved Reserved Reserved STCLK Reserved Reserved MAT0.0 MAT0.1 Reserved Reserved PWM1.2 PWM1.3 Reserved 0 00 00 0 Not available on 80-pin package. 5.7 Pin Function Select Register 9 (PINSEL9 - 0x4002 C024) The PINSEL9 register controls the functions of the upper half of Port 4. The direction control bit in the FIO4DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 84. Pin function select register 9 (PINSEL9 - address 0x4002 C024) bit description Function when Function 00 when 01 Function when 10 Function when 11 Reset value PINSEL9 Pin name 23:0 25:24 27:26 31:28 P4.28 P4.29 - Reserved GPIO Port 4.28 GPIO Port 4.29 Reserved Reserved RX_MCLK TX_MCLK Reserved Reserved MAT2.0 MAT2.1 Reserved Reserved TXD3 RXD3 Reserved 00 00 00 00 5.8 Pin Function Select Register 10 (PINSEL10 - 0x4002 C028) Only bit 3 of this register is used to control the Trace function on pins P2.2 through P2.6. Table 85. Bit Pin function select register 10 (PINSEL10 - address 0x4002 C028) bit description Value Description Reset value Symbol 2:0 3 GPIO/TRACE 0 1 Reserved. Software should not write 1 to these bits. NA TPIU interface pins control. TPIU interface is disabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content. Reserved. Software should not write 1 to these bits. NA 0 31:4 - - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 109 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block 5.9 Pin Mode select register 0 (PINMODE0 - 0x4002 C040) This register controls pull-up/pull-down resistor configuration for Port 0 pins 0 to 15. Table 86. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description Value Description Reset value PINMODE0 Symbol 1:0 P0.00MODE 00 01 10 11 Port 0 pin 0 on-chip pull-up/down resistor control. P0.0 pin has a pull-up resistor enabled. P0.0 pin has repeater mode enabled. P0.0 pin has neither pull-up nor pull-down. P0.0 has a pull-down resistor enabled. Port 0 pin 1 control, see P0.00MODE. Port 0 pin 2 control, see P0.00MODE. Port 0 pin 3 control, see P0.00MODE. Port 0 pin 4 control, see P0.00MODE. Port 0 pin 5 control, see P0.00MODE. Port 0 pin 6 control, see P0.00MODE. Port 0 pin 7 control, see P0.00MODE. Port 0 pin 8 control, see P0.00MODE. Port 0 pin 9control, see P0.00MODE. Port 0 pin 10 control, see P0.00MODE. Port 0 pin 11 control, see P0.00MODE. Reserved. Port 0 pin 15 control, see P0.00MODE. 00 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 29:24 31:30 [1] P0.01MODE P0.02MODE P0.03MODE P0.04MODE[1] P0.05MODE[1] P0.06MODE P0.07MODE P0.08MODE P0.09MODE P0.10MODE P0.11MODE P0.15MODE 00 00 00 00 00 00 00 00 00 00 00 NA 00 Not available on 80-pin package. 5.10 Pin Mode select register 1 (PINMODE1 - 0x4002 C044) This register controls pull-up/pull-down resistor configuration for Port 1 pins 16 to 26. For details see Section 8–4 “Pin mode select register values”. Table 87. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description Description Reset value PINMODE1 Symbol 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 P0.16MODE P0.17MODE P0.18MODE P0.19MODE[1] P0.20MODE[1] P0.21MODE[1] P0.22MODE P0.23MODE[1] P0.24MODE[1] P0.25MODE Port 1 pin 16 control, see P0.00MODE. Port 1 pin 17 control, see P0.00MODE. Port 1 pin 18 control, see P0.00MODE. Port 1 pin 19 control, see P0.00MODE. Port 1 pin 20control, see P0.00MODE. Port 1 pin 21 control, see P0.00MODE. Port 1 pin 22 control, see P0.00MODE. Port 1 pin 23 control, see P0.00MODE. Port 1 pin 24 control, see P0.00MODE. Port 1 pin 25 control, see P0.00MODE. 00 00 00 00 00 00 00 00 00 00 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 110 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description Description Reset value Table 87. PINMODE1 Symbol 21:20 29:22 31:30 [1] [2] P0.26MODE - Port 1 pin 26 control, see P0.00MODE. Reserved. Reserved. [2] 00 NA NA Not available on 80-pin package. The pin mode cannot be selected for pins P0[27] to P0[30]. Pins P0[27] and P0[28] are dedicated I2C open-drain pins without pull-up/down. Pins P0[29] and P0[30] are USB specific pins without configurable pull-up or pull-down resistors. Pins P0[29] and P0[30] also must have the same direction since they operate as a unit for the USB function, see Section 9–5.1 “GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009 C000 to 0x2009 C080)”. 5.11 Pin Mode select register 2 (PINMODE2 - 0x4002 C048) This register controls pull-up/pull-down resistor configuration for Port 1 pins 0 to 15. For details see Section 8–4 “Pin mode select register values”. Table 88. Pin Mode select register 2 (PINMODE2 - address 0x4002 C048) bit description Description Reset value PINMODE2 Symbol 1:0 3:2 7:4 9:8 15:10 17:16 19:18 21:20 27:22 29:28 31:30 P1.00MODE P1.01MODE P1.04MODE P1.08MODE P1.09MODE P1.10MODE P1.14MODE P1.15MODE Port 1 pin 0 control, see P0.00MODE. Port 1 pin 1 control, see P0.00MODE. Reserved. Port 1 pin 4 control, see P0.00MODE. Reserved. Port 1 pin 8 control, see P0.00MODE. Port 1 pin 9 control, see P0.00MODE. Port 1 pin 10 control, see P0.00MODE. Reserved. Port 1 pin 14 control, see P0.00MODE. Port 1 pin 15 control, see P0.00MODE. 00 00 NA 00 NA 00 00 00 NA 00 00 5.12 Pin Mode select register 3 (PINMODE3 - 0x4002 C04C) This register controls pull-up/pull-down resistor configuration for Port 1 pins 16 to 31. For details see Section 8–4 “Pin mode select register values”. Table 89. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description Description Reset value PINMODE3 Symbol 1:0 3:2 5:4 7:6 9:8 11:10 13:12 UM10360_1 P1.16MODE[1] P1.17MODE[1] P1.18MODE P1.19MODE P1.20MODE P1.21MODE[1] P1.22MODE Port 1 pin 16 control, see P0.00MODE. Port 1 pin 17 control, see P0.00MODE. Port 1 pin 18 control, see P0.00MODE. Port 1 pin 19 control, see P0.00MODE. Port 1 pin 20 control, see P0.00MODE. Port 1 pin 21 control, see P0.00MODE. Port 1 pin 22 control, see P0.00MODE. 00 00 00 00 00 00 00 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 111 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description Description Reset value Table 89. PINMODE3 Symbol 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 [1] P1.23MODE P1.24MODE P1.25MODE P1.26MODE P1.27MODE[1] P1.28MODE P1.29MODE P1.30MODE P1.31MODE Port 1 pin 23 control, see P0.00MODE. Port 1 pin 24 control, see P0.00MODE. Port 1 pin 25 control, see P0.00MODE. Port 1 pin 26 control, see P0.00MODE. Port 1 pin 27 control, see P0.00MODE. Port 1 pin 28 control, see P0.00MODE. Port 1 pin 29 control, see P0.00MODE. Port 1 pin 30 control, see P0.00MODE. Port 1 pin 31 control, see P0.00MODE. 00 00 00 00 00 00 00 00 00 Not available on 80-pin package. 5.13 Pin Mode select register 4 (PINMODE4 - 0x4002 C050) This register controls pull-up/pull-down resistor configuration for Port 2 pins 0 to 15. For details see Section 8–4 “Pin mode select register values”. Table 90. Pin Mode select register 4 (PINMODE4 - address 0x4002 C050) bit description Symbol Description Reset value PINMODE4 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 31:28 [1] P2.00MODE P2.01MODE P2.02MODE P2.03MODE P2.04MODE P2.05MODE P2.06MODE P2.07MODE P2.08MODE P2.09MODE P2.10MODE P2.11MODE[1] P2.12MODE[1] P2.13MODE[1] - Port 2 pin 0 control, see P0.00MODE. Port 2 pin 1 control, see P0.00MODE. Port 2 pin 2 control, see P0.00MODE. Port 2 pin 3 control, see P0.00MODE. Port 2 pin 4 control, see P0.00MODE. Port 2 pin 5 control, see P0.00MODE. Port 2 pin 6 control, see P0.00MODE. Port 2 pin 7 control, see P0.00MODE. Port 2 pin 8 control, see P0.00MODE. Port 2 pin 9 control, see P0.00MODE. Port 2 pin 10 control, see P0.00MODE. Port 2 pin 11 control, see P0.00MODE. Port 2 pin 12 control, see P0.00MODE. Port 2 pin 13 control, see P0.00MODE. Reserved. 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA Not available on 80-pin package. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 112 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block 5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C) This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For details see Section 8–4 “Pin mode select register values”. Table 91. Pin Mode select register 7 (PINMODE7 - address 0x4002 C05C) bit description Description Reset value PINMODE7 Symbol 17:0 19:18 21:20 31:22 [1] P3.25MODE[1] P3.26MODE[1] - Reserved Port 3 pin 25 control, see P0.00MODE. Port 3 pin 26 control, see P0.00MODE. Reserved. NA 00 00 NA Not available on 80-pin package. 5.15 Pin Mode select register 9 (PINMODE9 - 0x4002 C064) This register controls pull-up/pull-down resistor configuration for Port 4 pins 16 to 31. For details see Section 8–4 “Pin mode select register values”. Table 92. Pin Mode select register 9 (PINMODE9 - address 0x4002 C064) bit description Description Reset value PINMODE9 Symbol 23:0 25:24 27:26 31:28 P4.28MODE P4.29MODE - Reserved. Port 4 pin 28 control, see P0.00MODE. Port 4 pin 29 control, see P0.00MODE. Reserved. NA 00 00 NA 5.16 Open Drain Pin Mode select register 0 (PINMODE_OD0 - 0x4002 C068) This register controls the open drain mode for Port 0 pins. For details see Section 8–4 “Pin mode select register values”. Table 93. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description Value Description Reset value PINMODE Symbol _OD0 0 P0.00OD[3] 0 1 Port 0 pin 0 open drain mode control. P0.0 pin is in the normal (not open drain) mode. P0.0 pin is in the open drain mode. Port 0 pin 1 open drain mode control, see P0.00OD Port 0 pin 2 open drain mode control, see P0.00OD Port 0 pin 3 open drain mode control, see P0.00OD Port 0 pin 4 open drain mode control, see P0.00OD Port 0 pin 5 open drain mode control, see P0.00OD Port 0 pin 6 open drain mode control, see P0.00OD Port 0 pin 7 open drain mode control, see P0.00OD Port 0 pin 8 open drain mode control, see P0.00OD Port 0 pin 9 open drain mode control, see P0.00OD 0 1 2 3 4 5 6 7 8 9 P0.01OD[3] P0.02OD P0.03OD P0.04OD P0.05OD P0.06OD P0.07OD P0.08OD P0.09OD 0 0 0 0 0 0 0 0 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 113 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description Value Description Reset value Table 93. PINMODE Symbol _OD0 10 11 14:12 15 16 17 18 19 20 21 22 23 24 25 26 28:27 29 30 31 [1] [2] P0.10OD[3] P0.11OD[3] P0.15OD P0.16OD P0.17OD P0.18OD P0.19OD[3] P0.20OD[3] P0.21OD P0.22OD P0.23OD P0.24OD P0.25OD P0.26OD [2] Port 0 pin 10 open drain mode control, see P0.00OD Port 0 pin 11 open drain mode control, see P0.00OD Reserved. Port 0 pin 15 open drain mode control, see P0.00OD Port 0 pin 16 open drain mode control, see P0.00OD Port 0 pin 17 open drain mode control, see P0.00OD Port 0 pin 18 open drain mode control, see P0.00OD Port 0 pin 19 open drain mode control, see P0.00OD Port 0 pin 20open drain mode control, see P0.00OD Port 0 pin 21 open drain mode control, see P0.00OD Port 0 pin 22 open drain mode control, see P0.00OD Port 0 pin 23 open drain mode control, see P0.00OD Port 0 pin 24open drain mode control, see P0.00OD Port 0 pin 25 open drain mode control, see P0.00OD Port 0 pin 26 open drain mode control, see P0.00OD Reserved. Port 0 pin 29 open drain mode control, see P0.00OD Port 0 pin 30 open drain mode control, see P0.00OD Reserved. 0 0 NA 0 0 0 0 0 0 0 0 0 0 0 0 NA 0 0 NA P0.29OD P0.30OD Not available on 80-pin package. Port 0 pins 27 and 28 should be set up using the I2CPADCFG register if they are used for an I2C-bus. Bits 27 and 28 of PINMODE_OD0 do not have any affect on these pins, they are special open drain I2C-bus compatible pins. Port 0 bits 1:0, 11:10, and 20:19 may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0. [3] 5.17 Open Drain Pin Mode select register 1 (PINMODE_OD1 0x4002 C06C) This register controls the open drain mode for Port 1 pins. For details see Section 8–4 “Pin mode select register values”. Table 94. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description Value Description Reset value PINMODE Symbol _OD1 0 P1.00OD 0 1 Port 1 pin 0 open drain mode control. P1.0 pin is in the normal (not open drain) mode. P1.0 pin is in the open drain mode. Port 1 pin 1 open drain mode control, see P1.00OD Reserved. Port 1 pin 4 open drain mode control, see P1.00OD 0 1 3:2 4 P1.01OD P1.04OD 0 NA 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 114 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description Value Description Reset value Table 94. PINMODE Symbol _OD1 7:5 8 9 10 13:11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 [1] P1.08OD P1.09OD P1.10OD P1.14OD P1.15OD P1.16OD[1] P1.17OD[1] P1.18OD P1.19OD P1.20OD P1.21OD[1] P1.22OD P1.23OD P1.24OD P1.25OD P1.26OD P1.27OD[1] P1.28OD P1.29OD P1.30OD P1.31OD Not available on 80-pin package. Reserved. Port 1 pin 8 open drain mode control, see P1.00OD Port 1 pin 9 open drain mode control, see P1.00OD Port 1 pin 10 open drain mode control, see P1.00OD Reserved. Port 1 pin 14 open drain mode control, see P1.00OD Port 1 pin 15 open drain mode control, see P1.00OD Port 1 pin 16 open drain mode control, see P1.00OD Port 1 pin 17 open drain mode control, see P1.00OD Port 1 pin 18 open drain mode control, see P1.00OD Port 1 pin 19 open drain mode control, see P1.00OD Port 1 pin 20open drain mode control, see P1.00OD Port 1 pin 21 open drain mode control, see P1.00OD Port 1 pin 22 open drain mode control, see P1.00OD Port 1 pin 23 open drain mode control, see P1.00OD Port 1 pin 24open drain mode control, see P1.00OD Port 1 pin 25 open drain mode control, see P1.00OD Port 1 pin 26 open drain mode control, see P1.00OD Port 1 pin 27 open drain mode control, see P1.00OD Port 1 pin 28 open drain mode control, see P1.00OD Port 1 pin 29 open drain mode control, see P1.00OD Port 1 pin 30 open drain mode control, see P1.00OD Port 1 pin 31 open drain mode control. NA 0 0 0 NA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.18 Open Drain Pin Mode select register 2 (PINMODE_OD2 - 0x4002 C070) This register controls the open drain mode for Port 2 pins. For details see Section 8–4 “Pin mode select register values”. Table 95. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description Value Description Reset value PINMODE Symbol _OD2 0 P2.00OD 0 1 Port 2 pin 0 open drain mode control. P2.0 pin is in the normal (not open drain) mode. P2.0 pin is in the open drain mode. Port 2 pin 1 open drain mode control, see P2.00OD Port 2 pin 2 open drain mode control, see P2.00OD Port 2 pin 3 open drain mode control, see P2.00OD Port 2 pin 4 open drain mode control, see P2.00OD 0 1 2 3 4 UM10360_1 P2.01OD P2.02OD P2.03OD P2.04OD 0 0 0 0 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 115 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description Value Description Reset value Table 95. PINMODE Symbol _OD2 5 6 7 8 9 10 11 12 13 31:14 [1] P2.05OD P2.06OD P2.07OD P2.08OD P2.09OD P2.10OD P2.11OD[1] P2.12OD[1] P2.13OD[1] - Port 2 pin 5 open drain mode control, see P2.00OD Port 2 pin 6 open drain mode control, see P2.00OD Port 2 pin 7 open drain mode control, see P2.00OD Port 2 pin 8 open drain mode control, see P2.00OD Port 2 pin 9 open drain mode control, see P2.00OD Port 2 pin 10 open drain mode control, see P2.00OD Port 2 pin 11 open drain mode control, see P2.00OD Port 2 pin 12 open drain mode control, see P2.00OD Port 2 pin 13 open drain mode control, see P2.00OD Reserved. 0 0 0 0 0 0 0 0 0 NA Not available on 80-pin package. 5.19 Open Drain Pin Mode select register 3 (PINMODE_OD3 - 0x4002 C074) This register controls the open drain mode for Port 3 pins. For details see Section 8–4 “Pin mode select register values”. Table 96. Open Drain Pin Mode select register 3 (PINMODE_OD3 - address 0x4002 C074) bit description Value Description Reset value PINMODE Symbol _OD3 24:0 25 P3.25OD[1] 0 1 Reserved. Port 3 pin 0 open drain mode control. P3.25 pin is in the normal (not open drain) mode. P3.25 pin is in the open drain mode. Port 3 pin 26 open drain mode control, see P3.25OD Reserved. NA 0 26 31:27 [1] P3.26OD[1] - 0 NA Not available on 80-pin package. 5.20 Open Drain Pin Mode select register 4 (PINMODE_OD4 - 0x4002 C078) This register controls the open drain mode for Port 4 pins. For details see Section 8–4 “Pin mode select register values”. Table 97. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description Value Description Reset value PINMODE Symbol _OD4 27:0 - Reserved. NA UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 116 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description Value Description Reset value Table 97. PINMODE Symbol _OD4 28 P4.28OD 0 1 Port 4 pin 28 open drain mode control. P4.28 pin is in the normal (not open drain) mode. P4.28 pin is in the open drain mode. Port 4 pin 29 open drain mode control, see P4.28OD Reserved. 0 29 31:30 P4.28OD - 0 NA 5.21 I2C Pin Configuration register (I2CPADCFG - 0x4002 C07C) The I2CPADCFG register allows configuration of the I2C pins for the I2C0 interface only, in order to support various I2C-bus operating modes. For use in standard or Fast Mode I2C, the 4 bits in I2CPADCFG should be 0, the default value for this register. For Fast Mode Plus, the SDADRV0 and SCLDRV0 bits should be 1. For non-I2C use of these pins, it may be desirable to turn off I2C filtering and slew rate control by setting SDAI2C0 and SCLI2C0 to 1. See Table 8–98 below. Table 98. I2C Pin Configuration register (I2CPADCFG - address 0x4002 C07C) bit description Value Description Reset value I2CPADCFG Symbol 0 SDADRV0 0 1 Drive mode control for the SDA0 pin, P0.27. The SDA0 pin is in the standard drive mode. The SDA0 pin is in Fast Mode Plus drive mode. 0 1 SDAI2C0 0 1 I2C mode control for the SDA0 pin, P0.27. The SDA0 pin has I2C glitch filtering and slew rate control enabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled. Drive mode control for the SCL0 pin, P0.28. 0 1 The SCL0 pin is in the standard drive mode. The SCL0 pin is in Fast Mode Plus drive mode. 0 2 SCLDRV0 0 3 SCLI2C0 0 1 I2C mode control for the SCL0 pin, P0.28. The SCL0 pin has I2C glitch filtering and slew rate control enabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled. Reserved. 0 31:4 - NA UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 117 of 835 UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Rev. 01 — 4 January 2010 User manual 1. Basic configuration GPIOs are configured using the following registers: 1. Power: always enabled. 2. Pins: See Section 8–3 for GPIO pins and their modes. 3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see (Section 4–8.8). 4. Interrupts: Enable GPIO interrupts in IO0/2IntEnR (Table 9–113) or IO0/2IntEnF (Table 9–115). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 2. Features 2.1 Digital I/O ports • Accelerated GPIO functions: – GPIO registers are located on a peripheral AHB bus for fast I/O timing. – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte, half-word, and word addressable. – Entire port value can be written in one instruction. – GPIO registers are accessible by the GPDMA. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • All GPIO registers support Cortex-M3 bit-banding. • GPIO registers are accessible by the GPDMA controller to allow DMA of data to or from GPIOs, synchronized to any DMA request. • Direction control of individual port bits. • All I/Os default to input with pullup after reset. 2.2 Interrupt generating digital ports • Port 0 and Port 2 can provide a single interrupt for any combination of port pins. • Each port pin can be programmed to generate an interrupt on a rising edge, a falling edge, or both. • Edge detection is asynchronous, so it may operate when clocks are not present, such as during Power-down mode. With this feature, level triggered interrupts are not needed. • Each enabled interrupt contributes to a wake-up signal that can be used to bring the part out of Power-down mode. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 118 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) • Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending GPIO interrupts. • GPIO0 and GPIO2 interrupts share the same position in the NVIC with External Interrupt 3. 3. Applications • • • • • General purpose I/O Driving LEDs or other indicators Controlling off-chip devices Sensing digital inputs, detecting edges Bringing the part out of Power-down mode 4. Pin description Table 99. Pin Name GPIO pin description Type Description P0[30:0][1]; P1[31:0][2]; P2[13:0]; P3[26:25]; P4[29:28] Input/ Output General purpose input/output. These are typically shared with other peripherals functions and will therefore not all be available in an application. Packaging options may affect the number of GPIOs available in a particular device. Some pins may be limited by requirements of the alternate functions of the pin. For example, the pins containing the I2C0 functions are open-drain for any function selected on that pin. Details may be found in Section 7–1.1. [1] [2] P0[14:12] are not available. P1[2], P1[3], P1[7:5], P1[13:11] are not available. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 119 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 5. Register description Due to compatibility requirements with the LPC2300 series ARM7-based products, the LPC17xx implements portions of five 32-bit General Purpose I/O ports. Details on a specific GPIO port usage can be found in Section 8–3. The registers in Table 9–100 represent the enhanced GPIO features available on all of the GPIO ports. These registers are located on an AHB bus for fast read and write timing. They can all be accessed in byte, half-word, and word sizes. A mask register allows access to a group of bits in a single GPIO port independently from other bits in the same port. Table 100. GPIO register map (local bus accessible registers - enhanced GPIO features) Generic Name Description Access Reset PORTn Register value[1] Name & Address FIODIR Fast GPIO Port Direction control register. This register individually controls the direction of each port pin. R/W 0 FIO0DIR - 0x2009 C000 FIO1DIR - 0x2009 C020 FIO2DIR - 0x2009 C040 FIO3DIR - 0x2009 C060 FIO4DIR - 0x2009 C080 FIO0MASK - 0x2009 C010 FIO1MASK - 0x2009 C030 FIO2MASK - 0x2009 C050 FIO3MASK - 0x2009 C070 FIO4MASK - 0x2009 C090 FIO0PIN - 0x2009 C014 FIO1PIN - 0x2009 C034 FIO2PIN - 0x2009 C054 FIO3PIN - 0x2009 C074 FIO4PIN - 0x2009 C094 FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to R/W port (done via writes to FIOPIN, FIOSET, and FIOCLR, and reads of FIOPIN) alter or return only the bits enabled by zeros in this register. FIOPIN Fast Port Pin value register using FIOMASK. The current state R/W of digital port pins can be read from this register, regardless of pin direction or alternate function selection (as long as pins are not configured as an input to ADC). The value read is masked by ANDing with inverted FIOMASK. Writing to this register places corresponding values in all bits enabled by zeros in FIOMASK. Important: if an FIOPIN register is read, its bit(s) masked with 1 in the FIOMASK register will be read as 0 regardless of the physical pin state. 0 0 FIOSET Fast Port Output Set register using FIOMASK. This register R/W controls the state of output pins. Writing 1s produces highs at the corresponding port pins. Writing 0s has no effect. Reading this register returns the current contents of the port output register. Only bits enabled by 0 in FIOMASK can be altered. Fast Port Output Clear register using FIOMASK. This register WO controls the state of output pins. Writing 1s produces lows at the corresponding port pins. Writing 0s has no effect. Only bits enabled by 0 in FIOMASK can be altered. 0 FIO0SET - 0x2009 C018 FIO1SET - 0x2009 C038 FIO2SET - 0x2009 C058 FIO3SET - 0x2009 C078 FIO4SET - 0x2009 C098 FIO0CLR - 0x2009 C01C FIO1CLR - 0x2009 C03C FIO2CLR - 0x2009 C05C FIO3CLR - 0x2009 C07C FIO4CLR - 0x2009 C09C FIOCLR 0 [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 120 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 101. GPIO interrupt register map Generic Name Description Access Reset value[1] PORTn Register Name & Address IntEnR IntEnF IntStatR IntStatF IntClr IntStatus [1] GPIO Interrupt Enable for Rising edge. GPIO Interrupt Enable for Falling edge. GPIO Interrupt Status for Rising edge. GPIO Interrupt Status for Falling edge. GPIO Interrupt Clear. GPIO overall Interrupt Status. R/W R/W RO RO WO RO 0 0 0 0 0 0 IO0IntEnR - 0x4002 8090 IO2IntEnR - 0x4002 80B0 IO0IntEnR - 0x4002 8094 IO2IntEnR - 0x4002 80B4 IO0IntStatR - 0x4002 8084 IO2IntStatR - 0x4002 80A4 IO0IntStatF - 0x4002 8088 IO2IntStatF - 0x4002 80A8 IO0IntClr - 0x4002 808C IO2IntClr - 0x4002 80AC IOIntStatus - 0x4002 8080 Reset value reflects the data stored in used bits only. It does not include reserved bits content. 5.1 GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009 C000 to 0x2009 C080) This word accessible register is used to control the direction of the pins when they are configured as GPIO port pins. Direction bit for any pin must be set according to the pin functionality. Note that GPIO pins P0.29 and P0.30 are shared with the USB_D+ and USB_D- pins and must have the same direction. If either FIO0DIR bit 29 or 30 are configured as zero, both P0.29 and P0.30 will be inputs. If both FIO0DIR bits 29 and 30 are ones, both P0.29 and P0.30 will be outputs. Table 102. Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to 0x2009 C080) bit description Bit Symbol Value Description Reset value 31:0 FIO0DIR FIO1DIR FIO2DIR FIO3DIR FIOI4DIR Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31. 0 1 Controlled pin is input. Controlled pin is output. 0x0 Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 9–103, too. Next to providing the same functions as the FIODIR register, these additional registers allow easier and faster access to the physical port pins. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 121 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 103. Fast GPIO port Direction control byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxDIR0 Fast GPIO Port x Direction 8 (byte) control register 0. Bit 0 in R/W FIOxDIR0 register corresponds to pin Px.0 … bit 7 to pin Px.7. Fast GPIO Port x Direction 8 (byte) control register 1. Bit 0 in R/W FIOxDIR1 register corresponds to pin Px.8 … bit 7 to pin Px.15. Fast GPIO Port x Direction 8 (byte) control register 2. Bit 0 in R/W FIOxDIR2 register corresponds to pin Px.16 … bit 7 to pin Px.23. Fast GPIO Port x Direction 8 (byte) control register 3. Bit 0 in R/W FIOxDIR3 register corresponds to pin Px.24 … bit 7 to pin Px.31. Fast GPIO Port x Direction control Lower half-word register. Bit 0 in FIOxDIRL register corresponds to pin Px.0 … bit 15 to pin Px.15. Fast GPIO Port x Direction control Upper half-word register. Bit 0 in FIOxDIRU register corresponds to Px.16 … bit 15 to Px.31. 0x00 FIO0DIR0 - 0x2009 C000 FIO1DIR0 - 0x2009 C020 FIO2DIR0 - 0x2009 C040 FIO3DIR0 - 0x2009 C060 FIO4DIR0 - 0x2009 C080 FIO0DIR1 - 0x2009 C001 FIO1DIR1 - 0x2009 C021 FIO2DIR1 - 0x2009 C041 FIO3DIR1 - 0x2009 C061 FIO4DIR1 - 0x2009 C081 FIO0DIR2 - 0x2009 C002 FIO1DIR2 - 0x2009 C022 FIO2DIR2 - 0x2009 C042 FIO3DIR2 - 0x2009 C062 FIO4DIR2 - 0x2009 C082 FIO0DIR3 - 0x2009 C003 FIO1DIR3 - 0x2009 C023 FIO2DIR3 - 0x2009 C043 FIO3DIR3 - 0x2009 C063 FIO4DIR3 - 0x2009 C083 FIOxDIR1 0x00 FIO0DIR2 0x00 FIOxDIR3 0x00 FIOxDIRL 16 (half-word) 0x0000 FIO0DIRL - 0x2009 C000 R/W FIO1DIRL - 0x2009 C020 FIO2DIRL - 0x2009 C040 FIO3DIRL - 0x2009 C060 FIO4DIRL - 0x2009 C080 16 (half-word) 0x0000 FIO0DIRU - 0x2009 C002 R/W FIO1DIRU - 0x2009 C022 FIO2DIRU - 0x2009 C042 FIO3DIRU - 0x2009 C062 FIO4DIRU - 0x2009 C082 FIOxDIRU 5.2 GPIO port output Set register FIOxSET (FIO0SET to FIO4SET - 0x2009 C018 to 0x2009 C098) This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the FIOxSET has no effect. Reading the FIOxSET register returns the value of this register, as determined by previous writes to FIOxSET and FIOxCLR (or FIOxPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 122 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Access to a port pin via the FIOxSET register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9–5.5). Table 104. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018 to 0x2009 C098) bit description Bit Symbol Value Description Reset value 31:0 FIO0SET FIO1SET FIO2SET 0 FIO3SET FIO4SET 1 Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin Px.0, bit 31 in FIOxSET controls pin Px.31. Controlled pin output is unchanged. Controlled pin output is set to HIGH. 0x0 Aside from the 32-bit long and word only accessible FIOxSET register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 9–105, too. Next to providing the same functions as the FIOxSET register, these additional registers allow easier and faster access to the physical port pins. Table 105. Fast GPIO port output Set byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxSET0 Fast GPIO Port x output Set register 0. Bit 0 in FIOxSET0 register corresponds to pin Px.0 … bit 7 to pin Px.7. Fast GPIO Port x output Set register 1. Bit 0 in FIOxSET1 register corresponds to pin Px.8 … bit 7 to pin Px.15. Fast GPIO Port x output Set register 2. Bit 0 in FIOxSET2 register corresponds to pin Px.16 … bit 7 to pin Px.23. Fast GPIO Port x output Set register 3. Bit 0 in FIOxSET3 register corresponds to pin Px.24 … bit 7 to pin Px.31. 8 (byte) R/W 0x00 FIO0SET0 - 0x2009 C018 FIO1SET0 - 0x2009 C038 FIO2SET0 - 0x2009 C058 FIO3SET0 - 0x2009 C078 FIO4SET0 - 0x2009 C098 FIO0SET1 - 0x2009 C019 FIO1SET1 - 0x2009 C039 FIO2SET1 - 0x2009 C059 FIO3SET1 - 0x2009 C079 FIO4SET1 - 0x2009 C099 FIO0SET2 - 0x2009 C01A FIO1SET2 - 0x2009 C03A FIO2SET2 - 0x2009 C05A FIO3SET2 - 0x2009 C07A FIO4SET2 - 0x2009 C09A FIO0SET3 - 0x2009 C01B FIO1SET3 - 0x2009 C03B FIO2SET3 - 0x2009 C05B FIO3SET3 - 0x2009 C07B FIO4SET3 - 0x2009 C09B FIOxSET1 8 (byte) R/W 0x00 FIOxSET2 8 (byte) R/W 0x00 FIOxSET3 8 (byte) R/W 0x00 FIOxSETL Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETL - 0x2009 C018 Lower half-word register. Bit 0 R/W FIO1SETL - 0x2009 C038 in FIOxSETL register FIO2SETL - 0x2009 C058 corresponds to pin Px.0 … bit FIO3SETL - 0x2009 C078 15 to pin Px.15. FIO4SETL - 0x2009 C098 Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETU - 0x2009 C01A Upper half-word register. Bit 0 R/W FIO1SETU - 0x2009 C03A in FIOxSETU register FIO2SETU - 0x2009 C05A corresponds to Px.16 … bit FIO3SETU - 0x2009 C07A 15 to Px.31. FIO4SETU - 0x2009 C09A FIOxSETU UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 123 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR0x2009 C01C to 0x2009 C09C) This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears the corresponding bit in the FIOxSET register. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to FIOxCLR has no effect. Access to a port pin via the FIOxCLR register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9–5.5). Table 106. Fast GPIO port output Clear register (FIO0CLR to FIO4CLR- addresses 0x2009 C01C to 0x2009 C09C) bit description Bit Symbol Value Description Reset value 31:0 FIO0CLR FIO1CLR FIO2CLR 0 FIO3CLR FIO4CLR 1 Fast GPIO output value Clear bits. Bit 0 in FIOxCLR controls pin 0x0 Px.0, bit 31 controls pin Px.31. Controlled pin output is unchanged. Controlled pin output is set to LOW. Aside from the 32-bit long and word only accessible FIOxCLR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 9–107, too. Next to providing the same functions as the FIOxCLR register, these additional registers allow easier and faster access to the physical port pins. Table 107. Fast GPIO port output Clear byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxCLR0 Fast GPIO Port x output Clear register 0. Bit 0 in FIOxCLR0 register corresponds to pin Px.0 … bit 7 to pin Px.7. Fast GPIO Port x output Clear register 1. Bit 0 in FIOxCLR1 register corresponds to pin Px.8 … bit 7 to pin Px.15. Fast GPIO Port x output Clear register 2. Bit 0 in FIOxCLR2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 8 (byte) WO 0x00 FIO0CLR0 - 0x2009 C01C FIO1CLR0 - 0x2009 C03C FIO2CLR0 - 0x2009 C05C FIO3CLR0 - 0x2009 C07C FIO4CLR0 - 0x2009 C09C FIO0CLR1 - 0x2009 C01D FIO1CLR1 - 0x2009 C03D FIO2CLR1 - 0x2009 C05D FIO3CLR1 - 0x2009 C07D FIO4CLR1 - 0x2009 C09D FIO0CLR2 - 0x2009 C01E FIO1CLR2 - 0x2009 C03E FIO2CLR2 - 0x2009 C05E FIO3CLR2 - 0x2009 C07E FIO4CLR2 - 0x2009 C09E FIOxCLR1 8 (byte) WO 0x00 FIOxCLR2 8 (byte) WO 0x00 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 124 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 107. Fast GPIO port output Clear byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxCLR3 Fast GPIO Port x output Clear register 3. Bit 0 in FIOxCLR3 register corresponds to pin Px.24 … bit 7 to pin Px.31. Fast GPIO Port x output Clear Lower half-word register. Bit 0 in FIOxCLRL register corresponds to pin Px.0 … bit 15 to pin Px.15. 8 (byte) WO 0x00 FIO0CLR3 - 0x2009 C01F FIO1CLR3 - 0x2009 C03F FIO2CLR3 - 0x2009 C05F FIO3CLR3 - 0x2009 C07F FIO4CLR3 - 0x2009 C09F FIOxCLRL 16 (half-word) WO 0x0000 FIO0CLRL - 0x2009 C01C FIO1CLRL - 0x2009 C03C FIO2CLRL - 0x2009 C05C FIO3CLRL - 0x2009 C07C FIO4CLRL - 0x2009 C09C 0x0000 FIO0CLRU - 0x2009 C01E FIO1CLRU - 0x2009 C03E FIO2CLRU - 0x2009 C05E FIO3CLRU - 0x2009 C07E FIO4CLRU - 0x2009 C09E FIOxCLRU Fast GPIO Port x output Clear Upper half-word register. Bit 0 in FIOxCLRU register corresponds to pin Px.16 … bit 15 to Px.31. 16 (half-word) WO 5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009 C014 to 0x2009 C094) This register provides the value of port pins that are configured to perform only digital functions. The register will give the logic value of the pin regardless of whether the pin is configured for input or output, or as GPIO or an alternate digital function. As an example, a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output as selectable functions. Any configuration of that pin will allow its current logic state to be read from the corresponding FIOxPIN register. If a pin has an analog function as one of its options, the pin state cannot be read if the analog configuration is selected. Selecting the pin as an A/D input disconnects the digital features of the pin. In that case, the pin value read in the FIOxPIN register is not valid. Writing to the FIOxPIN register stores the value in the port output register, bypassing the need to use both the FIOxSET and FIOxCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port. Access to a port pin via the FIOxPIN register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9–5.5). Only pins masked with zeros in the Mask register (see Section 9–5.5) will be correlated to the current content of the Fast GPIO port pin value register. Table 108. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to 0x2009 C094) bit description Bit Symbol Value Description Reset value 31:0 FIO0VAL FIO1VAL FIO2VAL FIO3VAL FIO4VAL Fast GPIO output value Set bits. Bit 0 in FIOxCLR corresponds to pin Px.0, bit 31 in FIOxCLR corresponds to pin Px.31. 0 1 Controlled pin output is set to LOW. Controlled pin output is set to HIGH. 0x0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 125 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Aside from the 32-bit long and word only accessible FIOxPIN register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 9–109, too. Next to providing the same functions as the FIOxPIN register, these additional registers allow easier and faster access to the physical port pins. Table 109. Fast GPIO port Pin value byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxPIN0 Fast GPIO Port x Pin value register 0. Bit 0 in FIOxPIN0 register corresponds to pin Px.0 … bit 7 to pin Px.7. Fast GPIO Port x Pin value register 1. Bit 0 in FIOxPIN1 register corresponds to pin Px.8 … bit 7 to pin Px.15. Fast GPIO Port x Pin value register 2. Bit 0 in FIOxPIN2 register corresponds to pin Px.16 … bit 7 to pin Px.23. Fast GPIO Port x Pin value register 3. Bit 0 in FIOxPIN3 register corresponds to pin Px.24 … bit 7 to pin Px.31. Fast GPIO Port x Pin value Lower half-word register. Bit 0 in FIOxPINL register corresponds to pin Px.0 … bit 15 to pin Px.15. 8 (byte) R/W 0x00 FIO0PIN0 - 0x2009 C014 FIO1PIN0 - 0x2009 C034 FIO2PIN0 - 0x2009 C054 FIO3PIN0 - 0x2009 C074 FIO4PIN0 - 0x2009 C094 FIO0PIN1 - 0x2009 C015 FIO1PIN1 - 0x2009 C035 FIO2PIN1 - 0x2009 C055 FIO3PIN1 - 0x2009 C075 FIO4PIN1 - 0x2009 C095 FIO0PIN2 - 0x2009 C016 FIO1PIN2 - 0x2009 C036 FIO2PIN2 - 0x2009 C056 FIO3PIN2 - 0x2009 C076 FIO4PIN2 - 0x2009 C096 FIO0PIN3 - 0x2009 C017 FIO1PIN3 - 0x2009 C037 FIO2PIN3 - 0x2009 C057 FIO3PIN3 - 0x2009 C077 FIO4PIN3 - 0x2009 C097 FIOxPIN1 8 (byte) R/W 0x00 FIOxPIN2 8 (byte) R/W 0x00 FIOxPIN3 8 (byte) R/W 0x00 FIOxPINL 16 (half-word) 0x0000 FIO0PINL - 0x2009 C014 R/W FIO1PINL - 0x2009 C034 FIO2PINL - 0x2009 C054 FIO3PINL - 0x2009 C074 FIO4PINL - 0x2009 C094 FIOxPINU Fast GPIO Port x Pin value 16 (half-word) 0x0000 FIO0PINU - 0x2009 C016 Upper half-word register. Bit 0 R/W FIO1PINU - 0x2009 C036 in FIOxPINU register FIO2PINU - 0x2009 C056 corresponds to pin Px.16 … bit FIO3PINU - 0x2009 C076 15 to Px.31. FIO4PINU - 0x2009 C096 5.5 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK 0x2009 C010 to 0x2009 C090) This register is used to select port pins that will and will not be affected by write accesses to the FIOxPIN, FIOxSET or FIOxCLR register. Mask register also filters out port’s content when the FIOxPIN register is read. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 126 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) A zero in this register’s bit enables an access to the corresponding physical pin via a read or write access. If a bit in this register is one, corresponding pin will not be changed with write access and if read, will not be reflected in the updated FIOxPIN register. For software examples, see Section 9–6. Table 110. Fast GPIO port Mask register (FIO0MASK to FIO4MASK - addresses 0x2009 C010 to 0x2009 C090) bit description Bit Symbol Value Description Reset value 31:0 FIO0MASK FIO1MASK FIO2MASK FIO3MASK FIO4MASK Fast GPIO physical pin access control. 0 Controlled pin is affected by writes to the port’s FIOxSET, FIOxCLR, and FIOxPIN register(s). Current state of the pin can be read from the FIOxPIN register. Controlled pin is not affected by writes into the port’s FIOxSET, FIOxCLR and FIOxPIN register(s). When the FIOxPIN register is read, this bit will not be updated with the state of the physical pin. 0x0 1 Aside from the 32-bit long and word only accessible FIOxMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 9–111, too. Next to providing the same functions as the FIOxMASK register, these additional registers allow easier and faster access to the physical port pins. Table 111. Fast GPIO port Mask byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset PORTn Register value Address & Name FIOxMASK0 Fast GPIO Port x Mask register 0. Bit 0 in FIOxMASK0 register corresponds to pin Px.0 … bit 7 to pin Px.7. Fast GPIO Port x Mask register 1. Bit 0 in FIOxMASK1 register corresponds to pin Px.8 … bit 7 to pin Px.15. 8 (byte) R/W 0x0 FIO0MASK0 - 0x2009 C010 FIO1MASK0 - 0x2009 C030 FIO2MASK0 - 0x2009 C050 FIO3MASK0 - 0x2009 C070 FIO4MASK0 - 0x2009 C090 FIO0MASK1 - 0x2009 C011 FIO1MASK1 - 0x2009 C031 FIO2MASK1 - 0x2009 C051 FIO3MASK1 - 0x2009 C071 FIO4MASK1 - 0x2009 C091 FIO0MASK2 - 0x2009 C012 FIO1MASK2 - 0x2009 C032 FIO2MASK2 - 0x2009 C052 FIO3MASK2 - 0x2009 C072 FIO4MASK2 - 0x2009 C092 FIOxMASK1 8 (byte) R/W 0x0 FIOxMASK2 Fast GPIO Port x Mask 8 (byte) register 2. Bit 0 in R/W FIOxMASK2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 0x0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 127 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 111. Fast GPIO port Mask byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset PORTn Register value Address & Name FIOxMASK3 Fast GPIO Port x Mask 8 (byte) register 3. Bit 0 in R/W FIOxMASK3 register corresponds to pin Px.24 … bit 7 to pin Px.31. Fast GPIO Port x Mask Lower half-word register. Bit 0 in FIOxMASKL register corresponds to pin Px.0 … bit 15 to pin Px.15. Fast GPIO Port x Mask Upper half-word register. Bit 0 in FIOxMASKU register corresponds to pin Px.16 … bit 15 to Px.31. 16 (half-word) R/W 0x0 FIO0MASK3 - 0x2009 C013 FIO1MASK3 - 0x2009 C033 FIO2MASK3 - 0x2009 C053 FIO3MASK3 - 0x2009 C073 FIO4MASK3 - 0x2009 C093 FIO0MASKL - 0x2009 C010 FIO1MASKL - 0x2009 C030 FIO2MASKL - 0x2009 C050 FIO3MASKL - 0x2009 C070 FIO4MASKL - 0x2009 C090 FIO0MASKU - 0x2009 C012 FIO1MASKU - 0x2009 C032 FIO2MASKU - 0x2009 C052 FIO3MASKU - 0x2009 C072 FIO4MASKU - 0x2009 C092 FIOxMASKL 0x0 FIOxMASKU 16 (half-word) R/W 0x0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 128 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 5.6 GPIO interrupt registers The following registers configure the pins of Port 0 and Port 2 to generate interrupts. 5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts. Only status one bit per port is required. Table 112. GPIO overall Interrupt Status register (IOIntStatus - address 0x4002 8080) bit description Bit Symbol Value Description Reset value 0 P0Int 0 1 Port 0 GPIO interrupt pending. There are no pending interrupts on Port 0. There is at least one pending interrupt on Port 0. Reserved. The value read from a reserved bit is not defined. Port 2 GPIO interrupt pending. 0 1 There are no pending interrupts on Port 2. There is at least one pending interrupt on Port 2. Reserved. The value read from a reserved bit is not defined. 0 1 2 P2Int - NA 0 31:2 - - NA 5.6.2 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) Each bit in these read-write registers enables the rising edge interrupt for the corresponding port 0 pin. Table 113. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description Bit Symbol Value Description Reset value 0 P0.0ER 0 1 Enable rising edge interrupt for P0.0. Rising edge interrupt is disabled on P0.0. Rising edge interrupt is enabled on P0.0. Enable rising edge interrupt for P0.1. Enable rising edge interrupt for P0.2. Enable rising edge interrupt for P0.3. Enable rising edge interrupt for P0.4. Enable rising edge interrupt for P0.5. Enable rising edge interrupt for P0.6. Enable rising edge interrupt for P0.7. Enable rising edge interrupt for P0.8. Enable rising edge interrupt for P0.9. Enable rising edge interrupt for P0.10. Enable rising edge interrupt for P0.11. Reserved Enable rising edge interrupt for P0.15. Enable rising edge interrupt for P0.16. 0 1 2 3 4 5 6 7 8 9 10 11 15 16 P0.1ER P0.2ER P0.3ER P0.4ER[1] P0.5ER[1] P0.6ER P0.7ER P0.8ER P0.9ER P0.10ER P0.11ER P0.15ER P0.16ER 0 0 0 0 0 0 0 0 0 0 0 NA 0 0 14:12 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 129 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 113. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description Bit Symbol Value Description Reset value 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 [1] P0.17ER P0.18ER P0.19ER[1] P0.20ER[1] P0.21ER[1] P0.22ER P0.23ER[1] P0.24ER[1] P0.25ER P0.26ER P0.27ER[1] P0.28ER[1] P0.29ER P0.30ER - Enable rising edge interrupt for P0.17. Enable rising edge interrupt for P0.18. Enable rising edge interrupt for P0.19. Enable rising edge interrupt for P0.20. Enable rising edge interrupt for P0.21. Enable rising edge interrupt for P0.22. Enable rising edge interrupt for P0.23. Enable rising edge interrupt for P0.24. Enable rising edge interrupt for P0.25. Enable rising edge interrupt for P0.26. Enable rising edge interrupt for P0.27. Enable rising edge interrupt for P0.28. Enable rising edge interrupt for P0.29. Enable rising edge interrupt for P0.30. Reserved. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA Not available on 80-pin package. 5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) Each bit in these read-write registers enables the rising edge interrupt for the corresponding port 2 pin. Table 114. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description Bit Symbol Value Description Reset value 0 P2.0ER 0 1 Enable rising edge interrupt for P2.0. Rising edge interrupt is disabled on P2.0. Rising edge interrupt is enabled on P2.0. Enable rising edge interrupt for P2.1. Enable rising edge interrupt for P2.2. Enable rising edge interrupt for P2.3. Enable rising edge interrupt for P2.4. Enable rising edge interrupt for P2.5. Enable rising edge interrupt for P2.6. Enable rising edge interrupt for P2.7. Enable rising edge interrupt for P2.8. Enable rising edge interrupt for P2.9. Enable rising edge interrupt for P2.10. Enable rising edge interrupt for P2.11. 0 1 2 3 4 5 6 7 8 9 10 11 P2.1ER P2.2ER P2.3ER P2.4ER P2.5ER P2.6ER P2.7ER P2.8ER P2.9ER P2.10ER P2.11ER[1] 0 0 0 0 0 0 0 0 0 0 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 130 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 114. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description Bit Symbol Value Description Reset value 12 13 P2.12ER[1] P2.13ER[1] Enable rising edge interrupt for P2.12. Enable rising edge interrupt for P2.13. Reserved. 0 0 NA 31:14 [1] Not available on 80-pin package. 5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094) Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 0 pin. Table 115. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description Bit Symbol Value Description Reset value 0 P0.0EF 0 1 Enable falling edge interrupt for P0.0 Falling edge interrupt is disabled on P0.0. Falling edge interrupt is enabled on P0.0. Enable falling edge interrupt for P0.1. Enable falling edge interrupt for P0.2. Enable falling edge interrupt for P0.3. Enable falling edge interrupt for P0.4. Enable falling edge interrupt for P0.5. Enable falling edge interrupt for P0.6. Enable falling edge interrupt for P0.7. Enable falling edge interrupt for P0.8. Enable falling edge interrupt for P0.9. Enable falling edge interrupt for P0.10. Enable falling edge interrupt for P0.11. Reserved. Enable falling edge interrupt for P0.15. Enable falling edge interrupt for P0.16. Enable falling edge interrupt for P0.17. Enable falling edge interrupt for P0.18. Enable falling edge interrupt for P0.19. Enable falling edge interrupt for P0.20. Enable falling edge interrupt for P0.21. Enable falling edge interrupt for P0.22. Enable falling edge interrupt for P0.23. Enable falling edge interrupt for P0.24. Enable falling edge interrupt for P0.25. Enable falling edge interrupt for P0.26. Enable falling edge interrupt for P0.27. Rev. 01 — 4 January 2010 0 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 26 27 UM10360_1 P0.1EF P0.2EF P0.3EF P0.4EF[1] P0.5EF[1] P0.6EF P0.7EF P0.8EF P0.9EF P0.10EF P0.11EF P0.15EF P0.16EF P0.17EF P0.18EF P0.19EF[1] P0.20EF[1] P0.21EF[1] P0.22EF P0.23EF[1] P0.24EF[1] P0.25EF P0.26EF P0.27EF[1] 0 0 0 0 0 0 0 0 0 0 0 NA 0 0 0 0 0 0 0 0 0 0 0 0 0 © NXP B.V. 2010. All rights reserved. 14:12 - User manual 131 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 115. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description Bit Symbol Value Description Reset value 28 29 30 31 [1] P0.28EF[1] P0.29EF P0.30EF - Enable falling edge interrupt for P0.28. Enable falling edge interrupt for P0.29. Enable falling edge interrupt for P0.30. Reserved. 0 0 0 NA Not available on 80-pin package. 5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 2 pin. Table 116. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit description Bit Symbol Value Description Reset value 0 P2.0EF 0 1 Enable falling edge interrupt for P2.0 Falling edge interrupt is disabled on P2.0. Falling edge interrupt is enabled on P2.0. Enable falling edge interrupt for P2.1. Enable falling edge interrupt for P2.2. Enable falling edge interrupt for P2.3. Enable falling edge interrupt for P2.4. Enable falling edge interrupt for P2.5. Enable falling edge interrupt for P2.6. Enable falling edge interrupt for P2.7. Enable falling edge interrupt for P2.8. Enable falling edge interrupt for P2.9. Enable falling edge interrupt for P2.10. Enable falling edge interrupt for P2.11. Enable falling edge interrupt for P2.12. Enable falling edge interrupt for P2.13. Reserved. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 P2.1EF P2.2EF P2.3EF P2.4EF P2.5EF P2.6EF P2.7EF P2.8EF P2.9EF P2.10EF P2.11EF[1] P2.12EF[1] P2.13EF[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 NA 31:14 [1] Not available on 80-pin package. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 132 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR 0x4002 8084) Each bit in these read-only registers indicates the rising edge interrupt status for port 0. Table 117. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) bit description Bit Symbol Value Description Reset value 0 P0.0REI 0 1 Status of Rising Edge Interrupt for P0.0 A rising edge has not been detected on P0.0. Interrupt has been generated due to a rising edge on P0.0. Status of Rising Edge Interrupt for P0.1. Status of Rising Edge Interrupt for P0.2. Status of Rising Edge Interrupt for P0.3. Status of Rising Edge Interrupt for P0.4. Status of Rising Edge Interrupt for P0.5. Status of Rising Edge Interrupt for P0.6. Status of Rising Edge Interrupt for P0.7. Status of Rising Edge Interrupt for P0.8. Status of Rising Edge Interrupt for P0.9. Status of Rising Edge Interrupt for P0.10. Status of Rising Edge Interrupt for P0.11. Reserved. Status of Rising Edge Interrupt for P0.15. Status of Rising Edge Interrupt for P0.16. Status of Rising Edge Interrupt for P0.17. Status of Rising Edge Interrupt for P0.18. Status of Rising Edge Interrupt for P0.19. Status of Rising Edge Interrupt for P0.20. Status of Rising Edge Interrupt for P0.21. Status of Rising Edge Interrupt for P0.22. Status of Rising Edge Interrupt for P0.23. Status of Rising Edge Interrupt for P0.24. Status of Rising Edge Interrupt for P0.25. Status of Rising Edge Interrupt for P0.26. Status of Rising Edge Interrupt for P0.27. Status of Rising Edge Interrupt for P0.28. Status of Rising Edge Interrupt for P0.29. Status of Rising Edge Interrupt for P0.30. Reserved. 0 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 [1] P0.1REI P0.2REI P0.3REI P0.4REI[1] P0.5REI[1] P0.6REI P0.7REI P0.8REI P0.9REI P0.10REI P0.11REI P0.15REI P0.16REI P0.17REI P0.18REI P0.19REI[1] P0.20REI[1] P0.21REI[1] P0.22REI P0.23REI[1] P0.24REI[1] P0.25REI P0.26REI P0.27REI[1] P0.28REI[1] P0.29REI P0.30REI - 0 0 0 0 0 0 0 0 0 0 0 NA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA 14:12 - Not available on 80-pin package. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 133 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR 0x4002 80A4) Each bit in these read-only registers indicates the rising edge interrupt status for port 2. Table 118. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) bit description Bit Symbol Value Description Reset value 0 P2.0REI 0 1 Status of Rising Edge Interrupt for P2.0 A rising edge has not been detected on P2.0. Interrupt has been generated due to a rising edge on P2.0. Status of Rising Edge Interrupt for P2.1. Status of Rising Edge Interrupt for P2.2. Status of Rising Edge Interrupt for P2.3. Status of Rising Edge Interrupt for P2.4. Status of Rising Edge Interrupt for P2.5. Status of Rising Edge Interrupt for P2.6. Status of Rising Edge Interrupt for P2.7. Status of Rising Edge Interrupt for P2.8. Status of Rising Edge Interrupt for P2.9. Status of Rising Edge Interrupt for P2.10. Status of Rising Edge Interrupt for P2.11. Status of Rising Edge Interrupt for P2.12. Status of Rising Edge Interrupt for P2.13. Reserved. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 P2.1REI P2.2REI P2.3REI P2.4REI P2.5REI P2.6REI P2.7REI P2.8REI P2.9REI P2.10REI P2.11REI[1] P2.12REI[1] P2.13REI[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 NA 31:14 [1] Not available on 80-pin package. 5.6.8 GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF 0x4002 8088) Each bit in these read-only registers indicates the falling edge interrupt status for port 0. Table 119. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description Bit Symbol Value Description Reset value 0 P0.0FEI 0 1 Status of Falling Edge Interrupt for P0.0 A falling edge has not been detected on P0.0. Interrupt has been generated due to a falling edge on P0.0. Status of Falling Edge Interrupt for P0.1. Status of Falling Edge Interrupt for P0.2. Status of Falling Edge Interrupt for P0.3. Status of Falling Edge Interrupt for P0.4. Status of Falling Edge Interrupt for P0.5. Status of Falling Edge Interrupt for P0.6. Status of Falling Edge Interrupt for P0.7. 0 1 2 3 4 5 6 7 UM10360_1 P0.1FEI P0.2FEI P0.3FEI P0.4FEI[1] P0.5FEI[1] P0.6FEI P0.7FEI 0 0 0 0 0 0 0 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 134 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 119. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description Bit Symbol Value Description Reset value 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 [1] P0.8FEI P0.9FEI P0.10FEI P0.11FEI P0.15FEI P0.16FEI P0.17FEI P0.18FEI P0.19FEI[1] P0.20FEI[1] P0.21FEI[1] P0.22FEI P0.23FEI[1] P0.24FEI[1] P0.25FEI P0.26FEI P0.27FEI[1] P0.28FEI[1] P0.29FEI P0.30FEI - Status of Falling Edge Interrupt for P0.8. Status of Falling Edge Interrupt for P0.9. Status of Falling Edge Interrupt for P0.10. Status of Falling Edge Interrupt for P0.11. Reserved. Status of Falling Edge Interrupt for P0.15. Status of Falling Edge Interrupt for P0.16. Status of Falling Edge Interrupt for P0.17. Status of Falling Edge Interrupt for P0.18. Status of Falling Edge Interrupt for P0.19. Status of Falling Edge Interrupt for P0.20. Status of Falling Edge Interrupt for P0.21. Status of Falling Edge Interrupt for P0.22. Status of Falling Edge Interrupt for P0.23. Status of Falling Edge Interrupt for P0.24. Status of Falling Edge Interrupt for P0.25. Status of Falling Edge Interrupt for P0.26. Status of Falling Edge Interrupt for P0.27. Status of Falling Edge Interrupt for P0.28. Status of Falling Edge Interrupt for P0.29. Status of Falling Edge Interrupt for P0.30. Reserved. 0 0 0 0 NA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA 14:12 - Not available on 80-pin package. 5.6.9 GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF 0x4002 80A8) Each bit in these read-only registers indicates the falling edge interrupt status for port 2. Table 120. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description Bit Symbol Value Description Reset value 0 P2.0FEI 0 1 Status of Falling Edge Interrupt for P2.0 A falling edge has not been detected on P2.0. Interrupt has been generated due to a falling edge on P2.0. Status of Falling Edge Interrupt for P2.1. Status of Falling Edge Interrupt for P2.2. Status of Falling Edge Interrupt for P2.3. Status of Falling Edge Interrupt for P2.4. Status of Falling Edge Interrupt for P2.5. Status of Falling Edge Interrupt for P2.6. Rev. 01 — 4 January 2010 0 1 2 3 4 5 6 UM10360_1 P2.1FEI P2.2FEI P2.3FEI P2.4FEI P2.5FEI P2.6FEI 0 0 0 0 0 0 © NXP B.V. 2010. All rights reserved. User manual 135 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 120. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description Bit Symbol Value Description Reset value 7 8 9 10 11 12 13 P2.7FEI P2.8FEI P2.9FEI P2.10FEI P2.11FEI[1] P2.12FEI[1] P2.13FEI[1] Status of Falling Edge Interrupt for P2.7. Status of Falling Edge Interrupt for P2.8. Status of Falling Edge Interrupt for P2.9. Status of Falling Edge Interrupt for P2.10. Status of Falling Edge Interrupt for P2.11. Status of Falling Edge Interrupt for P2.12. Status of Falling Edge Interrupt for P2.13. Reserved. 0 0 0 0 0 0 0 NA 31:14 [1] Not available on 80-pin package. 5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C) Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 0 pin. Table 121. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description Bit Symbol Value Description Reset value 0 P0.0CI 0 1 Clear GPIO port Interrupts for P0.0 Corresponding bits in IOxIntStatR and IOxIntStatF are unchanged. Corresponding bits in IOxIntStatR and IOxStatF are cleared. Clear GPIO port Interrupts for P0.1. Clear GPIO port Interrupts for P0.2. Clear GPIO port Interrupts for P0.3. Clear GPIO port Interrupts for P0.4. Clear GPIO port Interrupts for P0.5. Clear GPIO port Interrupts for P0.6. Clear GPIO port Interrupts for P0.7. Clear GPIO port Interrupts for P0.8. Clear GPIO port Interrupts for P0.9. Clear GPIO port Interrupts for P0.10. Clear GPIO port Interrupts for P0.11. Reserved. Clear GPIO port Interrupts for P0.15. Clear GPIO port Interrupts for P0.16. Clear GPIO port Interrupts for P0.17. Clear GPIO port Interrupts for P0.18. Clear GPIO port Interrupts for P0.19. Clear GPIO port Interrupts for P0.20. Clear GPIO port Interrupts for P0.21. Clear GPIO port Interrupts for P0.22. Rev. 01 — 4 January 2010 0 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 UM10360_1 P0.1CI P0.2CI P0.3CI P0.4CI[1] P0.5CI[1] P0.6CI P0.7CI P0.8CI P0.9CI P0.10CI P0.11CI P0.15CI P0.16CI P0.17CI P0.18CI P0.19CI[1] P0.20CI[1] P0.21CI[1] P0.22CI 0 0 0 0 0 0 0 0 0 0 0 NA 0 0 0 0 0 0 0 0 © NXP B.V. 2010. All rights reserved. 14:12 - User manual 136 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Table 121. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description Bit Symbol Value Description Reset value 23 24 25 26 27 28 29 30 31 [1] P0.23CI[1] P0.24CI[1] P0.25CI P0.26CI P0.27CI[1] P0.28CI[1] P0.29CI P0.30CI - Clear GPIO port Interrupts for P0.23. Clear GPIO port Interrupts for P0.24. Clear GPIO port Interrupts for P0.25. Clear GPIO port Interrupts for P0.26. Clear GPIO port Interrupts for P0.27. Clear GPIO port Interrupts for P0.28. Clear GPIO port Interrupts for P0.29. Clear GPIO port Interrupts for P0.30. Reserved. 0 0 0 0 0 0 0 0 NA Not available on 80-pin package. 5.6.11 GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 2 pin. Table 122. GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) bit description Bit Symbol Value Description Reset value 0 P2.0CI 0 1 Clear GPIO port Interrupts for P2.0 Corresponding bits in IOxIntStatR and IOxIntStatF are unchanged. Corresponding bits in IOxIntStatR and IOxStatF are cleared. Clear GPIO port Interrupts for P2.1. Clear GPIO port Interrupts for P2.2. Clear GPIO port Interrupts for P2.3. Clear GPIO port Interrupts for P2.4. Clear GPIO port Interrupts for P2.5. Clear GPIO port Interrupts for P2.6. Clear GPIO port Interrupts for P2.7. Clear GPIO port Interrupts for P2.8. Clear GPIO port Interrupts for P2.9. Clear GPIO port Interrupts for P2.10. Clear GPIO port Interrupts for P2.11. Clear GPIO port Interrupts for P2.12. Clear GPIO port Interrupts for P2.13. Reserved. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 P2.1CI P2.2CI P2.3CI P2.4CI P2.5CI P2.6CI P2.7CI P2.8CI P2.9CI P2.10CI P2.11CI[1] P2.12CI[1] P2.13CI[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 NA 31:14 [1] Not available on 80-pin package. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 137 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 6. GPIO usage notes 6.1 Example: An instantaneous output of 0s and 1s on a GPIO port Solution 1: using 32-bit (word) accessible fast GPIO registers FIO0MASK = 0xFFFF00FF ; FIO0PIN = 0x0000A500; Solution 2: using 16-bit (half-word) accessible fast GPIO registers FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Solution 3: using 8-bit (byte) accessible fast GPIO registers FIO0PIN1 = 0xA5; 6.2 Writing to FIOSET/FIOCLR vs. FIOPIN Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output pin(s) to both high and low levels at the same time. When FIOSET or FIOCLR are used, only pin/bit(s) written with 1 will be changed, while those written as 0 will remain unaffected. Writing to the FIOPIN register enables instantaneous output of a desired value on the parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs on that port: zeroes in the value will produce low level pin outputs and ones in the value will produce high level pin outputs. A subset of a port’s pins may be changed by using the FIOMASK register to define which pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that will be changed, and ones for all others. Solution 2 from Section 9–6.1 above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as they were before. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 138 of 835 UM10360 Chapter 10: LPC17xx Ethernet Rev. 01 — 4 January 2010 User manual 1. Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCENET. Remark: On reset, the Ethernet block is disabled (PCENET = 0). 2. Clock: see Table 4–38. 3. Pins: Enable Ethernet pins through the PINSEL registers and select their modes through the PINMODE registers, see Section 8–5. 4. Wake-up: Activity on the Ethernet port can wake up the microcontroller from Power-down mode, see Section 4–8.8. 5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 10–17.2. 2. Introduction The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU. The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix, it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum bandwidth to the Ethernet function. The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (Reduced Media Independent Interface) protocol and the on-chip MIIM (Media Independent Interface Management) serial bus, also referred to as MDIO (Management Data Input/Output). Table 123. Ethernet acronyms, abbreviations, and definitions Acronym or Abbreviation Definition AHB CRC DMA Double-word FCS Fragment Advanced High-performance bus Cyclic Redundancy Check Direct Memory Access 64-bit entity Frame Check Sequence (CRC) A (part of an) Ethernet frame; one or multiple fragments can add up to a single Ethernet frame. © NXP B.V. 2010. All rights reserved. UM10360_1 User manual Rev. 01 — 4 January 2010 139 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 123. Ethernet acronyms, abbreviations, and definitions Acronym or Abbreviation Definition Frame Half-word LAN MAC MII MIIM Octet Packet PHY RMII Rx TCP/IP Tx VLAN WoL Word An Ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. 16-bit entity Local Area Network Media Access Control sublayer Media Independent Interface MII management An 8-bit data entity, used in lieu of "byte" by IEEE 802.3 A frame that is transported across Ethernet; a packet consists of a preamble, a start of frame delimiter and an Ethernet frame. Ethernet Physical Layer Reduced MII Receive Transmission Control Protocol / Internet Protocol. The most common high-level protocol used with Ethernet. Transmit Virtual LAN Wake-up on LAN 32-bit entity 3. Features • Ethernet standards support: – Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – VLAN frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and prefetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic FCS insertion (CRC) for transmit. – Selectable automatic transmit frame padding. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 140 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through a standard Reduced MII (RMII) interface. – PHY register access is available via the Media Independent Interface Management (MIIM) interface. 4. Architecture and operation Figure 10–16 shows the internal architecture of the Ethernet block. BU S IN TER F ACE BUS IN T ERF AC E RMII DMA interface (AHB master) RECEIVE DMA RECEIVE BUFFER MIIM RECEIVE FILTER ETHERNET BLOCK Fig 16. Ethernet block diagram The block diagram for the Ethernet block consists of: • The host registers module containing the registers in the software view and handling AHB accesses to the Ethernet block. The host registers connect to the transmit and receive data path as well as the MAC. • The DMA to AHB interface. This provides an AHB master connection that allows the Ethernet block to access on-chip SRAM for reading of descriptors, writing of status, and reading and writing data buffers. • The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface. • The transmit data path, including: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 141 of 835 ET HE RN ET PHY TRANSMIT DMA TRANSMIT RETRY ETH ER N ET MAC R MII A DAP TER AH B BU S register interface (AHB slave) HOST REGISTERS TRANSMIT FLOW CONTROL NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet – The transmit DMA manager which reads descriptors and data from memory and writes status to memory. – The transmit retry module handling Ethernet retry and abort situations. – The transmit flow control module which can insert Ethernet pause frames. • The receive data path, including: – The receive DMA manager which reads descriptors from memory and writes data and status to memory. – The Ethernet MAC which detects frame types by parsing part of the frame header. – The receive filter which can filter out certain Ethernet frames by applying different filtering schemes. – The receive buffer implementing a delay for receive frames to allow the filter to filter out certain frames before storing them to memory. 5. DMA engine functions The Ethernet block is designed to provide optimized performance via DMA hardware acceleration. Independent scatter/gather DMA engines connected to the AHB bus off-load many data transfers from the CPU. Descriptors, which are stored in memory, contain information about fragments of incoming or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller amount of data. Each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be transmitted or received. Descriptors are stored in arrays in memory, which are located by pointer registers in the Ethernet block. Other registers determine the size of the arrays, point to the next descriptor in each array that will be used by the DMA engine, and point to the next descriptor in each array that will be used by the Ethernet device driver. 6. Overview of DMA operation The DMA engine makes use of a Receive descriptor array and a Transmit descriptor array in memory. All or part of an Ethernet frame may be contained in a memory buffer associated with a descriptor. When transmitting, the transmit DMA engine uses as many descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and sends them out in sequence. When receiving, the receive DMA engine also uses as many descriptors as needed (one or more) to find places to store (scatter) all of the data in the received frame. The base address registers for the descriptor array, registers indicating the number of descriptor array entries, and descriptor array input/output pointers are contained in the Ethernet block. The descriptor entries and all transmit and receive packet data are stored in memory which is not a part of the Ethernet block. The descriptor entries tell where related frame data is stored in memory, certain aspects of how the data is handled, and the result status of each Ethernet transaction. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 142 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer. The two pointers create a circular queue in the descriptor array and allow both the DMA hardware and the driver software to know which descriptors (if any) are available for their use, including whether the descriptor array is empty or full. Similarly, driver software must set up pointers to data that will be transmitted by the Ethernet MAC, giving instructions for each fragment of data, and advancing the software transmit pointer for outgoing data. Hardware in the DMA engine reads this information and sends the data to the Ethernet MAC interface when possible, updating the status and advancing the hardware transmit pointer. 7. Ethernet Packet Figure 10–17 illustrates the different fields in an Ethernet packet. ethernet packet PREAMBLE 7 bytes start-of-frame delimiter 1 byte ETHERNET FRAME DESTINATION ADDRESS SOURCE ADDRESS OPTIONAL VLAN LEN TYPE PAYLOAD FCS DesA oct6 DesA oct5 DesA oct4 DesA oct3 DesA oct2 DesA oct1 SrcA oct6 SrcA oct5 SrcA oct4 SrcA oct3 SrcA oct2 SrcA oct1 LSB oct(0) oct(1) oct(2) oct(3) oct(4) oct(5) oct(6) MSB oct(7) time Fig 17. Ethernet packet fields A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 143 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit. 8. Overview 8.1 Partitioning The Ethernet block and associated device driver software offer the functionality of the Media Access Control (MAC) sublayer of the data link layer in the OSI reference model (see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving frames to the next higher protocol level, the MAC client layer, typically the Logical Link Control sublayer. The device driver software implements the interface to the MAC client layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing to frames in memory and receives results back from the Ethernet block through interrupts. When a frame is transmitted, the software partially sets up the Ethernet frames by providing pointers to the destination address field, source address field, the length/type field, the MAC client data field and optionally the CRC in the frame check sequence field. Preferably concatenation of frame fields should be done by using the scatter/gather functionality of the Ethernet core to avoid unnecessary copying of data. The hardware adds the preamble and start frame delimiter fields and can optionally add the CRC, if requested by software. When a packet is received the hardware strips the preamble and start frame delimiter and passes the rest of the packet - the Ethernet frame - to the device driver, including destination address, source address, length/type field, MAC client data and frame check sequence (FCS). Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that control receive and transmit data streams between the MAC and the AHB interface. Frames are passed via descriptor arrays located in host memory, so that the hardware can process many frames without software/CPU support. Frames can consist of multiple fragments that are accessed with scatter/gather DMA. The DMA managers optimize memory bandwidth using prefetching and buffering. A receive filter block is used to identify received frames that are not addressed to this Ethernet station, so that they can be discarded. The Rx filters include a perfect address filter and a hash filter. Wake-on-LAN power management support makes it possible to wake the system up from a power-down state -a state in which some of the clocks are switched off -when wake-up frames are received over the LAN. Wake-up frames are recognized by the receive filtering modules or by a Magic Frame detection technology. System wake-up occurs by triggering an interrupt. An interrupt logic block raises and masks interrupts and keeps track of the cause of interrupts. The interrupt block sends an interrupt request signal to the host system. Interrupts can be enabled, cleared and set by software. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 144 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block. Receive flow control frames are automatically handled by the MAC. Transmit flow control frames can be initiated by software. In half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded. The Ethernet block has a standard Reduced Media Independent Interface (RMII) to connect to an external Ethernet PHY chip. Registers in the PHY chip are accessed via the AHB interface through the serial management connection of the MIIM bus, typically operating at 2.5 MHz. 8.2 Example PHY Devices Some examples of compatible PHY devices are shown in Table 10–124. Table 124. Example PHY Devices Manufacturer Part Number(s) Broadcom ICS Intel LSI Logic Micrel National SMSC BCM5221 ICS1893 LXT971A L80223, L80225, L80227 KS8721 DP83847, DP83846, DP83843 LAN83C185 9. Pin description Table 10–125 shows the signals used for connecting the Reduced Media Independent Interface (RMII) to the external PHY. Table 125. Ethernet RMII pin descriptions Pin Name Type Pin Description ENET_TX_EN ENET_TXD[1:0] ENET_RXD[1:0] ENET_RX_ER ENET_CRS ENET_REF_CLK/ ENET_RX_CLK Output Output Input Input Input Input Transmit data enable Transmit data, 2 bits Receive data, 2 bits. Receive error. Carrier sense/data valid. Reference clock Table 10–126 shows the signals used for Media Independent Interface Management (MIIM) of the external PHY. Table 126. Ethernet MIIM pin descriptions Pin Name Type Pin Description ENET_MDC ENET_MDIO Output Input/Output MIIM clock. MI data input and output UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 145 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 10. Registers and software interface The software interface of the Ethernet block consists of a register view and the format definitions for the transmit and receive descriptors. These two aspects are addressed in the next two subsections. 10.1 Register map Table 10–127 lists the registers, register addresses and other basic information. The total AHB address space required is 4 kilobytes. After a hard reset or a soft reset via the RegReset bit of the Command register all bits in all registers are reset to 0 unless stated otherwise in the following register descriptions. Some registers will have unused bits which will return a 0 on a read via the AHB interface. Writing to unused register bits of an otherwise writable register will not have side effects. The register map consists of registers in the Ethernet MAC and registers around the core for controlling DMA transfers, flow control and filtering. Reading from reserved addresses or reserved bits leads to unpredictable data. Writing to reserved addresses or reserved bits has no effect. Reading of write-only registers will return a read error on the AHB interface. Writing of read-only registers will return a write error on the AHB interface. Table 127. Ethernet register definitions Name MAC registers Description Access Reset Value Address MAC1 MAC2 IPGT IPGR CLRT MAXF SUPP TEST MCFG MCMD MADR MWTD MRDD MIND SA0 SA1 SA2 Control registers MAC configuration register 1. MAC configuration register 2. Back-to-Back Inter-Packet-Gap register. Non Back-to-Back Inter-Packet-Gap register. Collision window / Retry register. Maximum Frame register. PHY Support register. Test register. MII Mgmt Configuration register. MII Mgmt Command register. MII Mgmt Address register. MII Mgmt Write Data register. MII Mgmt Read Data register. MII Mgmt Indicators register. Station Address 0 register. Station Address 1 register. Station Address 2 register. Command register. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO RO RO R/W R/W R/W R/W 0x8000 0 0 0 0x370F 0x0600 0 0 0 0 0 0 0 0 0 0 0 0 0x5000 0000 0x5000 0004 0x5000 0008 0x5000 000C 0x5000 0010 0x5000 0014 0x5000 0018 0x5000 001C 0x5000 0020 0x5000 0024 0x5000 0028 0x5000 002C 0x5000 0030 0x5000 0034 0x5000 0040 0x5000 0044 0x5000 0048 0x5000 0100 Command UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 146 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 127. Ethernet register definitions Name Description Access Reset Value Address Status RxDescriptor RxStatus RxDescriptorNumber RxProduceIndex RxConsumeIndex TxDescriptor TxStatus TxDescriptorNumber TxProduceIndex TxConsumeIndex TSV0 TSV1 RSV FlowControlCounter FlowControlStatus Rx filter registers Status register. Receive descriptor base address register. Receive status base address register. Receive number of descriptors register. Receive produce index register. Receive consume index register. Transmit descriptor base address register. Transmit status base address register. Transmit number of descriptors register. Transmit produce index register. Transmit consume index register. Transmit status vector 0 register. Transmit status vector 1 register. Receive status vector register. Flow control counter register. Flow control status register. Receive filter control register. Receive filter WoL status register. Receive filter WoL clear register. Hash filter table LSBs register. Hash filter table MSBs register. Interrupt status register. Interrupt enable register. Interrupt clear register. Interrupt set register. Power-down register. RO R/W R/W R/W RO R/W R/W R/W R/W R/W RO RO RO RO R/W RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x5000 0104 0x5000 0108 0x5000 010C 0x5000 0110 0x5000 0114 0x5000 0118 0x5000 011C 0x5000 0120 0x5000 0124 0x5000 0128 0x5000 012C 0x5000 0158 0x5000 015C 0x5000 0160 0x5000 0170 0x5000 0174 0x5000 0200 0x5000 0204 0x5000 0208 0x5000 0210 0x5000 0214 0x5000 0FE0 0x5000 0FE4 0x5000 0FE8 0x5000 0FEC 0x5000 0FF4 RxFliterCtrl RxFilterWoLStatus RxFilterWoLClear HashFilterL HashFilterH IntStatus IntEnable IntClear IntSet PowerDown Module control registers RO R/W WO WO R/W 0 0 0 0 0 The third column in the table lists the accessibility of the register: read-only, write-only, read/write. All AHB register write transactions except for accesses to the interrupt registers are posted i.e. the AHB transaction will complete before write data is actually committed to the register. Accesses to the interrupt registers will only be completed by accepting the write data when the data has been committed to the register. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 147 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 11. Ethernet MAC register definitions This section defines the bits in the individual registers of the Ethernet block register map. 11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000) The MAC configuration register 1 (MAC1) has an address of 0x5000 0000. Its bit definition is shown in Table 10–128. Table 128. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description Bit Symbol Function Reset value 0 1 2 3 4 7:5 8 9 10 11 RECEIVE ENABLE PASS ALL RECEIVE FRAMES Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream. When enabled (set to ’1’), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames. 0 0 0 0 RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored. TX FLOW CONTROL LOOPBACK RESET TX RESET MCS / TX RESET RX RESET MCS / RX When enabled (set to ’1’), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked. Setting this bit will cause the MAC Transmit interface to be looped back to the MAC 0 Receive interface. Clearing this bit results in normal operation. Unused Setting this bit will put the Transmit Function logic in reset. Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control. Setting this bit will put the Ethernet receive logic in reset. Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control. Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 0 0 0 0x0 0x0 0 1 0x0 13:12 14 15 SIMULATION RESET Setting this bit will cause a reset to the random number generator within the Transmit Function. SOFT RESET Setting this bit will put all modules within the MAC in reset except the Host Interface. Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 31:16 - 11.2 MAC Configuration Register 2 (MAC2 - 0x5000 0004) The MAC configuration register 2 (MAC2) has an address of 0x5000 0004. Its bit definition is shown in Table 10–129. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 148 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 129. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description Bit Symbol Function Reset value 0 1 FULL-DUPLEX FRAME LENGTH CHECKING HUGE FRAME ENABLE DELAYED CRC When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. 0 When enabled (set to ’1’), both transmit and receive frame lengths are compared to 0 the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame. When enabled (set to ’1’), frames of any length are transmitted and received. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header. Set this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC. 0 0 2 3 4 CRC ENABLE 0 5 PAD / CRC ENABLE Set this bit to have the MAC pad all short frames. Clear this bit if frames presented 0 to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 10–131 - Pad Operation for details on the pad function. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid 0 CRC. Consult Table 10–131 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared. Set this bit to cause the MAC to automatically detect the type of frame, either tagged 0 or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 10–131 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared. When enabled (set to ’1’), the MAC will verify the content of the preamble to ensure 0 it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed. When enabled (set to ’1’), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard. Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. When enabled (set to ’1’), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard. 0 6 VLAN PAD ENABLE 7 AUTO DETECT PAD ENABLE 8 PURE PREAMBLE ENFORCEMENT LONG PREAMBLE ENFORCEMENT NO BACKOFF 9 11:10 12 0x0 0 13 BACK PRESSURE / NO BACKOFF EXCESS DEFER When enabled (set to ’1’), after the MAC incidentally causes a collision during back 0 pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached. Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 14 31:15 - 0x0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 149 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 130. Pad operation Type Auto detect VLAN pad pad enable enable MAC2 [7] MAC2 [6] Pad/CRC enable MAC2 [5] Action Any Any Any Any x 0 x 1 x 0 1 0 0 1 1 1 No pad or CRC check Pad to 60 bytes, append CRC Pad to 64 bytes, append CRC If untagged, pad to 60 bytes and append CRC. If VLAN tagged: pad to 64 bytes and append CRC. 11.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0x5000 0008) The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0x5000 0008. Its bit definition is shown in Table 10–131. Table 131. Back-to-back Inter-packet-gap register (IPGT - address 0x5000 0008) bit description Bit Symbol Function Reset value 6:0 BACK-TO-BACK INTER-PACKET-GAP This is a programmable field representing the nibble time offset of the minimum 0x0 possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in 10 Mbps mode). Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0x0 31:7 - 11.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0x5000 000C) The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of 0x5000 000C. Its bit definition is shown in Table 10–132. Table 132. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description Bit Symbol Function Reset value 6:0 NON-BACK-TO-BACK INTER-PACKET-GAP PART2 This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in 10 Mbps mode). 0x0 7 14:8 NON-BACK-TO-BACK INTER-PACKET-GAP PART1 Reserved. User software should not write ones to reserved bits. The value 0x0 read from a reserved bit is not defined. This is a programmable field representing the optional carrierSense 0x0 window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d) Reserved. User software should not write ones to reserved bits. The value 0x0 read from a reserved bit is not defined. © NXP B.V. 2010. All rights reserved. 31:15 - UM10360_1 User manual Rev. 01 — 4 January 2010 150 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 11.5 Collision Window / Retry Register (CLRT - 0x5000 0010) The Collision window / Retry register (CLRT) has an address of 0x5000 0010. Its bit definition is shown in Table 10–133. Table 133. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description Bit Symbol Function Reset value 3:0 RETRANSMISSION MAXIMUM COLLISION WINDOW - This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. 0xF 7:4 13:8 Reserved. User software should not write ones to reserved bits. The value read from 0x0 a reserved bit is not defined. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD. 0x37 31:14 Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. 11.6 Maximum Frame Register (MAXF - 0x5000 0014) The Maximum Frame register (MAXF) has an address of 0x5000 0014. Its bit definition is shown in Table 10–134. Table 134. Maximum Frame register (MAXF - address 0x5000 0014) bit description Bit Symbol Function Reset value 15:0 MAXIMUM FRAME This field resets to the value 0x0600, which represents a maximum receive frame of 0x0600 LENGTH 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field. Unused 0x0 31:16 11.7 PHY Support Register (SUPP - 0x5000 0018) The PHY Support register (SUPP) has an address of 0x5000 0018. The SUPP register provides additional control over the RMII interface. The bit definition of this register is shown in Table 10–135. Table 135. PHY Support register (SUPP - address 0x5000 0018) bit description Bit Symbol Function Reset value 7:0 8 31:9 SPEED - Unused 0x0 This bit configures the Reduced MII logic for the current operating speed. When set, 0 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. Unused 0x0 Unused bits in the PHY support register should be left as zeroes. 11.8 Test Register (TEST - 0x5000 001C) The Test register (TEST) has an address of 0x5000 001C. The bit definition of this register is shown in Table 10–136. These bits are used for testing purposes only. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 151 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 136. Test register (TEST - address 0x5000 ) bit description Bit Symbol Function Reset value 0 1 2 SHORTCUT PAUSE QUANTA TEST PAUSE TEST BACKPRESSURE - This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. 0 This bit causes the MAC Control sublayer to inhibit transmissions, just as if a 0 PAUSE Receive Control frame with a nonzero pause time parameter was received. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure 0 causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure. Unused 0x0 31:3 11.9 MII Mgmt Configuration Register (MCFG - 0x5000 0020) The MII Mgmt Configuration register (MCFG) has an address of 0x5000 0020. The bit definition of this register is shown in Table 10–137. Table 137. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description Bit Symbol Function Reset value 0 SCAN INCREMENT Set this bit to cause the MII Management hardware to perform read cycles across a 0 range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble. 0 1 SUPPRESS PREAMBLE CLOCK SELECT 5:2 This field is used by the clock divide logic in creating the MII Management Clock 0 (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 10–138 below for the definition of values for this field. Unused This bit resets the MII Management hardware. Unused 0x0 0 0x0 14:6 15 31:16 RESET MII MGMT - Table 138. Clock select encoding Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB clock supported Host Clock divided by 4 Host Clock divided by 6 Host Clock divided by 8 Host Clock divided by 10 Host Clock divided by 14 Host Clock divided by 20 Host Clock divided by 28 Host Clock divided by 36 Host Clock divided by 40 Host Clock divided by 44 UM10360_1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 x 0 1 0 1 0 1 0 1 0 10 15 20 25 35 50 70 80[1] 90[1] 100[1] © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 152 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 138. Clock select encoding Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB clock supported Host Clock divided by 48 Host Clock divided by 52 Host Clock divided by 56 Host Clock divided by 60 Host Clock divided by 64 [1] 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 120[1] 130[1] 140[1] 150[1] 160[1] The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device. 11.10 MII Mgmt Command Register (MCMD - 0x5000 0024) The MII Mgmt Command register (MCMD) has an address of 0x5000 0024. The bit definition of this register is shown in Table 10–139. Table 139. MII Mgmt Command register (MCMD - address 0x5000 0024) bit description Bit Symbol Function Reset value 0 1 31:2 READ SCAN - This bit causes the MII Management hardware to perform a single Read cycle. The Read data is 0 returned in Register MRDD (MII Mgmt Read Data). This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. Unused 0 0x0 11.11 MII Mgmt Address Register (MADR - 0x5000 0028) The MII Mgmt Address register (MADR) has an address of 0x5000 0028. The bit definition of this register is shown in Table 10–140. Table 140. MII Mgmt Address register (MADR - address 0x5000 0028) bit description Bit Symbol Function Reset value 4:0 7:5 12:8 31:13 REGISTER ADDRESS PHY ADDRESS - This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed. Unused This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved). Unused 0x0 0x0 0x0 0x0 11.12 MII Mgmt Write Data Register (MWTD - 0x5000 002C) The MII Mgmt Write Data register (MWTD) is a write-only register with an address of 0x5000 002C. The bit definition of this register is shown in Table 10–141. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 153 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 141. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description Bit Symbol Function Reset value 15:0 WRITE DATA - When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR). Unused 0x0 31:16 0x0 11.13 MII Mgmt Read Data Register (MRDD - 0x5000 0030) The MII Mgmt Read Data register (MRDD) is a read-only register with an address of 0x5000 0030. The bit definition of this register is shown in Table 10–142. Table 142. MII Mgmt Read Data register (MRDD - address 0x5000 0030) bit description Bit Symbol Function Reset value 15:0 31:16 READ DATA - Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location. Unused 0x0 0x0 11.14 MII Mgmt Indicators Register (MIND - 0x5000 0034) The MII Mgmt Indicators register (MIND) is a read-only register with an address of 0x5000 0034. The bit definition of this register is shown in Table 10–143. Table 143. MII Mgmt Indicators register (MIND - address 0x5000 0034) bit description Bit Symbol Function Reset value 0 1 2 3 31:4 BUSY When ’1’ is returned - indicates MII Mgmt is currently performing an 0 MII Mgmt Read or Write cycle. 0 0 0 0x0 SCANNING When ’1’ is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress. NOT VALID When ’1’ is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid. MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has occurred. Unused Here are two examples to access PHY via the MII Management Controller. For PHY Write if scan is not used: 1. Write 0 to MCMD 2. Write PHY address and register address to MADR 3. Write data to MWTD 4. Wait for busy bit to be cleared in MIND For PHY Read if scan is not used: 1. Write 1 to MCMD 2. Write PHY address and register address to MADR UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 154 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 3. Wait for busy bit to be cleared in MIND 4. Write 0 to MCMD 5. Read data from MRDD 11.15 Station Address 0 Register (SA0 - 0x5000 0040) The Station Address 0 register (SA0) has an address of 0x5000 0040. The bit definition of this register is shown in Table 10–144. Table 144. Station Address register (SA0 - address 0x5000 0040) bit description Bit Symbol Function Reset value 7:0 15:8 31:16 STATION ADDRESS, This field holds the second octet of the station address. 2nd octet STATION ADDRESS, This field holds the first octet of the station address. 1st octet Unused 0x0 0x0 0x0 The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 10–17. 11.16 Station Address 1 Register (SA1 - 0x5000 0044) The Station Address 1 register (SA1) has an address of 0x5000 0044. The bit definition of this register is shown in Table 10–145. Table 145. Station Address register (SA1 - address 0x5000 0044) bit description Bit Symbol Function Reset value 7:0 15:8 31:16 STATION ADDRESS, This field holds the fourth octet of the station address. 4th octet STATION ADDRESS, This field holds the third octet of the station address. 3rd octet Unused 0x0 0x0 0x0 The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 10–17. 11.17 Station Address 2 Register (SA2 - 0x5000 0048) The Station Address 2 register (SA2) has an address of 0x5000 0048. The bit definition of this register is shown in Table 10–146. Table 146. Station Address register (SA2 - address 0x5000 0048) bit description Bit Symbol Function Reset value 7:0 15:8 31:16 STATION ADDRESS, This field holds the sixth octet of the station address. 6th octet STATION ADDRESS, This field holds the fifth octet of the station address. 5th octet Unused 0x0 0x0 0x0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 155 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 10–17. 12. Control register definitions 12.1 Command Register (Command - 0x5000 0100) The Command register (Command) register has an address of 0x5000 0100. Its bit definition is shown in Table 10–147. Table 147. Command register (Command - address 0x5000 0100) bit description Bit Symbol Function Reset value 0 1 2 3 4 5 6 RxEnable TxEnable RegReset TxReset RxReset PassRuntFrame Enable receive. Enable transmit. Unused When a ’1’ is written, all datapaths and the host registers are reset. The MAC needs to be reset separately. When a ’1’ is written, the transmit datapath is reset. When a ’1’ is written, the receive datapath is reset. When set to ’1’, passes runt frames smaller than 64 bytes to memory unless they have a CRC error. If ’0’ runt frames are filtered out. When set to ’1’, disables receive filtering i.e. all frames received are written to memory. Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. 0 0 0x0 0 0 0 0 7 8 9 10 31:11 PassRxFilter TxFlowControl RMII FullDuplex - 0 0 When set to “1”, RMII mode is selected. This bit must be set to 0 one during Ethernet initialization. See Section 10–17.2. When set to “1”, indicates full duplex operation. Unused 0 0x0 All bits can be written and read. The Tx/RxReset bits are write-only, reading will return a 0. 12.2 Status Register (Status - 0x5000 0104) The Status register (Status) is a read-only register with an address of 0x5000 0104. Its bit definition is shown in Table 10–148. Table 148. Status register (Status - address 0x5000 0104) bit description Bit Symbol Function Reset value 0 1 31:2 RxStatus If 1, the receive channel is active. If 0, the receive channel is inactive. Unused 0 0x0 TxStatus If 1, the transmit channel is active. If 0, the transmit channel is inactive. 0 The values represent the status of the two channels/data paths. When the status is 1, the channel is active, meaning: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 156 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet • It is enabled and the Rx/TxEnable bit is set in the Command register or it just got disabled while still transmitting or receiving a frame. • Also, for the transmit channel, the transmit queue is not empty i.e. ProduceIndex != ConsumeIndex. • Also, for the receive channel, the receive queue is not full i.e. ProduceIndex != ConsumeIndex - 1. The status transitions from active to inactive if the channel is disabled by a software reset of the Rx/TxEnable bit in the Command register and the channel has committed the status and data of the current frame to memory. The status also transitions to inactive if the transmit queue is empty or if the receive queue is full and status and data have been committed to memory. 12.3 Receive Descriptor Base Address Register (RxDescriptor 0x5000 0108) The Receive Descriptor base address register (RxDescriptor) has an address of 0x5000 0108. Its bit definition is shown in Table 10–149. Table 149. Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108) bit description Bit Symbol Function Reset value 1:0 31:2 RxDescriptor Fixed to ’00’ MSBs of receive descriptor base address. 0x0 The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors. 12.4 Receive Status Base Address Register (RxStatus - 0x5000 010C) The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors. Table 150. receive Status Base Address register (RxStatus - address 0x5000 010C) bit description Bit Symbol Function Reset value 2:0 31:3 RxStatus Fixed to ’000’ MSBs of receive status base address. 0x0 The receive status base address is a byte address aligned to a double word boundary i.e. LSB 2:0 are fixed to “000”. 12.5 Receive Number of Descriptors Register (RxDescriptor - 0x5000 0110) The Receive Number of Descriptors register (RxDescriptorNumber) has an address of 0x5000 0110. Its bit definition is shown in Table 10–151. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 157 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 151. Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit description Bit Symbol Function Reset value 15:0 RxDescriptorNumber Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded. Unused 0x0 31:16 - 0x0 The receive number of descriptors register defines the number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 12.6 Receive Produce Index Register (RxProduceIndex - 0x5000 0114) The Receive Produce Index register (RxProduceIndex) is a read-only register with an address of 0x5000 0114. Its bit definition is shown in Table 10–152. Table 152. Receive Produce Index register (RxProduceIndex - address 0x5000 0114) bit description Bit Symbol Function Reset value 15:0 31:16 RxProduceIndex Index of the descriptor that is going to be filled next by the receive datapath. Unused 0x0 0x0 The receive produce index register defines the descriptor that is going to be filled next by the hardware receive process. After a frame has been received, hardware increments the index. The value is wrapped to 0 once the value of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 12.7 Receive Consume Index Register (RxConsumeIndex - 0x5000 0118) The Receive consume index register (RxConsumeIndex) has an address of 0x5000 0118. Its bit definition is shown in Table 10–153. Table 153. Receive Consume Index register (RxConsumeIndex - address 0x5000 0118) bit description Bit Symbol Function Reset value 15:0 31:16 RxConsumeIndex Index of the descriptor that is going to be processed next by the receive Unused 0x0 The receive consume register defines the descriptor that is going to be processed next by the software receive driver. The receive array is empty as long as RxProduceIndex equals RxConsumeIndex. As soon as the array is not empty, software can process the frame pointed to by RxConsumeIndex. After a frame has been processed by software, software should increment the RxConsumeIndex. The value must be wrapped to 0 once the value UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 158 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 12.8 Transmit Descriptor Base Address Register (TxDescriptor 0x5000 011C) The Transmit Descriptor base address register (TxDescriptor) has an address of 0x5000 011C. Its bit definition is shown in Table 10–154. Table 154. Transmit Descriptor Base Address register (TxDescriptor - address 0x5000 011C) bit description Bit Symbol Function Reset value 1:0 31:2 TxDescriptor Fixed to ’00’ MSBs of transmit descriptor base address. 0x0 The transmit descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors. 12.9 Transmit Status Base Address Register (TxStatus - 0x5000 0120) The Transmit Status base address register (TxStatus) has an address of 0x5000 0120. Its bit definition is shown in Table 10–155. Table 155. Transmit Status Base Address register (TxStatus - address 0x5000 0120) bit description Bit Symbol Function Reset value 1:0 31:2 TxStatus Fixed to ’00’ MSBs of transmit status base address. 0x0 The transmit status base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of statuses. 12.10 Transmit Number of Descriptors Register (TxDescriptorNumber 0x5000 0124) The Transmit Number of Descriptors register (TxDescriptorNumber) has an address of 0x5000 0124. Its bit definition is shown in Table 10–156. Table 156. Transmit Number of Descriptors register (TxDescriptorNumber - address 0x5000 0124) bit description Bit Symbol Function Reset value 15:0 TxDescriptorNumber Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded. Unused 0x0 31:16 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 159 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The transmit number of descriptors register defines the number of descriptors in the descriptor array for which TxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 12.11 Transmit Produce Index Register (TxProduceIndex - 0x5000 0128) The Transmit Produce Index register (TxProduceIndex) has an address of 0x5000 0128. Its bit definition is shown in Table 10–157. Table 157. Transmit Produce Index register (TxProduceIndex - address 0x5000 0128) bit description Bit Symbol Function Reset value 15:0 31:16 TxProduceIndex Index of the descriptor that is going to be filled next by the transmit software driver. Unused 0x0 0x0 The transmit produce index register defines the descriptor that is going to be filled next by the software transmit driver. The transmit descriptor array is empty as long as TxProduceIndex equals TxConsumeIndex. If the transmit hardware is enabled, it will start transmitting frames as soon as the descriptor array is not empty. After a frame has been processed by software, it should increment the TxProduceIndex. The value must be wrapped to 0 once the value of TxDescriptorNumber has been reached. If the TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software should stop producing new descriptors until hardware has transmitted some frames and updated the TxConsumeIndex. 12.12 Transmit Consume Index Register (TxConsumeIndex - 0x5000 012C) The Transmit Consume Index register (TxConsumeIndex) is a read-only register with an address of 0x5000 012C. Its bit definition is shown in Table 10–158. Table 158. Transmit Consume Index register (TxConsumeIndex - address 0x5000 012C) bit description Bit Symbol Function Reset value 15:0 31:16 TxConsumeIndex Index of the descriptor that is going to be transmitted next by the transmit datapath. Unused 0x0 0x0 The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors. 12.13 Transmit Status Vector 0 Register (TSV0 - 0x5000 0158) The Transmit Status Vector 0 register (TSV0) is a read-only register with an address of 0x5000 0158. The transmit status vector registers store the most recent transmit status returned by the MAC. Since the status vector consists of more than 4 bytes, status is UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 160 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet distributed over two registers TSV0 and TSV1. These registers are provided for debug purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. Table 10–159 lists the bit definitions of the TSV0 register. Table 159. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description Bit Symbol Function Reset value 0 1 2 3 4 5 6 7 8 9 10 11 27:12 28 29 30 31 [1] CRC error Length check error The attached CRC in the packet did not match the internally generated CRC. Indicates the frame length field does not match the actual number of data items and is not a type field. 0 0 0 0 0 0 Length out of range[1] Indicates that frame type/length field was larger than 1500 bytes. Done Multicast Broadcast Packet Defer Excessive Defer Excessive Collision Late Collision Giant Underrun Total bytes Control frame Pause Backpressure VLAN Transmission of packet was completed. Packet’s destination was a multicast address. Packet’s destination was a broadcast address. Packet was deferred for at least one attempt, but less than 0 an excessive defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode. 0 Packet was aborted due to exceeding of maximum allowed 0 number of collisions. Collision occurred beyond collision window, 512 bit times. Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. Host side caused buffer underrun. The total number of bytes transferred including collided attempts. The frame was a control frame. The frame was a control frame with a valid PAUSE opcode. Carrier-sense method backpressure was previously applied. Frame’s length/type field contained 0x8100 which is the VLAN protocol identifier. 0 0 0 0x0 0 0 0 0 The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 12.14 Transmit Status Vector 1 Register (TSV1 - 0x5000 015C) The Transmit Status Vector 1 register (TSV1) is a read-only register with an address of 0x5000 015C. The transmit status vector registers store the most recent transmit status returned by the MAC. Since the status vector consists of more than 4 bytes, status is distributed over two registers TSV0 and TSV1. These registers are provided for debug UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 161 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted.Table 10–160 lists the bit definitions of the TSV1 register. Table 160. Transmit Status Vector 1 register (TSV1 - address 0x5000 015C) bit description Bit Symbol Function Reset value 15:0 19:16 Transmit byte count Transmit collision count - The total number of bytes in the frame, not counting the collided bytes. 0x0 Number of collisions the current packet incurred during 0x0 transmission attempts. The maximum number of collisions (16) cannot be represented. Unused 0x0 31:20 12.15 Receive Status Vector Register (RSV - 0x5000 0160) The Receive status vector register (RSV) is a read-only register with an address of 0x5000 0160. The receive status vector register stores the most recent receive status returned by the MAC. This register is provided for debug purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. Table 10–161 lists the bit definitions of the RSV register. Table 161. Receive Status Vector register (RSV - address 0x5000 0160) bit description Bit Symbol Function Reset value 15:0 16 17 18 19 20 21 22 23 24 25 Received byte count Packet previously ignored RXDV event previously seen Carrier event previously seen Receive code violation CRC error Length check error Indicates length of received frame. Indicates that a packet was dropped. Indicates that the last receive event seen was not long enough to be a valid packet. 0x0 0 0 Indicates that at some time since the last receive statistics, 0 a carrier event was detected. Indicates that received PHY data does not represent a valid receive code. The attached CRC in the packet did not match the internally generated CRC. Indicates the frame length field does not match the actual number of data items and is not a type field. 0 0 0 0 0 0 0 Length out of range[1] Indicates that frame type/length field was larger than 1518 bytes. Receive OK Multicast Broadcast The packet had valid CRC and no symbol errors. The packet destination was a multicast address. The packet destination was a broadcast address. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 162 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 161. Receive Status Vector register (RSV - address 0x5000 0160) bit description Bit Symbol Function Reset value 26 Dribble Nibble Indicates that after the end of packet another 1-7 bits were 0 received. A single nibble, called dribble nibble, is formed but not sent out. The frame was a control frame. The frame was a control frame with a valid PAUSE opcode. 0 0 27 28 29 30 31 [1] Control frame PAUSE Unsupported Opcode The current frame was recognized as a Control Frame but 0 contains an unknown opcode. VLAN Frame’s length/type field contained 0x8100 which is the VLAN protocol identifier. Unused 0 0x0 The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 12.16 Flow Control Counter Register (FlowControlCounter - 0x5000 0170) The Flow Control Counter register (FlowControlCounter) has an address of 0x5000 0170. Table 10–162 lists the bit definitions of the register. Table 162. Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit description Bit Symbol Function Reset value 15:0 31:16 MirrorCounter PauseTimer In full duplex mode the MirrorCounter specifies the number 0x0 of cycles before re-issuing the Pause control frame. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles. 0x0 12.17 Flow Control Status Register (FlowControlStatus - 0x5000 0174) The Flow Control Status register (FlowControlStatus) is a read-only register with an address of 0x5000 8174. Table 10–163 lists the bit definitions of the register. Table 163. Flow Control Status register (FlowControlStatus - address 0x5000 8174) bit description Bit Symbol Function Reset value 15:0 MirrorCounterCurrent In full duplex mode this register represents the current 0x0 value of the datapath’s mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. Unused 0x0 31:16 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 163 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 13. Receive filter register definitions 13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200) The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200. Table 10–164 lists the definition of the individual bits in the register. Table 164. Receive Filter Control register (RxFilterCtrl - address 0x5000 0200) bit description Bit Symbol Function Reset value 0 1 2 3 4 5 AcceptUnicastEn AcceptBroadcastEn AcceptMulticastEn AcceptUnicastHashEn AcceptMulticastHashEn AcceptPerfectEn When set to ’1’, all unicast frames are accepted. When set to ’1’, all broadcast frames are accepted. When set to ’1’, all multicast frames are accepted. 0 0 0 When set to ’1’, unicast frames that pass the imperfect 0 hash filter are accepted. When set to ’1’, multicast frames that pass the imperfect hash filter are accepted. When set to ’1’, the frames with a destination address identical to the station address are accepted. 0 0 11:6 - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. When set to ’1’, the result of the magic packet filter will 0 generate a WoL interrupt when there is a match. When set to ’1’, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match. Unused 0 12 13 MagicPacketEnWoL RxFilterEnWoL 31:14 - 0x0 13.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0x5000 0204) The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a read-only register with an address of 0x5000 0204. Table 10–165 lists the definition of the individual bits in the register. Table 165. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit description Bit Symbol Function Reset value 0 1 2 3 4 5 AcceptUnicastWoL AcceptBroadcastWoL AcceptMulticastWoL AcceptUnicastHashWoL When the value is ’1’, a unicast frames caused WoL. When the value is ’1’, a broadcast frame caused WoL. When the value is ’1’, a multicast frame caused WoL. When the value is ’1’, a unicast frame that passes the imperfect hash filter caused WoL. 0 0 0 0 0 AcceptMulticastHashWoL When the value is ’1’, a multicast frame that passes the imperfect hash filter caused WoL. AcceptPerfectWoL When the value is ’1’, the perfect address matching filter 0 caused WoL. © NXP B.V. 2010. All rights reserved. UM10360_1 User manual Rev. 01 — 4 January 2010 164 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 165. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit description Bit Symbol Function Reset value 6 7 8 RxFilterWoL MagicPacketWoL Unused When the value is ’1’, the receive filter caused WoL. When the value is ’1’, the magic packet filter caused WoL. Unused 0x0 0 0 0x0 31:9 - The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be cleared by writing the RxFilterWoLClear register. 13.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0x5000 0208) The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear) is a write-only register with an address of 0x5000 0208. Table 10–166 lists the definition of the individual bits in the register. Table 166. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit description Bit Symbol Function Reset value 0 1 2 3 4 5 6 7 8 AcceptUnicastWoLClr AcceptBroadcastWoLClr AcceptMulticastWoLClr AcceptUnicastHashWoLClr AcceptMulticastHashWoLClr AcceptPerfectWoLClr RxFilterWoLClr MagicPacketWoLClr When a ’1’ is written to one of these bits (0 to 5), the corresponding status bit in the RxFilterWoLStatus register is cleared. 0 0 0 0 0 0 Unused 0x0 When a ’1’ is written to one of these bits (7 and/or 8), 0 the corresponding status bit in the RxFilterWoLStatus 0 register is cleared. Unused 0x0 31:9 - The bits in this register are write-only; writing resets the corresponding bits in the RxFilterWoLStatus register. 13.4 Hash Filter Table LSBs Register (HashFilterL - 0x5000 0210) The Hash Filter table LSBs register (HashFilterL) has an address of 0x5000 0210. Table 10–167 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10–17.10 “Receive filtering” on page 196. Table 167. Hash Filter Table LSBs register (HashFilterL - address 0x5000 0210) bit description Bit Symbol Function Reset value 31:0 HashFilterL Bits 31:0 of the imperfect filter hash table for receive filtering. 0x0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 165 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214) The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214. Table 10–168 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10–17.10 “Receive filtering” on page 196. Table 168. Hash Filter MSBs register (HashFilterH - address 0x5000 0214) bit description Bit Symbol Function Reset value 31:0 HashFilterH Bits 63:32 of the imperfect filter hash table for receive filtering. 0x0 14. Module control register definitions 14.1 Interrupt Status Register (IntStatus - 0x5000 0FE0) The Interrupt Status register (IntStatus) is a read-only register with an address of 0x5000 0FE0. The interrupt status register bit definition is shown in Table 10–169. Note that all bits are flip-flops with an asynchronous set in order to be able to generate interrupts if there are wake-up events while clocks are disabled. Table 169. Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description Bit Symbol Function Reset value 0 RxOverrunInt Interrupt set on a fatal overrun error in the receive queue. The 0 fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error. Interrupt trigger on receive errors: AlignmentError, RangeError, 0 LengthError, SymbolError, CRCError or NoDescriptor or Overrun. Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. 0 1 2 RxErrorInt RxFinishedInt 3 4 RxDoneInt Interrupt triggered when a receive descriptor has been processed 0 while the Interrupt bit in the Control field of the descriptor was set. TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The 0 fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error. TxErrorInt Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun. Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. Unused Interrupt triggered by software writing a 1 to the SoftintSet bit in the IntSet register. Interrupt triggered by a Wake-up event detected by the receive filter. Unused 0 5 6 TxFinishedInt 0 7 11:8 12 13 31:14 UM10360_1 TxDoneInt SoftInt WakeupInt - 0 0x0 0 0 0x0 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 166 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The interrupt status register is read-only. Setting can be done via the IntSet register. Reset can be accomplished via the IntClear register. 14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4) The Interrupt Enable register (IntEnable) has an address of 0x5000 0FE4. The interrupt enable register bit definition is shown in Table 10–170. Table 170. Interrupt Enable register (intEnable - address 0x5000 0FE4) bit description Bit Symbol Function Reset value 0 1 2 RxOverrunIntEn RxErrorIntEn RxFinishedIntEn Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. Enable for interrupt trigger on receive errors. 0 0 Enable for interrupt triggered when all receive descriptors have 0 been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. Enable for interrupt triggered when a receive descriptor has 0 been processed while the Interrupt bit in the Control field of the descriptor was set. 0 0 0 3 RxDoneIntEn 4 5 6 TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor underrun situations. TxErrorIntEn TxFinishedIntEn Enable for interrupt trigger on transmit errors. Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex. Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set. Unused Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register. Enable for interrupt triggered by a Wake-up event detected by the receive filter. Unused 7 TxDoneIntEn 0 11:8 12 SoftIntEn 0x0 0 13 31:14 WakeupIntEn - 0 0x0 14.3 Interrupt Clear Register (IntClear - 0x5000 0FE8) The Interrupt Clear register (IntClear) is a write-only register with an address of 0x5000 0FE8. The interrupt clear register bit definition is shown in Table 10–171. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 167 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 171. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description Bit Symbol Function Reset value 0 1 2 3 4 5 6 7 11:8 12 13 31:14 RxOverrunIntClr RxErrorIntClr RxFinishedIntClr RxDoneIntClr TxUnderrunIntClr TxErrorIntClr TxFinishedIntClr TxDoneIntClr SoftIntClr WakeupIntClr - Writing a ’1’ to one of these bits clears (0 to 7) the corresponding status bit in interrupt status register IntStatus. 0 0 0 0 0 0 0 0 Unused Writing a ’1’ to one of these bits (12 and/or 13) clears the corresponding status bit in interrupt status register IntStatus. Unused 0x0 0 0 0x0 The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears the corresponding bit in the status register. Writing a 0 will not affect the interrupt status. 14.4 Interrupt Set Register (IntSet - 0x5000 0FEC) The Interrupt Set register (IntSet) is a write-only register with an address of 0x5000 0FEC. The interrupt set register bit definition is shown in Table 10–172. Table 172. Interrupt Set register (IntSet - address 0x5000 0FEC) bit description Bit Symbol Function Reset value 0 1 2 3 4 5 6 7 11:8 12 13 31:14 RxOverrunIntSet RxErrorIntSet RxFinishedIntSet RxDoneIntSet TxUnderrunIntSet TxErrorIntSet TxFinishedIntSet TxDoneIntSet SoftIntSet WakeupIntSet - Writing a ’1’ to one of these bits (0 to 7) sets the corresponding status bit in interrupt status register IntStatus. 0 0 0 0 0 0 0 0 Unused Writing a ’1’ to one of these bits (12 and/or 13) sets the corresponding status bit in interrupt status register IntStatus. Unused 0x0 0 0 0x0 The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the corresponding bit in the status register. Writing a 0 will not affect the interrupt status. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 168 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 14.5 Power-Down Register (PowerDown - 0x5000 0FF4) The Power-Down register (PowerDown) is used to block all AHB accesses except accesses to the Power-Down register. The register has an address of 0x5000 0FF4. The bit definition of the register is listed in Table 10–173. Table 173. Power-Down register (PowerDown - address 0x5000 0FF4) bit description Bit Symbol Function Reset value 30:0 31 PowerDownMACAHB Unused If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register. 0x0 0 Setting the bit will return an error on all read and write accesses on the MACAHB interface except for accesses to the Power-Down register. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 169 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 15. Descriptor and status formats This section defines the descriptor format for the transmit and receive scatter/gather DMA engines. Each Ethernet frame can consist of one or more fragments. Each fragment corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for receive) and gather (for transmit) multiple fragments for a single Ethernet frame. 15.1 Receive descriptors and statuses Figure 10–18 depicts the layout of the receive descriptors in memory. RxDescriptor RxStatus 1 PACKET CONTROL DATA BUFFER StatusInfo StatusHashCRC 2 PACKET CONTROL DATA BUFFER StatusInfo StatusHashCRC 3 PACKET CONTROL DATA BUFFER StatusInfo StatusHashCRC 4 PACKET CONTROL DATA BUFFER StatusInfo StatusHashCRC 5 PACKET CONTROL DATA BUFFER StatusInfo StatusHashCRC RxDescriptorNumber PACKET CONTROL DATA BUFFER StatusInfo StatusHashCRC Fig 18. Receive descriptor memory layout Receive descriptors are stored in an array in memory. The base address of the array is stored in the RxDescriptor register, and should be aligned on a 4 byte address boundary. The number of descriptors in the array is stored in the RxDescriptorNumber register using a minus one encoding style e.g. if the array has 8 elements the register value should be 7. Parallel to the descriptors there is an array of statuses. For each element of the descriptor array there is an associated status field in the status array. The base address of the status array is stored in the RxStatus register, and must be aligned on an 8 byte address boundary. During operation (when the receive data path is enabled) the RxDescriptor, RxStatus and RxDescriptorNumber registers should not be modified. Two registers, RxConsumeIndex and RxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both registers act as counters starting at 0 and wrapping when they reach the value of RxDescriptorNumber. The RxProduceIndex contains the index of the descriptor that is going to be filled with the next frame being UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 170 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet received. The RxConsumeIndex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. When RxProduceIndex == RxConsumeIndex, the receive buffer is empty. When RxProduceIndex == RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly received data would generate an overflow unless the software driver frees up one or more descriptors. Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes two words (8 bytes) in memory. Each receive descriptor consists of a pointer to the data buffer for storing receive data (Packet) and a control word (Control). The Packet field has a zero address offset, the control field has a 4 byte address offset with respect to the descriptor address as defined in Table 10–174. Table 174. Receive Descriptor Fields Symbol Address Bytes Description offset Packet Control 0x0 0x4 4 4 Base address of the data buffer for storing receive data. Control information, see Table 10–175. The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. The definition of the control word bits is listed in Table 10–175. Table 175. Receive Descriptor Control Word Bit Symbol Description 10:0 Size Size in bytes of the data buffer. This is the size of the buffer reserved by the device driver for a frame or frame fragment i.e. the byte size of the buffer pointed to by the Packet field. The size is -1 encoded e.g. if the buffer is 8 bytes the size field should be equal to 7. Unused If true generate an RxDone interrupt when the data in this frame or frame fragment and the associated status information has been committed to memory. 30:11 31 Interrupt Table 10–176 lists the fields in the receive status elements from the status array. Table 176. Receive Status Fields Symbol Address Bytes Description offset StatusInfo 0x0 4 4 Receive status return flags, see Table 10–178. The concatenation of the destination address hash CRC and the source address hash CRC. StatusHashCRC 0x4 Each receive status consists of two words. The StatusHashCRC word contains a concatenation of the two 9-bit hash CRCs calculated from the destination and source addresses contained in the received frame. After detecting the destination and source addresses, StatusHashCRC is calculated once, then held for every fragment of the same frame. The concatenation of the two CRCs is shown in Table 10–177: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 171 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Table 177. Receive Status HashCRC Word Bit Symbol Description 8:0 15:9 SAHashCRC Hash CRC calculated from the source address. Unused Unused 24:16 DAHashCRC Hash CRC calculated from the destination address. 31:25 - The StatusInfo word contains flags returned by the MAC and flags generated by the receive data path reflecting the status of the reception. Table 10–178 lists the bit definitions in the StatusInfo word. Table 178. Receive status information word Bit Symbol Description 10:0 RxSize The size in bytes of the actual data transferred into one fragment buffer. In other words, this is the size of the frame or fragment as actually written by the DMA manager for one descriptor. This may be different from the Size bits of the Control field in the descriptor that indicate the size of the buffer allocated by the device driver. Size is -1 encoded e.g. if the buffer has 8 bytes the RxSize value will be 7. Unused Indicates this is a control frame for flow control, either a pause frame or a frame with an unsupported opcode. Indicates a VLAN frame. Indicates this frame has failed the Rx filter. These frames will not normally pass to memory. But due to the limitation of the size of the buffer, part of this frame may already be passed to memory. Once the frame is found to have failed the Rx filter, the remainder of the frame will be discarded without being passed to the memory. However, if the PassRxFilter bit in the Command register is set, the whole frame will be passed to memory. Set when a multicast frame is received. Set when a broadcast frame is received. The received frame had a CRC error. The PHY reports a bit error over the PHY interface during reception. The frame length field value in the frame specifies a valid length, but does not match the actual data length. The received packet exceeds the maximum packet size. 17:11 18 19 20 ControlFrame VLAN FailFilter 21 22 23 24 25 26 27 Multicast Broadcast CRCError SymbolError LengthError RangeError[1] AlignmentError An alignment error is flagged when dribble bits are detected and also a CRC error is detected. This is in accordance with IEEE std. 802.3/clause 4.3.2. Overrun NoDescriptor LastFlag Error Receive overrun. The adapter can not accept the data stream. No new Rx descriptor is available and the frame is too long for the buffer size in the current receive descriptor. When set to 1, indicates this descriptor is for the last fragment of a frame. If the frame consists of a single fragment, this bit is also set to 1. An error occurred during reception of this frame. This is a logical OR of AlignmentError, RangeError, LengthError, SymbolError, CRCError, and Overrun. 28 29 30 31 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 172 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. For multi-fragment frames, the value of the AlignmentError, RangeError, LengthError, SymbolError and CRCError bits in all but the last fragment in the frame will be 0; likewise the value of the FailFilter, Multicast, Broadcast, VLAN and ControlFrame bits is undefined. The status of the last fragment in the frame will copy the value for these bits from the MAC. All fragment statuses will have valid LastFrag, RxSize, Error, Overrun and NoDescriptor bits. 15.2 Transmit descriptors and statuses Figure 10–19 depicts the layout of the transmit descriptors in memory. TxDescriptor TxStatus 1 PACKET CONTROL DATA BUFFER StatusInfo 2 PACKET CONTROL DATA BUFFER StatusInfo 3 PACKET CONTROL DATA BUFFER StatusInfo 4 PACKET CONTROL DATA BUFFER StatusInfo 5 PACKET CONTROL DATA BUFFER StatusInfo TxDescriptorNumber PACKET CONTROL DATA BUFFER StatusInfo Fig 19. Transmit descriptor memory layout Transmit descriptors are stored in an array in memory. The lowest address of the transmit descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte address boundary. The number of descriptors in the array is stored in the TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8 elements the register value should be 7. Parallel to the descriptors there is an array of statuses. For each element of the descriptor array there is an associated status field in the status array. The base address of the status array is stored in the TxStatus register, and must be aligned on a 4 byte address boundary. During operation (when the transmit data path is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers should not be modified. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 173 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both register act as counters starting at 0 and wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex contains the index of the next descriptor that is going to be filled by the software driver. The TxConsumeIndex contains the index of the next descriptor going to be transmitted by the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty. When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), the transmit buffer is full and the software driver cannot add new descriptors until the hardware has transmitted one or more frames to free up descriptors. Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a pointer to the data buffer containing transmit data (Packet) and a control word (Control). The Packet field has a zero address offset, whereas the control field has a 4 byte address offset, see Table 10–179. Table 179. Transmit descriptor fields Symbol Address offset Bytes Description Packet Control 0x0 0x4 4 4 Base address of the data buffer containing transmit data. Control information, see Table 10–180. The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. The definition of the control word bits is listed in Table 10–180. Table 180. Transmit descriptor control word Bit Symbol Description 10:0 Size Size in bytes of the data buffer. This is the size of the frame or fragment as it needs to be fetched by the DMA manager. In most cases it will be equal to the byte size of the data buffer pointed to by the Packet field of the descriptor. Size is -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7. Unused Per frame override. If true, bits 30:27 will override the defaults from the MAC internal registers. If false, bits 30:27 will be ignored and the default values from the MAC will be used. If true, enables huge frame, allowing unlimited frame sizes. When false, prevents transmission of more than the maximum frame length (MAXF[15:0]). If true, pad short frames to 64 bytes. If true, append a hardware CRC to the frame. If true, indicates that this is the descriptor for the last fragment in the transmit frame. If false, the fragment from the next descriptor should be appended. If true, a TxDone interrupt will be generated when the data in this frame or frame fragment has been sent and the associated status information has been committed to memory. 25:11 26 Override 27 28 29 30 31 Huge Pad CRC Last Interrupt Table 10–181 shows the one field transmit status. Table 181. Transmit status fields Symbol Address offset Bytes Description StatusInfo 0x0 4 Transmit status return flags, see Table 10–182. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 174 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The transmit status consists of one word which is the StatusInfo word. It contains flags returned by the MAC and flags generated by the transmit data path reflecting the status of the transmission. Table 10–182 lists the bit definitions in the StatusInfo word. Table 182. Transmit status information word Bit Symbol Description 20:0 - Unused The number of collisions this packet incurred, up to the Retransmission Maximum. This packet incurred deferral, because the medium was occupied. This is not an error unless excessive deferral occurs. This packet incurred deferral beyond the maximum deferral limit and was aborted. 24:21 CollisionCount 25 26 27 28 29 30 31 Defer ExcessiveDefer ExcessiveCollision Indicates this packet exceeded the maximum collision limit and was aborted. LateCollision Underrun NoDescriptor Error An Out of window Collision was seen, causing packet abort. A Tx underrun occurred due to the adapter not producing transmit data. The transmit stream was interrupted because a descriptor was not available. An error occurred during transmission. This is a logical OR of Underrun, LateCollision, ExcessiveCollision, and ExcessiveDefer. For multi-fragment frames, the value of the LateCollision, ExcessiveCollision, ExcessiveDefer, Defer and CollissionCount bits in all but the last fragment in the frame will be 0. The status of the last fragment in the frame will copy the value for these bits from the MAC. All fragment statuses will have valid Error, NoDescriptor and Underrun bits. 16. Ethernet block functional description This section defines the functions of the DMA capable 10/100 Ethernet MAC. After introducing the DMA concepts of the Ethernet block, and a description of the basic transmit and receive functions, this section elaborates on advanced features such as flow control, receive filtering, etc. 16.1 Overview The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet PHY connected through the RMII interface. Typically during system start-up, the Ethernet block will be initialized. Software initialization of the Ethernet block should include initialization of the descriptor and status arrays as well as the receiver fragment buffers. Remark: when initializing the Ethernet block, it is important to first configure the PHY and insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins and connected to the EMAC module (selecting the appropriate pins using the PINSEL registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become locked and no further functionality will be possible. This will cause JTAG lose communication with the target, if debug mode is being used. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 175 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet To transmit a packet the software driver has to set up the appropriate Control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementing the TxProduceIndex register. After transmission, hardware will increment TxConsumeIndex and optionally generate an interrupt. The hardware will receive packets from the PHY and apply filtering as configured by the software driver. While receiving a packet the hardware will read a descriptor from memory to find the location of the associated receiver data buffer. Receive data is written in the data buffer and receive status is returned in the receive descriptor status word. Optionally an interrupt can be generated to notify software that a packet has been received. Note that the DMA manager will prefetch and buffer up to three descriptors. 16.2 AHB interface The registers of the Ethernet block connect to an AHB slave interface to allow access to the registers from the CPU. The AHB interface has a 32-bit data path, which supports only word accesses and has an address aperture of 4 kB. Table 10–127 lists the registers of the Ethernet block. All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear and IntEnable registers. AHB write operations are executed in order. If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses will return a read or write error except for accesses to the PowerDown register. Bus Errors The Ethernet block generates errors for several conditions: • The AHB interface will return a read error when there is an AHB read access to a write-only register; likewise a write error is returned when there is an AHB write access to the read-only register. An AHB read or write error will be returned on AHB read or write accesses to reserved registers. These errors are propagated back to the CPU. Registers defined as read-only and write-only are identified in Table 10–127. • If the PowerDown bit is set all accesses to AHB registers will result in an error response except for accesses to the PowerDown register. 17. Interrupts The Ethernet block has a single interrupt request output to the CPU (via the NVIC). The interrupt service routine must read the IntStatus register to determine the origin of the interrupt. All interrupt statuses can be set by software writing to the IntSet register; statuses can be cleared by software writing to the IntClear register. The transmit and receive data paths can only set interrupt statuses, they cannot clear statuses. The SoftInt interrupt cannot be set by hardware and can be used by software for test purposes. 17.1 Direct Memory Access (DMA) Descriptor arrays UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 176 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The Ethernet block includes two DMA managers. The DMA managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame. The DMA managers work with arrays of frame descriptors and statuses that are stored in memory. The descriptors and statuses act as an interface between the Ethernet hardware and the device driver software. There is one descriptor array for receive frames and one descriptor array for transmit frames. Using buffering for frame descriptors, the memory traffic and memory bandwidth utilization of descriptors can be kept small. Each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer containing a frame or a fragment, whereas the second field is a control word related to that frame or fragment. The software driver must write the base addresses of the descriptor and status arrays in the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number of descriptors/statuses in each array must be written in the TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in an array corresponds to the number of statuses in the associated status array. Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be aligned on a 4 byte (32bit)address boundary, while the receive status array must be aligned on a 8 byte (64bit) address boundary. Ownership of descriptors Both device driver software and Ethernet hardware can read and write the descriptor arrays at the same time in order to produce and consume descriptors. A descriptor is "owned" either by the device driver or by the Ethernet hardware. Only the owner of a descriptor reads or writes its value. Typically, the sequence of use and ownership of descriptors and statuses is as follows: a descriptor is owned and set up by the device driver; ownership of the descriptor/status is passed by the device driver to the Ethernet block, which reads the descriptor and writes information to the status field; the Ethernet block passes ownership of the descriptor back to the device driver, which uses the status information and then recycles the descriptor to be used for another frame. Software must pre-allocate the memory used to hold the descriptor arrays. Software can hand over ownership of descriptors and statuses to the hardware by incrementing (and wrapping if on the array boundary) the TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors and status to software by updating the TxConsumeIndex/ RxProduceIndex registers. After handing over a descriptor to the receive and transmit DMA hardware, device driver software should not modify the descriptor or reclaim the descriptor by decrementing the TxProduceIndex/ RxConsumeIndex registers because descriptors may have been prefetched by the hardware. In this case the device driver software will have to wait until the frame has been transmitted or the device driver has to soft-reset the transmit and/or receive data paths which will also reset the descriptor arrays. Sequential order with wrap-around When descriptors are read from and statuses are written to the arrays, this is done in sequential order with wrap-around. Sequential order means that when the Ethernet block has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 177 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet the one at the next higher, adjacent memory address. Wrap around means that when the Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. Full and Empty state of descriptor arrays The descriptor arrays can be empty, partially full or full. A descriptor array is empty when all descriptors are owned by the producer. A descriptor array is partially full if both producer and consumer own part of the descriptors and both are busy processing those descriptors. A descriptor array is full when all descriptors (except one) are owned by the consumer, so that the producer has no more room to process frames. Ownership of descriptors is indicated with the use of a consume index and a produce index. The produce index is the first element of the array owned by the producer. It is also the index of the array element that is next going to be used by the producer of frames (it may already be busy using it and subsequent elements). The consume index is the first element of the array that is owned by the consumer. It is also the number of the array element next to be consumed by the consumer of frames (it and subsequent elements may already be in the process of being consumed). If the consume index and the produce index are equal, the descriptor array is empty and all array elements are owned by the producer. If the consume index equals the produce index plus one, then the array is full and all array elements (except the one at the produce index) are owned by the consumer. With a full descriptor array, still one array element is kept empty, to be able to easily distinguish the full or empty state by looking at the value of the produce index and consume index. An array must have at least 2 elements to be able to indicate a full descriptor array with a produce index of value 0 and a consume index of value 1. The wrap around of the arrays is taken into account when determining if a descriptor array is full, so a produce index that indicates the last element in the array and a consume index that indicates the first element in the array, also means the descriptor array is full. When the produce index and the consume index are unequal and the consume index is not the produce index plus one (with wrap around taken into account), then the descriptor array is partially full and both the consumer and producer own enough descriptors to be able to operate actively on the descriptor array. Interrupt bit The descriptors have an Interrupt bit, which is programmed by software. When the Ethernet block is processing a descriptor and finds this bit set, it will allow triggering an interrupt (after committing status to memory) by passing the RxDoneInt or TxDoneInt bits in the IntStatus register to the interrupt output pin. If the Interrupt bit is not set in the descriptor, then the RxDoneInt or TxDoneInt are not set and no interrupt is triggered (note that the corresponding bits in IntEnable must also be set to trigger interrupts). This offers flexible ways of managing the descriptor arrays. For instance, the device driver could add 10 frames to the Tx descriptor array, and set the Interrupt bit in descriptor number 5 in the descriptor array. This would invoke the interrupt service routine before the transmit descriptor array is completely exhausted. The device driver could add another batch of frames to the descriptor array, without interrupting continuous transmission of frames. Frame fragments For maximum flexibility in frame storage, frames can be split up into multiple frame fragments with fragments located in different places in memory. In this case one descriptor is used for each frame fragment. So, a descriptor can point to a single frame or UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 178 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. By stringing together fragments it is possible to create large frames from small memory areas. Another use of fragments is to be able to locate a frame header and frame payload in different places and to concatenate them without copy operations in the device driver. For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor is a new Ethernet frame. 17.2 Initialization After reset, the Ethernet software driver needs to initialize the Ethernet block. During initialization the software needs to: • Remove the soft reset condition from the MAC • Configure the PHY via the MIIM interface of the MAC. Remark: it is important to configure the PHY and insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins and connected to the EMAC module (selecting the appropriate pins using the PINSEL registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become locked and no further functionality will be possible. This will cause JTAG lose communication with the target, if debug mode is being used. • • • • Select RMII mode Configure the transmit and receive DMA engines, including the descriptor arrays Configure the host registers (MAC1,MAC2 etc.) in the MAC Enable the receive and transmit data paths Depending on the PHY, the software needs to initialize registers in the PHY via the MII Management interface. The software can read and write PHY registers by programming the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the MWTD register; read data and status information can be read from the MRDD and MIND registers. The Ethernet block supports RMII PHYs. During initialization software must select RMII mode by programming the Command register. Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be de-asserted. The phy_ref_clk must be running and internally connected during this operation. Transmit and receive DMA engines should be initialized by the device driver by allocating the descriptor and status arrays in memory. Transmit and receive functions have their own dedicated descriptor and status arrays. The base addresses of these arrays need to be programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The number of descriptors in an array matches the number of statuses in an array. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 179 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Please note that the transmit descriptors, receive descriptors and receive statuses are 8 bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit statuses need to be aligned on 4 byte boundaries; receive status arrays need to be aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor array has 4 descriptors the value of the number of descriptors register should be 3. After setting up the descriptor arrays, frame buffers need to be allocated for the receive descriptors before enabling the receive data path. The Packet field of the receive descriptors needs to be filled with the base address of the frame buffer of that descriptor. Amongst others the Control field in the receive descriptor needs to contain the size of the data buffer using -1 encoding. The receive data path has a configurable filtering function for discarding/ignoring specific Ethernet frames. The filtering function should also be configured during initialization. After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The soft reset condition must be removed before the Ethernet block can be enabled. Enabling of the receive function is located in two places. The receive DMA manager needs to be enabled and the receive data path of the MAC needs to be enabled. To prevent overflow in the receive DMA engine the receive DMA engine should be enabled by setting the RxEnable bit in the Command register before enabling the receive data path in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register. The transmit DMA engine can be enabled at any time by setting the TxEnable bit in the Command register. Before enabling the data paths, several options can be programmed in the MAC, such as automatic flow control, transmit to receive loop-back for verification, full/half duplex modes, etc. Base addresses of descriptor arrays and descriptor array sizes cannot be modified without a (soft) reset of the receive and transmit data paths. 17.3 Transmit process Overview This section outlines the transmission process. Device driver sets up descriptors and data If the descriptor array is full the device driver should wait for the descriptor arrays to become not full before writing to a descriptor in the descriptor array. If the descriptor array is not full, the device driver should use the descriptor numbered TxProduceIndex of the array pointed to by TxDescriptor. The Packet pointer in the descriptor is set to point to a data frame or frame fragment to be transmitted. The Size field in the Command field of the descriptor should be set to the number of bytes in the fragment buffer, -1 encoded. Additional control information can be indicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad). UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 180 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet After writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrapping) the TxProduceIndex register. If the transmit data path is disabled, the device driver should not forget to enable the transmit data path by setting the TxEnable bit in the Command register. When there is a multi-fragment transmission for fragments other than the last, the Last bit in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To trigger an interrupt when the frame has been transmitted and transmission status has been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have the hardware add a CRC in the frame sequence control field of this Ethernet frame, set the CRC bit in the descriptor. This should be done if the CRC has not already been added by software. To enable automatic padding of small frames to the minimum required frame size, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits CRC and Pad are both set to 1. The device driver can set up interrupts using the IntEnable register to wait for a signal of completion from the hardware or can periodically inspect (poll) the progress of transmission. It can also add new frames at the end of the descriptor array, while hardware consumes descriptors at the start of the array. The device driver can stop the transmit process by resetting the TxEnable bit in the Command register to 0. The transmission will not stop immediately; frames already being transmitted will be transmitted completely and the status will be committed to memory before deactivating the data path. The status of the transmit data path can be monitored by the device driver reading the TxStatus bit in the Status register. As soon as the transmit data path is enabled and the corresponding TxConsumeIndex and TxProduceIndex are not equal i.e. the hardware still needs to process frames from the descriptor array, the TxStatus bit in the Status register will return to 1 (active). Tx DMA manager reads the Tx descriptor array When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at the address determined by TxDescriptor and TxConsumeIndex. The number of descriptors requested is determined by the total number of descriptors owned by the hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes memory loading. Read data returned from memory is buffered and consumed as needed. Tx DMA manager transmits data After reading the descriptor the transmit DMA engine reads the associated frame data from memory and transmits the frame. After transfer completion, the Tx DMA manager writes status information back to the StatusInfo and StatusHashCRC words of the status field. The value of the TxConsumeIndex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The Tx DMA manager continues to transmit frames until the descriptor array is empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the TxFinishedInt bit of the IntStatus register. The transmit data path will still be enabled. The Tx DMA manager inspects the Last bit of the descriptor Control field when loading the descriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments. The Tx DMA manager gathers all the fragments from the host memory, visiting a string of UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 181 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection. When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1, this indicates the last fragment of the frame and thus the end of the frame is found. Update ConsumeIndex Each time the Tx DMA manager commits a status word to memory it completes the transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around into account) to hand the descriptor back to the device driver software. Software can re-use the descriptor for new transmissions after hardware has handed it back. The device driver software can keep track of the progress of the DMA manager by reading the TxConsumeIndex register to see how far along the transmit process is. When the Tx descriptor array is emptied completely, the TxConsumeIndex register retains its last value. Write transmission status After the frame has been transmitted over the RMII bus, the StatusInfo word of the frame descriptor is updated by the DMA manager. If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame transmission, error flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set in the status. The CollisionCount field is set to the number of collisions the frame incurred, up to the Retransmission Maximum programmed in the Collision window/retry register of the MAC. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. Even if the descriptor is for a frame fragment other than the last fragment, the error flags are returned via the AHB interface. If the Ethernet block detects a transmission error during transmission of a (multi-fragment) frame, all remaining fragments of the frame are still read via the AHB interface. After an error, the remaining transmit data is discarded by the Ethernet block. If there are errors during transmission of a multi-fragment frame the error statuses will be repeated until the last fragment of the frame. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. These may include error information if the error is detected early enough. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection. Thus, the status for the last fragment will always reflect any error that occurred anywhere in the frame. The status of the last frame transmission can also be inspected by reading the TSV0 and TSV1 registers. These registers do not report statuses on a fragment basis and do not store information of previously sent frames. They are provided primarily for debug purposes, because the communication between driver software and the Ethernet block takes place through the frame descriptors. The status registers are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. Transmission error handling If an error occurs during the transmit process, the Tx DMA manager will report the error via the transmission StatusInfo word written in the Status array and the IntStatus interrupt status register. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 182 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The transmission can generate several types of errors: LateCollision, ExcessiveCollision, ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the transmission StatusInfo word. In addition to the separate bits in the StatusInfo word, LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer, or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus register. Underrun errors can have three causes: • The next fragment in a multi-fragment transmission is not available. This is a nonfatal error. A NoDescriptor status will be returned on the previous fragment and the TxError bit in IntStatus will be set. • The transmission fragment data is not available when the Ethernet block has already started sending the frame. This is a nonfatal error. An Underrun status will be returned on transfer and the TxError bit in IntStatus will be set. • The flow of transmission statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. This is a fatal error which can only be resolved by a soft reset of the hardware. The first and second situations are nonfatal and the device driver has to re-send the frame or have upper software layers re-send the frame. In the third case the hardware is in an undefined state and needs to be soft reset by setting the TxReset bit in the Command register. After reporting a LateCollision, ExcessiveCollision, ExcessiveDefer or Underrun error, the transmission of the erroneous frame will be aborted, remaining transmission data and frame fragments will be discarded and transmission will continue with the next frame in the descriptor array. Device drivers should catch the transmission errors and take action. Transmit triggers interrupts The transmit data path can generate four different interrupt types: • If the Interrupt bit in the descriptor Control field is set, the Tx DMA will set the TxDoneInt bit in the IntStatus register after sending the fragment and committing the associated transmission status to memory. Even if a descriptor (fragment) is not the last in a multi-fragment frame the Interrupt bit in the descriptor can be used to generate an interrupt. • If the descriptor array is empty while the Ethernet hardware is enabled the hardware will set the TxFinishedInt bit of the IntStatus register. • If the AHB interface does not consume the transmission statuses at a sufficiently high bandwidth the transmission may underrun in which case the TxUnderrun bit will be set in the IntStatus register. This is a fatal error which requires a soft reset of the transmission queue. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 183 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet • In the case of a transmission error (LateCollision, ExcessiveCollision, or ExcessiveDefer) or a multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus register. All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the NVIC). The interrupts, either of individual frames or of the whole list, are a good means of communication between the DMA manager and the device driver, triggering the device driver to inspect the status words of descriptors that have been processed. Transmit example Figure 10–20 illustrates the transmit process in an example transmitting uses a frame header of 8 bytes and a frame payload of 12 bytes. TxDescriptor 0x200810EC 0x2008131B 0x20081314 TxStatus 0x200811F8 status 0 0x200810EC PACKET 0 HEADER (8 bytes) descriptor 0 0x2008141C 0x20081411 0x20081419 Packet 0x20081314 0x200811F8 StatusInfo 0x200810F0 status 1 PACKET 0 PAYLOAD (12 bytes) descriptor 1 Packet 0x20081411 status 2 0x200810F4 StatusInfo 0x20081200 descriptor array 0 0 CONTROL 7 Control status 3 0x200810F8 StatusInfo 0x20081204 descriptor 2 0x20081100 1 1 CONTROL 3 Control 0x2008132B 0x20081324 0x200810FC Packet 0x20081419 TxProduceIndex TxConsumeIndex TxDescriptorNumber =3 PACKET 1 HEADER (8 bytes) 0x20081104 descriptor 3 Packet 0x20081324 0x20081108 0 0 CONTROL 7 Control descriptor array fragment buffers status array Fig 20. Transmit example memory and registers After reset the values of the DMA registers will be zero. During initialization the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 184 of 835 status array 0 0 CONTROL 7 Control StatusInfo 0x200811FC NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet boundary. Since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) to the TxDescriptor register and the base address of the status array (0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized, yet. At this point, the transmit data path may be enabled by setting the TxEnable bit in the Command register. If the transmit data path is enabled while there are no further frames to send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load only the desired interrupts can be enabled by setting the relevant bits in the IntEnable register. Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will add a header to the frame. The frame header need not be immediately in front of the payload data in memory. The device driver can program the Tx DMA to collect header and payload data. To do so, the device driver will program the first descriptor to point at the frame header; the Last flag in the descriptor will be set to false/0 to indicate a multi-fragment transmission. The device driver will program the next descriptor to point at the actual payload data. The maximum size of a payload buffer is 2 kB so a single descriptor suffices to describe the payload buffer. For the sake of the example though the payload is distributed across two descriptors. After the first descriptor in the array describing the header, the second descriptor in the array describes the initial 8 bytes of the payload; the third descriptor in the array describes the remaining 4 bytes of the frame. In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set in the last fragment of the frame in order to trigger an interrupt after the transmission completed. The Size field in the descriptor’s Control word is set to the number of bytes in the fragment buffer, -1 encoded. Note that in real device drivers, the payload will typically only be split across multiple descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to the hardware without the device driver copying it (zero copy device driver). After setting up the descriptors for the transaction the device driver increments the TxProduceIndex register by 3 since three descriptors have been programmed. If the transmit data path was not enabled during initialization the device driver needs to enable the data path now. If the transmit data path is enabled the Ethernet block will start transmitting the frame as soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero after reset. The Tx DMA will start reading the descriptors from memory. The memory system will return the descriptors and the Ethernet block will accept them one by one while reading the transmit data fragments. As soon as transmission read data is returned from memory, the Ethernet block will try to start transmission on the Ethernet connection via the RMII interface. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 185 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet After transmitting each fragment of the frame the Tx DMA will write the status of the fragment’s transmission. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection. Since the Interrupt bit in the descriptor of the last fragment is set, after committing the status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt, which triggers the device driver to inspect the status information. In this example the device driver cannot add new descriptors as long as the Ethernet block has not incremented the TxConsumeIndex because the descriptor array is full (even though one descriptor is not programmed yet). Only after the hardware commits the status for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager can the device driver program the next (the fourth) descriptor. The fourth descriptor can already be programmed before completely transmitting the first frame. In this example the hardware adds the CRC to the frame. If the device driver software adds the CRC, the CRC trailer can be considered another frame fragment which can be added by doing another gather DMA. Each data byte is transmitted across the RMII interface as four 2-bit values. The Ethernet block adds the preamble, frame delimiter leader, and the CRC trailer if hardware CRC is enabled. Once transmission on the RMII interface commences the transmission cannot be interrupted without generating an underrun error, which is why descriptors and data read commands are issued as soon as possible and pipelined. Using an RMII PHY, the data communication between the Ethernet block and the PHY is communicated at 50 MHz. In 10 Mbps mode data will only be transmitted once every 10 clock cycles. 17.4 Receive process This section outlines the receive process including the activities in the device driver software. Device driver sets up descriptors After initializing the receive descriptor and status arrays to receive frames from the Ethernet connection, the receive data path should be enabled in the MAC1 register and the Control register. During initialization, each Packet pointer in the descriptors is set to point to a data fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt bit allows generation of an interrupt after a fragment buffer has been filled and its status has been committed to memory. After the initialization and enabling of the receive data path, all descriptors are owned by the receive hardware and should not be modified by the software unless hardware hands over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been received. The device driver is allowed to modify the descriptors after a (soft) reset of the receive data path. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 186 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Rx DMA manager reads Rx descriptor arrays When the RxEnable bit in the Command register is set, the Rx DMA manager reads the descriptors from memory at the address determined by RxDescriptor and RxProduceIndex. The Ethernet block will start reading descriptors even before actual receive data arrives on the RMII interface (descriptor prefetching). The block size of the descriptors to be read is determined by the total number of descriptors owned by the hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors minimizes memory load. Read data returned from memory is buffered and consumed as needed. RX DMA manager receives data After reading the descriptor, the receive DMA engine waits for the MAC to return receive data from the RMII interface that passes the receive filter. Receive frames that do not match the filtering criteria are not passed to memory. Once a frame passes the receive filter, the data is written in the fragment buffer associated with the descriptor. The Rx DMA does not write beyond the size of the buffer. When a frame is received that is larger than a descriptor’s fragment buffer, the frame will be written to multiple fragment buffers of consecutive descriptors. In the case of a multi-fragment reception, all but the last fragment in the frame will return a status where the LastFrag bit is set to 0. Only on the last fragment of a frame the LastFrag bit in the status will be set to 1. If a fragment buffer is the last of a frame, the buffer may not be filled completely. The first receive data of the next frame will be written to the fragment buffer of the next descriptor. After receiving a fragment, the Rx DMA manager writes status information back to the StatusInfo and StatusHashCRC words of the status. The Ethernet block writes the size in bytes of a descriptor’s fragment buffer in the RxSize field of the Status word. The value of the RxProduceIndex is only updated after the fragment data and the fragment status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The Rx DMA manager continues to receive frames until the descriptor array is full. If the descriptor array is full, the Ethernet hardware will set the RxFinishedInt bit of the IntStatus register. The receive data path will still be enabled. If the receive descriptor array is full any new receive data will generate an overflow error and interrupt. Update ProduceIndex Each time the Rx DMA manager commits a data fragment and the associated status word to memory, it completes the reception of a descriptor and increments the RxProduceIndex (taking wrap around into account) in order to hand the descriptor back to the device driver software. Software can re-use the descriptor for new receptions by handing it back to hardware when the receive data has been processed. The device driver software can keep track of the progress of the DMA manager by reading the RxProduceIndex register to see how far along the receive process is. When the Rx descriptor array is emptied completely, the RxProduceIndex retains its last value. Write reception status After the frame has been received from the RMII bus, the StatusInfo and StatusHashCRC words of the frame descriptor are updated by the DMA manager. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 187 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually written to the fragment buffer, -1 encoded. For fragments not being the last in the frame the RxSize will match the size of the buffer. The hash CRCs of the destination and source addresses of a packet are calculated once for all the fragments belonging to the same packet and then stored in every StatusHashCRC word of the statuses associated with the corresponding fragments. If the reception reports an error, any remaining data in the receive frame is discarded and the LastFrag bit will be set in the receive status field, so the error flags in all but the last fragment of a frame will always be 0. The status of the last received frame can also be inspected by reading the RSV register. The register does not report statuses on a fragment basis and does not store information of previously received frames. RSV is provided primarily for debug purposes, because the communication between driver software and the Ethernet block takes place through the frame descriptors. Reception error handling When an error occurs during the receive process, the Rx DMA manager will report the error via the receive StatusInfo written in the Status array and the IntStatus interrupt status register. The receive process can generate several types of errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError, Overrun, and NoDescriptor. All have corresponding bits in the receive StatusInfo. In addition to the separate bits in the StatusInfo, AlignmentError, RangeError, LengthError, SymbolError, and CRCError are ORed together into the Error bit of the StatusInfo. Errors are also propagated to the IntStatus register; the RxError bit in the IntStatus register is set if there is an AlignmentError, RangeError, LengthError, SymbolError, CRCError, or NoDescriptor error; nonfatal overrun errors are reported in the RxError bit of the IntStatus register; fatal Overrun errors are report in the RxOverrun bit of the IntStatus register. On fatal overrun errors, the Rx data path needs to be soft reset by setting the RxReset bit in the Command register. Overrun errors can have three causes: • In the case of a multi-fragment reception, the next descriptor may be missing. In this case the NoDescriptor field is set in the status word of the previous descriptor and the RxError in the IntStatus register is set. This error is nonfatal. • The data flow on the receiver data interface stalls, corrupting the packet. In this case the overrun bit in the status word is set and the RxError bit in the IntStatus register is set. This error is nonfatal. • The flow of reception statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. This error will corrupt the hardware state and requires the hardware to be soft reset. The error is detected and sets the Overrun bit in the IntStatus register. The first overrun situation will result in an incomplete frame with a NoDescriptor status and the RxError bit in IntStatus set. Software should discard the partially received frame. In the second overrun situation the frame data will be corrupt which results in the Overrun status bit being set in the Status word while the IntError interrupt bit is set. In the third case UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 188 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet receive errors cannot be reported in the receiver Status arrays which corrupts the hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The RxReset bit in the Command register should be used to soft reset the hardware. Device drivers should catch the above receive errors and take action. Receive triggers interrupts The receive data path can generate four different interrupt types: • If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the RxDoneInt bit in the IntStatus register after receiving a fragment and committing the associated data and status to memory. Even if a descriptor (fragment) is not the last in a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an interrupt. • If the descriptor array is full while the Ethernet hardware is enabled, the hardware will set the RxFinishedInt bit of the IntStatus register. • If the AHB interface does not consume receive statuses at a sufficiently high bandwidth, the receive status process may overrun, in which case the RxOverrun bit will be set in the IntStatus register. • If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or CRCError), or a multi-fragment frame where the device driver did provide descriptors for the initial fragments but did not provide the descriptors for the rest of the fragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt bit of the IntStatus register. All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the NVIC). The interrupts, either of individual frames or of the whole list, are a good means of communication between the DMA manager and the device driver, triggering the device driver to inspect the status words of descriptors that have been processed. Device driver processes receive data As a response to status (e.g. RxDoneInt) interrupts or polling of the RxProduceIndex, the device driver can read the descriptors that have been handed over to it by the hardware (RxProduceIndex - RxConsumeIndex). The device driver should inspect the status words in the status array to check for multi-fragment receptions and receive errors. The device driver can forward receive data and status to upper software layers. After processing of data and status, the descriptors, statuses and data buffers may be recycled and handed back to hardware by incrementing the RxConsumeIndex. Receive example Figure 10–21 illustrates the receive process in an example receiving a frame of 19 bytes. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 189 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 0x20081409 RxDescriptor 0x200810EC 0x20081410 RxStatus 0x200811F8 Status 0 0x200810EC FRAGMENT 0 BUFFER bytes) (8 Descriptor 0 0x20081411 0x20081418 StatusInfo 7 0x200811F8 PACKET 0x20081409 StatusHashCRC StatusInfo 7 0x20081200 0x200810F0 1 CONTROL 7 Status 1 StatusHashCRC StatusInfo 2 0x20081208 FRAGMENT 1 BUFFER bytes) (8 Descriptor 1 0x200810F4 0x2008141B 0x20081419 PACKET 0x20081411 Status 2 StatusHashCRC StatusInfo 7 0x20081210 descriptor array Status 3 0x200810F8 1 CONTROL 7 FRAGMENT 2 BUFFER bytes) (3 Descriptor 2 0x20081325 0x2008132C StatusHashCRC 0x200810FC PACKET 0x20081419 0x20081100 1 CONTROL 7 FRAGMENT 3 BUFFER bytes) (8 0x20081104 Descriptor 3 PACKET 0x20081325 RxProduceIndex RxConsumeIndex RxDescriptorNumber= 3 fragment buffers status array 0x20081108 1 CONTROL 7 descriptor array Fig 21. Receive Example Memory and Registers After reset, the values of the DMA registers will be zero. During initialization, the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. Since the number of descriptors matches the number of statuses, the status array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) in the RxDescriptor register, and the base address of the status array (0x2008 11F8) in the RxStatus register. The device driver writes the number of descriptors and statuses minus 1 (3) in the RxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized yet. After allocating the descriptors, a fragment buffer needs to be allocated for each of the descriptors. Each fragment buffer can be between 1 byte and 2 k bytes. The base address of the fragment buffer is stored in the Packet field of the descriptors. The number of bytes in the fragment buffer is stored in the Size field of the descriptor Control word. The Interrupt field in the Control word of the descriptor can be set to generate an interrupt as soon as the descriptor has been filled by the receive process. In this example the fragment buffers are 8 bytes, so the value of the Size field in the Control word of the descriptor is set to 7. Note that in this example, the fragment buffers are actually a UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 190 of 835 status array NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space. The device driver should enable the receive process by writing a 1 to the RxEnable bit of the Command register, after which the MAC needs to be enabled by writing a 1 to the ‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts can be disabled by setting the relevant bits in the IntEnable register. After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In this example the number of descriptors is 4. Initially the RxProduceIndex and RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex == RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex RxProduceIndex - 1 =) 3 descriptors; note the wrapping. After enabling the receive function in the MAC, data reception will begin starting at the next frame i.e. if the receive function is enabled while the RMII interface is halfway through receiving a frame, the frame will be discarded and reception will start at the next frame. The Ethernet block will strip the preamble and start of frame delimiter from the frame. If the frame passes the receive filtering, the Rx DMA manager will start writing the frame to the first fragment buffer. Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, the frame will be distributed over three fragment buffers. After writing the initial 8 bytes in the first fragment buffer, the status for the first fragment buffer will be written and the Rx DMA will continue filling the second fragment buffer. Since this is a multi-fragment receive, the status of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; the RxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second fragment the Rx DMA will continue writing the third fragment. The status of the second fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing the three bytes in the third fragment buffer, the end of the frame has been reached and the status of the third fragment is written. The third fragment’s status will have the LastFrag bit set to 1 and the RxSize equal to 2 (3, -1 encoded). The next frame received from the RMII interface will be written to the fourth fragment buffer i.e. five bytes of the third buffer will be unused. The Rx DMA manager uses an internal tag protocol in the memory interface to check that the receive data and status have been committed to memory. After the status of the fragments are committed to memory, an RxDoneInt interrupt will be triggered, which activates the device driver to inspect the status information. In this example, all descriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate an interrupt after committing data and status to memory. In this example the receive function cannot read new descriptors as long as the device driver does not increment the RxConsumeIndex, because the descriptor array is full (even though one descriptor is not programmed yet). Only after the device driver has forwarded the receive data to application software, and after the device driver has updated the RxConsumeIndex by incrementing it, will the Ethernet block can continue reading descriptors and receive data. The device driver will probably increment the RxConsumeIndex by 3, since the driver will forward the complete frame consisting of three fragments to the application, and hence free up three descriptors at the same time. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 191 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Each four pairs of bits transferred on the RMII interface are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the buffer NoDescriptor error probability, three descriptors are buffered. The value of the RxProduceIndex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The software device driver will process the receive data, after which the device driver will update the RxConsumeIndex. 17.5 Transmission retry If a collision on the Ethernet occurs, it usually takes place during the collision window spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that this data can be used during the retry. A transmission retry within the first 64 bytes in a frame is fully transparent to the application and device driver software. When a collision occurs outside of the 64 byte collision window, a LateCollision error is triggered, and the transmission is aborted. After a LateCollision error, the remaining data in the transmit frame will be discarded. The Ethernet block will set the Error and LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the IntStatus register will be propagated to the CPU (via the NVIC). The device driver software should catch the interrupt and take appropriate actions. The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure the maximum number of retries before aborting the transmission. 17.6 Status hash CRC calculations For each received frame, the Ethernet block is able to detect the destination address and source address and from them calculate the corresponding hash CRCs. To perform the computation, the Ethernet block features two internal blocks: one is a controller synchronized with the beginning and the end of each frame, the second block is the CRC calculator. When a new frame is detected, internal signaling notifies the controller.The controller starts counting the incoming bytes of the frame, which correspond to the destination address bytes. When the sixth (and last) byte is counted, the controller notifies the calculator to store the corresponding 32-bit CRC into a first inner register. Then the controller repeats counting the next incoming bytes, in order to get synchronized with the source address. When the last byte of the source address is encountered, the controller again notifies the CRC calculator, which freezes until the next new frame. When the calculator receives this second notification, it stores the present 32-bit CRC into a second inner register. Then the CRCs remain frozen in their own registers until new notifications arise. The destination address and source address hash CRCs being written in the StatusHashCRC word are the nine most significant bits of the 32-bit CRCs as calculated by the CRC calculator. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 192 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 17.7 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. For a full duplex connection the FullDuplex bit of the Command register needs to be set to 1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for half duplex the same bits need to be set to 0. 17.8 IEE 802.3/Clause 31 flow control Overview For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control using pause frames. This type of flow control may be used in full-duplex point-to-point connections. Flow control allows a receiver to stall a transmitter e.g. when the receive buffers are (almost) full. For this purpose, the receiving side sends a pause frame to the transmitting side. Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles. Receive flow control In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives a pause frame. Rx flow control is initiated by the receiving side of the transmission. It is enabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control frames. When a pause frame is received on the Rx side of the Ethernet block, transmission on the Tx side will be interrupted after the currently transmitting frame has completed, for an amount of time as indicated in the received pause frame. The transmit data path will stop transmitting data for the number of 512 bit slot times encoded in the pause-timer field of the received pause control frame. By default the received pause control frames are not forwarded to the device driver. To forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE FRAMES’ bit in the MAC1 configuration register. Transmit flow control If case device drivers need to stall the receive data e.g. because software buffers are full, the Ethernet block can transmit pause control frames. Transmit flow control needs to be initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated by hardware, such as the DMA managers. With software flow control, the device driver can detect a situation in which the process of receiving frames needs to be interrupted by sending out Tx pause frames. Note that due to Ethernet delays, a few frames can still be received before the flow control takes effect and the receive stream stops. Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command register. When the Ethernet block operates in full duplex mode, this will result in transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is written to TxFlowControl bit of the Command register. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 193 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission. The value inserted into the pause-timer value field of transmitted pause frames is programmed via the PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. When flow control be in force for an extended time, a sequence of pause frames must be transmitted. This is supported with a mirror counter mechanism. To enable mirror counting, a nonzero value is written to the MirrorCounter[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is transmitted. After sending the pause frame, an internal mirror counter is initialized to zero. The internal mirror counter starts incrementing one every 512 bit-slot times. When the internal mirror counter reaches the MirrorCounter value, another pause frame is transmitted with pause-timer value equal to the PauseTimer field from the FlowControlCounter register, the internal mirror counter is reset to zero and restarts counting. The register MirrorCounter[15:0] is usually set to a smaller value than register PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send a new pause frame before the transmission on the other side can resume. By continuing to send pause frames before the transmitting side finishes counting the pause timer, the pause can be extended as long as TxFlowControl is asserted. This continues until TxFlowControl is de-asserted when a final pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. To disable the mirror counter mechanism, write the value 0 to MirrorCounter field in the FlowControlCounter register. When using the mirror counter mechanism, account for time-of-flight delays, frame transmission time, queuing delays, crystal frequency tolerances, and response time delays by programming the MirrorCounter conservatively, typically about 80% of the PauseTimer value. If the software device driver sets the MirrorCounter field of the FlowControlCounter register to zero, the Ethernet block will only send one pause control frame. After sending the pause frame an internal pause counter is initialized at zero; the internal pause counter is incremented by one every 512 bit-slot times. Once the internal pause counter reaches the value of the PauseTimer register, the TxFlowControl bit in the Command register will be reset. The software device driver can poll the TxFlowControl bit to detect when the pause completes. The value of the internal counter in the flow control module can be read out via the FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register will return the value of the internal mirror counter; if the MirrorCounter is zero the FlowControlStatus register will return the value of the internal pause counter value. The device driver is allowed to dynamically modify the MirrorCounter register value and switch between zero MirrorCounter and nonzero MirrorCounter modes. Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1 configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not transmit pause control frames, software must not initiate pause frame transmissions, and the TxFlowControl bit in the Command register should be zero. Transmit flow control example Figure 10–22 illustrates the transmit flow control. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 194 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet device driver PauseTimer register MirrorCounter TxFlowCtl writes RMII transmit MirrorCounter (1/515 bit slots) RMII receive normal receive normal transmission pause control frame transmission clear TxFlowCtl normal transimisson pause control frame transmission pause control frame transmission pause in effect normal receive 0 50 100 150 200 250 300 350 400 450 500 Fig 22. Transmit Flow Control In this example, a frame is received while transmitting another frame (full duplex.) The device driver detects that some buffer might overrun and enables the transmit flow control by programming the PauseTimer and MirrorCounter fields of the FlowControlCounter register, after which it enables the transmit flow control by setting the TxFlowControl bit in the Command register. As a response to the enabling of the flow control a pause control frame will be sent after the currently transmitting frame has been transmitted. When the pause frame transmission completes the internal mirror counter will start counting bit slots; as soon as the counter reaches the value in the MirrorCounter field another pause frame is transmitted. While counting the transmit data path will continue normal transmissions. As soon as software disables transmit flow control a zero pause control frame is transmitted to resume the receive process. 17.9 Half-Duplex mode backpressure When in half-duplex mode, backpressure can be generated to stall receive packets by sending continuous preamble that basically jams any other transmissions on the Ethernet medium. When the Ethernet block operates in half duplex mode, asserting the TxFlowControl bit in the Command register will result in applying continuous preamble on the Ethernet wire, effectively blocking traffic from any other Ethernet station on the same segment. In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent until TxFlowControl is de-asserted. If the medium is idle, the Ethernet block begins transmitting preamble, which raises carrier sense causing all other stations to defer. In the event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the collision. The colliding station backs off and then defers to the backpressure. If during backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame sent and then the backpressure resumed. If TxFlowControl is asserted for longer than 3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending preamble for several byte times to avoid the jabber limit. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 195 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 17.10 Receive filtering Features of receive filtering The Ethernet MAC has several receive packet filtering functions that can be configured from the software driver: • Perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver. • Hash table filter: allows imperfect filtering of packets based on the station address. • Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or broadcast packets. • Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt. The filtering functions can be logically combined to create complex filtering functions. Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; a promiscuous mode allows all packets to be passed to software. Overview The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet destination address in the frame. This capability greatly reduces the load on the host system, because Ethernet frames that are addressed to other stations would otherwise need to be inspected and rejected by the device driver software, using up bandwidth, memory space, and host CPU time. Address filtering can be implemented using the perfect address filter or the (imperfect) hash filter. The latter produces a 6-bit hash code which can be used as an index into a 64 entry programmable hash table. Figure 10–23 depicts a functional view of the receive filter. At the top of the diagram the Ethernet receive frame enters the filters. Each filter is controlled by signals from control registers; each filter produces a ‘Ready’ output and a ‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering then it will assert its Ready output; if the filter finds a matching frame it will assert the Match output along with the Ready output. The results of the filters are combined by logic functions into a single RxAbort output. If the RxAbort output is asserted, the frame does not need to be received. In order to reduce memory traffic, the receive data path has a buffer of 68 bytes. The Ethernet MAC will only start writing a frame to memory after 68 byte delays. If the RxAbort signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and removed from the buffer and not stored to memory at all, not using up receive descriptors, etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due to reception of a Magic Packet), part of the frame is already written to memory and the Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the status word of the frame will be set to indicate that the software device driver can discard the frame immediately. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 196 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet packet AcceptUnicastEn AcceptMulticastEn AcceptMulticastHashEn IMPERFECT HASH FILTER AcceptUnicastHashEn HashFilter H FMatc h PAReady HFReady PAMatch StationAddress AcceptPerfectEn PERFECT ADDRESS FILTER CRC OK? FMatch RxFilterWoL RxFilterEnWoL FReady RxAbort Fig 23. Receive filter block diagram Unicast, broadcast and multicast Generic filtering based on the type of frame (unicast, multicast or broadcast) can be programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits of the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, and AcceptBroadcast bits causes all frames of types unicast, multicast and broadcast, respectively, to be accepted, ignoring the Ethernet destination address in the frame. To program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1. Perfect address match When a frame with a unicast destination address is received, a perfect filter compares the destination address with the 6 byte station address programmed in the station address registers SA0, SA1, SA2. If the AcceptPerfectEn bit in the RxFilterCtrl register is set to 1, and the address matches, the frame is accepted. Imperfect hash filtering An imperfect filter is available, based on a hash mechanism. This filter applies a hash function to the destination address and uses the hash to access a table that indicates if the frame should be accepted. The advantage of this type of filter is that a small table can cover any possible address. The disadvantage is that the filtering is imperfect, i.e. sometimes frames are accepted that should have been discarded. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 197 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet • Hash function: – The standard Ethernet cyclic redundancy check (CRC) function is calculated from the 6 byte destination address in the Ethernet frame (this CRC is calculated anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of the 32-bit CRC result are taken to form the hash. The 6-bit hash is used to access the hash table: it is used as an index in the 64-bit HashFilter register that has been programmed with accept values. If the selected accept value is 1, the frame is accepted. – The device driver can initialize the hash filter table by writing to the registers HashFilterL and HashfilterH. HashFilterL contains bits 0 through 31 of the table and HashFilterH contains bit 32 through 63 of the table. So, hash value 0 corresponds to bit 0 of the HashfilterL register and hash value 63 corresponds to bit 31 of the HashFilterH register. • Multicast and unicast – The imperfect hash filter can be applied to multicast addresses, by setting the AcceptMulticastHashEn bit in the RxFilter register to 1. – The same imperfect hash filter that is available for multicast addresses can also be used for unicast addresses. This is useful to be able to respond to a multitude of unicast addresses without enabling all unicast addresses. The hash filter can be applied to unicast addresses by setting the AcceptUnicastHashEn bit in the RxFilter register to 1. Enabling and disabling filtering The filters as defined in the sections above can be bypassed by setting the PassRxFilter bit in the Command register. When the PassRxFilter bit is set, all receive frames will be passed to memory. In this case the device driver software has to implement all filtering functionality in software. Setting the PassRxFilter bit does not affect the runt frame filtering as defined in the next section. Runt frames A frame with less than 64 bytes (or 68 bytes for VLAN frames) is shorter than the minimum Ethernet frame size and therefore considered erroneous; they might be collision fragments. The receive data path automatically filters and discards these runt frames without writing them to memory and using a receive descriptor. When a runt frame has a correct CRC there is a possibility that it is intended to be useful. The device driver can receive the runt frames with correct CRC by setting the PassRuntFrame bit of the Command register to 1. 17.11 Power management The Ethernet block supports power management by means of clock switching. All clocks in the Ethernet core can be switched off. If Wake-up on LAN is needed, the rx_clk should not be switched off. 17.12 Wake-up on LAN Overview UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 198 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state. Wake-up of the system takes effect through an interrupt. When a wake-up event is detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This interrupt should be used by system power management logic to wake up the system. While in a power-down state the packet that generates a Wake-up on LAN event is lost. There are two ways in which Ethernet packets can trigger wake-up events: generic Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if the triggering packet has a valid CRC. Figure 10–23 shows the generation of the wake-up signal. The RxFilterWoLStatus register can be read by the software to inspect the reason for a Wake-up event. Before going to power-down the power management software should clear the register by writing the RxFilterWolClear register. NOTE: when entering in power-down mode, a receive frame might be not entirely stored into the Rx buffer. In this situation, after turning exiting power-down mode, the next receive frame is corrupted due to the data of the previous frame being added in front of the last received frame. Software drivers have to reset the receive data path just after exiting power-down mode. The following subsections describe the two Wake-up on LAN mechanisms. Filtering for WoL The receive filter functionality can be used to generate Wake-up on LAN events. If the RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt bit of the IntStatus register if a frame is received that passes the filter. The interrupt will only be generated if the CRC of the frame is correct. Magic Packet WoL The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely intended for wake-up purposes. This packet can be received, analyzed and recognized by the Ethernet block and used to trigger a wake-up event. A Magic Packet is a packet that contains in its data portion the station address repeated 16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in the data portion of the packet. The whole packet must be a well-formed Ethernet frame. The magic packet detection unit analyzes the Ethernet packets, extracts the packet address and checks the payload for the Magic Packet pattern. The address from the packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 199 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet packet only sets the wake-up interrupt status bit if the packet passes the receive filter as illustrated in Figure 10–23: the result of the receive filter is ANDed with the magic packet filter result to produce the result. Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets is more strict. When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register, the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the bit writing a 1 to the corresponding bit of the RxFilterWoLClear register. Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55 0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet): FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 11 22 33 44 55 66 11 22 33 44 11 22 33 44 55 66 11 22 33 44 11 22 33 44 55 66 11 22 33 44 11 22 33 44 55 66 11 22 33 44 11 22 33 44 55 66 11 22 33 44 11 22 33 44 55 66 11 22 33 44 11 22 33 44 55 66 11 22 33 44 55 55 55 55 55 55 55 55 66 66 66 66 66 66 66 66 17.13 Enabling and disabling receive and transmit Enabling and disabling reception After reset, the receive function of the Ethernet block is disabled. The receive function can be enabled by the device driver setting the RxEnable bit in the Command register and the “RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order). The status of the receive data path can be monitored by the device driver by reading the RxStatus bit of the Status register. Figure 10–24 illustrates the state machine for the generation of the RxStatus bit. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 200 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet ACTIVE RxStatus = 1 xxxxxxxxxxxxxxxxxx RxEnable = 1 RxEnable = 0 and not busy receiving OR RxProduceIndex = RxConsumeIndex - 1 INACTIVE RxStatus = 0 reset Fig 24. Receive Active/Inactive state machine After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state. As soon as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If the receive data path is busy receiving a packet while the receive data path gets disabled, the packet will be received completely, stored to memory along with its status before returning to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will return to the INACTIVE state. For the state machine in Figure 10–24, a soft reset is like a hardware reset assertion, i.e. after a soft reset the receive data path is inactive until the data path is re-enabled. Enabling and disabling transmission After reset, the transmit function of the Ethernet block is disabled. The Tx transmit data path can be enabled by the device driver setting the TxEnable bit in the Command register to 1. The status of the transmit data paths can be monitored by the device driver reading the TxStatus bit of the Status register. Figure 10–25 illustrates the state machine for the generation of the TxStatus bit. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 201 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet ACTIVE TxStatus = 1 xxxxxxxxxxxxxxxxxxxxxx TxEnable = 1 AND TxProduceIndex TxConsumeIndex TxEnable = 0 and not busy transmitting OR TxProduceIndex = TxConsumeIndex INACTIVE TxStatus = 0 reset Fig 25. Transmit Active/Inactive state machine After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set in the Command register and the Produce and Consume indices are not equal, the state machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the transmit data path has completed all pending transmissions, including committing the transmission status to memory, the state machine returns to the INACTIVE state. The state machine will also return to the INACTIVE state if the Produce and Consume indices are equal again i.e. all frames have been transmitted. For the state machine in Figure 10–25, a soft reset is like a hardware reset assertion, i.e. after a soft reset the transmit data path is inactive until the data path is re-enabled. 17.14 Transmission padding and CRC In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’ (ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the MAC2 configuration register, as well as the Override and Pad bits from the transmit descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and ‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and CRC bits from the transmit descriptor Control word. The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable (ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the descriptor. If padding is required and enabled, a CRC will always be appended to the padded frames. A CRC will only be appended to the non-padded frames if ECRCE is set. If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is set. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 202 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating 64 or 68 bytes padded frames. If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information. 17.15 Huge frames and frame length checking The ‘HUGE FRAME ENABLE’ bit in the MAC2 configuration register can be set to 1 to enable transmission and reception of frames of any length. Huge frame transmission can be enabled on a per frame basis by setting the Override and Huge bits in the transmit descriptor Control word. When enabling huge frames, the Ethernet block will not check frame lengths and report frame length errors (RangeError and LengthError). If huge frames are enabled, the received byte count in the RSV register may be invalid because the frame may exceed the maximum size; the RxSize fields from the receive status arrays will be valid. Frame lengths are checked by comparing the length/type field of the frame to the actual number of bytes in the frame. A LengthError is reported by setting the corresponding bit in the receive StatusInfo word. The MAXF register allows the device driver to specify the maximum number of bytes in a frame. The Ethernet block will compare the actual receive frame to the MAXF value and report a RangeError in the receive StatusInfo word if the frame is larger. 17.16 Statistics counters Generally, Ethernet applications maintain many counters that track Ethernet traffic statistics. There are a number of standards specifying such counters, such as IEEE std 802.3 / clause 30. Other standards are RFC 2665 and RFC 2233. The approach taken here is that by default all counters are implemented in software. With the help of the StatusInfo field in frame statuses, many of the important statistics events listed in the standards can be counted by software. 17.17 MAC status vectors Transmit and receive status information as detected by the MAC are available in registers TSV0, TSV1 and RSV so that software can poll them. These registers are normally of limited use because the communication between driver software and the Ethernet block takes place primarily through frame descriptors. Statistical events can be counted by software in the device driver. However, for debug purposes the transmit and receive status vectors are made visible. They are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 203 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 17.18 Reset The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified. Hard reset After a hard reset, all registers will be set to their default value. Soft reset Parts of the Ethernet block can be soft reset by setting bits in the Command register and the MAC1 configuration register.The MAC1 register has six different reset bits: • SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware reset. • SIMULATION RESET: Resets the random number generator in the Transmit Function. The value after a hardware reset assertion is 0. • RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame logic) and the receive function in the MAC. The value after a hardware reset assertion is 0. • RESET Rx: Setting this bit will reset the receive function in the MAC. The value after a hardware reset assertion is 0. • RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame logic) and the transmit function in the MAC. The value after a hardware reset assertion is 0. • RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after a hardware reset assertion is 0. The above reset bits must be cleared by software. The Command register has three different reset bits: • TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit data path, excluding the MAC portions, including all (read-only) registers in the transmit data path, as well as the TxProduceIndex register in the host registers module. A soft reset of the transmit data path will abort all AHB transactions of the transmit data path. The reset bit will be cleared autonomously by the Ethernet block. A soft reset of the Tx data path will clear the TxStatus bit in the Status register. • RxReset: Writing a ‘1’ to the RxReset bit will reset the receive data path, excluding the MAC portions, including all (read-only) registers in the receive data path, as well as the RxConsumeIndex register in the host registers module. A soft reset of the receive data path will abort all AHB transactions of the receive data path. The reset bit will be cleared autonomously by the Ethernet block. A soft reset of the Rx data path will clear the RxStatus bit in the Status register. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 204 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet • RegReset: Resets all of the data paths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive data path. The reset bit will be cleared autonomously by the Ethernet block. To do a full soft reset of the Ethernet block, device driver software must: • • • • Set the ‘SOFT RESET’ bit in the MAC1 register to 1. Set the RegReset bit in the Command register, this bit clears automatically. Re-initialize the MAC registers (0x000 to 0x0FC). Reset the ‘SOFT RESET’ bit in the MAC1 register to 0. To reset just the transmit data path, the device driver software has to: • Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1. • Disable the Tx DMA managers by setting the TxEnable bits in the Command register to 0. • Set the TxReset bit in the Command register, this bit clears automatically. • Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0. To reset just the receive data path, the device driver software has to: • Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1 configuration register and resetting of the RxEnable bit of the Command register. • Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1. • Set the RxReset bit in the Command register, this bit clears automatically. • Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0. 17.19 Ethernet errors The Ethernet block generates errors for the following conditions: • A reception can cause an error: AlignmentError, RangeError, LengthError, SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in the receive StatusInfo and in the interrupt status register (IntStatus). • A transmission can cause an error: LateCollision, ExcessiveCollision, ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in the transmission StatusInfo and in the interrupt status register (IntStatus). UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 205 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 18. AHB bandwidth The Ethernet block is connected to an AHB bus which must carry all of the data and control information associated with all Ethernet traffic in addition to the CPU accesses required to operate the Ethernet block and deal with message contents. 18.1 DMA access Assumptions By making some assumptions, the bandwidth needed for each type of AHB transfer can be calculated and added in order to find the overall bandwidth requirement. The flexibility of the descriptors used in the Ethernet block allows the possibility of defining memory buffers in a range of sizes. In order to analyze bus bandwidth requirements, some assumptions must be made about these buffers. The "worst case" is not addressed since that would involve all descriptors pointing to single byte buffers, with most of the memory occupied in holding descriptors and very little data. It can easily be shown that the AHB cannot handle the huge amount of bus traffic that would be caused by such a degenerate (and illogical) case. For this analysis, an Ethernet packet is assumed to consist of a 64 byte frame. Continuous traffic is assumed on both the transmit and receive channels. This analysis does not reflect the flow of Ethernet traffic over time, which would include inter-packet gaps in both the transmit and receive channels that reduce the bandwidth requirements over a larger time frame. Types of DMA access and their bandwidth requirements The interface to an external Ethernet PHY is via RMII. RMII operates at 50 MHz, transferring a byte in 4 clock cycles. The data transfer rate is 12.5 Mbps. The Ethernet block initiates DMA accesses for the following cases: • Tx descriptor read: – Transmit descriptors occupy 2 words (8 bytes) of memory and are read once for each use of a descriptor. – Two word read happens once every 64 bytes (16 words) of transmitted data. – This gives 1/8th of the data rate, which = 1.5625 Mbps. • Rx descriptor read: – Receive descriptors occupy 2 words (8 bytes) of memory and are read once for each use of a descriptor. – Two word read happens once every 64 bytes (16 words) of received data. – This gives 1/8th of the data rate, which = 1.5625 Mbps. • Tx status write: – Transmit status occupies 1 word (4 bytes) of memory and is written once for each use of a descriptor. – One word write happens once every 64 bytes (16 words) of transmitted data. – This gives 1/16th of the data rate, which = 0.7813 Mbps. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 206 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet • Rx status write: – Receive status occupies 2 words (8 bytes) of memory and is written once for each use of a descriptor. – Two word write happens once every 64 bytes (16 words) of received data. – This gives 1/8 of the data rate, which = 1.5625 Mbps. • Tx data read: – Data transmitted in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. • Rx data write: – Data to be received in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function. 18.2 Types of CPU access • Accesses that mirror each of the DMA access types: – All or part of status values must be read, and all or part of descriptors need to be written after each use, transmitted data must be stored in the memory by the CPU, and eventually received data must be retrieved from the memory by the CPU. – This gives roughly the same or slightly lower rate as the combined DMA functions, which = 30.5 Mbps. • Access to registers in the Ethernet block: – The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus registers, and both read and write the RxConsumeIndex and TxProduceIndex registers. – 7 word read/writes once every 64 bytes (16 words) of transmitted and received data. – This gives 7/16 of the data rate, which = 5.4688 Mbps. This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function. 18.3 Overall bandwidth Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, which comes to approximately 66.5 MB/s. The peak bandwidth requirement can be somewhat higher due to the use of small memory buffers, in order to hold often used addresses (e.g. the station address) for example. Driver software can determine how to build frames in an efficient manner that does not overutilize the AHB. The bandwidth available on the AHB bus depends on the system clock frequency. As an example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses related to the Ethernet will be word transfers. The raw AHB bandwidth can be approximated as 4 bytes per two system clocks, which equals 2 times the system clock rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 207 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet for Ethernet traffic during simultaneous transmit and receive operations. This shows that it is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty of bandwidth headroom. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 208 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 19. CRC calculation The calculation is used for several purposes: • Generation the FCS at the end of the Ethernet frame. • Generation of the hash table index for the hash table filtering. • Generation of the destination and source address hash CRCs. The C pseudocode function below calculates the CRC on a frame taking the frame (without FCS) and the number of bytes in the frame as arguments. The function returns the CRC as a 32-bit integer. int crc_calc(char frame_no_fcs[], int frame_len) { int i; // iterator int j; // another iterator char byte; // current byte int crc; // CRC result int q0, q1, q2, q3; // temporary variables crc = 0xFFFFFFFF; for (i = 0; i < frame_len; i++) { byte = *frame_no_fcs++; for (j = 0; j < 2; j++) { if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) q3 = 0x04C11DB7; } else { q3 = 0x00000000; } if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) q2 = 0x09823B6E; } else { q2 = 0x00000000; } if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) q1 = 0x130476DC; } else { q1 = 0x00000000; } if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) q0 = 0x2608EDB8; } else { q0 = 0x00000000; } crc = (crc >= 4; } } return crc; } { { { { For FCS calculation, this function is passed a pointer to the first byte of the frame and the length of the frame without the FCS. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 209 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet For hash filtering, this function is passed a pointer to the destination address part of the frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits [28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector. If the corresponding bit is set the packet is passed, otherwise it is rejected by the hash filter. For obtaining the destination and source address hash CRCs, this function calculates first both the 32-bit CRCs, then the nine most significant bits from each 32-bit CRC are extracted, concatenated, and written in every StatusHashCRC word of every fragment status. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 210 of 835 UM10360 Chapter 11: LPC17xx USB device controller Rev. 01 — 4 January 2010 User manual 1. How to read this chapter This chapter describes the USB controller which is present on all LPC17xx devices except the LPC1767. On some LPC17xx family devices, the USB controller can also be configured for Host or OTG operation. 2. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the USB clock or with the Main PLL (PLL0). See Section 4–6.1. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 8–5). 4. Wake-up: Activity on the USB bus port can wake up the microcontroller from Power-down mode, see Section 4–8.8. 5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 11–13. 3. Introduction The Universal Serial Bus (USB) is a four-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame (SOF) marker and transactions that transfer data to or from device endpoints. Each device can have a maximum of 16 logical or 32 physical endpoints. There are four types of transfers defined for the endpoints. Control transfers are used to configure the device. Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no error correction. For more information on the Universal Serial Bus, see the USB Implementers Forum website. The USB device controller on the LPC17xx enables full-speed (12 Mb/s) data exchange with a USB host controller. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 211 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 183. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description AHB ATLE ATX DD DDP DMA EOP EP EP_RAM FS LED LS MPS NAK PLL RAM SOF SIE SRAM UDCA USB Advanced High-performance bus Auto Transfer Length Extraction Analog Transceiver DMA Descriptor DMA Description Pointer Direct Memory Access End-Of-Packet Endpoint Endpoint RAM Full Speed Light Emitting Diode Low Speed Maximum Packet Size Negative Acknowledge Phase Locked Loop Random Access Memory Start-Of-Frame Serial Interface Engine Synchronous RAM USB Device Communication Area Universal Serial Bus 4. Features • • • • • • • • • Fully compliant with the USB 2.0 specification (full speed). Supports 32 physical (16 logical) endpoints. Supports Control, Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time. Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. Supports SoftConnect and GoodLink features. Supports DMA transfers on all non-control endpoints. Allows dynamic switching between CPU controlled and DMA modes. Double buffer implementation for Bulk and Isochronous endpoints. 5. Fixed endpoint configuration Table 11–184 shows the supported endpoint configurations. Endpoints are realized and configured at run time using the Endpoint realization registers, documented in Section 11–10.4 “Endpoint realization registers”. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 212 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 184. Fixed endpoint configuration Logical endpoint Physical endpoint Endpoint type Direction Packet size (bytes) Double buffer 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Control Control Interrupt Interrupt Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Bulk Bulk Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In Out In 8, 16, 32, 64 8, 16, 32, 64 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 1 to 1023 1 to 1023 1 to 64 1 to 64 8, 16, 32, 64 8, 16, 32, 64 8, 16, 32, 64 8, 16, 32, 64 No No No No Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes Yes Yes 6. Functional description The architecture of the USB device controller is shown below in Figure 11–26. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 213 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller BUS MASTER INTERFACE DMA interface (AHB master) AHB BUS VBUS DMA ENGINE USB_CONNECT REGISTER INTERFACE EP_RAM ACCESS CONTROL SERIAL INTERFACE ENGINE USB ATX USB_D+ USB_D- USB_UP_LED register interface (AHB slave) EP_RAM (4K) USB DEVICE BLOCK Fig 26. USB device controller block diagram 6.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional D+ and D- signals of the USB bus. 6.2 Serial Interface Engine (SIE) The SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. It handles transfer of data between the endpoint buffers in EP_RAM and the USB bus. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. 6.3 Endpoint RAM (EP_RAM) Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the EP_RAM. The total EP_RAM space required depends on the number of realized endpoints, the maximum packet size of the endpoint, and whether the endpoint supports double buffering. 6.4 EP_RAM access control The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the three sources that can access it: the CPU (via the Register Interface), the SIE, and the DMA Engine. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 214 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 6.5 DMA engine and bus master interface When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints. When transferring data, the DMA Engine functions as a master on the AHB bus through the bus master interface. 6.6 Register interface The Register Interface allows the CPU to control the operation of the USB Device Controller. It also provides a way to write transmit data to the controller and read receive data from the controller. 6.7 SoftConnect The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow software to finish its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without having to unplug the cable. To use the SoftConnect feature, the CONNECT signal should control an external switch that connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the CONNECT signal by writing to the CON bit using the SIE Set Device Status command. 6.8 GoodLink Good USB connection indication is provided through GoodLink technology. When the device is successfully enumerated and configured, the LED indicator will be permanently ON. During suspend, the LED will be OFF. This feature provides a user-friendly indicator on the status of the USB device. It is a useful field diagnostics tool to isolate faulty equipment. To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED signal is controlled using the SIE Configure Device command. 7. Operational overview Transactions on the USB bus transfer data between device endpoints and the host. The direction of a transaction is defined with respect to the host. OUT transactions transfer data from the host to the device. IN transactions transfer data from the device to the host. All transactions are initiated by the host controller. For an OUT transaction, the USB ATX receives the bi-directional D+ and D- signals of the USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and converts it into a parallel data stream. The parallel data is written to the corresponding endpoint buffer in the EP_RAM. For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM, converts it into serial data, and transmits it onto the USB bus using the USB ATX. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 215 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Once data has been received or sent, the endpoint buffer can be read or written. How this is accomplished depends on the endpoint’s type and operating mode. The two operating modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode. In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the Register Interface. See Section 11–14 “Slave mode operation” for a detailed description of this mode. In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See Section 11–15 “DMA operation” for a detailed description of this mode. 8. Pin description Table 185. USB external interface Name Direction Description VBUS I VBUS status input. When this function is not enabled via its corresponding PINSEL register, it is driven HIGH internally. SoftConnect control signal. GoodLink LED control signal. Positive differential data. Negative differential data. USB_CONNECT USB_UP_LED USB_D+ USB_D- O O I/O I/O 9. Clocking and power management This section describes the clocking and power management features of the USB Device Controller. 9.1 Power requirements The USB protocol insists on power management by the device. This becomes very critical if the device draws power from the bus (bus-powered device). The following constraints should be met by a bus-powered device: 1. A device in the non-configured state should draw a maximum of 100 mA from the bus. 2. A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor. The maximum value is 500 mA. 3. A suspended device can draw a maximum of 2.5 mA. 9.2 Clocks The USB device controller clocks are shown in Table 11–186 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 216 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 186. USB device controller clock sources Clock source Description AHB master clock AHB slave clock usbclk Clock for the AHB master bus interface and DMA Clock for the AHB slave interface 48 MHz clock from the dedicated USB PLL (PLL1) or the Main PLL (PLL0), used to recover the 12 MHz clock from the USB bus 9.3 Power management support To help conserve power, the USB device controller automatically disables the AHB master clock and usbclk when not in use. When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), the usbclk input to the device controller is automatically disabled, helping to conserve power. However, if software wishes to access the device controller registers, usbclk must be active. To allow access to the device controller registers while in the suspend state, the USBClkCtrl and USBClkSt registers are provided. When software wishes to access the device controller registers, it should first ensure usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll the corresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain enabled until DEV_CLK_EN is cleared by software. When a DMA transfer occurs, the device controller automatically turns on the AHB master clock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure that DMA throughput is not affected by turning off the AHB master clock. 2 ms after the last DMA access, the AHB master clock is automatically disabled to help conserve power. If desired, software also has the capability of forcing this clock to remain enabled using the USBClkCtrl register. Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is set. When the device controller is not in use, all of the device controller clocks may be disabled by clearing PCUSB. The USB_NEED_CLK signal is used to facilitate going into and waking up from chip Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt register are asserted. After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off. When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK can be read from the USBIntSt register. Any bus activity in the suspend state will cause the USB_NEED_CLK signal to be asserted. When the chip is in Power-down mode and the USB interrupt is enabled, the assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 217 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 9.4 Remote wake-up The USB device controller supports software initiated remote wake-up. Remote wake-up involves resume signaling on the USB bus initiated from the device. This is done by clearing the SUS bit in the SIE Set Device Status register. Before writing into the register, all the clocks to the device controller have to be enabled using the USBClkCtrl register. 10. Register description Table 11–187 shows the USB Device Controller registers directly accessible by the CPU. The Serial Interface Engine (SIE) has other registers that are indirectly accessible via the SIE command registers. See Section 11–12 “Serial interface engine command description” for more info. Table 187. USB device register map Name Clock control registers Description Access Reset value[1] Address USBClkCtrl USBClkSt USBIntSt USBDevIntSt USBDevIntEn USBDevIntClr USBDevIntSet USBDevIntPri USBEpIntSt USBEpIntEn USBEpIntClr USBEpIntSet USBEpIntPri USBReEp USBEpInd USBMaxPSize USB transfer registers USB Clock Control USB Clock Status USB Interrupt Status USB Device Interrupt Status USB Device Interrupt Enable USB Device Interrupt Clear USB Device Interrupt Set USB Device Interrupt Priority USB Endpoint Interrupt Status USB Endpoint Interrupt Enable USB Endpoint Interrupt Clear USB Endpoint Interrupt Set USB Endpoint Priority USB Realize Endpoint USB Endpoint Index USB MaxPacketSize USB Receive Data USB Receive Packet Length USB Transmit Data USB Transmit Packet Length USB Control USB Command Code USB Command Data R/W RO R/W RO R/W WO WO WO RO R/W WO WO WO[2] R/W WO[2] R/W RO RO WO[2] WO[2] R/W WO[2] RO 0 0 0x8000 0000 0x10 0 0 0 0 0 0 0 0 0 0x3 0 0x8 0 0 0 0 0 0 0 0x5000 CFF4 0x5000 CFF8 0x400F C1C0 0x5000 C200 0x5000 C204 0x5000 C208 0x5000 C20C 0x5000 C22C 0x5000 C230 0x5000 C234 0x5000 C238 0x5000 C23C 0x5000 C240 0x5000 C244 0x5000 C248 0x5000 C24C 0x5000 C218 0x5000 C220 0x5000 C21C 0x5000 C224 0x5000 C228 0x5000 C210 0x5000 C214 © NXP B.V. 2010. All rights reserved. Device interrupt registers Endpoint interrupt registers Endpoint realization registers USBRxData USBRxPLen USBTxData USBTxPLen USBCtrl USBCmdCode USBCmdData UM10360_1 SIE Command registers User manual Rev. 01 — 4 January 2010 218 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 187. USB device register map Name DMA registers Description Access Reset value[1] Address USBDMARSt USBDMARClr USBDMARSet USBUDCAH USBEpDMASt USBEpDMAEn USBEpDMADis USBDMAIntSt USBDMAIntEn USBEoTIntSt USBEoTIntClr USBEoTIntSet USBNDDRIntSt USBNDDRIntClr USBNDDRIntSet USBSysErrIntSt USBSysErrIntClr USBSysErrIntSet [1] [2] USB DMA Request Status USB DMA Request Clear USB DMA Request Set USB UDCA Head USB Endpoint DMA Status USB Endpoint DMA Enable USB Endpoint DMA Disable USB DMA Interrupt Status USB DMA Interrupt Enable USB End of Transfer Interrupt Status USB End of Transfer Interrupt Clear USB End of Transfer Interrupt Set USB New DD Request Interrupt Status USB New DD Request Interrupt Clear USB New DD Request Interrupt Set USB System Error Interrupt Status USB System Error Interrupt Clear USB System Error Interrupt Set RO WO[2] WO[2] R/W RO WO[2] WO[2] RO R/W RO WO[2] WO[2] RO WO[2] WO[2] RO WO[2] WO[2] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x5000 C250 0x5000 C254 0x5000 C258 0x5000 C280 0x5000 C284 0x5000 C288 0x5000 C28C 0x5000 C290 0x5000 C294 0x5000 C2A0 0x5000 C2A4 0x5000 C2A8 0x5000 C2AC 0x5000 C2B0 0x5000 C2B4 0x5000 C2B8 0x5000 C2BC 0x5000 C2C0 Reset value reflects the data stored in used bits only. It does not include reserved bits content. Reading WO register will return an invalid value. 10.1 Clock control registers 10.1.1 USB Clock Control register (USBClkCtrl - 0x5000 CFF4) This register controls the clocking of the USB Device Controller. Whenever software wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN must be set. The PORTSEL_CLK_EN bit need only be set when accessing the OTGStCtrl register (see Section 13–8.6) when the USB is used in OTG configuration. The software does not have to repeat this exercise for every register access, provided that the corresponding USBClkCtrl bits are already set. Note that this register is functional only when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device controller are disabled irrespective of the contents of this register. USBClkCtrl is a read/write register. Table 188. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description Bit Symbol Description Reset value 0 1 2 DEV_CLK_EN - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Device clock enable. Enables the usbclk input to the device controller Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 0 NA UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 219 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 188. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description Bit Symbol Description Reset value 3 4 31:5 PORTSEL_CLK_EN AHB_CLK_EN - Port select register clock enable. AHB clock enable Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 0 NA 10.1.2 USB Clock Status register (USBClkSt - 0x5000 CFF8) This register holds the clock availability status. The bits of this register are ORed together to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with the register access. Software does not have to repeat this exercise for every access, provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read-only register. Table 189. USB Clock Status register (USBClkSt - address 0x5000 CFF8) bit description Bit Symbol Description Reset value 0 1 2 3 4 31:5 DEV_CLK_ON PORTSEL_CLK_ON AHB_CLK_ON - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Device clock on. The usbclk input to the device controller is active. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Port select register clock on. AHB clock on. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 0 NA NA 0 NA 10.2 Device interrupt registers 10.2.1 USB Interrupt Status register (USBIntSt - 0x5000 C1C0) The USB Device Controller has three interrupt lines. This register allows software to determine their status with a single read operation. All three interrupt lines are ORed together to a single channel of the vectored interrupt controller. This register also contains the USB_NEED_CLK status and EN_USB_INTS control bits. USBIntSt is a read/write register. Table 190. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description Bit Symbol Description Reset value 0 1 2 7:3 USB_INT_REQ_LP USB_INT_REQ_HP USB_INT_REQ_DMA - Low priority interrupt line status. This bit is read-only. High priority interrupt line status. This bit is read-only. DMA interrupt line status. This bit is read-only. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 0 NA UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 220 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 190. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description Bit Symbol Description Reset value 8 USB_NEED_CLK USB need clock indicator. This bit is set to 1 when USB activity or a change 1 of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4–8.8 “Wake-up from Reduced Power Modes” for details). Also see Section 4–5.9 “PLL0 and Power-down mode” and Section 4–8.9 “Power Control for Peripherals register (PCONP - 0x400F C0C4)” for considerations about the PLL and invoking the Power-down mode. This bit is read-only. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Enable all USB interrupts. When this bit is cleared, the Vectored Interrupt Controller does not see the ORed output of the USB interrupt lines. NA 1 30:9 31 EN_USB_INTS 10.2.2 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200) The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and 1 indicates the presence of the interrupt. USBDevIntSt is a read-only register. Table 191. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ERR_INT 1 EP_RLZED 0 TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME Table 192. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description Bit Symbol Description Reset value 0 1 2 3 FRAME EP_FAST EP_SLOW DEV_STAT The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0 Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, 0 the corresponding endpoint interrupt will be routed to this bit. Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. 0 Set when USB Bus reset, USB suspend change or Connect change event occurs. 0 Refer to Section 11–12.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on page 245. The command code register (USBCmdCode) is empty (New command can be written). 1 Command data register (USBCmdData) is full (Data can be read now). The current packet in the endpoint buffer is transferred to the CPU. 0 0 4 5 6 7 CCEMPTY CDFULL RxENDPKT TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes 0 programmed in the TxPacket length register (USBTxPLen). © NXP B.V. 2010. All rights reserved. UM10360_1 User manual Rev. 01 — 4 January 2010 221 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 192. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description Bit Symbol Description Reset value 8 9 EP_RLZED ERR_INT Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize 0 register (USBMaxPSize) is updated and the corresponding operation is completed. Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 11–12.9 “Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 247 0 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 10.2.3 USB Device Interrupt Enable register (USBDevIntEn - 0x5000 C204) Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to generate an interrupt on one of the interrupt lines when set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. USBDevIntEn is a read/write register. Table 193. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ERR_INT 1 EP_RLZED 0 TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME Table 194. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit description Bit Symbol Value Description Reset value 31:0 See 0 USBDevIntEn 1 bit allocation table above No interrupt is generated. An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 11–191) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri. 0 10.2.4 USB Device Interrupt Clear register (USBDevIntClr - 0x5000 C208) Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a zero has no effect. Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding endpoint interrupts in USBEpIntSt should be cleared. USBDevIntClr is a write-only register. Table 195. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation Reset value: 0x0000 0000 Bit Symbol UM10360_1 31 30 29 28 27 26 25 24 - - - Rev. 01 — 4 January 2010 - - - 222 of 835 © NXP B.V. 2010. All rights reserved. User manual NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 22 21 20 19 18 17 16 Bit Symbol Bit Symbol Bit Symbol 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ERR_INT 1 EP_RLZED 0 TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME Table 196. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit description Bit Symbol Value Description Reset value 31:0 See 0 USBDevIntClr 1 bit allocation table above No effect. The corresponding bit in USBDevIntSt (Section 11–10.2.2) is cleared. 0 10.2.5 USB Device Interrupt Set register (USBDevIntSet - 0x5000 C20C) Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing a zero has no effect USBDevIntSet is a write-only register. Table 197. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ERR_INT 1 EP_RLZED 0 TxENDPKT Rx ENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME Table 198. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit description Bit Symbol Value Description Reset value 31:0 See 0 USBDevIntSet 1 bit allocation table above No effect. The corresponding bit in USBDevIntSt (Section 11–10.2.2) is set. 0 10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C) Writing one to a bit in this register causes the corresponding interrupt to be routed to the USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write-only register. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 223 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 199. USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description Bit Symbol Value Description Reset value 0 1 31:2 FRAME EP_FAST - 0 1 0 1 FRAME interrupt is routed to USB_INT_REQ_LP. FRAME interrupt is routed to USB_INT_REQ_HP. EP_FAST interrupt is routed to USB_INT_REQ_LP. EP_FAST interrupt is routed to USB_INT_REQ_HP. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 NA 10.3 Endpoint interrupt registers The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are used in Slave mode operation. 10.3.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0x5000 C230) Each physical non-isochronous endpoint is represented by a bit in this register to indicate that it has generated an interrupt. All non-isochronous OUT endpoints generate an interrupt when they receive a packet without an error. All non-isochronous IN endpoints generate an interrupt when a packet is successfully transmitted, or when a NAK handshake is sent on the bus and the interrupt on NAK feature is enabled (see Section 11–12.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page 244). A bit set to one in this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set depending on the value of the corresponding bit of USBEpDevIntPri. USBEpIntSt is a read-only register. Note that for Isochronous endpoints, handling of packet data is done when the FRAME interrupt occurs. Table 200. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 EP15TX 23 EP15RX 22 EP14TX 21 EP14RX 20 EP13TX 19 EP13RX 18 EP12TX 17 EP12RX 16 EP11TX 15 EP11RX 14 EP10TX 13 EP10RX 12 EP9TX 11 EP9RX 10 EP8TX 9 EP8RX 8 EP7TX 7 EP7RX 6 EP6TX 5 EP6RX 4 EP5TX 3 EP5RX 2 EP4TX 1 EP4RX 0 EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 201. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description Bit Symbol Description Reset value 0 1 2 3 4 5 UM10360_1 EP0RX EP0TX EP1RX EP1TX EP2RX EP2TX Endpoint 0, Data Received Interrupt bit. Endpoint 0, Data Transmitted Interrupt bit or sent a NAK. Endpoint 1, Data Received Interrupt bit. Endpoint 1, Data Transmitted Interrupt bit or sent a NAK. Endpoint 2, Data Received Interrupt bit. Endpoint 2, Data Transmitted Interrupt bit or sent a NAK. 0 0 0 0 0 0 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 224 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 201. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description Bit Symbol Description Reset value 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EP3RX EP3TX EP4RX EP4TX EP5RX EP5TX EP6RX EP6TX EP7RX EP7TX EP8RX EP8TX EP9RX EP9TX EP10RX EP10TX EP11RX EP11TX EP12RX EP12TX EP13RX EP13TX EP14RX EP14TX EP15RX EP15TX Endpoint 3, Isochronous endpoint. Endpoint 3, Isochronous endpoint. Endpoint 4, Data Received Interrupt bit. Endpoint 4, Data Transmitted Interrupt bit or sent a NAK. Endpoint 5, Data Received Interrupt bit. Endpoint 5, Data Transmitted Interrupt bit or sent a NAK. Endpoint 6, Isochronous endpoint. Endpoint 6, Isochronous endpoint. Endpoint 7, Data Received Interrupt bit. Endpoint 7, Data Transmitted Interrupt bit or sent a NAK. Endpoint 8, Data Received Interrupt bit. Endpoint 8, Data Transmitted Interrupt bit or sent a NAK. Endpoint 9, Isochronous endpoint. Endpoint 9, Isochronous endpoint. Endpoint 10, Data Received Interrupt bit. Endpoint 10, Data Transmitted Interrupt bit or sent a NAK. Endpoint 11, Data Received Interrupt bit. Endpoint 11, Data Transmitted Interrupt bit or sent a NAK. Endpoint 12, Isochronous endpoint. Endpoint 12, Isochronous endpoint. Endpoint 13, Data Received Interrupt bit. Endpoint 13, Data Transmitted Interrupt bit or sent a NAK. Endpoint 14, Data Received Interrupt bit. Endpoint 14, Data Transmitted Interrupt bit or sent a NAK. Endpoint 15, Data Received Interrupt bit. Endpoint 15, Data Transmitted Interrupt bit or sent a NAK. NA NA 0 0 0 0 NA NA 0 0 0 0 NA NA 0 0 0 0 NA NA 0 0 0 0 0 0 10.3.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0x5000 C234) Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated endpoint. USBEpIntEn is a read/write register. Table 202. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 EP15TX 23 EP15RX 22 EP14TX 21 EP14RX 20 EP13TX 19 EP13RX 18 EP12TX 17 EP12RX 16 EP11TX 15 EP11RX 14 EP10TX 13 EP10RX 12 EP9TX 11 EP9RX 10 EP8TX 9 EP8RX 8 EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 225 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 6 5 4 3 2 1 0 Bit Symbol 7 EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 203. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntEn bit 0 allocation table above 1 The corresponding bit in USBDMARSt is set when an interrupt occurs 0 for this endpoint. The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint. 10.3.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0x5000 C238) Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt command to be executed (Table 11–247) for the corresponding physical endpoint. Writing zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the CDFULL bit is set, USBCmdData contains the status of the endpoint, and the corresponding bit in USBEpIntSt is cleared. Notes: • When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be set to ensure the corresponding interrupt has been cleared before proceeding. • While setting multiple bits in USBEpIntClr simultaneously is possible, it is not recommended; only the status of the endpoint corresponding to the least significant interrupt bit cleared will be available at the end of the operation. • Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly invoked using the SIE command registers, but using USBEpIntClr is recommended because of its ease of use. Each physical endpoint has its own reserved bit in this register. The bit field definition is the same as that of USBEpIntSt shown in Table 11–200. USBEpIntClr is a write-only register. Table 204. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 EP15TX 23 EP15RX 22 EP14TX 21 EP14RX 20 EP13TX 19 EP13RX 18 EP12TX 17 EP12RX 16 EP11TX 15 EP11RX 14 EP10TX 13 EP10RX 12 EP9TX 11 EP9RX 10 EP8TX 9 EP8RX 8 EP7TX 7 EP7RX 6 EP6TX 5 EP6RX 4 EP5TX 3 EP5RX 2 EP4TX 1 EP4RX 0 EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 226 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 205. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntClr bit allocation table above 0 1 No effect. Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint. 0 10.3.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0x5000 C23C) Writing a one to a bit in this register sets the corresponding bit in USBEpIntSt. Writing zero has no effect. Each endpoint has its own bit in this register. USBEpIntSet is a write-only register. Table 206. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 EP15TX 23 EP15RX 22 EP14TX 21 EP14RX 20 EP13TX 19 EP13RX 18 EP12TX 17 EP12RX 16 EP11TX 15 EP11RX 14 EP10TX 13 EP10RX 12 EP9TX 11 EP9RX 10 EP8TX 9 EP8RX 8 EP7TX 7 EP7RX 6 EP6TX 5 EP6RX 4 EP5TX 3 EP5RX 2 EP4TX 1 EP4RX 0 EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 207. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntSet bit allocation table above 0 1 No effect. Sets the corresponding bit in USBEpIntSt. 0 10.3.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0x5000 C240) This register determines whether an endpoint interrupt is routed to the EP_FAST or EP_SLOW bits of USBDevIntSt. If a bit in this register is set to one, the interrupt is routed to EP_FAST, if zero it is routed to EP_SLOW. Routing of multiple endpoints to EP_FAST or EP_SLOW is possible. Note that the USBDevIntPri register determines whether the EP_FAST interrupt is routed to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line. USBEpIntPri is a write-only register. Table 208. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation Reset value: 0x0000 0000 Bit Symbol Bit Symbol Bit Symbol Bit Symbol UM10360_1 31 30 29 28 27 26 25 24 EP15TX 23 EP15RX 22 EP14TX 21 E14RX 20 EP13TX 19 EP13RX 18 EP12TX 17 EP12RX 16 EP11TX 15 EP11RX 14 EP10TX 13 EP10RX 12 EP9TX 11 EP9RX 10 EP8TX 9 EP8RX 8 EP7TX 7 EP7RX 6 EP6TX 5 EP6RX 4 EP5TX 3 EP5RX 2 EP4TX 1 EP4RX 0 EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX 227 of 835 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 209. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntPri bit allocation table above 0 1 The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt 0 10.4 Endpoint realization registers The registers in this group allow realization and configuration of endpoints at run time. 10.4.1 EP RAM requirements The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next word boundary. Also, each buffer has one word header showing the size of the packet length received. The EP_ RAM space (in words) required for the physical endpoint can be expressed as MaxPacketSize + 3 EPRAMspace = ⎛ ------------------------------------------------- + 1⎞ × dbstatus ⎝ ⎠ 4 where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint. Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is N TotalEPRAMspace = 32 + ∑ n=0 EPRAMspace ( n ) where N is the number of realized endpoints. Total EP_RAM space should not exceed 4096 bytes (4 kB, 1 kwords). 10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244) Writing one to a bit in this register causes the corresponding endpoint to be realized. Writing zeros causes it to be unrealized. This register returns to its reset state when a bus reset occurs. USBReEp is a read/write register. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 228 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller Table 210. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit allocation Reset value: 0x0000 0003 Bit Symbol Bit Symbol Bit Symbol Bit Symbol 31 30 29 28 27 26 25 24 EP31 23 EP30 22 EP29 21 EP28 20 EP27 19 EP26 18 EP25 17 EP24 16 EP23 15 EP22 14 EP21 13 EP20 12 EP19 11 EP18 10 EP17 9 EP16 8 EP15 7 EP14 6 EP13 5 EP12 4 EP11 3 EP10 2 EP9 1 EP8 0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 Table 211. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit description Bit Symbol Value Description Reset value 0 1 31:2 EP0 EP1 EPxx 0 1 0 1 0 1 Control endpoint EP0 is not realized. Control endpoint EP0 is realized. Control endpoint EP1 is not realized. Control endpoint EP1 is realized. Endpoint EPxx is not realized. Endpoint EPxx is realized. 1 1 0 On reset, only the control endpoints are realized. Other endpoints, if required, are realized by programming the corresponding bits in USBReEp. To calculate the required EP_RAM space for the realized endpoints, see Section 11–10.4.1. Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is shown below. Clear EP_RLZED bit in USBDevIntSt; for every endpoint to be realized, { /* OR with the existing value of the Realize Endpoint register */ USBReEp |= (UInt32) ((0x1 0) and DLM = 0, the value of the DLL register must be greater than 2. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 332 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Table 305: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description Bit Function Value Description Reset value 3:0 7:4 DIVADDVAL MULVAL 0 1 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. 0 1 31:8 - NA Reserved, user software should not write ones to reserved bits. The value read 0 from a reserved bit is not defined. This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART1 disabled making sure that UART1 is fully software and hardware compatible with UARTs not equipped with this feature. UART1 baud rate can be calculated as (n = 1): (4) PCLK UART1 baudrate = ---------------------------------------------------------------------------------------------------------------------------------DivAddVal 16 × ( 256 × U1DLM + U1DLL ) × ⎛ 1 + ---------------------------- ⎞ ⎝ MulVal ⎠ Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 1 ≤ MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 14 3. DIVADDVAL < MULVAL The value of the U1FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. If the U1FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided. 4.16.1 Baud rate calculation UART1 can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 333 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Calculating UART baudrate (BR) PCLK, BR DL est = PCLK/(16 x BR) DL est is an integer? True False FR est = 1.5 DIVADDVAL = 0 MULVAL = 1 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DL est [15:8] DLL = DLest [7:0] End Fig 50. Algorithm for setting UART dividers UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 334 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Table 306. Fractional Divider setting look-up table FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal 1.000 1.067 1.071 1.077 1.083 1.091 1.100 1.111 1.125 1.133 1.143 1.154 1.167 1.182 1.200 1.214 1.222 1.231 0/1 1/15 1/14 1/13 1/12 1/11 1/10 1/9 1/8 2/15 1/7 2/13 1/6 2/11 1/5 3/14 2/9 3/13 1.250 1.267 1.273 1.286 1.300 1.308 1.333 1.357 1.364 1.375 1.385 1.400 1.417 1.429 1.444 1.455 1.462 1.467 1/4 4/15 3/11 2/7 3/10 4/13 1/3 5/14 4/11 3/8 5/13 2/5 5/12 3/7 4/9 5/11 6/13 7/15 1.500 1.533 1.538 1.545 1.556 1.571 1.583 1.600 1.615 1.625 1.636 1.643 1.667 1.692 1.700 1.714 1.727 1.733 1/2 8/15 7/13 6/11 5/9 4/7 7/12 3/5 8/13 5/8 7/11 9/14 2/3 9/13 7/10 5/7 8/11 11/15 1.750 1.769 1.778 1.786 1.800 1.818 1.833 1.846 1.857 1.867 1.875 1.889 1.900 1.909 1.917 1.923 1.929 1.933 3/4 10/13 7/9 11/14 4/5 9/11 5/6 11/13 6/7 13/15 7/8 8/9 9/10 10/11 11/12 12/13 13/14 14/15 4.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600 According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600) = 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and DLL = 96. 4.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200 According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) = 6.51. This DLest is not an integer number and the next step is to estimate the FR parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up table. The closest value for FRest = 1.628 in the look-up Table 15–306 is FR = 1.625. It is equivalent to DIVADDVAL = 5 and MULVAL = 8. Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4, DIVADDVAL = 5, and MULVAL = 8. According to Equation 15–4 the UART rate is 115384. This rate has a relative error of 0.16% from the originally specified 115200. 4.17 UART1 Transmit Enable Register (U1TER - 0x4001 0030) In addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), U1TER enables implementation of software flow control, too. When TxEn=1, UART1 transmitter will keep sending data as long as they are available. As soon as TxEn becomes 0, UART1 transmission will stop. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 335 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Although Table 15–307 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART1 transmission will stop. Table 15–307 describes how to use TXEn bit in order to achieve software flow control. Table 307: UART1 Transmit Enable Register (U1TER - address 0x4001 0030) bit description Bit Symbol Description Reset Value 6:0 7 TXEN Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as 1 soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31:8 - 4.18 UART1 RS485 Control register (U1RS485CTRL - 0x4001 004C) The U1RS485CTRL register controls the configuration of the UART in RS-485/EIA-485 mode. Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description Bit Symbol Value Description Reset value 0 NMMEN 0 1 RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. The receiver is enabled. The receiver is disabled. Auto Address Detect (AAD) is disabled. Auto Address Detect (AAD) is enabled. 0 1 2 3 4 RXDIS AADEN SEL DCTRL 0 1 0 1 0 1 0 1 0 0 If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. Disable Auto Direction Control. Enable Auto Direction Control. 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 336 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description Bit Symbol Value Description Reset value 5 OINV 0 1 This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0 The direction control pin will be driven to logic ‘0’ when the transmitter has data to be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted. The direction control pin will be driven to logic ‘1’ when the transmitter has data to be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31:6 - - 4.19 UART1 RS-485 Address Match register (U1RS485ADRMATCH 0x4001 0050) The U1RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 309. UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description Bit Symbol Description Reset value 7:0 31:8 ADRMATCH - Contains the address match value. 0x00 Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 4.20 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054) The user may program the 8-bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. Table 310. UART1 RS-485 Delay value register (U1RS485DLY - address 0x4001 0054) bit description Bit Symbol Description Reset value 7:0 31:8 DLY - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. 0x00 Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 4.21 RS-485/EIA-485 modes of operation The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave. The addressable slave is one of multiple slaves controlled by a single master. The UART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’. Each UART slave receiver can be assigned a unique address. The slave can be programmed to either manually or automatically reject data following an address which is not theirs. RS-485/EIA-485 Normal Multidrop Mode (NMM) Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 337 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. While the receiver is ENABLED (RS485CTRL bit 1 =’0’) all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address. When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver. RS-485/EIA-485 Auto Address Detection (AAD) mode When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are set, the UART is in auto address detect mode. In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit value programmed into the RS485ADRMATCH register. If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value. When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be cleared by hardware). The receiver will also generate n Rx Data Ready Interrupt. While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO. RS-485/EIA-485 Auto Direction Control RS485/EIA-485 Mode includes the option of allowing the transmitter to automatically control the state of either the RTS pin or the DTR pin as a direction control output signal. Setting RS485CTRL bit 4 = ‘1’ enables this feature. Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use the DTR pin when RS485CTRL bit 3 = ‘1’. When Auto Direction Control is enabled, the selected pin will be asserted (driven low) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven high) once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register. The RS485CTRL bit 4 takes precedence over all other mechanisms controlling RTS (or DTR) with the exception of loopback mode. RS485/EIA-485 driver delay time The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 338 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 RS485/EIA-485 output inversion The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin will be driven to logic 0 after the last bit of data has been transmitted. 4.22 UART1 FIFO Level register (U1FIFOLVL - 0x4001 0058) U1FIFOLVL register is a read-only register that allows software to read the current FIFO level status. Both the transmit and receive FIFO levels are present in this register. Table 311. UART1 FIFO Level register (U1FIFOLVL - address 0x4001 0058) bit description Bit Symbol Description Reset value 3:0 7:4 11:8 RXFIFILVL TXFIFOLVL Reflects the current level of the UART1 receiver FIFO. 0 = empty, 0xF = FIFO full. Reserved. The value read from a reserved bit is not defined. Reflects the current level of the UART1 transmitter FIFO. 0 = empty, 0xF = FIFO full. Reserved, the value read from a reserved bit is not defined. 0x00 NA 0x00 NA 31:12 - 5. Architecture The architecture of the UART1 is shown below in the block diagram. The APB interface provides a communications link between the CPU or host and the UART1. The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input. The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register (U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the serial output pin, TXD1. The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT. The modem interface contains registers U1MCR and U1MSR. This interface is responsible for handshaking between a modem peripheral and the UART1. The interrupt interface contains registers U1IER and U1IIR. The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks. Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 339 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Transmitter Transmitter Holding Register Transmitter FIFO Transmitter DMA Interface TX_DMA_REQ TX_DMA_CLR Baud Rate Generator Fractional Main Rate Divider Divider (DLM, DLL) FIFO Control & Status Interrupt Control & Status U1_OE Line Control & Status RS485, IrDA, & Auto-baud Receiver Receiver Buffer Register Receiver FIFO Receiver DMA Interface RX_DMA_REQ RX_DMA_CLR Receiver Shift Register U1_RXD Transmitter Shift Register U1_TXD PCLK UART1 interrupt U1_CTS U1_RTS U1_DSR U1_DTR U1_DCD U1_RI Modem Control & Status Fig 51. UART1 block diagram UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 340 of 835 UM10360 Chapter 16: LPC17xx CAN1/2 Rev. 01 — 4 January 2010 User manual 1. Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 4–46), set bits PCAN1/2. Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_CAN1, PCLK_CAN2, and, for the acceptance filter, PCLK_ACF. Note that these must all be the same value. Remark: If CAN baud rates above 100 kbit/s (see Table 16–323) are needed, do not select the IRC as the clock source (see Table 4–17). 3. Wake-up: CAN controllers are able to wake up the microcontroller from Power-down mode, see Section 4–8.8. 4. Pins: Select CAN1/2 pins through the PINSEL registers and their pin modes through the PINMODE registers (Section 8–5). 5. Interrupts: CAN interrupts are enabled using the CAN1/2IER registers (Table 16–322). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. CAN controller initialization: see CANMOD register (Section 16–7.1). 2. CAN controllers Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The CAN Controller is designed to provide a full implementation of the CAN-Protocol according to the CAN Specification Version 2.0B. Microcontrollers with this on-chip CAN controller are used to build powerful local networks by supporting distributed real-time control with a very high level of security. The applications are automotive, industrial environments, and high speed networks as well as low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced diagnostic and supervisory capabilities. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in various applications. The CAN module consists of two elements: the controller and the Acceptance Filter. All registers and the RAM are accessed as 32-bit words. 3. Features 3.1 General CAN features • Compatible with CAN specification 2.0B, ISO 11898-1. • Multi-master architecture with non destructive bit-wise arbitration. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 341 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 • • • • • • • Bus access priority determined by the message identifier (11-bit or 29-bit). Guaranteed latency time for high priority messages. Programmable transfer rate (up to 1 Mbit/s). Multicast and broadcast message facility. Data length from 0 up to 8 bytes. Powerful error handling capability. Non-return-to-zero (NRZ) encoding/decoding with bit stuffing. 3.2 CAN controller features • • • • • • • • 2 CAN controllers and buses. Supports 11-bit identifier as well as 29-bit identifier. Double Receive Buffer and Triple Transmit Buffer. Programmable Error Warning Limit and Error Counters with read/write access. Arbitration Lost Capture and Error Code Capture with detailed bit position. Single Shot Transmission (no re-transmission). Listen Only Mode (no acknowledge, no active error flags). Reception of "own" messages (Self Reception Request). 3.3 Acceptance filter features • Fast hardware implemented search algorithm supporting a large number of CAN identifiers. • Global Acceptance Filter recognizes 11-bit and 29-bit Rx Identifiers for all CAN buses. • Allows definition of explicit and groups for 11-bit and 29-bit CAN identifiers. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. 4. Pin description Table 312. CAN Pin descriptions Pin Name Type Description Serial Inputs. From CAN transceivers. Serial Outputs. To CAN transceivers. RD1, RD2 TD1, TD2 Input Output 5. CAN controller architecture The CAN Controller is a complete serial interface with both Transmit and Receive Buffers but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a separate block (Acceptance Filter). Except for message buffering and acceptance filtering the functionality is similar to the PeliCAN concept. The CAN Controller Block includes interfaces to the following blocks: • APB Interface UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 342 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 • • • • Acceptance Filter Nested Vectored Interrupt Controller (NVIC) CAN Transceiver Common Status Registers APB BUS INTERFACE MANAGEMENT LOGIC CAN CORE BLOCK TX ERROR MANAGEMENT LOGIC RX CAN TRANSCEIVER NVIC TRANSMIT BUFFERS 1,2 AND 3 COMMON STATUS REGISTER BIT TIMING LOGIC ACCEPTANCE FILTER RECEIVE BUFFERS 1 AND 2 BIT STREAM PROCESSOR Fig 52. CAN controller block diagram 5.1 APB Interface Block (AIB) The APB Interface Block provides access to all CAN Controller registers. 5.2 Interface Management Logic (IML) The Interface Management Logic interprets commands from the CPU, controls internal addressing of the CAN Registers and provides interrupts and status information to the CPU. 5.3 Transmit Buffers (TXB) The TXB represents a Triple Transmit Buffer, which is the interface between the Interface Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is able to store a complete message which can be transmitted over the CAN network. This buffer is written by the CPU and read out by the BSP. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 343 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 31 24 23 16 15 87 0 TX Frame info unused 0 ... 0 TX DLC unused TX Priority ID.28 ... ID.18 TFS TID TDA Descriptor Field TX Data 4 TX Data 8 TX Data 3 TX Data 7 TX Data 2 TX Data 6 TX Data 1 TX Data 5 Data Field TDB Standard Frame Format (11-bit Identifier) 31 24 23 16 15 87 0 TX 000 Frame info ID.28 unused TX DLC ... unused TX Priority ID.00 TFS TID TDA Descriptor Field TX Data 4 TX Data 8 TX Data 3 TX Data 7 TX Data 2 TX Data 6 TX Data 1 TX Data 5 Data Field TDB Extended Frame Format (29-bit Identifier) Fig 53. Transmit buffer layout for standard and extended frame format configurations 5.4 Receive Buffer (RXB) The Receive Buffer (RXB) represents a CPU accessible Double Receive Buffer. It is located between the CAN Controller Core Block and APB Interface Block and stores all received messages from the CAN Bus line. With the help of this Double Receive Buffer concept the CPU is able to process one message while another message is being received. The global layout of the Receive Buffer is very similar to the Transmit Buffer described earlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length Code have the same meaning as described for the Transmit Buffer. In addition, the Receive Buffer includes an ID Index field (see Section 16–7.9.1 “ID index field”). The received Data Length Code represents the real transmitted Data Length Code, which may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum number of received data bytes is 8. This should be taken into account by reading a message from the Receive Buffer. If there is not enough space for a new message within the Receive Buffer, the CAN Controller generates a Data Overrun condition when this message becomes valid and the acceptance test was positive. A message that is partly written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. This situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if enabled. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 344 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 31 24 23 16 15 10 9 8 7 0 RX Frame info unused unused RX DLC unused ID Index ID.28 ... ID.18 RFS RID RDA Descriptor Field RX Data 4 RX Data 8 RX Data 3 RX Data 7 RX Data 2 RX Data 6 RX Data 1 RX Data 5 Data Field RDB BPM=bypass message Standard Frame Format (11-bit Identifier) 31 24 23 16 15 10 9 8 7 0 RX unused Frame info ID.28 unused RX DLC ... unused ID Index ID.00 RFS RID RDA Descriptor Field RX Data 4 RX Data 8 RX Data 3 RX Data 7 RX Data 2 RX Data 6 RX Data 1 RX Data 5 Data Field RDB Extended Frame Format (29-bit Identifier) Fig 54. Receive buffer layout for standard and extended frame format configurations 5.5 Error Management Logic (EML) The EML is responsible for the error confinement. It gets error announcements from the BSP and then informs the BSP and IML about error statistics. 5.6 Bit Timing Logic (BTL) The Bit Timing Logic monitors the serial CAN Bus line and handles the Bus line related bit timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant" Bus line transition at the beginning of a message (hard synchronization) and re-synchronizes on further transitions during the reception of a message (soft synchronization). The BTL also provides programmable time segments to compensate for the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the sample point and the number of samples to be taken within a bit time. 5.7 Bit Stream Processor (BSP) The Bit Stream Processor is a sequencer, controlling the data stream between the Transmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection, arbitration, stuffing and error handling on the CAN Bus. 5.8 CAN controller self-tests The CAN controller supports two different options for self-tests: • Global Self-Test (setting the self reception request bit in normal Operating Mode) • Local Self-Test (setting the self reception request bit in Self Test Mode) UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 345 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled. Global self test A Global Self-Test can for example be used to verify the chosen configuration of the CAN Controller in a given CAN system. As shown in Figure 16–55, at least one other CAN node, which is acknowledging each CAN message has to be connected to the CAN bus. TX Buffer TX Buffer TX Buffer LPC17xx Transceiver CAN Bus ack RX Buffer Fig 55. Global Self-Test (high-speed CAN Bus example) Initiating a Global Self-Test is similar to a normal CAN transmission. In this case the transmission of a CAN message(s) is initiated by setting Self Reception Request bit (SRR) in conjunction with the selected Message Buffer bits (STB3, STB2, STB1) in the CAN Controller Command register (CANCMR). Local self test The Local Self-Test perfectly fits for single node tests. In this case an acknowledge from other nodes is not needed. As shown in the Figure below, a CAN transceiver with an appropriate CAN bus termination has to be connected to the LPC17xx. The CAN Controller has to be put into the 'Self Test Mode' by setting the STM bit in the CAN Controller Mode register (CANMOD). Hint: Setting the Self Test Mode bit (STM) is possible only when the CAN Controller is in Reset Mode. TX Buffer TX Buffer TX Buffer LPC17xx Transceiver RX Buffer Fig 56. Local self test (high-speed CAN Bus example) A message transmission is initiated by setting Self Reception Request bit (SRR) in conjunction with the selected Message Buffer(s) (STB3, STB2, STB1). UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 346 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 6. Memory map of the CAN block The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: Table 313. Memory map of the CAN block Address Range Used for 0x4003 8000 - 0x4003 87FF 0x4003 C000 - 0x4003 C017 0x4004 0000 - 0x4004 000B 0x4004 4000 - 0x4004 405F 0x4004 8000 - 0x4004 805F 0x400F C110 - 0x400F C114 Acceptance Filter RAM. Acceptance Filter Registers. Central CAN Registers. CAN Controller 1 Registers. CAN Controller 2 Registers. CAN Wake and Sleep Registers. 7. CAN controller registers CAN block implements the registers shown in Table 16–314 and Table 16–315. More detailed descriptions follow. Table 314. CAN acceptance filter and central CAN registers Name Description Access Reset Value Address AFMR SFF_sa SFF_GRP_sa EFF_sa EFF_GRP_sa ENDofTable LUTerrAd LUTerr CANTxSR CANRxSR CANMSR Acceptance Filter Register Standard Frame Individual Start Address Register Standard Frame Group Start Address Register Extended Frame Start Address Register Extended Frame Group Start Address Register End of AF Tables register LUT Error Address register LUT Error Register CAN Central Transmit Status Register CAN Central Receive Status Register CAN Central Miscellaneous Register R/W R/W R/W R/W R/W R/W RO RO RO RO RO 1 0 0 0 0 0 0 0 0x0003 0300 0 0 0x4003 C000 0x4003 C004 0x4003 C008 0x4003 C00C 0x4003 C010 0x4003 C014 0x4003 C018 0x4003 C01C 0x4004 0000 0x4004 0004 0x4004 0008 Table 315. CAN1 and CAN2 controller register map Generic Description Name Access Reset value CAN1 & 2 Register Name & Address MOD CMR GSR ICR IER Controls the operating mode of the CAN Controller. Command bits that affect the state of the CAN Controller Global Controller Status and Error Counters R/W WO RO[1] 1 0 0x3C 0 0 CAN1MOD - 0x4004 4000 CAN2MOD - 0x4004 8000 CAN1CMR - 0x4004 4004 CAN2CMR - 0x4004 8004 CAN1GSR - 0x4004 4008 CAN2GSR - 0x4004 8008 CAN1ICR - 0x4004 400C CAN2ICR - 0x4004 800C CAN1IER - 0x4004 4010 CAN2IER - 0x4004 8010 Interrupt status, Arbitration Lost Capture, Error Code Capture RO Interrupt Enable R/W UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 347 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 315. CAN1 and CAN2 controller register map Generic Description Name Access Reset value CAN1 & 2 Register Name & Address BTR EWL SR RFS RID RDA RDB TFI1 TID1 TDA1 TDB1 TFI2 TID2 TDA2 TDB2 TFI3 TID3 TDA3 TDB3 Bus Timing Error Warning Limit Status Register Receive frame status Received Identifier Received data bytes 1-4 Received data bytes 5-8 Transmit frame info (Tx Buffer 1) Transmit Identifier (Tx Buffer 1) Transmit data bytes 1-4 (Tx Buffer 1) Transmit data bytes 5-8 (Tx Buffer 1) Transmit frame info (Tx Buffer 2) Transmit Identifier (Tx Buffer 2) Transmit data bytes 1-4 (Tx Buffer 2) Transmit data bytes 5-8 (Tx Buffer 2) Transmit frame info (Tx Buffer 3) Transmit Identifier (Tx Buffer 3) Transmit data bytes 1-4 (Tx Buffer 3) Transmit data bytes 5-8 (Tx Buffer 3) R/W[2] R/W[2] RO R/W[2] R/W[2] R/W[2] R/W[2] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x1C0000 0x60 CAN1BTR - 0x4004 4014 CAN2BTR - 0x4004 8014 CAN1EWL - 0x4004 4018 CAN2EWL - 0x4004 8018 0x3C3C3C CAN1SR - 0x4004 401C CAN2SR - 0x4004 801C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN1RFS - 0x4004 4020 CAN2RFS - 0x4004 8020 CAN1RID - 0x4004 4024 CAN2RID - 0x4004 8024 CAN1RDA - 0x4004 4028 CAN2RDA - 0x4004 8028 CAN1RDB - 0x4004 402C CAN2RDB - 0x4004 802C CAN1TFI1 - 0x4004 4030 CAN2TFI1 - 0x4004 8030 CAN1TID1 - 0x4004 4034 CAN2TID1 - 0x4004 8034 CAN1TDA1 - 0x4004 4038 CAN2TDA1 - 0x4004 8038 CAN1TDB1- 0x4004 403C CAN2TDB1 - 0x4004 803C CAN1TFI2 - 0x4004 4040 CAN2TFI2 - 0x4004 8040 CAN1TID2 - 0x4004 4044 CAN2TID2 - 0x4004 8044 CAN1TDA2 - 0x4004 4048 CAN2TDA2 - 0x4004 8048 CAN1TDB2 - 0x4004 404C CAN2TDB2 - 0x4004 804C CAN1TFI3 - 0x4004 4050 CAN2TFI3 - 0x4004 8050 CAN1TID3 - 0x4004 4054 CAN2TID3 - 0x4004 8054 CAN1TDA3 - 0x4004 4058 CAN2TDA3 - 0x4004 8058 CAN1TDB3 - 0x4004 405C CAN2TDB3 - 0x4004 805C [1] [2] The error counters can only be written when RM in CANMOD is 1. These registers can only be written when RM in CANMOD is 1. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 348 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 The internal registers of each CAN Controller appear to the CPU as on-chip memory mapped peripheral registers. Because the CAN Controller can operate in different modes (Operating/Reset, see also Section 16–7.1 “CAN Mode register (CAN1MOD 0x4004 4000, CAN2MOD - 0x4004 8000)”), one has to distinguish between different internal address definitions. Note that write access to some registers is only allowed in Reset Mode. Table 316. CAN1 and CAN2 controller register summary Generic Name Operating Mode Read Write Reset Mode Read Write MOD CMR GSR ICR IER BTR EWL SR RFS RID RDA RDB TFI1 TID1 TDA1 TDB1 Mode 0x00 Global Status and Error Counters Interrupt and Capture Interrupt Enable Bus Timing Error Warning Limit Status Rx Info and Index Rx Identifier Rx Data Rx Info and Index Tx Info1 Tx Identifier Tx Data Tx Data Mode Command Interrupt Enable Tx Info Tx Identifier Tx Data Tx Data Mode 0x00 Global Status and Error Counters Interrupt and Capture Interrupt Enable Bus Timing Error Warning Limit Status Rx Info and Index Rx Identifier Rx Data Rx Info and Index Tx Info Tx Identifier Tx Data Tx Data Mode Command Error Counters only Interrupt Enable Bus Timing Error Warning Limit Rx Info and Index Rx Identifier Rx Data Rx Info and Index Tx Info Tx Identifier Tx Data Tx Data Table 317. CAN Wake and Sleep registers Name Description Access Reset Value Address CANSLEEPCLR Allows clearing the current CAN channel sleep state as well as R/W reading that state. R/W 0 0 0x400F C110 0x400F C114 CANWAKEFLAGS Allows reading the wake-up state of the CAN channels. In the following register tables, the column “Reset Value” shows how a hardware reset affects each bit or field, while the column “RM Set” indicates how each bit or field is affected if software sets the RM bit, or RM is set because of a Bus-Off condition. Note that while hardware reset sets RM, in this case the setting noted in the “Reset Value” column prevails over that shown in the “RM Set” column, in the few bits where they differ. In both columns, X indicates the bit or field is unchanged. 7.1 CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD 0x4004 8000) The contents of the Mode Register are used to change the behavior of the CAN Controller. Bits may be set or reset by the CPU that uses the Mode Register as a read/write memory. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 349 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 318. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description Bit Symbol Value Function Reset RM Value Set 0 RM[1][6] 0 (normal) 1 (reset) Reset Mode. The CAN Controller is in the Operating Mode, and certain registers can not be written. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. Listen Only Mode. 0 (normal) 1 (listen only) The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in “error passive” mode. This mode is intended for software bit rate detection and “hot plugging”. Self Test Mode. 0 (normal) 1 (self test) A transmitted message must be acknowledged to be considered successful. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR. 1 1 1 LOM[3][2] [6] 0 x 2 STM[3][6] 0 x 3 TPM[4] 0 (CAN ID) 1 (local prio) Transmit Priority Mode. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer. Sleep Mode. 0 (wake-up) 1 (sleep) Normal operation. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 16–8.2 on page 369. Receive Polarity Mode. 0 (low active) 1 (high active) RD input is active Low (dominant bit = 0). RD input is active High (dominant bit = 1) -- reverse polarity. Reserved, user software should not write ones to reserved bits. Test Mode. 0 (disabled) 1 (enabled) Normal operation. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 x 4 SM[5] 0 0 5 RPM 0 x 6 7 TM - 0 0 0 x 31:8 - NA [1] During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit is set '0' the CAN Controller will wait for: - one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiated reset. - 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the Bus-On mode. [2] This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can be used e.g. for software driven bit rate detection and "hot plugging". © NXP B.V. 2010. All rights reserved. UM10360_1 User manual Rev. 01 — 4 January 2010 350 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [3] [4] [5] A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously. Transmit Priority Mode is explained in more detail in Section 16–5.3 “Transmit Buffers (TXB)”. The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits (Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only when Bus-Free is detected again. The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation. [6] 7.2 CAN Command Register (CAN1CMR - 0x4004 x004, CAN2CMR 0x4004 8004) Writing to this write-only register initiates an action within the transfer layer of the CAN Controller. Reading this register yields zeroes. At least one internal clock cycle is needed for processing between two commands. Table 319. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description Bit Symbol Value Function Reset RM Value Set 0[1][2] TR 0 (absent) 1 (present) Transmission Request. No transmission request. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 16–5.3 “Transmit Buffers (TXB)”) Abort Transmission. 0 (no action) 1 (present) Do not abort the transmission. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. Release Receive Buffer. 0 (no action) 1 (released) Do not release the receive buffer. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). Clear Data Overrun. 0 (no action) 1 (clear) Do not clear the data overrun bit. The Data Overrun bit in Status Register(s) is cleared. Self Reception Request. 0 (absent) 1 (present) No self reception request. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter. 0 0 1[1][3] AT 0 0 2[4] RRB 0 0 3[5] CDO 0 0 4[1][6] SRR 0 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 351 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 319. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description Bit Symbol Value Function Reset RM Value Set 5 STB1 0 (not selected) 1 (selected) Select Tx Buffer 1. Tx Buffer 1 is not selected for transmission. Tx Buffer 1 is selected for transmission. Select Tx Buffer 2. 0 (not selected) 1 (selected) Tx Buffer 2 is not selected for transmission. Tx Buffer 2 is selected for transmission. Select Tx Buffer 3. 0 (not selected) 1 (selected) Tx Buffer 3 is not selected for transmission. Tx Buffer 3 is selected for transmission. Reserved, user software should not write ones to reserved bits. 0 0 6 STB2 0 0 7 STB3 0 0 31:8 [1] - NA - Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in case of an error or arbitration lost (single shot transmission). - Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature. No re-transmission will be performed in case of an error or arbitration lost. - Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically. - Setting TR and SRR simultaneously will ignore the set SRR bit. If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the bits. The requested transmission may only be cancelled by setting the Abort Transmission bit. The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated. After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'. This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit is reset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated. This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Overrun Status bit is set no further Data Overrun Interrupt is generated. Upon Self Reception Request, a message is transmitted and simultaneously received if the Acceptance Filter is set to the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in Section 16–7.1 “CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)”). [2] [3] [4] [5] [6] 7.3 CAN Global Status Register (CAN1GSR - 0x4004 x008, CAN2GSR 0x4004 8008) The content of the Global Status Register reflects the status of the CAN Controller. This register is read-only, except that the Error Counters can be written when the RM bit in the CANMOD register is 1. Bits not listed read as 0 and should be written as 0. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 352 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 320. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit description Bit Symbol Value Function Reset RM Value Set 0 RBS[1] 0 (empty) 1 (full) Receive Buffer Status. No message is available. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. Data Overrun Status. 0 (absent) 1 (overrun) No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). Transmit Buffer Status. 0 (locked) At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. Transmit Complete Status. 0 (incomplete) 1 (complete) At least one requested transmission has not been successfully completed yet. All requested transmission(s) has (have) been successfully completed. Receive Status. 0 (idle) 1 (receive) The CAN controller is idle. The CAN controller is receiving a message. Transmit Status. 0 (idle) 1 (transmit) The CAN controller is idle. The CAN controller is sending a message. Error Status. 0 (ok) 1 (error) Both error counters are below the Error Warning Limit. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. Bus Status. 0 (Bus-On) 1 (Bus-Off) The CAN Controller is involved in bus activities The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. The current value of the Rx Error Counter (an 8-bit value). The current value of the Tx Error Counter (an 8-bit value). 0 0 1 DOS[2] 0 0 2 TBS 1 1 1 (released) 3 TCS[3] 1 x 4 RS[4] 1 0 5 TS[4] 1 0 6 ES[5] 0 0 7 BS[6] 0 0 15:8 - - NA 0 0 X X 23:16 RXERR 31:24 TXERR [1] After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared. © NXP B.V. 2010. All rights reserved. UM10360_1 User manual Rev. 01 — 4 January 2010 353 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [2] If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 16–7.7 “CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)”. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. [3] [4] [5] [6] RX error counter The RX Error Counter Register, which is part of the Status Register, reflects the current value of the Receive Error Counter. After hardware reset this register is initialized to 0. In Operating Mode this register appears to the CPU as a read-only memory. A write access to this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error Counter is initialized to 0. As long as Bus Off is valid, writing to this register has no effect.The Rx Error Counter is determined as follows: RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x00010000 Note that a CPU-forced content change of the RX Error Counter is possible only if the Reset Mode was entered previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again. TX error counter The TX Error Counter Register, which is part of the Status Register, reflects the current value of the Transmit Error Counter. In Operating Mode this register appears to the CPU as a read-only memory. After hardware reset this register is initialized to 0. A write access to this register is possible only in Reset Mode. If a bus-off event occurs, the TX Error Counter is initialized to 127 to count the minimum protocol-defined time (128 occurrences of the Bus-Free signal). Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. If Bus Off is active, a write access to TXERR in the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence of 11 consecutive recessive bits (bus free) after clearing of Reset Mode. The Tx error counter is determined as follows: TX Error Counter = (CANxGSR AND 0xFF000000) / 0x01000000 Writing 255 to TXERR allows initiation of a CPU-driven Bus Off event. Note that a CPU-forced content change of the TX Error Counter is possible only if the Reset Mode was entered previously. An Error or Bus Status change (Status Register), an Error UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 354 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Warning, or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX Counter content is interpreted and the Bus Off event is performed in the same way as if it was forced by a bus error event. That means, that the Reset Mode is entered again, the TX Error Counter is initialized to 127, the RX Counter is cleared, and all concerned Status and Interrupt Register bits are set. Clearing of Reset Mode now will perform the protocol defined Bus Off recovery sequence (waiting for 128 occurrences of the Bus-Free signal). If the Reset Mode is entered again before the end of Bus Off recovery (TXERR>0), Bus Off keeps active and TXERR is frozen. 7.4 CAN Interrupt and Capture Register (CAN1ICR - 0x4004 400C, CAN2ICR - 0x4004 800C) Bits in this register indicate information about events on the CAN bus. This register is read-only. The Interrupt flags of the Interrupt and Capture Register allow the identification of an interrupt source. When one or more bits are set, a CAN interrupt will be indicated to the CPU. After this register is read from the CPU all interrupt bits are reset except of the Receive Interrupt bit. The Interrupt Register appears to the CPU as a read-only memory. Bits 1 through 10 clear when they are read. Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur. Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either of these bytes is captured, its value will remain the same until it is read, at which time it is released to capture a new value. The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read from CANxICR, regardless of whether part or all of the register is read. This means that software should always read CANxICR as a word, and process and deal with all bits of the register as appropriate for the application. Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value Function Reset RM Value Set 0 RI[1] 0 (reset) 1 (set) 0 (reset) 1 (set) 0 (reset) 1 (set) 0 (reset) 1 (set) 0 (reset) 1 (set) Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. 0 0 1 TI1 Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 0 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. Error Warning Interrupt. This bit is set on every change (set or clear) of either the 0 Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change. Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 0 to 1 and the DOIE bit in CANxIER is 1. Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity 0 is detected and the WUIE bit in CANxIER is 1. 0 2 EI X 3 4 DOI WUI[2] 0 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 355 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value Function Reset RM Value Set 5 EPI 0 (reset) 1 (set) Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again. 0 0 6 ALI 0 (reset) 1 (set) 0 (reset) 1 (set) 0 (reset) 1 (set) Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver. Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus. ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register. 0 0 7 8 BEI IDI 0 0 X 0 9 TI2 0 (reset) 1 (set) 0 (reset) 1 (set) - Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 0 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1. Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 0 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1. Reserved, user software should not write ones to reserved bits. 0 0 10 TI3 0 15:11 - 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 356 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value Function Reset RM Value Set 20:16 ERRBIT 4:0[3] 00011 00010 00110 00100 00101 00111 01111 01110 01100 01101 01001 01011 01010 01000 11000 11001 11011 11010 10010 10001 10110 10011 10111 11100 21 ERRDIR 0 1 23:22 ERRC1:0 00 01 10 11 Error Code Capture: when the CAN controller detects a bus error, the location of 0 the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: Start of Frame ID28 ... ID21 ID20 ... ID18 SRTR Bit IDE bit ID17 ... 13 ID12 ... ID5 ID4 ... ID0 RTR Bit Reserved Bit 1 Reserved Bit 0 Data Length Code Data Field CRC Sequence CRC Delimiter Acknowledge Slot Acknowledge Delimiter End of Frame Intermission Active Error Flag Passive Error Flag Tolerate Dominant Bits Error Delimiter Overload flag When the CAN controller detects a bus error, the direction of the current bit is captured in this bit. Error occurred during transmitting. Error occurred during receiving. When the CAN controller detects a bus error, the type of error is captured in this 0 field: Bit error Form error Stuff error Other error 0 X X X UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 357 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 321. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description Bit Symbol Value Function Reset RM Value Set 31:24 ALCBIT[4] - Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. arbitration lost in the first bit (MS) of identifier arbitration lost in SRTS bit (RTR bit for standard frame messages) arbitration lost in IDE bit arbitration lost in 12th bit of identifier (extended frame only) arbitration lost in last bit of identifier (extended frame only) arbitration lost in RTR bit (extended frame only) [1] 0 X 00 ... 11 12 13 ... 30 31 The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command “Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again. [2] [3] [4] 7.5 CAN Interrupt Enable Register (CAN1IER - 0x4004 4010, CAN2IER 0x4004 8010) This read/write register controls whether various events on the CAN controller will result in an interrupt or not. Bits 10:0 in this register correspond 1-to-1 with bits 10:0 in the CANxICR register. If a bit in the CANxIER register is 0 the corresponding interrupt is disabled; if a bit in the CANxIER register is 1 the corresponding source is enabled to trigger an interrupt. Table 322. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description Bit Symbol Function Reset RM Value Set 0 1 RIE TIE1 Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. 0 0 X X 2 EIE 0 X UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 358 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 322. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description Bit Symbol Function Reset RM Value Set 3 4 5 6 7 8 9 DOIE WUIE EPIE ALIE BEIE IDIE TIE2 Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the 0 CAN Controller requests the respective interrupt. Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. 0 0 0 X X X X X X X Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the 0 respective interrupt. ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 0 10 TIE3 0 X 31:11 - NA 7.6 CAN Bus Timing Register (CAN1BTR - 0x4004 4014, CAN2BTR 0x4004 8014) This register controls how various CAN timings are derived from the APB clock. It defines the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW). Furthermore, it defines the length of the bit period, the location of the sample point and the number of samples to be taken at each sample point. It can be read at any time but can only be written if the RM bit in CANmod is 1. Table 323. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description Bit Symbol Value Function Reset RM Value Set 9:0 BRP Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the 0 CAN clock. Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. The Synchronization Jump Width is (this value plus one) CAN clocks. The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. 0 1100 X 13:10 15:14 SJW 19:16 TESG1 22:20 TESG2 X X X The delay from the sample point to the next nominal sync point is (this value plus one) 001 CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 359 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 323. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description Bit Symbol Value Function Reset RM Value Set 23 SAM 0 1 Sampling The bus is sampled once (recommended for high speed buses) The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 0 X 31:24 - Baud rate prescaler The period of the CAN system clock tSCL is programmable and determines the individual bit timing. The CAN system clock tSCL is calculated using the following equation: (5) t SCL = t CANsuppliedCLK × ( BRP + 1 ) Synchronization jump width To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width tSJW defines the maximum number of clock cycles a certain bit period may be shortened or lengthened by one re-synchronization: (6) t SJW = t SCL × ( SJW + 1 ) Time segment 1 and time segment 2 Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point: (7) t SYNCSEG = t SCL (8) t TSEG1 = t SCL × ( TSEG1 + 1 ) (9) t TSEG2 = t SCL × ( TSEG2 + 1 ) 7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018) This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time but can only be written if the RM bit in CANmod is 1. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 360 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 324. CAN Error Warning Limit register (CAN1EWL - address 0x4004 4018, CAN2EWL - address 0x4004 8018) bit description Bit Symbol Function Reset Value RM Set 7:0 31:8 EWL - During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 9610 = 0x60 X NA Note that a content change of the Error Warning Limit Register is possible only if the Reset Mode was entered previously. An Error Status change (Status Register) and an Error Warning Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again. 7.8 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR 0x4004 801C) This read-only register contains three status bytes in which the bits not related to transmission are identical to the corresponding bits in the Global Status Register, while those relating to transmission reflect the status of each of the 3 Tx Buffers. Table 325. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description Bit Symbol Value Function Reset RM Value Set 0 1 2 RBS DOS TBS1[1] 0(locked) Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. Transmit Buffer Status 1. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. Transmission Complete Status. 0(incomplete) 1(complete) The previously requested transmission for Tx Buffer 1 is not complete. The previously requested transmission for Tx Buffer 1 has been successfully completed. Receive Status. This bit is identical to the RS bit in the GSR. Transmit Status 1. 0(idle) 1(transmit) There is no transmission from Tx Buffer 1. The CAN Controller is transmitting a message from Tx Buffer 1. Error Status. This bit is identical to the ES bit in the CANxGSR. Bus Status. This bit is identical to the BS bit in the CANxGSR. Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0 1 0 0 1 1(released) 3 TCS1[2] 1 x 4 5 RS TS1 1 1 0 0 6 7 8 9 ES BS RBS DOS 0 0 0 0 0 0 0 0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 361 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 325. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description Bit Symbol Value Function Reset RM Value Set 10 TBS2[1] 0(locked) Transmit Buffer Status 2. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. Transmission Complete Status. 0(incomplete) 1(complete) The previously requested transmission for Tx Buffer 2 is not complete. The previously requested transmission for Tx Buffer 2 has been successfully completed. Receive Status. This bit is identical to the RS bit in the GSR. Transmit Status 2. 0(idle) 1(transmit) There is no transmission from Tx Buffer 2. The CAN Controller is transmitting a message from Tx Buffer 2. Error Status. This bit is identical to the ES bit in the CANxGSR. Bus Status. This bit is identical to the BS bit in the CANxGSR. Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. Transmit Buffer Status 3. 0(locked) Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. Transmission Complete Status. 0(incomplete) 1(complete) The previously requested transmission for Tx Buffer 3 is not complete. The previously requested transmission for Tx Buffer 3 has been successfully completed. Receive Status. This bit is identical to the RS bit in the GSR. Transmit Status 3. 0(idle) 1(transmit) There is no transmission from Tx Buffer 3. The CAN Controller is transmitting a message from Tx Buffer 3. Error Status. This bit is identical to the ES bit in the CANxGSR. Bus Status. This bit is identical to the BS bit in the CANxGSR. Reserved, the value read from a reserved bit is not defined. 1 1 1(released) 11 TCS2[2] 1 x 12 13 RS TS2 1 1 0 0 14 15 16 17 18 ES BS RBS DOS TBS3[1] 0 0 0 0 1 0 0 0 0 1 1(released) 19 TCS3[2] 1 x 20 21 RS TS3 1 1 0 0 22 23 ES BS 0 0 NA 0 0 31:24 [1] [2] If the CPU tries to write to this Transmit Buffer when the Transmit Buffer Status bit is '0' (locked), the written byte is not accepted and is lost without this being signalled. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 362 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 7.9 CAN Receive Frame Status register (CAN1RFS - 0x4004 4020, CAN2RFS - 0x4004 8020) This register defines the characteristics of the current received message. It is read-only in normal operation but can be written for testing purposes if the RM bit in CANxMOD is 1. Table 326. CAN Receive Frame Status register (CAN1RFS - address 0x4004 4020, CAN2RFS - address 0x4004 8020) bit description Bit Symbol Function Reset RM Value Set 9:0 ID Index If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry 0 at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 16–17 “Examples of acceptance filter tables and ID index values” on page 391 for examples of ID Index values. If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA X 10 BP X 15:11 19:16 DLC The field contains the Data Length Code (DLC) field of the current received message. When 0 RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. X 29:20 30 RTR Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier. NA 0 X 31 FF A 0 in this bit indicates that the current received message included an 11-bit Identifier, while 0 a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below. X 7.9.1 ID index field The ID Index is a 10-bit field in the Info Register that contains the table position of the ID Look-up Table if the currently received message was accepted. The software can use this index to simplify message transfers from the Receive Buffer into the Shared Message Memory. Whenever bit 10 (BP) of the ID Index in the CANRFS register is 1, the current CAN message was received in acceptance filter bypass mode. 7.10 CAN Receive Identifier register (CAN1RID - 0x4004 4024, CAN2RID 0x4004 8024) This register contains the Identifier field of the current received message. It is read-only in normal operation but can be written for testing purposes if the RM bit in CANmod is 1. It has two different formats depending on the FF bit in CANRFS. See Table 16–314 for details on specific CAN channel register address. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 363 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 327. CAN Receive Identifier register (CAN1RID - address 0x4004 4024, CAN2RID - address 0x4004 8024) bit description Bit Symbol Function Reset Value RM Set 10:0 ID The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they’re called ID29-18. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA X 31:11 - Table 328. RX Identifier register when FF = 1 Bit Symbol Function Reset Value RM Set 28:0 ID The 29-bit Identifier field of the current received message. In CAN 2.0B these bits 0 are called ID29-0. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA X 31:29 - 7.11 CAN Receive Data register A (CAN1RDA - 0x4004 4028, CAN2RDA 0x4004 8028) This register contains the first 1-4 Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 16–314 for details on specific CAN channel register address. Table 329. CAN Receive Data register A (CAN1RDA - address 0x4004 4028, CAN2RDA - address 0x4004 8028) bit description Bit Symbol Function Reset Value RM Set 7:0 15:8 Data 1 Data 2 If the DLC field in CANRFS ≥ 0001, this contains the first Data byte of the current 0 received message. If the DLC field in CANRFS ≥ 0010, this contains the first Data byte of the current 0 received message. If the DLC field in CANRFS ≥ 0011, this contains the first Data byte of the current 0 received message. If the DLC field in CANRFS ≥ 0100, this contains the first Data byte of the current 0 received message. X X X X 23:16 Data 3 31:24 Data 4 7.12 CAN Receive Data register B (CAN1RDB - 0x4004 402C, CAN2RDB 0x4004 802C) This register contains the 5th through 8th Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 16–314 for details on specific CAN channel register address. Table 330. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit description Bit Symbol Function Reset Value RM Set 7:0 Data 5 If the DLC field in CANRFS ≥ 0101, this contains the first Data byte of the current 0 received message. X UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 364 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 330. CAN Receive Data register B (CAN1RDB - address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit description Bit Symbol Function Reset Value RM Set 15:8 Data 6 If the DLC field in CANRFS ≥ 0110, this contains the first Data byte of the current 0 received message. If the DLC field in CANRFS ≥ 0111, this contains the first Data byte of the current 0 received message. If the DLC field in CANRFS ≥ 1000, this contains the first Data byte of the current 0 received message. X X X 23:16 Data 7 31:24 Data 8 7.13 CAN Transmit Frame Information register (CAN1TFI[1/2/3] 0x4004 40[30/ 40/50], CAN2TFI[1/2/3] - 0x4004 80[30/40/50]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the format of the next transmit message for that Tx buffer. Bits not listed read as 0 and should be written as 0. The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be set to the values expected in the Receive Buffer for an easy comparison, when using the Self Reception facility (self test), otherwise they are not defined. The CAN Controller consist of three Transmit Buffers. Each of them has a length of 4 words and is able to store one complete CAN message as shown in Figure 16–53. The buffer layout is subdivided into Descriptor and Data Field where the first word of the Descriptor Field includes the TX Frame Info that describes the Frame Format, the Data Length and whether it is a Remote or Data Frame. In addition, a TX Priority register allows the definition of a certain priority for each transmit message. Depending on the chosen Frame Format, an 11-bit identifier for Standard Frame Format (SFF) or an 29-bit identifier for Extended Frame Format (EFF) follows. Note that unused bits in the TID field have to be defined as 0. The Data Field in TDA and TDB contains up to eight data bytes. Table 331. CAN Transmit Frame Information register (CAN1TFI[1/2/3] - address 0x4004 40[30/40/50], CAN2TFI[1/2/3] 0x4004 80[30/40/50]) bit description Bit Symbol Function Reset RM Value Set 7:0 PRIO If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first. Reserved. Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes 0 0 x 15:8 - 19:16 DLC X 29:20 30 RTR Reserved. This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes. 0 0 X 31 FF If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame 0 format), while if it’s 1, the message will be sent with a 29-bit Identifier (extended frame format). X UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 365 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Automatic transmit priority detection To allow uninterrupted streams of transmit messages, the CAN Controller provides Automatic Transmit Priority Detection for all Transmit Buffers. Depending on the selected Transmit Priority Mode, internal prioritization is based on the CAN Identifier or a user defined "local priority". If more than one message is enabled for transmission (TR=1) the internal transmit message queue is organized such as that the transmit buffer with the lowest CAN Identifier (TID) or the lowest "local priority" (TX Priority) wins the prioritization and is sent first. The result of the internal scheduling process is taken into account short before a new CAN message is sent on the bus. This is also true after the occurrence of a transmission error and right before a re-transmission. Tx DLC The number of bytes in the Data Field of a message is coded with the Data Length Code (DLC). At the start of a Remote Frame transmission the DLC is not considered due to the RTR bit being '1 ' (remote). This forces the number of transmitted/received data bytes to be 0. Nevertheless, the DLC must be specified correctly to avoid bus errors, if two CAN Controllers start a Remote Frame transmission with the same identifier simultaneously. For reasons of compatibility no DLC > 8 should be used. If a value greater than 8 is selected, 8 bytes are transmitted in the data frame with the Data Length Code specified in DLC. The range of the Data Byte Count is 0 to 8 bytes and is coded as follows: (10) D ataByteCount = DLC 7.14 CAN Transmit Identifier register (CAN1TID[1/2/3] 0x4004 40[34/44/54], CAN2TID[1/2/3] - 0x4004 80[34/44/54]) When the corresponding TBS bit in CANxSR is 1, software can write to one of these registers to define the Identifier field of the next transmit message. Bits not listed read as 0 and should be written as 0. The register assumes two different formats depending on the FF bit in CANTFI. In Standard Frame Format messages, the CAN Identifier consists of 11 bits (ID.28 to ID.18), and in Extended Frame Format messages, the CAN identifier consists of 29 bits (ID.28 to ID.0). ID.28 is the most significant bit, and it is transmitted first on the bus during the arbitration process. The Identifier acts as the message's name, used in a receiver for acceptance filtering, and also determines the bus access priority during the arbitration process. Table 332. CAN Transfer Identifier register (CAN1TID[1/2/3] - address 0x4004 40[34/44/54], CAN2TID[1/2/3] - address 0x4004 80[34/44/54]) bit description Bit Symbol Function Reset Value RM Set 10:0 ID The 11-bit Identifier to be sent in the next transmit message. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA X 31:11 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 366 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 333. Transfer Identifier register when FF = 1 Bit Symbol Function Reset Value RM Set 28:0 ID The 29-bit Identifier to be sent in the next transmit message. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA X 31:29 - 7.15 CAN Transmit Data register A (CAN1TDA[1/2/3] - 0x4004 40[38/48/58], CAN2TDA[1/2/3] - 0x4004 80[38/48/58]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the first 1 - 4 data bytes of the next transmit message. The Data Length Code defines the number of transferred data bytes. The first bit transmitted is the most significant bit of TX Data Byte 1. Table 334. CAN Transmit Data register A (CAN1TDA[1/2/3] - address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - address 0x4004 80[38/48/58]) bit description Bit Symbol Function Reset Value RM Set 7:0 15;8 Data 1 Data 2 If RTR = 0 and DLC ≥ 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message. If RTR = 0 and DLC ≥ 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message. If RTR = 0 and DLC ≥ 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message. If RTR = 0 and DLC ≥ 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message. 0 0 0 0 X X X X 23:16 Data 3 31:24 Data 4 7.16 CAN Transmit Data register B (CAN1TDB[1/2/3] - 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0x4004 80[3C/4C/5C]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the 5th through 8th data bytes of the next transmit message. The Data Length Code defines the number of transferred data bytes. The first bit transmitted is the most significant bit of TX Data Byte 1. Table 335. CAN Transmit Data register B (CAN1TDB[1/2/3] - address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - address 0x4004 80[3C/4C/5C]) bit description Bit Symbol Function Reset Value RM Set 7:0 15;8 Data 5 Data 6 If RTR = 0 and DLC ≥ 0101 in the corresponding CANTFI, this byte is sent as the 0 5th Data byte of the next transmit message. If RTR = 0 and DLC ≥ 0110 in the corresponding CANTFI, this byte is sent as the 0 6th Data byte of the next transmit message. If RTR = 0 and DLC ≥ 0111 in the corresponding CANTFI, this byte is sent as the 0 7th Data byte of the next transmit message. If RTR = 0 and DLC ≥ 1000 in the corresponding CANTFI, this byte is sent as the 0 8th Data byte of the next transmit message. X X X X 23:16 Data 7 31:24 Data 8 7.17 CAN Sleep Clear register (CANSLEEPCLR - 0x400F C110) This register provides the current sleep state of the two CAN channels and provides a means to restore the clocks to that channel following wake-up. Refer to Section 16–8.2 “Sleep mode” for more information on the CAN sleep feature. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 367 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Table 336. CAN Sleep Clear register (CANSLEEPCLR - address 0x400F C110) bit description Bit Symbol Function Reset Value 0 1 CAN1SLEEP Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. 0 2 CAN2SLEEP Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. 0 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a NA reserved bit is not defined. 7.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114) This register provides the wake-up status for the two CAN channels and allows clearing wake-up events. Refer to Section 16–8.2 “Sleep mode” for more information on the CAN sleep feature. Table 337. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description Bit Symbol Function Reset Value 0 1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA CAN1WAKE Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit. 0 2 CAN2WAKE Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit. 0 31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 8. CAN controller operation 8.1 Error handling The CAN Controllers count and handle transmit and receive errors as specified in CAN Spec 2.0B. The Transmit and Receive Error Counters are incriminated for each detected error and are decremented when operation is error-free. If the Transmit Error counter contains 255 and another error occurs, the CAN Controller is forced into a state called Bus-Off. In this state, the following register bits are set: BS in CANxSR, BEI and EI in CANxIR if these are enabled, and RM in CANxMOD. RM resets and disables much of the CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit Error Counter will count down 128 occurrences of the Bus Free condition (11 consecutive UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 368 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 recessive bits). Software can monitor this countdown by reading the Tx Error Counter. When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, and sets EI in CANxSR if EIE in IER is 1. The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to the Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANxSR) is 1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software clears RM in CANxMOD thereafter, only one Bus Free condition (11 consecutive recessive bits) is needed before operation resumes. 8.2 Sleep mode The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN Interrupt Enable register to enable an interrupt on any wake-up condition. The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller that wakes up in response to bus activity is not able to receive an initial message until after it detects Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is active when software sets SM, the wake-up is immediate. Upon wake-up, software needs to do the following things: 1. Write a 1 to the relevant bit(s) in the CANSLEEPCLR register. 2. Write a 0 to the SM bit in the CAN1MOD and/or CAN2MOD register. 3. Write a 1 to the relevant bit(s) in the CANWAKEFLAGS register. Failure to perform this step will prevent subsequent entry into Power-down mode. If the LPC17xx is in Deep Sleep or Power-down mode, CAN activity will wake up the device if the CAN activity interrupt is enabled. See Section 4–8 “Power control”. 8.3 Interrupts Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”. The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each Receive and Transmit interrupt request from each controller is assigned its own channel in the NVIC, and can have its own interrupt service routine. The “other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr condition, are ORed into one NVIC channel. 8.4 Transmit priority If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for the right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1, they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have the same smallest value, the lowest-numbered buffer sends first. The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it sends each message. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 369 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 9. Centralized CAN registers For easy and fast access, all CAN Controller Status bits from each CAN Controller Status register are bundled together. Each defined byte of the following registers contains one particular status bit from each of the CAN controllers, in its LS bits. All Status registers are read-only and allow byte, half word and word access. 9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000) Table 338. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description Bit Symbol Description Reset Value 0 1 7:2 8 9 TS1 TS2 TBS1 TBS2 When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR). When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR). When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR). Reserved, the value read from a reserved bit is not defined. 0 0 NA 1 1 NA 1 1 NA 15:10 16 TCS1 17:16 TCS2 31:18 - 9.2 Central Receive Status Register (CANRxSR - 0x4004 0004) Table 339. Central Receive Status Register (CANRxSR - address 0x4004 0004) bit description Bit Symbol Description Reset Value 0 1 7:2 8 9 RS1 RS2 RB1 RB2 When 1, CAN1 is receiving a message (same as RS in CAN1GSR). When 1, CAN2 is receiving a message (same as RS in CAN2GSR). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR). When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR). When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR). Reserved, the value read from a reserved bit is not defined. 0 0 NA 0 0 NA 0 0 NA 15:10 16 DOS1 17:16 DOS2 31:18 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 370 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008) Table 340. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description Bit Symbol Description Reset Value 0 1 7:2 8 9 E1 E2 BS1 BS2 When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the 0 CAN1EWL register (same as ES in CAN1GSR) When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the 0 CAN2EWL register (same as ES in CAN2GSR) Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR). When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR). Reserved, the value read from a reserved bit is not defined. NA 0 0 NA 31:10 - 10. Global acceptance filter This block provides lookup for received Identifiers (called Acceptance Filtering in CAN terminology) for all the CAN Controllers. It includes a 512 × 32 (2 kB) RAM in which software maintains one to five tables of Identifiers. This RAM can contain up to 1024 Standard Identifiers or 512 Extended Identifiers, or a mixture of both types. 11. Acceptance filter modes The Acceptance Filter can be put into different modes by setting the according AccOff, AccBP, and eFCAN bits in the Acceptance Filter Mode Register (Section 16–14.1 “Acceptance Filter Mode Register (AFMR - 0x4003 C000)”). During each mode the access to the Configuration Register and the ID Look-up table is handled differently. Table 341. Acceptance filter modes and access control Acceptance Bit Bit Acceptance filter mode AccOff AccBP filter state ID Look-up table RAM[1] Acceptanc e filter config. registers CAN controller message receive interrupt Off Mode Bypass Mode Operating Mode and FullCAN Mode [1] [2] 1 X 0 0 1 0 reset & halted reset & halted running r/w access from CPU r/w access from CPU read-only from CPU[2] r/w access from CPU r/w access from CPU no messages accepted all messages accepted access from hardware Acceptance acceptance filtering filter only The whole ID Look-up Table RAM is only word accessible. During the Operating Mode of the Acceptance Filter the Look-up Table can be accessed only to disable or enable Messages. A write access to all section configuration registers is only possible during the Acceptance Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 371 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 11.1 Acceptance filter Off mode The Acceptance Filter Off Mode is typically used during initialization. During this mode an unconditional access to all registers and to the Look-up Table RAM is possible. With the Acceptance Filter Off Mode, CAN messages are not accepted and therefore not stored in the Receive Buffers of active CAN Controllers. 11.2 Acceptance filter Bypass mode The Acceptance Filter Bypass Mode can be used for example to change the acceptance filter configuration during a running system, e.g. change of identifiers in the ID-Look-up Table memory. During this re-configuration, software acceptance filtering has to be used. It is recommended to use the ID ready Interrupt (ID Index) and the Receive Interrupt (RI). In this mode all CAN message are accepted and stored in the Receive Buffers of active CAN Controllers. 11.3 Acceptance filter Operating mode The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the Configuration Register is set and the eFCAN = 0. 11.4 FullCAN mode The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the Configuration Register is set and the eFCAN = 1. More details on FullCAN mode are available in Section 16–16 “FullCAN mode”. 12. Sections of the ID look-up table RAM Four 12-bit section configuration registers (SFF_sa, SFF_GRP_sa, EFF_sa, EFF_GRP_sa) are used to define the boundaries of the different identifier sections in the ID-Look-up Table Memory. The fifth 12-bit section configuration register, the End of Table address register (ENDofTable) is used to define the end of all identifier sections. The End of Table address is also used to assign the start address of the section where FullCAN Message Objects, if enabled are stored. Table 342. Section configuration register settings ID-Look up Table Section Register Value Section status FullCAN (Standard Frame Format) Identifier Section Explicit Standard Frame Format Identifier Section Group of Standard Frame Format Identifier Section Explicit Extended Frame Format Identifier Section Group of Extended Frame Format Identifier Section SFF_sa = 0x000 > 0x000 disabled enabled disabled enabled SFF_GRP_sa = SFF_sa > SFF_sa EFF_sa = SFF_GRP_sa disabled > SFF_GRP_sa enabled disabled enabled EFF_GRP_sa = EFF_sa > EFF_sa ENDofTable = EFF_GRP_sa disabled > EFF_GRP_sa enabled UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 372 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 13. ID look-up table RAM The Whole ID Look-up Table RAM is only word accessible. A write access is only possible during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all Acceptance Filter Modes. If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty. If the optional “FullCAN mode” is enabled, the first table contains Standard identifiers for which reception is to be handled in this mode. The next table contains individual Standard Identifiers and the third contains ranges of Standard Identifiers, for which messages are to be received via the CAN Controllers. The tables of FullCAN and individual Standard Identifiers must be arranged in ascending numerical order, one per halfword, two per word. Since each CAN bus has its own address map, each entry also contains the number of the CAN Controller (001-010) to which it applies. 31 15 29 13 26 10 16 0 CONTROLLER # DIS NOT ABLE USED IDENTIFIER Fig 57. Entry in FullCAN and individual standard identifier tables The table of Standard Identifier Ranges contains paired upper and lower (inclusive) bounds, one pair per word. These must also be arranged in ascending numerical order. 31 29 NOT US ED DISABLE 26 LOWER IDENTIFIER BOUND 16 CONTROLLER # DISABLE NOT US ED 10 UPPER IDENTIFIER BOUND 0 CONTROLLER # Fig 58. Entry in standard identifier range table The disable bits in Standard entries provide a means to turn response, to particular CAN Identifiers or ranges of Identifiers, on and off dynamically. When the Acceptance Filter function is enabled, only the disable bits in Acceptance Filter RAM can be changed by software. Response to a range of Standard addresses can be enabled by writing 32 zero bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in RAM. Only the disable bits are actually changed. Disabled entries must maintain the ascending sequence of Identifiers. If Extended (29-bit) Identifiers are used in the application, at least one of the other two tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers and one for ranges of Extended Identifiers. The table of individual Extended Identifiers must be arranged in ascending numerical order. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 373 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 31 29 28 0 CONTROLLER # IDENTIFIER Fig 59. Entry in either extended identifier table The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table. Like the Individual Extended table, the Extended Range must be arranged in ascending numerical order. The first and second (3rd and 4th …) entries in the table are implicitly paired as an inclusive range of Extended addresses, such that any received address that falls in the inclusive range is received (accepted). Software must maintain the table to consist of such word pairs. There is no facility to receive messages to Extended identifiers using the FullCAN method. Five address registers point to the boundaries between the tables in Acceptance Filter RAM: FullCAN Standard addresses, Standard Individual addresses, Standard address ranges, Extended Individual addresses, and Extended address ranges. These tables must be consecutive in memory. The start of each of the latter four tables is implicitly the end of the preceding table. The end of the Extended range table is given in an End of Tables register. If the start address of a table equals the start of the next table or the End Of Tables register, that table is empty. When the Receive side of a CAN controller has received a complete Identifier, it signals the Acceptance Filter of this fact. The Acceptance Filter responds to this signal, and reads the Controller number, the size of the Identifier, and the Identifier itself from the Controller. It then proceeds to search its RAM to determine whether the message should be received or ignored. If FullCAN mode is enabled and the CAN controller signals that the current message contains a Standard identifier, the Acceptance Filter first searches the table of identifiers for which reception is to be done in FullCAN mode. Otherwise, or if the AF doesn’t find a match in the FullCAN table, it searches its individual Identifier table for the size of Identifier signalled by the CAN controller. If it finds an equal match, the AF signals the CAN controller to retain the message, and provides it with an ID Index value to store in its Receive Frame Status register. If the Acceptance Filter does not find a match in the appropriate individual Identifier table, it then searches the Identifier Range table for the size of Identifier signalled by the CAN controller. If the AF finds a match to a range in the table, it similarly signals the CAN controller to retain the message, and provides it with an ID Index value to store in its Receive Frame Status register. If the Acceptance Filter does not find a match in either the individual or Range table for the size of Identifier received, it signals the CAN controller to discard/ignore the received message. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 374 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 14. Acceptance filter registers 14.1 Acceptance Filter Mode Register (AFMR - 0x4003 C000) The AccBP and AccOff bits of the acceptance filter mode register are used for putting the acceptance filter into the Bypass and Off mode. The eFCAN bit of the mode register can be used to activate a FullCAN mode enhancement for received 11-bit CAN ID messages. Table 343. Acceptance Filter Mode Register (AFMR - address 0x4003 C000) bit description Bit Symbol Value Description Reset Value 0 1 AccOff[2] AccBP[1] 1 1 if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN 1 buses are ignored. All Rx messages are accepted on enabled CAN controllers. Software must set this 0 bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers. Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers. The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 16–16 “FullCAN mode” on page 380. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1] 2 eFCAN[3] 0 1 0 31:3 - NA Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance Filter Mode Register, the Acceptance filter is put into the Acceptance Filter Bypass mode. During bypass mode, the internal state machine of the Acceptance Filter is reset and halted. All received CAN messages are accepted, and acceptance filtering can be done by software. Acceptance Filter Off mode (AccOff): After power-up or hardware reset, the Acceptance filter will be in Off mode, the AccOff bit in the Acceptance filter Mode register 0 will be set to 1. The internal state machine of the acceptance filter is reset and halted. If not in Off mode, setting the AccOff bit, either by hardware or by software, will force the acceptance filter into Off mode. FullCAN Mode Enhancements: A FullCAN mode for received CAN messages can be enabled by setting the eFCAN bit in the acceptance filter mode register. [2] [3] 14.2 Section configuration registers The 10-bit section configuration registers are used for the ID look-up table RAM to indicate the boundaries of the different sections for explicit and group of CAN identifiers for 11-bit CAN and 29-bit CAN identifiers, respectively. The 10-bit wide section configuration registers allow the use of a 512x32 (2 kB) look-up table RAM. The whole ID Look-up Table RAM is only word accessible. All five section configuration registers contain APB addresses for the acceptance filter RAM and do not include the APB base address. A write access to all section configuration registers is only possible during the Acceptance filter off and Bypass modes. Read access is allowed in all acceptance filter modes. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 375 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 14.3 Standard Frame Individual Start Address register (SFF_sa 0x4003 C004) Table 344. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description Bit Symbol Description Reset Value 1:0 10:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA SFF_sa[1] The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the 0 table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1] 31:11 - NA Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 14.4 Standard Frame Group Start Address register (SFF_GRP_sa 0x4003 C008) Table 345. Standard Frame Group Start Address register (SFF_GRP_sa - address 0x4003 C008) bit description Bit Symbol Description Reset Value 1:0 11:2 - Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. SFF_GRP_sa[1] The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If 0 the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 31:12 - 14.5 Extended Frame Start Address register (EFF_sa - 0x4003 C00C) Table 346. Extended Frame Start Address register (EFF_sa - address 0x4003 C00C) bit description Bit Symbol Description Reset Value 1:0 10:2 EFF_sa[1] Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the 0 table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31:11 - UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 376 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 14.6 Extended Frame Group Start Address register (EFF_GRP_sa 0x4003 C010) Table 347. Extended Frame Group Start Address register (EFF_GRP_sa - address 0x4003 C010) bit description Bit Symbol Description Reset Value 1:0 11:2 Eff_GRP_sa[1] Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If 0 the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. Reserved, user software should not write ones to reserved bits. The value read from NA a reserved bit is not defined. [1] Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 31:12 - 14.7 End of AF Tables register (ENDofTable - 0x4003 C014) Table 348. End of AF Tables register (ENDofTable - address 0x4003 C014) bit description Bit Symbol Description Reset Value 1:0 11:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 0 EndofTable[1] The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table. 31:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1] NA Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 14.8 Status registers The look-up table error status registers, the error addresses, and the flag register provide information if a programming error in the look-up table RAM during the ID screening was encountered. The look-up table error address and flag register have only read access. If an error is detected, the LUTerror flag is set, and the LUTerrorAddr register provides the UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 377 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 information under which address during an ID screening an error in the look-up table was encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table interrupt. 14.9 LUT Error Address register (LUTerrAd - 0x4003 C018) Table 349. LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description Bit Symbol Description Reset Value 1:0 10:2 LUTerrAd Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables. Reserved, the value read from a reserved bit is not defined. NA 0 31:11 - NA 14.10 LUT Error register (LUTerr - 0x4003 C01C) Table 350. LUT Error register (LUTerr - address 0x4003 C01C) bit description Bit Symbol Description Reset Value 0 LUTerr This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the “other CAN” interrupts from the CAN controllers, to produce the request that is connected to the NVIC. Reserved, the value read from a reserved bit is not defined. 0 31:1 - NA 14.11 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020) A write access to the Global FullCAN Interrupt Enable register is only possible when the Acceptance Filter is in the off mode. Table 351. Global FullCAN Enable register (FCANIE - address 0x4003 C020) bit description Bit Symbol Description Reset Value 0 31:1 FCANIE - Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 NA 14.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and FCANIC1 - 0x4003 C028) For detailed description on these two registers, see Section 16–16.2 “FullCAN interrupts”. Table 352. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description Bit Symbol Description Reset Value 0 ... 31 IntPnd0 IntPndx (0 Lower or same, unsigned ≤ Greater than or equal, signed ≥ Less than, signed < Greater than, signed > Less than or equal, signed ≤ Always. This is the default when no suffix is specified. Section 34– shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1). Section 34– shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3. Example: Absolute value: IT MI RSBMI R0, R1, #0 M OVS R0, R1 ; R0 = R1, setting flags ; IT instruction for the negative condition ; If negative, R0 = -R1 Example: Compare and update value: C MP R0, R1 ; Compare R0 and R1, setting flags ITT GT ; IT instruction for the two GT conditions CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags MOVGT R4, R5 ; If still 'greater than', do R4 = R5 2.3.8 Instruction width selection There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, you can force a specific instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding. If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error. Remark: In some cases it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding. To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. Section 34–2.3.8.1 shows instructions with the instruction width suffix. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 655 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.3.8.1 Example: Instruction width selection BCS.W label ; creates a 32-bit instruction even for a short branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 656 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4 Memory access instructions Table 34–617 shows the memory access instructions: Table 617. Memory access instructions Mnemonic ADR CLREX LDM{mode} LDR{type} LDR{type} LDR{type}T LDR LDREX{type} POP PUSH STM{mode} STR{type} STR{type} STR{type}T STREX{type} Brief description See Load PC-relative address Clear Exclusive Load Multiple registers Load Register using immediate offset Load Register using register offset Load Register with unprivileged access Load Register Exclusive Pop registers from stack Push registers onto stack Store Multiple registers Store Register using immediate offset Store Register using register offset Store Register with unprivileged access Store Register Exclusive Section 34–2.4.1 Section 34–2.4.9 Section 34–2.4.6 Section 34–2.4.2 Section 34–2.4.3 Section 34–2.4.4 Section 34–2.4.8 Section 34–2.4.7 Section 34–2.4.7 Section 34–2.4.6 Section 34–2.4.2 Section 34–2.4.3 Section 34–2.4.4 Section 34–2.4.8 Load Register using PC-relative address Section 34–2.4.5 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 657 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.1 ADR Load PC-relative address. 2.4.1.1 Syntax ADR {cond} Rd, label where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. label is a PC-relative expression. See Section 34–2.3.6 “PC-relative expressions”. 2.4.1.2 Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative. If you use A DR to generate a target address for a B X or B LX instruction, you must ensure that bit[0] of the address you generate is set to1 for correct execution. Values of label must be within the range of −4095 to +4095 from the address in the PC. Remark: You might have to use the .W suffix to get the maximum offset range or to generate addresses that are not word-aligned. See Section 34–2.3.8 “Instruction width selection”. 2.4.1.3 Restrictions Rd must not be SP and must not be PC. 2.4.1.4 Condition flags This instruction does not change the flags. 2.4.1.5 Examples ADR R1, TextMessage ; Write address value of a location labelled as ; TextMessage to R1 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 658 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.2 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. 2.4.2.1 Syntax op{type}{cond} Rt, [Rn {, #offset}] op{type}{cond} Rt, [Rn, #offset]! op{type}{cond} Rt, [Rn], #offset opD{cond} Rt, Rt2, [Rn {, #offset}] opD{cond} Rt, Rt2, [Rn, #offset]! opD{cond} Rt, Rt2, [Rn], #offset where: op is one of: LDR : Load register. STR : Store register. type is one of: B : unsigned byte, zero extend to 32 bits on loads. SB : signed byte, sign extend to 32 bits (LDR only). H : unsigned halfword, zero extend to 32 bits on loads. SH : signed halfword, sign extend to 32 bits (LDR only). —: omit, for word. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn. If offset is omitted, the address is the contents of Rn. Rt2 is the additional register to load or store for two-word operations. 2.4.2.2 Operation LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes: ; immediate offset ; pre-indexed ; post-indexed ; immediate offset, two words ; pre-indexed, two words ; post-indexed, two words • Offset addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 659 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide [Rn, #offset] • Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! • Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See Section 34–2.3.5 “Address alignment”. Table 34–618 shows the ranges of offset for immediate, pre-indexed and post-indexed forms. Table 618. Offset ranges Instruction type Immediate offset Pre-indexed −255 to 255 Post-indexed −255 to 255 Word, halfword, signed −255 to 4095 halfword, byte, or signed byte Two words multiple of 4 in the range −1020 to 1020 multiple of 4 in the range -1020 to 1020 multiple of 4 in the range −1020 to 1020 2.4.2.3 Restrictions For load instructions: • Rt can be SP or PC for word loads only • Rt must be different from Rt2 for two-word loads • Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. When Rt is PC in a word load instruction: • bit[0] of the loaded value must be 1 for correct execution • a branch occurs to the address created by changing bit[0] of the loaded value to 0 • if the instruction is conditional, it must be the last instruction in the IT block. For store instructions: • • • • 2.4.2.4 Rt can be SP for word stores only Rt must not be PC Rn must not be PC Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. Condition flags These instructions do not change the flags. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 660 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.2.5 Examples L DR LDRNE ; ; ; ; R2, [R9,#const-struc] ; ; R3, [R4], #4 ; ; R8, R9, [R3, #0x20] ; ; ; R0, R1, [R8], #-16 ; ; ; R8, [R10] R2, [R5, #960]! Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095. Store R3 as halfword data into address in R4, then increment R4 by 4 Load R8 from a word 32 bytes above the address in R3, and load R9 from a word 36 bytes above the address in R3 Store R0 to address in R8, and store R1 to a word 4 bytes above the address in R8, and then decrement R8 by 16. STR STRH LDRD STRD UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 661 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.3 LDR and STR, register offset Load and Store with register offset. 2.4.3.1 Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR : Load Register. STR : Store Register. type is one of: B : unsigned byte, zero extend to 32 bits on loads. SB : signed byte, sign extend to 32 bits (LDR only). H : unsigned halfword, zero extend to 32 bits on loads. SH : signed halfword, sign extend to 32 bits (LDR only). —: omit, for word. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. Rm is a register containing a value to be used as the offset. LSL #n is an optional shift, with n in the range 0 to 3. 2.4.3.2 Operation LDR instructions load a register with a value from memory. STR instructions store a register value into memory. The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using L SL . The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See Section 34–2.3.5 “Address alignment”. 2.4.3.3 Restrictions In these instructions: • • • • Rn must not be PC Rm must not be SP and must not be PC Rt can be SP only for word loads and word stores Rt can be PC only for word loads. When Rt is PC in a word load instruction: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 662 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block. 2.4.3.4 Condition flags These instructions do not change the flags. 2.4.3.5 Examples STR ; ; LDRSB R0, [R5, R1, LSL #1] ; ; ; STR R0, [R1, R2, LSL #2] ; ; R0, [R5, R1] Store value of R0 into an address equal to sum of R5 and R1 Read byte value from an address equal to sum of R5 and two times R1, sign extended it to a word value and put it in R0 Stores R0 to an address equal to sum of R1 and four times R2 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 663 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.4 LDR and STR, unprivileged Load and Store with unprivileged access. 2.4.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] where: op is one of: LDR : Load Register. STR : Store Register. type is one of: B : unsigned byte, zero extend to 32 bits on loads. SB : signed byte, sign extend to 32 bits (LDR only). H : unsigned halfword, zero extend to 32 bits on loads. SH : signed halfword, sign extend to 32 bits (LDR only). —: omit, for word. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn. 2.4.4.2 Operation These load and store instructions perform the same function as the memory access instructions with immediate offset, see Section 34–2.4.2. The difference is that these instructions have only unprivileged access even when used in privileged software. When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset. 2.4.4.3 Restrictions In these instructions: ; immediate offset • Rn must not be PC • Rt must not be SP and must not be PC. 2.4.4.4 Condition flags These instructions do not change the flags. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 664 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.4.5 Examples STRBTEQ R4, [R7] LDRHT R2, [R2, #8] ; ; ; ; Conditionally store least significant byte in R4 to an address in R7, with unprivileged access Load halfword value from an address equal to sum of R2 and 8 into R2, with unprivileged access UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 665 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.5 LDR, PC-relative Load register from memory. 2.4.5.1 Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label type is one of: B : unsigned byte, zero extend to 32 bits on loads. SB : signed byte, sign extend to 32 bits (LDR only). H : unsigned halfword, zero extend to 32 bits on loads. SH : signed halfword, sign extend to 32 bits (LDR only). —: omit, for word. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rt2 is the second register to load or store. label is a PC-relative expression. See Section 34–2.3.6 “PC-relative expressions”. 2.4.5.2 Operation LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See Section 34–2.3.5 “Address alignment”. label must be within a limited range of the current instruction. Table 34–619 shows the possible offsets between label and the PC. Table 619. Offset ranges Instruction type Offset range −4095 to 4095 −1020 to 1020 ; Load two words Word, halfword, signed halfword, byte, signed byte Two words Remark: You might have to use the .W suffix to get the maximum offset range. See Section 34–2.3.8 “Instruction width selection”. 2.4.5.3 Restrictions In these instructions: • Rt can be SP or PC only for word loads • Rt2 must not be SP and must not be PC • Rt must be different from Rt2. When Rt is PC in a word load instruction: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 666 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block. 2.4.5.4 Condition flags These instructions do not change the flags. 2.4.5.5 Examples LDR LDRSB R0, LookUpTable R7, localdata ; ; ; ; ; Load R0 with a word of data from an address labelled as LookUpTable Load a byte value from an address labelled as localdata, sign extend it to a word value, and put it in R7 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 667 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.6 LDM and STM Load and Store Multiple registers. 2.4.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM : Load Multiple registers. STM : Store Multiple registers. addr_mode is any one of the following: IA : Increment address After each access. This is the default. DB : Decrement address Before each access. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rn is the register on which the memory addresses are based. ! is an optional writeback suffix. If ! is present the final address, that is loaded from or stored to, is written back into Rn. reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range, see Section 34–2.4.6.5. LDM and L DMFD are synonyms for L DMIA . L DMFD refers to its use for popping data from Full Descending stacks. LDMEA is a synonym for L DMDB , and refers to its use for popping data from Empty Ascending stacks. STM and S TMEA are synonyms for S TMIA . S TMEA refers to its use for pushing data onto Empty Ascending stacks. STMFD is s synonym for S TMDB , and refers to its use for pushing data onto Full Descending stacks 2.4.6.2 Operation LDM instructions load the registers in reglist with word values from memory addresses based on Rn. STM instructions store the word values in the registers in reglist to memory addresses based on Rn. For L DM , L DMIA , L DMFD , S TM , S TMIA , and S TMEA the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 668 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide For L DMDB , L DMEA , S TMDB , and S TMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The P USH and P OP instructions can be expressed in this form. See Section 34–2.4.7 for details. 2.4.6.3 Restrictions In these instructions: • • • • • Rn must not be PC reglist must not contain SP in any S TM instruction, reglist must not contain PC in any L DM instruction, reglist must not contain PC if it contains LR reglist must not contain Rn if you specify the writeback suffix. When PC is in reglist in an L DM instruction: • bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block. 2.4.6.4 Condition flags These instructions do not change the flags. 2.4.6.5 Examples LDM STMDB 2.4.6.6 R8,{R0,R2,R9} ; LDMIA is a synonym for LDM R1!,{R3-R6,R11,R12} Incorrect examples STM LDM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable R2, {} ; There must be at least one register in the list UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 669 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. 2.4.7.1 Syntax PUSH {cond} reglist POP {cond} reglist where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range. PUSH and P OP are synonyms for S TMDB and L DM (or L DMIA ) with the memory addresses for the access based on SP, and with the final address for the access written back to the SP. P USH and P OP are the preferred mnemonics in these cases. 2.4.7.2 Operation PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. See Section 34–2.4.6 for more information. 2.4.7.3 Restrictions In these instructions: • reglist must not contain SP • for the P USH instruction, reglist must not contain PC • for the P OP instruction, reglist must not contain PC if it contains LR. When PC is in reglist in a P OP instruction: • bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block. 2.4.7.4 Condition flags These instructions do not change the flags. 2.4.7.5 Examples PUSH PUSH POP UM10360_1 {R0,R4-R7} {R2,LR} {R0,R10,PC} © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 670 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.8 LDREX and STREX Load and Store Register Exclusive. 2.4.8.1 Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the value in Rn. 2.4.8.2 Operation LDREX , L DREXB , and L DREXH load a word, byte, and halfword respectively from a memory address. STREX , S TREXB , and S TREXH attempt to store a word, byte, and halfword respectively to a memory address. The address used in any Store-Exclusive instruction must be the same as the address in the most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see Section 34–3.2.7 “Synchronization primitives” If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is guaranteed that no other process in the system has accessed the memory location between the Load-exclusive and Store-Exclusive instructions. For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and Store-Exclusive instruction to a minimum. Remark: The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding Load-Exclusive instruction is unpredictable. 2.4.8.3 Restrictions In these instructions: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 671 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide • • • • 2.4.8.4 do not use PC do not use SP for Rd and Rt for S TREX , Rd must be different from both Rt and Rn the value of offset must be a multiple of four in the range 0-1020. Condition flags These instructions do not change the flags. 2.4.8.5 Examples M OV try LDREX CMP ITT STREXEQ CMPEQ BNE .... R0, R0, EQ R0, R0, try [LockAddr] #0 ; ; ; R1, [LockAddr] ; #0 ; ; ; Load the lock value Is the lock free? IT instruction for STREXEQ and CMPEQ Try and claim the lock Did this succeed? No – try again Yes – we have the lock R1, #0x1 ; Initialize the ‘lock taken’ value UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 672 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.4.9 CLREX Clear Exclusive. 2.4.9.1 Syntax CLREX{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.4.9.2 Operation Use C LREX to make the next S TREX , S TREXB , or S TREXH instruction write 1 to its destination register and fail to perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation. See Section 34–3.2.7 “Synchronization primitives” for more information. 2.4.9.3 Condition flags These instructions do not change the flags. 2.4.9.4 Examples CLREX UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 673 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5 General data processing instructions Table 34–620 shows the data processing instructions: Table 620. Data processing instructions Mnemonic ADC ADD ADDW AND ASR BIC CLZ CMN CMP EOR LSL LSR MOV MOVT MOVW MVN ORN ORR RBIT REV REV16 REVSH ROR RRX RSB SBC SUB SUBW TEQ TST Brief description See Add with Carry Add Add Logical AND Arithmetic Shift Right Bit Clear Count leading zeros Compare Negative Compare Exclusive OR Logical Shift Left Logical Shift Right Move Move Top Move 16-bit constant Move NOT Logical OR NOT Logical OR Reverse Bits Reverse byte order in a word Reverse byte order in each halfword Reverse byte order in bottom halfword and sign extend Rotate Right Rotate Right with Extend Reverse Subtract Subtract with Carry Subtract Subtract Test Equivalence Test Section 34–2.5.1 Section 34–2.5.1 Section 34–2.5.1 Section 34–2.5.2 Section 34–2.5.3 Section 34–2.5.2 Section 34–2.5.4 Section 34–2.5.5 Section 34–2.5.5 Section 34–2.5.2 Section 34–2.5.3 Section 34–2.5.3 Section 34–2.5.6 Section 34–2.5.7 Section 34–2.5.6 Section 34–2.5.6 Section 34–2.5.2 Section 34–2.5.2 Section 34–2.5.8 Section 34–2.5.8 Section 34–2.5.8 Section 34–2.5.8 Section 34–2.5.3 Section 34–2.5.3 Section 34–2.5.1 Section 34–2.5.1 Section 34–2.5.1 Section 34–2.5.1 Section 34–2.5.9 Section 34–2.5.9 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 674 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 2.5.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 where: op is one of: ADD: Add. ADC: Add with Carry. SUB: Subtract. RSB: Reverse Subtract. S: is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34–2.3.7 “Conditional execution”. cond: is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the first operand. Operand2 is a flexible second operand. See Section 34–2.3.3 for details of the options. imm12 is any value in the range 0-4095. 2.5.1.2 Operation The A DD instruction adds the value of Operand2 or imm12 to the value in Rn. The A DC instruction adds the values in Rn and Operand2, together with the carry flag. The S UB instruction subtracts the value of Operand2 or imm12 from the value in Rn. The S BC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one. The R SB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2. Use A DC and S BC to synthesize multiword arithmetic, see Section 34–2.5.1.6. See also Section 34–2.4.1. Remark: A DDW is equivalent to the A DD syntax that uses the imm12 operand. S UBW is equivalent to the S UB syntax that uses the imm12 operand. 2.5.1.3 Restrictions ; ADD and SUB only • Operand2 must not be SP and must not be PC • Rd can be SP only in A DD and S UB , and only with the additional restrictions: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 675 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide – Rn must also be SP – any shift in Operand2 must be limited to a maximum of 3 bits using L SL • Rn can be SP only in A DD and S UB • Rd can be PC only in the cond instruction where: – you must not specify the S suffix – Rm must not be PC and must not be SP – if the instruction is conditional, it must be the last instruction in the IT block • with the exception of the cond instruction, Rn can be PC only in A DD and S UB , and only with the additional restrictions: – you must not specify the S suffix – the second operand must be a constant in the range 0 to 4095. Note • When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to b00 before performing the calculation, making the base address for the calculation word-aligned. • If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. ARM recommends that you use the A DR instruction instead of A DD or S UB with Rn equal to the PC, because your assembler automatically calculates the correct constant for the A DR instruction. When Rd is PC in the cond instruction: • bit[0] of the value written to the PC is ignored • a branch occurs to the address created by forcing bit[0] of that value to 0. 2.5.1.4 Condition flags If S is specified, these instructions update the N, Z, C and V flags according to the result. 2.5.1.5 Examples ADD SUBS RSB ADCHI R2, R1, R3 R8, R6, #240 R4, R4, #1280 R11, R0, R3 ; ; ; ; Sets the flags on the result Subtracts contents of R4 from 1280 Only executed if C flag set and Z flag clear 2.5.1.6 Multiword arithmetic examples Section 34– shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5. Multiword values do not have to use consecutive registers. Section 34– shows instructions that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2. 64-bit addition: A DDS R4, R0, R2 ADC R5, R1, R3 ; add the least significant words ; add the most significant words with carry © NXP B.V. 2010. All rights reserved. UM10360_1 User manual Rev. 01 — 4 January 2010 676 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 96-bit subtraction: S UBS R6, R6, R9 SBCS R9, R2, R1 SBC R2, R8, R11 ; subtract the least significant words ; subtract the middle words with carry ; subtract the most significant words with carry UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 677 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. 2.5.2.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND: logical AND. ORR: logical OR, or bit set. EOR: logical Exclusive OR. BIC: logical AND NOT, or bit clear. ORN: logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34–2.3.7 “Conditional execution”. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. Rn is the register holding the first operand. Operand2 is a flexible second operand. See Section 34–2.3.3 for details of the options. 2.5.2.2 Operation The A ND , E OR , and O RR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2. The B IC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. The O RN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. 2.5.2.3 Restrictions Do not use SP and do not use PC. 2.5.2.4 Condition flags If S is specified, these instructions: • update the N and Z flags according to the result • can update the C flag during the calculation of Operand2, see Section 34–2.3.3 • do not affect the V flag. 2.5.2.5 Examples AND ORREQ ANDS UM10360_1 R9, R2, #0xFF00 R2, R0, R5 R9, R8, #0x19 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 678 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide EORS BIC ORN ORNS R7, R0, R7, R7, R11, #0x18181818 R1, #0xab R11, R14, ROR #4 R11, R14, ASR #32 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 679 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 2.5.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR: Arithmetic Shift Right. LSL: Logical Shift Left. LSR : Logical Shift Right. ROR: Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. Rm is the register holding the shift length to apply to the value in Rm. Only the least significant byte is used and can be in the range 0 to 255. Rs s the register holding the shift length to apply to the value in Rm. Only the least significant byte is used and can be in the range 0 to 255. n is the shift length. The range of shift length depends on the instruction: ASR: shift length from 1 to 32 LSL: shift length from 0 to 31 LSR: shift length from 1 to 32 ROR: shift length from 1 to 31 Remark: M OV{S}{cond} Rd, Rm is the preferred syntax for L SL{S}{cond} Rd, Rm, #0 . 2.5.3.2 Operation ASR , L SL , L SR , and R OR move the bits in the register Rm to the left or right by the number of places specified by constant n or register Rs. RRX moves the bits in register Rm to the right by 1. In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on what result is generated by the different instructions, see Section 34–2.3.4 “Shift Operations”. 2.5.3.3 Restrictions Do not use SP and do not use PC. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 680 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.3.4 Condition flags If S is specified: • these instructions update the N and Z flags according to the result • the C flag is updated to the last bit shifted out, except when the shift length is 0, see Section 34–2.3.4 “Shift Operations”. 2.5.3.5 Examples ASR LSLS LSR ROR RRX R7, R1, R4, R4, R4, R8, R2, R5, R5, R5 #9 #3 #6 R6 ; ; ; ; ; Arithmetic shift right by 9 bits Logical shift left by 3 bits with flag update Logical shift right by 6 bits Rotate right by the value in the bottom byte of R6 Rotate right with extend UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 681 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.4 CLZ Count Leading Zeros. 2.5.4.1 Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see Section 34–2.3.7. Rd is the destination register. Rm is the operand register. 2.5.4.2 Operation The C LZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31] is set. 2.5.4.3 Restrictions Do not use SP and do not use PC. 2.5.4.4 Condition flags This instruction does not change the flags. 2.5.4.5 Examples CLZ CLZNE R4,R9 R2,R3 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 682 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.5 CMP and CMN Compare and Compare Negative. 2.5.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see Section 34–2.3.7. Rn is the register holding the first operand. Operand2 is a flexible second operand. See Flexible second operand on page 3-10for details of the options. 2.5.5.2 Operation These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not write the result to a register. The C MP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a S UBS instruction, except that the result is discarded. The C MN instruction adds the value of Operand2 to the value in Rn. This is the same as an A DDS instruction, except that the result is discarded. 2.5.5.3 Restrictions In these instructions: • do not use PC • Operand2 must not be SP. 2.5.5.4 Condition flags These instructions update the N, Z, C and V flags according to the result. 2.5.5.5 Examples CMP CMN CMPGT R2, R9 R0, #6400 SP, R7, LSL #2 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 683 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.6 MOV and MVN Move and Move NOT. 2.5.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34–2.3.7. cond is an optional condition code, see Section 34–2.3.7. Rd is the destination register. Operand2 is a flexible second operand. See Flexible second operand on page 3-10for details of the options. imm16 is any value in the range 0-65535. 2.5.6.2 Operation The M OV instruction copies the value of Operand2 into Rd. When Operand2 in a M OV instruction is a register with a shift other than L SL #0 , the preferred syntax is the corresponding shift instruction: • ASR{S}{cond} Rd, Rm, #n is the preferred syntax for M OV{S}{cond} Rd, Rm, ASR #n • LSL{S}{cond} Rd, Rm, #n is the preferred syntax for M OV{S}{cond} Rd, Rm, LSL #n n if != 0 • LSR{S}{cond} Rd, Rm, #n is the preferred syntax for M OV{S}{cond} Rd, Rm, LSR #n • ROR{S}{cond} Rd, Rm, #n is the preferred syntax for M OV{S}{cond} Rd, Rm, ROR #n • RRX{S}{cond} Rd, Rm is the preferred syntax for M OV{S}{cond} Rd, Rm, RRX . Also, the M OV instruction permits additional forms of Operand2 as synonyms for shift instructions: • • • • MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for A SR{S}{cond} Rd, Rm, Rs MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for L SL{S}{cond} Rd, Rm, Rs MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for L SR{S}{cond} Rd, Rm, Rs MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for R OR{S}{cond} Rd, Rm, Rs See Section 34–2.5.3. The M VN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd. Remark: The M OVW instruction provides the same function as M OV , but is restricted to using the imm16 operand. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 684 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.6.3 Restrictions You can use SP and PC only in the M OV instruction, with the following restrictions: • the second operand must be a register without shift • you must not specify the S suffix. When Rd is PC in a M OV instruction: • bit[0] of the value written to the PC is ignored • a branch occurs to the address created by forcing bit[0] of that value to 0. Remark: Though it is possible to use M OV as a branch instruction, ARM strongly recommends the use of a B X or B LX instruction to branch for software portability to the ARM instruction set. 2.5.6.4 Condition flags If S is specified, these instructions: • update the N and Z flags according to the result • can update the C flag during the calculation of Operand2, see Section 34–2.3.3 • do not affect the V flag. 2.5.6.5 Example MOVS R11, MOV MOVS MOV MOV MVNS #0x000B ; Write value of 0x000B to R11, flags get updated R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated R10, R12 ; Write value in R12 to R10, flags get updated R3, #23 ; Write value of 23 to R3 R8, SP ; Write value of stack pointer to R8 R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF) ; to the R2 and update flags UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 685 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.7 MOVT Move Top. 2.5.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see Section 34–2.3.7. Rd is the destination register. imm16 is a 16-bit immediate constant. 2.5.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The M OV , M OVT instruction pair enables you to generate any 32-bit constant. 2.5.7.3 Restrictions Rd must not be SP and must not be PC. 2.5.7.4 Condition flags This instruction does not change the flags. 2.5.7.5 Examples MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword ; and APSR are unchanged UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 686 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 2.5.8.1 Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see Section 34–2.3.7. Rd is the destination register. Rn is the register holding the operand. 2.5.8.2 Operation Use these instructions to change endianness of data: REV: converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian data. REV16 converts 16-bit big-endian data into little-endian data or 16-bit little-endian data into big-endian data. REVSH converts either: 16-bit signed big-endian data into 32-bit signed little-endian data 16-bit signed little-endian data into 32-bit signed big-endian data. 2.5.8.3 Restrictions Do not use SP and do not use PC. 2.5.8.4 Condition flags These instructions do not change the flags. 2.5.8.5 Examples REV REV16 REVSH REVHS RBIT R3, R0, R0, R3, R7, R7 R0 R5 R7 R8 ; ; ; ; ; Reverse Reverse Reverse Reverse Reverse byte order of value in R7 and write it to R3 byte order of each 16-bit halfword in R0 Signed Halfword with Higher or Same condition bit order of value in R8 and write the result to R7 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 687 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.5.9 TST and TEQ Test bits and Test Equivalence. 2.5.9.1 Syntax TST {cond} Rn, Operand2 TEQ {cond} Rn, Operand2 where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rn is the register holding the first operand. Operand2 is a flexible second operand. See Section 34–2.3.3 for details of the options. 2.5.9.2 Operation These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register. The T ST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as the A NDS instruction, except that it discards the result. To test whether a bit of Rn is 0 or 1, use the T ST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0. The T EQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. This is the same as the E ORS instruction, except that it discards the result. Use the T EQ instruction to test if two values are equal without affecting the V or C flags. TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands. 2.5.9.3 Restrictions Do not use SP and do not use PC. 2.5.9.4 Condition flags These instructions: • update the N and Z flags according to the result • can update the C flag during the calculation of Operand2, see Section 34–2.3.3 • do not affect the V flag. 2.5.9.5 Examples TST TEQEQ R0, #0x3F8 ; ; R10, R9 ; ; Perform bitwise AND of R0 value to 0x3F8, APSR is updated but result is discarded Conditionally test if value in R10 is equal to value in R9, APSR is updated but result is discarded UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 688 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.6 Multiply and divide instructions Table 34–621 shows the multiply and divide instructions: Table 621. Multiply and divide instructions Mnemonic MLA MLS MUL SDIV SMLAL SMULL UDIV UMLAL UMULL Brief description See Multiply with Accumulate, 32-bit result Multiply and Subtract, 32-bit result Multiply, 32-bit result Signed Divide Signed Multiply with Accumulate (32x32+64), 64-bit result Signed Multiply (32x32), 64-bit result Unsigned Divide Unsigned Multiply with Accumulate (32x32+64), 64-bit result Unsigned Multiply (32x32), 64-bit result Section 34–2.6.1 Section 34–2.6.1 Section 34–2.6.1 Section 34–2.6.3 Section 34–2.6.2 Section 34–2.6.2 Section 34–2.6.3 Section 34–2.6.2 Section 34–2.6.2 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 689 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. 2.6.1.1 Syntax MUL{S} {cond} {Rd,} Rn, Rm ; Multiply MLA {cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be added or subtracted from. 2.6.1.2 Operation The M UL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd. The M LA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32 bits of the result in Rd. The M LS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and places the least significant 32 bits of the result in Rd. The results of these instructions do not depend on whether the operands are signed or unsigned. 2.6.1.3 Restrictions In these instructions, do not use SP and do not use PC. If you use the S suffix with the M UL instruction: • Rd, Rn, and Rm must all be in the range R 0 to R 7 • Rd must be the same as Rm • you must not use the cond suffix. 2.6.1.4 Condition flags If S is specified, the M UL instruction: • updates the N and Z flags according to the result • does not affect the C and V flags. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 690 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.6.1.5 Examples MUL MLA MULS MULLT MLS R10, R2, R5 R10, R2, R1, R5 R0, R2, R2 R2, R3, R2 R4, R5, R6, R7 ; ; ; ; ; Multiply, R10 Multiply with Multiply with Conditionally Multiply with = R2 x R5 accumulate, R10 = flag update, R0 = multiply, R2 = R3 subtract, R4 = R7 (R2 x R1) + R5 R2 x R2 x R2 - (R5 x R6) UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 691 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.6.2 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. 2.6.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL: Unsigned Long Multiply. UMLAL: Unsigned Long Multiply, with Accumulate. SMULL: Signed Long Multiply. SMLAL: Signed Long Multiply, with Accumulate. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. RdHi, RdLo are the destination registers. For U MLAL and S MLAL they also hold the accumulating value. Rn, Rm are registers holding the operands. 2.6.2.2 Operation The U MULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The U MLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. The S MULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The S MLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. 2.6.2.3 Restrictions In these instructions: • do not use SP and do not use PC • RdHi and RdLo must be different registers. 2.6.2.4 Condition flags These instructions do not affect the condition code flags. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 692 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.6.2.5 Examples UMULL SMLAL R0, R4, R5, R6 R4, R5, R3, R8 ; Unsigned (R4,R0) = R5 x R6 ; Signed (R5,R4) = (R5,R4) + R3 x R8 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 693 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.6.3 SDIV and UDIV Signed Divide and Unsigned Divide. 2.6.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. 2.6.3.2 Operation SDIV performs a signed integer division of the value in Rn by the value in Rm. UDIV performs an unsigned integer division of the value in Rn by the value in Rm. For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero. 2.6.3.3 Restrictions Do not use SP and do not use PC. 2.6.3.4 Condition flags These instructions do not change the flags. 2.6.3.5 Examples SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4 UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 694 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.7 Saturating instructions This section describes the saturating instructions, S SAT and U SAT . 2.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 2.7.1.1 Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. n specifies the bit position to saturate to: • n ranges from 1 to 32 for S SAT . • n ranges from 0 to 31 for U SAT . Rm is the register containing the value to saturate. shift #s is an optional shift applied to Rm before saturating. It must be one of the following: ASR # s: where s is in the range 1 to 31 LSL # s: where s is in the range 0 to 31. 2.7.1.2 Operation These instructions saturate to a signed or unsigned n-bit value. The S SAT instruction applies the specified shift, then saturates to the signed range −2n–1 ≤ x ≤ 2n–1−1. The U SAT instruction applies the specified shift, then saturates to the unsigned range 0 ≤ x ≤ 2n−1. For signed n-bit saturation using S SAT , this means that: • if the value to be saturated is less than −2n-1, the result returned is −2n-1 • if the value to be saturated is greater than 2n-1−1, the result returned is 2n-1−1 • otherwise, the result returned is the same as the value to be saturated. For unsigned n-bit saturation using U SAT , this means that: • if the value to be saturated is less than 0, the result returned is 0 • if the value to be saturated is greater than 2n−1, the result returned is 2n−1 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 695 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide • otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, you must use the M SR instruction, see Section 34–2.10.7. To read the state of the Q flag, use the M RS instruction, see Section 34–2.10.6. 2.7.1.3 Restrictions Do not use SP and do not use PC. 2.7.1.4 Condition flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. 2.7.1.5 Examples SSAT R7, #16, R7, LSL #4 ; ; ; USATNE R0, #7, R5 ; ; Logical shift left value in R7 by 4, then saturate it as a signed 16-bit value and write it back to R7 Conditionally saturate value in R5 as an unsigned 7 bit value and write it to R0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 696 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.8 Bitfield instructions Table 34–622 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 622. Packing and unpacking instructions Mnemonic BFC BFI SBFX SXTB SXTH UBFX UXTB UXTH Brief description See Bit Field Clear Bit Field Insert Signed Bit Field Extract Sign extend a byte Sign extend a halfword Unsigned Bit Field Extract Zero extend a byte Zero extend a halfword Section 34–2.8.1 Section 34–2.8.1 Section 34–2.8.2 Section 34–2.8.3 Section 34–2.8.3 Section 34–2.8.2 Section 34–2.8.3 Section 34–2.8.3 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 697 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.8.1 BFC and BFI Bit Field Clear and Bit Field Insert. 2.8.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32−lsb. 2.8.1.2 Operation BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position l sb . Other bits in Rd are unchanged. BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit position l sb , with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged. 2.8.1.3 Restrictions Do not use SP and do not use PC. 2.8.1.4 Condition flags These instructions do not affect the flags. 2.8.1.5 Examples BFC BFI R4, #8, #12 R9, R2, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0 ; Replace bit 8 to bit 19 (12 bits) of R9 with ; bit 0 to bit 11 from R2 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 698 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.8.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 2.8.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32−lsb. 2.8.2.2 Operation SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register. U BFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination register. 2.8.2.3 Restrictions Do not use SP and do not use PC. 2.8.2.4 Condition flags These instructions do not affect the flags. 2.8.2.5 Examples SBFX R0, R1, #20, #4 ; ; UBFX R8, R11, #9, #10 ; ; Extract bit 20 to bit 23 (4 bits) from R1 and sign extend to 32 bits and then write the result to R0. Extract bit 9 to bit 18 (10 bits) from R11 and zero extend to 32 bits and then write the result to R8 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 699 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.8.3 SXT and UXT Sign extend and Zero extend. 2.8.3.1 Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B: Extends an 8-bit value to a 32-bit value. H: Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8: Value from Rm is rotated right 8 bits. ROR #16: Value from Rm is rotated right 16 bits. ROR #24: Value from Rm is rotated right 24 bits. If ROR #n is omitted, no rotation is performed. 2.8.3.2 Operation These instructions do the following: 1. Rotate the value from Rm right by 0, 8, 16 or 24 bits. 2. Extract bits from the resulting value: – SXTB extracts bits[7:0] and sign extends to 32 bits. – UXTB extracts bits[7:0] and zero extends to 32 bits. – SXTH extracts bits[15:0] and sign extends to 32 bits. – UXTH extracts bits[15:0] and zero extends to 32 bits. 2.8.3.3 Restrictions Do not use SP and do not use PC. 2.8.3.4 Condition flags These instructions do not affect the flags. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 700 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.8.3.5 Examples SXTH R4, R6, ROR #16 ; ; ; UXTB R3, R10 ; ; Rotate R6 right by 16 bits, then obtain the lower halfword of the result and then sign extend to 32 bits and write the result to R4. Extract lowest byte of the value in R10 and zero extend it, and write the result to R3 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 701 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.9 Branch and control instructions Table 34–623 shows the branch and control instructions: Table 623. Branch and control instructions Mnemonic B BL BLX BX CBNZ CBZ IT TBB TBH Brief description See Branch Branch with Link Branch indirect with Link Branch indirect Compare and Branch if Non Zero Compare and Branch if Non Zero If-Then Table Branch Byte Table Branch Halfword Section 34–2.9.1 Section 34–2.9.1 Section 34–2.9.1 Section 34–2.9.1 Section 34–2.9.2 Section 34–2.9.2 Section 34–2.9.3 Section 34–2.9.4 Section 34–2.9.4 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 702 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.9.1 B, BL, BX, and BLX Branch instructions. 2.9.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. label is a PC-relative expression. See Section 34–2.3.6 “PC-relative expressions”. Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must be 1, but the address to branch to is created by changing bit[0] to 0. 2.9.1.2 Operation All these instructions cause a branch to label, or to the address indicated in Rm. In addition: • The B L and B LX instructions write the address of the next instruction to LR (the link register, R14). • The B X and B LX instructions cause a UsageFault exception if bit[0] of Rm is 0. Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see Section 34–2.9.3. Table 34–624 shows the ranges for the various branch instructions. Table 624. Branch ranges Instruction B label B cond l abel (outside IT block) B cond l abel (inside IT block) BL {cond} l abel BX {cond} R m B LX {cond} R m Branch range −16 MB to +16 MB −1 MB to +1 MB −16 MB to +16 MB −16 MB to +16 MB Any value in register Any value in register Remark: You might have to use the .W suffix to get the maximum branch range. See Section 34–2.3.8 “Instruction width selection”. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 703 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.9.1.3 Restrictions The restrictions are: • do not use PC in the B LX instruction • for B X and B LX , bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 • when any of these instructions is inside an IT block, it must be the last instruction of the IT block. Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch range when it is inside an IT block. 2.9.1.4 Condition flags These instructions do not change the flags. 2.9.1.5 Examples B BLE B.W BEQ BEQ.W BL BX BXNE BLX loopA ng target target target funC LR R0 R0 ; ; ; ; ; ; ; ; ; ; ; Branch to loopA Conditionally branch to label ng Branch to target within 16MB range Conditionally branch to target Conditionally branch to target within 1MB Branch with link (Call) to function funC, return address stored in LR Return from function call Conditionally branch to address stored in R0 Branch with link and exchange (Call) to a address stored in R0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 704 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.9.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 2.9.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. 2.9.2.2 Operation Use the C BZ or C BNZ instructions to avoid changing the condition code flags and to reduce the number of instructions. C BZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BEQ label CBNZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BNE label 2.9.2.3 Restrictions The restrictions are: • Rn must be in the range of R 0 to R 7 • the branch destination must be within 4 to 130 bytes after the instruction • these instructions must not be used inside an IT block. 2.9.2.4 Condition flags These instructions do not change the flags. 2.9.2.5 Examples CBZ CBNZ R5, target ; Forward branch if R5 is zero R0, target ; Forward branch if R0 is not zero UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 705 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.9.3 IT If-Then condition instruction. 2.9.3.1 Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T: Then. Applies the condition cond to the instruction. E: Else. Applies the inverse condition of cond to the instruction. Remark: It is possible to use A L (the always condition) for cond in an I T instruction. If this is done, all of the instructions in the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E . 2.9.3.2 Operation The I T instruction makes up to four following instructions conditional. The conditions can be all the same, or some of them can be the logical inverse of the others. The conditional instructions following the I T instruction form the IT block. The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their syntax. Remark: Your assembler might be able to generate the required I T instructions for conditional instructions automatically, so that you do not need to write them yourself. See your assembler documentation for details. A B KPT instruction in an IT block is always executed, even if its condition fails. Exceptions can be taken between an I T instruction and the corresponding IT block, or within an IT block. Such an exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked PSR. Instructions designed for use for exception returns can be used as normal to return from the exception, and execution of the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to branch to an instruction in an IT block. 2.9.3.3 Restrictions The following instructions are not permitted in an IT block: • IT • CBZ and C BNZ UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 706 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide • CPSID and C PSIE. Other restrictions when using an IT block are: • a branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: – ADD PC, PC, Rm – MOV PC, Rm – B , B L , B X , B LX – any L DM , L DR , or P OP instruction that writes to the PC – TBB and T BH • do not branch to any instruction inside an IT block, except when returning from an exception handler • all conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one • each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block. Remark: Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them. 2.9.3.4 Condition flags This instruction does not change the flags. 2.9.3.5 Example ITTE ANDNE ADDSNE MOVEQ CMP NE R0, R0, R1 R2, R2, #1 R2, R3 R0, #9 ; ; ; ; Next 3 instructions are conditional ANDNE does not update condition flags ADDSNE updates condition flags Conditional move Convert R0 hex value (0 to 15) into ASCII ('0'-'9', 'A'-'F') Next 2 instructions are conditional Convert 0xA -> 'A' Convert 0x0 -> '0' ; ; ITE GT ; ADDGT R1, R0, #55 ; ADDLE R1, R0, #48 ; IT GT ; IT block with only one conditional instruction ; Increment R1 conditionally ADDGT R1, R1, #1 ITTEE MOVEQ ADDEQ ANDNE BNE.W EQ ; Next 4 instructions are conditional R0, R1 ; Conditional move R2, R2, #10 ; Conditional add R3, R3, #1 ; Conditional AND dloop ; Branch instruction can only be used in the last ; instruction of an IT block UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 707 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide IT ADD NE R0, R0, R1 ; Next instruction is conditional ; Syntax error: no condition code used in IT block UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 708 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.9.4 TBB and TBH Table Branch Byte and Table Branch Halfword. 2.9.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the T BB or T BH instruction. Rm is the index register. This contains an index into the table. For halfword tables, L SL #1 doubles the value in Rm to form the right offset into the table. 2.9.4.2 Operation These instructions cause a PC-relative forward branch using a table of single byte offsets for T BB , or halfword offsets for T BH . Rn provides a pointer to the table, and Rm supplies an index into the table. For T BB the branch offset is twice the unsigned value of the byte returned from the table. and for T BH the branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the address of the byte immediately after the T BB or T BH instruction. 2.9.4.3 Restrictions The restrictions are: • Rn must not be SP • Rm must not be SP and must not be PC • when any of these instructions is used inside an IT block, it must be the last instruction of the IT block. 2.9.4.4 Condition flags These instructions do not change the flags. 2.9.4.5 Examples ADR.W R0, BranchTable_Byte TBB [R0, R1] ; R1 is the index, R0 is the base address of the ; branch table Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 ; Case1 offset calculation DCB ((Case2-Case1)/2) ; Case2 offset calculation DCB ((Case3-Case1)/2) ; Case3 offset calculation UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 709 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 710 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10 Miscellaneous instructions Table 34–625 shows the remaining Cortex-M3 instructions: Table 625. Miscellaneous instructions Mnemonic BKPT CPSID CPSIE DMB DSB ISB MRS MSR NOP SEV SVC WFE WFI Brief description See Breakpoint Change Processor State, Disable Interrupts Change Processor State, Enable Interrupts Data Memory Barrier Data Synchronization Barrier Instruction Synchronization Barrier Move from special register to register Move from register to special register No Operation Send Event Supervisor Call Wait For Event Wait For Interrupt Section 34–2.10.1 Section 34–2.10.2 Section 34–2.10.2 Section 34–2.10.3 Section 34–2.10.4 Section 34–2.10.5 Section 34–2.10.6 Section 34–2.10.7 Section 34–2.10.8 Section 34–2.10.9 Section 34–2.10.10 Section 34–2.10.11 Section 34–2.10.12 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 711 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.1 BKPT Breakpoint. 2.10.1.1 Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 2.10.1.2 Operation The B KPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. The B KPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition specified by the I T instruction. 2.10.1.3 Condition flags This instruction does not change the flags. 2.10.1.4 Examples BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can ; extract the immediate value by locating it using the PC) UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 712 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.2 CPS Change Processor State. 2.10.2.1 Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register iflags is a sequence of one or more flags: i Set or clear PRIMASK. f Set or clear FAULTMASK. 2.10.2.2 Operation CPS changes the PRIMASK and FAULTMASK special register values. See Section 34–3.1.3.6 “Exception mask registers” for more information about these registers. 2.10.2.3 Restrictions The restrictions are: • use C PS only from privileged software, it has no effect if used in unprivileged software. • CPS cannot be conditional and so must not be used inside an IT block. 2.10.2.4 Condition flags This instruction does not change the condition flags. 2.10.2.5 Examples CPSID CPSID CPSIE CPSIE i f i f ; ; ; ; Disable interrupts and configurable fault handlers (set PRIMASK) Disable interrupts and all fault handlers (set FAULTMASK) Enable interrupts and configurable fault handlers (clear PRIMASK) Enable interrupts and fault handlers (clear FAULTMASK) UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 713 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.3 DMB Data Memory Barrier. 2.10.3.1 Syntax DMB{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the D MB instruction are completed before any explicit memory accesses that appear, in program order, after the D MB instruction. D MB does not affect the ordering or execution of instructions that do not access memory. 2.10.3.3 Condition flags This instruction does not change the flags. 2.10.3.4 Examples DMB ; Data Memory Barrier UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 714 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.4 DSB Data Synchronization Barrier. 2.10.4.1 Syntax DSB{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.4.2 Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the D SB , in program order, do not execute until the D SB instruction completes. The D SB instruction completes when all explicit memory accesses before it complete. 2.10.4.3 Condition flags This instruction does not change the flags. 2.10.4.4 Examples DSB ; Data Synchronisation Barrier UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 715 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.5 ISB Instruction Synchronization Barrier. 2.10.5.1 Syntax ISB{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the I SB are fetched from cache or memory again, after the I SB instruction has been completed. 2.10.5.3 Condition flags This instruction does not change the flags. 2.10.5.4 Examples ISB ; Instruction Synchronisation Barrier UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 716 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.6 MRS Move the contents of a special register to a general-purpose register. 2.10.6.1 Syntax MRS {cond} Rd, spec_reg where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. spec_reg can be any of: A PSR , I PSR , E PSR , I EPSR , I APSR , E APSR , P SR , M SP , P SP , P RIMASK , B ASEPRI , B ASEPRI_MAX , F AULTMASK , or C ONTROL . 2.10.6.2 Operation Use M RS in combination with M SR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag. In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use M RS in the state-saving instruction sequence and M SR in the state-restoring instruction sequence. Remark: B ASEPRI_MAX is an alias of B ASEPRI when used with the M RS instruction. See Section 34–2.10.7. 2.10.6.3 Restrictions Rd must not be SP and must not be PC. 2.10.6.4 Condition flags This instruction does not change the flags. 2.10.6.5 Examples MRS R0, PRIMASK ; Read PRIMASK value and write it to R0 UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 717 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.7 MSR Move the contents of a general-purpose register into the specified special register. 2.10.7.1 Syntax MSR {cond} spec_reg, Rn where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rn is the source register. spec_reg can be any of: A PSR , I PSR , E PSR , I EPSR , I APSR , E APSR , P SR , M SP , P SP , P RIMASK , B ASEPRI , B ASEPRI_MAX , F AULTMASK , or C ONTROL . 2.10.7.2 Operation The register access operation in M SR depends on the privilege level. Unprivileged software can only access the A PSR , see Table 34–629 “APSR bit assignments”. Privileged software can access all special registers. In unprivileged software writes to unallocated or execution state bits in the P SR are ignored. Note When you write to B ASEPRI_MAX , the instruction writes to B ASEPRI only if either: • Rn is non-zero and the current B ASEPRI value is 0 • Rn is non-zero and less than the current B ASEPRI value. See Section 34–2.10.6. 2.10.7.3 Restrictions Rn must not be SP and must not be PC. 2.10.7.4 Condition flags This instruction updates the flags explicitly based on the value in Rn. 2.10.7.5 Examples MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 718 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.8 NOP No Operation. 2.10.8.1 Syntax NOP{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.8.2 Operation NOP does nothing. N OP is not necessarily a time-consuming N OP . The processor might remove it from the pipeline before it reaches the execution stage. Use N OP for padding, for example to place the following instruction on a 64-bit boundary. 2.10.8.3 Condition flags This instruction does not change the flags. 2.10.8.4 Examples NOP ; No operation UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 719 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.9 SEV Send Event. 2.10.9.1 Syntax SEV{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.9.2 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see Section 34–3.5 “Power management”. 2.10.9.3 Condition flags This instruction does not change the flags. 2.10.9.4 Examples SEV ; Send Event UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 720 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.10 SVC Supervisor Call. 2.10.10.1 Syntax SVC {cond} #imm where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 2.10.10.2 Operation The S VC instruction causes the S VC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested. 2.10.10.3 Condition flags This instruction does not change the flags. 2.10.10.4 Examples SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value ; by locating it via the stacked PC) UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 721 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.11 WFE Wait For Event. 2.10.11.1 Syntax WFE{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution” 2.10.11.2 Operation WFE is a hint instruction. If the event register is 0, W FE suspends execution until one of the following events occurs: • an exception, unless masked by the exception mask registers or the current priority level • an exception enters the Pending state, if S EVONPEND in the System Control Register is set • a Debug Entry request, if Debug is enabled • an event signaled by a peripheral or another processor in a multiprocessor system using the S EV instruction. If the event register is 1, W FE clears it to 0 and returns immediately. For more information see Section 34–3.5 “Power management”. 2.10.11.3 Condition flags This instruction does not change the flags. 2.10.11.4 Examples WFE ; Wait for event UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 722 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 2.10.12 WFI Wait for Interrupt. 2.10.12.1 Syntax WFI{cond} where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. 2.10.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs: • an exception • a Debug Entry request, regardless of whether Debug is enabled. 2.10.12.3 Condition flags This instruction does not change the flags. 2.10.12.4 Examples WFI ; Wait for interrupt UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 723 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 3. ARM Cortex-M3 User Guide: Processor 3.1 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 3.1.1 Processor mode and privilege levels for software execution The processor modes are: • Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. • Handler mode Used to handle exceptions. The processor returns to Thread mode when it has finished exception processing. The privilege levels for software execution are: • Unprivileged The software: – has limited access to the M SR and M RS instructions, and cannot use the C PS instruction – cannot access the system timer, NVIC, or system control block – might have restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level. • Privileged The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level. In Thread mode, the CONTROL register controls whether software execution is privileged or unprivileged, see Table 34–635. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the S VC instruction to make a supervisor call to transfer control to privileged software. 3.1.2 Stacks The processor uses a full descending stack. This means the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see Section 34–3.1.3.2. In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see Table 34–635. In Handler mode, the processor always uses the main stack. The options for processor operations are: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 724 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Table 626. Summary of processor mode, execution privilege level, and stack use options Processor mode Used to execute Privilege level for software execution Stack used Thread Handler [1] See Table 34–635. Applications Exception handlers Privileged or unprivileged [1] Always privileged Main stack or process stack [1] Main stack 3.1.3 Core registers The processor core registers are: Table 627. Core register set summary Name Type [1] Required privilege [2] Reset value Description R0-R12 MSP PSP LR PC PSR ASPR IPSR UM10360_1 RW RW RW RW RW RW RW RO Either Privileged Either Either Either Privileged Either Privileged Undefined See description Undefined 0xFFFFFFFF Section 34–3.1.3.1 Section 34–3.1.3.2 Section 34–3.1.3.2 Section 34–3.1.3.3 Section 34–3.1.3.4 Section 34–3.1.3.5 Table 34–629 Table 34–630 © NXP B.V. 2010. All rights reserved. See description 0x01000000 0x00000000 0x00000000 User manual Rev. 01 — 4 January 2010 725 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Table 627. Core register set summary Name Type [1] Required privilege [2] Reset value 0x01000000 0x00000000 0x00000000 0x00000000 0x00000000 Description EPSR PRIMASK FAULTMASK BASEPRI CONTROL [1] [2] RO RW RW RW RW Privileged Privileged Privileged Privileged Privileged Table 34–631 Table 34–632 Table 34–633 Table 34–634 Table 34–635 Describes access type during program execution in thread mode and Handler mode. Debug access can differ. An entry of Either means privileged and unprivileged software can access the register. 3.1.3.1 General-purpose registers R0-R12 are 32-bit general-purpose registers for data operations. 3.1.3.2 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: On reset, the processor loads the MSP with the value from address 0 x00000000 . • 0 = Main Stack Pointer (MSP). This is the reset value. • 1 = Process Stack Pointer (PSP). 3.1.3.3 Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0 xFFFFFFFF. 3.1.3.4 Program Counter The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is always 0 because instruction fetches must be halfword aligned. On reset, the processor loads the PC with the value of the reset vector, which is at address 0 x00000004 . 3.1.3.5 Program Status Register The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 726 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide The PSR bit assignments are: Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the M SR or M RS instructions. For example: • read all of the registers using P SR with the M RS instruction • write to the APSR using A PSR with the M SR instruction. The PSR combinations and attributes are: Table 628. PSR register combinations Register Type Combination PSR IEPSR IAPSR EAPSR [1] [2] RW[1][2] RO RW[1] RW[2] APSR, EPSR, and IPSR EPSR and IPSR APSR and IPSR APSR and EPSR The processor ignores writes to the IPSR bits. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits See the instruction descriptions Section 34–2.10.6 “MRS” and Section 34–2.10.7 “MSR” for more information about how to access the program status registers. Application Program Status Register: The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 34–627 for its attributes. The bit assignments are: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 727 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Table 629. APSR bit assignments Bits Name Function [31] N Negative or less than flag: 0 = operation result was positive, zero, greater than, or equal 1 = operation result was negative or less than. [30] Z Zero flag: 0 = operation result was not zero 1 = operation result was zero. [29] C Carry or borrow flag: 0 = add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1 = add operation resulted in a carry bit or subtract operation did not result in a borrow bit. [28] V Overflow flag: 0 = operation did not result in an overflow 1 = operation resulted in an overflow. [27] Q Sticky saturation flag: 0 = indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1 = indicates when an S SAT or U SAT instruction results in saturation. This bit is cleared to zero by software using an M RS instruction. [26:0] - Reserved. Interrupt Program Status Register: The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 34–627 for its attributes. The bit assignments are: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 728 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Table 630. IPSR bit assignments Bits Name Function [31:9] [8:0] ISR_NUMBER Reserved This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault 4 = Memory management fault 5 = Bus fault 6 = Usage fault 7-10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 17 = IRQ1, first device specific interrupt . . 255 = IRQ243 (last implemented interrupt depends on device) see Section 34–3.3.2 for more information. Execution Program Status Register: The EPSR contains the Thumb state bit, and the execution state bits for either the: • If-Then (IT) instruction • Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. See the register summary in Table 34–627 for the EPSR attributes. The bit assignments are: Table 631. EPSR bit assignments Bits Name Function [31:27] [26:25], [15:10] [26:25], [15:10] [24] [23:16] [9:0] ICI IT T - Reserved. Interruptible-continuable instruction bits, see Section 34–. Indicates the execution state bits of the I T instruction, see Section 34–2.9.3 “IT”. Always set to 1. Reserved. Reserved. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 729 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Attempts to read the EPSR directly through application software using the M SR instruction always return zero. Attempts to write the EPSR using the M SR instruction in application software are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault. See Section 34–3.3.7 Interruptible-continuable instructions: When an interrupt occurs during the execution of an L DM or S TM instruction, the processor: After servicing the interrupt, the processor: • stops the load multiple or store multiple instruction operation temporarily. • stores the next register operand in the multiple operation to EPSR bits[15:12]. • returns to the register pointed to by bits[15:12]. • resumes execution of the multiple load or store instruction. When the EPSR holds ICI execution state, bits[26:25,11:10] are zero. If-Then block: The If-Then block contains up to four instructions following a 16-bit I T instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See Section 34–2.9.3 “IT” for more information. 3.1.3.6 Exception mask registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the M SR and M RS instructions, or the C PS instruction to change the value of PRIMASK or FAULTMASK. See Section 34–2.10.6 “MRS”, Section 34–2.10.7 “MSR”, and Section 34–2.10.2 “CPS” for more information. Priority Mask Register: The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 34–627 for its attributes. The bit assignments are shown in Table 34–632. Table 632. PRIMASK register bit assignments Bits Name Function [31:1] [0] PRIMASK Reserved 0 = no effect 1 = prevents the activation of all exceptions with configurable priority. Fault Mask Register: The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). See the register summary in Table 34–627 for its attributes. The bit assignments are shown in Table 34–633. Table 633. FAULTMASK register bit assignments Bits Name Function [31:1] [0] FAULTMASK Reserved 0 = no effect 1 = prevents the activation of all exceptions except for NMI. The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 730 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Base Priority Mask Register: The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 34–627 for its attributes. The bit assignments are shown in Table 34–634. Table 634. BASEPRI register bit assignments Bits Name Function [31:8] [7:0] BASEPRI [1] Reserved Priority mask bits: 0x0000 = no effect Nonzero = defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI. [1] This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:M] of this field, bits[M-1:0] read as zero and ignore writes. The value of M depends on the specific device. See Section 34–4.2.7 “Interrupt Priority Registers” for more information. Remember that higher priority field values correspond to lower exception priorities. 3.1.3.7 CONTROL register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 34–627 for its attributes. The bit assignments are shown in Table 34–635. Table 635. CONTROL register bit assignments Bits Name Function [31:2] [1] Active stack pointer Reserved Defines the current stack: 0 = MSP is the current stack pointer 1 = PSP is the current stack pointer. In Handler mode this bit reads as zero and ignores writes. [0] Thread mode privilege level Defines the Thread mode privilege level: 0 = privileged 1 = unprivileged. Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register. In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack. By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the M SR instruction to set the Active stack pointer bit to 1, see Section 34–2.10.7 “MSR”. Remark: When changing the stack pointer, software must use an I SB instruction immediately after the M SR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See Section 34–2.10.5 “ISB” UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 731 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 3.1.4 Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See Section 34–3.3.7.1 and Section 34–3.3.7.2 for more information. The NVIC registers control interrupt handling. See Section 34–4.2 “Nested Vectored Interrupt Controller” for more information. 3.1.5 Data types The processor: • supports the following data types: – 32-bit words – 16-bit halfwords – 8-bit bytes • supports 64-bit data transfer instructions. • manages all data memory accesses as little-endian. See Section 34–3.2.1 for more information. 3.1.6 The Cortex Microcontroller Software Interface Standard For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines: • a common way to: – access peripheral registers – define exception vectors • the names of: – the registers of the core peripherals – the core exception vectors • a device-independent interface for RTOS kernels, including a debug channel. The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3 processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack and a Flash file system. CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. Remark: This document uses the register short names defined by the CMSIS. In a few cases these differ from the architectural short names that might be used in other documents. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 732 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide The following sections give more information about the CMSIS: • • • • Section 34–3.5.4 Section 34–2.2 “Intrinsic functions” Section 34–4.2.1 “The CMSIS mapping of the Cortex-M3 NVIC registers” Section 34–4.2.10.1 “NVIC programming hints”. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 733 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide 3.2 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see Section 34–3.2.5. The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see Section 34–4.1 “About the Cortex-M3 peripherals”. 3.2.1 Memory regions, types and attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 734 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide • Normal: The processor can re-order transactions for efficiency, or perform speculative reads. • Device: The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. • Strongly-ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. The additional memory attributes include. • Shareable For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, software must ensure data coherency between the bus masters. • Execute Never (XN) Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an XN region causes a memory management fault exception. 3.2.2 Memory system ordering of memory accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see Section 34–3.2.4. However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses caused by two instructions is: Where: ‘—’ means that the memory system does not guarantee the ordering of the accesses. UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 735 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide ‘> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 800 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 3. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Ordering information . . . . . . . . . . . . . . . . . . . . .7 Ordering options for LPC17xx parts . . . . . . . . . .7 LPC17xx memory usage and details . . . . . . . .12 APB0 peripherals and base addresses . . . . . .14 APB1 peripherals and base addresses . . . . . .15 Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .17 Summary of system control registers . . . . . . . .18 Reset Source Identification register (RSID address 0x400F C180) bit description . . . . . . .21 External Interrupt registers . . . . . . . . . . . . . . . .24 External Interrupt Flag register (EXTINT - address 0x400F C140) bit description . . . . . . . . . . . . . .25 External Interrupt Mode register (EXTMODE address 0x400F C148) bit description . . . . . . .26 External Interrupt Polarity register (EXTPOLAR address 0x400F C14C) bit description . . . . . . .26 System Controls and Status register (SCS address 0x400F C1A0) bit description . . . . . . .28 Summary of system control registers . . . . . . . .30 Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode (OSCRANGE = 0, see Table 3–13) . . . . . . . . . . . . . . . . . . . . . .32 Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) high frequency mode (OSCRANGE = 1, see Table 3–13) . . . . . . . . . . . . . . . . . . . . . .32 Clock Source Select register (CLKSRCSEL address 0x400F C10C) bit description . . . . . . .34 PLL0 registers . . . . . . . . . . . . . . . . . . . . . . . . .36 PLL Control register (PLL0CON - address 0x400F C080) bit description . . . . . . . . . . . . . .37 PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description . . . . . . . . . . . . . .37 Multiplier values for PLL0 with a 32 kHz input .38 PLL Status register (PLL0STAT - address 0x400F C088) bit description . . . . . . . . . . . . . .39 PLL control bit combinations . . . . . . . . . . . . . .40 PLL Feed register (PLL0FEED - address 0x400F C08C) bit description . . . . . . . . . . . . . .40 PLL frequency parameter . . . . . . . . . . . . . . . . .41 Additional Multiplier Values for use with a Low Frequency Clock Input . . . . . . . . . . . . . . . . . . .42 Summary of PLL0 examples . . . . . . . . . . . . . .43 Potential values for PLL example . . . . . . . . . . .45 PLL1 registers . . . . . . . . . . . . . . . . . . . . . . . . .47 PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description . . . . . . . . . . . . . .50 Table 31. PLL Configuration register (PLL1CFG - address 0x400F C0A4) bit description. . . . . . . . . . . . . . 50 Table 32. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description. . . . . . . . . . . . . . 51 Table 33. PLL1 control bit combinations . . . . . . . . . . . . . 51 Table 34. PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description . . . . . . . . . . . . . 52 Table 35. Elements determining PLL frequency . . . . . . . 53 Table 36. PLL1 Divider values . . . . . . . . . . . . . . . . . . . . 54 Table 37. PLL1 Multiplier values . . . . . . . . . . . . . . . . . . . 54 Table 38. CPU Clock Configuration register (CCLKCFG address 0x400F C104) bit description . . . . . . . 55 Table 39. USB Clock Configuration register (USBCLKCFG address 0x400F C108) bit description . . . . . . . 56 Table 40. Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit description. . . . . . 57 Table 41. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0x400F C1AC) bit description . . . . . 57 Table 42. Peripheral Clock Selection register bit values . 58 Table 43. Power Control registers . . . . . . . . . . . . . . . . . . 61 Table 44. Power Mode Control register (PCON - address 0x400F C0C0) bit description . . . . . . . . . . . . . 62 Table 45. Encoding of reduced power modes . . . . . . . . . 63 Table 46. Power Control for Peripherals register (PCONP address 0x400F C0C4) bit description. . . . . . . 64 Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description 67 Table 48. Summary of flash accelerator registers . . . . . . 70 Table 49. Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 50. Connection of interrupt sources to the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . 74 Table 51. NVIC register map . . . . . . . . . . . . . . . . . . . . . 77 Table 52. Interrupt Set-Enable Register 0 register (ISER0 0xE000 E100) . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 53. Interrupt Set-Enable Register 1 register (ISER1 0xE000 E104) . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 54. Interrupt Clear-Enable Register 0 (ICER0 0xE000 E180) . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 55. Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 56. Interrupt Set-Pending Register 0 register (ISPR0 0xE000 E200) . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 57. Interrupt Set-Pending Register 1 register (ISPR1 0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 58. Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) . . . . . . . . . . . . . . . . . 84 Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 801 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 0x4002 C044) bit description . . . . . . . . . . . . . 110 Table 88. Pin Mode select register 2 (PINMODE2 - address 0x4002 C048) bit description . . . . . . . . . . . . . 111 Table 89. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description. . . . . . . . . . . . . 111 Table 90. Pin Mode select register 4 (PINMODE4 - address 0x4002 C050) bit description . . . . . . . . . . . . . 112 Table 91. Pin Mode select register 7 (PINMODE7 - address 0x4002 C05C) bit description. . . . . . . . . . . . . 113 Table 92. Pin Mode select register 9 (PINMODE9 - address 0x4002 C064) bit description . . . . . . . . . . . . . 113 Table 93. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 94. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 95. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 96. Open Drain Pin Mode select register 3 (PINMODE_OD3 - address 0x4002 C074) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 97. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 98. I2C Pin Configuration register (I2CPADCFG address 0x4002 C07C) bit description. . . . . . 117 Table 99. GPIO pin description . . . . . . . . . . . . . . . . . . . 119 Table 100.GPIO register map (local bus accessible registers - enhanced GPIO features) . . . . . . . . . . . . . . 120 Table 101.GPIO interrupt register map. . . . . . . . . . . . . . 121 Table 102.Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to 0x2009 C080) bit description . . . . . . . . . . . . . . . . . . . 121 Table 103.Fast GPIO port Direction control byte and half-word accessible register description . . . . 122 Table 104.Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018 to 0x2009 C098) bit description . . . . . . . . . . . . . . . . . . . 123 Table 105.Fast GPIO port output Set byte and half-word accessible register description. . . . . . . . . . . . 123 Table 106.Fast GPIO port output Clear register (FIO0CLR to FIO4CLR- addresses 0x2009 C01C to 0x2009 C09C) bit description . . . . . . . . . . . . . . . . . . . 124 Table 107.Fast GPIO port output Clear byte and half-word accessible register description. . . . . . . . . . . . 124 Table 108.Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to 0x2009 C094) bit description . . . . . . . . . . . . . . . . . . . 125 Table 109.Fast GPIO port Pin value byte and half-word Table 59. Interrupt Set-Pending Register 1 register (ISPR1 0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 60. Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 61. Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000 E400) 88 Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000 E404) 88 Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000 E408) 88 Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000 E410) 89 Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000 E414) 89 Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418) 90 Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000 E41C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Table 70. Interrupt Priority Register 8 (IPR8 0xE000 E420) . . . . . . . . . . . . . . . . . . . . . . . . .90 Table 71. Software Trigger Interrupt Register (STIR 0xE000 EF00) . . . . . . . . . . . . . . . . . . . . . . . . .91 Table 72. Pin description . . . . . . . . . . . . . . . . . . . . . . . . .93 Table 73. Summary of PINSEL registers . . . . . . . . . . . .102 Table 74. Pin function select register bits . . . . . . . . . . . .102 Table 75. Pin Mode Select register Bits . . . . . . . . . . . . .103 Table 76. Open Drain Pin Mode Select register Bits . . .104 Table 77. Pin Connect Block Register Map . . . . . . . . . .105 Table 78. Pin function select register 0 (PINSEL0 - address 0x4002 C000) bit description . . . . . . . . . . . . .106 Table 79. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description . . . . . . . . . . . . .106 Table 80. Pin function select register 2 (PINSEL2 - address 0x4002 C008) bit description . . . . . . . . . . . . .107 Table 81. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description . . . . . . . . . . . .107 Table 82. Pin function select register 4 (PINSEL4 - address 0x4002 C010) bit description . . . . . . . . . . . . .108 Table 83. Pin function select register 7 (PINSEL7 - address 0x4002 C01C) bit description . . . . . . . . . . . .109 Table 84. Pin function select register 9 (PINSEL9 - address 0x4002 C024) bit description . . . . . . . . . . . . .109 Table 85. Pin function select register 10 (PINSEL10 address 0x4002 C028) bit description . . . . . .109 Table 86. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description . . . . . . . . . . . . . 110 Table 87. Pin Mode select register 1 (PINMODE1 - address continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 802 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Table 134.Maximum Frame register (MAXF - address 0x5000 0014) bit description . . . . . . . . . . . . . 151 Table 135.PHY Support register (SUPP - address 0x5000 0018) bit description . . . . . . . . . . . . . 151 Table 136. Test register (TEST - address 0x5000 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 137.MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description . . . . . . . . . . . . . 152 Table 138. Clock select encoding . . . . . . . . . . . . . . . . . . 152 Table 139.MII Mgmt Command register (MCMD - address 0x5000 0024) bit description . . . . . . . . . . . . . 153 Table 140.MII Mgmt Address register (MADR - address 0x5000 0028) bit description . . . . . . . . . . . . . 153 Table 141.MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description . . . . . . . . . . . . . 154 Table 142.MII Mgmt Read Data register (MRDD - address 0x5000 0030) bit description . . . . . . . . . . . . . 154 Table 143.MII Mgmt Indicators register (MIND - address 0x5000 0034) bit description . . . . . . . . . . . . . 154 Table 144.Station Address register (SA0 - address 0x5000 0040) bit description . . . . . . . . . . . . . 155 Table 145.Station Address register (SA1 - address 0x5000 0044) bit description . . . . . . . . . . . . . 155 Table 146.Station Address register (SA2 - address 0x5000 0048) bit description . . . . . . . . . . . . . 155 Table 147.Command register (Command - address 0x5000 0100) bit description . . . . . . . . . . . . . 156 Table 148.Status register (Status - address 0x5000 0104) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 149.Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 150.receive Status Base Address register (RxStatus address 0x5000 010C) bit description . . . . . . 157 Table 151.Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 152.Receive Produce Index register (RxProduceIndex - address 0x5000 0114) bit description . . . . . 158 Table 153.Receive Consume Index register (RxConsumeIndex - address 0x5000 0118) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 154.Transmit Descriptor Base Address register (TxDescriptor - address 0x5000 011C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 155.Transmit Status Base Address register (TxStatus address 0x5000 0120) bit description . . . . . . 159 Table 156.Transmit Number of Descriptors register (TxDescriptorNumber - address 0x5000 0124) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 157.Transmit Produce Index register (TxProduceIndex accessible register description . . . . . . . . . . . .126 Table 110. Fast GPIO port Mask register (FIO0MASK to FIO4MASK - addresses 0x2009 C010 to 0x2009 C090) bit description. . . . . . . . . . . . . . . . . . . .127 Table 111. Fast GPIO port Mask byte and half-word accessible register description . . . . . . . . . . . .127 Table 112. GPIO overall Interrupt Status register (IOIntStatus - address 0x4002 8080) bit description . . . . .129 Table 113. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description . . .129 Table 114. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description . . .130 Table 115. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Table 116. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit description . . .132 Table 117. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Table 118. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Table 119. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Table 120.GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Table 121.GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description . . . . . . . . . . .136 Table 122.GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) bit description . . . . . . . . . . . .137 Table 123.Ethernet acronyms, abbreviations, and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Table 124.Example PHY Devices . . . . . . . . . . . . . . . . . .145 Table 125.Ethernet RMII pin descriptions . . . . . . . . . . . .145 Table 126.Ethernet MIIM pin descriptions . . . . . . . . . . . .145 Table 127.Ethernet register definitions . . . . . . . . . . . . . .146 Table 128.MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description . . . . . . . . . . . . .148 Table 129.MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description . . . . . . . . . . . . .149 Table 130. Pad operation . . . . . . . . . . . . . . . . . . . . . . . .150 Table 131.Back-to-back Inter-packet-gap register (IPGT address 0x5000 0008) bit description. . . . . . .150 Table 132. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Table 133.Collision Window / Retry register (CLRT - address 0x5000 0010) bit description . . . . . . . . . . . . .151 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 803 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Table 187.USB device register map . . . . . . . . . . . . . . . . 218 Table 188.USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description. . . . . . . . . . . . . 219 Table 189.USB Clock Status register (USBClkSt - address 0x5000 CFF8) bit description. . . . . . . . . . . . . 220 Table 190.USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description. . . . . . . . . . . . . 220 Table 191.USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 192.USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 193.USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 194.USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 195.USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 196.USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 197.USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit allocation . . . . . 223 Table 198.USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit description . . . . 223 Table 199.USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 200.USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 201.USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 202.USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 203.USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 204.USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 205.USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Table 206.USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 0128) bit description . . . . .160 Table 158.Transmit Consume Index register (TxConsumeIndex - address 0x5000 012C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Table 159. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description . . . . . . . . . . . . .161 Table 160.Transmit Status Vector 1 register (TSV1 - address 0x5000 015C) bit description . . . . . . . . . . . . .162 Table 161.Receive Status Vector register (RSV - address 0x5000 0160) bit description . . . . . . . . . . . . .162 Table 162.Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Table 163.Flow Control Status register (FlowControlStatus address 0x5000 8174) bit description. . . . . . .163 Table 164.Receive Filter Control register (RxFilterCtrl address 0x5000 0200) bit description. . . . . . .164 Table 165.Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Table 166.Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Table 167.Hash Filter Table LSBs register (HashFilterL address 0x5000 0210) bit description. . . . . . .165 Table 168.Hash Filter MSBs register (HashFilterH - address 0x5000 0214) bit description . . . . . . . . . . . . .166 Table 169.Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description . . . . . . . . . . . . .166 Table 170.Interrupt Enable register (intEnable - address 0x5000 0FE4) bit description . . . . . . . . . . . . .167 Table 171.Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description . . . . . . . . . . . . .168 Table 172.Interrupt Set register (IntSet - address 0x5000 0FEC) bit description . . . . . . . . . . . . .168 Table 173.Power-Down register (PowerDown - address 0x5000 0FF4) bit description . . . . . . . . . . . . .169 Table 174.Receive Descriptor Fields. . . . . . . . . . . . . . . .171 Table 175.Receive Descriptor Control Word . . . . . . . . . .171 Table 176.Receive Status Fields . . . . . . . . . . . . . . . . . . .171 Table 177.Receive Status HashCRC Word . . . . . . . . . . .172 Table 178.Receive status information word. . . . . . . . . . .172 Table 179.Transmit descriptor fields . . . . . . . . . . . . . . . .174 Table 180.Transmit descriptor control word . . . . . . . . . .174 Table 181.Transmit status fields . . . . . . . . . . . . . . . . . . .174 Table 182.Transmit status information word . . . . . . . . . .175 Table 183.USB related acronyms, abbreviations, and definitions used in this chapter . . . . . . . . . . . .212 Table 184.Fixed endpoint configuration. . . . . . . . . . . . . .213 Table 185.USB external interface . . . . . . . . . . . . . . . . . .216 Table 186.USB device controller clock sources . . . . . . .217 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 804 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information (USBDMAIntEn - address 0x5000 C294) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 231.USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 232.USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 233.USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0x5000 C2A8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 234.USB New DD Request Interrupt Status register (USBNDDRIntSt - address 0x5000 C2AC) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 235.USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0x5000 C2B0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 236.USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 237.USB System Error Interrupt Status register (USBSysErrIntSt - address 0x5000 C2B8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 238.USB System Error Interrupt Clear register (USBSysErrIntClr - address 0x5000 C2BC) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 239.USB System Error Interrupt Set register (USBSysErrIntSet - address 0x5000 C2C0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 240.SIE command code table . . . . . . . . . . . . . . . . 243 Table 241.Set Address command bit description . . . . . . 243 Table 242.Configure Device command bit description . . 244 Table 243.Set Mode command bit description . . . . . . . . 244 Table 244.Set Device Status command bit description. . 245 Table 245.Get Error Code command bit description. . . . 247 Table 246.Read Error Status command bit description . 247 Table 247.Select Endpoint command bit description . . . 248 Table 248.Set Endpoint Status command bit description 249 Table 249.Clear Buffer command bit description . . . . . . 250 Table 250.DMA descriptor . . . . . . . . . . . . . . . . . . . . . . . 255 Table 251.USB (OHCI) related acronyms and abbreviations used in this chapter . . . . . . . . . . . . . . . . . . . . 267 Table 252.USB Host port pins . . . . . . . . . . . . . . . . . . . . 269 Table 253.USB Host register address definitions . . . . . 269 Table 254.USB OTG port pins . . . . . . . . . . . . . . . . . . . . 273 Table 255.USB OTG and I2C register address definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Table 256.USB Interrupt Status register - (USBIntSt address 0x5000 C1C0) bit description. . . . . . 275 Table 257.OTG Interrupt Status register (OTGIntSt - address 0x5000 C100) bit description . . . . . . . . . . . . . 276 - address 0x5000 C23C) bit allocation . . . . .227 Table 207.USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit description . . . .227 Table 208.USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Table 209.USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .228 Table 210.USB Realize Endpoint register (USBReEp address 0x5000 C244) bit allocation . . . . . .229 Table 211. USB Realize Endpoint register (USBReEp address 0x5000 C244) bit description . . . . . .229 Table 212.USB Endpoint Index register (USBEpIn - address 0x5000 C248) bit description . . . . . . . . . . . . .230 Table 213.USB MaxPacketSize register (USBMaxPSize address 0x5000 C24C) bit description. . . . . .230 Table 214.USB Receive Data register (USBRxData address 0x5000 C218) bit description . . . . . .231 Table 215.USB Receive Packet Length register (USBRxPlen - address 0x5000 C220) bit description . . . . .231 Table 216.USB Transmit Data register (USBTxData address 0x5000 C21C) bit description. . . . . .231 Table 217.USB Transmit Packet Length register (USBTxPLen - address 0x5000 C224) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Table 218.USB Control register (USBCtrl - address 0x5000 C228) bit description . . . . . . . . . . . . . . . . . . .232 Table 219.USB Command Code register (USBCmdCode address 0x5000 C210) bit description . . . . . .233 Table 220.USB Command Data register (USBCmdData address 0x5000 C214) bit description . . . . . .233 Table 221.USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit allocation . . . . .233 Table 222.USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit description . . . . .234 Table 223.USB DMA Request Clear register (USBDMARClr - address 0x5000 C254) bit description . . . . .234 Table 224.USB DMA Request Set register (USBDMARSet address 0x5000 C258) bit description . . . . . .235 Table 225.USB UDCA Head register (USBUDCAH - address 0x5000 C280) bit description . . . . . . . . . . . . .235 Table 226.USB EP DMA Status register (USBEpDMASt address 0x5000 C284) bit description . . . . . .235 Table 227.USB EP DMA Enable register (USBEpDMAEn address 0x5000 C288) bit description . . . . . .236 Table 228.USB EP DMA Disable register (USBEpDMADis address 0x5000 C28C) bit description. . . . . .236 Table 229.USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description . . . . .236 Table 230.USB DMA Interrupt Enable register continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 805 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 0x4009 C00C) bit description. . . . . . . . . . . . . 304 Table 279:UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR 0x4009 C014) bit description . . . . . . . . . . . . . 305 Table 280:UARTn Scratch Pad Register (U0SCR - address 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR 0x4009 C01C) bit description. . . . . . . . . . . . . 306 Table 281:UARTn Auto-baud Control Register (U0ACR address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR - 0x4009 C020) bit description . . . . . 306 Table 282:UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit description . . . . . . . . . . . . . . . . . . . 309 Table 283:IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . . 310 Table 284:UARTn Fractional Divider Register (U0FDR address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR - 0x4009 C028) bit description . . . . . 310 Table 285.Fractional Divider setting look-up table . . . . . 313 Table 286:UARTn Transmit Enable Register (U0TER address 0x4000 C030, U2TER - 0x4009 8030, U3TER - 0x4009 C030) bit description . . . . . 314 Table 287.UARTn FIFO Level register (U0FIFOLVL - 0x4000 C058, U2FIFOLVL - 0x4009 8058, U3FIFOLVL 0x4009 C058) bit description . . . . . . . . . . . . . 314 Table 288:UART1 Pin Description . . . . . . . . . . . . . . . . . 317 Table 289:UART1 register map . . . . . . . . . . . . . . . . . . . 318 Table 290:UART1 Receiver Buffer Register (U1RBR address 0x4001 0000 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Table 291:UART1 Transmitter Holding Register (U1THR address 0x4001 0000 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Table 292:UART1 Divisor Latch LSB Register (U1DLL address 0x4001 0000 when DLAB = 1) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Table 293:UART1 Divisor Latch MSB Register (U1DLM address 0x4001 0004 when DLAB = 1) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Table 294:UART1 Interrupt Enable Register (U1IER address 0x4001 0004 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Table 295:UART1 Interrupt Identification Register (U1IIR address 0x4001 0008) bit description . . . . . . 321 Table 296:UART1 Interrupt Handling . . . . . . . . . . . . . . . 322 Table 297:UART1 FIFO Control Register (U1FCR - address 0x4001 0008) bit description . . . . . . . . . . . . . 323 Table 298:UART1 Line Control Register (U1LCR - address 0x4001 000C) bit description . . . . . . . . . . . . . 324 Table 299:UART1 Modem Control Register (U1MCR address 0x4001 0010) bit description . . . . . . 325 Table 300:Modem status interrupt generation . . . . . . . . 326 Table 258.OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description . . . . . . . . . . . . .277 Table 259.OTG Timer register (OTGTmr - address 0x5000 C114) bit description . . . . . . . . . . . . .278 Table 260.OTG clock control register (OTG_clock_control address 0x5000 CFF4) bit description . . . . . .278 Table 261.OTG clock status register (OTGClkSt - address 0x5000 CFF8) bit description . . . . . . . . . . . . .279 Table 262.I2C Receive register (I2C_RX - address 0x5000 C300) bit description . . . . . . . . . . . . .280 Table 263.I2C Transmit register (I2C_TX - address 0x5000 C300) bit description . . . . . . . . . . . . .280 Table 264.I2C status register (I2C_STS - address 0x5000 C304) bit description . . . . . . . . . . . . .280 Table 265.I2C Control register (I2C_CTL - address 0x5000 C308) bit description . . . . . . . . . . . . .282 Table 266.I2C_CLKHI register (I2C_CLKHI - address 0x5000 C30C) bit description . . . . . . . . . . . . .283 Table 267.I2C_CLKLO register (I2C_CLKLO - address 0x5000 C310) bit description . . . . . . . . . . . . .283 Table 268:UARTn Pin description . . . . . . . . . . . . . . . . . .297 Table 269.UART0/2/3 Register Map . . . . . . . . . . . . . . . .298 Table 270:UARTn Receiver Buffer Register (U0RBR address 0x4000 C000, U2RBR - 0x4009 8000, U3RBR - 04009 C000 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .299 Table 271:UARTn Transmit Holding Register (U0THR address 0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .299 Table 272:UARTn Divisor Latch LSB register (U0DLL address 0x4000 C000, U2DLL - 0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .300 Table 273:UARTn Divisor Latch MSB register (U0DLM address 0x4000 C004, U2DLM - 0x4009 8004, U3DLM - 0x4009 C004 when DLAB = 1) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .300 Table 274:UARTn Interrupt Enable Register (U0IER address 0x4000 C004, U2IER - 0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .300 Table 275:UARTn Interrupt Identification Register (U0IIR address 0x4000 C008, U2IIR - 0x4009 8008, U3IIR - 0x4009 C008) bit description . . . . . . .301 Table 276:UARTn Interrupt Handling . . . . . . . . . . . . . . .302 Table 277:UARTn FIFO Control Register (U0FCR - address 0x4000 C008, U2FCR - 0x4009 8008, U3FCR 0x4007 C008) bit description . . . . . . . . . . . . .303 Table 278:UARTn Line Control Register (U0LCR - address 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR - continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 806 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Table 325.CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 361 Table 326.CAN Receive Frame Status register (CAN1RFS address 0x4004 4020, CAN2RFS - address 0x4004 8020) bit description . . . . . . . . . . . . . 363 Table 327.CAN Receive Identifier register (CAN1RID address 0x4004 4024, CAN2RID - address 0x4004 8024) bit description . . . . . . . . . . . . . 364 Table 328.RX Identifier register when FF = 1 . . . . . . . . . 364 Table 329.CAN Receive Data register A (CAN1RDA address 0x4004 4028, CAN2RDA - address 0x4004 8028) bit description . . . . . . . . . . . . . 364 Table 330.CAN Receive Data register B (CAN1RDB address 0x4004 402C, CAN2RDB - address 0x4004 802C) bit description . . . . . . . . . . . . . 364 Table 331.CAN Transmit Frame Information register (CAN1TFI[1/2/3] - address 0x4004 40[30/40/50], CAN2TFI[1/2/3] - 0x4004 80[30/40/50]) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Table 332.CAN Transfer Identifier register (CAN1TID[1/2/3] address 0x4004 40[34/44/54], CAN2TID[1/2/3] address 0x4004 80[34/44/54]) bit description 366 Table 333.Transfer Identifier register when FF = 1. . . . . 367 Table 334.CAN Transmit Data register A (CAN1TDA[1/2/3] address 0x4004 40[38/48/58], CAN2TDA[1/2/3] address 0x4004 80[38/48/58]) bit description 367 Table 335.CAN Transmit Data register B (CAN1TDB[1/2/3] address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] address 0x4004 80[3C/4C/5C]) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Table 336.CAN Sleep Clear register (CANSLEEPCLR address 0x400F C110) bit description . . . . . . 368 Table 337.CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description . . . . . 368 Table 338.Central Transit Status Register (CANTxSR address 0x4004 0000) bit description . . . . . . 370 Table 339.Central Receive Status Register (CANRxSR address 0x4004 0004) bit description . . . . . . 370 Table 340.Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description . . . . . 371 Table 341.Acceptance filter modes and access control . 371 Table 342.Section configuration register settings . . . . . . 372 Table 343.Acceptance Filter Mode Register (AFMR address 0x4003 C000) bit description . . . . . . 375 Table 344.Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Table 345.Standard Frame Group Start Address register (SFF_GRP_sa - address 0x4003 C008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Table 301:UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description . . . . . . . . . . . . .327 Table 302:UART1 Modem Status Register (U1MSR address 0x4001 0018) bit description. . . . . . .328 Table 303:UART1 Scratch Pad Register (U1SCR - address 0x4001 0014) bit description . . . . . . . . . . . . .329 Table 304:Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description . . . . . . . . . . . . .329 Table 305:UART1 Fractional Divider Register (U1FDR address 0x4001 0028) bit description. . . . . . .333 Table 306.Fractional Divider setting look-up table. . . . . .335 Table 307:UART1 Transmit Enable Register (U1TER address 0x4001 0030) bit description. . . . . . .336 Table 308:UART1 RS485 Control register (U1RS485CTRL address 0x4001 004C) bit description . . . . . .336 Table 309.UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description . . . . . . . . . . . . . . . . . . . . . . . . .337 Table 310.UART1 RS-485 Delay value register (U1RS485DLY - address 0x4001 0054) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .337 Table 311. UART1 FIFO Level register (U1FIFOLVL address 0x4001 0058) bit description. . . . . . .339 Table 312.CAN Pin descriptions . . . . . . . . . . . . . . . . . . .342 Table 313.Memory map of the CAN block. . . . . . . . . . . .347 Table 314.CAN acceptance filter and central CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 Table 315.CAN1 and CAN2 controller register map . . . .347 Table 316.CAN1 and CAN2 controller register summary 349 Table 317.CAN Wake and Sleep registers . . . . . . . . . . .349 Table 318.CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description . . . . . . . . . . . . .350 Table 319.CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description . . . . . . . . . . . . . . . . . . . . . . . . .351 Table 320.CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit description . . . . . . . . . . . . . . . . . . . . . . . . .353 Table 321.CAN Interrupt and Capture Register (CAN1ICR address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description . . . . . . . . . . . . .355 Table 322.CAN Interrupt Enable Register (CAN1IER address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description . . . . . . . . . . . . .358 Table 323.CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description . . . . . . . . . . . . . . . . . . . . . . . . .359 Table 324.CAN Error Warning Limit register (CAN1EWL address 0x4004 4018, CAN2EWL - address 0x4004 8018) bit description . . . . . . . . . . . . .361 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 807 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 0x4008 8008, SSP1DR - 0x4003 0008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Table 374:SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Table 375:SSPn Clock Prescale Register (SSP0CPSR address 0x4008 8010, SSP1CPSR 0x4003 0010) bit description . . . . . . . . . . . . . 422 Table 376:SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014, SSP1IMSC 0x4003 0014) bit description . . . . . . . . . . . . . 423 Table 377:SSPn Raw Interrupt Status register (SSP0RIS address 0x4008 8018, SSP1RIS - 0x4003 0018) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 423 Table 378:SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS 0x4003 001C) bit description . . . . . . . . . . . . . 424 Table 379:SSPn interrupt Clear Register (SSP0ICR address 0x4008 8020, SSP1ICR - 0x4003 0020) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 424 Table 380:SSPn DMA Control Register (SSP0DMACR address 0x4008 8024, SSP1DMACR 0x4003 0024) bit description . . . . . . . . . . . . . 424 Table 381.I2C Pin Description. . . . . . . . . . . . . . . . . . . . . 427 Table 382.I2C0CONSET and I2C1CONSET used to configure Master mode . . . . . . . . . . . . . . . . . 428 Table 383.I2C0CONSET and I2C1CONSET used to configure Slave mode . . . . . . . . . . . . . . . . . . 430 Table 384.I2C register map . . . . . . . . . . . . . . . . . . . . . . . 436 Table 385.I2C Control Set register (I2CONSET: I2C0, I2C0CONSET - address 0x4001 C000, I2C1, I2C1CONSET - address 0x4005 C000, I2C2, I2C2CONSET - address 0x400A 0000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Table 386.I2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR - 0x4001 C018; I2C1, I2C1CONCLR - 0x4005 C018; I2C2, I2C2CONCLR - 0x400A 0018) bit description 439 Table 387.I2C Status register (I2STAT: I2C0, I2C0STAT 0x4001 C004; I2C1, I2C1STAT - 0x4005 C004; I2C2, I2C2STAT - 0x400A 0004) bit description. . 440 Table 388.I2C Data register (I2DAT: I2C0, I2C0DAT 0x4001 C008; I2C1, I2C1DAT - 0x4005 C008; I2C2, I2C2DAT - 0x400A 0008) bit description441 Table 389.I2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C; I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) bit description 441 Table 390.I2C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER - 0x4001 C02C; I2C1, Table 346.Extended Frame Start Address register (EFF_sa address 0x4003 C00C) bit description . . . . . .376 Table 347.Extended Frame Group Start Address register (EFF_GRP_sa - address 0x4003 C010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .377 Table 348.End of AF Tables register (ENDofTable - address 0x4003 C014) bit description . . . . . . . . . . . . .377 Table 349.LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description . . . . . . . . . . . . .378 Table 350.LUT Error register (LUTerr - address 0x4003 C01C) bit description . . . . . . . . . . . . .378 Table 351.Global FullCAN Enable register (FCANIE address 0x4003 C020) bit description . . . . . .378 Table 352.FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .378 Table 353.FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0x4003 C028) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .379 Table 354.Format of automatically stored Rx messages.382 Table 355.FullCAN semaphore operation . . . . . . . . . . . .382 Table 356.Example of Acceptance Filter Tables and ID index Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 Table 357.Used ID-Look-up Table sections. . . . . . . . . . .394 Table 358.Used ID-Look-up Table sections. . . . . . . . . . .395 Table 359.SPI pin description . . . . . . . . . . . . . . . . . . . . .400 Table 360.SPI Data To Clock Phase Relationship. . . . . .401 Table 361.SPI register map . . . . . . . . . . . . . . . . . . . . . . .404 Table 362:SPI Control Register (S0SPCR - address 0x4002 0000) bit description . . . . . . . . . . . . .405 Table 363:SPI Status Register (S0SPSR - address 0x4002 0004) bit description . . . . . . . . . . . . .406 Table 364:SPI Data Register (S0SPDR - address 0x4002 0008) bit description . . . . . . . . . . . . .406 Table 365:SPI Clock Counter Register (S0SPCCR - address 0x4002 000C) bit description . . . . . . . . . . . . .407 Table 366:SPI Test Control Register (SPTCR - address 0x4002 0010) bit description . . . . . . . . . . . . .407 Table 367:SPI Test Status Register (SPTSR - address 0x4002 0014) bit description . . . . . . . . . . . . .407 Table 368:SPI Interrupt Register (S0SPINT - address 0x4002 001C) bit description . . . . . . . . . . . . .408 Table 369.SSP pin descriptions . . . . . . . . . . . . . . . . . . . 411 Table 370.SSP Register Map . . . . . . . . . . . . . . . . . . . . .419 Table 371:SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 - 0x4003 0000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .420 Table 372:SSPn Control Register 1 (SSP0CR1 - address 0x4008 8004, SSP1CR1 - 0x4003 0004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .421 Table 373:SSPn Data Register (SSP0DR - address continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 808 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Table 413:Interrupt Request Control register (I2SIRQ address 0x400A 801C) bit description . . . . . . 476 Table 414:Transmit Clock Rate register (I2TXRATE address 0x400A 8020) bit description . . . . . . 477 Table 415:Receive Clock Rate register (I2SRXRATE address 0x400A 8024) bit description . . . . . . 478 Table 416:Transmit Clock Rate register (I2TXBITRATE address 0x400A 8028) bit description . . . . . . 478 Table 417:Receive Clock Rate register (I2SRXBITRATE address 0x400A 802C) bit description . . . . . . 478 Table 418:Transmit Mode Control register (I2STXMODE 0x400A 8030) bit description . . . . . . . . . . . . . 479 Table 419:Receive Mode Control register (I2SRXMODE 0x400A 8034) bit description . . . . . . . . . . . . . 479 Table 420:I2S transmit modes . . . . . . . . . . . . . . . . . . . . 481 Table 421:I2S receive modes . . . . . . . . . . . . . . . . . . . . . 483 Table 422.Conditions for FIFO level comparison . . . . . . 485 Table 423.DMA and interrupt request generation. . . . . . 485 Table 424.Status feedback in the I2SSTATE register . . . 485 Table 425.Timer/Counter pin description . . . . . . . . . . . . 488 Table 426.TIMER/COUNTER0-3 register map. . . . . . . . 489 Table 427.Interrupt Register (T[0/1/2/3]IR - addresses 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000) bit description . . . . . . . . . . . . . 490 Table 428.Timer Control Register (TCR, TIMERn: TnTCR addresses 0x4000 4004, 0x4000 8004, 0x4009 0004, 0x4009 4004) bit description . . 491 Table 429.Count Control Register (T[0/1/2/3]CTCR addresses 0x4000 4070, 0x4000 8070, 0x4009 0070, 0x4009 4070) bit description . . 491 Table 430.Match Control Register (T[0/1/2/3]MCR addresses 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014) bit description . . 493 Table 431.Capture Control Register (T[0/1/2/3]CCR addresses 0x4000 4028, 0x4000 8020, 0x4009 0028, 0x4009 4028) bit description . . 494 Table 432.External Match Register (T[0/1/2/3]EMR addresses 0x4000 403C, 0x4000 803C, 0x4009 003C, 0x4009 403C) bit description . 495 Table 433.External Match Control . . . . . . . . . . . . . . . . . 495 Table 434.Repetitive Interrupt Timer register map . . . . . 498 Table 435.RI Compare Value register (RICOMPVAL address 0x400B 0000) bit description . . . . . . 498 Table 436.RI Compare Value register (RICOMPVAL address 0x400B 0004) bit description . . . . . . 498 Table 437.RI Control register (RICTRL - address 0x400B 0008) bit description. . . . . . . . . . . . . . . . . . . . 499 Table 438.RI Counter register (RICOUNTER - address 0x400B 000C) bit description. . . . . . . . . . . . . 499 Table 439.System Tick Timer register map. . . . . . . . . . . 502 Table 440.System Timer Control and status register I2C1DATA_BUFFER- 0x4005 C02C; I2C2, I2C2DATA_BUFFER- 0x400A 002C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .443 Table 391.I2C Slave Address registers (I2ADR0 to 3: I2C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28]; I2C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I2C2, I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28]) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .443 Table 392.I2C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C]; I2C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I2C2, I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .444 Table 393.I2C SCL HIGH Duty Cycle register (I2SCLH: I2C0, I2C0SCLH - address 0x4001 C010; I2C1, I2C1SCLH - address 0x4005 C010; I2C2, I2C2SCLH - 0x400A 0010) bit description . . .444 Table 394.I2C SCL Low duty cycle register (I2SCLL: I2C0 I2C0SCLL: 0x4001 C014; I2C1 - I2C1SCLL: 0x4005 C014; I2C2 - I2C2SCLL: 0x400A 0014) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .444 Table 395.Example I2C clock rates . . . . . . . . . . . . . . . . .445 Table 396.Abbreviations used to describe an I2C operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .446 Table 397.I2CONSET used to initialize Master Transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447 Table 398.I2CONSET used to initialize Slave Receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 Table 399.Master Transmitter mode . . . . . . . . . . . . . . . .454 Table 400.Master Receiver mode . . . . . . . . . . . . . . . . . .455 Table 401.Slave Receiver mode . . . . . . . . . . . . . . . . . . .456 Table 402.Slave Transmitter mode . . . . . . . . . . . . . . . . .458 Table 403.Miscellaneous States . . . . . . . . . . . . . . . . . . .459 Table 404.Pin descriptions . . . . . . . . . . . . . . . . . . . . . . .472 Table 405.I2S register map . . . . . . . . . . . . . . . . . . . . . . .473 Table 406:Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description . . . . . . . . . . . . .473 Table 407:Digital Audio Input register (I2SDAI - address 0x400A 8004) bit description . . . . . . . . . . . . .474 Table 408:Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description . . . . . . . . . . . . .474 Table 409:Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description . . . . . . . . . . . . .475 Table 410:Status Feedback register (I2SSTATE - address 0x400A 8010) bit description . . . . . . . . . . . . .475 Table 411: DMA Configuration register 1 (I2SDMA1 - address 0x400A 8014) bit description . . . . . . . . . . . . .475 Table 412:DMA Configuration register 2 (I2SDMA2 - address 0x400A 8018) bit description . . . . . . . . . . . . .476 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 809 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Table 467.MCPWM Interrupt Flags read address (MCINTF 0x400B 8068) bit description . . . . . . . . . . . . . 527 Table 468.MCPWM Interrupt Flags set address (PWMINTF_SET - 0x400B 806C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Table 469.MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 Table 470.MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description 528 Table 471.MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Table 472.MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Table 473.MCPWM Timer/Counter 0-2 registers (MCTC0-2 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Table 474.MCPWM Limit 0-2 registers (MCLIM0-2 0x400B 8024, 0x400B 8028, 0x400B 802C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Table 475.MCPWM Match 0-2 registers (MCMAT0-2 addresses 0x400B 8030, 0x400B 8034, 0x400B 8038) bit description . . . . . . . . . . . . . 531 Table 476.MCPWM Dead-time register (MCDT - address 0x400B 803C) bit description. . . . . . . . . . . . . 532 Table 477.MCPWM Commutation Pattern register (MCCP address 0x400B 8040) bit description . . . . . . 532 Table 478.MCPWM Capture read addresses (MCCAP0/1/2 0x400B 8044, 0x400B 8048, 0x400B 804C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 Table 479.MCPWM Capture clear address (CAP_CLR 0x400B 8074) bit description . . . . . . . . . . . . . 533 Table 480.Encoder states . . . . . . . . . . . . . . . . . . . . . . . . 542 Table 481.Encoder state transitions[1] . . . . . . . . . . . . . . 542 Table 482.Encoder direction . . . . . . . . . . . . . . . . . . . . . 543 Table 483.QEI pin description. . . . . . . . . . . . . . . . . . . . . 545 Table 484.QEI Register summary. . . . . . . . . . . . . . . . . . 546 Table 485:QEI Control register (QEICON - address 0x400B C000) bit description. . . . . . . . . . . . . 547 Table 486:QEI Configuration register (QEICONF - address 0x400B C008) bit description. . . . . . . . . . . . . 547 Table 487:QEI Interrupt Status register (QEISTAT - address 0x400B C004) bit description. . . . . . . . . . . . . 547 Table 488:QEI Position register (QEIPOS - address 0x400B C00C) bit description . . . . . . . . . . . . 548 Table 489:QEI Maximum Position register (QEIMAXPOS address 0x400B C010) bit description . . . . . . 548 Table 490:QEI Position Compare register 0 (CMPOS0 address 0x400B C014) bit description . . . . . . 548 (STCTRL - 0xE000 E010) bit description . . . .502 Table 441.System Timer Reload value register (STRELOAD - 0xE000 E014) bit description . . . . . . . . . . . .503 Table 442.System Timer Current value register (STCURR 0xE000 E018) bit description . . . . . . . . . . . . .503 Table 443.System Timer Calibration value register (STCALIB - 0xE000 E01C) bit description . . .504 Table 444.Set and reset inputs for PWM Flip-Flops . . . .509 Table 445.Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . .510 Table 446.PWM1 register map . . . . . . . . . . . . . . . . . . . . 511 Table 447:PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description . . . . . . . . . . . . .512 Table 448:PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description . . . . . . . . . . . . .513 Table 449:PWM Count control Register (PWM1CTCR address 0x4001 8004) bit description. . . . . . .513 Table 450:Match Control Register (PWM1MCR - address 0x4000 4014) bit description . . . . . . . . . . . . .514 Table 451:PWM Capture Control Register (PWM1CCR address 0x4001 8028) bit description. . . . . . .515 Table 452:PWM Control Register (PWM1PCR - address 0x4001 804C) bit description . . . . . . . . . . . . .516 Table 453:PWM Latch Enable Register (PWM1LER address 0x4001 8050) bit description. . . . . . .517 Table 454.Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . .519 Table 455.Motor Control Pulse Width Modulator (MCPWM) register map . . . . . . . . . . . . . . . . . . . . . . . . . .522 Table 456.MCPWM Control read address (MCCON 0x400B 8000) bit description . . . . . . . . . . . . .523 Table 457.MCPWM Control set address (MCCON_SET 0x400B 8004) bit description . . . . . . . . . . . . .524 Table 458.MCPWM Control clear address (MCCON_CLR 0x400B 8008) bit description . . . . . . . . . . . . .525 Table 459.MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) bit description 525 Table 460.MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .526 Table 461.MCPWM Capture control clear register (MCCAPCON_CLR - address 0x400B 8014) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .526 Table 462.Motor Control PWM interrupts . . . . . . . . . . . .526 Table 463.Interrupt sources bit allocation table . . . . . . . .526 Table 464.MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050) bit description . . .526 Table 465.PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .527 Table 466.PWM interrupt enable clear register (MCINTEN_CLR - address 0x400B 8058) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .527 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 810 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 0x4002 401C) bit description . . . . . . . . . . . . . 563 Table 518.Time Counter relationships and values . . . . . 563 Table 519.Time Counter registers. . . . . . . . . . . . . . . . . . 563 Table 520.Calibration register (CALIBRATION - address 0x4002 4040) bit description . . . . . . . . . . . . . 564 Table 521.General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044 to 0x4002 4054) bit description. . . . . . . . . . . . . . . . . . . . 565 Table 522.Alarm registers. . . . . . . . . . . . . . . . . . . . . . . . 565 Table 523.Watchdog register map . . . . . . . . . . . . . . . . . 567 Table 524:Watchdog Mode register (WDMOD - address 0x4000 0000) bit description . . . . . . . . . . . . . 568 Table 525.Watchdog operating modes selection . . . . . . 568 Table 526:Watchdog Constant register (WDTC - address 0x4000 0004) bit description . . . . . . . . . . . . . 569 Table 527:Watchdog Feed register (WDFEED - address 0x4000 0008) bit description . . . . . . . . . . . . . 569 Table 528:Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description . . . . . . . . . . . . . 569 Table 529:Watchdog Timer Clock Source Selection register (WDCLKSEL - address 0x4000 0010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Table 530.ADC pin description . . . . . . . . . . . . . . . . . . . . 572 Table 531.ADC registers. . . . . . . . . . . . . . . . . . . . . . . . . 573 Table 532:A/D Control Register (AD0CR - address 0x4003 4000) bit description . . . . . . . . . . . . . 574 Table 533:A/D Global Data Register (AD0GDR - address 0x4003 4004) bit description . . . . . . . . . . . . . 575 Table 534:A/D Status register (AD0INTEN - address 0x4003 400C) bit description . . . . . . . . . . . . . 575 Table 535:A/D Data Registers (AD0DR0 to AD0DR7 0x4003 4010 to 0x4003 402C) bit description 576 Table 536:A/D Status register (AD0STAT - address 0x4003 4030) bit description . . . . . . . . . . . . . 577 Table 537:A/D Trim register (ADTRM - address 0x4003 4034) bit description . . . . . . . . . . . . . 577 Table 538.D/A Pin Description . . . . . . . . . . . . . . . . . . . . 579 Table 539.DAC registers. . . . . . . . . . . . . . . . . . . . . . . . . 580 Table 540:D/A Converter Register (DACR - address 0x4008 C000) bit description . . . . . . . . . . . . . 580 Table 541.D/A Control register (DACCTRL - address 0x4008 C004) bit description . . . . . . . . . . . . . 581 Table 542:D/A Converter register (DACR - address 0x4008 C000) bit description . . . . . . . . . . . . . 581 Table 543.Endian behavior . . . . . . . . . . . . . . . . . . . . . . 586 Table 544.DMA Connections . . . . . . . . . . . . . . . . . . . . . 589 Table 545.GPDMA register map. . . . . . . . . . . . . . . . . . . 590 Table 546.DMA Interrupt Status register (DMACIntStat 0x5000 4000) . . . . . . . . . . . . . . . . . . . . . . . . 592 Table 547.DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004) . . . 592 Table 491:QEI Position Compare register 1 (CMPOS1 address 0x400B C018) bit description . . . . . .548 Table 492:QEI Position Compare register 2 (CMPOS2 address 0x400B C01C) bit description . . . . . .549 Table 493:QEI Index Count register (CMPOS - address 0x400B C020) bit description . . . . . . . . . . . . .549 Table 494:QEI Index Compare register (CMPOS - address 0x400B C024) bit description . . . . . . . . . . . . .549 Table 495:QEI Timer Load register (QEILOAD - address 0x400B C028) bit description . . . . . . . . . . . . .549 Table 496:QEI Timer register (QEITIME - address 0x400B C02C) bit description . . . . . . . . . . . . .549 Table 497:QEI Velocity register (QEIVEL - address 0x400B C030) bit description . . . . . . . . . . . . .550 Table 498:QEI Velocity Capture register (QEICAP - address 0x400B C034) bit description . . . . . . . . . . . . .550 Table 499:QEI Velocity Compare register (VELCOMP address 0x400B C038) bit description . . . . . .550 Table 500:QEI Digital Filter register (FILTER - address 0x400B C03C) bit description . . . . . . . . . . . . .550 Table 501:QEI Interrupt Status register (QEIINTSTAT address 0x400B CFE0) bit description . . . . . .551 Table 502:QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description . . . . . . . . . . . .551 Table 503:QEI Interrupt Clear register (QEICLR 0x400B CFE8) bit description . . . . . . . . . . . . .552 Table 504:QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description . . . . . . . . . . . . .552 Table 505:QEI Interrupt Enable Set register (QEIIES address 0x400B CFDC) bit description . . . . .553 Table 506:QEI Interrupt Enable Clear register (QEIIEC address 0x400B CFD8) bit description . . . . . .554 Table 507.RTC pin description . . . . . . . . . . . . . . . . . . . .557 Table 508.Real-Time Clock register map . . . . . . . . . . . .558 Table 509.Interrupt Location Register (ILR - address 0x4002 4000) bit description . . . . . . . . . . . . .559 Table 510.Clock Control Register (CCR - address 0x4002 4008) bit description . . . . . . . . . . . . .559 Table 511. Counter Increment Interrupt Register (CIIR address 0x4002 400C) bit description . . . . . .560 Table 512.Alarm Mask Register (AMR - address 0x4002 4010) bit description . . . . . . . . . . . . .561 Table 513.RTC Auxiliary control register (RTC_AUX address 0x4002 405C) bit description . . . . . .561 Table 514.RTC Auxiliary Enable register (RTC_AUXEN address 0x4002 4058) bit description. . . . . . .561 Table 515.Consolidated Time register 0 (CTIME0 - address 0x4002 4014) bit description . . . . . . . . . . . . .562 Table 516.Consolidated Time register 1 (CTIME1 - address 0x4002 4018) bit description . . . . . . . . . . . . .562 Table 517.Consolidated Time register 2 (CTIME2 - address continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 811 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 Table 579.ISP Copy command . . . . . . . . . . . . . . . . . . . . 623 Table 580.ISP Go command. . . . . . . . . . . . . . . . . . . . . . 624 Table 581.ISP Erase sector command . . . . . . . . . . . . . . 624 Table 582.ISP Blank check sector command . . . . . . . . . 625 Table 583.ISP Read Part Identification command . . . . . 625 Table 584.LPC17xx part identification numbers . . . . . . . 625 Table 585.ISP Read Boot Code version number command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 Table 586.ISP Read device serial number command. . . 626 Table 587.ISP Compare command. . . . . . . . . . . . . . . . . 626 Table 588.ISP Return Codes Summary . . . . . . . . . . . . . 627 Table 589.IAP Command Summary . . . . . . . . . . . . . . . . 629 Table 590.IAP Prepare sector(s) for write operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 Table 591.IAP Copy RAM to Flash command . . . . . . . . 630 Table 592.IAP Erase Sector(s) command . . . . . . . . . . . 631 Table 593.IAP Blank check sector(s) command . . . . . . . 631 Table 594.IAP Read part identification number command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 Table 595.IAP Read Boot Code version number command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 Table 596.IAP Read device serial number command. . . 632 Table 597.IAP Compare command. . . . . . . . . . . . . . . . . 632 Table 598.Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . . 633 Table 599.IAP Status Codes Summary . . . . . . . . . . . . . 633 Table 600.Register overview: FMC (base address 0x2020 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 Table 601.Flash Module Signature Start register (FMSSTART - 0x4008 4020) bit description . 635 Table 602.Flash Module Signature Stop register (FMSSTOP - 0x4008 4024) bit description . . . . . . . . . . . . 635 Table 603.FMSW0 register bit description (FMSW0, address: 0x2020 002C) . . . . . . . . . . . . . . . . . 635 Table 604.FMSW1 register bit description (FMSW1, address: 0x2020 0030) . . . . . . . . . . . . . . . . . 635 Table 605.FMSW2 register bit description (FMSW2, address: 0x2020 0034) . . . . . . . . . . . . . . . . . 636 Table 606.FMSW3 register bit description (FMSW3, address: 0x2020 0038) . . . . . . . . . . . . . . . . 636 Table 607.Flash module Status register (FMSTAT - 0x4008 4FE0) bit description . . . . . . . . . . . . . . . . . . . 636 Table 608.Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8) bit description . . . . . . . . . . 636 Table 609.JTAG pin description . . . . . . . . . . . . . . . . . . . 639 Table 610.Serial Wire Debug pin description . . . . . . . . . 639 Table 611. Parallel Trace pin description. . . . . . . . . . . . . 639 Table 612.Memory Mapping Control register (MEMMAP 0x400F C040) bit description . . . . . . . . . . . . . 640 Table 613.Cortex-M3 instructions . . . . . . . . . . . . . . . . . 644 Table 614.CMSIS intrinsic functions to generate some Table 548.DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008) . .592 Table 549.DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C) . . . . . . . . .593 Table 550.DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010) . . . . . . . . . .593 Table 551.DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014) . . . . . .593 Table 552.DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018) . . . . . .594 Table 553.DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C) . . . . . . . .594 Table 554.DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020) . . . . . . . . .594 Table 555.DMA Software Single Request register (DMACSoftSReq - 0x5000 4024) . . . . . . . . .595 Table 556.DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000 4028) . . . . . . . .595 Table 557.DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C) . . . . . . . .596 Table 558.DMA Configuration register (DMACConfig 0x5000 4030) . . . . . . . . . . . . . . . . . . . . . . . . .596 Table 559.DMA Synchronization register (DMACSync 0x5000 4034) . . . . . . . . . . . . . . . . . . . . . . . . .596 Table 560.DMA Request Select register (DMAReqSel 0x400F C1C4) . . . . . . . . . . . . . . . . . . . . . . . .597 Table 561.DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0) . . . . . . . . .598 Table 562.DMA Channel Destination Address registers (DMACCxDestAddr - 0x5000 41x4) . . . . . . . .598 Table 563.DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8) . . . . . . . . . . . . .599 Table 564.DMA channel control registers (DMACCxControl 0x5000 41xC) . . . . . . . . . . . . . . . . . . . . . . . .600 Table 565.DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0) . . . . . . . . . .602 Table 566.Transfer type bits . . . . . . . . . . . . . . . . . . . . . .603 Table 567.DMA request signal usage . . . . . . . . . . . . . .606 Table 568.Sectors in a LPC17xx device . . . . . . . . . . . . .617 Table 569.Code Read Protection options . . . . . . . . . . . .618 Table 570.Code Read Protection hardware/software interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .619 Table 571.ISP command summary . . . . . . . . . . . . . . . . .620 Table 572.ISP Unlock command . . . . . . . . . . . . . . . . . . .620 Table 573.ISP Set Baud Rate command. . . . . . . . . . . . .621 Table 574.Correlation between possible ISP baudrates and CCLK frequency (in MHz). . . . . . . . . . . . . . . .621 Table 575.ISP Echo command . . . . . . . . . . . . . . . . . . . .621 Table 576.ISP Write to RAM command. . . . . . . . . . . . . .622 Table 577.ISP Read Memory command . . . . . . . . . . . . .622 Table 578.ISP Prepare sector(s) for write operation continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 812 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Table 660.AIRCR bit assignments . . . . . . . . . . . . . . . . . 768 Table 661.Priority grouping. . . . . . . . . . . . . . . . . . . . . . . 769 Table 662.SCR bit assignments . . . . . . . . . . . . . . . . . . . 770 Table 663.CCR bit assignments . . . . . . . . . . . . . . . . . . . 771 Table 664.System fault handler priority fields . . . . . . . . . 772 Table 665.SHPR1 register bit assignments . . . . . . . . . . 772 Table 666.SHPR2 register bit assignments . . . . . . . . . . 772 Table 667.SHPR3 register bit assignments . . . . . . . . . . 772 Table 668.SHCSR bit assignments . . . . . . . . . . . . . . . . 773 Table 669.MMFSR bit assignments . . . . . . . . . . . . . . . . 774 Table 670.BFSR bit assignments . . . . . . . . . . . . . . . . . . 775 Table 671.UFSR bit assignments . . . . . . . . . . . . . . . . . . 777 Table 672.HFSR bit assignments . . . . . . . . . . . . . . . . . . 778 Table 673.MMFAR bit assignments . . . . . . . . . . . . . . . . 778 Table 674.BFAR bit assignments . . . . . . . . . . . . . . . . . . 779 Table 675.System timer registers summary . . . . . . . . . . 780 Table 676.SysTick CTRL register bit assignments . . . . . 780 Table 677.LOAD register bit assignments . . . . . . . . . . . 781 Table 678.VAL register bit assignments . . . . . . . . . . . . . 781 Table 679.CALIB register bit assignments . . . . . . . . . . . 781 Table 680.Memory attributes summary . . . . . . . . . . . . . 783 Table 681.MPU registers summary . . . . . . . . . . . . . . . . 784 Table 682.TYPE register bit assignments. . . . . . . . . . . . 784 Table 683.MPU CTRL register bit assignments . . . . . . . 785 Table 684.RNR bit assignments . . . . . . . . . . . . . . . . . . . 786 Table 685.RBAR bit assignments . . . . . . . . . . . . . . . . . . 787 Table 686.RASR bit assignments . . . . . . . . . . . . . . . . . . 788 Table 687.Example SIZE field values . . . . . . . . . . . . . . . 788 Table 688.TEX, C, B, and S encoding . . . . . . . . . . . . . . 789 Table 689.Cache policy for memory attribute encoding . 789 Table 690.AP encoding. . . . . . . . . . . . . . . . . . . . . . . . . . 790 Table 691.Memory region attributes for a microcontroller793 Table 692.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 798 Cortex-M3 instructions . . . . . . . . . . . . . . . . . .647 Table 615.CMSIS intrinsic functions to access the special registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 Table 616.Condition code suffixes. . . . . . . . . . . . . . . . . .654 Table 617.Memory access instructions . . . . . . . . . . . . . .657 Table 618.Offset ranges . . . . . . . . . . . . . . . . . . . . . . . . .660 Table 619.Offset ranges . . . . . . . . . . . . . . . . . . . . . . . . .666 Table 620.Data processing instructions. . . . . . . . . . . . . .674 Table 621.Multiply and divide instructions . . . . . . . . . . . .689 Table 622.Packing and unpacking instructions . . . . . . . .697 Table 623.Branch and control instructions . . . . . . . . . . .702 Table 624.Branch ranges . . . . . . . . . . . . . . . . . . . . . . . .703 Table 625.Miscellaneous instructions . . . . . . . . . . . . . . . 711 Table 626.Summary of processor mode, execution privilege level, and stack use options . . . . . . . . . . . . . .725 Table 627.Core register set summary . . . . . . . . . . . . . . .725 Table 628.PSR register combinations . . . . . . . . . . . . . . .727 Table 629.APSR bit assignments . . . . . . . . . . . . . . . . . .728 Table 630.IPSR bit assignments . . . . . . . . . . . . . . . . . . .729 Table 631.EPSR bit assignments . . . . . . . . . . . . . . . . . .729 Table 632.PRIMASK register bit assignments. . . . . . . . .730 Table 633.FAULTMASK register bit assignments . . . . . .730 Table 634.BASEPRI register bit assignments . . . . . . . . .731 Table 635.CONTROL register bit assignments . . . . . . . .731 Table 636.Memory access behavior . . . . . . . . . . . . . . . .736 Table 637.SRAM memory bit-banding regions . . . . . . . .738 Table 638.Peripheral memory bit-banding regions . . . . .738 Table 639.C compiler intrinsic functions for exclusive access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .741 Table 640.Properties of the different exception types . . .743 Table 641.Exception return behavior. . . . . . . . . . . . . . . .748 Table 642.Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .750 Table 643.Fault status and fault address registers . . . . .751 Table 644.Core peripheral register regions . . . . . . . . . . .756 Table 645.NVIC register summary . . . . . . . . . . . . . . . . .757 Table 646.Mapping of interrupts to the interrupt variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .758 Table 647.ISER bit assignments . . . . . . . . . . . . . . . . . . .758 Table 648.ICER bit assignments . . . . . . . . . . . . . . . . . . .759 Table 649.ISPR bit assignments . . . . . . . . . . . . . . . . . . .759 Table 650.ICPR bit assignments . . . . . . . . . . . . . . . . . . .760 Table 651.IABR bit assignments . . . . . . . . . . . . . . . . . . .760 Table 652.IPR bit assignments . . . . . . . . . . . . . . . . . . . .761 Table 653.STIR bit assignments . . . . . . . . . . . . . . . . . . .761 Table 654.CMSIS functions for NVIC control . . . . . . . . .763 Table 655.Summary of the system control block registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .764 Table 656.ACTLR bit assignments . . . . . . . . . . . . . . . . .765 Table 657.CPUID register bit assignments . . . . . . . . . . .765 Table 658.ICSR bit assignments . . . . . . . . . . . . . . . . . . .766 Table 659.VTOR bit assignments . . . . . . . . . . . . . . . . . .768 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 813 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 4. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. LPC1768 simplified block diagram. . . . . . . . . . . . .8 LPC1768 block diagram, CPU and buses . . . . . . 11 LPC17xx system memory map . . . . . . . . . . . . . .13 Reset block diagram including the wake-up timer19 Example of start-up after reset. . . . . . . . . . . . . . .20 External interrupt logic . . . . . . . . . . . . . . . . . . . . .23 Clock generation for the LPC17xx . . . . . . . . . . . .29 Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for CX1/X2 evaluation32 PLL0 block diagram . . . . . . . . . . . . . . . . . . . . . . .36 PLL1 block diagram . . . . . . . . . . . . . . . . . . . . . . .49 PLLs and clock dividers . . . . . . . . . . . . . . . . . . . .55 CLKOUT selection . . . . . . . . . . . . . . . . . . . . . . . .67 Simplified block diagram of the flash accelerator showing potential bus connections . . . . . . . . . . .69 LPC176x LQFP100 pin configuration . . . . . . . . .92 LPC175x LQFP80 pin configuration . . . . . . . . . .92 Ethernet block diagram . . . . . . . . . . . . . . . . . . .141 Ethernet packet fields . . . . . . . . . . . . . . . . . . . .143 Receive descriptor memory layout. . . . . . . . . . .170 Transmit descriptor memory layout . . . . . . . . . .173 Transmit example memory and registers. . . . . .184 Receive Example Memory and Registers . . . . .190 Transmit Flow Control . . . . . . . . . . . . . . . . . . . .195 Receive filter block diagram. . . . . . . . . . . . . . . .197 Receive Active/Inactive state machine . . . . . . .201 Transmit Active/Inactive state machine . . . . . . .202 USB device controller block diagram . . . . . . . . .214 USB MaxPacketSize register array indexing . . .230 Interrupt event handling . . . . . . . . . . . . . . . . . . .241 UDCA Head register and DMA Descriptors . . . .254 Isochronous OUT endpoint operation example .261 Data transfer in ATLE mode. . . . . . . . . . . . . . . .262 USB Host controller block diagram . . . . . . . . . .268 USB OTG controller block diagram . . . . . . . . . .272 USB OTG port configuration . . . . . . . . . . . . . . .273 USB host port configuration . . . . . . . . . . . . . . . .274 USB device port configuration . . . . . . . . . . . . . .274 USB OTG interrupt handling . . . . . . . . . . . . . . .284 USB OTG controller with software stack . . . . . .285 Hardware support for B-device switching from peripheral state to host state . . . . . . . . . . . . . . .286 State transitions implemented in software during B-device switching from peripheral to host . . . .287 Hardware support for A-device switching from host state to peripheral state . . . . . . . . . . . . . . . . . . .289 State transitions implemented in software during Fig 43. Fig 44. Fig 45. Fig 46. Fig 47. Fig 48. Fig 49. Fig 50. Fig 51. Fig 52. Fig 53. Fig 54. Fig 55. Fig 56. Fig 57. Fig 58. Fig 59. Fig 60. Fig 61. Fig 62. Fig 63. Fig 64. Fig 65. Fig 66. Fig 67. Fig 68. Fig 69. Fig 70. Fig 71. Fig 72. Fig 73. Fig 74. Fig 75. A-device switching from host to peripheral . . . . 290 Clocking and power control. . . . . . . . . . . . . . . . 293 Auto-baud a) mode 0 and b) mode 1 waveform 309 Algorithm for setting UART dividers . . . . . . . . . 312 UART0, 2 and 3 block diagram . . . . . . . . . . . . . 315 Auto-RTS Functional Timing . . . . . . . . . . . . . . . 326 Auto-CTS Functional Timing . . . . . . . . . . . . . . . 327 Auto-baud a) mode 0 and b) mode 1 waveform 332 Algorithm for setting UART dividers . . . . . . . . . 334 UART1 block diagram . . . . . . . . . . . . . . . . . . . . 340 CAN controller block diagram . . . . . . . . . . . . . . 343 Transmit buffer layout for standard and extended frame format configurations . . . . . . . . . . . . . . . 344 Receive buffer layout for standard and extended frame format configurations . . . . . . . . . . . . . . . 345 Global Self-Test (high-speed CAN Bus example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Local self test (high-speed CAN Bus example). 346 Entry in FullCAN and individual standard identifier tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Entry in standard identifier range table . . . . . . . 373 Entry in either extended identifier table . . . . . . . 374 ID Look-up table example explaining the search algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Semaphore procedure for reading an auto-stored message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 FullCAN section example of the ID look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 FullCAN message object layout . . . . . . . . . . . . 385 Normal case, no messages lost . . . . . . . . . . . . 387 Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Message gets overwritten . . . . . . . . . . . . . . . . . 388 Message overwritten indicated by semaphore bits and message lost . . . . . . . . . . . . . . . . . . . . . . . 389 Message overwritten indicated by message lost390 Clearing message lost. . . . . . . . . . . . . . . . . . . . 391 Detailed example of acceptance filter tables and ID index values . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 ID Look-up table configuration example (no FullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 ID Look-up table configuration example (FullCAN activated and enabled) . . . . . . . . . . . . . . . . . . . 397 SPI data transfer format (CPHA = 0 and CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . 409 Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two Frames Transfer . . . . . . . . . . . . . . . . . . . . 412 Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 814 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Fig 110. Receiver slave mode sharing the transmitter reference clock . . . . . . . . . . . . . . . . . . . . . . . . . 484 Fig 111. 4-wire receiver slave mode sharing the transmitter bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . . 485 Fig 112. FIFO contents for various I2S modes . . . . . . . . 486 Fig 113. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled. . . . . 496 Fig 114. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled . . . . . 496 Fig 115. Timer block diagram . . . . . . . . . . . . . . . . . . . . . 497 Fig 116. RI timer block diagram . . . . . . . . . . . . . . . . . . . 500 Fig 117. System Tick Timer block diagram . . . . . . . . . . . 502 Fig 118. PWM block diagram . . . . . . . . . . . . . . . . . . . . . 508 Fig 119. Sample PWM waveforms . . . . . . . . . . . . . . . . . 509 Fig 120. MCPWM Block Diagram . . . . . . . . . . . . . . . . . . 520 Fig 121. Edge-aligned PWM waveform without dead time, POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 Fig 122. Center-aligned PWM waveform without dead time, POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Fig 123. Edge-aligned PWM waveform with dead time, POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Fig 124. Center-aligned waveform with dead time, POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 Fig 125. Three-phase DC mode sample waveforms. . . . 538 Fig 126. Three-phase AC mode sample waveforms, edge aligned PWM mode. . . . . . . . . . . . . . . . . . . . . . 539 Fig 127. Encoder interface block diagram. . . . . . . . . . . . 541 Fig 128. Quadrature Encoder Basic Operation . . . . . . . . 543 Fig 129. RTC domain conceptual diagram . . . . . . . . . . . 556 Fig 130. RTC functional block diagram . . . . . . . . . . . . . . 556 Fig 131. Watchdog block diagram. . . . . . . . . . . . . . . . . . 570 Fig 132. DAC control with DMA interrupt and timer . . . . 582 Fig 133. DMA controller block diagram . . . . . . . . . . . . . . 584 Fig 134. LLI example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 Fig 135. Map of lower memory . . . . . . . . . . . . . . . . . . . . 613 Fig 136. Boot process flowchart . . . . . . . . . . . . . . . . . . . 616 Fig 137. IAP parameter passing . . . . . . . . . . . . . . . . . . . 629 Fig 138. Algorithm for generating a 128 bit signature . . . 637 Fig 139. Typical Cortex-M3 implementation . . . . . . . . . . 641 Fig 140. ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 Fig 141. LSR#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 Fig 142. LSL#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 Fig 143. ROR#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 Fig 144. RRX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 Fig 145. Bit-band mapping . . . . . . . . . . . . . . . . . . . . . . . 739 Fig 146. Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 Fig 76. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer) . . . . . . . . . .413 Fig 77. SPI frame format with CPOL=0 and CPHA=1 . .414 Fig 78. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) . . . . . . . . . .415 Fig 79. SPI Frame Format with CPOL = 1 and CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 Fig 80. Microwire frame format (single transfer) . . . . . .417 Fig 81. Microwire frame format (continuos transfers) . .418 Fig 82. Microwire frame format setup and hold details .418 Fig 83. I2C-bus configuration . . . . . . . . . . . . . . . . . . . . .427 Fig 84. Format in the Master Transmitter mode. . . . . . .429 Fig 85. Format of Master Receiver mode . . . . . . . . . . .430 Fig 86. A Master Receiver switches to Master Transmitter after sending repeated START . . . . . . . . . . . . .430 Fig 87. Format of Slave Receiver mode . . . . . . . . . . . .431 Fig 88. Format of Slave Transmitter mode . . . . . . . . . .431 Fig 89. I2C serial interface block diagram . . . . . . . . . . .432 Fig 90. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .434 Fig 91. Serial clock synchronization. . . . . . . . . . . . . . . .434 Fig 92. Format and states in the Master Transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448 Fig 93. Format and states in the Master Receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 Fig 94. Format and states in the Slave Receiver mode .452 Fig 95. Format and states in the Slave Transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453 Fig 96. Simultaneous repeated START conditions from two masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461 Fig 97. Forced access to a busy I2C-bus. . . . . . . . . . . .461 Fig 98. Recovering from a bus obstruction caused by a LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . .461 Fig 99. Simple I2S configurations and bus timing . . . . .472 Fig 100. Typical transmitter master mode, with or without MCLK output . . . . . . . . . . . . . . . . . . . . . . . . . . .482 Fig 101. Transmitter master mode sharing the receiver reference clock . . . . . . . . . . . . . . . . . . . . . . . . .482 Fig 102. 4-wire transmitter master mode sharing the receiver bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .482 Fig 103. Typical transmitter slave mode . . . . . . . . . . . . .482 Fig 104. Transmitter slave mode sharing the receiver reference clock . . . . . . . . . . . . . . . . . . . . . . . . .482 Fig 105. 4-wire transmitter slave mode sharing the receiver bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .483 Fig 106. Typical receiver master mode, with or without MCLK output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484 Fig 107. Receiver master mode sharing the transmitter reference clock . . . . . . . . . . . . . . . . . . . . . . . . .484 Fig 108. 4-wire receiver master mode sharing the transmitter bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .484 Fig 109. Typical receiver slave mode. . . . . . . . . . . . . . . .484 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 815 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 5. Contents Chapter 1: LPC17xx Introductory information 1 2 3 4 4.1 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering information . . . . . . . . . . . . . . . . . . . . . Part options summary. . . . . . . . . . . . . . . . . . . . Simplified block diagram . . . . . . . . . . . . . . . . . 3 4 6 7 7 8 6 7 7.1 8 9 10 Architectural overview . . . . . . . . . . . . . . . . . . . 9 ARM Cortex-M3 processor . . . . . . . . . . . . . . . . 9 Cortex-M3 Configuration Options . . . . . . . . . . 9 On-chip flash memory system. . . . . . . . . . . . 10 On-chip Static RAM. . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 2: LPC17xx Memory map 1 2 3 Memory map and peripheral addressing. . . . 12 Memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . 12 APB peripheral addresses . . . . . . . . . . . . . . . 14 4 5 6 Memory re-mapping . . . . . . . . . . . . . . . . . . . . 15 AHB arbitration . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus fault exceptions . . . . . . . . . . . . . . . . . . . . 16 Chapter 3: LPC17xx System control 1 2 3 4 4.1 5 6 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Source Identification Register (RSID 0x400F C180) . . . . . . . . . . . . . . . . . . . . . . . . . Brown-out detection . . . . . . . . . . . . . . . . . . . . External interrupt inputs . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . 17 17 18 18 6.2 6.3 6.4 7 7.1 21 22 23 24 External Interrupt flag register (EXTINT 0x400F C140) . . . . . . . . . . . . . . . . . . . . . . . . 24 External Interrupt Mode register (EXTMODE 0x400F C148) . . . . . . . . . . . . . . . . . . . . . . . . 25 External Interrupt Polarity register (EXTPOLAR 0x400F C14C) . . . . . . . . . . . . . . . . . . . . . . . . 26 Other system controls and status flags . . . . 28 System Controls and Status register (SCS 0x400F C1A0) . . . . . . . . . . . . . . . . . . . . . . . . 28 Chapter 4: LPC17xx Clocking and power control 1 2 3 3.1 3.2 3.3 4 4.1 5 5.1 5.1.1 5.2 5.3 Summary of clocking and power control functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal RC oscillator . . . . . . . . . . . . . . . . . . . Main oscillator. . . . . . . . . . . . . . . . . . . . . . . . . RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . Clock source selection multiplexer . . . . . . . . Clock Source Select register (CLKSRCSEL 0x400F C10C) . . . . . . . . . . . . . . . . . . . . . . . . PLL0 (Phase Locked Loop 0) . . . . . . . . . . . . . PLL0 operation . . . . . . . . . . . . . . . . . . . . . . . . PLL0 and startup/boot code interaction . . . . . PLL0 register description . . . . . . . . . . . . . . . . PLL0 Control register (PLL0CON 0x400F C080) . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 29 30 31 31 31 33 34 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 6 6.1 6.2 34 35 35 35 36 36 PLL0 Configuration register (PLL0CFG 0x400F C084) . . . . . . . . . . . . . . . . . . . . . . . . PLL0 Status register (PLL0STAT 0x400F C088) . . . . . . . . . . . . . . . . . . . . . . . . PLL0 Interrupt: PLOCK0 . . . . . . . . . . . . . . . . PLL0 Modes. . . . . . . . . . . . . . . . . . . . . . . . . . PLL0 Feed register (PLL0FEED 0x400F C08C) . . . . . . . . . . . . . . . . . . . . . . . . PLL0 and Power-down mode. . . . . . . . . . . . . PLL0 frequency calculation . . . . . . . . . . . . . . Procedure for determining PLL0 settings. . . . Examples of PLL0 settings . . . . . . . . . . . . . . PLL0 setup sequence . . . . . . . . . . . . . . . . . . PLL1 (Phase Locked Loop 1) . . . . . . . . . . . . . PLL1 register description . . . . . . . . . . . . . . . . PLL1 Control register (PLL1CON 0x400F C0A0) . . . . . . . . . . . . . . . . . . . . . . . . 37 39 39 40 40 40 40 42 43 46 47 47 49 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 816 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 59 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Deep Sleep mode . . . . . . . . . . . . . . . . . . . . . 59 Power-down mode . . . . . . . . . . . . . . . . . . . . . 60 Deep Power-down mode . . . . . . . . . . . . . . . . 61 Peripheral power control . . . . . . . . . . . . . . . . 61 Register description . . . . . . . . . . . . . . . . . . . . 61 Power Mode Control register (PCON 0x400F C0C0) . . . . . . . . . . . . . . . . . . . . . . . . 62 Encoding of Reduced Power Modes . . . . . . . 63 Wake-up from Reduced Power Modes . . . . . 63 Power Control for Peripherals register (PCONP 0x400F C0C4) . . . . . . . . . . . . . . . . . . . . . . . . 63 Power control usage notes . . . . . . . . . . . . . . 65 Power domains . . . . . . . . . . . . . . . . . . . . . . . 65 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . 66 External clock output pin . . . . . . . . . . . . . . . . 67 Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) . . . . . . . . . . . 67 6.3 6.4 6.4.1 6.5 6.6 6.7 6.8 6.9 7 7.1 7.2 7.3 PLL1 Configuration register (PLL1CFG 0x400F C0A4) . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL1 Status register (PLL1STAT 0x400F C0A8) . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL1 modes . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL1 Interrupt: PLOCK1. . . . . . . . . . . . . . . . . 51 PLL1 Feed register (PLL1FEED 0x400F C0AC) . . . . . . . . . . . . . . . . . . . . . . . . 52 PLL1 and Power-down mode . . . . . . . . . . . . . 52 PLL1 frequency calculation . . . . . . . . . . . . . . 53 Procedure for determining PLL1 settings . . . . 53 Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 55 CPU Clock Configuration register (CCLKCFG 0x400F C104) . . . . . . . . . . . . . . . . . . . . . . . . . 55 USB Clock Configuration register (USBCLKCFG 0x400F C108) . . . . . . . . . . . . . . . . . . . . . . . . . 56 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0x400F C1A8 and PCLKSEL1 0x400F C1AC) . . . . . . . . . . . . . . . . . . . . . . . . 56 8.7.1 8.8 8.9 8.10 8.11 9 10 10.1 Chapter 5: LPC17xx Flash accelerator 1 2 2.1 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash accelerator blocks . . . . . . . . . . . . . . . . . Flash memory bank . . . . . . . . . . . . . . . . . . . . Flash programming Issues . . . . . . . . . . . . . . . 69 69 69 70 3 4 5 Register description . . . . . . . . . . . . . . . . . . . . 70 Flash Accelerator Configuration register (FLASHCFG - 0x400F C000) . . . . . . . . . . . . . . 71 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 1 2 3 4 5 5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . 73 Vector table remapping . . . . . . . . . . . . . . . . . . 76 Register description . . . . . . . . . . . . . . . . . . . . 77 Interrupt Set-Enable Register 0 register (ISER0 0xE000 E100) . . . . . . . . . . . . . . . . . . . . . . . . . 78 Interrupt Set-Enable Register 1 register (ISER1 0xE000 E104) . . . . . . . . . . . . . . . . . . . . . . . . . 79 Interrupt Clear-Enable Register 0 (ICER0 0xE000 E180) . . . . . . . . . . . . . . . . . . . . . . . . . 80 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184). . . . . . . . . . . . . . . . . . . . . . . . 81 Interrupt Set-Pending Register 0 register (ISPR0 0xE000 E200) . . . . . . . . . . . . . . . . . . . . . . . . . 82 Interrupt Set-Pending Register 1 register (ISPR1 0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 83 . . . . . Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) . . . . . . . . . . . . . . . . . 84 . . . . . Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284) . . . . . . . . . . . . . . . . . 85 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Interrupt Priority Register 0 (IPR0 0xE000 E400) . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupt Priority Register 1 (IPR1 0xE000 E404) . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupt Priority Register 2 (IPR2 0xE000 E408) . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupt Priority Register 3 (IPR3 0xE000 E40C) . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt Priority Register 4 (IPR4 0xE000 E410) . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt Priority Register 5 (IPR5 0xE000 E414) . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt Priority Register 6 (IPR6 0xE000 E418) . . . . . . . . . . . . . . . . . . . . . . . . 90 Interrupt Priority Register 7 (IPR7 0xE000 E41C) . . . . . . . . . . . . . . . . . . . . . . . . 90 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 817 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 5.20 Software Trigger Interrupt Register (STIR 0xE000 EF00) . . . . . . . . . . . . . . . . . . . . . . . . 91 5.19 Interrupt Priority Register 8 (IPR8 0xE000 E420) . . . . . . . . . . . . . . . . . . . . . . . . . 90 Chapter 7: LPC17xx Pin configuration 1 LPC17xx pin configuration . . . . . . . . . . . . . . . 92 1.1 LPC17xx pin description . . . . . . . . . . . . . . . . 92 Chapter 8: LPC17xx Pin connect block 1 2 3 4 5 5.1 How to read this chapter . . . . . . . . . . . . . . . . 102 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Pin function select register values. . . . . . . . 102 Pin mode select register values . . . . . . . . . . 103 Register description . . . . . . . . . . . . . . . . . . . 105 Pin Function Select register 0 (PINSEL0 0x4002 C000) . . . . . . . . . . . . . . . . . . . . . . . . 106 Pin Function Select Register 1 (PINSEL1 0x4002 C004) . . . . . . . . . . . . . . . . . . . . . . . . 106 Pin Function Select register 2 (PINSEL2 0x4002 C008) . . . . . . . . . . . . . . . . . . . . . . . . 107 Pin Function Select Register 3 (PINSEL3 0x4002 C00C) . . . . . . . . . . . . . . . . . . . . . . . 107 Pin Function Select Register 4 (PINSEL4 0x4002 C010) . . . . . . . . . . . . . . . . . . . . . . . . 108 Pin Function Select Register 7 (PINSEL7 0x4002 C01C) . . . . . . . . . . . . . . . . . . . . . . . 109 Pin Function Select Register 9 (PINSEL9 0x4002 C024) . . . . . . . . . . . . . . . . . . . . . . . . 109 Pin Function Select Register 10 (PINSEL10 0x4002 C028) . . . . . . . . . . . . . . . . . . . . . . . . 109 Pin Mode select register 0 (PINMODE0 0x4002 C040) . . . . . . . . . . . . . . . . . . . . . . . . 110 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Pin Mode select register 1 (PINMODE1 0x4002 C044) . . . . . . . . . . . . . . . . . . . . . . . . Pin Mode select register 2 (PINMODE2 0x4002 C048) . . . . . . . . . . . . . . . . . . . . . . . . Pin Mode select register 3 (PINMODE3 0x4002 C04C) . . . . . . . . . . . . . . . . . . . . . . . . Pin Mode select register 4 (PINMODE4 0x4002 C050) . . . . . . . . . . . . . . . . . . . . . . . . Pin Mode select register 7 (PINMODE7 0x4002 C05C) . . . . . . . . . . . . . . . . . . . . . . . . Pin Mode select register 9 (PINMODE9 0x4002 C064) . . . . . . . . . . . . . . . . . . . . . . . . Open Drain Pin Mode select register 0 (PINMODE_OD0 - 0x4002 C068) . . . . . . . . . Open Drain Pin Mode select register 1 (PINMODE_OD1 - 0x4002 C06C) . . . . . . . . . Open Drain Pin Mode select register 2 (PINMODE_OD2 - 0x4002 C070) . . . . . . . . . Open Drain Pin Mode select register 3 (PINMODE_OD3 - 0x4002 C074) . . . . . . . . . Open Drain Pin Mode select register 4 (PINMODE_OD4 - 0x4002 C078) . . . . . . . . . I2C Pin Configuration register (I2CPADCFG 0x4002 C07C) . . . . . . . . . . . . . . . . . . . . . . . . 110 111 111 112 113 113 113 114 115 116 116 117 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) 1 2 2.1 2.2 3 4 5 5.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 118 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Digital I/O ports . . . . . . . . . . . . . . . . . . . . . . . 118 Interrupt generating digital ports . . . . . . . . . . 118 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 119 Register description . . . . . . . . . . . . . . . . . . . 120 GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009 C000 to 0x2009 C080) . . 121 GPIO port output Set register FIOxSET (FIO0SET to FIO4SET - 0x2009 C018 to 0x2009 C098) 122 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR- 0x2009 C01C to 0x2009 C09C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.4 5.5 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.2 5.3 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009 C014 to 0x2009 C094) . . 125 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK - 0x2009 C010 to 0x2009 C090) . . . . . . . . . . . . . . . . . . . . . . . 126 GPIO interrupt registers . . . . . . . . . . . . . . . . 129 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080). . . . . . . . . . . . . . . . . . . . . . . 129 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) . . . . . . . . . . . . . 129 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) . . . . . . . . . . . . . 130 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094) . . . . . . . . . . . . . 131 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) . . . . . . . . . . . . . 132 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 818 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 5.6.10 133 5.6.11 134 134 135 6 6.1 5.6.6 5.6.7 5.6.8 5.6.9 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) . . . . . GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) . . . . . GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088). . . . . . GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) . . . . . 6.2 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C) . . . . . . . . . . . . . . . . . . . . . . 136 GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) . . . . . . . . . . . . . . . . . . . . . . 137 GPIO usage notes . . . . . . . . . . . . . . . . . . . . . 138 Example: An instantaneous output of 0s and 1s on a GPIO port . . . . . . . . . . . . . . . . . . . . . . . . . 138 Writing to FIOSET/FIOCLR vs. FIOPIN . . . . 138 Chapter 10: LPC17xx Ethernet 1 2 3 4 5 6 7 8 8.1 8.2 9 10 10.1 11 11.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 139 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Architecture and operation . . . . . . . . . . . . . . 141 DMA engine functions . . . . . . . . . . . . . . . . . . 142 Overview of DMA operation . . . . . . . . . . . . . 142 Ethernet Packet . . . . . . . . . . . . . . . . . . . . . . . 143 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Example PHY Devices . . . . . . . . . . . . . . . . . 145 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 145 Registers and software interface . . . . . . . . . 146 Register map . . . . . . . . . . . . . . . . . . . . . . . . 146 Ethernet MAC register definitions . . . . . . . . 148 MAC Configuration Register 1 (MAC1 0x5000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 148 MAC Configuration Register 2 (MAC2 0x5000 0004) . . . . . . . . . . . . . . . . . . . . . . . . 148 Back-to-Back Inter-Packet-Gap Register (IPGT 0x5000 0008) . . . . . . . . . . . . . . . . . . . . . . . . 150 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0x5000 000C) . . . . . . . . . . . . . . . . . 150 Collision Window / Retry Register (CLRT 0x5000 0010) . . . . . . . . . . . . . . . . . . . . . . . . 151 Maximum Frame Register (MAXF 0x5000 0014) . . . . . . . . . . . . . . . . . . . . . . . . 151 PHY Support Register (SUPP 0x5000 0018) . . . . . . . . . . . . . . . . . . . . . . . . 151 Test Register (TEST - 0x5000 001C) . . . . . . 151 MII Mgmt Configuration Register (MCFG 0x5000 0020) . . . . . . . . . . . . . . . . . . . . . . . . 152 MII Mgmt Command Register (MCMD 0x5000 0024) . . . . . . . . . . . . . . . . . . . . . . . . 153 MII Mgmt Address Register (MADR 0x5000 0028) . . . . . . . . . . . . . . . . . . . . . . . . 153 MII Mgmt Write Data Register (MWTD 0x5000 002C) . . . . . . . . . . . . . . . . . . . . . . . . 153 11.13 11.14 11.15 11.16 11.17 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 MII Mgmt Read Data Register (MRDD 0x5000 0030) . . . . . . . . . . . . . . . . . . . . . . . . 154 MII Mgmt Indicators Register (MIND 0x5000 0034) . . . . . . . . . . . . . . . . . . . . . . . . 154 Station Address 0 Register (SA0 0x5000 0040) . . . . . . . . . . . . . . . . . . . . . . . . 155 Station Address 1 Register (SA1 0x5000 0044) . . . . . . . . . . . . . . . . . . . . . . . . 155 Station Address 2 Register (SA2 0x5000 0048) . . . . . . . . . . . . . . . . . . . . . . . . 155 Control register definitions . . . . . . . . . . . . . 156 Command Register (Command 0x5000 0100) . . . . . . . . . . . . . . . . . . . . . . . . 156 Status Register (Status - 0x5000 0104) . . . . 156 Receive Descriptor Base Address Register (RxDescriptor - 0x5000 0108) . . . . . . . . . . . 157 Receive Status Base Address Register (RxStatus - 0x5000 010C) . . . . . . . . . . . . . . . . . . . . . . 157 Receive Number of Descriptors Register (RxDescriptor - 0x5000 0110) . . . . . . . . . . . 157 Receive Produce Index Register (RxProduceIndex - 0x5000 0114) . . . . . . . . 158 Receive Consume Index Register (RxConsumeIndex - 0x5000 0118) . . . . . . . 158 Transmit Descriptor Base Address Register (TxDescriptor - 0x5000 011C) . . . . . . . . . . . 159 Transmit Status Base Address Register (TxStatus - 0x5000 0120). . . . . . . . . . . . . . . . . . . . . . . 159 Transmit Number of Descriptors Register (TxDescriptorNumber - 0x5000 0124) . . . . . 159 Transmit Produce Index Register (TxProduceIndex - 0x5000 0128) . . . . . . . . 160 Transmit Consume Index Register (TxConsumeIndex - 0x5000 012C) . . . . . . . 160 Transmit Status Vector 0 Register (TSV0 0x5000 0158) . . . . . . . . . . . . . . . . . . . . . . . . 160 Transmit Status Vector 1 Register (TSV1 0x5000 015C) . . . . . . . . . . . . . . . . . . . . . . . 161 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 819 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 15.2 16 16.1 16.2 17 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13 17.14 17.15 17.16 17.17 17.18 17.19 18 18.1 18.2 18.3 19 Transmit descriptors and statuses . . . . . . . . Ethernet block functional description. . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . AHB interface. . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Memory Access (DMA) . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . Transmit process . . . . . . . . . . . . . . . . . . . . . Receive process . . . . . . . . . . . . . . . . . . . . . Transmission retry . . . . . . . . . . . . . . . . . . . . Status hash CRC calculations . . . . . . . . . . . Duplex modes . . . . . . . . . . . . . . . . . . . . . . . IEE 802.3/Clause 31 flow control. . . . . . . . . Half-Duplex mode backpressure . . . . . . . . . Receive filtering . . . . . . . . . . . . . . . . . . . . . . Power management. . . . . . . . . . . . . . . . . . . Wake-up on LAN . . . . . . . . . . . . . . . . . . . . . Enabling and disabling receive and transmit Transmission padding and CRC . . . . . . . . . Huge frames and frame length checking . . . Statistics counters . . . . . . . . . . . . . . . . . . . . MAC status vectors . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet errors . . . . . . . . . . . . . . . . . . . . . . . AHB bandwidth . . . . . . . . . . . . . . . . . . . . . . . DMA access. . . . . . . . . . . . . . . . . . . . . . . . . Types of CPU access. . . . . . . . . . . . . . . . . . Overall bandwidth . . . . . . . . . . . . . . . . . . . . CRC calculation. . . . . . . . . . . . . . . . . . . . . . . 173 175 175 176 176 176 179 180 186 192 192 193 193 195 196 198 198 200 202 203 203 203 204 205 206 206 207 207 209 12.15 12.16 12.17 13 13.1 13.2 13.3 13.4 13.5 14 14.1 14.2 14.3 14.4 14.5 15 15.1 Receive Status Vector Register (RSV 0x5000 0160) . . . . . . . . . . . . . . . . . . . . . . . . 162 Flow Control Counter Register (FlowControlCounter - 0x5000 0170) . . . . . . 163 Flow Control Status Register (FlowControlStatus 0x5000 0174) . . . . . . . . . . . . . . . . . . . . . . . . 163 Receive filter register definitions . . . . . . . . . 164 Receive Filter Control Register (RxFilterCtrl 0x5000 0200) . . . . . . . . . . . . . . . . . . . . . . . . 164 Receive Filter WoL Status Register (RxFilterWoLStatus - 0x5000 0204) . . . . . . . 164 Receive Filter WoL Clear Register (RxFilterWoLClear - 0x5000 0208) . . . . . . . . 165 Hash Filter Table LSBs Register (HashFilterL 0x5000 0210) . . . . . . . . . . . . . . . . . . . . . . . . 165 Hash Filter Table MSBs Register (HashFilterH 0x5000 0214) . . . . . . . . . . . . . . . . . . . . . . . . 166 Module control register definitions . . . . . . . 166 Interrupt Status Register (IntStatus 0x5000 0FE0) . . . . . . . . . . . . . . . . . . . . . . . . 166 Interrupt Enable Register (IntEnable 0x5000 0FE4) . . . . . . . . . . . . . . . . . . . . . . . . 167 Interrupt Clear Register (IntClear 0x5000 0FE8) . . . . . . . . . . . . . . . . . . . . . . . . 167 Interrupt Set Register (IntSet 0x5000 0FEC) . . . . . . . . . . . . . . . . . . . . . . . 168 Power-Down Register (PowerDown 0x5000 0FF4) . . . . . . . . . . . . . . . . . . . . . . . . 169 Descriptor and status formats . . . . . . . . . . . 170 Receive descriptors and statuses. . . . . . . . . 170 Chapter 11: LPC17xx USB device controller 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 8 How to read this chapter . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed endpoint configuration . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . Analog transceiver . . . . . . . . . . . . . . . . . . . . Serial Interface Engine (SIE) . . . . . . . . . . . . Endpoint RAM (EP_RAM) . . . . . . . . . . . . . . EP_RAM access control . . . . . . . . . . . . . . . . DMA engine and bus master interface . . . . . Register interface . . . . . . . . . . . . . . . . . . . . . SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational overview . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . 211 211 211 212 212 213 214 214 214 214 215 215 215 215 215 216 9 9.1 9.2 9.3 9.4 10 10.1 10.1.1 Clocking and power management. . . . . . . . 216 Power requirements . . . . . . . . . . . . . . . . . . . 216 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Power management support . . . . . . . . . . . . 217 Remote wake-up . . . . . . . . . . . . . . . . . . . . . 218 Register description . . . . . . . . . . . . . . . . . . . 218 Clock control registers . . . . . . . . . . . . . . . . . 219 USB Clock Control register (USBClkCtrl 0x5000 CFF4) . . . . . . . . . . . . . . . . . . . . . . . 219 USB Clock Status register (USBClkSt - 0x5000 CFF8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Device interrupt registers . . . . . . . . . . . . . . . 220 USB Interrupt Status register (USBIntSt 0x5000 C1C0) . . . . . . . . . . . . . . . . . . . . . . . 220 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200) . . . . . . . . . . 221 10.1.2 10.2 10.2.1 10.2.2 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 820 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 10.7.4 10.7.5 10.7.6 10.7.7 10.7.8 10.7.9 10.7.10 10.7.11 10.7.12 10.7.13 10.7.14 10.7.15 10.7.16 10.7.17 10.7.18 11 12 10.2.3 10.2.4 10.2.5 10.2.6 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.6 10.6.1 10.6.2 10.7 10.7.1 10.7.2 10.7.3 USB Device Interrupt Enable register (USBDevIntEn - 0x5000 C204) . . . . . . . . . . 222 USB Device Interrupt Clear register (USBDevIntClr - 0x5000 C208) . . . . . . . . . . 222 USB Device Interrupt Set register (USBDevIntSet - 0x5000 C20C) . . . . . . . . . . . . . . . . . . . . . . 223 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C) . . . . . . . . . . 223 Endpoint interrupt registers. . . . . . . . . . . . . . 224 USB Endpoint Interrupt Status register (USBEpIntSt - 0x5000 C230). . . . . . . . . . . . 224 USB Endpoint Interrupt Enable register (USBEpIntEn - 0x5000 C234) . . . . . . . . . . . 225 USB Endpoint Interrupt Clear register (USBEpIntClr - 0x5000 C238) . . . . . . . . . . . 226 USB Endpoint Interrupt Set register (USBEpIntSet - 0x5000 C23C) . . . . . . . . . . . . . . . . . . . . . . 227 USB Endpoint Interrupt Priority register (USBEpIntPri - 0x5000 C240) . . . . . . . . . . . 227 Endpoint realization registers . . . . . . . . . . . . 228 EP RAM requirements . . . . . . . . . . . . . . . . . 228 USB Realize Endpoint register (USBReEp 0x5000 C244) . . . . . . . . . . . . . . . . . . . . . . . 228 USB Endpoint Index register (USBEpIn - 0x5000 C248). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 USB MaxPacketSize register (USBMaxPSize 0x5000 C24C) . . . . . . . . . . . . . . . . . . . . . . . 230 USB transfer registers . . . . . . . . . . . . . . . . . 230 USB Receive Data register (USBRxData - 0x5000 C218). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 USB Receive Packet Length register (USBRxPLen - 0x5000 C220) . . . . . . . . . . . 231 USB Transmit Data register (USBTxData - 0x5000 C21C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 USB Transmit Packet Length register (USBTxPLen - 0x5000 C224) . . . . . . . . . . . 232 USB Control register (USBCtrl 0x5000 C228) . . . . . . . . . . . . . . . . . . . . . . . 232 SIE command code registers . . . . . . . . . . . . 232 USB Command Code register (USBCmdCode 0x5000 C210) . . . . . . . . . . . . . . . . . . . . . . . 233 USB Command Data register (USBCmdData 0x5000 C214) . . . . . . . . . . . . . . . . . . . . . . . 233 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . 233 USB DMA Request Status register (USBDMARSt - 0x5000 C250) . . . . . . . . . . . . . . . . . . . . . . 233 USB DMA Request Clear register (USBDMARClr - 0x5000 C254) . . . . . . . . . . . . . . . . . . . . . . 234 USB DMA Request Set register (USBDMARSet 0x5000 C258) . . . . . . . . . . . . . . . . . . . . . . . 234 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 USB UDCA Head register (USBUDCAH - 0x5000 C280) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 USB EP DMA Status register (USBEpDMASt 0x5000 C284) . . . . . . . . . . . . . . . . . . . . . . . 235 USB EP DMA Enable register (USBEpDMAEn 0x5000 C288) . . . . . . . . . . . . . . . . . . . . . . . 236 USB EP DMA Disable register (USBEpDMADis 0x5000 C28C). . . . . . . . . . . . . . . . . . . . . . . 236 USB DMA Interrupt Status register (USBDMAIntSt - 0x5000 C290) . . . . . . . . . . . . . . . . . . . . . . 236 USB DMA Interrupt Enable register (USBDMAIntEn - 0x5000 C294) . . . . . . . . . 237 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0) . . . . . . . . . . 237 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4) . . . . . . . . . 237 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0x5000 C2A8) . . . . . . . . . 238 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0x5000 C2AC) . . . . . . . . 238 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0x5000 C2B0) . . . . . . . 238 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0x5000 C2B4) . . . . . . . 238 USB System Error Interrupt Status register (USBSysErrIntSt - 0x5000 C2B8) . . . . . . . . 239 USB System Error Interrupt Clear register (USBSysErrIntClr - 0x5000 C2BC) . . . . . . . 239 USB System Error Interrupt Set register (USBSysErrIntSet - 0x5000 C2C0). . . . . . . 239 Interrupt handling . . . . . . . . . . . . . . . . . . . . 239 Serial interface engine command description. . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Set Address (Command: 0xD0, Data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . 243 Configure Device (Command: 0xD8, Data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Set Mode (Command: 0xF3, Data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes) . . . . . . . . . . . . . . . . 244 Read Test Register (Command: 0xFD, Data: read 2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Set Device Status (Command: 0xFE, Data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Get Device Status (Command: 0xFE, Data: read 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Get Error Code (Command: 0xFF, Data: read 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 821 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 15.4.9 15.4.10 15.4.11 15.4.12 15.4.13 15.4.14 15.4.15 15.5 15.5.1 15.5.2 15.5.3 15.5.4 15.5.5 15.5.6 15.6 15.6.1 15.6.2 15.6.3 15.6.4 15.6.5 15.7 15.7.1 15.7.2 15.7.3 15.7.4 16 16.1 16.2 DD_status . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Packet_valid. . . . . . . . . . . . . . . . . . . . . . . . . 257 LS_byte_extracted . . . . . . . . . . . . . . . . . . . . 257 MS_byte_extracted . . . . . . . . . . . . . . . . . . . 257 Present_DMA_count . . . . . . . . . . . . . . . . . . 257 Message_length_position . . . . . . . . . . . . . . 257 Isochronous_packetsize_memory_address. 257 Non-isochronous endpoint operation . . . . . . 258 Setting up DMA transfers. . . . . . . . . . . . . . . 258 Finding DMA Descriptor. . . . . . . . . . . . . . . . 258 Transferring the data . . . . . . . . . . . . . . . . . . 258 Optimizing descriptor fetch . . . . . . . . . . . . . 258 Ending the packet transfer . . . . . . . . . . . . . . 259 No_Packet DD . . . . . . . . . . . . . . . . . . . . . . . 259 Isochronous endpoint operation. . . . . . . . . . 259 Setting up DMA transfers. . . . . . . . . . . . . . . 259 Finding the DMA Descriptor. . . . . . . . . . . . . 260 Transferring the Data . . . . . . . . . . . . . . . . . . 260 DMA descriptor completion . . . . . . . . . . . . . 260 Isochronous OUT Endpoint Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Auto Length Transfer Extraction (ATLE) mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Setting up the DMA transfer. . . . . . . . . . . . . 263 Finding the DMA Descriptor. . . . . . . . . . . . . 263 Transferring the Data . . . . . . . . . . . . . . . . . . 263 Ending the packet transfer . . . . . . . . . . . . . . 264 Double buffered endpoint operation . . . . . . 264 Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . 264 Isochronous endpoints . . . . . . . . . . . . . . . . . 266 12.9 12.10 12.11 12.12 12.13 12.14 13 14 14.1 14.2 14.3 15 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.4.6 15.4.7 15.4.8 Read Error Status (Command: 0xFB, Data: read 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional)) . . . . . . . . . . . . . . . . . 247 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte) . . . . . . . . . . 248 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional)). . . . . . . . . . . . . 249 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional)) . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Validate Buffer (Command: 0xFA, Data: none) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 USB device controller initialization . . . . . . . 250 Slave mode operation . . . . . . . . . . . . . . . . . . 251 Interrupt generation . . . . . . . . . . . . . . . . . . . 251 Data transfer for OUT endpoints. . . . . . . . . . 252 Data transfer for IN endpoints. . . . . . . . . . . . 252 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 252 Transfer terminology. . . . . . . . . . . . . . . . . . . 253 USB device communication area . . . . . . . . . 253 Triggering the DMA engine. . . . . . . . . . . . . . 254 The DMA descriptor . . . . . . . . . . . . . . . . . . . 254 Next_DD_pointer . . . . . . . . . . . . . . . . . . . . . 255 DMA_mode. . . . . . . . . . . . . . . . . . . . . . . . . . 256 Next_DD_valid . . . . . . . . . . . . . . . . . . . . . . . 256 Isochronous_endpoint . . . . . . . . . . . . . . . . . 256 Max_packet_size . . . . . . . . . . . . . . . . . . . . . 256 DMA_buffer_length. . . . . . . . . . . . . . . . . . . . 256 DMA_buffer_start_addr . . . . . . . . . . . . . . . . 256 DD_retired . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Chapter 12: LPC17xx USB Host controller 1 2 3 3.1 3.2 How to read this chapter . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 267 267 267 268 268 4 4.1 4.1.1 4.2 4.2.1 4.2.2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . USB host usage note . . . . . . . . . . . . . . . . . . Software interface . . . . . . . . . . . . . . . . . . . . Register map . . . . . . . . . . . . . . . . . . . . . . . . USB Host Register Definitions . . . . . . . . . . . 268 269 269 269 269 270 Chapter 13: LPC17xx USB OTG controller 1 2 3 4 5 6 7 How to read this chapter . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of operation . . . . . . . . . . . . . . . . . . . . Pin configuration . . . . . . . . . . . . . . . . . . . . . . 271 271 271 271 272 272 273 7.1 7.2 7.3 8 8.1 Connecting the USB port to an external OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Connecting USB as a host. . . . . . . . . . . . . . 274 Connecting USB as device . . . . . . . . . . . . . 274 Register description . . . . . . . . . . . . . . . . . . . 275 USB Interrupt Status Register (USBIntSt 0x5000 C1C0) . . . . . . . . . . . . . . . . . . . . . . . 275 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 822 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 9.2 10 10.1 10.1.1 10.2 11 I2C Transmit Register (I2C_TX 0x5000 C300) . . . . . . . . . . . . . . . . . . . . . . . I2C Status Register (I2C_STS 0x5000 C304) . . . . . . . . . . . . . . . . . . . . . . . I2C Control Register (I2C_CTL 0x5000 C308) . . . . . . . . . . . . . . . . . . . . . . . I2C Clock High Register (I2C_CLKHI 0x5000 C30C) . . . . . . . . . . . . . . . . . . . . . . . I2C Clock Low Register (I2C_CLKLO 0x5000 C310) . . . . . . . . . . . . . . . . . . . . . . . Interrupt handling . . . . . . . . . . . . . . . . . . . . . HNP support . . . . . . . . . . . . . . . . . . . . . . . . . B-device: peripheral to host switching . . . . . A-device: host to peripheral HNP switching. Clocking and power management. . . . . . . . Device clock request signals . . . . . . . . . . . . Host clock request signals . . . . . . . . . . . . . . Power-down mode support . . . . . . . . . . . . . USB OTG controller initialization . . . . . . . . 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 OTG Interrupt Status Register (OTGIntSt 0x5000 C100) . . . . . . . . . . . . . . . . . . . . . . . . 276 OTG Interrupt Enable Register (OTGIntEn 0x5000 C104) . . . . . . . . . . . . . . . . . . . . . . . . 276 OTG Interrupt Set Register (OTGIntSet 0x5000 C20C) . . . . . . . . . . . . . . . . . . . . . . . 276 OTG Interrupt Clear Register (OTGIntClr 0x5000 C10C) . . . . . . . . . . . . . . . . . . . . . . . 277 OTG Status and Control Register (OTGStCtrl 0x5000 C110) . . . . . . . . . . . . . . . . . . . . . . . . 277 OTG Timer Register (OTGTmr 0x5000 C114) . . . . . . . . . . . . . . . . . . . . . . . . 278 OTG Clock Control Register (OTGClkCtrl 0x5000 CFF4). . . . . . . . . . . . . . . . . . . . . . . . 278 OTG Clock Status Register (OTGClkSt 0x5000 CFF8). . . . . . . . . . . . . . . . . . . . . . . . 279 I2C Receive Register (I2C_RX 0x5000 C300) . . . . . . . . . . . . . . . . . . . . . . . . 279 280 280 282 283 283 283 284 285 288 292 293 294 294 294 Chapter 14: LPC17xx UART0/2/3 1 2 3 4 14.4.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 296 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 297 Register description . . . . . . . . . . . . . . . . . . . 297 UARTn Receiver Buffer Register (U0RBR 0x4000 C000, U2RBR - 0x4009 8000, U3RBR 0x4009 C000 when DLAB = 0) . . . . . . . . . . . 299 UARTn Transmit Holding Register (U0THR 0x4000 C000, U2THR - 0x4009 8000, U3THR 0x4009 C000 when DLAB = 0) . . . . . . . . . . . 299 UARTn Divisor Latch LSB register (U0DLL 0x4000 C000, U2DLL - 0x4009 8000, U3DLL 0x4009 C000 when DLAB = 1) and UARTn Divisor Latch MSB register (U0DLM - 0x4000 C004, U2DLL - 0x4009 8004, U3DLL - 0x4009 C004 when DLAB = 1) . . . . . . . . . . . . . . . . . . . . . . 299 UARTn Interrupt Enable Register (U0IER 0x4000 C004, U2IER - 0x4009 8004, U3IER 0x4009 C004 when DLAB = 0) . . . . . . . . . . . 300 UARTn Interrupt Identification Register (U0IIR 0x4000 C008, U2IIR - 0x4009 8008, U3IIR 0x4009 C008) . . . . . . . . . . . . . . . . . . . . . . . . 301 UARTn FIFO Control Register (U0FCR 0x4000 C008, U2FCR - 0x4009 8008, U3FCR 0x4009 C008) . . . . . . . . . . . . . . . . . . . . . . . . 303 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 303 4.7 4.2 4.3 4.4 4.5 4.6 4.6.1 UARTn Line Control Register (U0LCR 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR 0x4009 C00C) . . . . . . . . . . . . . . . . . . . . . . . 304 4.8 UARTn Line Status Register (U0LSR 0x4000 C014, U2LSR - 0x4009 8014, U3LSR 0x4009 C014) . . . . . . . . . . . . . . . . . . . . . . . 304 4.9 UARTn Scratch Pad Register (U0SCR 0x4000 C01C, U2SCR - 0x4009 801C U3SCR 0x4009 C01C) . . . . . . . . . . . . . . . . . . . . . . . 306 4.10 UARTn Auto-baud Control Register (U0ACR 0x4000 C020, U2ACR - 0x4009 8020, U3ACR 0x4009 C020) . . . . . . . . . . . . . . . . . . . . . . . 306 14.4.10.1 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 307 14.4.10.2 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 308 4.11 UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR 0x4009 C024) . . . . . . . . . . . . . . . . . . . . . . . 309 4.12 UARTn Fractional Divider Register (U0FDR 0x4000 C028, U2FDR - 0x4009 8028, U3FDR 0x4009 C028) . . . . . . . . . . . . . . . . . . . . . . . 310 4.12.1 Baud rate calculation . . . . . . . . . . . . . . . . . . . 311 4.13 UARTn Transmit Enable Register (U0TER 0x4000 C030, U2TER - 0x4009 8030, U3TER 0x4009 C030) . . . . . . . . . . . . . . . . . . . . . . . 313 4.14 UARTn FIFO Level register (U0FIFOLVL 0x4000 C058, U2FIFOLVL - 0x4009 8058, U3FIFOLVL - 0x4009 C058) . . . . . . . . . . . . 314 5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 314 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 823 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Chapter 15: LPC17xx UART1 1 2 3 4 4.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 316 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 317 Register description . . . . . . . . . . . . . . . . . . . 318 UART1 Receiver Buffer Register (U1RBR 0x4001 0000, when DLAB = 0). . . . . . . . . . . 319 4.2 UART1 Transmitter Holding Register (U1THR 0x4001 0000 when DLAB = 0) . . . . . . . . . . . 319 4.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0x4001 0000 and U1DLM 0x4001 0004, when DLAB = 1). . . . . . . . . . . 319 4.4 UART1 Interrupt Enable Register (U1IER 0x4001 0004, when DLAB = 0). . . . . . . . . . . 320 4.5 UART1 Interrupt Identification Register (U1IIR 0x4001 0008) . . . . . . . . . . . . . . . . . . . . . . . . 321 4.6 UART1 FIFO Control Register (U1FCR 0x4001 0008) . . . . . . . . . . . . . . . . . . . . . . . . 323 4.6.1 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 323 4.7 UART1 Line Control Register (U1LCR 0x4001 000C) . . . . . . . . . . . . . . . . . . . . . . . . 324 4.8 UART1 Modem Control Register (U1MCR 0x4001 0010) . . . . . . . . . . . . . . . . . . . . . . . . 324 4.9 Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 325 15.4.9.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 15.4.9.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.16.1 4.17 4.18 4.19 4.20 4.21 4.22 5 UART1 Line Status Register (U1LSR 0x4001 0014) . . . . . . . . . . . . . . . . . . . . . . . . 327 UART1 Modem Status Register (U1MSR 0x4001 0018) . . . . . . . . . . . . . . . . . . . . . . . . 328 UART1 Scratch Pad Register (U1SCR 0x4001 001C) . . . . . . . . . . . . . . . . . . . . . . . 329 UART1 Auto-baud Control Register (U1ACR 0x4001 0020) . . . . . . . . . . . . . . . . . . . . . . . . 329 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 331 UART1 Fractional Divider Register (U1FDR 0x4001 0028) . . . . . . . . . . . . . . . . . . . . . . . . 332 Baud rate calculation . . . . . . . . . . . . . . . . . . 333 UART1 Transmit Enable Register (U1TER 0x4001 0030) . . . . . . . . . . . . . . . . . . . . . . . . 335 UART1 RS485 Control register (U1RS485CTRL 0x4001 004C) . . . . . . . . . . . . . . . . . . . . . . . 336 UART1 RS-485 Address Match register (U1RS485ADRMATCH - 0x4001 0050) . . . . 337 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054) . . . . . . . . . . 337 RS-485/EIA-485 modes of operation . . . . . . 337 UART1 FIFO Level register (U1FIFOLVL 0x4001 0058) . . . . . . . . . . . . . . . . . . . . . . . . 339 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Chapter 16: LPC17xx CAN1/2 1 2 3 3.1 3.2 3.3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 6 7 Basic configuration . . . . . . . . . . . . . . . . . . . . CAN controllers . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General CAN features . . . . . . . . . . . . . . . . . CAN controller features . . . . . . . . . . . . . . . . Acceptance filter features . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . CAN controller architecture . . . . . . . . . . . . . APB Interface Block (AIB) . . . . . . . . . . . . . . Interface Management Logic (IML). . . . . . . . Transmit Buffers (TXB) . . . . . . . . . . . . . . . . . Receive Buffer (RXB) . . . . . . . . . . . . . . . . . Error Management Logic (EML) . . . . . . . . . Bit Timing Logic (BTL) . . . . . . . . . . . . . . . . . Bit Stream Processor (BSP) . . . . . . . . . . . . . CAN controller self-tests . . . . . . . . . . . . . . . . Memory map of the CAN block. . . . . . . . . . . CAN controller registers . . . . . . . . . . . . . . . . 341 341 341 341 342 342 342 342 343 343 343 344 345 345 345 345 347 347 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.9.1 CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000) . . . . . . . . . . . . . 349 CAN Command Register (CAN1CMR 0x4004 x004, CAN2CMR - 0x4004 8004) . . 351 CAN Global Status Register (CAN1GSR 0x4004 x008, CAN2GSR - 0x4004 8008) . . 352 CAN Interrupt and Capture Register (CAN1ICR 0x4004 400C, CAN2ICR - 0x4004 800C) . . 355 CAN Interrupt Enable Register (CAN1IER 0x4004 4010, CAN2IER - 0x4004 8010) . . . 358 CAN Bus Timing Register (CAN1BTR 0x4004 4014, CAN2BTR - 0x4004 8014) . . 359 CAN Error Warning Limit register (CAN1EWL 0x4004 4018, CAN2EWL - 0x4004 8018) . . 360 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR - 0x4004 801C). . . . . . . . . . . . . . . 361 CAN Receive Frame Status register (CAN1RFS 0x4004 4020, CAN2RFS - 0x4004 8020) . . 363 ID index field . . . . . . . . . . . . . . . . . . . . . . . . 363 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 824 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 14.12 Standard Frame Group Start Address register (SFF_GRP_sa - 0x4003 C008) . . . . . . . . . . 376 Extended Frame Start Address register (EFF_sa 0x4003 C00C) . . . . . . . . . . . . . . . . . . . . . . . 376 Extended Frame Group Start Address register (EFF_GRP_sa - 0x4003 C010) . . . . . . . . . . 377 End of AF Tables register (ENDofTable 0x4003 C014) . . . . . . . . . . . . . . . . . . . . . . . 377 Status registers . . . . . . . . . . . . . . . . . . . . . . 377 LUT Error Address register (LUTerrAd 0x4003 C018) . . . . . . . . . . . . . . . . . . . . . . . 378 LUT Error register (LUTerr - 0x4003 C01C). 378 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020) . . . . . . . . . . . . . . . . . . . . . . 378 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and FCANIC1 0x4003 C028) . . . . . . . . . . . . . . . . . . . . . . . 378 Configuration and search algorithm . . . . . . 379 Acceptance filter search algorithm . . . . . . . . 379 FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . . 380 FullCAN message layout . . . . . . . . . . . . . . . 382 FullCAN interrupts . . . . . . . . . . . . . . . . . . . . 384 FullCAN message interrupt enable bit . . . . . 384 Message lost bit and CAN channel number. 385 Setting the interrupt pending bits (IntPnd 63 to 0) . . . . . . . . . . . . . . . . . . . . . . 386 Clearing the interrupt pending bits (IntPnd 63 to 0) . . . . . . . . . . . . . . . . . . . . . . 386 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0). . . . . . . . 386 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to 0). . . . . . . . 386 Set and clear mechanism of the FullCAN interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Scenario 1: Normal case, no message lost . 386 Scenario 2: Message lost. . . . . . . . . . . . . . . 387 Scenario 3: Message gets overwritten indicated by Semaphore bits . . . . . . . . . . . . . . . . . . . . 388 Scenario 3.1: Message gets overwritten indicated by Semaphore bits and Message Lost. . . . . 388 Scenario 3.2: Message gets overwritten indicated by Message Lost . . . . . . . . . . . . . . . . . . . . . 389 Scenario 4: Clearing Message Lost bit . . . . 390 Examples of acceptance filter tables and ID index values. . . . . . . . . . . . . . . . . . . . . . . . . . 391 Example 1: only one section is used . . . . . . 391 Example 2: all sections are used . . . . . . . . . 391 Example 3: more than one but not all sections are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 Configuration example 4 . . . . . . . . . . . . . . . 392 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 10 11 11.1 11.2 11.3 11.4 12 13 14 14.1 14.2 14.3 CAN Receive Identifier register (CAN1RID 0x4004 4024, CAN2RID - 0x4004 8024) . . . 363 CAN Receive Data register A (CAN1RDA 0x4004 4028, CAN2RDA - 0x4004 8028) . . 364 CAN Receive Data register B (CAN1RDB 0x4004 402C, CAN2RDB - 0x4004 802C) . . 364 CAN Transmit Frame Information register (CAN1TFI[1/2/3] - 0x4004 40[30/ 40/50], CAN2TFI[1/2/3] - 0x4004 80[30/40/50]) . . . . 365 CAN Transmit Identifier register (CAN1TID[1/2/3] 0x4004 40[34/44/54], CAN2TID[1/2/3] 0x4004 80[34/44/54]) . . . . . . . . . . . . . . . . . . 366 CAN Transmit Data register A (CAN1TDA[1/2/3] 0x4004 40[38/48/58], CAN2TDA[1/2/3] 0x4004 80[38/48/58]) . . . . . . . . . . . . . . . . . . 367 CAN Transmit Data register B (CAN1TDB[1/2/3] 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] 0x4004 80[3C/4C/5C]) . . . . . . . . . . . . . . . . . 367 CAN Sleep Clear register (CANSLEEPCLR 0x400F C110) . . . . . . . . . . . . . . . . . . . . . . . . 367 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114) . . . . . . . . . . . . . . . . . . . . . . . 368 CAN controller operation . . . . . . . . . . . . . . . 368 Error handling . . . . . . . . . . . . . . . . . . . . . . . . 368 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . 369 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Transmit priority . . . . . . . . . . . . . . . . . . . . . . 369 Centralized CAN registers. . . . . . . . . . . . . . . 370 Central Transmit Status Register (CANTxSR 0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . 370 Central Receive Status Register (CANRxSR 0x4004 0004) . . . . . . . . . . . . . . . . . . . . . . . . 370 Central Miscellaneous Status Register (CANMSR - 0x4004 0008) . . . . . . . . . . . . . . . . . . . . . . . 371 Global acceptance filter . . . . . . . . . . . . . . . . 371 Acceptance filter modes . . . . . . . . . . . . . . . . 371 Acceptance filter Off mode . . . . . . . . . . . . . . 372 Acceptance filter Bypass mode . . . . . . . . . . 372 Acceptance filter Operating mode . . . . . . . . 372 FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . 372 Sections of the ID look-up table RAM . . . . . 372 ID look-up table RAM. . . . . . . . . . . . . . . . . . . 373 Acceptance filter registers . . . . . . . . . . . . . . 375 Acceptance Filter Mode Register (AFMR 0x4003 C000) . . . . . . . . . . . . . . . . . . . . . . . . 375 Section configuration registers . . . . . . . . . . . 375 Standard Frame Individual Start Address register (SFF_sa - 0x4003 C004) . . . . . . . . . . . . . . . 376 15 15.1 16 16.1 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.2.6 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 17 17.1 17.2 17.3 17.4 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 825 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 17.7 17.8 Configuration example 7 . . . . . . . . . . . . . . . 395 Look-up table programming guidelines . . . . 397 17.5 17.6 Configuration example 5. . . . . . . . . . . . . . . . 392 Configuration example 6. . . . . . . . . . . . . . . . 393 Chapter 17: LPC17xx SPI 1 2 3 4 5 6 6.1 6.2 6.3 6.4 7 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI overview. . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . SPI data transfers . . . . . . . . . . . . . . . . . . . . . SPI peripheral details . . . . . . . . . . . . . . . . . . General information . . . . . . . . . . . . . . . . . . . Master operation. . . . . . . . . . . . . . . . . . . . . . Slave operation. . . . . . . . . . . . . . . . . . . . . . . Exception conditions. . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . 399 399 399 400 400 402 402 402 403 403 404 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 SPI Control Register (S0SPCR 0x4002 0000) . . . . . . . . . . . . . . . . . . . . . . . . SPI Status Register (S0SPSR 0x4002 0004) . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register (S0SPDR - 0x4002 0008) SPI Clock Counter Register (S0SPCCR 0x4002 000C) . . . . . . . . . . . . . . . . . . . . . . . SPI Test Control Register (SPTCR 0x4002 0010) . . . . . . . . . . . . . . . . . . . . . . . . SPI Test Status Register (SPTSR 0x4002 0014) . . . . . . . . . . . . . . . . . . . . . . . . SPI Interrupt Register (S0SPINT 0x4002 001C) . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 404 406 406 406 407 407 408 409 Chapter 18: LPC17xx SSP0/1 interface 1 2 3 4 5 5.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 410 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 411 Bus description . . . . . . . . . . . . . . . . . . . . . . . 411 Texas Instruments synchronous serial frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 SPI frame format . . . . . . . . . . . . . . . . . . . . . 412 Clock Polarity (CPOL) and Phase (CPHA) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 SPI format with CPOL=0,CPHA=0 . . . . . . . . 413 SPI format with CPOL=0,CPHA=1 . . . . . . . . 414 SPI format with CPOL = 1,CPHA = 0 . . . . . . 414 SPI format with CPOL = 1,CPHA = 1 . . . . . . 416 National Semiconductor Microwire frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Setup and hold time requirements on CS with respect to SK in Microwire mode . . . . . . . . . 418 Register description . . . . . . . . . . . . . . . . . . . 419 6.1 6.2 6.3 6.4 6.5 6.6 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3 5.3.1 6 6.7 6.8 6.9 6.10 SSPn Control Register 0 (SSP0CR0 0x4008 8000, SSP1CR0 - 0x4003 0000). . . 419 SSPn Control Register 1 (SSP0CR1 0x4008 8004, SSP1CR1 - 0x4003 0004). . . 420 SSPn Data Register (SSP0DR - 0x4008 8008, SSP1DR - 0x4003 0008) . . . . . . . . . . . . . . . 421 SSPn Status Register (SSP0SR - 0x4008 800C, SSP1SR - 0x4003 000C) . . . . . . . . . . . . . . . 422 SSPn Clock Prescale Register (SSP0CPSR 0x4008 8010, SSP1CPSR - 0x4003 0010) . 422 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0x4008 8014, SSP1IMSC 0x4003 0014) . . . . . . . . . . . . . . . . . . . . . . . . 422 SSPn Raw Interrupt Status Register (SSP0RIS 0x4008 8018, SSP1RIS - 0x4003 0018) . . . 423 SSPn Masked Interrupt Status Register (SSP0MIS - 0x4008 801C, SSP1MIS 0x4003 001C) . . . . . . . . . . . . . . . . . . . . . . . 423 SSPn Interrupt Clear Register (SSP0ICR 0x4008 8020, SSP1ICR - 0x4003 0020) . . . 424 SSPn DMA Control Register (SSP0DMACR 0x4008 8024, SSP1DMACR - 0x4003 0024) 424 Chapter 19: LPC17xx I2C0/1/2 interface 1 2 3 4 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 425 426 426 4.1 5 6 6.1 I2C FAST Mode Plus . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . I2C operating modes . . . . . . . . . . . . . . . . . . . Master Transmitter mode . . . . . . . . . . . . . . . 427 427 428 428 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 826 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 8.9 I2C SCL HIGH duty cycle register (I2SCLH: I2C0, I2C0SCLH - 0x4001 C010; I2C1, I2C1SCLH 0x4005 C010; I2C2, I2C2SCLH 0x400A 0010). . . . . . . . . . . . . . . . . . . . . . . . 444 I2C SCL Low duty cycle register (I2SCLL: I2C0 I2C0SCLL: 0x4001 C014; I2C1 - I2C1SCLL: 0x4005 C014; I2C2 - I2C2SCLL: 0x400A 0014). . . . . . . . . . . . . . . . . . . . . . . . 444 Selecting the appropriate I2C data rate and duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Details of I2C operating modes . . . . . . . . . . 446 Master Transmitter mode . . . . . . . . . . . . . . . 447 Master Receiver mode. . . . . . . . . . . . . . . . . 449 Slave Receiver mode. . . . . . . . . . . . . . . . . . 451 Slave Transmitter mode . . . . . . . . . . . . . . . . 453 Detailed state tables. . . . . . . . . . . . . . . . . . . 454 Miscellaneous states . . . . . . . . . . . . . . . . . . 459 I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 459 I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 459 Some special cases . . . . . . . . . . . . . . . . . . . 459 Simultaneous repeated START conditions from two masters . . . . . . . . . . . . . . . . . . . . . . . . . 459 Data transfer after loss of arbitration . . . . . . 460 Forced access to the I2C-bus. . . . . . . . . . . . 460 I2C-bus obstructed by a LOW level on SCL or SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 I2C state service routines . . . . . . . . . . . . . . . 462 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 462 I2C interrupt service . . . . . . . . . . . . . . . . . . . 462 The state service routines . . . . . . . . . . . . . . 462 Adapting state services to an application. . . 462 Software example . . . . . . . . . . . . . . . . . . . . . 463 Initialization routine . . . . . . . . . . . . . . . . . . . 463 Start Master Transmit function . . . . . . . . . . . 463 Start Master Receive function . . . . . . . . . . . 463 I2C interrupt routine . . . . . . . . . . . . . . . . . . . 463 Non mode specific states. . . . . . . . . . . . . . . 463 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 463 Master States . . . . . . . . . . . . . . . . . . . . . . . . 464 State: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 464 State: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Master Transmitter states . . . . . . . . . . . . . . 464 State: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 464 State: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 465 State: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 465 State: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 465 State: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Master Receive states . . . . . . . . . . . . . . . . . 465 State: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 465 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.8 Master Receiver mode . . . . . . . . . . . . . . . . . 429 Slave Receiver mode . . . . . . . . . . . . . . . . . . 430 Slave Transmitter mode . . . . . . . . . . . . . . . . 431 I2C implementation and operation . . . . . . . . 431 Input filters and output stages. . . . . . . . . . . . 432 Address Registers, I2ADR0 to I2ADR3 . . . . 433 Address mask registers, I2MASK0 to I2MASK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 433 Shift register, I2DAT . . . . . . . . . . . . . . . . . . . 433 Arbitration and synchronization logic . . . . . . 433 Serial clock generator . . . . . . . . . . . . . . . . . . 434 Timing and control . . . . . . . . . . . . . . . . . . . . 435 Control register, I2CONSET and I2CONCLR 435 Status decoder and status register . . . . . . . . 435 Register description . . . . . . . . . . . . . . . . . . . 436 I2C Control Set register (I2CONSET: I2C0, I2C0CONSET - 0x4001 C000; I2C1, I2C1CONSET - 0x4005 C000; I2C2, I2C2CONSET - 0x400A 0000) . . . . . . . . . . . 437 I2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR - 0x4001 C018; I2C1, I2C1CONCLR - 0x4005 C018; I2C2, I2C2CONCLR - 0x400A 0018) . . . . . . . . . . . 439 I2C Status register (I2STAT: I2C0, I2C0STAT 0x4001 C004; I2C1, I2C1STAT - 0x4005 C004; I2C2, I2C2STAT - 0x400A 0004). . . . . . . . . . 440 I2C Data register (I2DAT: I2C0, I2C0DAT 0x4001 C008; I2C1, I2C1DAT - 0x4005 C008; I2C2, I2C2DAT - 0x400A 0008) . . . . . . . . . . 440 I2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C; I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) . . . . . . . . . . . 441 Interrupt in Monitor mode . . . . . . . . . . . . . . . 442 Loss of arbitration in Monitor mode . . . . . . . 442 I2C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER - 0x4001 C02C; I2C1, I2C1DATA_BUFFER- 0x4005 C02C; I2C2, I2C2DATA_BUFFER- 0x400A 002C) . . . . . . 443 I2C Slave Address registers (I2ADR0 to 3: I2C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28]; I2C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I2C2, I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28]). . . . 443 I2C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C]; I2C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I2C2, I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C]). . 444 8.10 8.11 9 9.1 9.2 9.3 9.4 9.5 9.6 9.6.1 9.6.2 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.8 9.8.1 9.8.2 9.8.3 9.8.4 10 10.1 10.2 10.3 10.4 10.5 10.5.1 10.5.2 10.5.3 10.5.4 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.7 10.7.1 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 827 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 466 466 466 466 466 467 467 467 467 468 10.8.7 10.8.8 10.8.9 10.9 10.9.1 10.9.2 10.9.3 10.9.4 10.9.5 State: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0xA0. . . . . . . . . . . . . . . . . . . . . . . . . . Slave Transmitter states . . . . . . . . . . . . . . . State: 0xA8. . . . . . . . . . . . . . . . . . . . . . . . . . State: 0xB0. . . . . . . . . . . . . . . . . . . . . . . . . . State: 0xB8. . . . . . . . . . . . . . . . . . . . . . . . . . State: 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . . State: 0xC8 . . . . . . . . . . . . . . . . . . . . . . . . . 468 468 468 468 468 469 469 469 469 10.7.2 10.7.3 10.7.4 10.8 10.8.1 10.8.2 10.8.3 10.8.4 10.8.5 10.8.6 State: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Receiver states . . . . . . . . . . . . . . . . . . State: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . State: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 20: LPC17xx I2S interface 1 2 3 4 5 5.1 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . Digital Audio Output register (I2SDAO 0x400A 8000) . . . . . . . . . . . . . . . . . . . . . . . . Digital Audio Input register (I2SDAI 0x400A 8004) . . . . . . . . . . . . . . . . . . . . . . . . Transmit FIFO register (I2STXFIFO 0x400A 8008) . . . . . . . . . . . . . . . . . . . . . . . . Receive FIFO register (I2SRXFIFO 0x400A 800C). . . . . . . . . . . . . . . . . . . . . . . . Status Feedback register (I2SSTATE 0x400A 8010) . . . . . . . . . . . . . . . . . . . . . . . . DMA Configuration Register 1 (I2SDMA1 0x400A 8014) . . . . . . . . . . . . . . . . . . . . . . . . DMA Configuration Register 2 (I2SDMA2 0x400A 8018) . . . . . . . . . . . . . . . . . . . . . . . . 470 470 471 472 473 5.8 5.9 5.9.1 5.10 5.11 5.12 5.13 5.14 6 7 8 473 474 474 474 475 475 476 5.2 5.3 5.4 5.5 5.6 5.7 Interrupt Request Control register (I2SIRQ 0x400A 801C) . . . . . . . . . . . . . . . . . . . . . . . 476 Transmit Clock Rate register (I2STXRATE 0x400A 8020). . . . . . . . . . . . . . . . . . . . . . . . 476 Notes on fractional rate generators . . . . . . . 477 Receive Clock Rate register (I2SRXRATE 0x400A 8024). . . . . . . . . . . . . . . . . . . . . . . . 477 Transmit Clock Bit Rate register (I2STXBITRATE - 0x400A 8028) . . . . . . . . . . . . . . . . . . . . . . 478 Receive Clock Bit Rate register (I2SRXBITRATE 0x400A 802C) . . . . . . . . . . . . . . . . . . . . . . . 478 Transmit Mode Control register (I2STXMODE 0x400A 8030). . . . . . . . . . . . . . . . . . . . . . . . 478 Receive Mode Control register (I2SRXMODE 0x400A 8034). . . . . . . . . . . . . . . . . . . . . . . . 479 I2S transmit and receive interfaces . . . . . . . 480 I2S operating modes . . . . . . . . . . . . . . . . . . . 481 FIFO controller . . . . . . . . . . . . . . . . . . . . . . . 485 Chapter 21: LPC17xx Timer 0/1/2/3 1 2 3 4 5 5.1 6 6.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 487 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 488 Multiple CAP and MAT pins . . . . . . . . . . . . . 488 Register description . . . . . . . . . . . . . . . . . . . 489 Interrupt Register (T[0/1/2/3]IR - 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000) . 490 Timer Control Register (T[0/1/2/3]CR 0x4000 4004, 0x4000 8004, 0x4009 0004, 0x4009 4004) . . . . . . . . . . . . . . . . . . . . . . . . 490 6.3 6.4 6.5 6.6 6.2 6.7 6.8 6.9 Count Control Register (T[0/1/2/3]CTCR 0x4000 4070, 0x4000 8070, 0x4009 0070, 0x4009 4070) . . . . . . . . . . . . . . . . . . . . . . . . 491 Timer Counter . . . . . . . . registers (T0TC - T3TC, 0x4000 4008, 0x4000 8008, 0x4009 0008, 0x4009 4008) . . . . . . . . . . . . . . . . . . . . . . . . 492 Prescale register (T0PR - T3PR, 0x4000 400C, 0x4000 800C, 0x4009 000C, 0x4009 400C) 492 Prescale Counter register (T0PC - T3PC, 0x4000 4010, 0x4000 8010, 0x4009 0010, 0x4009 4010) . . . . . . . . . . . . . . . . . . . . . . . . 492 Match Registers (MR0 - MR3) . . . . . . . . . . . 493 Match Control Register (T[0/1/2/3]MCR 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014) . . . . . . . . . . . . . . . . . . . . . . . . 493 Capture Registers (CR0 - CR1) . . . . . . . . . . 494 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 828 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 6.12 7 8 DMA operation . . . . . . . . . . . . . . . . . . . . . . . 495 Example timer operation . . . . . . . . . . . . . . . 496 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 497 6.10 6.11 Capture Control Register (T[0/1/2/3]CCR 0x4000 4028, 0x4000 8028, 0x4009 0028, 0x4009 4028) . . . . . . . . . . . . . . . . . . . . . . . . 494 External Match Register (T[0/1/2/3]EMR 0x4000 403C, 0x4000 803C, 0x4009 003C, 0x4009 403C) . . . . . . . . . . . . . . . . . . . . . . . . 494 Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) 1 2 3 3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . RI Compare Value register (RICOMPVAL 0x400B 0000) . . . . . . . . . . . . . . . . . . . . . . . . 498 498 498 3.2 3.3 3.4 4 498 RI Mask register (RIMASK - 0x400B 0004) . RI Control register (RICTRL - 0x400B 0008) RI Counter register (RICOUNTER - 0x400B 000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RI timer operation . . . . . . . . . . . . . . . . . . . . . 498 499 499 499 Chapter 23: LPC17xx System Tick Timer 1 2 3 4 5 5.1 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . System Timer Control and status register (STCTRL - 0xE000 E010) . . . . . . . . . . . . . . 501 501 501 501 502 5.2 5.3 5.4 6 502 System Timer Reload value register (STRELOAD - 0xE000 E014) . . . . . . . . . . . . . . . . . . . . . . 503 System Timer Current value register (STCURR 0xE000 E018) . . . . . . . . . . . . . . . . . . . . . . . 503 System Timer Calibration value register (STCALIB - 0xE000 E01C) . . . . . . . . . . . . . 503 Example timer calculations . . . . . . . . . . . . . 505 Chapter 24: LPC17xx Pulse Width Modulator (PWM) 1 2 3 4 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample waveform with rules for single and double edge control. . . . . . . . . . . . . . . . . . . . Rules for Single Edge Controlled PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rules for Double Edge Controlled PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . 506 506 507 509 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4.1 4.2 5 6 510 510 510 511 PWM Interrupt Register (PWM1IR 0x4001 8000) . . . . . . . . . . . . . . . . . . . . . . . . 512 PWM Timer Control Register (PWM1TCR 0x4001 8004) . . . . . . . . . . . . . . . . . . . . . . . . 513 PWM Count Control Register (PWM1CTCR 0x4001 8070) . . . . . . . . . . . . . . . . . . . . . . . . 513 PWM Match Control Register (PWM1MCR 0x4001 8014) . . . . . . . . . . . . . . . . . . . . . . . . 514 PWM Capture Control Register (PWM1CCR 0x4001 8028) . . . . . . . . . . . . . . . . . . . . . . . . 515 PWM Control Register (PWM1PCR 0x4001 804C) . . . . . . . . . . . . . . . . . . . . . . . 516 PWM Latch Enable Register (PWM1LER 0x4001 8050) . . . . . . . . . . . . . . . . . . . . . . . . 517 Chapter 25: LPC17xx Motor Control PWM 1 2 3 4 5 6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 519 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 520 Configuring other modules for MCPWM use 521 General Operation . . . . . . . . . . . . . . . . . . . . . 521 7 7.1 7.1.1 Register description . . . . . . . . . . . . . . . . . . . 522 MCPWM Control register . . . . . . . . . . . . . . . 523 MCPWM Control read address (MCCON 0x400B 8000). . . . . . . . . . . . . . . . . . . . . . . . 523 MCPWM Control set address (MCCON_SET 0x400B 8004). . . . . . . . . . . . . . . . . . . . . . . . 524 7.1.2 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 829 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 7.5 7.6 7.7 7.7.1 7.7.2 7.7.3 7.8 7.9 7.10 7.10.1 7.10.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 7.1.3 7.2 7.2.1 7.2.2 7.2.3 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4 7.4.1 7.4.2 7.4.3 MCPWM Control clear address (MCCON_CLR 0x400B 8008) . . . . . . . . . . . . . . . . . . . . . . . . 524 MCPWM Capture Control register . . . . . . . . 525 MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) . . . . . . . . . . . 525 MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) . . . . . . . 525 MCPWM Capture control clear address (MCCAPCON_CLR - 0x400B 8014). . . . . . . 526 MCPWM Interrupt registers . . . . . . . . . . . . . 526 MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050) . . . . . . . . . . . . . 526 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054) . . . . . . . . . 527 MCPWM Interrupt Enable clear address (MCINTEN_CLR - 0x400B 8058) . . . . . . . . 527 MCPWM Interrupt Flags read address (MCINTF 0x400B 8068) . . . . . . . . . . . . . . . . . . . . . . . 527 MCPWM Interrupt Flags set address (MCINTF_SET - 0x400B 806C) . . . . . . . . . . 527 MCPWM Interrupt Flags clear address (MCINTF_CLR - 0x400B 8070) . . . . . . . . . . 527 MCPWM Count Control register . . . . . . . . . . 528 MCPWM Count Control read address (MCCNTCON - 0x400B 805C) . . . . . . . . . . . 528 MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) . . . . . . . 529 MCPWM Count Control clear address (MCCNTCON_CLR - 0x400B 8064). . . . . . . 529 MCPWM Timer/Counter 0-2 registers (MCTC0-2 0x400B 8018, 0x400B 801C, 0x400B 8020) 529 MCPWM Limit 0-2 registers (MCLIM0-2 0x400B 8024, 0x400B 8028, 0x400B 802C) 530 MCPWM Match 0-2 registers (MCMAT0-2 0x400B 8030, 0x400B 8034, 0x400B 8038) 530 Match register in Edge-Aligned mode . . . . . 531 Match register in Center-Aligned mode . . . . 531 0 and 100% duty cycle. . . . . . . . . . . . . . . . . 531 MCPWM Dead-time register (MCDT 0x400B 803C) . . . . . . . . . . . . . . . . . . . . . . . 531 MCPWM Commutation Pattern register (MCCP 0x400B 8040). . . . . . . . . . . . . . . . . . . . . . . . 532 MCPWM Capture Registers. . . . . . . . . . . . . 532 MCPWM Capture read addresses (MCCAP0-2 0x400B 8044, 0x400B 8048, 0x400B 804C) 532 MCPWM Capture clear address (MCCAP_CLR 0x400B 8074). . . . . . . . . . . . . . . . . . . . . . . . 532 PWM operation . . . . . . . . . . . . . . . . . . . . . . . 534 Pulse-width modulation . . . . . . . . . . . . . . . . 534 Shadow registers and simultaneous updates 536 Fast Abort (ABORT). . . . . . . . . . . . . . . . . . . 536 Capture events. . . . . . . . . . . . . . . . . . . . . . . 536 External event counting (Counter mode) . . . 537 Three-phase DC mode . . . . . . . . . . . . . . . . 537 Three phase AC mode. . . . . . . . . . . . . . . . . 538 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) 1 2 3 4 4.1 4.1.1 4.1.2 4.2 4.3 4.4 5 6 6.1 6.2 6.2.1 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . Input signals . . . . . . . . . . . . . . . . . . . . . . . . . Quadrature input signals . . . . . . . . . . . . . . . Digital input filtering . . . . . . . . . . . . . . . . . . . Position capture . . . . . . . . . . . . . . . . . . . . . . Velocity capture . . . . . . . . . . . . . . . . . . . . . . Velocity compare . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . Register summary . . . . . . . . . . . . . . . . . . . . Control registers . . . . . . . . . . . . . . . . . . . . . . QEI Control register (QEICON 0x400B C000). . . . . . . . . . . . . . . . . . . . . . . . QEI Configuration register (QEICONF 0x400B C008). . . . . . . . . . . . . . . . . . . . . . . . 540 540 540 542 542 542 543 543 543 544 545 546 546 547 6.2.3 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 547 6.3.8 547 6.2.2 QEI Status register (QEISTAT 0x400B C004) . . . . . . . . . . . . . . . . . . . . . . . 547 Position, index and timer registers. . . . . . . . 548 QEI Position register (QEIPOS 0x400B C00C) . . . . . . . . . . . . . . . . . . . . . . . 548 QEI Maximum Position register (QEIMAXPOS 0x400B C010) . . . . . . . . . . . . . . . . . . . . . . . 548 QEI Position Compare register 0 (CMPOS0 0x400B C014) . . . . . . . . . . . . . . . . . . . . . . . 548 QEI Position Compare register 1 (CMPOS1 0x400B C018) . . . . . . . . . . . . . . . . . . . . . . . 548 QEI Position Compare register 2 (CMPOS2 0x400B C01C) . . . . . . . . . . . . . . . . . . . . . . . 549 QEI Index Count register (INXCNT - 0x400B C020) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 QEI Index Compare register (INXCMP - 0x400B C024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 QEI Timer Reload register (QEILOAD - 0x400B C028) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 830 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 QEI Interrupt Status register (QEIINTSTAT) 551 QEI Interrupt Set register (QEISET - 0x400B CFEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 QEI Interrupt Clear register (QEICLR - 0x400B CFE8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 QEI Interrupt Enable register (QEIIE - 0x400B CFE4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 QEI Interrupt Enable Set register (QEIIES 0x400B CFDC). . . . . . . . . . . . . . . . . . . . . . . 553 QEI Interrupt Enable Clear register (QEIIEC 0x400B CFD8) . . . . . . . . . . . . . . . . . . . . . . . 554 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 6.4 QEI Timer register (QEITIME 0x400B C02C) . . . . . . . . . . . . . . . . . . . . . . . 549 QEI Velocity register (QEIVEL 0x400B C030). . . . . . . . . . . . . . . . . . . . . . . . 550 QEI Velocity Capture register (QEICAP - 0x400B C034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 QEI Velocity Compare register (VELCOMP 0x400B C038). . . . . . . . . . . . . . . . . . . . . . . . 550 QEI Digital Filter register (FILTER 0x400B C03C) . . . . . . . . . . . . . . . . . . . . . . . 550 Interrupt registers . . . . . . . . . . . . . . . . . . . . . 551 Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 1 2 3 4 5 6 6.1 6.2 6.2.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 555 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 556 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 557 Register description . . . . . . . . . . . . . . . . . . . 557 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . 559 Miscellaneous register group . . . . . . . . . . . . 559 Interrupt Location Register (ILR 0x4002 4000) . . . . . . . . . . . . . . . . . . . . . . . . 559 Clock Control Register (CCR - 0x4002 4008) 559 Counter Increment Interrupt Register (CIIR 0x4002 400C) . . . . . . . . . . . . . . . . . . . . . . . . 560 Alarm Mask Register (AMR - 0x4002 4010) . 560 RTC Auxiliary control register (RTC_AUX 0x4002 405C) . . . . . . . . . . . . . . . . . . . . . . . . 561 RTC Auxiliary Enable register (RTC_AUXEN 0x4002 4058) . . . . . . . . . . . . . . . . . . . . . . . . 561 6.3 6.3.1 6.3.2 6.3.3 6.4 6.4.1 6.4.2 6.5 6.6 6.6.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.7 7 Consolidated time registers . . . . . . . . . . . . . 562 Consolidated Time Register 0 (CTIME0 0x4002 4014) . . . . . . . . . . . . . . . . . . . . . . . . 562 Consolidated Time Register 1 (CTIME1 0x4002 4018) . . . . . . . . . . . . . . . . . . . . . . . . 562 Consolidated Time Register 2 (CTIME2 0x4002 401C) . . . . . . . . . . . . . . . . . . . . . . . 562 Time Counter Group . . . . . . . . . . . . . . . . . . 563 Leap year calculation . . . . . . . . . . . . . . . . . . 563 Calibration register (CALIBRATION - address 0x4002 4040) . . . . . . . . . . . . . . . . . . . . . . . . 563 Calibration procedure. . . . . . . . . . . . . . . . . . 564 General purpose registers . . . . . . . . . . . . . 565 General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044 to 0x4002 4054) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Alarm register group . . . . . . . . . . . . . . . . . . 565 RTC usage notes. . . . . . . . . . . . . . . . . . . . . . 565 Chapter 28: LPC17xx Watchdog Timer (WDT) 1 2 3 4 4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . Watchdog Mode register (WDMOD 0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Constant register (WDTC 0x4000 0004) . . . . . . . . . . . . . . . . . . . . . . . . 566 566 567 567 4.3 4.4 4.5 5 568 569 4.2 Watchdog Feed register (WDFEED 0x4000 0008) . . . . . . . . . . . . . . . . . . . . . . . . 569 Watchdog Timer Value register (WDTV 0x4000 000C) . . . . . . . . . . . . . . . . . . . . . . . 569 Watchdog Timer Clock Source Selection register (WDCLKSEL - 0x4000 0010). . . . . . . . . . . . 569 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 570 Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 1 2 3 4 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . 571 571 571 572 5 5.1 Register description . . . . . . . . . . . . . . . . . . . 573 A/D Control Register (AD0CR 0x4003 4000) . . . . . . . . . . . . . . . . . . . . . . . . 574 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 831 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 5.6 6 6.1 6.2 6.3 6.4 A/D Trim register (ADTRIM - 0x4003 4034). Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware-triggered conversion . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . Accuracy vs. digital receiver . . . . . . . . . . . . DMA control . . . . . . . . . . . . . . . . . . . . . . . . . 577 578 578 578 578 578 5.2 5.3 5.4 5.5 A/D Global Data Register (AD0GDR 0x4003 4004) . . . . . . . . . . . . . . . . . . . . . . . . A/D Interrupt Enable register (AD0INTEN 0x4003 400C) . . . . . . . . . . . . . . . . . . . . . . . . A/D Data Registers (AD0DR0 to AD0DR7 0x4003 4010 to 0x4003 402C) . . . . . . . . . . . A/D Status register (ADSTAT - 0x4003 4030) 575 575 576 577 Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) 1 2 3 4 4.1 Basic configuration . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . D/A Converter Register (DACR 0x4008 C000) . . . . . . . . . . . . . . . . . . . . . . . . 579 579 579 580 4.2 4.3 5 5.1 5.2 580 D/A Converter Control register (DACCTRL 0x4008 C004) . . . . . . . . . . . . . . . . . . . . . . . D/A Converter Counter Value register (DACCNTVAL - 0x4008 C008). . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA counter . . . . . . . . . . . . . . . . . . . . . . . . Double buffering. . . . . . . . . . . . . . . . . . . . . . 580 581 581 581 581 Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 1 2 3 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.2 4.2.1 4.2.2 4.2.3 5 5.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 583 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Functional description . . . . . . . . . . . . . . . . . 584 DMA controller functional description . . . . . . 584 AHB slave interface . . . . . . . . . . . . . . . . . . . 584 Control logic and register bank . . . . . . . . . . . 585 DMA request and response interface . . . . . . 585 Channel logic and channel register bank . . . 585 Interrupt request . . . . . . . . . . . . . . . . . . . . . . 585 AHB master interface . . . . . . . . . . . . . . . . . . 585 Channel hardware . . . . . . . . . . . . . . . . . . . . 588 DMA request priority . . . . . . . . . . . . . . . . . . . 588 Interrupt generation . . . . . . . . . . . . . . . . . . . 588 DMA system connections . . . . . . . . . . . . . . . 588 DMA request signals . . . . . . . . . . . . . . . . . . 588 DMA response signals . . . . . . . . . . . . . . . . . 588 DMA request connections . . . . . . . . . . . . . . 589 Register description . . . . . . . . . . . . . . . . . . . 590 DMA Interrupt Status register (DMACIntStat 0x5000 4000) . . . . . . . . . . . . . . . . . . . . . . . . 592 DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004). . . 592 DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008) . 592 DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C) . . . . . . . . . 592 DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010) . . . . . . . . . . 593 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.20.1 5.2 5.3 5.4 5.5 DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014) . . . . . 593 DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018) . . . . . 593 DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C) . . . . . . . 594 DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020). . . . . . . . . 594 DMA Software Single Request register (DMACSoftSReq - 0x5000 4024). . . . . . . . . 595 DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000 4028). . . . . . . . 595 DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C) . . . . . . . 595 DMA Configuration register (DMACConfig 0x5000 4030) . . . . . . . . . . . . . . . . . . . . . . . . 596 DMA Synchronization register (DMACSync 0x5000 4034) . . . . . . . . . . . . . . . . . . . . . . . . 596 DMA Request Select register (DMAReqSel 0x400F C1C4) . . . . . . . . . . . . . . . . . . . . . . . 597 DMA Channel registers . . . . . . . . . . . . . . . . 597 DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0). . . . . . . . 598 DMA Channel Destination Address registers (DMACCxDestAddr - 0x5000 41x4). . . . . . . 598 DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8). . . . . . . . . . . . 598 DMA channel control registers (DMACCxControl 0x5000 41xC). . . . . . . . . . . . . . . . . . . . . . . . 599 Protection and access information. . . . . . . . 599 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 832 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 6.1.7 6.2 6.2.1 6.2.2 6.2.3 6.3 6.3.1 6.4 6.4.1 6.5 6.5.1 Programming a DMA channel . . . . . . . . . . . 605 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . 605 Peripheral-to-memory or memory-to-peripheral DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 Peripheral-to-peripheral DMA flow. . . . . . . . 606 Memory-to-memory DMA flow . . . . . . . . . . . 607 Interrupt requests . . . . . . . . . . . . . . . . . . . . . 607 Hardware interrupt sequence flow . . . . . . . . 608 Address generation . . . . . . . . . . . . . . . . . . . 608 Word-aligned transfers across a boundary . 608 Scatter/gather . . . . . . . . . . . . . . . . . . . . . . . 608 Linked list items . . . . . . . . . . . . . . . . . . . . . . 609 5.21 5.21.1 5.21.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0) . . . . . . . . . Lock control . . . . . . . . . . . . . . . . . . . . . . . . . Transfer type. . . . . . . . . . . . . . . . . . . . . . . . . Using the DMA controller . . . . . . . . . . . . . . . Programming the DMA controller . . . . . . . . . Enabling the DMA controller . . . . . . . . . . . . . Disabling the DMA controller . . . . . . . . . . . . Enabling a DMA channel . . . . . . . . . . . . . . . Disabling a DMA channel . . . . . . . . . . . . . . . Setting up a new DMA transfer. . . . . . . . . . . Halting a DMA channel . . . . . . . . . . . . . . . . . 601 603 603 604 604 604 604 604 604 604 605 Chapter 32: LPC17xx Flash memory interface and programming 1 2 3 3.1 3.1.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 4 5 6 7 7.1 7.2 7.3 7.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 612 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 Memory map after any reset. . . . . . . . . . . . . 613 Criterion for Valid User Code . . . . . . . . . . . . 613 Communication protocol . . . . . . . . . . . . . . . . 614 ISP command format . . . . . . . . . . . . . . . . . . 614 ISP response format . . . . . . . . . . . . . . . . . . . 614 ISP data format. . . . . . . . . . . . . . . . . . . . . . . 614 ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 615 ISP command abort . . . . . . . . . . . . . . . . . . . 615 Interrupts during IAP. . . . . . . . . . . . . . . . . . . 615 RAM used by ISP command handler . . . . . . 615 RAM used by IAP command handler . . . . . . 615 Boot process flowchart . . . . . . . . . . . . . . . . . 616 Sector numbers . . . . . . . . . . . . . . . . . . . . . . . 617 Code Read Protection (CRP) . . . . . . . . . . . . 618 ISP commands . . . . . . . . . . . . . . . . . . . . . . . . 620 Unlock . . . . . . . . . . . . . . . . . 620 Set Baud Rate . . . . 621 Echo . . . . . . . . . . . . . . . . . . . . . . . 621 Write to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 Read Memory . . . 622 Prepare sector(s) for write operation . . . . . . . . . . 623 Copy RAM to Flash . . . . . . . . . . . . . . . . 623 Go . . . . . . . . . . . . . . . . . 624 Erase sector(s) . . . . . . . . . . . . . . . . . . . . . . . 624 Blank check sector(s) . . . . . . . . . . . . . . . . . . . . . . . 625 Read Part Identification number . . . . . . . . . . 625 7.12 7.13 7.14 7.5 7.6 7.7 7.8 7.9 7.10 7.11 Read Boot Code version number. . . . . . . . . 626 Read device serial number . . . . . . . . . . . . . 626 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 7.15 ISP Return Codes . . . . . . . . . . . . . . . . . . . . 627 8 IAP commands . . . . . . . . . . . . . . . . . . . . . . . 628 8.1 Prepare sector(s) for write operation . . . . . . 630 8.2 Copy RAM to Flash . . . . . . . . . . . . . . . . . . . 630 8.3 Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . 631 8.4 Blank check sector(s). . . . . . . . . . . . . . . . . . 631 8.5 Read part identification number . . . . . . . . . . 631 8.6 Read Boot Code version number. . . . . . . . . 632 8.7 Read device serial number . . . . . . . . . . . . . 632 8.8 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 8.9 Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . 633 8.10 IAP Status Codes . . . . . . . . . . . . . . . . . . . . . 633 9 JTAG flash programming interface . . . . . . . 633 10 Flash signature generation . . . . . . . . . . . . . 634 10.1 Register description for signature generation 634 10.1.1 Signature generation address and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 10.1.2 Signature generation result registers . . . . . . 635 10.1.3 Flash Module Status register (FMSTAT 0x0x4008 4FE0). . . . . . . . . . . . . . . . . . . . . . 636 10.1.4 Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8) . . . . . . . . . . . . . . . . . . . . 636 10.2 Algorithm and procedure for signature generation . . . . . . . . . . . . . . . . . . . . . . . . . . 637 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 833 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information Chapter 33: LPC17xx JTAG, Serial Wire Debug, and Trace 1 2 3 4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . 638 638 638 638 5 6 6.1 7 Debug Notes . . . . . . . . . . . . . . . . . . . . . . . . . 639 Debug memory re-mapping . . . . . . . . . . . . . 640 Memory Mapping Control register (MEMMAP 0x400F C040) . . . . . . . . . . . . . . . . . . . . . . . 640 JTAG TAP Identification . . . . . . . . . . . . . . . . 640 Chapter 34: Appendix: Cortex-M3 User Guide 1 1.1 1.1.1 1.1.2 1.1.3 ARM Cortex-M3 User Guide: Introduction. . About the processor and core peripherals . . System level interface . . . . . . . . . . . . . . . . . Integrated configurable debug . . . . . . . . . . . Cortex-M3 processor features and benefits summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cortex-M3 core peripherals . . . . . . . . . . . . . ARM Cortex-M3 User Guide: Instruction Set Instruction set summary . . . . . . . . . . . . . . . . Intrinsic functions . . . . . . . . . . . . . . . . . . . . . About the instruction descriptions. . . . . . . . . Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . Restrictions when using PC or SP . . . . . . . . Flexible second operand . . . . . . . . . . . . . . . Shift Operations . . . . . . . . . . . . . . . . . . . . . . Address alignment . . . . . . . . . . . . . . . . . . . . PC-relative expressions . . . . . . . . . . . . . . . . Conditional execution . . . . . . . . . . . . . . . . . . Instruction width selection. . . . . . . . . . . . . . . Memory access instructions . . . . . . . . . . . . . ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDR and STR, immediate offset . . . . . . . . . . LDR and STR, register offset . . . . . . . . . . . . LDR and STR, unprivileged . . . . . . . . . . . . . LDR, PC-relative. . . . . . . . . . . . . . . . . . . . . . LDM and STM . . . . . . . . . . . . . . . . . . . . . . . PUSH and POP . . . . . . . . . . . . . . . . . . . . . . LDREX and STREX . . . . . . . . . . . . . . . . . . . CLREX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General data processing instructions . . . . . . ADD, ADC, SUB, SBC, and RSB . . . . . . . . . AND, ORR, EOR, BIC, and ORN . . . . . . . . . ASR, LSL, LSR, ROR, and RRX . . . . . . . . . CLZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMP and CMN . . . . . . . . . . . . . . . . . . . . . . . MOV and MVN . . . . . . . . . . . . . . . . . . . . . . . MOVT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REV, REV16, REVSH, and RBIT . . . . . . . . . TST and TEQ . . . . . . . . . . . . . . . . . . . . . . . . Multiply and divide instructions . . . . . . . . . . . 641 641 642 642 1.1.4 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8 2.5.9 2.6 643 643 644 644 647 647 648 648 648 649 652 653 653 655 657 658 659 662 664 666 668 670 671 673 674 675 678 680 682 683 684 686 687 688 689 2.6.1 MUL, MLA, and MLS . . . . . . . . . . . . . . . . . . 690 2.6.2 UMULL, UMLAL, SMULL, and SMLAL . . . . 692 2.6.3 SDIV and UDIV . . . . . . . . . . . . . . . . . . . . . . 694 2.7 Saturating instructions . . . . . . . . . . . . . . . . . 695 2.7.1 SSAT and USAT. . . . . . . . . . . . . . . . . . . . . . 695 2.8 Bitfield instructions . . . . . . . . . . . . . . . . . . . . 697 2.8.1 BFC and BFI . . . . . . . . . . . . . . . . . . . . . . . . 698 2.8.2 SBFX and UBFX . . . . . . . . . . . . . . . . . . . . . 699 2.8.3 SXT and UXT. . . . . . . . . . . . . . . . . . . . . . . . 700 2.9 Branch and control instructions . . . . . . . . . . 702 2.9.1 B, BL, BX, and BLX . . . . . . . . . . . . . . . . . . . 703 2.9.2 CBZ and CBNZ . . . . . . . . . . . . . . . . . . . . . . 705 2.9.3 IT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 2.9.4 TBB and TBH. . . . . . . . . . . . . . . . . . . . . . . . 709 2.10 Miscellaneous instructions . . . . . . . . . . . . . . . 711 2.10.1 BKPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 2.10.2 CPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 2.10.3 DMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 2.10.4 DSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 2.10.5 ISB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 2.10.6 MRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 2.10.7 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 2.10.8 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 2.10.9 SEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 2.10.10 SVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 2.10.11 WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 2.10.12 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 3 ARM Cortex-M3 User Guide: Processor . . . 724 3.1 Programmers model . . . . . . . . . . . . . . . . . . 724 3.1.1 Processor mode and privilege levels for software execution . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 3.1.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 3.1.3 Core registers . . . . . . . . . . . . . . . . . . . . . . . 725 3.1.4 Exceptions and interrupts . . . . . . . . . . . . . . 732 3.1.5 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . 732 3.1.6 The Cortex Microcontroller Software Interface Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 3.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . 734 3.2.1 Memory regions, types and attributes . . . . . 734 continued >> UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 834 of 835 NXP Semiconductors UM10360 Chapter 35: LPC17xx Supplementary information 4.2.8 4.2.9 4.2.10 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 5 Software Trigger Interrupt Register . . . . . . . Level-sensitive and pulse interrupts. . . . . . . NVIC design hints and tips. . . . . . . . . . . . . . System control block . . . . . . . . . . . . . . . . . . The CMSIS mapping of the Cortex-M3 SCB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Control Register . . . . . . . . . . . . . . CPUID Base Register . . . . . . . . . . . . . . . . . Interrupt Control and State Register . . . . . . Vector Table Offset Register . . . . . . . . . . . . Application Interrupt and Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Register . . . . . . . . . . . . . . . Configuration and Control Register . . . . . . . System Handler Priority Registers . . . . . . . . System Handler Control and State Register Configurable Fault Status Register . . . . . . . Hard Fault Status Register. . . . . . . . . . . . . . Memory Management Fault Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Fault Address Register . . . . . . . . . . . . . System control block design hints and tips . System timer, SysTick . . . . . . . . . . . . . . . . . SysTick Control and Status Register . . . . . . SysTick Reload Value Register . . . . . . . . . . SysTick Current Value Register . . . . . . . . . . SysTick Calibration Value Register . . . . . . . SysTick design hints and tips. . . . . . . . . . . . Memory protection unit . . . . . . . . . . . . . . . . MPU Type Register . . . . . . . . . . . . . . . . . . . MPU Control Register . . . . . . . . . . . . . . . . . MPU Region Number Register . . . . . . . . . . MPU Region Base Address Register. . . . . . MPU Region Attribute and Size Register. . . MPU access permission attributes. . . . . . . . MPU mismatch. . . . . . . . . . . . . . . . . . . . . . . Updating an MPU region . . . . . . . . . . . . . . . MPU design hints and tips . . . . . . . . . . . . . . ARM Cortex-M3 User Guide: Glossary . . . . 761 761 762 764 764 764 765 765 767 768 769 770 771 772 774 778 778 778 779 780 780 781 781 781 782 783 784 785 786 786 787 789 790 790 793 794 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 Memory system ordering of memory accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . Behavior of memory accesses . . . . . . . . . . . Software ordering of memory accesses . . . . Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . Memory endianness . . . . . . . . . . . . . . . . . . . Synchronization primitives . . . . . . . . . . . . . . Programming hints for the synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception model . . . . . . . . . . . . . . . . . . . . . . Exception states . . . . . . . . . . . . . . . . . . . . . . Exception types . . . . . . . . . . . . . . . . . . . . . . Exception handlers . . . . . . . . . . . . . . . . . . . . Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . Exception priorities . . . . . . . . . . . . . . . . . . . . Interrupt priority grouping . . . . . . . . . . . . . . . Exception entry and return . . . . . . . . . . . . . . Fault handling . . . . . . . . . . . . . . . . . . . . . . . . Fault types . . . . . . . . . . . . . . . . . . . . . . . . . . Fault escalation and hard faults . . . . . . . . . . Fault status registers and fault address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power management . . . . . . . . . . . . . . . . . . . Entering sleep mode. . . . . . . . . . . . . . . . . . . Wakeup from sleep mode. . . . . . . . . . . . . . . The Wakeup Interrupt Controller . . . . . . . . . Power management programming hints. . . . ARM Cortex-M3 User Guide: Peripherals . . About the Cortex-M3 peripherals . . . . . . . . . Nested Vectored Interrupt Controller . . . . . . The CMSIS mapping of the Cortex-M3 NVIC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Set-enable Registers . . . . . . . . . . . Interrupt Clear-enable Registers. . . . . . . . . . Interrupt Set-pending Registers . . . . . . . . . . Interrupt Clear-pending Registers. . . . . . . . . Interrupt Active Bit Registers . . . . . . . . . . . . Interrupt Priority Registers . . . . . . . . . . . . . . 735 736 736 737 740 740 741 742 742 742 744 745 745 746 746 750 750 751 751 752 753 753 754 754 755 756 756 757 757 758 758 759 759 760 760 Chapter 35: LPC17xx Supplementary information 1 2 2.1 2.2 2.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 798 799 799 799 799 3 4 5 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 835 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 January 2010 Document identifier: UM10360_1