LPC1778FBD208

LPC178x/7x 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 2 — 27 May 2011 Objective data sheet 1. General description The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration. The Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals. The Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches. The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x is targeted to operate at up to 120 MHz CPU frequency. The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory controller (EMC), LCD (LPC178x only), Ethernet, USB Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers, three I2C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a Quadrature Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx and LPC23xx. 2. Features and benefits  Functional replacement for LPC23xx and 24xx family devices.  System:  ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory Protection Unit (MPU) supporting eight regions is included.  ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).  Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, and General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.  Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy. NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller       Cortex-M3 system tick timer, including an external clock input option.  Standard JTAG test/debug interface as well as Serial Wire Debug and Serial WireTrace Port options.  Emulation trace module supports real-time trace.  Boundary scan for simplified board testing.  Non-maskable Interrupt (NMI) input. Memory:  512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash.  96 kB on-chip SRAM includes: 64 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. Two 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for DMA memory as well as for general purpose instruction and data storage.  4032 byte on-chip EEPROM. LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays.  Dedicated DMA controller.  Selectable display resolution (up to 1024  768 pixels).  Supports up to 24-bit true-color mode. External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers. Serial interfaces:  Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB.  USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller.  Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one UART (USART4) supports IrDA, synchronous mode, and a smart card mode conforming to ISO7816-3.  Three SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.  Three enhanced I2C-bus interfaces, one with a true open-drain output supporting the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.  I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. LPC178X_7X Objective data sheet Rev. 2 — 27 May 2011 2 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller  CAN controller with two channels.  Digital peripherals:  SD/MMC memory card interface.  Up to 165 General Purpose I/O (GPIO) pins depending on the packaging, with configurable pull-up/down resistors, open-drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access and support Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt.  Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources.  Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.  Quadrature encoder interface that can monitor one external quadrature encoder.  Two standard PWM/timer blocks with external count input option.  One motor control PWM with support for three-phase motor control.  Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.  Event Recorder that can capture the clock value when an event occurs on any of three inputs. The event identification and the time it occurred are stored in registers. The Event Recorder is located in the RTC power domain and can therefore operate as long as there is RTC power.  Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal oscillator, watchdog warning interrupt, and safety features.  CRC Engine block can calculate a CRC on supplied data using one of three standard polynomials. The CRC engine can be used in conjunction with the DMA controller to generate a CRC without CPU involvement in the data transfer.  Analog peripherals:  12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.  10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.  Power control:  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes.  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2 pin interrupt, and NMI).  Brownout detect with separate threshold for interrupt and forced reset.  On-chip Power-On Reset (POR). LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 3 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller  Clock generation:  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, USB clock, or the watchdog timer clock.  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be used as a system clock.  An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator or the internal RC oscillator.  A second, dedicated PLL may be used for USB interface in order to allow added flexibility for the Main PLL settings.  Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions.  Unique device serial number for identification purposes.  Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C.  Available as LQFP208, TFBGA208, TFBGA180, and LQFP144 package. 3. Applications  Communications:  Point-of-sale terminals, web servers, multi-protocol bridges  Industrial/Medical:  Automation controllers, application control, robotics control, HVAC, PLC, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom  Consumer/Appliance:  Audio, MP3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment  Automotive:  After-market, car alarms, GPS/fleet monitors LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 4 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 4. Ordering information Table 1. Ordering information Package Name LPC1788 LPC1788FBD208 LPC1788FET208 LPC1788FET180 LPC1788FBD144 LPC1787 LPC1787FBD208 LPC1786 LPC1786FBD208 LPC1785 LPC1785FBD208 LPC1778 LPC1778FBD208 LPC1778FET208 LPC1778FET180 LPC1778FBD144 LPC1777 LPC1777FBD208 LPC1776 LPC1776FBD208 LPC1776FET180 LPC1774 LPC1774FBD208 LPC1774FBD144 LQFP208 LQFP144 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT459-1 SOT486-1 LQFP208 TFBGA180 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm thin fine-pitch ball grid array package; 180 balls; body 12  12 0.8 mm SOT459-1 SOT570-2 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LQFP208 TFBGA208 TFBGA180 LQFP144 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm thin fine-pitch ball grid array package; 180 balls; body 12  12 0.8 mm plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT459-1 SOT950-1 SOT570-2 SOT486-1 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LQFP208 TFBGA208 TFBGA180 LQFP144 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm thin fine-pitch ball grid array package; 180 balls; body 12  12 0.8 mm plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT459-1 SOT950-1 SOT570-2 SOT486-1 Description Version Type number LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 5 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 2. LPC178x/7x ordering options All parts include two CAN channels, three SSP interfaces, three I2C interfaces, one I2S interface, DAC, and an 8-channel 12-bit ADC. Type number Flash CPU Peripheral Total EEPROM Ethernet USB (kB) SRAM SRAM SRAM (byte) (kB) (kB) (kB) 64 64 64 64 64 64 64 64 64 64 64 64 32 32 16  2 16  2 16  2 16  2 16 16 16  2 16  2 16  2 16  2 16 16 8 8 96 96 96 96 80 80 96 96 96 96 80 80 40 40 4032 4032 4032 4032 4032 4032 4032 4032 4032 4032 4032 4032 2016 2016 Y Y Y N Y N Y Y Y N Y Y N N UART EMC [1] LCD QEI SD/ MMC LPC178x LPC1788FBD208/ 512 LPC1788FET208 LPC1788FET180 512 LPC1788FBD144 512 LPC1787FBD208 512 LPC1786FBD208 256 LPC1785FBD208 256 LPC177x LPC1778FBD208/ 512 LPC1778FET208 LPC1778FET180 512 LPC1778FBD144 512 LPC1777FBD208 512 LPC1776FBD208 256 LPC1776FET180 256 LPC1774FBD208 128 LPC1774FBD144 128 [1] [2] H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 H/O/D 5 D D 5 4[2] 32-bit 16-bit 8-bit 32-bit 32-bit 32-bit 32-bit 16-bit 8-bit 32-bit 32-bit 16-bit 32-bit 8-bit Y Y Y Y Y Y N N N N N N N N Y Y Y Y Y N Y Y Y Y Y Y N N Y Y Y Y Y Y Y Y Y Y Y Y N N Maximum data bus width of the External Memory Controller (EMC) depends on package size. Smaller widths may be used. USART4 not available. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 6 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 5. Block diagram debug port JTAG interface EMULATION TRACE MODULE TEST/DEBUG INTERFACE ARM CORTEX-M3 LPC178x/7x CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls slave ROM slave MULTILAYER AHB MATRIX SRAM 96/80/40 kB slave EMC slave LCD(1) I-code bus D-code bus system bus MPU GPDMA CONTROLLER ETHERNET(1) USB DEVICE/ HOST(1)/OTG(1) master master master slave HIGH-SPEED GPIO APB slave group 0 SSP1 UART0/1 I2C0/1 CAN 0/1 TIMER 0/1 WINDOWED WDT PWM0/1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL EVENT RECORDER 32 kHz OSCILLATOR RTC CRC slave slave AHB TO APB BRIDGE 0 slave AHB TO APB BRIDGE 1 slave FLASH ACCELERATOR FLASH 512/256/128/64 kB 4032 B/ 2016 B EEPROM APB slave group 1 SSP0/2 UART2/3 USART4(1) I2C2 SD/MMC(1) TIMER2/3 QUADRATURE ENCODER(1) DAC I2S MOTOR CONTROL PWM SYSTEM CONTROL BACKUP REGISTERS RTC POWER DOMAIN = connected to GPDMA 002aaf528 (1) Not available on all parts. See Table 2. Fig 1. LPC178X_7X Block diagram All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 7 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 6.1 Pinning 208 157 156 105 104 4 3 5 6 7 8 9 53 002aaf518 1 LPC178x/7xFBD208 52 Fig 2. Pin configuration (LQFP208) ball A1 index area 1 A B C D E F G H J K L M N P R T U 2 10 12 14 16 11 13 15 17 LPC178x/7x 002aaf529 Transparent top view Fig 3. Pin configuration (TFBGA208) LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 8 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller ball A1 index area LPC178x/7x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aaf519 Transparent top view Fig 4. Pin configuration (TFBGA180) 144 1 109 108 LPC178x/7x 36 37 72 73 002aaf520 Fig 5. Pin configuration (LQFP144) 6.2 Pin description I/O pins on the LPC178x/7x are 5V tolerant and have input hysteresis unless otherwise indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5V tolerant and the input voltage must be limited to the voltage at the ADC positive reference pin (VREFP). All port pins Pn[m] are multiplexed, and the functions appear in their order defined in the FUNC bits of the corresponding IOCON register. Each port pin can support up to eight multiplexed functions. IOCON register FUNC values which are reserved are noted as “R” in the pin configuration table LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 9 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] Pin LQFP144 P0[0] to P0[31] P0[0] 94 U15 M10 66 [3] I/O Type[2] Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. P0[0] — General purpose digital input/output pin. CAN_RD1 — CAN1 receiver input. U3_TXD — Transmitter output for UART3. I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). U0_TXD — Transmitter output for UART0. P0[1] — General purpose digital input/output pin. CAN_TD1 — CAN1 transmitter output. U3_RXD — Receiver input for UART3. I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). U0_RXD — Receiver input for UART0. P0[2] — General purpose digital input/output pin. U0_TXD — Transmitter output for UART0. U3_TXD — Transmitter output for UART3. P0[3] — General purpose digital input/output pin. U0_RXD — Receiver input for UART0. U3_RXD — Receiver input for UART3. P0[4] — General purpose digital input/output pin. I2S_RX_SCK — I2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. CAN_RD2 — CAN2 receiver input. T2_CAP0 — Capture input for Timer 2, channel 0. R — Function reserved. R — Function reserved. R — Function reserved. LCD_VD[0] — LCD data. I/O I O I/O I/O I/O O I I/O I I/O O O I/O I I I/O I/O I I O I; PU P0[1] 96 T14 N11 67 [3] I; PU P0[2] 202 C4 D5 141 [3] I; PU P0[3] 204 D6 A3 142 [3] I; PU P0[4] 168 B12 A11 116 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 10 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P0[5] 166 C12 B11 115 I; PU I/O I/O Type[2] P0[5] — General purpose digital input/output pin. I2S_RX_WS — I2S Receive word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. CAN_TD2 — CAN2 transmitter output. T2_CAP1 — Capture input for Timer 2, channel 1. R — Function reserved. R — Function reserved. R — Function reserved. LCD_VD[1] — LCD data. P0[6] — General purpose digital input/output pin. I2S_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. SSP1_SSEL1 — Slave Select for SSP1. T2_MAT0 — Match output for Timer 2, channel 0. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. R — Function reserved. R — Function reserved. LCD_VD[8] — LCD data. P0[7] — General purpose digital input/output pin. I2S_TX_SCK — I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. SSP1_SCK — Serial Clock for SSP1. T2_MAT1 — Match output for Timer 2, channel 1. RTC_EV0 — Event input 0 to Event Monitor/Recorder. R — Function reserved. R — Function reserved. LCD_VD[9] — LCD data. O I O I/O I/O I/O O O O I/O I/O O I O P0[6] 164 D13 D11 113 [3] I; PU P0[7] 162 C13 B12 112 [4] I; IA I/O LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 11 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [4] Pin LQFP144 P0[8] 160 A15 C12 111 I; IA I/O I/O Type[2] P0[8] — General purpose digital input/output pin. I2S_TX_WS — I2S Transmit word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. SSP1_MISO — Master In Slave Out for SSP1. T2_MAT2 — Match output for Timer 2, channel 2. RTC_EV1 — Event input 1 to Event Monitor/Recorder. R — Function reserved. R — Function reserved. LCD_VD[16] — LCD data. P0[9] — General purpose digital input/output pin. I2S_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. SSP1_MOSI — Master Out Slave In for SSP1. T2_MAT3 — Match output for Timer 2, channel 3. RTC_EV2 — Event input 2 to Event Monitor/Recorder. R — Function reserved. R — Function reserved. LCD_VD[17] — LCD data. P0[10] — General purpose digital input/output pin. U2_TXD — Transmitter output for UART2. I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad). T3_MAT0 — Match output for Timer 3, channel 0. R — Function reserved. R — Function reserved. R — Function reserved. LCD_VD[5] — LCD data. I/O O I O I/O I/O O I O I/O O I/O O O P0[9] 158 C14 A13 109 [4] I; IA I/O P0[10] 98 T15 L10 69 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 12 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P0[11] 100 R14 P12 70 I; PU I/O I I/O O O Type[2] P0[11] — General purpose digital input/output pin. U2_RXD — Receiver input for UART2. I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). T3_MAT1 — Match output for Timer 3, channel 1. R — Function reserved. R — Function reserved. R — Function reserved. LCD_VD[10] — LCD data. P0[12] — General purpose digital input/output pin. USB_PPWR2 — Port Power enable signal for USB port 2. SSP1_MISO — Master In Slave Out for SSP1. ADC0_IN[6] — A/D converter 0, input 6. When configured as an ADC input, the digital function of the pin must be disabled. P0[13] — General purpose digital input/output pin. USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. SSP1_MOSI — Master Out Slave In for SSP1. ADC0_IN[7] — A/D converter 0, input 7. When configured as an ADC input, the digital function of the pin must be disabled. P0[14] — General purpose digital input/output pin. USB_HSTEN2 — Host Enabled status for USB port 2. SSP1_SSEL — Slave Select for SSP1. USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. P0[15] — General purpose digital input/output pin. U1_TXD — Transmitter output for UART1. SSP0_SCK — Serial clock for SSP0. P0 [16] — General purpose digital input/output pin. U1_RXD — Receiver input for UART1. SSP0_SSEL — Slave Select for SSP0. P0[17] — General purpose digital input/output pin. U1_CTS — Clear to Send input for UART1. SSP0_MISO — Master In Slave Out for SSP0. I/O O I/O I I/O O I/O I I/O O I/O O I/O O I/O I/O I I/O I/O I I/O P0[12] 41 R1 J4 29 [5] I; PU P0[13] 45 R2 J5 32 [5] I; PU P0[14] 69 T7 M5 48 [3] I; PU P0[15] 128 J16 H13 89 [3] I; PU P0[16] 130 J14 H14 90 [3] I; PU P0[17] 126 K17 J12 87 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 13 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P0[18] 124 K15 J13 86 I; PU I/O I I/O I/O I O I/O O Type[2] P0[18] — General purpose digital input/output pin. U1_DCD — Data Carrier Detect input for UART1. SSP0_MOSI — Master Out Slave In for SSP0. P0[19] — General purpose digital input/output pin. U1_DSR — Data Set Ready input for UART1. SD_CLK — Clock output line for SD card interface. I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). R — Function reserved. R — Function reserved. R — Function reserved. LCD_VD[13] — LCD data. P0[20] — General purpose digital input/output pin. U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. SD_CMD — Command line for SD card interface. I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). R — Function reserved. R — Function reserved. R — Function reserved. LCD_VD[14] — LCD data. P0[21] — General purpose digital input/output pin. U1_RI — Ring Indicator input for UART1. SD_PWR — Power Supply Enable for external SD card power supply. U4_OE — RS-485/EIA-485 output enable signal for UART4. CAN_RD1 — CAN1 receiver input. U4_SCLK — USART 4 clock input or output in synchronous mode. I/O O I/O I/O O I/O I O O I I/O P0[19] 122 L17 J10 85 [3] I; PU P0[20] 120 M17 K14 83 [3] I; PU P0[21] 118 M16 K11 82 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 14 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [6] Pin LQFP144 P0[22] 116 N17 L14 80 I; PU I/O O Type[2] P0[22] — General purpose digital input/output pin. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. SD_DAT[0] — Data line 0 for SD card interface. U4_TXD — Transmitter output for USART4 (input/output in smart card mode). CAN_TD1 — CAN1 transmitter output. P0[23] — General purpose digital input/output pin. ADC0_IN[0] — A/D converter 0, input 0. When configured as an ADC input, the digital function of the pin must be disabled. I2S_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. T3_CAP0 — Capture input for Timer 3, channel 0. P0[24] — General purpose digital input/output pin. ADC0_IN[1] — A/D converter 0, input 1. When configured as an ADC input, the digital function of the pin must be disabled. I2S_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. T3_CAP1 — Capture input for Timer 3, channel 1. P0[25] — General purpose digital input/output pin. ADC0_IN[2] — A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled. I2S_RX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. U3_TXD — Transmitter output for UART3. P0[26] — General purpose digital input/output pin. ADC0_IN[3] — A/D converter 0, input 3. When configured as an ADC input, the digital function of the pin must be disabled. DAC_OUT — D/A converter output. When configured as the DAC output, the digital function of the pin must be disabled. U3_RXD — Receiver input for UART3. P0[27] — General purpose digital input/output pin. I2C0_SDA — I2C0 data input/output. (this pin uses a specialized I2C pad). USB_SDA1 — I2C serial data for communication with an external USB transceiver. © NXP B.V. 2011. All rights reserved. I/O O O P0[23] 18 H1 F5 13 [5] I; PU I/O I I/O I P0[24] 16 G2 E1 11 [5] I; PU I/O I I/O I P0[25] 14 F1 E4 10 [5] I; PU I/O I I/O O P0[26] 12 E1 D1 8 [7] I; PU I/O I O I P0[27] 50 T1 L3 35 [8] I/O I/O I/O LPC178X_7X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 2 — 27 May 2011 15 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [8] Pin LQFP144 P0[28] 48 R3 M1 34 I/O I/O I/O Type[2] P0[28] — General purpose digital input/output pin. I2C0_SCL — I2C0 clock input/output (this pin uses a specialized I2C pad. USB_SCL1 — I2C serial clock for communication with an external USB transceiver. P0[29] — General purpose digital input/output pin. USB_D+1 — USB port 1 bidirectional D+ line. EINT0 — External interrupt 0 input. P0[30] — General purpose digital input/output pin. USB_D1 — USB port 1 bidirectional D line. EINT1 — External interrupt 1 input. P0[31] — General purpose digital input/output pin. USB_D+2 — USB port 2 bidirectional D+ line. Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block P1[0] — General purpose digital input/output pin. ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). R — Function reserved. T3_CAP1 — Capture input for Timer 3, channel 1. SSP2_SCK — Serial clock for SSP2. P1[1] — General purpose digital input/output pin. ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). R — Function reserved. T3_MAT3 — Match output for Timer 3, channel 3. SSP2_MOSI — Master Out Slave In for SSP2. P1[2] — General purpose digital input/output pin. ENET_TXD2 — Ethernet transmit data 2 (MII interface). SD_CLK — Clock output line for SD card interface. PWM0[1] — Pulse Width Modulator 0, output 1. P1[3] — General purpose digital input/output pin. ENET_TXD3 — Ethernet transmit data 3 (MII interface). SD_CMD — Command line for SD card interface. PWM0[2] — Pulse Width Modulator 0, output 2. I/O I/O I I/O I/O I I/O I/O I/O I/O O I I/O I/O O O I/O I/O O O O I/O O I/O O P0[29] 61 U4 K5 42 [9] P0[30] 62 R6 N4 43 [9] P0[31] P1[0] to P1[31] P1[0] 51 T2 N1 36 [9] 196 A3 B5 136 [3] I; PU P1[1] 194 B5 A5 135 [3] I; PU P1[2] 185 D9 B7 - [3] I; PU P1[3] 177 A10 A9 - [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 16 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P1[4] 192 A5 C6 133 I; PU I/O O O I/O Type[2] P1[4] — General purpose digital input/output pin. ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface). R — Function reserved. T3_MAT2 — Match output for Timer 3, channel 2. SSP2_MISO — Master In Slave Out for SSP2. P1[5] — General purpose digital input/output pin. ENET_TX_ER — Ethernet Transmit Error (MII interface). SD_PWR — Power Supply Enable for external SD card power supply. PWM0[3] — Pulse Width Modulator 0, output 3. P1[6] — General purpose digital input/output pin. ENET_TX_CLK — Ethernet Transmit Clock (MII interface). SD_DAT[0] — Data line 0 for SD card interface. PWM0[4] — Pulse Width Modulator 0, output 4. P1[7] — General purpose digital input/output pin. ENET_COL — Ethernet Collision detect (MII interface). SD_DAT[1] — Data line 1 for SD card interface. PWM0[5] — Pulse Width Modulator 0, output 5. P1[8] — General purpose digital input/output pin. ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). R — Function reserved. T3_MAT1 — Match output for Timer 3, channel 1. SSP2_SSEL — Slave Select for SSP2. P1[9] — General purpose digital input/output pin. ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). R — Function reserved. T3_MAT0 — Match output for Timer 3, channel 0. P1[10] — General purpose digital input/output pin. ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). R — Function reserved. T3_CAP0 — Capture input for Timer 3, channel 0. I/O O O O I/O I I/O O I/O I I/O O I/O I O I/O I/O I O I/O I I P1[5] 156 A17 B13 - [3] I; PU P1[6] 171 B11 B10 - [3] I; PU P1[7] 153 D14 C13 - [3] I; PU P1[8] 190 C7 B6 132 [3] I; PU P1[9] 188 A6 D7 131 [3] I; PU P1[10] 186 C8 A7 129 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 17 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P1[11] 163 A14 A12 - I; PU I/O I I/O O Type[2] P1[11] — General purpose digital input/output pin. ENET_RXD2 — Ethernet Receive Data 2 (MII interface). SD_DAT[2] — Data line 2 for SD card interface. PWM0[6] — Pulse Width Modulator 0, output 6. P1[12] — General purpose digital input/output pin. ENET_RXD3 — Ethernet Receive Data (MII interface). SD_DAT[3] — Data line 3 for SD card interface. PWM0_CAP0 — Capture input for PWM0, channel 0. P1[13] — General purpose digital input/output pin. ENET_RX_DV — Ethernet Receive Data Valid (MII interface). P1[14] — General purpose digital input/output pin. ENET_RX_ER — Ethernet receive error (RMII/MII interface). R — Function reserved. T2_CAP0 — Capture input for Timer 2, channel 0. P1[15] — General purpose digital input/output pin. ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). R — Function reserved. I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad). P1[16] — General purpose digital input/output pin. ENET_MDC — Ethernet MIIM clock. I2S_TX_MCLK — I2S transmit master clock. P1[17] — General purpose digital input/output pin. ENET_MDIO — Ethernet MIIM data input and output. I2S_RX_MCLK — I2S receive master clock. P1[18] — General purpose digital input/output pin. USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. PWM1[1] — Pulse Width Modulator 1, channel 1 output. T1_CAP0 — Capture input for Timer 1, channel 0. R — Function reserved. SSP1_MISO — Master In Slave Out for SSP1. I/O I I/O I I/O I I/O I I I/O I I/O I/O O O I/O I/O O I/O O O I I/O P1[12] 157 A16 A14 - [3] I; PU P1[13] P1[14] 147 D16 184 A7 D14 D8 128 [3] I; PU I; PU [3] P1[15] 182 A8 A8 126 [3] I; PU P1[16] 180 D10 B8 125 [3] I; PU P1[17] 178 A9 C9 123 [3] I; PU P1[18] 66 P7 L5 46 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 18 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P1[19] 68 U6 P5 47 I; PU I/O O O I O I/O O Type[2] P1[19] — General purpose digital input/output pin. USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver). USB_PPWR1 — Port Power enable signal for USB port 1. T1_CAP1 — Capture input for Timer 1, channel 1. MC_0A — Motor control PWM channel 0, output A. SSP1_SCK — Serial clock for SSP1. U2_OE — RS-485/EIA-485 output enable signal for UART2. P1[20] — General purpose digital input/output pin. USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver). PWM1[2] — Pulse Width Modulator 1, channel 2 output. QEI_PHA — Quadrature Encoder Interface PHA input. MC_FB0 — Motor control PWM channel 0 feedback input. SSP0_SCK — Serial clock for SSP0. LCD_VD[6] — LCD data. LCD_VD[10] — LCD data. P1[21] — General purpose digital input/output pin. USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver). PWM1[3] — Pulse Width Modulator 1, channel 3 output. SSP0_SSEL — Slave Select for SSP0. MC_ABORT — Motor control PWM, active low fast abort. R — Function reserved. LCD_VD[7] — LCD data. LCD_VD[11] — LCD data. P1[22] — General purpose digital input/output pin. USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver). USB_PWRD1 — Power Status for USB port 1 (host power switch). T1_MAT0 — Match output for Timer 1, channel 0. MC_0B — Motor control PWM channel 0, output B. SSP1_MOSI — Master Out Slave In for SSP1. LCD_VD[8] — LCD data. LCD_VD[12] — LCD data. I/O O O I I I/O O O I/O O O I/O I O O I/O I I O O I/O O O P1[20] 70 U7 K6 49 [3] I; PU P1[21] 72 R8 N6 50 [3] I; PU P1[22] 74 U8 M6 51 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 19 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P1[23] 76 P9 N7 53 I; PU I/O I O I I I/O O O Type[2] P1[23] — General purpose digital input/output pin. USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver). PWM1[4] — Pulse Width Modulator 1, channel 4 output. QEI_PHB — Quadrature Encoder Interface PHB input. MC_FB1 — Motor control PWM channel 1 feedback input. SSP0_MISO — Master In Slave Out for SSP0. LCD_VD[9] — LCD data. LCD_VD[13] — LCD data. P1[24] — General purpose digital input/output pin. USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver). PWM1[5] — Pulse Width Modulator 1, channel 5 output. QEI_IDX — Quadrature Encoder Interface INDEX input. MC_FB2 — Motor control PWM channel 2 feedback input. SSP0_MOSI — Master Out Slave in for SSP0. LCD_VD[10] — LCD data. LCD_VD[14] — LCD data. P1[25] — General purpose digital input/output pin. USB_LS1 — Low Speed status for USB port 1 (OTG transceiver). USB_HSTEN1 — Host Enabled status for USB port 1. T1_MAT1 — Match output for Timer 1, channel 1. MC_1A — Motor control PWM channel 1, output A. CLKOUT — Selectable clock output. LCD_VD[11] — LCD data. LCD_VD[15] — LCD data. P1[26] — General purpose digital input/output pin. USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver). PWM1[6] — Pulse Width Modulator 1, channel 6 output. T0_CAP0 — Capture input for Timer 0, channel 0. MC_1B — Motor control PWM channel 1, output B. SSP1_SSEL — Slave Select for SSP1. LCD_VD[12] — LCD data. LCD_VD[20] — LCD data. I/O I O I I I/O O O I/O O O O O O O O I/O O O I O I/O O O P1[24] 78 T9 P7 54 [3] I; PU P1[25] 80 T10 L7 56 [3] I; PU P1[26] 82 R10 P8 57 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 20 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P1[27] 88 T12 M9 61 I; PU I/O I I I O O O Type[2] P1[27] — General purpose digital input/output pin. USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver). USB_OVRCR1 — USB port 1 Over-Current status. T0_CAP1 — Capture input for Timer 0, channel 1. CLKOUT — Selectable clock output. R — Function reserved. LCD_VD[13] — LCD data. LCD_VD[21] — LCD data. P1[28] — General purpose digital input/output pin. USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver). PWM1_CAP0 — Capture input for PWM1, channel 0. T0_MAT0 — Match output for Timer 0, channel 0. MC_2A — Motor control PWM channel 2, output A. SSP0_SSEL — Slave Select for SSP0. LCD_VD[14] — LCD data. LCD_VD[22] — LCD data. P1[29] — General purpose digital input/output pin. USB_SDA1 — USB port 1 I2C serial data (OTG transceiver). PWM1_CAP1 — Capture input for PWM1, channel 1. T0_MAT1 — Match output for Timer 0, channel 0. MC_2B — Motor control PWM channel 2, output B. U4_TXD — Transmitter output for USART4 (input/output in smart card mode). LCD_VD[15] — LCD data. LCD_VD[23] — LCD data. P1[30] — General purpose digital input/output pin. USB_PWRD2 — Power Status for USB port 2. USB_VBUS — Monitors the presence of USB bus power. This signal must be HIGH for USB reset to occur. I I/O O ADC0_IN[4] — A/D converter 0, input 4. When configured as an ADC input, the digital function of the pin must be disabled. I2C0_SDA — I2C0 data input/output (this pin does not use a specialized I2C pad. U3_OE — RS-485/EIA-485 output enable signal for UART3. I/O I/O I O O I/O O O I/O I/O I O O O O O I/O I I P1[28] 90 T13 P10 63 [3] I; PU P1[29] 92 U14 N10 64 [3] I; PU P1[30] 42 P2 K3 30 [5] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 21 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [5] Pin LQFP144 P1[31] 40 P1 K2 28 I; PU I/O I I/O I I/O Type[2] P1[31] — General purpose digital input/output pin. USB_OVRCR2 — Over-Current status for USB port 2. SSP1_SCK — Serial Clock for SSP1. ADC0_IN[5] — A/D converter 0, input 5. When configured as an ADC input, the digital function of the pin must be disabled. I2C0_SCL — I2C0 clock input/output (this pin does not use a specialized I2C pad. Port 2: Port 2 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. P2[0] — General purpose digital input/output pin. PWM1[1] — Pulse Width Modulator 1, channel 1 output. U1_TXD — Transmitter output for UART1. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. LCD_PWR — LCD panel power enable. P2[1] — General purpose digital input/output pin. PWM1[2] — Pulse Width Modulator 1, channel 2 output. U1_RXD — Receiver input for UART1. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. LCD_LE — Line end signal. P2[2] — General purpose digital input/output pin. PWM1[3] — Pulse Width Modulator 1, channel 3 output. U1_CTS — Clear to Send input for UART1. T2_MAT3 — Match output for Timer 2, channel 3. R — Function reserved. TRACEDATA[3] — Trace data, bit 3. R — Function reserved. LCD_DCLK — LCD panel clock. I/O I/O O O O I/O O I O I/O O I O O O P2[0] to P2[31] P2[0] 154 B17 D12 107 [3] I; PU P2[1] 152 E14 C14 106 [3] I; PU P2[2] 150 D15 E11 105 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 22 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P2[3] 144 E16 E13 100 I; PU I/O O I O O O Type[2] P2[3] — General purpose digital input/output pin. PWM1[4] — Pulse Width Modulator 1, channel 4 output. U1_DCD — Data Carrier Detect input for UART1. T2_MAT2 — Match output for Timer 2, channel 2. R — Function reserved. TRACEDATA[2] — Trace data, bit 2. R — Function reserved. LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT). P2[4] — General purpose digital input/output pin. PWM1[5] — Pulse Width Modulator 1, channel 5 output. U1_DSR — Data Set Ready input for UART1. T2_MAT1 — Match output for Timer 2, channel 1. R — Function reserved. TRACEDATA[1] — Trace data, bit 1. R — Function reserved. LCD_ENAB_M — STN AC bias drive or TFT data enable output. P2[5] — General purpose digital input/output pin. PWM1[6] — Pulse Width Modulator 1, channel 6 output. U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. T2_MAT0 — Match output for Timer 2, channel 0. R — Function reserved. TRACEDATA[0] — Trace data, bit 0. R — Function reserved. LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). P2[6] — General purpose digital input/output pin. PWM1_CAP0 — Capture input for PWM1, channel 0. U1_RI — Ring Indicator input for UART1. T2_CAP0 — Capture input for Timer 2, channel 0. U2_OE — RS-485/EIA-485 output enable signal for UART2. TRACECLK — Trace clock. LCD_VD[0] — LCD data. LCD_VD[4] — LCD data. © NXP B.V. 2011. All rights reserved. P2[4] 142 D17 E14 99 [3] I; PU I/O O I O O O P2[5] 140 F16 F12 97 [3] I; PU I/O O O O O O P2[6] 138 E17 F13 96 [3] I; PU I/O I I I O O O O LPC178X_7X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 2 — 27 May 2011 23 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P2[7] 136 G16 G11 95 I; PU I/O I O Type[2] P2[7] — General purpose digital input/output pin. CAN_RD2 — CAN2 receiver input. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. R — Function reserved. R — Function reserved. R — Function reserved. LCD_VD[1] — LCD data. LCD_VD[5] — LCD data. P2[8] — General purpose digital input/output pin. CAN_TD2 — CAN2 transmitter output. U2_TXD — Transmitter output for UART2. U1_CTS — Clear to Send input for UART1. ENET_MDC — Ethernet MIIM clock. R — Function reserved. LCD_VD[2] — LCD data. LCD_VD[6] — LCD data. P2[9] — General purpose digital input/output pin. USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an external 1.5 k resistor under the software control. Used with the SoftConnect USB feature. U2_RXD — Receiver input for UART2. U4_RXD — Receiver input for USART4. ENET_MDIO — Ethernet MIIM data input and output. R — Function reserved. LCD_VD[3] — LCD data. LCD_VD[7] — LCD data. P2[10] — General purpose digital input/output pin. This pin includes a 5 ns input glitch filter. A LOW on this pin while RESET is LOW forces the on-chip boot loader to take over control of the part after a reset and go into ISP mode. I I EINT0 — External interrupt 0 input. NMI — Non-maskable interrupt input. O O I/O O O I O O O I/O O I I I/O I I I/O P2[8] 134 H15 G14 93 [3] I; PU P2[9] 132 H16 H11 92 [3] I; PU P2[10] 110 N15 M13 76 [10] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 24 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [10] Pin LQFP144 P2[11] 108 T17 M12 75 I; PU I/O I I/O I/O Type[2] P2[11] — General purpose digital input/output pin. This pin includes a 5 ns input glitch filter. EINT1 — External interrupt 1 input. SD_DAT[1] — Data line 1 for SD card interface. I2S_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. R — Function reserved. R — Function reserved. R — Function reserved. LCD_CLKIN — LCD clock. P2[12] — General purpose digital input/output pin. This pin includes a 5 ns input glitch filter. EINT2 — External interrupt 2 input. SD_DAT[2] — Data line 2 for SD card interface. I2S_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. LCD_VD[4] — LCD data. LCD_VD[3] — LCD data. LCD_VD[8] — LCD data. LCD_VD[18] — LCD data. P2[13] — General purpose digital input/output pin. This pin includes a 5 ns input glitch filter. EINT3 — External interrupt 3 input. SD_DAT[3] — Data line 3 for SD card interface. I2S_TX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. R — Function reserved. LCD_VD[5] — LCD data. LCD_VD[9] — LCD data. LCD_VD[19] — LCD data. P2[14] — General purpose digital input/output pin. EMC_CS2 — LOW active Chip Select 2 signal. I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). T2_CAP0 — Capture input for Timer 2, channel 0. © NXP B.V. 2011. All rights reserved. O P2[12] 106 N14 N14 73 [10] I; PU I/O I I/O I/O O O O O P2[13] 102 T16 M11 71 [10] I; PU I/O I I/O I/O O O O P2[14] 91 R12 [3] I; PU I/O O I/O I LPC178X_7X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 2 — 27 May 2011 25 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P2[15] 99 P13 - - I; PU I/O O I/O I Type[2] P2[15] — General purpose digital input/output pin. EMC_CS3 — LOW active Chip Select 3 signal. I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). T2_CAP1 — Capture input for Timer 2, channel 1. P2[16] — General purpose digital input/output pin. EMC_CAS — LOW active SDRAM Column Address Strobe. P2[17] — General purpose digital input/output pin. EMC_RAS — LOW active SDRAM Row Address Strobe. P2[18] — General purpose digital input/output pin. EMC_CLK[0] — SDRAM clock 0. P2[19] — General purpose digital input/output pin. EMC_CLK[1] — SDRAM clock 1. P2[20] — General purpose digital input/output pin. EMC_DYCS0 — SDRAM chip select 0. P2[21] — General purpose digital input/output pin. EMC_DYCS1 — SDRAM chip select 1. P2[22] — General purpose digital input/output pin. EMC_DYCS2 — SDRAM chip select 2. SSP0_SCK — Serial clock for SSP0. T3_CAP0 — Capture input for Timer 3, channel 0. P2[23] — General purpose digital input/output pin. EMC_DYCS3 — SDRAM chip select 3. SSP0_SSEL — Slave Select for SSP0. T3_CAP1 — Capture input for Timer 3, channel 1. P2[24] — General purpose digital input/output pin. EMC_CKE0 — SDRAM clock enable 0. P2[25] — General purpose digital input/output pin. EMC_CKE1 — SDRAM clock enable 1. P2[26] — General purpose digital input/output pin. EMC_CKE2 — SDRAM clock enable 2. SSP0_MISO — Master In Slave Out for SSP0. T3_MAT0 — Match output for Timer 3, channel 0. I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O I I/O O I/O I I/O O I/O O I/O O I/O O P2[16] P2[17] P2[18] P2[19] P2[20] P2[21] P2[22] 87 95 59 67 73 81 85 R11 R13 U3 R7 T8 U11 U12 P9 P11 P3 N5 P6 N8 - - [3] I; PU I; PU I; PU I; PU I; PU I; PU I; PU [3] [6] [6] [3] [3] [3] P2[23] 64 U5 - - [3] I; PU P2[24] P2[25] P2[26] 53 54 57 P5 R4 T4 P1 P2 - - [3] I; PU I; PU I; PU [3] [3] LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 26 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P2[27] 47 P3 - - I; PU I/O O I/O O Type[2] P2[27] — General purpose digital input/output pin. EMC_CKE3 — SDRAM clock enable 3. SSP0_MOSI — Master Out Slave In for SSP0. T3_MAT1 — Match output for Timer 3, channel 1. P2[28] — General purpose digital input/output pin. EMC_DQM0 — Data mask 0 used with SDRAM and static devices. P2[29] — General purpose digital input/output pin. EMC_DQM1 — Data mask 1 used with SDRAM and static devices. P2[30] — General purpose digital input/output pin. EMC_DQM2 — Data mask 2 used with SDRAM and static devices. I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad). T3_MAT2 — Match output for Timer 3, channel 2. P2[31] — General purpose digital input/output pin. EMC_DQM3 — Data mask 3 used with SDRAM and static devices. I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). T3_MAT3 — Match output for Timer 3, channel 3. Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. P3[0] — General purpose digital input/output pin. EMC_D[0] — External memory data line 0. P3[1] — General purpose digital input/output pin. EMC_D[1] — External memory data line 1. P3[2] — General purpose digital input/output pin. EMC_D[2] — External memory data line 2. P3[3] — General purpose digital input/output pin. EMC_D[3] — External memory data line 3. P3[4] — General purpose digital input/output pin. EMC_D[4] — External memory data line 4. P3[5] — General purpose digital input/output pin. EMC_D[5] — External memory data line 5. I/O O I/O O I/O O I/O O I/O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P2[28] 49 P4 M2 - [3] I; PU I; PU I; PU P2[29] 43 N3 L1 - [3] P2[30] 31 L4 - - [3] P2[31] 39 N2 - - [3] I; PU P3[0] to P3[31] P3[0] P3[1] P3[2] P3[3] P3[4] P3[5] 197 B4 201 B3 207 B1 3 13 17 E4 F2 G1 D6 E6 A2 G5 D3 E3 137 140 144 2 9 12 [3] I; PU I; PU I; PU I; PU I; PU I; PU [3] [3] [3] [3] [3] LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 27 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P3[6] P3[7] P3[8] P3[9] P3[10] P3[11] P3[12] P3[13] P3[14] 23 27 J1 L1 F4 G3 A6 A4 B3 B2 A1 C1 F1 16 19 - I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O Type[2] P3[6] — General purpose digital input/output pin. EMC_D[6] — External memory data line 6. P3[7] — General purpose digital input/output pin. EMC_D[7] — External memory data line 7. P3[8] — General purpose digital input/output pin. EMC_D[8] — External memory data line 8. P3[9] — General purpose digital input/output pin. EMC_D[9] — External memory data line 9. P3[10] — General purpose digital input/output pin. EMC_D[10] — External memory data line 10. P3[11] — General purpose digital input/output pin. EMC_D[11] — External memory data line 11. P3[12] — General purpose digital input/output pin. EMC_D[12] — External memory data line 12. P3[13] — General purpose digital input/output pin. EMC_D[13] — External memory data line 13. P3[14] — General purpose digital input/output pin. EMC_D[14] — External memory data line 14. On POR, this pin serves as the BOOT0 pin. P3[15] — General purpose digital input/output pin. EMC_D[15] — External memory data line 15. P3[16] — General purpose digital input/output pin. EMC_D[16] — External memory data line 16. PWM0[1] — Pulse Width Modulator 0, output 1. U1_TXD — Transmitter output for UART1. P3[17] — General purpose digital input/output pin. EMC_D[17] — External memory data line 17. PWM0[2] — Pulse Width Modulator 0, output 2. U1_RXD — Receiver input for UART1. P3[18] — General purpose digital input/output pin. EMC_D[18] — External memory data line 18. PWM0[3] — Pulse Width Modulator 0, output 3. U1_CTS — Clear to Send input for UART1. I/O I/O O I I/O I/O O I [3] 191 D8 199 C5 205 B2 208 D5 1 7 21 D4 C1 H2 [3] [3] [3] [3] [3] [3] [3] P3[15] P3[16] 28 M1 G4 - - [3] 137 F17 [3] P3[17] 143 F15 - - [3] I; PU P3[18] 151 C15 - - [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 28 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P3[19] 161 B14 - - I; PU I/O I/O O I Type[2] P3[19] — General purpose digital input/output pin. EMC_D[19] — External memory data line 19. PWM0[4] — Pulse Width Modulator 0, output 4. U1_DCD — Data Carrier Detect input for UART1. P3[20] — General purpose digital input/output pin. EMC_D[20] — External memory data line 20. PWM0[5] — Pulse Width Modulator 0, output 5. U1_DSR — Data Set Ready input for UART1. P3[21] — General purpose digital input/output pin. EMC_D[21] — External memory data line 21. PWM0[6] — Pulse Width Modulator 0, output 6. U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. P3[22] — General purpose digital input/output pin. EMC_D[22] — External memory data line 22. PWM0_CAP0 — Capture input for PWM0, channel 0. U1_RI — Ring Indicator input for UART1. P3[23] — General purpose digital input/output pin. EMC_D[23] — External memory data line 23. PWM1_CAP0 — Capture input for PWM1, channel 0. T0_CAP0 — Capture input for Timer 0, channel 0. P3[24] — General purpose digital input/output pin. EMC_D[24] — External memory data line 24. PWM1[1] — Pulse Width Modulator 1, output 1. T0_CAP1 — Capture input for Timer 0, channel 1. P3[25] — General purpose digital input/output pin. EMC_D[25] — External memory data line 25. PWM1[2] — Pulse Width Modulator 1, output 2. T0_MAT0 — Match output for Timer 0, channel 0. P3[26] — General purpose digital input/output pin. EMC_D[26] — External memory data line 26. PWM1[3] — Pulse Width Modulator 1, output 3. T0_MAT1 — Match output for Timer 0, channel 1. STCLK — System tick timer clock input. I/O I/O O I I/O I/O O O I/O I/O I I I/O I/O I I I/O I/O O I I/O I/O O O I/O I/O O O I P3[20] 167 A13 - - [3] I; PU P3[21] 175 C10 - - [3] I; PU P3[22] 195 C6 - - [3] I; PU P3[23] 65 T6 M4 45 [3] I; PU P3[24] 58 R5 N3 40 [3] I; PU P3[25] 56 U2 M3 39 [3] I; PU P3[26] 55 T3 K7 38 [3] I; PU LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 29 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P3[27] 203 A1 - - I; PU I/O I/O O I Type[2] P3[27] — General purpose digital input/output pin. EMC_D[27] — External memory data line 27. PWM1[4] — Pulse Width Modulator 1, output 4. T1_CAP0 — Capture input for Timer 1, channel 0. P3[28] — General purpose digital input/output pin. EMC_D[28] — External memory data line 28. PWM1[5] — Pulse Width Modulator 1, output 5. T1_CAP1 — Capture input for Timer 1, channel 1. P3[29] — General purpose digital input/output pin. EMC_D[29] — External memory data line 29. PWM1[6] — Pulse Width Modulator 1, output 6. T1_MAT0 — Match output for Timer 1, channel 0. P3[30] — General purpose digital input/output pin. EMC_D[30] — External memory data line 30. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. T1_MAT1 — Match output for Timer 1, channel 1. P3[31] — General purpose digital input/output pin. EMC_D[31] — External memory data line 31. R — Function reserved. T1_MAT2 — Match output for Timer 1, channel 2. Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. P4[0] — General purpose digital input/output pin. EMC_A[0] — External memory address line 0. P4[1] — General purpose digital input/output pin. EMC_A[1] — External memory address line 1. P4[2] — General purpose digital input/output pin. EMC_A[2] — External memory address line 2. P4[3] — General purpose digital input/output pin. EMC_A[3] — External memory address line 3. P4[4] — General purpose digital input/output pin. EMC_A[4] — External memory address line 4. P4[5] — General purpose digital input/output pin. EMC_A[5] — External memory address line 5. © NXP B.V. 2011. All rights reserved. P3[28] 5 D2 - - [3] I; PU I/O I/O O I P3[29] 11 F3 - - [3] I; PU I/O I/O O O P3[30] 19 H3 - - [3] I; PU I/O I/O O O P3[31] 25 J3 [3] I; PU I/O I/O O P4[0] to P4[31] P4[0] P4[1] P4[2] P4[3] P4[4] P4[5] 75 79 83 97 U9 U10 T11 U16 L6 M7 M8 K9 P13 H10 52 55 58 68 72 74 [3] I/O I; PU I; PU I; PU I; PU I; PU I; PU I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O [3] [3] [3] 103 R15 107 R16 [3] [3] LPC178X_7X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 2 — 27 May 2011 30 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P4[6] P4[7] P4[8]/ P4[9] P4[10] P4[11] P4[12] P4[13] P4[14] P4[15] P4[16] P4[17] P4[18] P4[19] P4[20] 113 M14 K10 K12 J11 H12 78 84 88 91 I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type[2] P4[6] — General purpose digital input/output pin. EMC_A[6] — External memory address line 6. P4[7] — General purpose digital input/output pin. EMC_A[7] — External memory address line 7. P4[8] — General purpose digital input/output pin. EMC_A[8] — External memory address line 8. P4[9] — General purpose digital input/output pin. EMC_A[9] — External memory address line 9. P4[10] — General purpose digital input/output pin. EMC_A[10] — External memory address line 10. P4[11] — General purpose digital input/output pin. EMC_A[11] — External memory address line 11. P4[12] — General purpose digital input/output pin. EMC_A[12] — External memory address line 12. P4[13] — General purpose digital input/output pin. EMC_A[13] — External memory address line 13. P4[14] — General purpose digital input/output pin. EMC_A[14] — External memory address line 14. P4[15] — General purpose digital input/output pin. EMC_A[15] — External memory address line 15. P4[16] — General purpose digital input/output pin. EMC_A[16] — External memory address line 16. P4[17] — General purpose digital input/output pin. EMC_A[17] — External memory address line 17. P4[18] — General purpose digital input/output pin. EMC_A[18] — External memory address line 18. P4[19] — General purpose digital input/output pin. EMC_A[19] — External memory address line 19. P4[20] — General purpose digital input/output pin. EMC_A[20] — External memory address line 20. I2C2_SDA — I2C2 data input/output ((this pin does not use a specialized I2C pad). SSP1_SCK — Serial Clock for SSP1. 121 L16 127 J17 131 H17 135 G17 145 F14 149 C16 155 B16 159 B15 173 A11 101 U17 104 P14 105 P15 111 P16 [3] [3] [3] G12 94 F11 F10 B14 E8 C10 N12 N13 P14 101 104 108 110 120 - [3] [3] [3] [3] [3] [3] [3] [3] [3] M14 - [3] 109 R17 [3] LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 31 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P4[21] 115 M15 - - I; PU I/O I/O I/O I/O Type[2] P4[21] — General purpose digital input/output pin. EMC_A[21] — External memory address line 21. I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). SSP1_SSEL — Slave Select for SSP1. P4[22] — General purpose digital input/output pin. EMC_A[22] — External memory address line 22. U2_TXD — Transmitter output for UART2. SSP1_MISO — Master In Slave Out for SSP1. P4[23] — General purpose digital input/output pin. EMC_A[23] — External memory address line 23. U2_RXD — Receiver input for UART2. SSP1_MOSI — Master Out Slave In for SSP1. P4[24] — General purpose digital input/output pin. EMC_OE — LOW active Output Enable signal. P4[25] — General purpose digital input/output pin. EMC_WE — LOW active Write Enable signal. P4[26] — General purpose digital input/output pin. EMC_BLS0 — LOW active Byte Lane select signal 0. P4[27] — General purpose digital input/output pin. EMC_BLS1 — LOW active Byte Lane select signal 1. P4 [28] — General purpose digital input/output pin. EMC_BLS2 — LOW active Byte Lane select signal 2. U3_TXD — Transmitter output for UART3. T2_MAT0 — Match output for Timer 2, channel 0. R — Function reserved. LCD_VD[6] — LCD data. LCD_VD[10] — LCD data. LCD_VD[2] — LCD data. I/O I/O O I/O I/O I/O I I/O I/O O I/O O I/O O I/O O I/O O O O O O O P4[22] 123 K14 - - [3] I; PU P4[23] 129 J15 - - [3] I; PU P4[24] P4[25] P4[26] P4[27] P4[28] 183 B8 179 B9 119 L15 C8 D9 K13 F14 D10 127 124 118 [3] I; PU I; PU I; PU I; PU I; PU [3] [3] 139 G15 170 C11 [3] [3] LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 32 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [3] Pin LQFP144 P4[29] 176 B10 B9 122 I; PU I/O O I O I/O O O O Type[2] P4[29] — General purpose digital input/output pin. EMC_BLS3 — LOW active Byte Lane select signal 3. U3_RXD — Receiver input for UART3. T2_MAT1 — Match output for Timer 2, channel 1. I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). LCD_VD[7] — LCD data. LCD_VD[11] — LCD data. LCD_VD[3] — LCD data. P4[30] — General purpose digital input/output pin. EMC_CS0 — LOW active Chip Select 0 signal. P4[31] — General purpose digital input/output pin. EMC_CS1 — LOW active Chip Select 1 signal. Port 5: Port 5 is a 5-bit I/O port with individual direction controls for each bit. The operation of port 5 pins depends upon the pin function selected via the pin connect block. P5[0] — General purpose digital input/output pin. EMC_A[24] — External memory address line 24. SSP2_MOSI — Master Out Slave In for SSP2. T2_MAT2 — Match output for Timer 2, channel 2. P5[1] — General purpose digital input/output pin. EMC_A[25] — External memory address line 25. SSP2_MISO — Master In Slave Out for SSP2. T2_MAT3 — Match output for Timer 2, channel 3. P5[2] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. T3_MAT2 — Match output for Timer 3, channel 2. R — Function reserved. I2C0_SDA — I2C0 data input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus). I/O O I/O O I/O I/O I/O I/O O I/O I/O I/O O I/O O I/O P4[30] P4[31] P5[0] to P5[4] 187 B7 193 A4 C7 E7 130 134 [3] I; PU I; PU [3] P5[0] 9 F4 E5 6 [3] I; PU P5[1] 30 J4 H1 21 [3] I; PU P5[2] 117 L14 L12 81 [11] LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 33 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] [11] Pin LQFP144 P5[3] 141 G14 G10 98 I/O I I/O Type[2] P5[3] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. U4_RXD — Receiver input for USART4. I2C0_SCL — I2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus. P5[4] — General purpose digital input/output pin. U0_OE — RS-485/EIA-485 output enable signal for UART0. R — Function reserved. T3_MAT3 — Match output for Timer 3, channel 3. U4_TXD — Transmitter output for USART4 (input/output in smart card mode). JTAG_TDO (SWO) — Test Data Out for JTAG interface. Also used as Serial wire trace output. JTAG_TDI — Test Data In for JTAG interface. JTAG_TMS (SWDIO) — Test Mode Select for JTAG interface. Also used as Serial wire debug data input/output. JTAG_TRST — Test Reset for JTAG interface. JTAG_TCK (SWDCLK) — Test Clock for JTAG interface. This clock must be slower than 1 /6 of the CPU clock (CCLK) for the JTAG interface to operate. Also used as serial wire clock. External reset input. A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin includes a 20 ns input glitch filter. Reset status output. A LOW output on this pin indicates that the device is in the reset state, for any reason. This reflects the RESET input pin and all internal reset sources. RTC_ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. Input to the RTC 32 kHz ultra-low power oscillator circuit. Output from the RTC 32 kHz ultra-low power oscillator circuit. USB_D2 — USB port 2 bidirectional D line. RTC power supply: 3.3 V on this pin supplies power to the RTC. I/O O O O O I I I I I O O I O I/O I P5[4] 206 C3 C4 143 [3] I; PU JTAG_TDO (SWO) JTAG_TDI JTAG_TMS (SWDIO) JTAG_TRST JTAG_TCK (SWDCLK) RESET 2 4 6 8 10 D3 C2 E3 D1 E2 B1 C3 C2 D4 D2 1 3 4 5 7 [3] [3] [3] [3] [3] 35 M2 J1 24 [12] RSTOUT 29 K3 H2 20 [3] RTC_ALARM RTCX1 RTCX2 USB_D2 VBAT 37 34 36 52 38 N1 K2 L2 U1 M3 H5 J2 J3 N2 K1 26 23 25 37 27 [13] [14] [15] [14] [15] [9] LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 34 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA208 Ball TFBGA180 Symbol Pin LQFP208 Description Reset state[1] Pin LQFP144 VDD(REG)(3V3) 26, H4, G1, 86, P11, N9, 174 D11 E9 20 G4 F2 18, 60, 121 14 S Type[2] 3.3 V regulator supply voltage: This is the power supply for the on-chip voltage regulator that supplies internal logic. Analog 3.3 V pad supply voltage: This can be connected to the same supply as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Note: this pin should be tied to 3.3V if the ADC and DAC are not used. 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the VBAT domain. S S S ADC positive reference voltage: This should be the same voltage as VDDA, but should be isolated to minimize noise and error. The voltage level on this pin is used as a reference for ADC and DAC. Note: this pin should be tied to 3.3V if the ADC and DAC are not used. Ground: 0 V reference for digital IO pins. G G Ground: 0 V reference for internal logic. G Analog ground: 0 V power supply and reference for the ADC and DAC. This should be the same voltage as VSS, but should be isolated to minimize noise and error. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. I O VDDA VDD(3V3) 15, 60, 71, 89, 112, 125, 146, 165, 181, 198 24 G3, P6, P8, U13, P17, K16, C17, B13, C9, D7 K1 E2, L4, K8, L11, J14, E12, E10, C5 41, 62, 77, 102, 114, 138 VREFP G2 17 VSS 33, 63, 77, 93, 114, 133, 148, 169, 189, 200 L3, T5, R9, P12, N16, H14, E15, A12, B6, A2 H4, P4, L9, L13, G13, D13, C11, B4 44, 65, 79, 103, 117, 139 VSSREG 32, D12, H3, 84, K4, L8, 172 P10 A10 22 J2 F3 22, 59, 119 15 VSSA XTAL1 XTAL2 44 46 M4 N4 L2 K4 31 33 [14] [16] [14] [16] [1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. LPC178X_7X Objective data sheet Rev. 2 — 27 May 2011 35 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller [2] [3] [4] [5] [6] [7] [8] I = Input; O = Output; G = Ground; S = Supply. 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the pad is disabled. 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [9] [10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [11] [12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [13] [14] Pad provides special analog functionality. [15] If the RTC is not used, these pins can be left floating. [16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Row A 1 5 9 13 17 Row B 1 5 9 13 17 Row C 1 5 9 13 17 Row D 1 5 LPC178X_7X Symbol P3[27] P1[4] P1[17] P3[20] P1[5] P3[2] P1[1] P4[25] VDD(3V3) P2[0] P3[13] P3[9] VDD(3V3) P0[7] VDD(3V3) JTAG_TRST P3[11] Ball Symbol 2 6 10 14 VSS P1[9] P1[3] P1[11] 2 6 10 14 P3[10] VSS P4[29] P3[19] 2 6 10 14 JTAG_TDI P3[22] P3[21] P0[9] 2 6 P3[28] P0[3] Ball 3 7 11 15 Symbol P1[0] P1[14] P4[15] P0[8] - Ball 4 8 12 16 Symbol P4[31] P1[15] VSS P1[12] - 3 7 11 15 P3[1] P4[30] P1[6] P4[14] - 4 8 12 16 P3[0] P4[24] P0[4] P4[13] - 3 7 11 15 P5[4] P1[8] P4[28] P3[18] - 4 8 12 16 P0[2] P1[10] P0[5] P4[12] - 3 7 JTAG_TDO (SWO) VDD(3V3) 4 8 P3[12] P3[8] © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 2 — 27 May 2011 36 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball 9 13 17 Row E 1 5 9 13 17 Row F 1 5 9 13 17 Row G 1 5 9 13 17 Row H 1 5 9 13 17 Row J 1 5 9 13 17 Row K 1 13 17 Row L 1 LPC178X_7X Symbol P1[2] P0[6] P2[4] P0[26] P2[6] P0[25] P3[16] P3[5] P4[10] P0[23] P4[9] P3[6] P4[8] VREFP P0[17] P3[7] Ball Symbol 10 14 P1[16] P1[7] 2 6 10 14 JTAG_TCK (SWDCLK) P2[1] 2 6 10 14 P3[4] P4[11] 2 6 10 14 P0[24] P5[3] 2 6 10 14 P3[14] VSS 2 6 10 14 VSSA P0[16] 2 14 RTCX1 P4[22] 2 RTCX2 Ball 11 15 Symbol VDD(REG)(3V3) P2[2] - Ball 12 16 Symbol VSSREG P1[13] - 3 7 11 15 JTAG_TMS (SWDIO) VSS - 4 8 12 16 P3[3] P2[3] - 3 7 11 15 P3[29] P3[17] - 4 8 12 16 P5[0] P2[5] - 3 7 11 15 VDD(3V3) P4[27] - 4 8 12 16 VDDA P2[7] - 3 7 11 15 P3[30] P2[8] - 4 8 12 16 VDD(REG)(3V3) P2[9] - 3 7 11 15 P3[31] P4[23] - 4 8 12 16 P5[1] P0[15] - 3 15 RSTOUT P0[18] - 4 16 VSSREG VDD(3V3) - 3 VSS 4 P2[30] © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 2 — 27 May 2011 37 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball 5 9 13 17 1 5 9 13 17 Row N 1 5 9 13 17 Row P 1 5 9 13 17 Row R 1 5 9 13 17 Row T 1 5 9 13 17 Row U 1 5 9 13 17 LPC178X_7X Symbol P0[19] P3[15] P0[20] RTC_ALARM P0[22] P1[31] P2[24] P1[23] P2[15] VDD(3V3) P0[12] P3[24] VSS P2[17] P4[20] P0[27] VSS P1[24] P1[28] P2[11] USB_D-2 P2[23] P4[0] VDD(3V3) P4[16]/EMC_A[16] Ball Symbol 6 10 14 P5[2] 2 6 10 14 RESET P4[6] 2 6 10 14 P2[31] P2[12 2 6 10 14 P1[30] VDD(3V3) VSSREG P4[17] 2 6 10 14 P0[13] P0[30] P1[26] P0[11] 2 6 10 14 P0[31] P3[23] P1[25] P0[1] 2 6 10 14 P3[25] P1[19] P4[1] P1[29] - Ball 7 11 15 Symbol P4[26] - Ball 8 12 16 Symbol P4[7] - Row M 3 7 11 15 VBAT P4[21] 3 7 11 15 P2[29] P2[10] 3 7 11 15 P2[27] P1[18] VDD(REG)(3V3) P4[18] 3 7 11 15 P0[28] P2[19] P2[16] P4[4] 3 7 11 15 P3[26] P0[14] P4[2] P0[10] 3 7 11 15 P2[18] P1[20] P2[21] P0[0] All information provided in this document is subject to legal disclaimers. 4 8 12 16 XTAL1 P0[21] - 4 8 12 16 XTAL2 VSS - 4 8 12 16 P2[28] VDD(3V3) VSS P4[19] - 4 8 12 16 P2[25] P1[21] P2[14] P4[5] - 4 8 12 16 P2[26] P2[20] P1[27] P2[13] - 4 8 12 16 P0[29] P1[22] P2[22] P4[3] © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 38 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Row A 5 9 13 Row B 1 5 9 13 Row C 1 5 9 13 Row D 1 5 9 13 Row E 1 5 9 13 Row F 1 5 9 13 Row G 1 5 9 13 Row H 1 5 9 13 P5[1] RTC_ALARM P0[15] 2 6 10 14 RSTOUT P4[5] P0[16] 3 7 11 VSSREG P2[9] 4 8 12 VSS P4[9] VDD(REG)(3V3) P3[3] VSS 2 6 10 14 VREFP P5[3] P2[8] 3 7 11 P3[7] P2[7] 4 8 12 P3[15] P4[10] P3[14] P0[23] P2[6] 2 6 10 14 VDDA P4[12] P4[27] 3 7 11 VSSA P4[11] 4 8 12 P3[6] P2[5] P0[24] P5[0] VDD(REG)(3V3) P2[3] 2 6 10 14 VDD(3V3) P3[1] VDD(3V3) P2[4] 3 7 11 P3[5] P4[31] P2[2] 4 8 12 P0[25] P4[14] VDD(3V3) P0[26] P0[2] P4[25] VSS 2 6 10 14 JTAG_TCK_SWDCLK 3 P3[0] P4[28] P1[13] 7 11 P3[4] P1[9] P0[6] 4 8 12 JTAG_TRST P1[14] P2[0] P3[13] VDD(3V3) P1[17] P1[7] 2 6 10 14 JTAG_TMS_SWDIO P1[4] P4[15] P2[1] 3 7 11 JTAG_TDI P4[30] VSS 4 8 12 P5[4] P4[24] P0[8] JTAG_TDO_SWO P1[0] P4[29] P1[5] 2 6 10 14 P3[11] P1[8] P1[6] P4[13] 3 7 11 P3[10] P1[2] P0[5] 4 8 12 VSS P1[16] P0[7] P1[1] P1[3] P0[9] 6 10 14 P3[8] VSSREG P1[12] 7 11 P1[10] P0[4] 8 12 P1[15] P1[11] Symbol Ball Symbol Ball Symbol Ball Symbol LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 39 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins). Ball Row J 1 5 9 13 Row K 1 5 9 13 Row L 1 5 9 13 1 5 9 13 Row N 1 5 9 13 Row P 1 5 9 13 P2[24] P1[19] P2[16] P4[4] 2 6 10 14 P2[25] P2[20] P1[28] P4[18] 3 7 11 P2[18] P1[24] P2[17] 4 8 12 VSS P1[26] P0[11] P0[31] P2[19] VDD(REG)(3V3) P4[17]/EMC_A[17] 2 6 10 14 USB_D-2 P1[21] P1[29] P2[12] 3 7 11 P3[24] P1[23] P0[1] 4 8 12 P0[30] P2[21] P4[16] P2[29] P1[18] VSS VSS P0[28] P0[14] P1[27] P2[10] 2 6 10 14 2 6 10 14 XTAL1 P4[0] P0[10] P0[22] P2[28] P1[22] P0[0] P4[19] 3 7 11 3 7 11 P0[27] P1[25] VDD(3V3) P3[25] P4[1] P2[13] 4 8 12 4 8 12 VDD(3V3) VSSREG P5[2] P3[23] P4[2] P2[11] VBAT P0[29] P4[3] P4[26] 2 6 10 14 P1[31] P1[20] P4[6] P0[20] 3 7 11 P1[30] P3[26] P0[21] 4 8 12 XTAL2 VDD(3V3) P4[7] RESET P0[13] P0[18] 2 6 10 14 RTCX1 P0[19] VDD(3V3) 3 7 11 RTCX2 P4[8] 4 8 12 P0[12] P0[17] Symbol Ball Symbol Ball Symbol Ball Symbol Row M 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 40 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website. 7.3 On-chip flash program memory The LPC178x/7x contain up to 512 kB of on-chip flash program memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 7.4 EEPROM The LPC178x/7x contains up to 4032 byte of on-chip byte-erasable and byte-programmable EEPROM data memory. 7.5 On-chip SRAM The LPC178x/7x contain a total of up to 96 kB on-chip static RAM data memory. This includes the main 64 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 7.6 Memory Protection Unit (MPU) The LPC178x/7x have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 41 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 7.7 Memory map Table 6. LPC178x/177x memory usage and details General Use On-chip non-volatile memory Address range details and description 0x0000 0000 - 0x0007 FFFF 0x0000 0000 - 0x0003 FFFF 0x0000 0000 - 0x0001 FFFF 0x0000 0000 - 0x0000 FFFF On-chip SRAM 0x1000 0000 - 0x1000 FFFF 0x1000 0000 - 0x1000 7FFF 0x1000 0000 - 0x1000 3FFF Boot ROM 0x2000 0000 to 0x3FFF FFFF On-chip SRAM (typically used for peripheral data) AHB peripherals 0x4000 0000 to 0x7FFF FFFF APB Peripherals 0x1FFF 0000 - 0x1FFF 1FFF 0x2000 0000 - 0x2000 1FFF 0x2002 0000 - 0x2000 3FFF 0x2000 4000 - 0x2000 7FFF 0x2008 0000 - 0x200B FFFF 0x4000 0000 - 0x4007 FFFF 0x4008 0000 - 0x400F FFFF 0x8000 0000 to 0xDFFF FFFF Off-chip Memory via the External Memory Controller Four static memory chip selects: 0x8000 0000 - 0x83FF FFFF 0x9000 0000 - 0x93FF FFFF 0x9800 0000 - 0x9BFF FFFF 0x9C00 0000 - 0x9FFF FFFF 0xA000 0000 - 0xAFFF FFFF 0xB000 0000 - 0xBFFF FFFF 0xC000 0000 - 0xCFFF FFFF 0xD000 0000 - 0xDFFF FFFF 0xE000 0000 to 0xE00F FFFF Cortex-M3 Private Peripheral Bus 0xE000 0000 - 0xE00F FFFF Static memory chip select 0 (up to 64 MB) Static memory chip select 1 (up to 64 MB) Static memory chip select 2 (up to 64 MB) Static memory chip select 3 (up to 64 MB) Dynamic memory chip select 0 (up to 256MB) Dynamic memory chip select 1 (up to 256MB) Dynamic memory chip select 2 (up to 256MB) Dynamic memory chip select 3 (up to 256MB) Cortex-M3 related functions, includes the NVIC and System Tick Timer. For devices with 512 kB of flash memory. For devices with 256 kB of flash memory. For devices with 128 kB of flash memory. For devices with 64 kB of flash memory. For devices with 64 kB of local SRAM. For devices with 32 kB of local SRAM. For devices with 16 kB of local SRAM. 8 kB Boot ROM with flash services. Peripheral RAM - bank 0 (first 8 kB) Peripheral RAM - bank 0 (second 8 kB) Peripheral RAM - bank 1 (16 kB) See Figure 6 for details APB0 Peripherals, up to 32 peripheral blocks of 16 kB each. APB1 Peripherals, up to 32 peripheral blocks of 16 kB each. Address range 0x0000 0000 to 0x1FFF FFFF Four dynamic memory chip selects: The LPC178x/7x incorporate several distinct memory regions, shown in the following figures. Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 42 of 117 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Objective data sheet Rev. 2 — 27 May 2011 43 of 117 LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors 0x4010 0000 0x400F C000 31 APB1 peripherals system control 30 - 17 reserved SD/MMC(1) QEI(1) motor control PWM reserved reserved SSP2 I2S USART4(1) I2C2 UART3 UART2 timer 3 timer 2 DAC SSP0 1 - 0 reserved 4 GB LPC178x/7x reserved private peripheral bus reserved EMC 4 x dynamic chip select(1) 0xA000 0000 EMC 4 x static chip select(1) reserved 0x4400 0000 peripheral bit-band alias addressing reserved APB1 peripherals 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 0x2900 0000 0x2800 0000 0x2400 0000 0x2200 0000 0x200A 0000 0x2008 0000 0x2000 8000 0x2000 4000 0x2000 0000 0x1FFF 2000 0x1FFF 0000 0x1001 0000 7 6 5 4 0x1000 0000 reserved 0x0008 0000 3 2 1 8 7 6 5 4 3 2 1 0 0x8000 0000 0xFFFF FFFF 0xE010 0000 0xE004 0000 0xE000 0000 23 APB0 peripherals 31 - 24 reserved I2C1 22 - 19 reserved 18 17 16 15 14 13 12 11 10 9 CAN2 CAN1 CAN common CAN AF registers CAN AF RAM ADC SSP1 pin connect GPIO interrupts RTC/event recorder + backup registers reserved I2C0 PWM1 PWM0 UART1 UART0 timer 1 timer 0 WWDT AHB peripherals EMC registers GPIO reserved CRC engine USB(1) LCD(1) Ethernet(1) GPDMA controller 0x4008 0000 0x4006 0000 0x4005 C000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 0x400C 0000 0x400B C000 0x400B 8000 0x400B 4000 0x400B 0000 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 0x4009 C000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 C000 0x4008 8000 0x4008 0000 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GB APB0 peripherals reserved reserved reserved AHB SRAM bit-band alias addressing reserved AHB peripherals reserved 16 kB AHB SRAM1(1) 16 kB AHB SRAM0(1) 0.5 GB reserved 8 kB boot ROM reserved I-code/D-code memory space 64 kB local static RAM(1) 32-bit ARM Cortex-M3 microcontroller 0x200A 0000 0x2009 C000 0x2009 8000 0x2009 4000 0x2009 0000 0x2008 C000 0x2008 8000 0x2008 4000 LPC178x/7x 0x0000 0400 0x0000 0000 active interrupt vectors + 256 words 0 GB 512 kB on-chip flash(1) 0x0000 0000 0 0x2008 0000 002aaf574 (1) Not available on all parts. See Table 2 and Table 7. Fig 6. LPC178x/7x memory map NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.8 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.8.1 Features • • • • • • Controls system exceptions and peripheral interrupts. In the LPC178x/7x, the NVIC supports 41 vectored interrupts. 32 programmable interrupt priority levels, with hardware priority level masking. Relocatable vector table. Non-Maskable Interrupt (NMI). Software interrupt generation. 7.8.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 7.9 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 7.10 External memory controller Remark: Supported memory size and type and EMC bus width vary for different parts (see Table 2). The EMC pin configuration for each part is shown in Table 7. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 44 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 7. Part External memory controller pin configuration Data bus pins Address bus pins EMC_A[25:0] Control pins SRAM SDRAM EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] not available LPC1788FBD208 EMC_D[31:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[1:0], EMC_CS[1:0], EMC_OE, EMC_WE EMC_BLS[3:2], EMC_CS[1:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS_[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[1:0], EMC_CS[1:0], EMC_OE, EMC_WE EMC_CS[1:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_CS[1:0], EMC_OE, EMC_WE LPC1788FET208 EMC_D[31:0] EMC_A[25:0] LPC1788FET180 EMC_D[15:0] EMC_A[19:0] LPC1788FBD144 EMC_D[7:0] EMC_A[15:0] LPC1787FBD208 EMC_D[31:0] EMC_A[25:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] not available EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] not available LPC1786FBD208 EMC_D[31:0] EMC_A[25:0] LPC1785FBD208 EMC_D[31:0] EMC_A[25:0] LPC1778FBD208 EMC_D[31:0] EMC_A[25:0] LPC1778FET208 EMC_D[31:0] EMC_A[25:0] LPC1778FET180 EMC_D[15:0] EMC_A[19:0] LPC1778FBD144 EMC_D[7:0] LPC1777FBD208 EMC_D[31:0] EMC_A[15:0] EMC_A[25:0] LPC1776FBD208 EMC_D[31:0] EMC_A[25:0] LPC1776FET180 EMC_D[15:0] EMC_A[19:0] LPC1774FBD208 EMC_D[31:0] EMC_A[25:0] LPC1774FBD144 EMC_D[7:0] EMC_A[15:0] LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 45 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. See Table 6 for EMC memory access. 7.10.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • • • • • Low transaction latency. Read and write buffers to reduce latency and to improve performance. 8/16/32 data and 16/20/26 address lines wide static memory support. 16 bit and 32 bit wide chip select SDRAM memory support. Static memory features include: – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.11 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master. The GPDMA controller allows data transfers between the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the I2S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be triggered by selected timer match conditions. Memory-to-memory transfers and transfers to or from GPIO are supported. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 46 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.11.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.12 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 7.12.1 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. • Supports CPU PIO or DMA back-to-back transfer. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 47 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation – 16-bit write: 2-cycle operation (8-bit x 2-cycle) – 32-bit write: 4-cycle operation (8-bit x 4-cycle) 7.13 LCD controller Remark: The LCD controller is available on parts LPC1788/87/86/85. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.13.1 Features • • • • AHB master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320  200, 320  240, 640  200, 640  240, 640  480, 800  600, and 1024  768. • • • • • • • • • • • • Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized, for color STN and TFT. 24 bpp true-color non-palettized, for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. LPC178X_7X Objective data sheet Rev. 2 — 27 May 2011 48 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.14 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.14.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 49 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.15 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85 and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. Details on typical USB interfacing solutions can be found in Section 14.1. 7.15.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM. 7.15.1.1 Features • • • • • Fully compliant with USB 2.0 Specification (full speed). Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. Supports Control, Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time. Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC178x/7x can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 7.15.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification. 7.15.2.1 Features • OHCI compliant • Two downstream ports LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 50 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Supports per-port power switching 7.15.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.15.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 7.16 SD/MMC card interface Remark: The SD/MMC card interface is available on parts LPC1788/87/86/85 and parts LPC1778/77/76. The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.16.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 7.17 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC178x/7x use accelerated GPIO functions: LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 51 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • • • • All GPIO registers are byte and half-word addressable. Entire port value can be written in one instruction. Support for Cortex-M3 bit banding. Support for use with the GPDMA controller. Additionally, any pin on Port 0 and Port 2 providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.17.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 7.18 12-bit ADC The LPC178x/7x contain one ADC. It is a single 12-bit successive approximation ADC with eight channels and DMA support. 7.18.1 Features • • • • • • • • • • 12-bit successive approximation ADC. Input multiplexing among eight pins. Power-down mode. Measurement range VSS to VREFP. 12-bit conversion rate: up to 400 kHz. Individual channels can be selected for conversion. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or Timer Match signal. Individual result registers for each ADC channel to reduce interrupt overhead. DMA support. 7.19 10-bit DAC The LPC178x/7x contain one DAC. The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 52 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.19.1 Features • • • • • • • 10-bit DAC Resistor string architecture Buffered output Power-down mode Selectable output drive Dedicated conversion timer DMA support 7.20 UARTs Remark: USART4 is not available on part LPC1774FBD144. The LPC178x/7x contain five UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.20.1 Features • • • • • Maximum UART data bit rate of 7.5 MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto-baud capability. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing. • All UARTs have DMA support for both transmit and receive. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • USART4 includes an IrDA mode to support infrared communication. • USART4 supports synchronous mode and a smart card mode conforming to ISO7816-3. 7.21 SSP serial I/O controller The LPC178x/7x contain three SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 53 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.21.1 Features • Maximum SSP speed of 60 Mbit/s (master) or 10 Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA 7.22 I2C-bus serial I/O controllers The LPC178x/7x contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.22.1 Features • All I2C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s (Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of up to 400 kbit/s. • The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0 using pins P5[2] and P5[3]. • • • • • Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus. • Serial clock synchronization allows devices with different bit rates to communicate via • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • Both I2C-bus controllers support multiple address recognition and a bus monitor mode. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 54 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.23 I2S-bus serial I/O controllers The LPC178x/7x contain one I2S-bus interface. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC178x/7x provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.23.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • • • • Configurable word select period in master mode (separately for I2S input and output). Two 8 word FIFO data buffers are provided, one for transmit and one for receive. Generates interrupt requests when buffer levels cross a programmable boundary. Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S input and I2S output. 7.24 CAN controller and acceptance filters The LPC178x/7x contain two CAN controllers. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. 7.24.1 Features • • • • LPC178X_7X Two CAN controllers and buses. Data rates to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 55 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.25 General purpose 32-bit timers/external event counters The LPC178x/7x include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.25.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 7.26 Pulse Width Modulator (PWM) The LPC178x/7x contain two PWMs. The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC178x/7x. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 56 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 7.26.1 Features • LPC178x/7x has two PWM blocks with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 7.27 Motor control PWM The LPC178x/7x contain one motor control PWM. The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 57 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2n (see Table 8). Table 8. 6 bit 8 bit 10 bit PWM speed at operating frequency 120 MHz PWM speed 1.875 MHz 0.468 MHz 0.117 MHz PWM resolution 7.28 Quadrature Encoder Interface (QEI) Remark: The QEI is available on parts LPC1788/87/86 and LPC1778/77/76 A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.28.1 Features • • • • • • • • • • Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with “less than” interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 7.29 ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC178x/7x, this timer can be clocked from the internal AHB clock or from a device pin. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 58 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.30 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.30.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. always running if the watchdog timer is enabled. • The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is 7.31 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC178x/7x is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC178x/7x is powered off. The RTC includes an alarm function that can wake up the LPC178x/7x from all reduced power modes with a time resolution of 1 s. 7.31.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 59 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller • • • • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. Periodic interrupts can be generated from increments of any field of the time registers. Backup registers (20 bytes) powered by VBAT. RTC power supply is isolated from the rest of the chip. 7.32 Event monitor/recorder The event monitor/recorder allows recording of tampering events in sealed product enclosures. Sensors report any attempt to open the enclosure, or to tamper with the device in any other way. The event monitor/recorder stores records of such events when the device is powered only by the backup battery. 7.32.1 Features • Supports three digital event inputs in the VBAT power domain. • An event is defined as a level change at the digital event inputs. • For each event channel, two timestamps mark the first and the last occurrence of an event. Each channel also has a dedicated counter tracking the total number of events. Timestamp values are taken from the RTC. • Runs in VBAT power domain, independent of system power supply. The event/recorder/monitor can therefore operate in Deep power-down mode. • • • • Very low power consumption. Interrupt available if system is running. A qualified event can be used as a wake-up trigger. State of event interrupts accessible by software through GPIO. 7.33 Clocking and power control 7.33.1 Crystal oscillators The LPC178x/7x include four independent oscillators. These are the main oscillator, the IRC oscillator, the watchdog oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC178x/7x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency. See Figure 7 for an overview of the LPC178x/7x clock generation. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 60 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller LPC178x/7x IRC oscillator MAIN PLL0 main oscillator (osc_clk) CLKSRCSEL (system clock select) ALT PLL1 alt_pll_clk pll_clk sysclk sysclk pll_clk CCLKSEL (CPU clock select) CPU CLOCK DIVIDER cclk PERIPHERAL CLOCK DIVIDER pclk EMC CLOCK DIVIDER emc_clk sysclk pll_clk alt_pll_clk USBCLKSEL (USB clock select) USB CLOCK DIVIDER usb_clk 002aaf531 Fig 7. LPC178x/7x clock generation block diagram 7.33.1.1 Internal RC oscillator The IRC may be used as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC178x/7x use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.33.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the alternate PLL1. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.33.2 for additional information. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 61 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.33.1.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.33.1.4 Watchdog oscillator The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the Watchdog Timer that is always running if the Watchdog Timer is enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to allow observe its frequency. In order to allow Watchdog Timer operation with minimum power consumption, which can be important in reduced power modes, the Watchdog oscillator frequency is not tightly controlled. The Watchdog oscillator frequency will vary over temperature and power supply within a particular part, and may vary by processing across different parts. This variation should be taken into account when determining Watchdog reload values. Within a particular part, temperature and power supply variations can produce up to a 17 % frequency variation. Frequency variation between devices under the same operating conditions can be up to 30 %. 7.33.2 Main PLL (PLL0) and Alternate PLL (Alt PLL, PLL1) PLL0 (also called the Main PLL) and PLL1 (also called the Alt PLL) are functionally identical, but have somewhat different input possibilities and output connections. These possibilities are shown in Figure 7. The Main PLL can receive its input from either the IRC or the main oscillator, and can potentially be used to provide the clocks to nearly everything on the device. The Alternate PLL receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the USB. The USB has timing needs that may not always be filled by the Main PLL. Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB clock through that route. The source for each clock must be selected via the CLKSEL registers, and can be further reduced by clock dividers as needed. PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only the Main PLL is used, then its output frequency must be an integer multiple of all other clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional dividers to bring the output down to the desired frequencies. The minimum output divider value is 2, insuring that the output of the PLLs have a 50 % duty cycle. If the USB is used, the possibilities for the CPU clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the PLL0 output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in conjunction with the PLL can meet the precision and jitter specifications for USB. It is due to these limitations that the Alt PLL is provided. The alternate PLL accepts an input clock frequency from the main oscillator in the range of 10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied up to a multiple of 48 MHz (192 MHz or 288 MHz as described above). LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 62 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.33.3 Wake-up timer The LPC178x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.33.4 Power control The LPC178x/7x support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, the peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC178x/7x also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 7.33.4.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence other than re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 63 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The DMA controller can continue to work in Sleep mode, and has access to the peripheral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. 7.33.4.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The clock divider registers are automatically reset to zero. The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. Wake-up from Deep Sleep mode can initiated by the NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 7.33.4.3 Power-down mode Power-down mode does everything that Deep-sleep mode does but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and the clock selection multiplexers are set to use the system clock sysclk (the reset state). The clock divider control registers are automatically reset to zero. If the Watchdog timer is running, it will continue running in Power-down mode. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 64 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.33.4.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before device operation can be restarted. The LPC178x/7x can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.33.4.5 Wake-up Interrupt Controller (WIC) The WIC allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 7.33.5 Peripheral power control A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 7.33.6 Power domains The LPC178x/7x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup registers. On the LPC178x/7x, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC178x/7x application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 65 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available. LPC178x/7x VDD(3V3) VSS REGULATOR VDD(REG)(3V3) to I/O pads to core to memories, peripherals, oscillators, PLLs MAIN POWER DOMAIN VBAT POWER SELECTOR ULTRA-LOW POWER REGULATOR BACKUP REGISTERS RTCX1 RTCX2 32 kHz OSCILLATOR RTC POWER DOMAIN REAL-TIME CLOCK DAC VDDA VREFP ADC VSSA ADC POWER DOMAIN 002aaf530 Fig 8. Power distribution 7.34 System control 7.34.1 Reset Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 66 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Section 7.33.3), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.34.2 Brownout detection The LPC178x/7x include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC178x/7x when the voltage on the VDD(REG)(3V3) pins falls below 2.65 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 7.34.3 Code security (Code Read Protection - CRP) This feature of the LPC178x/7x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 67 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.34.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. 7.34.5 AHB multilayer matrix The LPC178x/7x use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 7.34.6 External interrupt inputs The LPC178x/7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. The external interrupt input can optionally be used to wake up the processor from Power-down mode. 7.34.7 Memory mapping control The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC178x/7x is configured for 128 total interrupts. 7.35 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 68 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) VDD(REG)(3V3) VDDA Vi(VBAT) Vi(VREFP) VIA VI Parameter supply voltage (3.3 V) regulator supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT input voltage on pin VREFP analog input voltage input voltage on ADC related pins 5 V tolerant I/O pins; only valid when the VDD(3V3) supply voltage is present other I/O pins IDD ISS Ilatch supply current ground current I/O latch-up current per supply pin per ground pin (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C Tstg Ptot(pack) storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model; all pins [6] [5] [2] Conditions external rail Min 2.4 2.4 0.5 Max 3.6 3.6 +4.6 +4.6 +4.6 +5.1 +5.5 Unit V V V V V V V for the RTC 0.5 0.5 0.5 0.5 [2][3] 0.5 - VDD(3V3) + 0.5 100 100 100 V mA mA mA [4] [4] 65 - +150 1.5 C W VESD electrostatic discharge voltage 4000 +4000 V [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] [3] [4] [5] [6] Including voltage on outputs in 3-state mode. Not to exceed 4.6 V. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 69 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, TJ (C), can be calculated using the following equation: T J = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 10. Thermal characteristics VDD = 2.4 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Tj(max) Parameter maximum junction temperature Conditions Min Typ Max 125 Unit C LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 70 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Supply pins VDD(3V3) VDD(REG)(3V3) VDDA Vi(VBAT) Vi(VREFP) IDD(REG)(3V3) supply voltage (3.3 V) regulator supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT input voltage on pin VREFP regulator supply current active mode; code (3.3 V) while(1){} executed from flash; all peripherals disabled PCLK = CCLK/4 CCLK = 12 MHz; PLL disabled CCLK = 120 MHz; PLL enabled active mode; code [4] [3] Parameter Conditions external rail [2] Min 2.4 2.4 2.7 2.1 2.7 Typ[1] 3.3 3.3 3.3 3.3 3.3 Max 3.6 3.6 3.6 3.6 VDDA Unit V V V V V - 7.09 51.22 - mA mA [4] while(1){} executed from flash; all peripherals enabled; PCLK = CCLK/4 CCLK = 12 MHz; PLL disabled CCLK = 120 MHz; PLL enabled Sleep mode Deep sleep mode Power-down mode Deep power-down mode IBAT battery supply current Deep power-down mode; RTC running VDD(REG)(3V3) present VDD(REG)(3V3) not present IDD(IO) I/O supply current Deep sleep mode Power-down mode Deep power-down mode [7] [8] [4] 14 100 4.86 370 56 1.3 mA mA A A A [4] [4][5] [4][6] [4][6] [4] - - nA nA nA nA nA [9] [9] [9] - LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 71 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IDD(ADC) Parameter ADC supply current Conditions Deep sleep mode Power-down mode Deep power-down mode II(ADC) ADC input current on pin VREFP Deep sleep mode Power-down mode Deep power-down mode Standard port pins, RESET IIL IIH LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = 4 mA IOL = 4 mA VOH = VDD(3V3)  0.4 V VOL = 0.4 V [15] [11] [11] [11] [10] [10] [10] Min - Typ[1] Max - Unit nA nA nA nA nA nA - 0.5 0.5 10 10 nA nA VI = VDD(3V3); on-chip pull-down resistor disabled VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled pin configured to provide a digital function output active [12][13] [14] IOZ - 0.5 10 nA VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu 0 0 - 5.0 VDD(3V3) - V V V 0.7VDD(3V3) 0.4 VDD(3V3)  0.4 4 4 10 15 0 50 50 0 0.3VDD(3V3) V 0.4 45 50 150 85 0 V V V mA mA mA mA A A A V HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD(3V3) VI = 5 V VI = 0 V VDD(3V3) < VI < 5 V [15] I2C-bus pins (P0[27] and P0[28]) VIH VIL HIGH-level input voltage LOW-level input voltage VDD(3 V3) - - VDD(3 V V3) LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 72 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Vhys VOL ILI USB pins IOZ VBUS VDI VCM Vth(rs)se OFF-state output current bus supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage for low-/full-speed HIGH-level output voltage (driven) for low-/full-speed RL of 1.5 k to 3.6 V (D+)  (D) includes VDI range 0 V < VI < 3.3 V 0.2 0.8 0.8 10 5.25 2.5 2.0 A V V V V Parameter hysteresis voltage LOW-level output voltage input leakage current IOLS = 3 mA VI = VDD(3V3) VI = 5 V [16] Conditions Min - Typ[1] V3) Max Unit V V A A VDD(3 0.4 VOL - - 0.18 V VOH RL of 15 k to GND 2.8 - 3.5 V Ctrans ZDRV transceiver capacitance pin to GND driver output with 33  series resistor; impedance for driver steady state drive which is not high-speed capable input voltage on pin XTAL1 output voltage on pin XTAL2 input voltage on pin RTCX1 output voltage on pin RTCX2 [17] 36 - 20 44.1 pF  Oscillator pins (see Section 14.2) Vi(XTAL1) Vo(XTAL2) Vi(RTCX1) Vo(RTCX2) 0.5 0.5 0.5 0.5 1.8 1.8 1.95 1.95 3.6 3.6 V V V V [1] [2] [3] [4] [5] [6] [7] [8] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. For USB operation 3.0 V  VDD((3V3)  3.6 V. Guaranteed by design. The RTC typically fails when Vi(VBAT) drops below 1.6 V. VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. IRC running at 12 MHz; main oscillator and PLL disabled; PCLK = CCLK/4. BOD disabled. On pin VBAT; IDD(REG)(3V3) = ; VDD(REG)(3V3) = 3.3 V; VBAT = 3.3 V; Tamb = 25 C. On pin VBAT; VBAT = 3.3 V; Tamb = 25 C. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. LPC178X_7X Objective data sheet Rev. 2 — 27 May 2011 73 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller [9] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C. [10] VDDA = 3.3 V; Tamb = 25 C. [11] Vi(VREFP) = 3.3 V; Tamb = 25 C. [12] Including voltage on outputs in 3-state mode. [13] VDD(3V3) supply voltages must be present. [14] 3-state outputs go into 3-state mode in Deep power-down mode. [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] To VSS. [17] Includes external resistors of 33   1 % on D+ and D. 10.1 Power consumption X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VDD(Reg)(3V3) = 3.3 V; BOD disabled. Fig 9. Deep-sleep mode: Regulator supply current IDD(Reg)(3V3) versus temperature LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 74 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VDD(Reg)(3V3) = 3.3 V; BOD disabled. Fig 10. Power-down mode: Regulator supply current IDD(Reg)(3V3) versus temperature X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VBAT = 3.3 V; VDD(Reg)(3V3) floating; RTC not running. Fig 11. Deep power-down mode: Battery supply current IBAT versus temperature LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 75 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz, 48 MHz, and 120 MHz. The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. Table 12. Power consumption for individual analog and digital blocks Tamb = 25 C, VDD(REG)(3V3) = V. PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz Timer0 Timer1 Timer2 Timer3 Timer0 + Timer1 + Timer2 + Timer3 UART0 UART1 UART2 UART3 USART4 UART0 + UART1 + UART2 + UART3 + USART4 PWM0 + PWM1 Motor control PWM I2C0 I2C1 I2C2 I2C0 + I2C1 + I2C2 SSP0 SSP1 DAC ADC (12 MHz clock) CAN1 CAN2 CAN1 + CAN2 DMA QEI GPIO LCD I2S LPC178X_7X All information provided in this document is subject to legal disclaimers. 48 MHz 0.06 0.07 0.07 0.07 0.28 0.19 0.24 0.2 0.23 0.27 1.13 0.31 0.15 0.03 0.03 0.03 0.1 0.1 0.11 0.31 1.61 0.44 0.4 0.59 4.27 0.11 1.72 3.84 0.18 120 MHz 0.15 0.16 0.17 0.16 0.67 0.45 0.56 0.47 0.56 0.66 2.74 0.75 0.36 0.08 0.1 0.08 0.26 0.26 0.27 0.33 1.7 1.08 0.98 1.44 10.27 0.28 4.16 9.25 0.46 0.01 0.02 0.02 0.01 0.07 0.05 0.06 0.05 0.06 0.07 0.29 0.08 0.04 0.01 0.01 0.01 0.02 0.03 0.02 0.3 1.51 0.11 0.1 0.15 PCLK = CCLK 1.1 0.02 0.4 0.99 0.04 © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 76 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 12. Power consumption for individual analog and digital blocks …continued Tamb = 25 C, VDD(REG)(3V3) = V. PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz EMC RTC USB + PLL1 Ethernet 0.82 0.01 0.62 PCENET bit set 0.54 to 1 in the PCONP register 48 MHz 3.17 0.01 0.97 2.08 120 MHz 7.63 0.05 1.67 5.03 LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 77 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 10.3 Electrical pin characteristics 3.6 VOH (V) 3.2 002aaf112 T = 85 °C 25 °C −40 °C 2.8 2.4 2 0 8 16 IOH (mA) 24 Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 15 IOL (mA) 10 T = 85 °C 25 °C −40 °C 002aaf111 5 0 0 0.2 0.4 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 78 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller +10 Ipu (μA) −10 002aaf108 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 VI (V) 5 Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 14. Typical pull-up current Ipu versus input voltage VI 90 Ipd (μA) 70 002aaf109 50 T = 85 °C 25 °C −40 °C 30 10 −10 0 1 2 3 4 VI (V) 5 Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15. Typical pull-down current Ipd versus input voltage VI LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 79 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 11. Dynamic characteristics 11.1 Flash memory Table 13. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Nendu tret ter tprog [1] [2] Parameter endurance retention time erase time programming time Conditions [1] Min 10000 10 20 95 [2] Typ 100 1 Max 105 1.05 Unit cycles years years ms ms 100000 - powered unpowered sector or multiple consecutive sectors 0.95 Number of program/erase cycles. Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Table 14. EEPROM characteristics Tamb = 40 C to +85 C; VDD(REG)(3V3) = 2.7 V to 3.6 V. Symbol fclk Nendu tret Parameter clock frequency endurance retention time powered unpowered Conditions Min 200 100000 10 10 Typ 375 500000 Max 400 Unit kHz cycles years years LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 80 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 11.2 External memory interface Table 15. Dynamic characteristics: Static external memory interface CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Tcy(clk) tCSLAV tCSLOEL tCSLBLSL tOELOEH Parameter[1] clock cycle time CS LOW to address valid time CS LOW to OE LOW time CS LOW to BLS LOW time OE LOW to OE HIGH time RD1 RD2 RD3; PB = 1 RD4 Conditions[1] Min 12.5 1.4 1.3 + Tcy(clk)  WAITOEN Typ 2.0 2.0 + Tcy(clk)  WAITOEN Max 2.5 2.5 + Tcy(clk)  WAITOEN Unit ns ns ns ns Read cycle parameters[2] (WAITRD  (WAITRD  WAITOEN + 1)  WAITOEN + 1)  Tcy(clk)  1.4 Tcy(clk)  1.0 [3] (WAITRD  ns WAITOEN + 1)  Tcy(clk)  1.6 (WAITRD  WAITOEN +1)  Tcy(clk)  15.5 0.1 3 2.5 2.9 2.5 + Tcy(clk)  (1 + WAITWEN) 3.0 ns tam memory access time RD5 (WAITRD  WAITOEN +1)  Tcy(clk)  7.2 0.1 1.5 (WAITRD  WAITOEN +1)  Tcy(clk)  10.5 0.1 2.3 2.0 2.3 2.0 + Tcy(clk)  (1 + WAITWEN) 2.3 th(D) tCSHBLSH tCSHOEH tOEHANV tdeact Write cycle tCSLAV tCSLDV tCSLWEL tCSLBLSL tWELWEH data input hold time CS HIGH to OE HIGH time OE HIGH to address invalid time deactivation time parameters[2] CS LOW to address valid time CS LOW to data valid time CS LOW to WE LOW time CS LOW to BLS LOW time WE LOW to WE HIGH time RD6 [4] ns ns ns ns ns ns ns ns ns CS HIGH to BLS HIGH time PB = 1 RD7 WR1 WR2 WR3; PB =1 WR4; PB = 1 WR5; PB =1 1.4 1.5 1.4 + Tcy(clk)  (1 + WAITWEN) 3.0 (WAITWR  (WAITWR  ns (WAITWR  WAITWEN + 1)  WAITWEN + 1)  WAITWEN + 1)  Tcy(clk)  1.5 Tcy(clk)  1.7 Tcy(clk)  1.0 (WAITWR  (WAITWR  ns (WAITWR  WAITWEN + 3)  WAITWEN + 3)  WAITWEN + 3)  Tcy(clk)  2.0 Tcy(clk)  2.7 Tcy(clk)  1.4 1.2 + Tcy(clk) [5] tBLSLBLSH BLS LOW to BLS HIGH time PB = 1 tWEHDNV tWEHEOW tBLSHDNV tWEHANV tdeact tCSLBLSL LPC178X_7X WE HIGH to data invalid time WE HIGH to end of write time BLS HIGH to data invalid time WR6; PB =1 WR7; PB = 1 PB = 1 1.8 + Tcy(clk) + Tcy(clk) 2.0 1.5 + Tcy(clk) 2.1 + Tcy(clk) + Tcy(clk) 2.7 1.7 + Tcy(clk) ns ns ns ns ns ns + Tcy(clk) 1.4 1 + Tcy(clk) WE HIGH to address invalid PB = 1 time deactivation time CS LOW to BLS LOW WR8; PB = 0; PB = 1 WR9; PB = 0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 81 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 15. Dynamic characteristics: Static external memory interface …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol tBLSLBLSH Parameter[1] Conditions[1] Min Typ Max Unit BLS LOW to BLS HIGH time WR10; PB = 0 (WAITWR  (WAITWR  ns (WAITWR  WAITWEN + 1)  WAITWEN + 1)  WAITWEN + 1)  Tcy(clk) + Tcy(clk) + Tcy(clk) + [5] tBLSHEOW tBLSHDNV BLS HIGH to end of write time BLS HIGH to data invalid time WR11; PB = 0 WR12; PB = 0 ns ns [1] [2] [3] [4] [5] Parameters are shown as RDn or WDn in Figure 16 as indicated in the Conditions column. Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges. Latest of address valid, CS LOW, OE LOW, BS LOW (PB = 1). After End Of Read (EOR): Earliest of CS HIGH, OE HIGH, BLSx HIGH (PB = 1), address invalid. End Of Write (EOW): Earliest of address invalid, CS HIGH, BLSx HIGH (PB = 1). A RD1 CS WR8 RD2 OE RD4 RD7 WR9 BLSx WE RD5 RD5 RD5 D EOR EOW 002aag214 WR1 WR10 WR11 RD6 WR2 WR12 Fig 16. External static memory read/write access (PB = 0) LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 82 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller A RD1 CS RD2 OE RD3 BLSx RD7 WR3 WE RD5 RD5 RD5 RD5 D EOR EOW 002aag215 WR1 WR8 RD4 RD7 WR4 WR8 WR5 WR7 RD6 WR2 WR6 Fig 17. External static memory read/write access (PB =1) A CS OE BLSx WE RD5 RD5 RD5 RD5 D 002aag216 Fig 18. External static memory burst read cycle Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. All programmable delays EMCDLYCTL are bypassed. Values guaranteed by design. Symbol td(SV) th(S) td(RASV) th(RAS) td(CASV) th(CAS) td(WV) LPC178X_7X Parameter chip select valid delay time chip select hold time row address strobe valid delay time row address strobe hold time column address strobe valid delay time column address strobe hold time write valid delay time Conditions Min 2.9 1.2 2.8 1.3 2.8 1.3 3.6 Typ 4.2 1.8 4.2 1.9 4.2 1.9 5.2 Max 6.2 3.3 6.2 3.5 6.2 3.5 7.7 Unit ns ns ns ns ns ns ns Common to read and write cycles All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 83 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. All programmable delays EMCDLYCTL are bypassed. Values guaranteed by design. Symbol th(W) td(GV) th(G) td(AV) th(A) tsu(D) th(D) td(QV) th(Q) [1] [2] Parameter write hold time output enable valid delay time output enable hold time address valid delay time address hold time data input set-up time data input hold time data output valid delay time data output hold time Conditions Min 1.6 3.4 1.1 5.3 3.7 3.9 0.2 Typ 2.4 5.0 1.7 3.8 4.3 5.8 0.6 Max 4.2 7.4 3.0 1.5 5.2 8.7 1.6 Unit ns ns ns ns ns ns ns ns ns Read cycle parameters Write cycle parameters The data input set-up time has to be selected with the following margin: tsu(D) + delay time of feedback clock  sdram access time  board delay time  0. The data input hold time has to be selected with the following margin: th(D) + sdram access time  board delay time  delay time of feedback clock  0. Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. All programmable delays EMCDLYCTL are bypassed. Values guaranteed by design. Symbol td(SV) th(S) td(RASV) th(RAS) td(CASV) th(CAS) td(WV) th(W) td(GV) th(G) td(AV) th(A) tsu(D) th(D) td(QV) th(Q) Parameter chip select valid delay time chip select hold time row address strobe valid delay time row address strobe hold time column address strobe valid delay time column address strobe hold time write valid delay time write hold time output enable valid delay time output enable hold time address valid delay time address hold time data input set-up time data input hold time data output valid delay time data output hold time Conditions Min 2.7 1.0 2.7 1.1 2.7 1.2 3.2 1.6 3.3 1.0 5.3 3.7 3.3 0.2 Typ 4.1 1.6 4.1 1.7 4.1 1.8 4.8 2.3 4.9 1.6 3.8 4.3 4.9 0.5 Max 6.0 3.1 6.0 3.3 6.1 3.3 7.1 4.2 7.3 2.8 1.5 5.2 7.3 1.6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Common to read and write cycles Read cycle parameters Write cycle parameters LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 84 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller [1] [2] The data input set-up time has to be selected with the following margin: tsu(D) + delay time of feedback clock  sdram access time  board delay time  0. The data input hold time has to be selected with the following margin: th(D) + sdram access time - board delay time - delay time of feedback clock  0. CLKOUT td(CS) th(CS) DYCS td(RAS) RAS th(RAS) td(CAS) CAS WE th(CAS) td(DQM) DQM td(A) A tsu(D) th(D) D th(A) th(DQM) 002aag205 Fig 19. Dynamic external memory interface signal timing (read access) Table 18. Dynamic characteristics: Dynamic external memory interface programmable clock delays CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V.Values guaranteed by design. Symbol Parameter Conditions td delay time Programmable delay block 0 (CMDDLY or CLKOUTnDLY bit 0 = 1) Programmable delay block 1 (CMDDLY or CLKOUTnDLY bit 1 = 1) Programmable delay block 2 (CMDDLY or CLKOUTnDLY bit 2 = 1) Programmable delay block 3 (CMDDLY or CLKOUTnDLY bit 3 = 1) Programmable delay block 4 (CMDDLY or CLKOUTnDLY bit 4 = 1) [1] [1] Min 0.06 0.21 0.54 1.17 2.43 Typ 0.09 0.32 0.82 1.76 3.66 Max 0.15 0.53 1.34 2.87 5.97 Unit ns ns ns ns ns [1] [1] [1] [1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user manual for details. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 85 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 11.3 External clock Table 19. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL [1] [2] Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time Conditions Min 1 40 Tcy(clk)  0.4 Tcy(clk)  0.4 - Typ[2] - Max 25 1000 5 5 Unit MHz ns ns ns ns ns Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCLCX Tcy(clk) tCHCX tCLCH 002aaa907 Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 11.4 Internal oscillators Table 20. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD(3V3)  3.6 V.[1] Symbol fosc(RC) fi(RTC) [1] [2] Parameter internal RC oscillator frequency RTC input frequency Conditions - Min 11.88 - Typ[2] 12 Max 12.12 Unit MHz kHz 32.768 - Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 86 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD(3V3) 3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 21. Internal RC oscillator frequency versus temperature 11.5 I/O pins Table 21. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol tr tf [1] Parameter rise time fall time Conditions pin configured as output pin configured as output Min 3.0 2.5 Typ - Max 5.0 5.0 Unit ns ns Applies to standard port pins and RESET pin. 11.6 SSP interface Table 22. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol SSP master Tcy(clk) clock cycle time full-duplex mode when only transmitting tDS tDH tv(Q) th(Q) SSP slave Tcy(PCLK) LPC178X_7X Parameter Conditions [1] Min 30 30 [2] [2] [2] [2] Typ 25 25 10.5 1 4.0 0.2 Max 6.3 - Unit ns ns ns ns ns ns ns data set-up time data hold time in SPI mode in SPI mode 14.8 2 2.4 10 data output valid time in SPI mode data output hold time in SPI mode PCLK cycle time All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 87 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 22. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Tcy(clk) tDS tDH tv(Q) th(Q) [1] Parameter clock cycle time data set-up time data hold time Conditions [3] Min 120 14.8 2 2.4 [3][4] [3][4] [3][4] [3][4] Typ 10.5 1 4.0 0.2 Max 6.3 - Unit ns ns ns ns ns in SPI mode in SPI mode data output valid time in SPI mode data output hold time in SPI mode Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. 2The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). Tamb = 40 C to 85 C; VDD(REG)(3V3) = 3.0 V to 3.6 V. Tcy(clk) = 12  Tcy(PCLK). Tamb = 25 C; VDD = 3.3 V. [2] [3] [4] Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID CPHA = 1 th(Q) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID th(Q) CPHA = 0 002aae829 Fig 22. SSP master timing in SPI mode LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 88 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tv(Q) MISO DATA VALID DATA VALID tDH DATA VALID th(Q) CPHA = 1 tDS MOSI DATA VALID tv(Q) MISO DATA VALID tDH DATA VALID th(Q) DATA VALID CPHA = 0 002aae830 Fig 23. SSP slave timing in SPI mode 11.7 I2C-bus Table 23. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol fSCL Parameter SCL clock frequency Conditions Standard-mode Fast-mode Fast-mode Plus tf fall time [4][5][6][7] Min 0 0 0 - Max 100 400 1 300 Unit kHz kHz MHz ns of both SDA and SCL signals Standard-mode Fast-mode Fast-mode Plus 20 + 0.1  Cb 4.7 1.3 0.5 4.0 0.6 0.26 300 120 - ns ns s s s s s s tLOW LOW period of the SCL clock Standard-mode Fast-mode Fast-mode Plus Standard-mode Fast-mode Fast-mode Plus tHIGH HIGH period of the SCL clock LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 89 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 23. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol tHD;DAT Parameter data hold time [3][4][8] Conditions Standard-mode Fast-mode Fast-mode Plus Min 0 0 0 250 100 50 Max - Unit s s s ns ns ns tSU;DAT data set-up time [9][10] Standard-mode Fast-mode Fast-mode Plus [1] [2] [3] [4] [5] [6] See the I2C-bus specification UM10204 for details. Parameters are valid over operating temperature range unless otherwise specified. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [7] [8] [9] [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. tf SDA 70 % 30 % tf 70 % 30 % 70 % 30 % tHD;DAT tSU;DAT tVD;DAT tHIGH SCL 70 % 30 % 70 % 30 % tLOW 70 % 30 % S 1 / fSCL 002aaf425 Fig 24. I2C-bus pins clock timing LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 90 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 11.8 I2S-bus interface Table 24. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol tr tf tWH tWL Parameter rise time fall time pulse width HIGH pulse width LOW on pins I2S_TX_SCK and I2S_RX_SCK on pins I2S_TX_SCK and I2S_RX_SCK Conditions [1] [1] [1] Min 25 - Max 6.7 8.0 25 Unit ns ns ns common to input and output [1] output tv(Q) input tsu(D) th(D) [1] data output valid time data input set-up time data input hold time on pin I2S_TX_SDA; on pin I2S_RX_SDA on pin I2S_RX_SDA [1] 5 2 6 - ns ns ns [1] [1] CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification. Tcy(clk) tf tr I2S_TX_SCK tWH I2S_TX_SDA tWL tv(Q) I2S_TX_WS tv(Q) 002aag202 Fig 25. I2S-bus timing (transmit) LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 91 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tf tr I2S_RX_SCK tWH I2S_RX_SDA tWL tsu(D) th(D) I2S_RX_WS tsu(D) tsu(D) 002aag203 Fig 26. I2S-bus timing (receive) 11.9 USB Table 25. Dynamic characteristics of USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3); 3.0 V  VDD(3V3)  3.6 V. Symbol tr tf tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise and fall time matching output signal crossover voltage source SE0 interval of EOP source jitter for differential transition to SE0 transition receiver jitter to next transition receiver jitter for paired transitions EOP width at receiver 10 % to 90 % must reject as EOP; see Figure 27 must accept as EOP; see Figure 27 [1] Conditions 10 % to 90 % 10 % to 90 % tr / tf Min 8.5 7.7 1.3 Typ - Max 13.8 13.7 109 2.0 175 +5 +18.5 +9 - Unit ns ns % V ns ns ns ns ns see Figure 27 see Figure 27 160 2 18.5 9 40 tEOPR2 EOP width at receiver [1] 82 - - ns [1] Characterized but not implemented as production test. Guaranteed by design. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 92 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller tPERIOD crossover point differential data lines crossover point extended source EOP width: tFEOPT differential data to SE0/EOP skew n × tPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 27. Differential data-to-EOP transition skew and EOP width 11.10 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. Table 26. Dynamic characteristics: Ethernet Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter RMII mode fclk dclk tsu clock frequency clock duty cycle set-up time for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV for ENET_TX_CLK for ENET_TXDn, ENET_TX_EN, ENET_TX_ER for ENET_TXDn, ENET_TX_EN, ENET_TX_ER for ENET_RX_CLK for ENET_RXDn, ENET_RX_ER, ENET_RX_DV for ENET_RXDn, ENET_RX_ER, ENET_RX_DV for ENET_RX_CLK [1] [1] [1][2] Conditions Min 50 4 Max 50 50 - Unit MHz % ns th hold time [1][2] 2 - ns MII mode fclk dclk tsu th fclk dclk tsu th [1] [2] clock frequency clock duty cycle set-up time hold time clock frequency clock duty cycle set-up time hold time [1] [1] [1][2] 50 4 2 50 4 2 25 50 25 50 - MHz % ns ns MHz % ns ns [1][2] [1] [1] [1][2] [1][2] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input capacitance of the receiving device. Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or output level. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 93 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller ENET_RX_CLK ENET_TX_CLK ENET_RXD[n] ENET_RX_DV ENET_RX_ER ENET_TXD[n] ENET_TX_EN ENET_TX_ER tsu th 002aag210 Fig 28. Ethernet timing 11.11 LCD Remark: The LCD controller is available on parts LPC1788/87/86/85. Table 27. Dynamic characteristics: LCD Values listed describe design constraints. Symbol Tcy(clk) Parameter clock cycle time Conditions for LCD clock on pin LCD_DCLK Min 25 Typ Max Unit ns X X (X) X 001aac984 X X X X X X X (X) X X X Fig 29. LCD timing 11.12 SD/MMC Remark: The SD/MMC card interface is available on parts LPC1788/87/86 and parts LPC1778/77/76. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 94 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 28. Dynamic characteristics: SD/MMC Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol fclk tsu(D) th(D) td(QV) th(Q) Parameter clock frequency data input set-up time Conditions on pin SD_CLK; data transfer mode on pin SD_CLK; identification mode on pins SD_CMD, SD_DAT[3:0] as inputs 6 6 3.5 Min Max 25 25 23 Unit MHz MHz ns ns ns ns data input hold time on pins SD_CMD, SD_DAT[3:0] as inputs data output valid delay time data output hold time on pins SD_CMD, SD_DAT[3:0] as outputs on pins SD_CMD, SD_DAT[3:0] as outputs Tcy(clk) SDIO_SCLK td(QV) SDIO_CMD (O) SDIO_D[3:0](O) th(Q) tsu(D) SDO_CMD (I) SDIO_D[3:0] (I) th(D) 002aag204 Fig 30. SD/MMC timing 12. ADC electrical characteristics Table 29. ADC characteristics VDDA = 2.7 V to 3.6 V; Tamb = 25 C. Symbol VIA Cia Rvsi Parameter analog input voltage analog input capacitance voltage source interface resistance differential linearity error integral non-linearity offset error gain error absolute error ADC clock frequency All information provided in this document is subject to legal disclaimers. Conditions Min 0 [8] Typ - Max VDDA Unit V pF k - 12-bit resolution; 400 kSamples/sec ED EL(adj) EO EG ET fclk(ADC) LPC178X_7X [1][2][3] - 1 6 4.5 3 - 12.4 LSB LSB LSB LSB LSB MHz 95 of 117 [1][4] [1][5] [1][6] [1][7] © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 29. ADC characteristics …continued VDDA = 2.7 V to 3.6 V; Tamb = 25 C. Symbol fc(ADC) Parameter ADC conversion frequency differential linearity error integral non-linearity offset error gain error absolute error ADC clock frequency ADC conversion frequency [1][2][3] Conditions Min - Typ - Max 400 Unit kHz 8-bit resolution[9]; 1.16 MSamples/sec ED EL(adj) EO EG ET fclk(ADC) fc(ADC) 1 1 1 1 36 1.16 LSB LSB LSB LSB LSB MHz MHz [1][4] [1][5] [1][6] [1][7] [1] [2] [3] [4] [5] [6] [7] [8] [9] Conditions: VSSA = 0 V, VDDA = 3.3 V. The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 31. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 31. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 31. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 31. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 31. See Figure 32. 8-bit resolution is achieved by ignoring the lower four bits of the ADC conversion result. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 96 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller offset error EO 4095 gain error EG 4094 4093 4092 4091 4090 (2) 7 code out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 4090 4091 4092 4093 4094 4095 4096 0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 31. 12-bit ADC characteristics LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 97 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller LPC17xx C3 ADC COMPARATOR BLOCK 2.2 pF Ri1 2 kΩ - 5.2 kΩ Ri2 100 Ω - 600 Ω AD0[n] C1 750 fF C2 65 fF Cia Rvsi VSS VEXT 002aaf197 The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are process-dependent. Fig 32. ADC interface to pins ADC0_IN[n] Table 30. Ri1 Ri2 C1 C2 C3 ADC interface components Range 2 k to 5.2 k 100  to 600  750 fF 65 fF 2.2 pF Description Switch-on resistance for channel selection switch. Varies with temperature, input voltage, and process. Switch-on resistance for the comparator input switch. Varies with temperature, input voltage, and process. Parasitic capacitance from the ADC block level. Parasitic capacitance from the ADC block level. Sampling capacitor. Component 13. DAC electrical characteristics Table 31. DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol ED EL(adj) EO EG CL RL Parameter differential linearity error integral non-linearity offset error gain error load capacitance load resistance Conditions Min 1 Typ 1 1.5 0.6 0.6 200 Max Unit LSB LSB % % pF k LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 98 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 14. Application information 14.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1788/87/86/85 and LPC1778/77/76 and as device-only controller on parts LPC1774. VDD(3V3) USB_UP_LED USB_CONNECT LPC17xx SoftConnect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB_D− RS = 33 Ω VSS 002aad939 USB-B connector Fig 33. USB interface on a self-powered device VDD(3V3) R2 LPC17xx USB_UP_LED VBUS USB_D+ RS = 33 Ω USB_D− RS = 33 Ω VSS R1 1.5 kΩ USB-B connector 002aad940 Fig 34. USB interface on a bus-powered device LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 99 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller VDD RSTOUT RESET_N ADR/PSW VDD OE_N/INT_N SPEED SUSPEND VBUS ID DP DM 33 Ω 33 Ω Mini-AB connector ISP1302 VSS LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED SCL SDA INT_N 002aad941 VDD Fig 35. USB OTG port configuration VDD USB_UP_LED VSS USB_D+ USB_D− 33 Ω 33 Ω 15 kΩ 15 kΩ D+ D− LPC17xx USB_PWRD USB_OVRCR USB_PPWR 5V USB-A connector VDD VBUS ENA IN FLAGA LM3526-L OUTA 002aad942 Fig 36. USB host port configuration LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 100 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller VDD USB_UP_LED VDD USB_CONNECT LPC17xx VSS USB_D+ USB_D− VBUS 33 Ω 33 Ω D+ D− VBUS USB-B connector 002aad943 Fig 37. USB device port configuration 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. LPC1xxx XTAL1 Ci 100 pF Cg 002aae835 Fig 38. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 38), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 39 and in Table 32 and Table 33. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 39 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 101 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller LPC1xxx L XTALIN XTALOUT = XTAL CL CP RS CX1 CX2 002aaf424 Fig 39. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 32. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): low frequency mode Crystal load capacitance CL 10 pF 20 pF 30 pF 5 MHz - 10 MHz 10 pF 20 pF 30 pF 10 MHz - 15 MHz 15 MHz - 20 MHz Table 33. 10 pF 20 pF 10 pF Maximum crystal series resistance RS < 300  < 300  < 300  < 300  < 200  < 100  < 160  < 60  < 80  External load capacitors CX1/CX2 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF Fundamental oscillation frequency FOSC 1 MHz - 5 MHz Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Crystal load capacitance CL 10 pF 20 pF 10 pF 20 pF Maximum crystal series resistance RS < 180  < 100  < 160  < 80  External load capacitors CX1, CX2 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF 39 pF, 39 pF Fundamental oscillation frequency FOSC 15 MHz - 20 MHz 20 MHz - 25 MHz 14.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 102 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 14.4 Standard I/O pin configuration Figure 40 shows the possible pin modes for standard I/O pins with analog input function: • • • • • Digital output driver: Open-drain mode enabled/disabled Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. VDD open-drain enable pin configured as digital output driver output enable data output strong pull-down strong pull-up VDD ESD PIN ESD VSS VDD weak pull-up pull-up enable repeater mode enable pull-down enable weak pull-down pin configured as digital input data input select analog input pin configured as analog input analog input 002aaf272 Fig 40. Standard I/O pin configuration with analog input LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 103 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 14.5 Reset pin configuration VDD VDD VDD Rpu ESD reset 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 41. Reset pin configuration LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 104 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 156 157 105 104 ZE e E HE A A2 A1 (A 3) θ Lp L detail X wM bp pin 1 index 208 53 1 52 e bp D HD wM ZD B vM A vM B 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.12 w 0.08 y 0.08 ZD 1.43 1.08 ZE 1.43 1.08 θ 7 o 0 o 30.15 30.15 29.85 29.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT459-1 REFERENCES IEC 136E30 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-06 03-02-20 Fig 42. LQFP208 package LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 105 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm SOT950-1 D B A ball A1 index area E A A2 A1 detail X e1 e b ∅v ∅w M M CAB C C y1 C y U T R P N M L K J H G F E D C B A e e2 ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.4 0.3 A2 0.8 0.6 b 0.5 0.4 D 15.1 14.9 E 15.1 14.9 e 0.8 e1 12.8 e2 12.8 v 0.15 w 0.08 y 0.12 y1 0.1 OUTLINE VERSION SOT950-1 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 06-06-01 06-06-14 Fig 43. TFBGA208 package LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 106 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller TFBGA180: thin fine-pitch ball grid array package; 180 balls; body 12 x 12 x 0.8 mm SOT570-2 D B A ball A1 index area A E A2 A1 detail X C e1 e P N M L K J H G F E D C B A 1/2 e b ∅v M C A B ∅wM C y1 C y e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.2 A1 0.35 0.25 A2 0.85 0.75 b 0.5 0.4 D 12.2 11.8 E 12.2 11.8 e 0.8 e1 10.4 e2 10.4 v 0.15 w 0.08 y 0.12 y1 0.1 OUTLINE VERSION SOT570-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-03-03 06-03-14 Fig 44. TFBGA180 package LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 107 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 108 109 73 72 ZE e E HE A A2 A1 (A 3) θ Lp L detail X wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 θ 7 o 0 o 22.15 22.15 21.85 21.85 ISSUE DATE 00-03-14 03-02-20 Fig 45. LQFP144 package LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 108 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 16. Soldering Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 P1 (0.125) Hy Gy By Ay C D2 (8×) Bx Ax Generic footprint pattern D1 Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By C 1.500 D1 0.280 D2 0.400 Gx Gy Hx Hy sot459-1_fr 0.560 31.300 31.300 28.300 28.300 28.500 28.500 31.550 31.550 Fig 46. Reflow soldering of the LQFP208 package LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 109 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570-2 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL occupied area solder resist SP SR detail X DIMENSIONS in mm P 0.80 SL 0.400 SP 0.400 SR 0.550 Hx Hy sot570-2_fr 12.575 12.575 Fig 47. Reflow soldering of the TFBGA180 package LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 110 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 P1 (0.125) Hy Gy By Ay C D2 (8×) Bx Ax Generic footprint pattern D1 Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By C 1.500 D1 0.280 D2 0.400 Gx Gy Hx Hy sot486-1_fr 0.560 23.300 23.300 20.300 20.300 20.500 20.500 23.550 23.550 Fig 48. Reflow soldering of the LQFP144 package LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 111 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 17. Abbreviations Table 34. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO GPS HVAC IRC IrDA JTAG MAC MIIM OHCI OTG PHY PLC PLL PWM RIT RMII SE0 SPI SSI SSP TCM TTL UART USB Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access Digital Signal Processing End Of Packet Embedded Trace Macrocell General Purpose Input/Output Global Positioning System Heating, Venting, and Air Conditioning Internal RC Infrared Data Association Joint Test Action Group Media Access Control Media Independent Interface Management Open Host Controller Interface On-The-Go Physical Layer Programmable Logic controller Phase-Locked Loop Pulse Width Modulator Repetitive Interrupt Timer Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Tightly Coupled Memory Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 112 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 18. Revision history Table 35. Revision history Release date 20110527 Data sheet status Objective data sheet Change notice Supersedes Document ID LPC178X_7X v.2 Modifications: • • • • • • • • • • Symbol names in Table 3 to Table 5 abbreviated. Reserved functions added in Table 3. Added function LCD_VD[5] to pin P0[10]. Added function LCD_VD[10] to pin P0[11]. Added function LCD_VD[13] to pin P0[19]. Added function LCD_VD[14] to pin P0[20]. Added function U4_SCLK to pin P0[21]. Added function SSP2_MOSI to pin P5[0]. Added function SSP2_MISO to pin P5[1]. Added EMC dynamic characteristics. Objective data sheet - LPC178X_7X v.1 20110524 LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 113 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2011. All rights reserved. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC178X_7X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 2 — 27 May 2011 114 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 115 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 40 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 40 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 41 7.3 On-chip flash program memory . . . . . . . . . . . 41 7.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 41 7.6 Memory Protection Unit (MPU). . . . . . . . . . . . 41 7.7 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.8 Nested Vectored Interrupt Controller (NVIC) . 44 7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.8.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 44 7.9 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 44 7.10 External memory controller. . . . . . . . . . . . . . . 44 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.11 General purpose DMA controller . . . . . . . . . . 46 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.12 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.13 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 48 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.14 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.15 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.15.1 USB device controller . . . . . . . . . . . . . . . . . . . 50 7.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.15.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 50 7.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.15.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 51 7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.16 SD/MMC card interface . . . . . . . . . . . . . . . . . 51 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.17 Fast general purpose parallel I/O . . . . . . . . . . 51 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.18 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.19 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.20 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.21 7.21.1 7.22 7.22.1 7.23 7.23.1 7.24 7.24.1 7.25 7.25.1 7.26 7.26.1 7.27 7.28 7.28.1 7.29 7.30 7.30.1 7.31 7.31.1 7.32 7.32.1 7.33 7.33.1 7.33.1.1 7.33.1.2 7.33.1.3 7.33.1.4 7.33.2 7.33.3 7.33.4 7.33.4.1 7.33.4.2 7.33.4.3 7.33.4.4 7.33.4.5 7.33.5 7.33.6 7.34 7.34.1 7.34.2 7.34.3 7.34.4 7.34.5 7.34.6 7.34.7 SSP serial I/O controller. . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus serial I/O controllers . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S-bus serial I/O controllers . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN controller and acceptance filters . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulator (PWM). . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motor control PWM . . . . . . . . . . . . . . . . . . . . Quadrature Encoder Interface (QEI) . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARM Cortex-M3 system tick timer . . . . . . . . . Windowed WatchDog Timer (WWDT) . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTC and backup registers . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event monitor/recorder . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking and power control . . . . . . . . . . . . . . Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . Internal RC oscillator . . . . . . . . . . . . . . . . . . . Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . Watchdog oscillator . . . . . . . . . . . . . . . . . . . . Main PLL (PLL0) and Alternate PLL (Alt PLL, PLL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . Power control . . . . . . . . . . . . . . . . . . . . . . . . . Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . Power-down mode . . . . . . . . . . . . . . . . . . . . . Deep power-down mode . . . . . . . . . . . . . . . . Wake-up Interrupt Controller (WIC) . . . . . . . . Peripheral power control . . . . . . . . . . . . . . . . Power domains . . . . . . . . . . . . . . . . . . . . . . . System control . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brownout detection . . . . . . . . . . . . . . . . . . . . Code security (Code Read Protection - CRP) APB interface . . . . . . . . . . . . . . . . . . . . . . . . . AHB multilayer matrix . . . . . . . . . . . . . . . . . . External interrupt inputs . . . . . . . . . . . . . . . . . Memory mapping control . . . . . . . . . . . . . . . . 53 54 54 54 55 55 55 55 56 56 56 57 57 58 58 58 59 59 59 59 60 60 60 60 61 61 62 62 62 63 63 63 64 64 65 65 65 65 66 66 67 67 68 68 68 68 continued >> LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2 — 27 May 2011 116 of 117 NXP Semiconductors LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 7.35 8 9 9.1 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Emulation and debugging . . . . . . . . . . . . . . . . 68 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 69 Thermal characteristics . . . . . . . . . . . . . . . . . 70 Thermal characteristics. . . . . . . . . . . . . . . . . . 70 Static characteristics. . . . . . . . . . . . . . . . . . . . 71 Power consumption . . . . . . . . . . . . . . . . . . . . 74 Peripheral power consumption . . . . . . . . . . . . 76 Electrical pin characteristics . . . . . . . . . . . . . . 78 Dynamic characteristics . . . . . . . . . . . . . . . . . 80 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 80 External memory interface . . . . . . . . . . . . . . . 81 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 86 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 86 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 87 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . . 91 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ADC electrical characteristics . . . . . . . . . . . . 95 DAC electrical characteristics . . . . . . . . . . . . 98 Application information. . . . . . . . . . . . . . . . . . 99 Suggested USB interface solutions . . . . . . . . 99 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Standard I/O pin configuration . . . . . . . . . . . 103 Reset pin configuration . . . . . . . . . . . . . . . . . 104 Package outline . . . . . . . . . . . . . . . . . . . . . . . 105 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 112 Revision history . . . . . . . . . . . . . . . . . . . . . . . 113 Legal information. . . . . . . . . . . . . . . . . . . . . . 114 Data sheet status . . . . . . . . . . . . . . . . . . . . . 114 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 115 Contact information. . . . . . . . . . . . . . . . . . . . 115 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 May 2011 Document identifier: LPC178X_7X