LPC1800

NXP 150 MHz, 32-bit Cortex-M3™ microcontrollers LPC1800 Fastest Cortex-M3 MCU, Largest SRAM, High Speed USB The LPC1800 series of low power, high-performance Cortex-M3 MCUs features frequencies up to 150 MHz and flexible Dual-Bank Flash for the highest reliability in-application re-programming. Key features 4 150 MHz, 32-bit ARM Cortex-M3 4 Up to 1 MB dual-bank Flash 4 Up to 200 KB SRAM 4 Up to 4 KB EEPROM 4 Memory Protection Unit (MPU) 4 Two high-speed USB 2.0 interfaces, on-chip high-speed PHY 4 10/100T Ethernet MAC with MII and RMII interfaces 4 LCD controller with 1024 x 768 pixel display resolution 4 Innovative Quad SPI Flash Interface (SPIFI) 4 State Configurable Timer (SCT) Subsystem 4 Two CAN 2.0B 4 AES Decryption with 128-bit secure OTP key storage 4 Up to 164 GPIO 4 Pin-compatible with the LPC4300 series Additional features 4 8-channel GPDMA controller 4 Two 8-channel, 10-bit ADCs and one 10-bit DAC (400 K samples per second) 4 Motor Control PWM and Quadrature Encoder Interface 4 Four UARTs, smart card interface 4 Two Fast-mode I2C, two I2S, two SSP/SPI 4 Temperature range: –40 to +85 ºC Lower power and high performance The LPC1800 - designed using NXP’s ultra low-leakage 90 nm process technology - is optimized for low power operation at very low frequencies all the way through to 150 MHz maximum performance from either Flash or RAM. This performance provides maximum connectivity and bandwidth options for a wide range of demanding applications including power conversion, lighting, motor control and audio applications. Large internal memory The LPC1800 offers the industry’s largest on-chip SRAM for a Cortex-M3 with up to 200 KB provided in multiple banks. A flexible dual-bank Flash architecture offers the highest reliability in-application re-programming, and allows for non-stop Flash operation. Extensive peripheral set The LPC1800 also features two new innovative peripherals: a flexible quad-SPI interface and a State Configurable Timer subsystem. The LPC1800 is the first microcontroller to provide a seamless high-speed interface that will connect with virtually all SPI and quad-SPI manufacturers. The LPC1800’s State Configurable Timer Subsystem comprises of a timer array with a state machine enabling complex functionality including event controlled PWM waveform generation, ADC synchronization and dead time control. This timer subsystem gives embedded designers increased flexibility to create user-defined wave-forms and control signals. Additional peripherals available on the LPC1800 include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware enabled TCP/IP checksum calculation, a high-resolution color LCD controller, and AES decryption including two 128-bit secure OTP memories for key storage. Versions with AES encryption are available on request. For more information, please visit www.nxp.com/microcontrollers LPC1800 block diagram LPC18xx MPU GPDMA Brownout Detector Power-on Reset Watchdog Timer SYSTEM Audio PLL Up to 1 MB Dual Bank Flash NVIC ARM CORTEX-M3 Up to 150 MHz USB PLL SRAM WIC Debug Trace CORE CPU PLL Up to 200 KB IRC ROM / OTP ROM MEMORY Bus System 2 x CAN 2.0B SPI Flash Interface 4 x UART Motor Ctrl PWM State Config Timer CONFIGURABLE INTERFACES 2 x HS USB 2.0 External Mem Ctrl 2 x SSP/SPI 4 x 32-bit Timers OTP Key Storage AES Decryption SECURITY Ethernet MAC SDIO 2 x I 2C RTC LCD Controller Quad Enc Interface INTERFACES 2 x I2S Alarm Timer TIMERS 2 x 8 Ch 10-bit ADC ANALOG 10-bit DAC Selection guide Type Memory FLASH RAM LCD Ethernet USB SPI Flash Interface State Config Timer Subsys • • • • • • • • • • • • • • • • ADC I/O pins Ext bus interface Temp. range Package options LPC1810 LPC1812 LPC1813 LPC1815 LPC1817 LPC1820 LPC1822 LPC1823 LPC1825 LPC1827 LPC1830 LPC1833 LPC1837 LPC1850 LPC1853 LPC1857 512 (2x256) 1024 (2x512) 512 (2x256) 1024 (2x512) 512 (1x512) 512 (2x256) 768 (2x384) 1024 (2x512) 512 (1x512) 512 (2x256) 768 (2x384) 1024 (2x512) 136 104 104 136 136 168 104 104 136 136 200 136 136 200 136 136 • • • • • • • • • 1 1 1 1 1 2 2 2 2 2 2 • • • • • • • • • • • • • • • • 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 4-6ch 10b 2x 8ch 10b 2x 8ch 10b 2x 8ch 10b 2x 8ch 10b 2x 8ch 10b 2x 8ch 10b 50-64 50-64 50-64 50-64 50-64 50-64 50-64 50-64 50-64 50-64 80 80 80 80 80 80 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 16-32 16-32 16-32 16-32 16-32 16-32 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100, LQFP100 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100 -40 to +85 °C LQFP144, TBGA100, LQFP100 -40 to +85 °C BGA256, BGA180, BGA100, LQFP144 -40 to +85 °C BGA256, BGA180, BGA100, LQFP144 -40 to +85 °C BGA256, BGA180, BGA100, LQFP144 -40 to +85 °C LQFP208, BGA256, BGA180 -40 to +85 °C LQFP208, BGA256, BGA180 -40 to +85 °C LQFP208, BGA256, BGA180 www.nxp.com © 2011 NXP Semiconductors N.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: June 2011 Document order number: 9397 750 17140 Printed in the Netherlands