LPC2292/LPC2294
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
Rev. 7 — 4 December 2008 Product data sheet
1. General description
The LPC2292/LPC2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/LPC2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
2. Features
2.1 Key features brought by LPC2292/LPC2294/01 devices
I Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device. They also allow for a port pin to be read at any time regardless of its function. I Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are 5 V tolerant when configured for digital I/O function(s). I UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented in hardware. I Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats. I SPI programmable data length and master mode enhancement. I Diversified Code Read Protection (CRP) enables different security levels to be implemented. This feature is available in LPC2292/LPC2294/00 devices as well. I General purpose timers can operate as external event counters.
2.2 Key features common for all devices
I 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
I 16 kB on-chip static RAM and 256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation. I In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader software. Single flash sector or full chip erase in 400 ms and programming of 256 B in 1 ms. I EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software as well as high-speed real-time tracing of instruction execution. I Two/four (LPC2292/LPC2294) interconnected CAN interfaces with advanced acceptance filters. Additional serial interfaces include two UARTs (16C550), Fast I2C-bus (400 kbit/s) and two SPIs. I Eight channel 10-bit ADC with conversion time as low as 2.44 µs. I Two 32-bit timers (with four capture and four compare channels), PWM unit (six outputs), Real-Time Clock (RTC), and watchdog. I Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses. I Configurable external memory interface with up to four banks, each up to 16 MB and 8/16/32-bit data width. I Up to 112 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive external interrupt pins available. I 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 µs. I The on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz. I Power saving modes include Idle and Power-down. I Processor wake-up from Power-down mode via external interrupt. I Individual enable/disable of peripheral functions for power optimization. I Dual power supply: N CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V). N I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1. Ordering information Package Name LPC2292FBD144 LPC2292FBD144/00 LPC2292FBD144/01 LPC2292FET144/00 LPC2292FET144/01 LPC2292FET144/G LQFP144 LQFP144 LQFP144 TFBGA144 TFBGA144 TFBGA144 Description plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm plastic thin fine-pitch ball grid array package; 144 balls; body 12 × 12 × 0.8 mm plastic thin fine-pitch ball grid array package; 144 balls; body 12 × 12 × 0.8 mm plastic thin fine-pitch ball grid array package; 144 balls; body 12 × 12 × 0.8 mm Version SOT486-1 SOT486-1 SOT486-1 SOT569-2 SOT569-2 SOT569-2 Type number
LPC2292_2294_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 4 December 2008
2 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Ordering information …continued Package Name Description plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm Version SOT486-1 SOT486-1 SOT486-1 LQFP144 LQFP144 LQFP144
Table 1.
Type number LPC2294HBD144 LPC2294HBD144/00 LPC2294HBD144/01
3.1 Ordering options
Table 2. Ordering options Flash memory RAM CAN Fast GPIO/ SSP/ Enhanced UART, ADC, Timer no no yes no yes no no no yes Temperature range Type number
LPC2292FBD144
256 kB
16 kB 16 kB 16 kB 16 kB 16 kB 16 kB 16 kB 16 kB 16 kB
2 channels 2 channels 2 channels 2 channels 2 channels 2 channels 4 channels 4 channels 4 channels
−40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C
LPC2292FBD144/00 256 kB LPC2292FBD144/01 256 kB LPC2292FET144/00 LPC2292FET144/01 LPC2292FET144/G LPC2294HBD144 256 kB 256 kB 256 kB 256 kB
LPC2294HBD144/00 256 kB LPC2294HBD144/01 256 kB
LPC2292_2294_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 4 December 2008
3 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
4. Block diagram
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1) XTAL2 XTAL1 RESET
EMULATION TRACE MODULE
LPC2292 LPC2294
HIGH-SPEED GPIO(4) 48 PINS TOTAL
TEST/DEBUG INTERFACE
PLL system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
AHB BRIDGE
P0, P1
ARM7 local bus INTERNAL SRAM CONTROLLER INTERNAL FLASH CONTROLLER
AMBA AHB (Advanced High-performance Bus)
AHB DECODER AHB TO APB BRIDGE APB DIVIDER CS3 to CS0(2) A23 to A0(2) BLS3 to BLS0(2) OE, WE(2) D31 to D0(2) SCL SDA SCK1 SPI1/SSP(4) SERIAL INTERFACE MOSI1 MISO1 SSEL1
16 kB SRAM
256 kB FLASH
EXTERNAL MEMORY CONTROLLER
EINT3 to EINT0
EXTERNAL INTERRUPTS
APB (advanced peripheral bus) I2C-BUS SERIAL INTERFACE
4 × CAP0 4 × CAP1 4 × MAT0 4 × MAT1
CAPTURE/ COMPARE TIMER 0/TIMER 1
AIN3 to AIN0 A/D CONVERTER AIN7 to AIN4 P0[30:0] P1[31:16], P1[1:0] P2[31:0] P3[31:0] PWM6 to PWM1 PWM0 CAN REAL-TIME CLOCK GENERAL PURPOSE I/O UART0/UART1 SPI0 SERIAL INTERFACE
SCK0 MOSI0 MISO0 SSEL0 TXD0, TXD1 RXD0, RXD1 DSR1, CTS1, DCD1, RI1 TD2, TD1 RD2, RD1 TD4, TD3(3) RD4, RD3(3)
SYSTEM CONTROL
WATCHDOG TIMER
002aad184
(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available. (2) Pins shared with GPIO. (3) Available in LPC2294 only. (4) SSP interface and high-speed GPIO are available on LPC2292/2294/01 only.
Fig 1. Block diagram
LPC2292_2294_7 © NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 4 December 2008
4 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
5. Pinning information
5.1 Pinning
144 109 108 73 37 72
002aad185
1
LPC2292FBD LPC2294HBD(1)
36
(1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 2. LQFP144 pinning
ball A1 index area
LPC2292FET144(1)
1 2 3 4 5 6 7 8 9 10 11 12 13
A B C D E F G H J K L M N
002aad191
Transparent top view
(1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 3. TFBGA144 pinning
LPC2292_2294_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 4 December 2008
5 of 53
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Product data sheet Rev. 7 — 4 December 2008
© NXP B.V. 2008. All rights reserved. LPC2292_2294_7
NXP Semiconductors
Table 3. 1 A B
Ball allocation 2 VDDA(1V8) P1[27]/ TDO 3 P1[28]/ TDI XTAL2 4 P2[21]/ D21 VSSA(PLL) 5 P2[18]/ D18 P2[19]/ D19 6 P2[14]/ D14 P2[15]/ D15 7 P1[29]/ TCK P2[12]/ D12 8 P2[11]/ D11 P0[20]/ MAT1[3]/ SSEL1/ EINT3 P0[19]/ MAT1[2]/ MOSI1/ CAP1[2] P0[18]/ CAP1[3]/ MISO1/ MAT1[3] 9 P2[10]/ D10 VDD(3V3) 10 P2[7]/D7 P2[6]/D6 11 VDD(3V3) VSS 12 VDD(1V8) P2[3]/D3 13 P2[4]/D4 VSS
Row Column P2[22]/ D22 VDD(3V3)
C
P0[21]/ PWM5/ CAP1[3] P0[24]/ TD2
VSS
XTAL1
VSSA
RESET
P2[16]/ D16
P2[13]/ D13
P2[9]/D9
P2[5]/D5
P2[2]/D2
P2[1]/D1
VDD(3V3)
D
P1[19]/ TRACE PKT3 P2[24]/ D24
P0[23]/ RD2
P0[22]/ CAP0[0]/ MAT0[0] VSS
P2[20]/ D20
P2[17]/ D17
VSS
P2[8]/D8
P1[30]/ TMS
VSS
P1[20]/ TRACE SYNC P2[0]/D0
P0[17]/ CAP1[2]/ SCK1/ MAT1[2] P3[30]/ BLS1
16/32-bit ARM microcontrollers with external memory interface
E
P2[25]/ D25
P2[23]
P0[16]/ EINT0/ MAT0[2]/ CAP0[2] P3[31]/ BLS0 P0[14]/ DCD1/ EINT1 P0[13]/ DTR1/ MAT1[1] P3[3]/A3
P0[15]/ RI1/ EINT2 P1[21]/ PIPE STAT0
F
P2[27]/ D27/ BOOT1 P2[29]/ D29 P0[25]/ RD1
P1[18]/ TRACE PKT2 P2[28]/ D28 TD1
VDDA(3V3)
P2[26]/ D26/ BOOT0
VDD(3V3)
VSS
G
P2[30]/ P2[31]/ D30/AIN4 D31/AIN5 P0[27]/ AIN0/ CAP0[1]/ MAT0[1] P3[29]/ BLS2/ AIN6 VDD(3V3) P1[17]/ TRACE PKT1 P3[28]/ BLS3/ AIN7 P3[22]/ A22 P3[20]/ A20 P0[1]/ RXD0/ PWM3/ EINT0 P3[14]/ A14 P1[25]/ EXTIN0 P3[11]/ A11
P1[0]/CS0 P3[0]/A0
P1[1]/OE
LPC2292/LPC2294
H
P1[22]/ PIPE STAT1 P1[23]/ PIPE STAT2 P0[10]/ RTS1/ CAP1[0]
P3[2]/A2
P3[1]/A1
J
P0[28]/ AIN1/ CAP0[2]/ MAT0[2] P3[27]/ WE
VSS
P0[11]/ CTS1/ CAP1[1] VSS
P0[12]/ DSR1/ MAT1[0] P3[4]/A4
K
P3[26]/ CS1
VDD(3V3)
6 of 53
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Table 3. 1 L P0[29]/ AIN2/ CAP0[3]/ MAT0[3] P3[25]/ CS2 Ball allocation …continued 2 P0[30]/ AIN3/ EINT3/ CAP0[0] P3[24]/ CS3 3 P1[16]/ TRACE PKT0 VDD(3V3) 4 P0[0]/ TXD0/ PWM1 P1[31]/ TRST 5 P3[19]/ A19 6 P0[2]/ SCL/ CAP0[0] VDD(3V3) 7 P3[15]/ A15 8 P0[4]/ SCK0/ CAP0[1] P0[3]/ SDA/ MAT0[0]/ EINT1 VDD(3V3) 9 P3[12]/ A12 10 VSS 11 P1[24]/ TRACE CLK P0[7]/ SSEL0/ PWM2/ EINT2 P0[6]/ MOSI0/ CAP0[2] 12 P0[8]/ TXD1/ PWM4 P3[7]/A7 13 P0[9]/ RXD1/ PWM6/ EINT3 P3[5]/A5
Product data sheet Rev. 7 — 4 December 2008
© NXP B.V. 2008. All rights reserved. LPC2292_2294_7
NXP Semiconductors
Row Column
M
P3[18]/ A18
P3[16]/ A16
P3[13]/ A13
P3[9]/A9
N
VDD(1V8)
VSS
P3[23]/ A23/ XCLK
P3[21]/ A21
P3[17]/ A17
P1[26]/ RTCK
VSS
P0[5]/ MISO0/ MAT0[1]
P3[10]/ A10
P3[8]/A8
P3[6]/A6
16/32-bit ARM microcontrollers with external memory interface
LPC2292/LPC2294
7 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
5.2 Pin description
Table 4. Symbol P0[0] to P0[31] Pin description Pin (LQFP) Pin (TFBGA)[1] Type I/O Description Port 0: Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. Pins 26 and 31 of port 0 are not available. P0[0]/TXD0/ PWM1 P0[1]/RXD0/ PWM3/EINT0 42[2] 49[4] L4[2] K6[4] O O I O I P0[2]/SCL/ CAP0[0] P0[3]/SDA/ MAT0[0]/EINT1 50[5] L6[5] I/O I 58[5] M8[5] I/O O I P0[4]/SCK0/ CAP0[1] P0[5]/MISO0/ MAT0[1] P0[6]/MOSI0/ CAP0[2] P0[7]/SSEL0/ PWM2/EINT2 59[2] L8[2] I/O I 61[2] N9[2] I/O O 68[2] N11[2] I/O I 69[4] M11[4] I O I P0[8]/TXD1/ PWM4 P0[9]/RXD1/ PWM6/EINT3 75[2] 76[4] L12[2] L13[4] O O I O I P0[10]/RTS1/ CAP1[0] P0[11]/CTS1/ CAP1[1] 78[2] 83[2] K11[2] J12[2] O I I I TXD0 — Transmitter output for UART0. PWM1 — Pulse Width Modulator output 1. RXD0 — Receiver input for UART0. PWM3 — Pulse Width Modulator output 3. EINT0 — External interrupt 0 input SCL — I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). CAP0[0] — Capture input for Timer 0, channel 0. SDA — I2C-bus data input/output. Open-drain output (for I2C-bus compliance). MAT0[0] — Match output for Timer 0, channel 0. EINT1 — External interrupt 1 input. SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave. CAP0[1] — Capture input for Timer 0, channel 1. MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data output from SPI slave. MAT0[1] — Match output for Timer 0, channel 1. MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. CAP0[2] — Capture input for Timer 0, channel 2. SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave. PWM2 — Pulse Width Modulator output 2. EINT2 — External interrupt 2 input. TXD1 — Transmitter output for UART1. PWM4 — Pulse Width Modulator output 4. RXD1 — Receiver input for UART1. PWM6 — Pulse Width Modulator output 6. EINT3 — External interrupt 3 input. RTS1 — Request to Send output for UART1. CAP1[0] — Capture input for Timer 1, channel 0. CTS1 — Clear to Send input for UART1. CAP1[1] — Capture input for Timer 1, channel 1.
LPC2292_2294_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 4 December 2008
8 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 4. Symbol
Pin description …continued Pin (LQFP) 84[2] Pin (TFBGA)[1] J13[2] Type I O I 85[2] H10[2] O O O 92[4] G10[4] I I Description DSR1 — Data Set Ready input for UART1. MAT1[0] — Match output for Timer 1, channel 0. RD4 — CAN4 receiver input (LPC2294 only). DTR1 — Data Terminal Ready output for UART1. MAT1[1] — Match output for Timer 1, channel 1. TD4 — CAN4 transmitter output (LPC2294 only). DCD1 — Data Carrier Detect input for UART1. EINT1 — External interrupt 1 input. Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after reset.
P0[12]/DSR1/ MAT1[0]/RD4
P0[13]/DTR1/ MAT1[1]/TD4
P0[14]/DCD1/ EINT1
P0[15]/RI1/ EINT2 P0[16]/EINT0/ MAT0[2]/ CAP0[2]
99[4] 100[4]
E11[4] E10[4]
I I I O I
RI1 — Ring Indicator input for UART1. EINT2 — External interrupt 2 input. EINT0 — External interrupt 0 input. MAT0[2] — Match output for Timer 0, channel 2. CAP0[2] — Capture input for Timer 0, channel 2. CAP1[2] — Capture input for Timer 1, channel 2. SCK1 — Serial Clock for SPI1/SSP[3]. SPI clock output from master or input to slave. MAT1[2] — Match output for Timer 1, channel 2. CAP1[3] — Capture input for Timer 1, channel 3. MISO1 — Master In Slave Out for SPI1/SSP[3]. Data input to SPI master or data output from SPI slave. MAT1[3] — Match output for Timer 1, channel 3. MAT1[2] — Match output for Timer 1, channel 2. MOSI1 — Master Out Slave In for SPI1/SSP[3]. Data output from SPI master or data input to SPI slave. CAP1[2] — Capture input for Timer 1, channel 2. MAT1[3] — Match output for Timer 1, channel 3. SSEL1 — Slave Select for SPI1/SSP[3]. Selects the SPI interface as a slave. EINT3 — External interrupt 3 input. PWM5 — Pulse Width Modulator output 5. RD3 — CAN3 receiver input (LPC2294 only). CAP1[3] — Capture input for Timer 1, channel 3. TD3 — CAN3 transmitter output (LPC2294 only). CAP0[0] — Capture input for Timer 0, channel 0. MAT0[0] — Match output for Timer 0, channel 0. RD2 — CAN2 receiver input. TD2 — CAN2 transmitter output. RD1 — CAN1 receiver input.
P0[17]/CAP1[2]/ 101[2] SCK1/MAT1[2]
D13[2]
I I/O O
P0[18]/CAP1[3]/ MISO1/MAT1[3]
121[2]
D8[2]
I I/O O
P0[19]/MAT1[2]/ MOSI1/CAP1[2]
122[2]
C8[2]
O I/O I
P0[20]/MAT1[3]/ SSEL1/EINT3
123[4]
B8[4]
O I I
P0[21]/PWM5/ RD3/CAP1[3]
4[2]
C1[2]
O I I
P0[22]/TD3/ CAP0[0]/ MAT0[0] P0[23]/RD2 P0[24]/TD2 P0[25]/RD1
5[2]
D4[2]
O I O
6[2] 8[2] 21[2]
D3[2] D1[2] H1[2]
I O I
LPC2292_2294_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 4 December 2008
9 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 4. Symbol
Pin description …continued Pin (LQFP) 23[6] Pin (TFBGA)[1] H3[6] Type I I O 25[6] J1[6] I I O 32[6] L1[6] I I O 33[6] L2[6] I I I Description AIN0 — ADC, input 0. This analog input is always connected to its pin. CAP0[1] — Capture input for Timer 0, channel 1. MAT0[1] — Match output for Timer 0, channel 1. AIN1 — ADC, input 1. This analog input is always connected to its pin. CAP0[2] — Capture input for Timer 0, channel 2. MAT0[2] — Match output for Timer 0, channel 2. AIN2 — ADC, input 2. This analog input is always connected to its pin. CAP0[3] — Capture input for Timer 0, Channel 3. MAT0[3] — Match output for Timer 0, channel 3. AIN3 — ADC, input 3. This analog input is always connected to its pin. EINT3 — External interrupt 3 input. CAP0[0] — Capture input for Timer 0, channel 0. Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect Block. Pins 2 through 15 of port 1 are not available. CS0 — LOW-active Chip Select 0 signal. (Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF) OE — LOW-active Output Enable signal. TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up. TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up. TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up. TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up. TRACESYNC — Trace Synchronization. Standard I/O port with internal pull-up. Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as Trace port after reset.
P0[27]/AIN0/ CAP0[1]/ MAT0[1]
P0[28]/AIN1/ CAP0[2]/ MAT0[2]
P0[29]/AIN2/ CAP0[3]/ MAT0[3]
P0[30]/AIN3/ EINT3/CAP0[0]
P1[0] to P1[31]
I/O
P1[0]/CS0 P1[1]/OE P1[16]/ TRACEPKT0 P1[17]/ TRACEPKT1 P1[18]/ TRACEPKT2 P1[19]/ TRACEPKT3 P1[20]/ TRACESYNC
91[7] 90[7] 34[7] 24[7] 15[7] 7[7] 102[7]
G11[7] G13[7] L3[7] H4[7] F2[7] D2[7] D12[7]
O O O O O O O
P1[21]/ PIPESTAT0 P1[22]/ PIPESTAT1 P1[23]/ PIPESTAT2 P1[24]/ TRACECLK
95[7] 86[7] 82[7] 70[7]
F11[7] H11[7] J11[7] L11[7]
O O O O
PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up. PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up. PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up. TRACECLK — Trace Clock. Standard I/O port with internal pull-up.
LPC2292_2294_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 4 December 2008
10 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 4. Symbol
Pin description …continued Pin (LQFP) 60[7] 52[7] Pin (TFBGA)[1] K8[7] N6[7] Type I I/O Description EXTIN0 — External Trigger Input. Standard I/O with internal pull-up. RTCK — Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as Debug port after reset.
P1[25]/EXTIN0 P1[26]/RTCK
P1[27]/TDO P1[28]/TDI P1[29]/TCK
144[7] 140[7] 126[7]
B2[7] A3[7] A7[7]
O I I
TDO — Test Data out for JTAG interface. TDI — Test Data in for JTAG interface. TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. TMS — Test Mode Select for JTAG interface. TRST — Test Reset for JTAG interface. Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin Connect Block. D0 — External memory data line 0. D1 — External memory data line 1. D2 — External memory data line 2. D3 — External memory data line 3. D4 — External memory data line 4. D5 — External memory data line 5. D6 — External memory data line 6. D7 — External memory data line 7. D8 — External memory data line 8. D9 — External memory data line 9. D10 — External memory data line 10. D11 — External memory data line 11. D12 — External memory data line 12. D13 — External memory data line 13. D14 — External memory data line 14. D15 — External memory data line 15. D16 — External memory data line 16. D17 — External memory data line 17. D18 — External memory data line 18. D19 — External memory data line 19. D20 — External memory data line 20. D21 — External memory data line 21. D22 — External memory data line 22. D23 — External memory data line 23.
© NXP B.V. 2008. All rights reserved.
P1[30]/TMS P1[31]/TRST P2[0] to P2[31]
113[7] 43[7]
D10[7] M4[7]
I I I/O
P2[0]/D0 P2[1]/D1 P2[2]/D2 P2[3]/D3 P2[4]/D4 P2[5]/D5 P2[6]/D6 P2[7]/D7 P2[8]/D8 P2[9]/D9 P2[10]/D10 P2[11]/D11 P2[12]/D12 P2[13]/D13 P2[14]/D14 P2[15]/D15 P2[16]/D16 P2[17]/D17 P2[18]/D18 P2[19]/D19 P2[20]/D20 P2[21]/D21 P2[22]/D22 P2[23]/D23
LPC2292_2294_7
98[7] 105[7] 106[7] 108[7] 109[7] 114[7] 115[7] 116[7] 117[7] 118[7] 120[7] 124[7] 125[7] 127[7] 129[7] 130[7] 131[7] 132[7] 133[7] 134[7] 136[7] 137[7] 1[7] 10[7]
E12[7] C12[7] C11[7] B12[7] A13[7] C10[7] B10[7] A10[7] D9[7] C9[7] A9[7] A8[7] B7[7] C7[7] A6[7] B6[7] C6[7] D6[7] A5[7] B5[7] D5[7] A4[7] A1[7] E3[7]
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 4. Symbol P2[24]/D24 P2[25]/D25
Pin description …continued Pin (LQFP) 11[7] 12[7] 13[7] Pin (TFBGA)[1] E2[7] E1[7] F4[7] Type I/O I/O I/O I Description D24 — External memory data line 24. D25 — External memory data line 25. D26 — External memory data line 26. BOOT0 — While RESET is low, together with BOOT1 controls booting and internal operation. Internal pull-up ensures high state if pin is left unconnected. D27 — External memory data line 27. BOOT1 — While RESET is low, together with BOOT0 controls booting and internal operation. Internal pull-up ensures high state if pin is left unconnected. BOOT1:0 = 00 selects 8-bit memory on CS0 for boot. BOOT1:0 = 01 selects 16-bit memory on CS0 for boot. BOOT1:0 = 10 selects 32-bit memory on CS0 for boot. BOOT1:0 = 11 selects internal flash memory.
P2[26]/D26/ BOOT0
P2[27]/D27/ BOOT1
16[7]
F1[7]
I/O I
P2[28]/D28 P2[29]/D29 P2[30]/D30/ AIN4 P2[31]/D31/ AIN5 P3[0] to P3[31]
17[7] 18[7] 19[6]
G2[7] G1[7] G3[6]
I/O I/O I/O I
D28 — External memory data line 28. D29 — External memory data line 29. D30 — External memory data line 30. AIN4 — ADC, input 4. This analog input is always connected to its pin. D31 — External memory data line 31. AIN5 — ADC, input 5. This analog input is always connected to its pin. Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the Pin Connect Block. A0 — External memory address line 0. A1 — External memory address line 1. A2 — External memory address line 2. A3 — External memory address line 3. A4 — External memory address line 4. A5 — External memory address line 5. A6 — External memory address line 6. A7 — External memory address line 7. A8 — External memory address line 8. A9 — External memory address line 9. A10 — External memory address line 10. A11 — External memory address line 11. A12 — External memory address line 12. A13 — External memory address line 13. A14 — External memory address line 14. A15 — External memory address line 15. A16 — External memory address line 16.
© NXP B.V. 2008. All rights reserved.
20[6]
G4[6]
I/O I I/O
P3[0]/A0 P3[1]/A1 P3[2]/A2 P3[3]/A3 P3[4]/A4 P3[5]/A5 P3[6]/A6 P3[7]/A7 P3[8]/A8 P3[9]/A9 P3[10]/A10 P3[11]/A11 P3[12]/A12 P3[13]/A13 P3[14]/A14 P3[15]/A15 P3[16]/A16
LPC2292_2294_7
89[7] 88[7] 87[7] 81[7] 80[7] 74[7] 73[7] 72[7] 71[7] 66[7] 65[7] 64[7] 63[7] 62[7] 56[7] 55[7] 53[7]
G12[7] H13[7] H12[7] J10[7] K13[7] M13[7] N13[7] M12[7] N12[7] M10[7] N10[7] K9[7] L9[7] M9[7] K7[7] L7[7] M7[7]
O O O O O O O O O O O O O O O O O
Product data sheet
Rev. 7 — 4 December 2008
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 4. Symbol P3[17]/A17 P3[18]/A18 P3[19]/A19 P3[20]/A20 P3[21]/A21 P3[22]/A22
Pin description …continued Pin (LQFP) 48[7] 47[7] 46[7] 45[7] 44[7] 41[7] 40[7] 36[7] 35[7] 30[7] 29[7] 28[6] Pin (TFBGA)[1] N5[7] M5[7] L5[7] K5[7] N4[7] K4[7] N3[7] M2[7] M1[7] K2[7] K1[7] J4[6] Type O O O O O O I/O O O O O O O I 27[6] J3[6] O I 97[7] 96[7] 22[7] 135[8] E13[7] F10[7] H2[7] C5[8] O O O I Description A17 — External memory address line 17. A18 — External memory address line 18. A19 — External memory address line 19. A20 — External memory address line 20. A21 — External memory address line 21. A22 — External memory address line 22. A23 — External memory address line 23. XCLK — Clock output. CS3 — LOW-active Chip Select 3 signal. (Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF) CS2 — LOW-active Chip Select 2 signal. (Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF) CS1 — LOW-active Chip Select 1 signal. (Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF) WE — LOW-active Write enable signal. BLS3 — LOW-active Byte Lane Select signal (Bank 3). AIN7 — ADC, input 7. This analog input is always connected to its pin. BLS2 — LOW-active Byte Lane Select signal (Bank 2). AIN6 — ADC, input 6. This analog input is always connected to its pin. BLS1 — LOW-active Byte Lane Select signal (Bank 1). BLS0 — LOW-active Byte Lane Select signal (Bank 0). TD1: CAN1 transmitter output. External Reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Ground: 0 V reference.
P3[23]/A23/ XCLK P3[24]/CS3 P3[25]/CS2 P3[26]/CS1 P3[27]/WE P3[28]/BLS3/ AIN7 P3[29]/BLS2/ AIN6 P3[30]/BLS1 P3[31]/BLS0 TD1 RESET
XTAL1 XTAL2 VSS
142[9] 141[9] 3, 9, 26, 38, 54, 67, 79, 93, 103, 107, 111, 128 139
C3[9] B3[9] C2, E4, J2, N2, N7, L10, K12, F13, D11, B13, B11, D7 C4
I O I
VSSA
I
Analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. PLL analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. 1.8 V core power supply: This is the power supply voltage for internal circuitry.
© NXP B.V. 2008. All rights reserved.
VSSA(PLL)
138
B4
I
VDD(1V8)
37, 110
N1, A12
I
LPC2292_2294_7
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 4. Symbol VDDA(1V8)
Pin description …continued Pin (LQFP) 143 Pin (TFBGA)[1] A2 Type I Description Analog 1.8 V core power supply: This is the power supply voltage for internal circuitry. This should be nominally the same voltage as VDD(1V8) but should be isolated to minimize noise and error. 3.3 V pad power supply: This is the power supply voltage for the I/O ports.
VDD(3V3)
I 2, 31, 39, 51, B1, K3, M3, 57, 77, 94, M6, N8, K10, 104, 112, 119 F12, C13, A11, B9 14 F3 I
VDDA(3V3)
Analog 3.3 V pad power supply: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error.
[1] [2] [3] [4] [5] [6]
LPC2294 only. 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. SSP interface available on LPC2292/2294/01 only. 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output functionality. Open-drain configuration applies to all output functions on this pin. 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured for a digital input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled. 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ. 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only. Pad provides special analog functionality.
[7] [8] [9]
LPC2292_2294_7
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISC. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set • A 16-bit Thumb set
The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-chip flash program memory
The LPC2292/LPC2294 incorporate a 256 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When the on-chip bootloader is used, 248 kB of flash memory is available for user code. The LPC2292/LPC2294 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data retention. On-chip bootloader (as of revision 1.64) provides Code Read Protection (CRP) for the LPC2292/LPC2294 on-chip flash memory. When the CRP is enabled, the JTAG debug port, external memory boot and ISP commands accessing either the on-chip RAM or flash memory are disabled. However, the ISP flash erase command can be executed at any time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is restored.
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6.3 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2292/LPC2294 provide 16 kB of SRAM.
6.4 Memory map
The LPC2292/LPC2294 memory maps incorporate several distinct regions, as shown in Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in Section 6.19 “System control”.
4.0 GB AHB PERIPHERALS 3.75 GB APB PERIPHERALS 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB RESERVED ADDRESS SPACE
0xC000 0000
2.0 GB
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY)
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4000 4000 0x4000 3FFF 16 kB ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0004 0000 0x0003 FFFF 256 kB ON-CHIP FLASH MEMORY 0.0 GB 0x0000 0000
002aaa754
Fig 4. LPC2292/LPC2294 memory map
LPC2292_2294_7
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Product data sheet
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 5 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the VIC, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Table 5. Block WDT ARM Core ARM Core Timer 0 Timer 1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved for software interrupts only EmbeddedICE, DbgCommRx EmbeddedICE, DbgCommTx Match 0 to 3 (MR0, MR1, MR2, MR3) Capture 0 to 3 (CR0, CR1, CR2, CR3) Match 0 to 3 (MR0, MR1, MR2, MR3) Capture 0 to 3 (CR0, CR1, CR2, CR3) RX Line Status (RLS) Transmit Holding Register Empty (THRE) RX Data Available (RDA) Character Time-out Indicator (CTI) Auto-baud time-out (ABTO)[1] End of auto-baud (ABEO)[1] 6 5 VIC channel # 0 1 2 3 4
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Interrupt sources …continued Flag(s) RX Line Status (RLS) Transmit Holding Register empty (THRE) RX Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-baud time-out (ABTO)[1] End of auto-baud (ABEO)[1] VIC channel # 7
Table 5. Block UART1
PWM0 I2C SPI0 PLL RTC System Control
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) SI (state change) SPIF, MODF PLL Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt 0 (EINT0) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2) External Interrupt 3 (EINT3)
8 9 10 11 12 13 14 15 16 17 18 19 20, 21 22, 23 24, 25 26, 27 28,29
SPI1 and SSP[1] SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS
ADC CAN
ADC 1 ORed CAN Acceptance Filter CAN1/2 Tx CAN2/3 Tx (LPC2294 only) reserved CAN1/2 Rx CAN3/4 Rx (LPC2294 only)
[1]
SSP interface and UART0/1 auto-baud control are available on LPC2292/2294/01 only.
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.
6.7 External memory controller
The external Static Memory Controller is a module which provides an interface between the system bus and external (off-chip) memory devices. It provides support for up to four independently configurable memory banks (16 MB each with byte lane enable control) simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash EPROM, burst ROM memory, or some external I/O devices. Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6.8 General purpose parallel I/O (GPIO) and Fast I/O
Device pins that are not connected to a specific peripheral function are controlled by the parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins.
6.8.1 Features
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits. • Separate control of output set and clear. • All I/O default to inputs after reset.
6.8.2 Features added with the Fast GPIO set of registers available on LPC2292/LPC2294/01 only
• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O
timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All Fast GPIO registers are byte addressable. • Entire port value can be written in one instruction. • Ports are accessible via either the legacy group of registers (GPIOs) or the group of
registers providing accelerated port access (Fast GPIOs).
6.9 10-bit ADC
The LPC2292/LPC2294 each contain a single 10-bit successive approximation ADC with four multiplexed channels.
6.9.1 Features
• • • •
Measurement range of 0 V to 3 V. Capable of performing more than 400000 10-bit samples per second. Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or Timer Match signal.
6.9.2 ADC features available in LPC2292/LPC2294/01 only
• Every analog input has a dedicated result register to reduce interrupt overhead. • Every analog input can generate an interrupt once the conversion is completed. • The ADC pads are 5 V tolerant when configured for digital I/O function(s).
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6.10 CAN controllers and acceptance filter
The LPC2292/LPC2294 each contain two/four CAN controllers. The CAN is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring.
6.10.1 Features
• • • • •
Data rates up to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1. Global Acceptance Filter recognizes 11-bit and 29-bit RX identifiers for all CAN buses. Acceptance Filter can provide FullCAN-style automatic reception for selected Standard identifiers.
6.11 UARTs
The LPC2292/LPC2294 each contain two UARTs. In addition to standard transmit and receive data lines, the UART1 also provides a full modem control handshake interface.
6.11.1 Features
• • • •
16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. control on both UARTs.
• Transmission FIFO control enables implementation of software (XON/XOFF) flow • UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
6.11.2 UART features available in LPC2292/LPC2294/01 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2292/LPC2294/01 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.
• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
• Auto-bauding. • Auto-CTS/RTS flow-control fully implemented in hardware. 6.12 I2C-bus serial I/O controller
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
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16/32-bit ARM microcontrollers with external memory interface
capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast I2C-bus).
6.12.1 Features
• • • • • •
Compliant with standard I2C-bus interface. Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus.
• Serial clock synchronization allows devices with different bit rates to communicate via • Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus may be used for test and diagnostic purposes. 6.13 SPI serial I/O controller
The LPC2292/LPC2294 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
6.13.1 Features
• • • •
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex communication. Combined SPI master and slave. Maximum data bit rate of 1⁄8 of the input clock rate.
6.13.2 Features available in LPC2292/LPC2294/01 only
• Eight to 16 bits per frame. • When the SPI interface is used in Master mode, the SSELn pin is not needed (can be
used for a different function).
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16/32-bit ARM microcontrollers with external memory interface
6.14 SSP controller (LPC2292/94/01 only)
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of four to 16 bits of data flowing from the master to the slave and from the slave to the master. While the SSP and SPI1 peripherals share the same physical pins, it is not possible to have both of these two peripherals active at the same time. Application can switch on the fly from SPI1 to SSP and back.
6.14.1 Features
• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
• • • •
Synchronous serial communication. Master or slave operation. 8-frame FIFOs for both transmit and receive. Four to 16 bits per frame.
6.15 General purpose timers
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.15.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler. • Timer or external event counter operation • Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.
• Four external outputs per timer corresponding to match registers, with the following
capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match.
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6.15.2 Features available in LPC2292/LPC2294/01 only
The LPC2292/LPC2294/01 can count external events on one of the capture inputs if the external pulse lasts at least one half of the period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts.
• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied
clock.
• When counting cycles of an externally supplied clock, only one of the timer’s capture
inputs can be selected as the timer’s clock. The rate of such a clock is limited to PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter than 1 / (2PCLK).
6.16 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.
6.16.1 Features
• Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• • • •
Incorrect/incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(PCLK) × 256 × 4) to (Tcy(PCLK) × 232 × 4) in multiples of Tcy(PCLK) × 4.
6.17 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
6.17.1 Features
• Measures the passage of time to maintain a calendar and clock. • Ultra-low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
• Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
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6.18 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2292/LPC2294. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).
6.18.1 Features
• Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
• The match registers also allow:
– Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
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• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become effective.
• May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit prescaler. 6.19 System control
6.19.1 Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.19.2 “PLL” for additional information.
6.19.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 µs.
6.19.3 Reset and wake-up timer
Reset has two sources on the LPC2292/LPC2294: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power-on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer.
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The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power-on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
6.19.4 Code security (Code Read Protection - CRP)
This feature of the LPC2292/LPC2294/01 allows the user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.
CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.
Remark: Devices without a /00 or /01 in the name have only a security level equivalent to CRP2 available.
6.19.5 External interrupt inputs
The LPC2292/LPC2294 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.
6.19.6 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
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6.19.7 Power control
The LPC2292/LPC2294 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode, and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.
6.19.8 APB bus
The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB bus must work properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at 1⁄4 of the processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
6.20 Emulation and debugging
The LPC2292/LPC2294 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself.
6.20.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol converter. EmbeddedICE protocol converter converts the remote debug protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug
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communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate.
6.20.2 Embedded trace
Since the LPC2292/LPC2294 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code cannot be traced because of this restriction.
6.20.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the Debug Communications Channel (DCC), which is present in the EmbeddedICE logic. The LPC2292/LPC2294 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory.
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7. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDDA(3V3) VIA VI IDD ISS Tj Tstg Ptot(pack) Parameter supply voltage (1.8 V) supply voltage (3.3 V) analog supply voltage (3.3 V) analog input voltage input voltage supply current ground current junction temperature storage temperature total power dissipation (per package) electrostatic discharge voltage based on package heat transfer, not device power consumption human body model all pins
[1]
[11] [10]
Conditions
[2] [3]
Min −0.5 −0.5 −0.5 −0.5
Max +2.5 +3.6 +4.6 +5.1 +6.0 VDD(3V3) + 0.5 100 100 150 +150 1.5
Unit V V V V V V mA mA °C °C W
5 V tolerant I/O pins other I/O pins
[4][5] [4][6] [7][8] [8][9]
−0.5 −0.5 −65 -
Vesd
−2000
+2000
V
The following applies to Table 6: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Internal rail. External rail. Including voltage on outputs in 3-state mode. Only valid when the VDD(3V3) supply voltage is present. Not to exceed 4.6 V. Per supply pin. The peak current is limited to 25 times the corresponding maximum current. Per ground pin.
[2] [3] [4] [5] [6] [7] [8] [9]
[10] Dependent on package type. [11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
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8. Static characteristics
Table 7. Static characteristics Tamb = −40 °C to +125 °C, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) Parameter supply voltage (1.8 V) supply voltage (3.3 V) Conditions
[2] [3]
Min 1.65 3.0 2.5
Typ[1] 1.8 3.3 3.3
Max 1.95 3.6 3.6
Unit V V V
VDDA(3V3) analog supply voltage (3.3 V) Standard port pins, RESET, RTCK IIL IIH IOZ Ilatch VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu LOW-level input current HIGH-level input current OFF-state output current I/O latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current pull-up current IOH = −4 mA IOL = 4 mA VOH = VDD(3V3) − 0.4 V VOL = 0.4 V VOH = 0 V VOL = VDD(3V3) VI = 5 V VI = 0 V VDD(3V3) < VI < 5 V Power consumption LPC2292, LPC2292/00, LPC2294, LPC2294/00 IDD(act) active mode supply current VDD(1V8) = 1.8 V; CCLK = 60 MHz; Tamb = 25 °C; code
[7] [7] [7] [7] [8]
VI = 0 V; no pull-up VI = VDD(3V3); no pull-down VO = 0 V, VO = VDD(3V3); no pull-up/down −(0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 °C
[4][5] [6]
100 0 0 2.0 0.4 −4 4 10 −15 0 -
50 −50 0 50
3 3 3 5.5 VDD(3V3) 0.8 0.4 −45 50 150 −85 0 -
µA µA µA mA V V V V V V V mA mA mA mA µA µA µA mA
output active
VDD(3V3) − 0.4 -
[8]
[9] [10] [9]
while(1){}
executed from flash; all peripherals enabled via PCONP[11] register but not configured to run
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Table 7. Static characteristics …continued Tamb = −40 °C to +125 °C, unless otherwise specified. Symbol IDD(pd) Parameter Power-down mode supply current Conditions VDD(1V8) = 1.8 V; Tamb = 25 °C VDD(1V8) = 1.8 V; Tamb = 85 °C VDD(1V8) = 1.8 V; Tamb = 125 °C Power consumption LPC2292/01 and LPC2294/01 IDD(act) active mode supply current VDD(1V8) = 1.8 V; CCLK = 60 MHz; Tamb = 25 °C; code 45 mA Min Typ[1] 10 110 300 Max 500 1000 Unit µA µA µA
while(1){}
executed from flash; all peripherals enabled via PCONP[11] register but not configured to run IDD(idle) Idle mode supply current VDD(1V8) = 1.8 V; CCLK = 60 MHz; Tamb = 25 °C; executed from flash; all peripherals enabled via PCONP[11] register but not configured to run IDD(pd) Power-down mode supply current VDD(1V8) = 1.8 V; Tamb = 25 °C VDD(1V8) = 1.8 V; Tamb = 85 °C VDD(1V8) = 1.8 V; Tamb = 125 °C I2C-bus pins VIH VIL Vhys VOL ILI HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS = 3 mA VI = VDD(3V3) VI = 5 V
[7] [12]
-
11.5
-
mA
-
10 -
180 430
µA µA µA
0.7VDD(3V3) -
2 10
-
V V V µA µA
0.3VDD(3V3) V 0.4 4 22
0.5VDD(3V3) -
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Table 7. Static characteristics …continued Tamb = −40 °C to +125 °C, unless otherwise specified. Symbol Vi(XTAL1) Vo(XTAL2) Parameter input voltage on pin XTAL1 output voltage on pin XTAL2 Conditions Min 0 0 Typ[1] Max 1.8 1.8 Unit V V Oscillator pins
[1] [2] [3] [4] [5] [6] [7] [8] [9]
Typical ratings are not guaranteed. The values listed are at room temperature (+25 °C), nominal supply voltages. Internal rail. External rail. Including voltage on outputs in 3-state mode. VDD(3V3) supply voltages must be present. 3-state outputs go into 3-state mode when VDD(3V3) is grounded. Accounts for 100 mV voltage drop in all supply lines. Allowed as long as the current limit does not exceed the maximum current allowed by the device. Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[10] Applies to P1[25:16]. [11] See the LPC2119/2129/2194/2292/2294 User Manual. [12] To VSS.
Table 8. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +125 °C unless otherwise specified. ADC frequency 4.5 MHz. Symbol VIA Cia ED EL(adj) EO EG ET
[1] [2] [3] [4] [5] [6] [7]
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
Min 0 [1][2][3] [1][4] [1][5] [1][6] [1][7]
Typ -
Max VDDA 1 ±1 ±2 ±3 ±0.5 ±4
Unit V pF LSB LSB LSB % LSB
-
Conditions: VSSA = 0 V, VDDA = 3.3 V. The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 5. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 5. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 5. The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 5.
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offset error EO 1023
gain error EG
1022
1021
1020
1019
1018
(2)
7 code out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024
0 1 2 3 4 5 6 7 VIA (LSBideal) offset error EO
1 LSB =
VDDA − VSSA 1024
002aaa668
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.
Fig 5. ADC characteristics
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8.1 Power consumption measurements for LPC2292/01 and LPC2294/01
The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register. For a description of the PCONP register bits, refer to the LPC2119/2129/2194/2292/2294 User Manual.
50 IDD(act) (mA) 40 all peripherals enabled all peripherals disabled 30
002aad102
20
10
0 12 20 28 36 44 52 60 frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; core voltage 1.8 V.
Fig 6.
Typical LPC2292/01 IDD(act) measured at different frequencies
50 IDD(act) (mA) 40
002aad103
60 MHz 48 MHz
30
20 12 MHz 10
0 1.65
1.80
voltage (V)
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; all peripherals enabled but not active.
Fig 7.
Typical LPC2292/01 IDD(act) measured at different core voltages
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45 60 MHz IDD(act) (mA) 35 48 MHz
002aad104
25
15 12 MHz
5 -40 -15 10 35 60 temperature (°C) 85
Test conditions: Active mode entered executing code on-chip flash; PCLK = CCLK⁄4; core voltage 1.8 V; all peripherals disabled.
Fig 8.
Typical LPC2292/01 IDD(act) measured at different temperatures
10.0 IDD(idle) (mA) 8.0 all peripherals enabled 6.0 all peripherals disabled
002aad105
4.0
2.0
0.0 12 20 28 36 44 52 frequency (MHz) 60
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; core voltage 1.8 V.
Fig 9.
Typical LPC2292/01 IDD(idle) measured at different frequencies
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10.0 IDD(idle) (mA) 8.0 60 MHz
002aad106
6.0
48 MHz
4.0
12 MHz 2.0 1.65 1.80 1.95
voltage (V)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; all peripherals enabled but not active.
Fig 10. Typical LPC2292/01 IDD(idle) measured at different core voltages
6.0 IDD(idle) (mA) 5.0 60 MHz
002aad107
4.0
48 MHz
3.0
2.0
12 MHz 1.0 -40 -15 10 35 60 temperature (°C) 85
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Core voltage 1.8 V; all peripherals disabled.
Fig 11. Typical LPC2292/01 IDD(idle) measured at different temperatures
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200 IDD(pd) (µA) 160 1.95 V 1.8 V 1.65 V
002aad108
120
80
40
0 -40
-15
10
35
60
temperature (°C)
85
Test conditions: Power-down mode entered executing code from on-chip flash.
Fig 12. Typical LPC2292/01 core power-down current IDD(pd) measured at different temperatures
50.0 IDD(act) (mA) 40.0 all peripherals enabled all peripherals disabled
002aad109
30.0
20.0
10.0
0.0 12 20 28 36 44 52 frequency (MHz) 60
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; core voltage 1.8 V.
Fig 13. Typical LPC2294/01 IDD(act) measured at different frequencies
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
55.0 IDD(act) (mA) 45.0 48 MHz 35.0 60 MHz
002aad110
25.0
12 MHz 15.0
5.0 1.65
1.80
voltage (V)
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; all peripherals enabled but not active.
Fig 14. Typical LPC2294/01 IDD(act) measured at different core voltages
45.0 IDD(act) (mA) 35.0 60 MHz
002aad111
48 MHz
25.0
15.0
12 MHz
5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (°C)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4; core voltage 1.8 V; all peripherals disabled.
Fig 15. Typical LPC2294/01 IDD(act) measured at different temperatures
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
002aad112
15.0 IDD(idle) (mA)
10.0 all peripherals enabled
5.0
all peripherals disabled
0.0 12 20 28 36 44 52 frequency (MHz) 60
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; core voltage 1.8 V.
Fig 16. Typical LPC2294/01 IDD(idle) measured at different frequencies
15.0
002aad113
IDD(idle) (mA) 10.0
60 MHz 48 MHz
5.0 12 MHz
0.0 1.65
1.80
voltage (V)
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; all peripherals enabled but not active.
Fig 17. Typical LPC2294/01 IDD(idle) measured at different core voltages
LPC2292_2294_7
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
6.50 IDD(idle) (mA) 5.50
002aad114
60 MHz
48 MHz 4.50
3.50
2.50 12 MHz 1.50
0.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (°C)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4; core voltage 1.8 V; all peripherals disabled.
Fig 18. Typical LPC2294/01 IDD(idle) measured at different temperatures
500 IDD(pd) (µA) 400 1.95 V 1.8 V 1.65 V 300
002aad115
200
100
0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip flash.
Fig 19. Typical LPC2294/01 core power-down current IDD(pd) measured at different temperatures
LPC2292_2294_7
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
45.0 IDD(act) (mA) 35.0 48 MHz 60 MHz
002aad116
25.0
15.0 12 MHz
5.0 1.65
1.80
voltage (V)
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; all peripherals disabled.
Fig 20. Typical LPC2292/01 and LPC2294/01 IDD(act) measured at different core voltages
10.0
002aad117
IDD(idle) (mA)
60 MHz 48 MHz
5.0
12 MHz
0.0 1.65
1.80
voltage (V)
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4; Tamb = 25 °C; all peripherals disabled.
Fig 21. Typical LPC2292/01 and LPC2294/01 IDD(idle) measured at different core voltages Table 9. Typical LPC2292/01 peripheral power consumption in active mode Core voltage 1.8 V; Tamb = 25 °C; all measurements in µA; PCLK = CCLK⁄4; all peripherals enabled. Peripheral Timer0 Timer1 UART0 UART1
LPC2292_2294_7
CCLK = 12 MHz 43 46 98 103
CCLK = 48 MHz 141 150 320 351
CCLK = 60 MHz 184 180 398 421
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 9. Typical LPC2292/01 peripheral power consumption in active mode …continued Core voltage 1.8 V; Tamb = 25 °C; all measurements in µA; PCLK = CCLK⁄4; all peripherals enabled. Peripheral PWM0 I2C-bus SPI0/1 RTC PCEMC ADC CAN1/2 CCLK = 12 MHz 103 9 6 16 306 33 229 CCLK = 48 MHz 341 37 27 55 994 128 771 CCLK = 60 MHz 407 53 29 78 1205 167 914
Table 10. Typical LPC2294/01 peripheral power consumption in active mode Core voltage 1.8 V; Tamb = 25 °C; all measurements in µA; PCLK = CCLK⁄4; all peripherals enabled. Peripheral Timer0 Timer1 UART0 UART1 PWM0 I2C-bus SPI0/1 RTC PCEMC ADC CAN1/2/3/4 CCLK = 12 MHz 43 46 98 103 103 9 6 16 306 33 230 CCLK = 48 MHz 141 150 320 351 341 37 27 55 994 128 769 CCLK = 60 MHz 184 180 398 421 407 53 29 78 1205 167 912
9. Dynamic characteristics
Table 11. Dynamic characteristics Tamb = −40 °C to +125 °C; VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol External clock fosc oscillator frequency supplied by an external oscillator (signal generator) external clock frequency supplied by an external crystal oscillator external clock frequency if on-chip PLL is used external clock frequency if on-chip bootloader is used for initial code download Tcy(clk) tCHCX tCLCX
LPC2292_2294_7
Parameter
Conditions
Min 1 1
Typ -
Max 25 25
Unit MHz MHz
10 10
-
25 25
MHz MHz
clock cycle time clock HIGH time clock LOW time
20 Tcy(clk) × 0.4 Tcy(clk) × 0.4
-
1000 -
ns ns ns
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 11. Dynamic characteristics …continued Tamb = −40 °C to +125 °C; VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol tCLCH tCHCL tr tf I2C-bus tf
[1] [2]
Parameter clock rise time clock fall time rise time fall time pins (P0[2] and P0[3]) fall time
Conditions
Min -
Typ 10 10
Max 5 5 -
Unit ns ns ns ns ns
Port pins (except P0[2] and P0[3])
VIH to VIL
[2]
20 + 0.1 × Cb -
Parameters are valid over operating temperature range unless otherwise specified. Bus capacitance Cb in pF, from 10 pF to 400 pF.
LPC2292_2294_7
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Product data sheet
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 12. External memory interface dynamic characteristics CL = 25 pF, Tamb = 40 °C Symbol tCHAV tCHCSL tCHCSH tCHANV Parameter XCLK HIGH to address valid time XCLK HIGH to CS LOW time XCLK HIGH to CS HIGH time XCLK HIGH to address invalid time CS LOW to address valid time OE LOW to address valid time CS LOW to OE LOW time memory access time memory access time (initial burst-ROM) memory access time (subsequent burst-ROM) data input hold time CS HIGH to OE HIGH time OE HIGH to address invalid time XCLK HIGH to OE LOW time XCLK HIGH to OE HIGH time address valid to CS LOW time CS LOW to data valid time CS LOW to WE LOW time CS LOW to BLS LOW time WE LOW to data valid time CS LOW to data valid time WE LOW to WE HIGH time BLS LOW to BLS HIGH time WE HIGH to address invalid time WE HIGH to data invalid time BLS HIGH to address invalid time
[2] [1] [2][3] [1]
Conditions
Min -
Typ Max 10 10 10 10
Unit ns ns ns ns
Common to read and write cycles
Read cycle parameters tCSLAV tOELAV tCSLOEL tam tam(ibr) tam(sbr) th(D) tCSHOEH tOEHANV tCHOEL tCHOEH −5 −5 −5 (Tcy(CCLK) × (2 + WST1)) + (−20) (Tcy(CCLK) × (2 + WST1)) + (−20) Tcy(CCLK) + (−20) 0 −5 −5 −5 −5 +10 +10 +5 +5 +5 +5 +5 ns ns ns ns ns ns ns ns ns ns ns
[1]
[2][3]
[2][4]
[5]
Write cycle parameters tAVCSL tCSLDV tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV Tcy(CCLK) − 10 −5 −5 −5 −5 −5 Tcy(CCLK) × (1 + WST2) − 5 Tcy(CCLK) × (1 + WST2) − 5 Tcy(CCLK) − 5 (2 × Tcy(CCLK)) − 5 Tcy(CCLK) − 5 +5 +5 +5 +5 +5 Tcy(CCLK) × (1 + WST2) + 5 Tcy(CCLK) × (1 + WST2) + 5 Tcy(CCLK) + 5 ns ns ns ns ns ns ns ns ns
[2]
[2]
[2] [2]
(2 × Tcy(CCLK)) + 5 ns Tcy(CCLK) + 5 ns
LPC2292_2294_7
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Table 12. External memory interface dynamic characteristics …continued CL = 25 pF, Tamb = 40 °C Symbol tBLSHDNV tCHDV tCHWEL tCHBLSL tCHWEH tCHBLSH tCHDNV Parameter BLS HIGH to data invalid time XCLK HIGH to data valid time XCLK HIGH to WE LOW time XCLK HIGH to BLS LOW time XCLK HIGH to WE HIGH time XCLK HIGH to BLS HIGH time XCLK HIGH to data invalid time Conditions
[2]
Min (2 × Tcy(CCLK)) − 5 -
Typ Max -
Unit
(2 × Tcy(CCLK)) + 5 ns 10 10 10 10 10 10 ns ns ns ns ns ns
[1] [2] [3] [4] [5]
Except on initial access, in which case the address is set up Tcy(CCLK) earlier. Tcy(CCLK) = 1⁄CCLK. Latest of address valid, CS LOW, OE LOW to data valid. Address valid to data valid. Earliest of CS HIGH, OE HIGH, address change to data invalid.
Table 13.
Standard read access specifications Max frequency WST[1] setting WST ≥ 0; round up to integer Memory access time requirement
Access cycle
standard read
2 + WST 1 f MAX ≤ -------------------------------t RAM + 20 ns 1 + WST 2 f MAX ≤ --------------------------------t WRITE + 5 ns 2 + WST 1 f MAX ≤ ------------------------------t INIT + 20 ns 1 f MAX ≤ -------------------------------t ROM + 20 ns
t RAM + 20 ns WST 1 ≥ -------------------------------- – 2 t cy ( CCLK ) t WRITE – t CYC + 5 WST 2 ≥ ------------------------------------------t cy ( CCLK ) t INIT + 20 ns W ST 1 ≥ ------------------------------- – 2 t cy ( CCLK ) N/A
t RAM ≤ t cy ( CCLK ) × ( 2 + WST 1 ) – 20 ns t WRITE ≤ t cy ( CCLK ) × ( 1 + WST 2 ) – 5 ns t INIT ≤ t cy ( CCLK ) × ( 2 + WST 1 ) – 20 ns t ROM ≤ t cy ( CCLK ) – 20 ns
standard write
burst read - initial
burst read - subsequent 3×
[1]
See the LPC2119/2129/2194/2292/2294 User Manual for a description of the WSTn bits.
LPC2292_2294_7
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
9.1 Timing
XCLK tCSLAV CS tCSHOEH
addr tam data tCSLOEL tOELAV OE tCHOEL tCHOEH
002aaa749
th(D)
tOEHANV
Fig 22. External memory read access
XCLK tCSLDV CS
tAVCSL tWELWEH tBLSLBLSH tWEHANV tCSLBLSL tWELDV tBLSHANV
tCSLWEL BLS/WE
addr tCSLDV data tWEHDNV tBLSHDNV
OE
002aaa750
Fig 23. External memory write access
LPC2292_2294_7
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 24. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
LPC2292_2294_7
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
10. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1
c
y X
A 108 109 73 72 ZE
e
E HE
A A2
A1
(A 3) θ Lp L detail X
wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 θ 7 o 0
o
22.15 22.15 21.85 21.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Fig 25. Package outline SOT486-1 (LQFP144)
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
TFBGA144: plastic thin fine-pitch ball grid array package; 144 balls
SOT569-2
D
B
A
ball A1 index area
E
A
A2 A1 detail X
e1 e b ∅v ∅w
M M
CAB C
C y1 C y
N M L K J H G F E D C B A
e e2
ball A1 index area
1
2
3
4
5
6
7
8
9
10
11
12
13
X
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 1.20 1.05 0.95 A1 0.40 0.35 0.30 A2 0.80 0.70 0.65 b 0.50 0.45 0.40 D 12.1 12.0 11.9 E 12.1 12.0 11.9 e 0.8 e1 9.6 e2 9.6 v 0.15 w 0.05 y 0.1 y1 0.08
OUTLINE VERSION SOT569-2
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 08-01-29 08-03-14
Fig 26. Package outline SOT569-2 (TFBGA144)
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
11. Abbreviations
Table 14. Acronym ADC AHB AMBA APB CAN CISC FIFO GPIO I/O JTAG LSB PLL PWM RISC SPI SRAM SSI SSP TTL UART Acronym list Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Controller Area Network Complex Instruction Set Computer First In, First Out General Purpose Input/Output Input/Output Joint Test Action Group Least Significant Bit Phase-Locked Loop Pulse Width Modulator Reduced Instruction Set Computer Serial Peripheral Interface Static Random Access Memory Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
LPC2292_2294_7
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Product data sheet
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LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
12. Revision history
Table 15. Revision history Release date 20081204 Data sheet status Product data sheet Change notice Supersedes LPC2292_2294_6 Document ID LPC2292_2294_7 Modifications:
• • • • • • • •
Figure 1 “Block diagram”: corrected high-speed GPIO ports 48 pins; P0/P1 only. Figure 24 “External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)”: removed figure note row “VDD = 1.8 V”, updated graphic. Table 4 “Pin description”: pad descriptions corrected for pins P2[30], P2[31], P3[28], P3[30], P3[31]. Table 5 “Interrupt sources”: CAN and UART0/1 interrupt sources corrected. Table 7 “Static characteristics”: Vhys, moved 0.4 from Typ to Min column. Maximum frequency fosc for external oscillator and external crystal updated. Changed SOT569-1 to SOT569-2. Added overbar to indicate LOW-active for BLSn, CSn, OE, and WE Product data sheet LPC2292_2294_5 Type number LPC2292FBD144/01 has been added. Type number LPC2292FET144/01 has been added. Type number LPC2294HBD144/01 has been added. Details introduced with /01 devices on new peripherals/features (Fast I/O ports, SSP, CRP) and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added. Power consumption measurements for LPC2292/2294/01 added. Description of JTAG pin TCK has been updated. Product data sheet Product data sheet Product data sheet Product data Preliminary data LPC2292_2294_4 LPC2292_2294_3 LPC2292_2294-02 LPC2292_2294-01 -
LPC2292_2294_6 Modifications:
20071210
• • • • • •
LPC2292_2294_5 LPC2292_2294_4 LPC2292_2294_3 LPC2292_2294-02 LPC2292_2294-01
20070215 20060711 20051101 20041223 20040205
LPC2292_2294_7
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Product data sheet
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NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
13. Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
13.3 Disclaimers
General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V.
14. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC2292_2294_7
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Product data sheet
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52 of 53
NXP Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
15. Contents
1 2 2.1 2.2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 6.7 6.8 6.8.1 6.8.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key features brought by LPC2292/ LPC2294/01 devices. . . . . . . . . . . . . . . . . . . . . 1 Key features common for all devices . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 15 Architectural overview. . . . . . . . . . . . . . . . . . . 15 On-chip flash program memory . . . . . . . . . . . 15 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 17 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 18 External memory controller. . . . . . . . . . . . . . . 18 General purpose parallel I/O (GPIO) and Fast I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features added with the Fast GPIO set of registers available on LPC2292/ LPC2294/01 only . . . . . . . . . . . . . . . . . . . . . . 19 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ADC features available in LPC2292/ LPC2294/01 only . . . . . . . . . . . . . . . . . . . . . . 19 CAN controllers and acceptance filter . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UART features available in LPC2292/ LPC2294/01 only . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus serial I/O controller . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features available in LPC2292/LPC2294/ 01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SSP controller (LPC2292/94/01 only). . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 General purpose timers . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.15.2 6.16 6.16.1 6.17 6.17.1 6.18 6.18.1 6.19 6.19.1 6.19.2 6.19.3 6.19.4 6.19.5 6.19.6 6.19.7 6.19.8 6.20 6.20.1 6.20.2 6.20.3 7 8 8.1 9 9.1 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Features available in LPC2292/ LPC2294/01 only . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse width modulator . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System control . . . . . . . . . . . . . . . . . . . . . . . . Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset and wake-up timer . . . . . . . . . . . . . . . . Code security (Code Read Protection - CRP) External interrupt inputs . . . . . . . . . . . . . . . . . Memory mapping control . . . . . . . . . . . . . . . . Power control . . . . . . . . . . . . . . . . . . . . . . . . . APB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emulation and debugging. . . . . . . . . . . . . . . . EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . Embedded trace. . . . . . . . . . . . . . . . . . . . . . . RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Power consumption measurements for LPC2292/01 and LPC2294/01 . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 23 24 24 25 25 25 25 26 26 26 27 27 27 27 28 28 29 30 34 42 46 48 50 51 52 52 52 52 52 52 53
6.9 6.9.1 6.9.2 6.10 6.10.1 6.11 6.11.1 6.11.2 6.12 6.12.1 6.13 6.13.1 6.13.2 6.14 6.14.1 6.15 6.15.1
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 December 2008 Document identifier: LPC2292_2294_7
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