LPC2888

LPC2880; LPC2888 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface Rev. 03 — 17 April 2008 Preliminary data sheet 1. General description The LPC2880/2888 is an ARM7-based microcontroller for portable applications requiring low power and high performance. It includes a USB 2.0 Hi-Speed device interface, an external memory interface that can interface to SDRAM and flash, an SD/MMC memory card interface, ADC and DACs, and serial interfaces including UART, I2C-bus, and I2S-bus. Architectural enhancements like multi-channel DMA, processor cache, simultaneous operations on multiple internal buses, and flexible clock generation help ensure that the LPC2880/2888 can handle more demanding applications than many competing devices. The chip can be powered from a single battery, from the USB, or from regulated 1.8 V and 3.3 V. 2. Features 2.1 Key features I I I I I I I I I I I ARM7TDMI processor with 8 kB cache, operating at up to 60 MHz 1 MB on-chip flash program memory with 128-bit access for high performance 64 kB SRAM Boot ROM allows execution of flash code, external code, or flash programming via USB On-chip DC-to-DC converter can generate all required voltages from a single battery or from USB power Multiple internal buses allow simultaneous simple DMA, USB DMA, and program execution from on-chip flash without contention External memory controller supports flash, SRAM, ROM, and SDRAM Advanced vectored interrupt controller, supporting up to 30 vectored interrupts Innovative event router allows interrupt, power-up, and clock-start capabilities from up to 107 sources Multi-channel general purpose DMA controller that can be used with most on-chip peripherals as well as for memory-to-memory transfers Serial interfaces: N Hi-Speed or Full-Speed USB 2.0 device (480 Mbit/s or 12 Mbit/s) with on-chip physical layer N UART with fractional baud rate generation, flow control, IrDA support, and FIFOs N I2C-bus interface N I2S-bus (Inter IC Sound bus) interface for independent stereo digital audio input and output SD/MMC memory card interface I NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface I I I I I I I 10-bit ADC with 5-channel input multiplexing 16-bit stereo ADC and DACs with gain control Advanced clock generation and power control reduce power consumption Two 32-bit timers with selectable prescalers 8-bit/4-bit LCD interface bus Real-Time Clock (RTC) can be clocked by 32 kHz oscillator or another source Watchdog timer with interrupt and/or reset capabilities 3. Ordering information Table 1. Ordering information Package Name LPC2880FET180 LPC2888FET180/01 LPC2888FET180/D1 Description Version SOT640-1 SOT640-1 SOT640-1 TFBGA180 plastic thin fine-pitch ball grid array package; 180 balls; body 10 × 10 × 0.8 mm TFBGA180 plastic thin fine-pitch ball grid array package; 180 balls; body 10 × 10 × 0.8 mm TFBGA180 plastic thin fine-pitch ball grid array package; 180 balls; body 10 × 10 × 0.8 mm Type number 3.1 Ordering options Table 2. Ordering options Flash memory 1 MB 1 MB JTAG interface enabled enabled disabled[1] RAM 64 kB 64 kB 64 kB Temperature range −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C Type number LPC2880FET180 LPC2888FET180/01 LPC2888FET180/D1 [1] JTAG interface disabled to provide code read protection. These devices are meant for volume production (no JTAG debugging is possible). The on-chip flash on these devices can only be programmed via USB. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 2 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 4. Block diagram JTAG_TRST JTAG_TMS JTAG_TDO JTAG_TCK JTAG_SEL JTAG_TDI A[20:0], D[15:0], etc. DP, DM, VBUS, RREF, RPU LPC2880/2888 JTAG DEBUG INTERFACE 1 MB FLASH(1) FLASH INTERFACE 64 kB SRAM SRAM INTERFACE BOOT ROM ROM INTERFACE ARM7TDMI 8 kB CACHE EXTERNAL MEMORY CONTROLLER HS USB WITH DMA VECTORED INTERRUPT CONTROLLER MULTI-LAYER AHB +1.5 V or +5 V 3.3 V, 1.8 V START, STOP WATCHDOG TIMER SYSTEM CONTROL EVENT ROUTER XTALI XTALO X32I X32O Px.y CLOCK OSCILLATOR GENERATION AND PLLs UNIT OSCILLATOR REAL-TIME CLOCK GENERAL PURPOSE I/O 10-BIT A/D CONVERTER I2C-BUS INTERFACE 32-BIT TIMER 0 32-BIT TIMER 1 AHB TO APB BRIDGE 3 DC-TO-DC CONVERTER AHB TO APB BRIDGE 0 AHB TO APB BRIDGE 1 AHB TO APB BRIDGE 2 GP DMA CONTROLLER register interface SD/MMC CARD INTERFACE UART WITH IrDA LCD INTERFACE MCLK, MCMD MD[3:0] TXD, RTS RXD, CTS LCD bus SCL, SDA AIN[4:0] VREF, AIN_LNA, AINA, AINB AOUT_LNA TRIPLE ANALOG FIFO INPUT DUAL ANALOG OUTPUT FIFO I2S-BUS INPUT I2S-BUS OUTPUT DATI BCKI, WSI DATO BCKO, DCLKO, WSO 002aac296 AOUTA, AOUTA_DAC, AOUTB, AOUTB_DAC FIFO FIFO (1) LPC2888 only. Fig 1. Block diagram LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 3 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 5. Pinning information 5.1 Pinning ball A1 index area 1 A B C D E F G H J K L M N P R T U V 002aac239 2 3 4 5 6 7 8 9 10 12 14 16 18 11 13 15 17 LPC2880FET180 LPC2888FET180/01 LPC2888FET180/D1 Transparent top view Fig 2. Pin configuration Table 3. Pin 1 5 9 13 17 1 5 9 13 17 1 5 9 13 17 1 LPC2880_LPC2888_3 Pin allocation table Pin 2 6 10 14 18 2 6 10 14 18 2 6 10 14 18 2 Symbol D1/P0[1] VSS2(EMC) MCLKO/P1[14] A15/P0[31] A6/P0[22] D2/P0[2] D11/P0[11] CKE/P1[9] A16/P1[0] A7/P0[23] LD0/P4[4] D10/P0[10] CAS/P1[16] A17/P1[1] A8/P0[24] LD3/P4[7] 3 3 7 11 15 3 7 11 15 Pin 3 7 11 15 Symbol D3/P0[3] VDD2(EMC) DQM1/P1[11] VSS1(EMC) LCS/P4[0] D13/P0[13] STCS2/P1[7] A13/P0[29] LD2/P4[6] D12/P0[12] WE/P1[15] A14/P0[30] LD5/P4[9] 4 4 8 12 16 4 8 12 16 Pin 4 8 12 16 Symbol D4/P0[4] STCS1/P1[6] BLS0/P1[12] VDD1(EMC) D5/P0[5] D15/P0[15] BLS1/P1[13] A11/P0[27] D8/P0[8] D14/P0[14] DQM0/P1[10] A12/P0[28] © NXP B.V. 2008. All rights reserved. Symbol D0/P0[0] D6/P0[6] RAS/P1[17] A18/P1[2] OE/P1[18] RPO/P1[19] D7/P0[7] DYCS/P1[8] A19/P1[3] A9/P0[25] LD1/P4[5] D9/P0[9] STCS0/P1[5] A20/P1[4] A10/P0[26] LD4/P4[8] Row A Row B Row C Row D Preliminary data sheet Rev. 03 — 17 April 2008 4 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Pin allocation table …continued Pin 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 Symbol A5/P0[21] LD6/P4[10] A2/P0[18] LER/P4[3] WSO LRW/P4[2] BCKO/P3[5] MCMD/P5[1] VSS4(IO) MD1/P5[4] VDD4(IO3V3) CTS/P6[2] MODE1/P2[2] VREFP(DAC) STOP AOUTL DCDC_CLEAN i.c.[1] DCDC_VDDO(1V8) VSS5(IO) 3 15 3 15 3 15 3 15 3 15 3 15 3 15 3 15 3 15 3 15 Pin 15 Symbol LD7/P4[11] LRS/P4[1] MCLK/P5[0] MD0/P5[5] MD3/P5[2] RXD/P6[0] TXD/P6[1] AOUTR i.c.[1] i.c.[1] 4 16 4 16 4 16 4 16 4 16 4 16 4 16 4 16 4 16 4 16 Pin 16 Symbol A3/P0[19] A0/P0[16] DCLKO/P3[3] DATI/P3[0] SCL MODE2/P2[3] P2[0] DCDC_GND DCDC_VDDI(3V3) DCDC_VSS2 RREF © NXP B.V. 2008. All rights reserved. Table 3. Pin 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 LPC2880_LPC2888_3 Symbol A4/P0[20] VDD1(IO3V3) A1/P0[17] VSS1(IO) DATO/P3[6] VSS1(CORE) WSI/P3[2] VDD1(CORE1V8) BCKI/P3[1] MD2/P5[3] SDA RTS/P6[3] P2[1] VDD(DAC3V3) START VREFN(DAC) DCDC_VBAT i.c.[1] DCDC_LX2 VSS6(IO) - Row E Row F Row G Row H Row J Row K Row L Row M Row N Row P Preliminary data sheet Rev. 03 — 17 April 2008 5 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Pin allocation table …continued Pin 18 2 14 18 2 6 10 14 18 2 6 10 14 18 2 6 10 14 18 Symbol DCDC_VSS1 VDD6(IO3V3) DCDC_VDDO(3V3) i.c.[1] AIN3 XTALI RESET DCDC_VUSB VREFP(DADC) AIN2 VSS(ADC) VBUS/P7[0] VDD3(USB3V3) VSS(DADC) VSS2(IO) VDD(ADC3V3) VDD3(IO3V3) VDD4(USB3V3) 3 7 11 15 3 7 11 15 3 7 11 15 3 15 Pin Symbol i.c.[1] VCOM(DADC) AIN1 VSS3(INT) CONNECT VDD(DADC3V3) AIN0 VSS2(INT) VDD1(USB1V8) VDD(DADC1V8) X32I VDD2(CORE1V8) VDD1(FLASH1V8) 4 8 12 16 4 8 12 16 4 8 12 16 4 16 Pin Symbol VSS2(USB) AINL X32O VSS1(INT) VSS3(USB) JTAG_SEL VDD(OSC321V8) JTAG_TMS VDD2(USB1V8) JTAG_TCK VSS(OSC32) VSS2(CORE) VDD2(FLASH1V8) - Table 3. Pin 17 1 13 17 1 5 9 13 17 1 5 9 13 17 1 5 9 13 17 [1] Symbol DCDC_LX1 VDD5(IO3V3) VSS1(USB) AINR JTAG_TDI VSS(OSC) JTAG_TRST DM VREF(DADC) AIN4 VDD(OSC1V8) JTAG_TDO DP VREFN(DADC) VDD2(IO3V3) XTALO VSS3(IO) VSS3(CORE) Row R Row T Row U Row V These pins are connected internally and must be left unconnected in an application. 5.2 Pin description Table 4. Symbol AINL AINR VCOM(DADC) VREF(DADC) VREFN(DADC) VREFP(DADC) VDD(DADC1V8) VDD(DADC3V3) VSS(DADC) Pin description Ball # T4 T1 T3 U1 V1 U2 V3 U3 V2 Type[1] I I RV RV RV RV P P P Description analog L input channel analog R input channel ADC common reference voltage and analog output reference voltage combined on-chip ADC reference voltage ADC negative reference voltage ADC positive reference voltage 1.8 V for dual ADC 3.3 V for dual ADC ground for dual ADC Analog in (dual converter) LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 6 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Table 4. Symbol AIN0 AIN1 AIN2 AIN3 AIN4 Pin description …continued Ball # U7 T7 U6 T6 U5 V10 U10 M2 M3 M1 L2 L1 H17 G16 G17 G18 F17 F16 F18 L17 L18 M18 L16 P17 N17 M17 M16 Type[1] I I I I I P P O O RV RV P FI FI FI FO FO FO O I I P P P P P P P P P P P Description multiplexed analog input multiplexed analog input multiplexed analog input multiplexed analog input multiplexed analog input 3.3 V analog supply and reference voltage ground DAC L analog out DAC R analog out negative reference voltage positive reference voltage 3.3 V for DAC DAI bit clock; 5 V tolerant GPIO pin DAI serial data input; 5 V tolerant GPIO pin DAI word select; 5 V tolerant GPIO pin DAO bit clock; 5 V tolerant GPIO pin DAO serial data output; 5 V tolerant GPIO pin 256 × clock output; 5 V tolerant GPIO pin DAO word select; 5 V tolerant pin DC-to-DC converter activation DC-to-DC converter deactivation reference circuit ground, not connected to substrate DC-to-DC converter main ground and substrate connect to external coil for DC/DC1 connect to external coil for DC/DC2 connect to battery + DC/DC1 3.3 V input voltage DC/DC2 1.8 V output voltage DC/DC1 3.3 V output voltage ground for DC/DC1, not connected to substrate ground for DC/DC2, not connected to substrate connect to +5 V pin of USB connector Analog in (single converter) VDD(ADC3V3) VSS(ADC) AOUTL AOUTR VREFN(DAC) VREFP(DAC) VDD(DAC3V3) DAI interface BCKI/P3[1] DATI/P3[0] WSI/P3[2] DAO interface BCKO/P3[5] DATO/P3[6] DCLKO/P3[3] WSO START STOP DCDC_CLEAN DCDC_GND DCDC_LX1 DCDC_LX2 DCDC_VBAT DCDC_VDDI(3V3) Analog out (dual channel) DC-to-DC converters DCDC_VDDO(1V8) N18 DCDC_VDDO(3V3) R18 DCDC_VSS1 DCDC_VSS2 DCDC_VUSB P18 N16 T18 LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 7 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Table 4. Symbol D0/P0[0] D1/P0[1] D2/P0[2] D3/P0[3] D4/P0[4] D5/P0[5] D6/P0[6] D7/P0[7] D8/P0[8] D9/P0[9] D10/P0[10] D11/P0[11] D12/P0[12] D13/P0[13] D14/P0[14] D15/P0[15] A0/P0[16] A1/P0[17] A2/P0[18] A3/P0[19] A4/P0[20] A5/P0[21] A6/P0[22] A7/P0[23] A8/P0[24] A9/P0[25] A10/P0[26] A11/P0[27] A12/P0[28] A13/P0[29] A14/P0[30] A15/P0[31] A16/P1[0] A17/P1[1] A18/P1[2] A19/P1[3] A20/P1[4] Pin description …continued Ball # A1 A2 B2 A3 A4 B4 A5 B5 C4 C5 C6 B6 C7 B7 C8 B8 E16 E17 E18 D16 D17 D18 A18 B18 C18 B17 C17 B16 C16 B15 C15 A14 B14 C14 A13 B13 C13 A12 B12 C10 FO FO FO byte lane select for D[7:0], active LOW for static memory; GPIO pin byte lane select for D[15:8], active LOW for static memory; GPIO pin column address strobe, active LOW for SDRAM; GPIO pin © NXP B.V. 2008. All rights reserved. Type[1] FI Description external memory data bus, low byte (I/O); GPIO pins External memory interface FI external memory data bus, high byte (I/O); GPIO pins FO address bus for SDRAM and static memory; GPIO pins FO address bus for static memory; GPIO pins BLS0/P1[12] BLS1/P1[13] CAS/P1[16] LPC2880_LPC2888_3 Preliminary data sheet Rev. 03 — 17 April 2008 8 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Table 4. Symbol CKE/P1[9] Pin description …continued Ball # B10 C12 A11 B9 A10 A17 A9 B1 C9 A8 B11 C11 K18 J16 K16 K17 interface H16 J17 U4 V4 T5 U12 T13 U13 B3 C2 C1 C3 D2 D1 D3 E2 E3 F2 F3 G2 I/O I/O I I I I I O FO FO FO FO FO FO FO FO FO FO FO FO 6800 E or 8080 RD or 5 V tolerant GPIO pin ‘HIGH’ data register select, ‘LOW’ instruction register select, or 5 V tolerant GPIO pin 6800 W/R or 8080 WR or 5 V tolerant GPIO pin © NXP B.V. 2008. All rights reserved. Type[1] FO FO FO FO FO FO FO FO FO FO FO FO FI FI FI FI Description clock enable; active HIGH for SDRAM; GPIO pin data mask output for D[7:0], active HIGH for SDRAM; GPIO pin data mask output for D[15:8], active HIGH for SDRAM; GPIO pin chip select, active LOW for SDRAM; GPIO pin clock for SDRAM and SyncFlash memory; GPIO pin output enable, active LOW for static memory; GPIO pin row address strobe, active LOW for SDRAM; GPIO pin reset power-down, active LOW for SyncFlash memory; GPIO pin chip select, active LOW for static memory bank 0; GPIO pin chip select, active LOW for static memory bank 1; GPIO pin chip select, active LOW for static memory bank 2; GPIO pin write enable, active LOW for SDRAM and static memory; GPIO pin start-up mode pin 1 (pull-down); 5 V tolerant GPIO pin start-up mode pin 2 (pull-down); 5 V tolerant GPIO pin 5 V tolerant GPIO pin 5 V tolerant GPIO pin serial clock (input/open-drain output); 5 V tolerant pin serial data (input/open-drain output); 5 V tolerant pin JTAG selection (pull-down); 5 V tolerant pin JTAG reset input (pull-down); 5 V tolerant pin JTAG data input (pull-up); 5 V tolerant pin JTAG mode select input (pull-up); 5 V tolerant pin JTAG reset input (pull-down); 5 V tolerant pin JTAG data output; 5 V tolerant pin chip select to LCD device, programmable polarity; 5 V tolerant GPIO pin data bus to/from LCD (I/O) or 5 V tolerant GPIO pins DQM0/P1[10] DQM1/P1[11] DYCS/P1[8] MCLKO/P1[14] OE/P1[18] RAS/P1[17] RPO/P1[19] STCS0/P1[5] STCS1/P1[6] STCS2/P1[7] WE/P1[15] MODE1/P2[2] MODE2/P2[3] P2[0] P2[1] I2C-bus SCL SDA JTAG interface JTAG_SEL JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TRST JTAG_TDO LCD interface LCS/P4[0] LD0/P4[4] LD1/P4[5] LD2/P4[6] LD3/P4[7] LD4/P4[8] LD5/P4[9] LD6/P4[10] LD7/P4[11] LER/P4[3] LRS/P4[1] LRW/P4[2] LPC2880_LPC2888_3 GPIO and mode control Preliminary data sheet Rev. 03 — 17 April 2008 9 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Table 4. Symbol Pin description …continued Ball # H2 H3 J2 J1 J3 G3 V7 T8 U8 V8 T10 V9 U9 T9 T14 K2 K3 K1 L3 T15 T17 U17 P16 U14 U15 U16 U18 V18 R17 R16 T16 Type[1] FI FI FI FI FI FO I O P P I O P P I FI FI FO FO P I/O I/O P FI P P P P P P P Description command (I/O); 5 V tolerant GPIO pin data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin MCI clock output; 5 V tolerant GPIO pin 32.768 kHz oscillator input 32.768 kHz oscillator output 1.8 V ground main oscillator input main oscillator output 1.8 V ground master reset, active LOW; 5 V tolerant pin clear to send or transmit flow control, active LOW; 5 V tolerant GPIO pin serial input; 5 V tolerant GPIO pin request to send or receive flow control, active LOW; 5 V tolerant GPIO pin serial output; 5 V tolerant GPIO pin used for signalling speed capability; for high-speed USB, connect an external 1.5 kΩ resistor to 3.3 V negative USB data line positive USB data line transceiver reference; connect an external 12 kΩ 1 % resistor to ground USB supply detection; 5 V tolerant GPIO pin analog 1.8 V analog 1.8 V analog 3.3 V analog 3.3 V analog ground analog ground analog ground Memory card interface MCMD/P5[1] MD0/P5[5] MD1/P5[4] MD2/P5[3] MD3/P5[2] MCLK/P5[0] X32I X32O VDD(OSC321V8) VSS(OSC32) Oscillator (main) XTALI XTALO VDD(OSC1V8) VSS(OSC) Reset RESET UART CTS/P6[2] RXD/P6[0] RTS/P6[3] TXD/P6[1] USB interface CONNECT DM DP RREF VBUS/P7[0] VDD1(USB1V8) VDD2(USB1V8) VDD3(USB3V3) VDD4(USB3V3) VSS1(USB) VSS2(USB) VSS3(USB) Oscillator (32.768 kHz) LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 10 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Table 4. Symbol Pin description …continued Ball # H1 V15 A16 E1 V11 A7 V16 V5 V14 J18 R1 R2 G1 A15 T12 F1 V12 A6 U11 V6 V17 T11 V13 H18 P2 P1 Type[1] P P P P P P P P P P P P P P P P P P P P P P P P P P Description 1.8 V for internal RAM and ROM 1.8 V for internal flash memory 1.8 V or 3.3 V for external memory controller 3.3 V for peripherals 1.8 V for core 1.8 V or 3.3 V for external memory controller 1.8 V for internal flash memory 3.3 V for peripherals 3.3 V for peripherals 3.3 V for peripherals 3.3 V for peripherals 3.3 V for peripherals ground for internal RAM and ROM ground for external memory controller ground for other internal blocks ground for peripherals ground for core ground for external memory controller ground for other internal blocks ground for peripherals ground for core, substrate, flash ground for other internal blocks ground for peripherals ground for peripherals ground for peripherals ground for peripherals Digital power and ground VDD1(CORE1V8) VDD1(FLASH1V8) VDD1(EMC) VDD1(IO3V3) VDD2(CORE1V8) VDD2(EMC) VDD2(FLASH1V8) VDD2(IO3V3) VDD3(IO3V3) VDD4(IO3V3) VDD5(IO3V3) VDD6(IO3V3) VSS1(CORE) VSS1(EMC) VSS1(INT) VSS1(IO) VSS2(CORE) VSS2(EMC) VSS2(INT) VSS2(IO) VSS3(CORE) VSS3(INT) VSS3(IO) VSS4(IO) VSS5(IO) VSS6(IO) [1] I = input; O = output; I/O = input/output; RV = reference voltage; FI = functional input; FO = functional output; P = power or ground 6. Functional description 6.1 Architectural overview The LPC2880/2888 includes an ARM7TDMI CPU with an 8 kB cache, an AMBA AHB interfacing to high-speed on-chip peripherals and internal and external memory, and four AMBA APBs for connection to other on-chip peripheral functions. The LPC2880/2888 includes a multi-layer AHB and four separate APBs, in order to minimize interference between the USB controller, other DMA operations, and processor activity. Bus masters include the ARM7 itself, the USB block, and the general purpose DMA controller. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 11 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Lower speed peripheral functions are connected to the APBs. The four AHB-to-APB bridges interface the APBs to the AHB. 6.1.1 ARM7TDMI processor The ARM7TDMI is a general purpose 32-bit microprocessor that offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISCs. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI processor has two instruction sets: • The standard 32-bit ARM instruction set. • A 16-bit Thumb instruction set. The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide down to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The ARM7TDMI processor is described in detail on the ARM web site. 6.1.2 On-chip flash memory system The LPC2880/2888 includes a 1 MB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the USB port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. The flash is 128 bit wide and includes buffering to allow 3 out of 4 sequential read operations to operate without wait states. 6.1.3 On-chip SRAM The LPC2880/2888 includes 64 kB of SRAM that may be used for code and/or data storage. 6.1.4 On-chip ROM The LPC2880/2888 includes an on-chip ROM that contains boot code. Execution begins in on-chip ROM after a reset. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 12 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface The boot code in this ROM reads the state of the mode inputs and accordingly does one of the following: • • • • Starts execution in internal flash Starts execution in external memory Performs a hardware self-test, or Downloads code from the USB interface into on-chip RAM and transfers control to the downloaded code 6.2 Memory map The LPC2880/2888 memory map incorporates several distinct regions, as shown in Figure 3. When an application is running, the CPU interrupt vectors are remapped to allow them to reside in on-chip SRAM. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 13 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 4.0 GB reserved 0x9000 0000 to 0xFFFF FFFF 0xFFFF FFFF 0x9000 0000 0x8FFF FFFF peripherals 2.0 GB includes AHB and 4 APB buses reserved dynamic memory bank 0, 64 MB reserved static memory bank 2, 2 MB 0x8000 0000 to 0x8FFF FFFF 0x5400 0000 to 0x7FFF FFFF 0x5000 0000 to 0x53FF FFFF 0x4820 0000 to 0x4FFF FFFF 0x4800 0000 to 0x481F FFFF 0x4420 0000 to 0x47FF FFFF 0x4400 0000 to 0x441F FFFF 0x4020 0000 to 0x43FF FFFF 0x4000 0000 to 0x401F FFFF 0x3400 0000 to 0x3FFF FFFF 0x3000 0000 to 0x33FF FFFF 0x2820 0000 to 0x2FFF FFFF 0x2800 0000 to 0x281F FFFF 0x2420 0000 to 0x27FF FFFF 0x2400 0000 to 0x241F FFFF 0x2020 0000 to 0x23FF FFFF 0x2000 0000 to 0x201F FFFF 0x1050 0000 to 0x1FFF FFFF 0x1040 0000 to 0x104F FFFF 0x1000 0000 to 0x0000 003F 0x0050 0000 to 0x0FFF FFFF 0x0040 0000 to 0x0040 FFFF 0x2000 0000 0x1FFF FFFF 0x4000 0000 0x3FFF FFFF 0x8000 0000 0x7FFF FFFF external memory (second instance) reserved static memory bank 1, 2 MB reserved static memory bank 0, 2 MB 1.0 GB reserved dynamic memory bank 0, 64 MB reserved static memory bank 2, 2 MB external memory (first instance) reserved static memory bank 1, 2 MB reserved static memory bank 0, 2 MB reserved internal memory internal flash (1 MB) reserved reserved internal RAM (64 kB) remapped area internal ROM (32 kB) exception vectors 0x0020 0000 to 0x0020 7FFF 0x0000 0000 to 0x0000 001F 0x1000 0000 0x0FFF FFFF 0.0 GB 0x0000 0000 002aac240 Fig 3. Memory map LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 14 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 6.3 Cache The CPU of the LPC2880/2888 has been extended with a 2-way set-associative cache. The cache is 8 kB in size and can store both data and instruction code. If code that is being executed is present in the cache from a previous execution, the CPU will not experience code fetch waits. Similarly, if requested data is present in the cache, the CPU will not experience a data access wait. The trade-off of introducing this cache is that each AHB access that bypasses the cache will have an extra wait state inserted. Therefore it is advisable that both instruction caching and data caching are turned on for most regions of on and off-chip memory. 6.3.1 Cache operation The cache works as follows, for each page for which it is enabled: • If data is read and is not in the cache (a cache miss), a line of eight 32-bit words is read from the AHB bus. The CPU waits until this process is complete. • If data is read and is found in the cache (a cache hit), data is read from cache with zero wait states. • If data is written, and the location is not in the cache (a cache miss), the data is written directly to memory. • If data is written, and the location is in the cache because this location has been read before (a cache hit), the data is written into the cache with zero wait states, and the cache line is marked as ‘dirty’. • If a ‘dirty’ cache line is about to be discarded because of a cache miss (the cache line needs to be reused for a different memory region), the old line is written back to memory (a cache-line flush). The cache can be set to data-only, instruction-only or combined (unified) caching. The cache has 16 configurable pages, each 2 MB in range. The pages occupy the bottom 32 MB of the memory map. The virtual address and enable/disable status is configurable for each page. 6.3.2 Features • • • • 8 kB, 2-way set-associative cache. May be used as both an instruction and data cache. Zero wait states for a cache hit. 16 configurable pages, each 2 MB in range. 6.4 Flash memory and programming The LPC2888 incorporates 1 MB of flash memory, while the LPC2880 is a flash-less device. The flash memory of the LPC2888 may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the USB port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage, field firmware upgrades, etc. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 15 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Programming the flash in a running application is accomplished via a register interface on the APB bus. The flash module can generate an interrupt request when burning or erasing is completed. The flash memory contains a buffer to allow for faster execution. Information is read from the flash 128 bits at a time. The buffer holds this entire amount, which can represent four 32-bit ARM instructions. These captured instructions can them be executed without flash read delays, improving system performance. 6.4.1 Features • Flash access for processor execution and data read is via the AHB bus. • Flash programming in a running application is via an APB register interface. • Initial programming or reprogramming is can be accomplished from the USB port. 6.5 DC-to-DC converters The LPC2880/2888 include two DC-to-DC converters providing an on-chip power system which allows the device to be powered by a standard single cell battery (AA or AAA for example) as well as receive power from a USB port or other power source. The LPC2880/2888 need two supply voltages, 3.3 V and 1.8 V, for various internal functions. When power is available from a higher voltage source such as USB, two internal Low Dropout regulators (LDO regulators) reduce the incoming voltage to the level needed by the LPC2880/2888. When only a low voltage battery supply is available, two DC-to-DC converters boost the voltage up to the needed levels. Switching between the two modes is supported. 6.6 External memory controller The LPC2880/2888 External Memory Controller (EMC) is a multi-port memory controller that supports asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as Single Data Rate SDRAM. It complies with ARM’s AMBA. 6.6.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • • • • • Low transaction latency. Read and write buffers to reduce latency and to improve performance. 8-bit and 16-bit static memory support. 16-bit SDRAM memory support. Static memory features include: – Asynchronous page mode read. – Programmable wait states. – Bus turnaround delay. – Output enable and write enable delays. – Extended wait. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 16 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface – 2 MB address range with three chip selects. • One chip select for synchronous memory and three chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048, 4096, and 8192 row address synchronous memory parts. That is typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per device. Remark: Synchronous static memory devices (synchronous burst mode) are not supported. 6.7 GPIO Many device pins that are not needed for a specific peripheral function can be used as GPIOs. These pins can be controlled by the mode registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The current state of the port pins may be read back via the PIN registers. 6.7.1 Features • 81 pins have dual use as a specific function I/O or as a GPIO. • Each dual use pin can be programmed for functional I/O, drive high, drive low, or hi-Z/input. • Four pins are dedicated as GPIO, programmable for drive high, drive low, or hi-Z/input. 6.8 Interrupt controller The interrupt controller accepts all of the interrupt request inputs and categorizes them as FIQ or IRQ. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the interrupt controller combines the requests to produce the FIQ signal to the ARM processor. The interrupt controller combines the requests from all the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the interrupt controller and jumping there. 6.8.1 Features • • • • • Maps all LPC2880/2888 interrupt sources to processor FIQ and IRQ Level sensitive sources Programmable priority among sources Nested interrupt capability Software interrupt capability for each source LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 17 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 6.9 Event router 88 external and 11 internal LPC2880/2888 signals are connected to the Event Router block. GPIO input pins, functional input pins, and even functional outputs can be monitored by the Event Router. Each signal can act as an interrupt source or a clock-enable for LPC2880/2888 modules, with individual options for high- or low-level sensitivity or rising- or falling-edge sensitivity. The outputs of the polarity and sensitivity logic can be read from Raw Status Registers 0 to 3. Each active state is next masked/enabled by a “global” mask bit for that signal. The results can be read from Pending Registers 0 to 3. All 99 Pending signals are presented to each of the five output logic blocks. Each output logic block includes a set of four Interrupt Output Mask Registers, each set totalling 99 bits, that control whether each signal applies to that output. These are logically ANDed with the corresponding Pending signals, and the 99 results in each logic block are logically ORed to make the output of the block. The 496 results can be read in the Interrupt Output Pending Registers. Outputs 0 to 3 are routed to the Interrupt Controller, in which each can be individually enabled to cause an interrupt. Output 4 is routed to the Clock Generation Unit, in which it can serve to enable clocking for selected clock domains. The five outputs can be read in the Output Register. 6.10 General purpose timers The LPC2880/2888 contains two fully independent general purpose timers. Each timer is a 32 bit wide down counter with a selectable prescaler. The prescaler allows either the system clock to be used directly, or the clock to be divided by 16 or 256. Two modes of operation are available, free-running and periodic timer. In periodic timer mode, the counter will generate an interrupt at a constant interval. In free-running mode the timer will overflow after reaching its zero value and continue to count down from the maximum value. 6.10.1 Features • Two independent 32-bit timers. • Free-running or periodic operating modes. • Generate timed interrupts. 6.11 Watchdog timer The purpose of the watchdog timer is to interrupt and/or reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate an interrupt or a system reset if the user program fails to reset the watchdog within a predetermined amount of time. Alternatively, it can be used as an additional general purpose Timer. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 18 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface The WDT clock increments a 32-bit Prescale Counter, the value of which is continually compared to the value of the Prescale Register. When the Prescale Counter matches the Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the value in the Prescale Register plus one. The value of the Timer Counter is continually compared to the values in two registers called Match Register 0 and 1. When/if the value of the Timer Counter matches that of Match Register 0 at a WDT clock edge, a signal ‘m0’ can be asserted to the Event Router, which can be programmed to send an interrupt signal to the Interrupt Controller as a result. When/if the value of the Timer Counter matches that of Match Register 1 at a WDT clock edge, a signal ‘m1’ can be asserted to the CGU, which resets the chip as a result. The CGU also includes a flag to indicate whether a reset is due to a watchdog time-out. 6.11.1 Features • Optionally resets chip (via Clock Generation Unit) if not periodically reloaded. • Optional interrupt via Event Router. • 32-bit Prescaler and 32-bit Counter allow extended watchdog period. 6.12 Real-time clock The Real-time clock is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in either mode. 6.12.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra Low Power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32 kHz oscillator. • Dedicated power supply pin can be connected to a battery or to the main 1.8 V. 6.13 General purpose DMA controller The General Purpose DMA controller (GPDMA) is an AMBA AHB compliant master allowing selected LPC2880/2888 peripherals to have DMA support. Peripherals that can be serviced by the GPDMA channels include the SD/MCI card interface, UART TX and/or RX, the I2C-bus interface, the Simple Analog Out (SAO) front-ends to the I2S/DAO and 16-bit dual DACs, the Simple Analog In (SAI) interfaces for data from the I2S/DAI and 16-bit dual ADCs, and the LCD interface. 6.13.1 Features • Eight DMA channels. Each channel can support a unidirectional transfer, or a pair of channels can be used together to follow a linked list of buffer addresses and transfer counts. The GPDMA provides 16 peripheral DMA request lines. Most of these are connected to the peripherals listed above; two can be used for external requests. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 19 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface • The GPDMA supports a subset of the flow control signals supported by ARM DMA channels, specifically ‘single’ but not ‘burst’ operation. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Rotating channel priority. Each DMA channel has equal opportunity to perform transfers. • The GPDMA is one of three AHB masters in the LPC2880/2888, the others being the ARM7 processor and the USB interface. • Incrementing or non-incrementing addressing for source and destination. • Supports 8 bit, 16 bit, and 32 bit wide transactions. • GPDMA channels can be programmed to swap data between big- and little-endian formats during a transfer. • An interrupt to the processor can be generated on DMA completion, when a DMA channel is halfway to completion, or when a DMA error has occurred. 6.14 UART and IrDA The LPC2880/2888 contains one UART with baud rate generator and IrDA support. 6.14.1 Features • • • • • • • • 32-Byte Receive and Transmit FIFOs. Register locations conform to the 16C650 industry standard. Receiver FIFO trigger points at 1 B, 16 B, 24 B, and 28 B. Built-in baud rate generator. CGU generates UART clock including fractional divider capability. Auto baud capability. Optional hardware flow control. IrDA mode for infrared communication. 6.15 I2C-bus interface The LPC2880/2888 I2C-bus interface is byte oriented and has four operating modes: master Transmit mode, master Receive mode, slave Transmit mode and slave Receive mode. The interface complies with the entire I2C-bus specification, and allows turning power off to the LPC2880/2888 without causing a problem with other devices on the same I2C-bus. 6.15.1 Features • Standard I2C-bus interface, configurable as Master, Slave, or Master/Slave. • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Programmable clock allows adjustment of I2C-bus transfer rates. • Bidirectional data transfer between masters and slaves. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 20 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • Supports normal (100 kHz) and fast (400 kHz) operation. 6.16 10-bit ADC The LPC2880/2888 contains a single 10-bit successive approximation ADC with five multiplexed channels. 6.16.1 Features • • • • • • 10-bit successive approximation ADC. Input multiplexing among 5 pins. Power-down mode. Measurement range 0 V to 3.3 V. 10-bit conversion time ≥ 2.44 µs. Single or continuous conversion mode. 6.17 Analog I/O The analog I/O system includes an I2S-bus input channel, an I2S-bus output channel, a dual ADC, and a dual DAC. Each channel includes a separate 4-sample FIFO. Each of the two ADC inputs is connected to a Programmable Gain Amplifier (PGA). Each DAC has two output pins. 6.17.1 Features • I2S-bus input channel with a 4-sample FIFO for stereo DAI. • I2S-bus output channel with a 4-sample FIFO for stereo DAO. • Dual 16-bit ADCs with individual inputs routed through programmable gain amplifiers. Input takes place through a 4-sample FIFO. • Dual 16-bit DACs. Each DAC has its own output pin. Output takes place through a 4-sample FIFO. 6.18 USB 2.0 Hi-Speed device controller The USB is a 4-wire bus that supports communication between a host and a number (127 maximum) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, un-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The host schedules transactions in 1 ms frames. Each frame contains an SOF marker and transactions that transfer data to/from device endpoints. There are four types of transfers defined for the endpoints. Control transfers are used to configure the device. Interrupt transfers are used for periodic data transfer. Bulk transfers are used when rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no error correction. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 21 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface The LPC2880/2888 USB controller enables 480 Mbit/s or 12 Mbit/s data exchange with a USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0 ATX physical interface. The USB controller consists of the protocol engine and buffer management blocks. It includes an SRAM that is accessible to the DMA engine and to the processor via the register interface. The DMA engine is an AHB master, having direct access to all of ARM memory space but particularly to on-chip RAM. Each USB endpoint that requires its data to be transferred via DMA is allocated to a logical DMA channel in the DMA engine. Endpoints with small packet sizes can be handled by software via registers in the USB controller. In particular, Control Endpoint 0 is always handled in this way. 6.18.1 Features • • • • • • • • • • Fully compliant with USB 2.0 specification (Hi-Speed and Full-Speed). 8 logical endpoints = 16 physical endpoints. Supports Control, Bulk, Interrupt and Isochronous endpoints. Endpoint type selection by software. Endpoint maximum packet size setting by software. Supports SoftConnect feature (requires an external 1.5 kΩ resistor between the CONNECT pad and 3.3 V). Supports bus-powered capability with low suspend current. Two DMA channels, assignable to any of 4 physical endpoints. Supports Burst data transfers on the AHB. Supports Retry and Split transactions on the AHB. 6.19 SD/MMC card interface The SD and MCI is an interface between the APB and multimedia and/or secure digital memory cards. The interface provides all functions specific to the Secure Digital/MultiMedia memory card, such as the clock generation unit, power management control, command, data transfer, interrupt generation, and DMA request generation. 6.19.1 Features • Conformance to Multimedia Card Specification v2.11. • Conformance to Secure Digital Memory Card Physical Layer Specification, v0.96. • Use as a multimedia card bus or a secure digital memory card bus host. It can be connected to several multimedia cards, or a single secure digital memory card. • DMA transfers are supported through the Simple DMA facility. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 22 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 6.20 LCD interface The LCD interface contains logic to interface to a 6800 or 8080 bus compatible LCD controller. The LCD interface is compatible with the 6800 bus standard and the 8080 bus standard, with one address pin (RS) for selecting the data or instruction register. The LCD interface makes use of a configurable clock (programmed in the CGU) to adjust the speed of the 6800/8080 bus to the speed of the connected peripheral. 6.20.1 Features • • • • • • 8-bit or 4-bit parallel interface mode: 6800-series, 8080-series. Selectable bus frequency supports high and low speed LCD controllers. Supports polling the busy flag from the LCD controller to avoid CPU polling. Contains a 16 B FIFO for sending control and data information to the LCD controller. Contains a serial interface which uses the same FIFO for serial transmissions. Supports FIFO level flow control to the General Purpose DMA controller. 6.21 Clocking and power control Clocking in the LPC2880/2888 is controlled by a versatile CGU, so that system and peripheral requirements may be met while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed, and may be enabled and disabled by selected events through the Event Router. Clock sources include a high frequency (1 MHz to 20 MHz) crystal oscillator and a 32 kHz RTC oscillator. Higher frequency clocks may be generated through the use of two programmable PLLs. Reset of individual functional blocks is also controlled by the CGU. Full chip reset can be initiated by the external reset pin or by the watchdog timer. 6.21.1 Features • Power and performance control provided by versatile clock generation to individual functional blocks. • Multiple clock sources including external crystal and programmable PLLs. • Individual control of software reset to many functional blocks. 6.21.2 Reset The LPC2880/2888 has two sources of reset: the RESET pin and the watchdog reset. The RESET pin includes an on-chip pull-up. RESET must remain low at power-up for 1 ms after power supply voltages are stable. This includes on-chip DC-to-DC converter voltages. When either reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 23 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface The on-chip watchdog timer can cause a chip reset if not updated within a programmable time interval. A status register allows software to determine if a reset was caused by the watchdog timer. The watchdog timer can also be configured to generate an interrupt if desired. Software reset of many individual functional blocks may be performed via registers within the CGU. 6.21.3 Crystal oscillator The main oscillator is the basis for the clocks most chip functions use by default. The oscillator may be used with crystal frequencies from 1 MHz to 20 MHz. 6.21.4 PLLs The LPC2880/2888 includes two PLLs: the main PLL provides clocks to most chip functions, and a high-speed PLL that can be used to generate faster clocks for selected chip functions. Each PLL can be driven from several clock sources. These include the main oscillator (1 MHz to 20 MHz), the RTC oscillator (32 kHz), the bit clock or word select inputs of the I2S input channel, the clock input from the SD/MMC card interface, or the output clock from the other PLL. The low power PLL takes the input clock and multiplies it up to a higher frequency (by 1 to 32), then divides it down (by 1, 2, 4, or 8) to provide the output clock used by the CGU. The output frequency of this PLL can range from 10 MHz to 320 MHz. Functional blocks may have limitations below this upper limit. The high-speed PLL takes the input clock, optionally divides it down (by 1 to 256), then multiplies it up to a higher frequency (by 1 to 1024), then divides it down (by 1 to 16) to provide the output clock used by the CGU. The output frequency of this PLL can range from 4.3 MHz to 550 MHz. Functional blocks may have limitations below this upper limit. 6.21.5 Power control and modes Power control on the LPC2880/2888 is accomplished by detailed control over the clocking of each functional block via the CGU. The LPC2880/2888 includes a very versatile clocking scheme that provides a great deal of control over performance and power usage. On-chip functions are divided into 11 groups. Each group has a selection for one of several basic clock sources. Graceful (glitch-free) switching between these clock sources is provided. Three of these functional groups include one fractional divider that allows any rate below the selected clock to be derived. Three other functional groups include more than one fractional divider, allowing several different slower clocks to be generated within the group. Each function within the group can then be assigned to use any one of the generated clocks. Each function within any group can also be individually turned off by disabling the clock to that function. When added to the versatile clock rate selection, this allows very detailed control of power utilization. Each function also can be configured to have clocks automatically turned on and off based on a signal from the Event Router. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 24 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 6.21.6 APBs Most peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APBs perform reads and writes to peripheral registers in three peripheral clocks. 6.22 Emulation and debugging The LPC2880/2888 supports emulation via a dedicated JTAG serial port. The dedicated JTAG port allows debugging of all chip features without impact to any pins that may be used in the application. Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 25 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDD(EMC) VIA VI IDD ISS Tstg Ptot(pack) Vesd Parameter supply voltage (1.8 V) supply voltage (3.3 V) external memory controller supply voltage analog input voltage input voltage input voltage supply current ground current storage temperature total power dissipation (per package) electrostatic discharge voltage human body model all pins [1] [5] Conditions Min −0.5 −0.5 Max +1.95 +4.6 +1.95 +3.6 VDD(ADC3V3) +6.0 VDD + 0.5 100 100 +125 1.5 Unit V V V V V V V mA mA °C W in 1.8 V range in 3.3 V range 5 V tolerant pins other pins per supply pin per ground pin [2][4] [2][3][4] −0.5 −0.5 −0.5 −0.5 −0.5 −40 - [6] −1000 +1000 V The following applies to Table 5: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. All inputs are 5 V tolerant except external memory bus and USB pins. Referenced to the applicable VDD for the pin. Not to exceed 4.6 V. Including voltage on outputs in 3-state mode. Based on package heat transfer, not device power consumption. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. [2] [3] [4] [5] [6] LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 26 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface 8. Static characteristics Table 6. Static characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) VDDA(3V3) VDD(EMC) Parameter supply voltage (1.8 V) supply voltage (3.3 V) analog supply voltage (3.3 V) external memory controller supply voltage in 1.8 V range in 3.3 V range VI = 0 V; no pull-up VI = VDD; no pull-down VO = 0 V; VO = VDD; no pull-up/down −(1.5VDD) < VI < (1.5VDD) [6] [6] Conditions [2] [3] [4] [5] [5] Min 1.7 3 3 1.7 2.7 300 [6] [6][7] [6][7][10] Typ[1] 1.8 3.3 3.3 1.8 3.3 - Max 1.95 3.6 3.6 1.95 3.6 1 1 1 100 VDD 5.5 0.6 0.8 0.4 0.4 −50 75 1.5 0.4 4 22 Unit V V V V V µA µA µA mV mA V V V V V V V V V V mA mA mA mA µA µA µA V V mV V µA µA Standard pins IIL IIH IOZ Vhys(i) Ilatch VI VIH VIL VOH VOL IOH IOL IOHS IOLS Ipu Ipd I2C-bus VIH VIL Vhys(i) VOL ILI pins HIGH-level input voltage LOW-level input voltage input hysteresis voltage LOW-level output voltage input leakage current IOL = 3 mA VI = VDD VI = 5 V [6] LOW-level input current HIGH-level input current OFF-state output current input hysteresis voltage I/O latch-up current input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current LOW-level short-circuit output current pull-up current pull-down current 0 0 1.6 2.0 - [8] [9] [8] [9] IOH = −1 mA IOH = −4 mA IOL = 4 mA IOL = 4 mA VOH = VDD − 0.4 V VOL = 0.4 V VOH = 0 V VOL = VDD VI = 0 V VDD < VI < 5.5 V VI = VDD [8][11] [9][11] [8][11] [9][11] [6][11] [6][11] [12] VDD − 0.4 VDD − 0.4 −13 20 3.5 250 −4 4 −45 50 −36 0 50 2 10 [6][12] [6] [6][10] [6] LPC2880_LPC2888_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 17 April 2008 27 of 43 NXP Semiconductors LPC2880; LPC2888 16/32-bit ARM microcontrollers with external memory interface Table 6. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Vi(xtal) Vo(xtal) VBAT VO(DCDC1) Parameter crystal input voltage crystal output voltage battery supply voltage DC-to-DC converter 1 output voltage VBAT = 1.2 V; IL(DCDC1)(max) = 100 mA Conditions on pins XTALI and X32I on pins XTALO and X32O Min 0 0 0.9 VBAT = 1.2 V; IL(DCDC2)(max) = 90 mA 4.0 VUSB = 5.0 V; IL(LDO1)(max) = 150 mA VUSB = 5.0 V; IL(LDO2)(max) = 100 mA VDD = 1.8 V VDD(EMC) = 1.8 V; HCLK = 18 MHz VDD(EMC) = 3.3 V; HCLK = 36 MHz IBAT ICC(osc) IDD(RTC) IDD(ADC) IDDIA IDDO(DAC) battery supply current oscillator supply current RTC supply current ADC supply current analog input supply current DAC output supply current VDCDC_VBAT = 1.2 V powered down oscillator running oscillator powered down oscillator running oscillator powered down normal powered down normal powered down normal powered down [15] [15] [16] [16] [17] [17] [18] [18] [19] [19] [13] [14] Typ[1] 1.2 3.2 100 12 1.83 90 12 5.0 3.4 150 1.88 100 60 1.2 2.2 130 18 300 300 6 10 0.7 10 Max 1.8 1.8 1.6 5.5 10 10 400