LPC3131FET180

LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 1 — 9 February 2009 Preliminary data sheet 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3130/3131 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. 2. Features 2.1 Key features I CPU platform N 180 MHz, 32-bit ARM926EJ-S N 16 kB D-cache and 16 kB I-cache N Memory Management Unit (MMU) I Internal memory N 96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM I External memory interface N NAND flash controller with 8-bit ECC N 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM I Communication and connectivity N High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY N Two I2S-bus interfaces N Integrated master/slave SPI N Two master/slave I2C-bus interfaces N Fast UART N Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA N Four-channel 10-bit ADC N Integrated 4/8/16-bit 6800/8080 compatible LCD interface I System functions N Dynamic clock gating and scaling N Multiple power domains N Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB N DMA controller N Four 32-bit timers N Watchdog timer NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers N PWM module N Random Number Generator (RNG) N General Purpose I/O (GPIO) pins N Flexible and versatile interrupt structure N JTAG interface with boundary scan and ARM debug access I Operating voltage and temperature N Core voltage: 1.2 V N I/O voltage: 1.8 V, 2.8 V, 3.3 V N Temperature: −40 °C to +85 °C I TFBGA180 package: 12 × 12 mm2, 0.8 mm pitch 3. Ordering information Table 1. Ordering information Package Name Description Version Type number LPC3130FET180 TFBGA180 plastic thin fine pitch ball grid array package, 180 balls, body 12 × 12 × 0.8 mm SOT570-3 LPC3131FET180 TFBGA180 plastic thin fine pitch ball grid array package, 180 balls, body 12 × 12 × 0.8 mm SOT570-3 Table 2. Ordering options for LPC3130/3131 Core/bus frequency 180 MHz/ 90 MHz 180 MHz/ 90 MHz Total SRAM 96 kB High-speed USB Device/ Host/OTG 10-bit ADC channels 4 4 I2S-bus/ I2C-bus 2 each 2 each MCI SDHC/ Temperature SDIO/ range CE-ATA yes yes −40 °C to +85 °C −40 °C to +85 °C Type number LPC3130FET180 LPC3131FET180 192 kB Device/ Host/OTG LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 2 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 4. Block diagram JTAG interface TEST/DEBUG INTERFACE INSTRUCTION CACHE 16 kB DATA CACHE 16 kB LPC3130/3131 ARM926EJ-S DMA CONTROLLER USB 2.0 HIGH-SPEED OTG master slave slave ROM slave 96 kB ISRAM0 slave master slave INTERRUPT CONTROLLLER slave master master MPMC slave MULTILAYER AHB MATRIX slave 96 kB ISRAM1(1) NAND CONTROLLER BUFFER slave MCI SD/SDIO slave AHB TO APB BRIDGE 0 ASYNC APB slave group 0 WDT SYSTEM CONTROL CGU slave AHB TO APB BRIDGE 1 ASYNC slave AHB TO APB BRIDGE 2 ASYNC slave AHB TO APB BRIDGE 3 ASYNC slave AHB TO APB BRIDGE 4 SYNC APB slave group 4 NAND REGISTERS DMA REGISTERS APB slave group 3 IOCONFIG I2S0/1 10-bit ADC EVENT ROUTER RANDOM NUMBER GENERATOR APB slave group 1 TIMER 0/1/2/3 PWM I2C0 I2C1 (1) LPC3131 only APB slave group 2 UART LCD SPI PCM 002aae124 Fig 1. LPC3130/3131 block diagram LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 3 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 5. Pinning information 5.1 Pinning ball A1 index area LPC3130/3131 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aae130 Transparent top view Fig 2. Table 3. Row A 1 5 9 13 1 5 9 13 1 5 9 13 1 5 9 13 LPC3130/3131 pinning TFBGA180 package Pin allocation table Pin Symbol 2 6 10 14 2 6 10 14 2 6 10 14 2 6 10 14 EBI_A_1_CLE mGPIO6 FFAST_IN ADC10B_GPA1 VDDE_IOA mGPIO5 FFAST_OUT ADC10B_GPA0 EBI_D_11 VDDI I2C_SDA0 ADC10B_GPA3 EBI_D_6 VSSE_IOC I2C_SCL0 BUF_TMS Pin Symbol 3 7 11 3 7 11 3 7 11 3 7 11 EBI_D_9 SPI_CS_OUT0 VSSI EBI_A_0_ALE SPI_MOSI GPIO3 VSSE_IOA VSSI GPIO4 EBI_D_13 VDDE_IOC VDDA12 Pin Symbol 4 8 12 4 8 12 4 8 12 4 8 12 mGPIO10 SPI_SCK ADC10B_GNDA mNAND_RYBN2 SPI_CS_IN VSSE_IOC VSSE_IOA SPI_MISO VDDI mNAND_RYBN3 VSSE_IOC VSSI - Pin Symbol EBI_D_10 mGPIO7 VDDI ADC10B_VDDA33 EBI_D_8 mGPIO8 PWM_DATA ADC10B_GPA2 EBI_D_7 mGPIO9 VDDI VDDE_IOC EBI_D_5 VDDE_IOC VSSE_IOC BUF_TCK Row B Row C Row D LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 4 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 3. Row E 1 5 9 13 1 5 13 1 5 13 1 5 13 1 5 13 1 5 9 13 1 5 9 13 1 5 9 13 1 5 9 13 Pin allocation table …continued Pin Symbol 2 6 10 14 2 10 14 2 10 14 2 10 14 2 10 14 2 6 10 14 2 6 10 14 2 6 10 14 2 6 10 14 EBI_D_4 mNAND_RYBN0 VDDA12 I2STX_BCK1 EBI_D_1 SCAN_TDO I2SRX_BCK1 EBI_D_0 I2STX_WS1 I2SRX_DATA1 EBI_NRAS_BLOUT_1 GPIO12 RSTIN_N EBI_NWE GPIO1 GPIO14 NAND_NCS_3 mLCD_DB_6 GPIO0 GPIO18 USB_VBUS VSSI VDDE_IOC GPIO2 USB_VDDA33_DRV VSSE_IOB I2SRX_DATA0 TCK USB_DM mLCD_DB_2 I2SRX_BCK0 mI2STX_CLK0 Pin Symbol 3 7 11 3 11 3 11 3 11 3 11 3 7 11 3 7 11 3 7 11 3 7 11 EBI_D_14 mNAND_RYBN1 ARM_TDO EBI_D_15 BUF_TRST_N EBI_D_12 VSSE_IOC VDDI GPIO19 NAND_NCS_1 GPIO16 VSSE_IOA mLCD_DB_10 VDDE_ESD USB_VSSA_TERM VDDI VSSI VSSE_IOB VDDE_IOB mI2STX_WS0 mLCD_DB_15 mLCD_DB_4 JTAGSEL Pin Symbol 4 8 12 4 12 4 12 4 12 4 12 4 8 12 4 8 12 4 8 12 4 8 12 VSSE_IOA VDDE_IOC I2C_SDA1 VSSE_IOA I2STX_DATA1 VSSI VDDE_IOC VSSE_IOA CLK_256FS_O CLOCK_OUT GPIO13 USB_VSSA_REF mLCD_CSB GPIO17 VDDE_IOB mLCD_E_RD VDDI VSSE_IOB VSSE_IOB mI2STX_BCK0 mLCD_DB_11 mLCD_DB_0 UART_TXD © NXP B.V. 2009. All rights reserved. Pin Symbol EBI_D_3 VDDE_IOA VSSA12 I2C_SCL1 EBI_D_2 VDDE_IOA I2SRX_WS1 EBI_NCAS_BLOUT_0 VDDE_IOA SYSCLK_O EBI_DQM_0_NOE VDDE_IOA GPIO11 NAND_NCS_0 USB_RREF GPIO15 NAND_NCS_2 mLCD_DB_12 TDI GPIO20 USB_VDDA12_PLL mLCD_DB_9 VSSE_IOC VSSE_IOC USB_ID VDDE_IOB VDDE_IOB mI2STX_DATA0 USB_GNDA mLCD_DB_8 mLCD_RW_WR mUART_CTS_N Row F Row G Row H Row J Row K Row L Row M Row N LPC3130_3131_1 Preliminary data sheet Rev. 1 — 9 February 2009 5 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 3. Row P 1 5 9 13 Pin allocation table …continued Pin Symbol 2 6 10 14 USB_DP mLCD_DB_3 TMS mUART_RTS_N Pin Symbol 3 7 11 mLCD_DB_14 mLCD_DB_5 I2SRX_WS0 Pin Symbol 4 8 12 mLCD_DB_13 mLCD_RS UART_RXD - Pin Symbol USB_VDDA33 mLCD_DB_7 mLCD_DB_1 TRST_N Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin state after reset - Cell Type [2] Description Clock Generation Unit FFAST_IN FFAST_OUT VDDA12 VSSA12 RSTIN_N CLK_256FS_O A10 B10 D11; E10 E9 H14 H12 SUP3 SUP3 SUP1 SUP1 SUP1 AI AO Supply Ground DI DO I O AIO2 AIO2 PS3 CG1 DIO2 DIO1 12 MHz oscillator clock input 12 MHz oscillator clock output 12 MHz oscillator/PLLs Analog supply 12 MHz oscillator/PLLs Analog ground System Reset Input (active LOW) Programmable clock output; fractionally derived from CLK1024FS_BASE clock domain. Generally used for Audio Codec master clock. Programmable clock output; fractionally derived from SYS_BASE clock domain. Programmable clock output. Output one of seven base/reference input clocks. No fractional divider. 10-bit ADC Analog Supply 10-bit ADC Analog Ground 10-bit ADC Analog Input 10-bit ADC Analog Input 10-bit ADC Analog Input 10-bit ADC Analog Input USB supply detection line Indicates to the USB transceiver whether in device (USB_ID HIGH) or host (USB_ID LOW) mode (contains internal pull-up resistor) USB Connection for external reference resistor (12 kΩ ± 1 %) to analog ground supply USB D+ connection with integrated 45 Ω termination resistor USB D− connection with integrated 45 Ω termination resistor © NXP B.V. 2009. All rights reserved. CLOCK_OUT SYSCLK_O[3] J4 G13 SUP3 SUP3 DO DO O O DIO1 DIO1 10-bit ADC ADC10B_VDDA33 ADC10B_GNDA ADC10B_GPA0 ADC10B_GPA1 ADC10B_GPA2 ADC10B_GPA3 USB HS 2.0 OTG USB_VBUS USB_ID L2 M1 SUP5 SUP3 AI AI AIO3 AIO1 A13 A12 B14 A14 B13 C14 SUP3 SUP3 SUP3 SUP3 SUP3 Supply Ground AI AI AI AI PS3 CG1 AIO1 AIO1 AIO1 AIO1 USB_RREF USB_DP USB_DM LPC3130_3131_1 J5 P2 N2 SUP3 SUP3 SUP3 AIO AIO AIO - AIO1 AIO1 AIO1 Preliminary data sheet Rev. 1 — 9 February 2009 6 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin state after reset I I I I I O/Z O O Cell Type [2] Description USB_VDDA12_PLL USB_VDDA33_DRV USB_VDDA33 USB_VSSA_TERM USB_GNDA USB_VSSA_REF JTAG JTAGSEL TDI TRST_N TCK TMS SCAN_TDO ARM_TDO BUF_TRST_N L1 M2 P1 L3 N1 K4 N11 K9 P13 M14 P10 F10 E11 F11 SUP1 SUP3 SUP3 Supply Supply Supply Ground Ground Ground PS3 PS3 PS3 CG1 CG1 CG1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 USB PLL supply USB Analog supply for driver USB Analog supply for PHY USB Analog ground for clean reference for on chip termination resistors USB Analog ground USB Analog ground for clean reference JTAG selection. Controls output function of SCAN_TDO and ARM_TDO signals. JTAG Data Input JTAG Reset Input JTAG Clock Input JTAG Mode Select Input JTAG TDO signal from scan TAP controller. Pin state is controlled by JTAGSEL. JTAG TDO signal from ARM926 TAP controller. Buffered TRST_N out signal. Used for connecting an on board TAP controller (FPGA, DSP, etc.). Buffered TCK out signal. Used for connecting an on board TAP controller (FPGA, DSP, etc.). Buffered TMS out signal. Used for connecting an on board TAP controller (FPGA, DSP, etc.). UART Clear To Send (active LOW) UART Ready To Send (active LOW) UART Serial Input UART Serial Output I2C Data Line I2C Clock line I2C Data Line I2C Clock line SPI Chip Select Output (Master) SPI Clock Input (Slave) / Clock Output (Master) SPI Data Input (Master) / Data Output (Slave) © NXP B.V. 2009. All rights reserved. SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 DI DI DI DI DI DO DO DO BUF_TCK BUF_TMS UART mUART_CTS_N[3][4] mUART_RTS_N[3][4] UART_RXD[3] UART_TXD[3] I2C I2C_SDA0 I2C_SCL0 I2C_SDA1[3] I2C_SCL1[3] SPI_CS_OUT0[3] SPI_SCK[3] SPI_MISO[3] LPC3130_3131_1 D13 D14 SUP3 SUP3 DO DO O O DIO1 DIO1 N13 P14 P12 N12 C10 D10 E12 E13 A7 A8 C8 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 DI / GPIO DO / GPIO DI / GPIO DO / GPIO DIO DIO DIO DIO DO DIO DIO I O I O I I O O O I I DIO1 DIO1 DIO1 DIO1 IICD IICC DIO1 DIO1 DIO4 DIO4 DIO4 master/slave interface Serial Peripheral Interface Preliminary data sheet Rev. 1 — 9 February 2009 7 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin state after reset I I - Cell Type [2] Description SPI_MOSI[3] SPI_CS_IN[3] Digital power supply VDDI B7 B8 H3; L7; L12; C12; C6 A11; C7; D12; G4; L6; L11 B2; E5; F5; G5; H5 L4; M5; M7; M9 SUP3 SUP3 SUP1 DIO DI Supply DIO4 DIO4 CS2 SPI Data Output (Master) / Data Input (Slave) SPI Chip Select Input (Slave) Digital Core Supply VSSI Ground - CG2 Digital Core Ground Peripheral power supply VDDE_IOA SUP4 Supply PS1 Peripheral supply for NAND flash interface VDDE_IOB SUP8 Supply - PS1 Peripheral supply for SDRAM/LCD VDDE_IOC C13; SUP3 D5; D7; E8; G12; L10; K11 C3; C4; E4; F4; H4; K3 M3; M4; M6; M8 SUP8 Supply - PS1 Peripheral supply VDDE_ESD VSSE_IOA Supply Ground - PS1 PG1 VSSE_IOB Ground - PG1 LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 8 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin state after reset - Cell Type [2] Description VSSE_IOC B12; D6; D8; D9; G11; L9; L13 K8 L8 P8 N9 N8 P9 N6 P6 N7 P7 K6 P5 N5 L5 K7 N4 K5 P4 P3 N3 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 SUP8 Ground PG1 LCD Interface mLCD_CSB[3] mLCD_E_RD[3] mLCD_RS[3] mLCD_RW_WR[3] mLCD_DB_0[3] mLCD_DB_1[3] mLCD_DB_2[3] mLCD_DB_3[3] mLCD_DB_4[3] mLCD_DB_5[3] mLCD_DB_6[3] mLCD_DB_7[3] mLCD_DB_8[3] mLCD_DB_9[3] mLCD_DB_10[3] mLCD_DB_11[3] mLCD_DB_12[3] mLCD_DB_13[3] mLCD_DB_14[3] mLCD_DB_15[3] DO DO DO DO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO O O O O O O O O O O O O O O O O O O O O DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 LCD Chip Select (active LOW) LCD, 6800 Enable, 8080 Read Enable (active HIGH) LCD, Instruction Register (LOW)/ Data Register (HIGH) select LCD, 6800 Read/write Select, 8080 Write Enable (active HIGH) LCD Data 0 LCD Data 1 LCD Data 2 LCD Data 3 LCD Data 4 LCD Data 5 LCD Data 6 LCD Data 7 LCD Data 8 / 8-bit Data 0 LCD Data 9 / 8-bit Data 1 LCD Data 10 / 8-bit Data 2 LCD Data 11 / 8-bit Data 3 LCD Data 12 / 8-bit Data 4 / 4-bit Data 0 LCD Data 13 / 8-bit Data 5 / 4-bit Data 1 / Serial Clock Output LCD Data 14 / 8-bit Data 6 / 4-bit Data 2 / Serial Data Input LCD Data 15 / 8-bit Data 7 / 4-bit Data 3 / Serial Data Output LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 9 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin state after reset I I I I I I O O O O O O O I I I I I I I I I I I I I I I I I I I I I Cell Type [2] Description I2S/Digital Audio Input I2SRX_DATA0[3] I2SRX_DATA1[3] I2SRX_BCK0[3] I2SRX_BCK1[3] I2SRX_WS0[3] I2SRX_WS1[3] I2S/Digital Audio Output mI2STX_DATA0[3] mI2STX_BCK0[3] mI2STX_WS0[3] mI2STX_CLK0[3] I2STX_DATA1[3] I2STX_BCK1[3] I2STX_WS1[3] GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 mGPIO5[3] mGPIO6[3] mGPIO7[3] mGPIO8[3] mGPIO9[3] mGPIO10[3] GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 M13 M12 M11 N14 F12 E14 G10 K10 J10 L14 B11 C11 B6 A6 A5 B5 C5 A4 H13 H10 J12 J14 J13 J11 K12 K14 H11 K13 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 DO / GPIO DO / GPIO DO / GPIO DO / GPIO DO / GPIO DO / GPIO DO / GPIO GPIO GPIO GPIO GPIO GPI GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 I2S Serial Data Transmit Output I2S Bitclock I2S Word select I2S Serial Clock I2S Serial Data Transmit Output I2S Bitclock I2S Word select General Purpose I/O Pin 0 (Mode pin 0) General Purpose I/O Pin 1 (Mode pin 1) General Purpose I/O Pin 2 (Mode pin 2) General Purpose I/O Pin 3 General Purpose Input Pin 4 General Purpose I/O Pin 5 General Purpose I/O Pin 6 General Purpose I/O Pin 7 General Purpose I/O Pin 8 General Purpose I/O Pin 9 General Purpose I/O Pin 10 General Purpose I/O Pin 11 General Purpose I/O Pin 12 General Purpose I/O Pin 13 General Purpose I/O Pin 14 General Purpose I/O Pin 15 General Purpose I/O Pin 16 General Purpose I/O Pin 17 General Purpose I/O Pin 18 General Purpose I/O Pin 19 General Purpose I/O Pin 20 M10 G14 N10 F14 P11 F13 SUP3 SUP3 SUP3 SUP3 SUP3 SUP3 DI / GPIO DI / GPIO DIO / GPIO DIO / GPIO DIO / GPIO DIO / GPIO DIO1 DIO1 DIO1 DIO1 DIO1 DIO1 I2S Serial Data Receive Input I2S Serial Data Receive Input I2S Bitclock I2S Bitclock I2S Word select I2S Word select General Purpose I/O (IOCONFIG module) LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 10 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin state after reset O O I I I I I I I I I I I I I I I I O O O O O O I I I I O O O Cell Type [2] Description External Bus Interface (NAND flash controller) EBI_A_0_ALE[3] EBI_A_1_CLE[3] EBI_D_0[3] EBI_D_1[3] EBI_D_2[3] EBI_D_3[3] EBI_D_4[3] EBI_D_5[3] EBI_D_6[3] EBI_D_7[3] EBI_D_8[3] EBI_D_9[3] EBI_D_10[3] EBI_D_11[3] EBI_D_12[3] EBI_D_13[3] EBI_D_14[3] EBI_D_15[3] EBI_DQM_0_NOE[3] EBI_NWE[3] NAND_NCS_0[3] NAND_NCS_1[3] NAND_NCS_2[3] NAND_NCS_3[3] mNAND_RYBN0[3] mNAND_RYBN1[3] mNAND_RYBN2[3] mNAND_RYBN3[3] EBI_NCAS_BLOUT_0[3] EBI_NRAS_BLOUT_1[3] PWM_DATA[3] [1] [2] [3] [4] B3 A2 G2 F2 F1 E1 E2 D1 D2 C1 B1 A3 A1 C2 G3 D3 E3 F3 H1 J2 J1 J3 K1 K2 E6 E7 B4 D4 G1 H2 B9 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP4 SUP3 DO DO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DO DO DO DO DO DO DI DI DI DI DO DO DO / GPIO DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO4 DIO1 EBI Address Latch Enable EBI Command Latch Enable EBI Data I/O 0 EBI Data I/O 1 EBI Data I/O 2 EBI Data I/O 3 EBI Data I/O 4 EBI Data I/O 5 EBI Data I/O 6 EBI Data I/O 7 EBI Data I/O 8 EBI Data I/O 9 EBI Data I/O 10 EBI Data I/O 11 EBI Data I/O 12 EBI Data I/O 13 EBI Data I/O 14 EBI Data I/O 15 NAND Read Enable (active LOW) NAND Write Enable (active LOW) NAND Chip Enable 0 NAND Chip Enable 1 NAND Chip Enable 2 NAND Chip Enable 3 NAND Ready/Busy 0 NAND Ready/Busy 1 NAND Ready/Busy 2 NAND Ready/Busy 3 EBI Lower lane byte select (7:0) EBI Upper lane byte select (15:8) PWM Output Pulse Width Modulation module Digital I/O levels are explained in Table 5. Cell types are explained in Table 6. Pin can be configured as GPIO pin in the IOCONFIG block. The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and SPI_CS_OUT2) © NXP B.V. 2009. All rights reserved. LPC3130_3131_1 Preliminary data sheet Rev. 1 — 9 February 2009 11 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 5. Supply Domain SUP1 SUP3 SUP4 Supply domains Voltage range 1.0 V– 1.3 V 2.7 V - 3.3 V 1.65 V - 1.95 V (in 1.8 V mode) 2.5 V - 3.1 V (in 2.8 V mode) 4.5 V– 5.5 V 1.65 V - 1.95 V (in 1.8 V mode) 2.5 V - 3.1 V (in 2.8 V mode) Related supply pins Description VDDI, VDDA12, USB_VDDA12_PLL, Digital core supply VDDE_IOC, ADC10B_VDDA33, Peripheral supply USB_VDDA33_DRV, USB_VDDA33, VDDE_IOA Peripheral supply for NAND flash interface USB VBUS voltage Peripheral supply for SDRAM/SRAM/bus-based LCD [1] SUP5 SUP8 USB_VBUS VDDE_IOB [1] When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD Interface must be the same, i.e. SUP4 and SUP8 should be connected to the same rail. (See also Section 6.26.3.) Table 6: Cell type DIO1 I/O pads Pad type bspts3chp Function Description Digital Input/Output Bidirectional 3.3 V; 3-state output; 3 ns slew rate control; plain input; CMOS with hysteresis; programmable pull-up, pull-down, repeater Digital Input/Output Bidirectional 5 V; plain input; 3-state output; CMOS with programmable hysteresis; programmable pull-up, pull-down, repeater Digital Input/Output Bidirectional 1.8 V or 2.8 V; plain input; 3-state output; programmable hysteresis; programmable pull-up, pull-down, repeater Digital Input/Output I2C-bus; clock signal Digital Input/Output I2C-bus; data signal Analog Input/Output Analog input/output; protection to external 3.3 V supply rail Analog Input/Output Analog input/output Analog Input/Output Analog input/output; 5 V tolerant pad-based ESD protection Core Supply Core Supply Peripheral Supply Peripheral Supply Core Ground Core Ground Peripheral Ground - DIO2 bpts5pcph DIO4 mem1 bsptz40pchp iic3m4scl iic3mvsda apio3v3 apio apiot5v vddco vddi vdde3v3 vdde vssco vssis vsse IICC IICD AIO1 AIO2 AIO3 CS1 CS2 PS1 PS2 CG1 CG2 PG1 LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 12 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6. Functional description 6.1 ARM926EJ-S The processor embedded in the LPC3130/3131 is the ARM926EJ-S. It is a member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important. This module has the following features: • ARM926EJ-S processor core which uses a five-stage pipeline consisting of fetch, decode, execute, memory, and write stages. The processor supports both the 32-bit ARM and 16-bit Thumb instruction sets, which allows a trade off between high performance and high code density. The ARM926EJ-S also executes an extended ARMv5TE instruction set which includes support for Java byte code execution. • Contains an AMBA BIU for both data accesses and instruction fetches. • Memory Management Unit (MMU). • 16 kB instruction and 16 kB data separate cache memories with an 8 word line length. The caches are organized using Harvard architecture. • Little Endian is supported. • The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debugging. • Supports dynamic clock gating for power reduction. • The processor core clock can be set equal to the AHB bus clock or to an integer number times the AHB bus clock. The processor can be switched dynamically between these settings. • ARM stall support. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 13 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.2 Memory map LPC3130/3131 4 GB 2 GB reserved reserved NAND buffer reserved interrupt controller reserved external SDRAM bank 0 0xFFFF FFFF 0x8000 0000 0x7000 0800 0x7000 0000 0x6000 1000 0x6000 0000 0x4000 0000 0x3000 0000 0x2004 0000 external SRAM bank 1 external SRAM bank 0 reserved USB OTG reserved MCI/SD/SDIO reserved MPMC configuration registers APB4 domain APB3 domain APB2 domain reserved APB1 domain APB0 domain reserved 0x1201 0000 128 kB ISROM reserved 0x1105 8000 96 kB ISRAM1(1) 96 kB ISRAM0 reserved 0 GB shadow area 0x1104 0000 APB0 domain 0x1102 8000 0x0000 1000 0x0000 0000 0x1200 0000 0x2002 0000 0x2000 0000 0x1900 1000 0x1900 0000 0x1800 0900 0x1800 0000 0x1700 9000 0x1700 8000 0x1700 0000 0x1600 0000 0x1500 0000 0x1300 B000 0x1300 8000 0x1300 0000 APB1 domain APB2 domain APB3 domain I2SRX_1 I2SRX_0 I2STX_1 I2STX_0 I2S system config reserved SPI UART reserved LCD PCM I2C1 I2C0 PWM TIMER 3 TIMER 2 TIMER 1 TIMER 0 RNG reserved CGU IOCONFIG NAND flash controller DMA reserved 0x1600 0280 0x1600 0200 0x1600 0180 0x1600 0100 0x1600 0080 0x1600 0000 0x1500 3000 0x1500 2000 0x1500 1000 0x1500 0800 0x1500 0400 0x1500 0000 0x1300 B000 0x1300 A400 0x1300 A000 0x1300 9000 0x1300 8C00 0x1300 8800 0x1300 8400 0x1300 8000 0x1300 6000 0x1300 5000 0x1300 4000 APB4 domain reserved 0x1700 1000 0x1700 0800 0x1700 0000 0x1700 8000 0x1300 3000 SYSCONFIG register 0x1300 2800 WDT 0x1300 2400 ADC 10 bit 0x1300 2000 event router 0x1300 0000 002aae125 (1) LPC3131 only. Fig 3. LPC3130/3131 memory map LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 14 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.3 JTAG The Joint Test Action Group (JTAG) interface allows the incorporation of the LPC3130/3131 in a JTAG scan chain. This module has the following features: • ARM926 debug access • Boundary scan 6.4 NAND flash controller The NAND flash controller is used as a dedicated interface to NAND flash devices. Figure 4 shows a block diagram of the NAND flash controller module. The heart of the module is formed by a controller block that controls the flow of data from/to the AHB bus through the NAND flash controller block to/from the (external) NAND flash. An error correction encoder/decoder (ECC enc/dec) module allows for hardware error correction for support of Multi-Level Cell (MLC) NAND flash devices. Before data is written from the buffer to the NAND flash, optionally it is first protected by an error correction code generated by the ECC module. After data is read from the NAND flash, the error correction module corrects any errors. AHB MULTILAYER MATRIX BUFFER CONTROLLER DMA transfer request ECC ENCODER/ DECODER NAND INTERFACE 002aae127 Fig 4. Block diagram of the NAND flash controller This module has the following features: • Dedicated NAND flash interface with hardware controlled read and write accesses. • Wear leveling support with 516 byte mode. • Software controlled command and address transfers to support wide range of flash devices. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 15 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers • • • • • • Software control mode where the ARM is directly master of the flash device. Support for 8 bit and 16 bit flash devices. Support for any page size from 0.5 kB upwards. Programmable NAND flash timing parameters. Support for up to 4 NAND devices. Error Correction Module (ECC) for MLC NAND flash support: – Reed-Solomon error correction encoding and decoding. – Uses Reed-Solomon code words with 9-bit symbols over GF(29), a total codeword length of 469 symbols, including 10 parity symbols, giving a minimum Hamming distance of 11. – Up to 8 symbol errors can be corrected per codeword. – Error correction can be turned on and off to match the demands of the application. – Parity generator for error correction encoding. – Wear leveling information can be integrated into protected data. – Interrupts generated after completion of error correction task with 3 interrupt registers. – Error correction statistics distributed to ARM using interrupt scheme. – Interface is compatible with the ARM External Bus Interface (EBI). 6.5 Multi-Port Memory Controller (MPMC) The multi-port memory controller supports the interface to different memory types, for example: • SDRAM • Low-power SDRAM • Static memory interface This module has the following features: • Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM. • Address line supporting up to 128 MB of dynamic memory. • The MPMC has two AHB interfaces: a. an interface for accessing external memory. b. a separate control interface to program the MPMC. This enables the MPMC registers to be situated in memory with other system peripheral registers. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance, particularly for un-cached processors. • Static memory features include: – asynchronous page mode read – programmable wait states – bus turnaround delay – output enable and write enable delays LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 16 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers – extended wait • One chip select for synchronous memory and two chip selects for static memory devices. • • • • • • Power-saving modes. Dynamic memory self-refresh mode supported. Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts. Support for all AHB burst types. Little and big-endian support. Support for the External Bus Interface (EBI) that enables the memory controller pads to be shared. 6.6 External Bus Interface (EBI) The EBI module acts as multiplexer with arbitration between the NAND flash and the SDRAM/SRAM memory modules connected externally through the MPMC. The main purpose for using the EBI module is to save external pins. However only data and address pins are multiplexed. Control signals towards and from the external memory devices are not multiplexed. Table 7. Module External SRAM0 External SRAM1 Memory map of the external SRAM/SDRAM memory modules Maximum address space 0x2000 0000 0x2000 0000 0x2002 0000 0x2002 0000 External SDRAM0 0x3000 0000 0x2000 FFFF 0x2001 FFFF 0x2002 FFFF 0x2003 FFFF 0x37FF FFFF Data width 8 bit 16 bit 8 bit 16 bit 16 bit Device size 64 kB 128 kB 64 kB 128 kB 128 MB 6.7 Internal ROM Memory The internal ROM memory is used to store the boot code of the LPC3130/3131. After a reset, the ARM processor will start its code execution from this memory. The LPC3130/3131 ROM memory has the following features: • Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and USB (DFU class) interfaces. • Supports option to perform CRC32 checking on the boot image. • Supports booting from managed NAND devices such as moviNAND, iNAND, eMMC-NAND and eSD-NAND using SD/MMC boot mode. • Contains pre-defined MMU table (16 kB) for simple systems. The boot ROM determines the boot mode based on reset state of GPIO0, GPIO1, and GPIO2 pins. Table 8 shows the various boot modes supported on the LPC3130/3131: LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 17 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers LPC3130/3131 boot modes GPIO0 GPIO1 GPIO2 Description 0 0 0 0 0 1 Boots from NAND flash. If proper image is not found, boot ROM will switch to DFU boot mode. Boot from SPI NOR flash connected to SPI_CS_OUT0. If proper image is not found, boot ROM will switch to DFU boot mode. Device boots via USB using DFU class specification. Boot ROM searches all the partitions on the SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image. If partition table is missing, it will start searching from sector 0. A valid image is said to be found if a valid image header is found, followed by a valid image. If a proper image is not found, boot ROM will switch to DFU boot mode. Reserved for testing. Boot from parallel NOR flash connected to EBI_NSTCS_1. Boot ROM tries to download boot image from UART ((115200 – 8 – n -1) assuming 12 MHz FFAST clock). Boot ROM is testing ISRAM using memory pattern test. After test switches to UART boot mode. Table 8. NAND SPI Boot mode DFU SD/MMC 0 0 1 1 0 1 Reserved 0 NOR flash UART Test 1 1 1 1 0 0 1 1 0 1 0 1 6.8 Internal RAM memory The ISRAM (Internal Static RAM Memory) controller module is used as controller between the AHB bus and the internal RAM memory. The internal RAM memory can be used as working memory for the ARM processor and as temporary storage to execute the code that is loaded by boot ROM from external devices such as SPI-flash, NAND flash, and SD/MMC cards. This module has the following features: • Capacity of 96 kB (LPC3130) or 192 kB (LPC3131) • On LPC3131 implemented as two independent 96 kB memory banks 6.9 Memory Card Interface (MCI) The MCI controller interface can be used to access memory cards according to the Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives. This module has the following features: • • • • • • LPC3130_3131_1 One 8-bit wide interface. Supports high-speed SD, versions 1.01, 1.10 and 2.0. Supports SDIO version 1.10. Supports MMCplus, MMCmobile and MMCmicro cards based on MMC 4.1. Supports SDHC memory cards. CRC generation and checking. © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 18 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers • • • • • • • • • • Supports 1/4-bit SD cards. Card detection and write protection. FIFO buffers of 16 bytes deep. Host pull-up control. SDIO suspend and resume. 1 to 65 535 bytes blocks. Suspend and resume operations. SDIO Read-wait. Maximum clock speed of 52 MHz (MMC 4.1). Supports CE-ATA 1.1: – 8 bit data width – Including ATA module 6.10 High-speed Universal Serial Bus 2.0 On-The-Go (OTG) The USB OTG module allows the LPC3130/3131 to connect directly to a USB host such as a PC (in device mode) or to a USB device in host mode. In addition, the LPC3130/3131 has a special, built-in mode in which it enumerates as a Device Firmware Upgrade (DFU) class, which allows for a (factory) download of the device firmware through USB. This module has the following features: • • • • • • • Complies with Universal Serial Bus specification 2.0. Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals. Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. • Contains UTMI+ compliant transceiver (PHY). • Supports interrupts. • This module has its own, integrated DMA engine. 6.11 DMA controller The DMA Controller can perform DMA transfers on the AHB bus without using the CPU. This module has the following features: • Supported transfer types: Memory to memory: – Memory can be copied from the source address to the destination address with a specified length, while incrementing the address for both the source and destination. Memory to peripheral: LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 19 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers – Data is transferred from incrementing memory to a fixed address of a peripheral. The flow is controlled by the peripheral. Peripheral to memory: – Data is transferred from a fixed address of a peripheral to incrementing memory. The flow is controlled by the peripheral. • Supports single data transfers for all transfer types. • Supports burst transfers for memory to memory transfers. A burst always consists of multiples of 4 (32 bit) words. • The DMA controller has 12 channels. • Scatter-gather is used to gather data located at different areas of memory. Two channels are needed per scatter-gather action. • Supports byte, half word and word transfers, and correctly aligns it over the AHB bus. • Compatible with ARM flow control for single requests (sreq), last single requests (lsreq), terminal count info (tc), and dma clearing (clr). • Supports swapping in endianess of the transported data. Table 9: Peripherals that support DMA access Supported Transfer Types Memory to memory Memory to peripheral and peripheral to memory Memory to peripheral and peripheral to memory Memory to peripheral Memory to peripheral and peripheral to memory Memory to peripheral and peripheral to memory Peripheral to memory Memory to peripheral Memory to peripheral and peripheral to memory Peripheral name NAND flash controller SPI MCI LCD interface UART I2C0/1-bus master/slave I2S0/1 receive I2S0/1 transmit PCM interface 6.12 Interrupt controller (INTC) The interrupt controller collects interrupt requests from multiple devices, masks interrupt requests, and forwards the combined requests to the processor. The interrupt controller also provides facilities to identify the interrupt requesting devices to be served. This module has the following features: • The interrupt controller decodes all the interrupt requests issued by the on-chip peripherals. • Two interrupt lines (Fast Interrupt Request (FIQ), Interrupt Request (IRQ)) to the ARM core. The ARM core supports two distinct levels of priority on all interrupt sources, FIQ for high priority interrupts and IRQ for normal priority interrupts. • • • • LPC3130_3131_1 Software interrupt request capability associated with each request input. Visibility of the interrupt’s request state before masking. Support for nesting of interrupt service routines. Interrupts routed to IRQ and to FIQ are vectored. © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 20 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers • Level interrupt support. The following blocks can generate interrupts: • • • • • • • • • • • • • NAND flash controller USB 2.0 high-speed OTG Event router 10-bit ADC UART LCD MCI SPI I2C0 and I2C1 controllers Timer0, Timer1, Timer2, and Timer3 I2S transmit: I2STX_0 and I2STX_1 I2S receive: I2SRX_0 and I2SRX_1 DMA 6.13 Multi-layer AHB The multi-layer AHB is an interconnection scheme based on the AHB protocol that enables parallel access paths between multiple masters and slaves in a system. Multiple masters can have access to different slaves at the same time. Figure 5 gives an overview of the multi-layer AHB configuration in the LPC3130/3131. AHB masters and slaves are numbered according to their AHB port number. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 21 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers D-CACHE I-CACHE DMA ARM 926EJ-S USB-OTG AHB MASTER masters 0 1 2 3 slaves 0 asynchronous bridge AHB-APB BRIDGE 0 0 EVENT ROUTER 1 10-bit ADC 2 WDT 6 asynchronous bridge RNG 3 SYSTEM CONTROL 5 IOCONFIG 4 CGU 1 AHB-APB BRIDGE 1 asynchronous bridge 0 TIMER 0 1 TIMER 1 2 TIMER 2 3 TIMER 3 4 PWM 5 6 I2C0 I2C0 2 AHB-APB BRIDGE 2 asynchronous bridge 0 PCM 1 LCD 2 UART 3 SPI 3 AHB-APB BRIDGE 3 synchronous bridge AHB-APB BRIDGE 4 0 I2S0/1 4 0 DMA REGISTERS 1 NAND REGISTERS 5 INTERRUPT CONTROLLER NAND CONTROLLER BUFFER 6 7 MCI SD/SDIO 8 9 USB HIGH-SPEED OTG ISRAM 0 ISRAM 1(1) 10 11 12 13 AHB MULTILAYER MATRIX = master/slave connection supported by matrix ISROM MPMC CONFIG MPMC CONTROLLER 002aae126 (1) LPC3131 only. Fig 5. LPC3130/3131 multi-layer AHB matrix connections This module has the following features: LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 22 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). • Round-robin priority mechanism for bus arbitration: all masters have the same priority and get bus access in their natural order • Four devices on a master port (listed in their natural order for bus arbitration): – DMA – ARM926 instruction port – ARM926 data port – USB OTG • Devices on a slave port (some ports are shared between multiple devices): – AHB to APB Bridge 0 – AHB to APB Bridge 1 – AHB to APB Bridge 2 – AHB to APB Bridge 3 – AHB to APB Bridge 4 – Interrupt Controller – NAND flash controller – MCI SD/SDIO – USB 2.0 high-speed OTG – 96 kB ISRAM – 96 kB ISRAM (LPC3131 only) – 128 kB ROM – MPMC 6.14 APB bridge The APB bridge is a bus bridge between the AMBA Advanced High-performance Bus (AHB) and the ARM Peripheral Bus (APB) interface. The module supports two different architectures: • Single-clock architecture, synchronous bridge. The same clock is used at the AHB side and at the APB side of the bridge. The AHB-to-APB4 bridge uses this architecture. • Dual-clock architecture, asynchronous bridge. Different clocks are used at the AHB side and at the APB side of the bridge. The AHB-to-APB0, AHB-to-APB1, AHB-to-APB2, and AHB-to-APB3 bridges use this architecture. 6.15 Clock Generation Unit (CGU) The clock generation unit generates all clock signals in the system and controls the reset signals for all modules. The structure of the CGU is shown in Figure 6. Each output clock generated by the CGU belongs to one of the domains. Each clock domain is fed by a single base clock that originates from one of the available clock sources. Within a clock domain, fractional dividers are available to divide the base clock to a lower frequency. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 23 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Within most clock domains, the output clocks are again grouped into one or more subdomains. All output clocks within one subdomain are either all generated by the same fractional divider or they are connected directly to the base clock. Therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock. The CGU reference clock is generated by the external crystal. In addition, the CGU has several Phase Locked Loop (PLL) circuits to generate clock signals that can be used for system clocks and/or audio clocks. All clock sources, except the output of the PLLs, can be used as reference input for the PLLs. This module has the following features: • Advanced features to optimize the system for low power: – All output clocks can be disabled individually for flexible power optimization. – Some modules have automatic clock gating. They are only active when bus access to the module is required. – Variable clock scaling for automatic power optimization of the AHB bus (high clock frequency when the bus is active, low clock frequency when the bus is idle). – Clock wake-up feature: module clocks can be programmed to be activated automatically on the basis of an event detected by the event router (see also Section 6.19). For example, all clocks (including the ARM /bus clocks) are off and activated automatically when a button is pressed. • Supports five clock sources: – Reference clock generated by the oscillator with an external crystal. – Pins I2SRX_BCK0, I2SRX_WS0, I2SRX_BCK1 and I2SRX_WS1 are used to input external clock signals (used for generating audio frequencies in I2SRX slave mode, see also Section 6.4). • Supports two PLLs: – System PLL generates programmable system clock frequency from its reference input. – I2S PLL generates programmable audio clock frequency (typically 256 × fs) from its reference input. Remark: Both the System PLL and the I2S PLL generate their frequencies based on their (individual) reference clocks. The reference clocks can be programmed to the oscillator clock or one of the external clock signals. • Highly flexible switchbox to distribute the signals from the clock sources to the module clocks: – Each clock generated by the CGU is derived from one of the base clocks and optionally divided by a fractional divider. – Each base clock can be programmed to have any one of the clock sources as an input clock. – Fractional dividers can be used to divide a base clock by a fractional number to a lower clock frequency. – Fractional dividers support clock stretching to obtain a (near) 50 % duty cycle output clock. • Register interface to reset all modules under software control. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 24 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers • Based on the input of the Watchdog timer (see also Section 6.16), the CGU can generate a system-wide reset in the case of a system stall. clock resources subdomain clocks clock outputs BASE EXTERNAL CRYSTAL OSCILLATOR FRACTIONAL DIVIDER 0 I2SRX_BCK0 I2SRX_WS0 I2SRX_BCK1 I2SRX_WS1 FRACTIONAL DIVIDER m SYSTEM PLL CLOCK DOMAIN 0 to modules I2S/AUDIO PLL CLOCK DOMAIN n SWITCHBOX 002aae085 The LPC3130/3131 has 11 clock domains (n = 11). The number of fractional dividers m depends on the clock domain. Fig 6. CGU block diagram 6.16 Watchdog Timer (WDT) The watchdog timer can be used to generate a system reset if there is a CPU/software crash. In addition, the watchdog timer can be used as an ordinary timer. Figure 7 shows how the watchdog timer module is connected in the system. This module has the following features: • In the event of a software or hardware failure, generates a chip-wide reset request when its programmed time-out period has expired (output m1). • Watchdog counter can be reset by a periodical software trigger. • After a reset, a register will indicate whether a reset has occurred because of a watchdog generated reset. • Watchdog timer can also be used as a normal timer (output m0). LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 25 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers m0 APB WDT m1 EVENT ROUTER CGU INTERRUPT CONTROLLER reset FIQ IRQ 002aae086 Fig 7. Block diagram of the Watchdog timer 6.17 Input/Output configuration module (IOCONFIG) The General Purpose Input/Output (GPIO) pins can be controlled through the register interface provided in the IOCONFIG module. Next to several dedicated GPIO pins, most digital I/O pins can also be used as GPIO if they are not required for their normal, dedicated function. This module has the following features: • Provides control for the digital pins that can double as GPIO (next to their normal function). The pinning list in Table 4 indicates which pins can double as GPIO. • Each pin controlled by the IOCONFIG can be configured for four operational modes: – Normal operation (i.e. controlled by a function block). – Driven LOW. – Driven HIGH. – High impedance/input. • The GPIO pins can be observed (read) in any mode. • The register interface provides set and clear access methods for choosing the operational mode. 6.18 10-bit Analog-to-Digital Converter (ADC10B) This module is a 10-bit successive approximation Analog-to-Digital Converter (ADC) with an input multiplexer to allow for multiple analog signals on its input. A common use of this module is to read out multiple keys on one input from a resistor network. This module has the following features: • Four analog input channels, selected by an analog multiplexer. • Programmable ADC resolution from 2 bit to 10 bit. • The maximum conversion rate is 400 ksample/s for 10 bit resolution and 1500 ksample/s for 2 bit resolution. • Single A/D conversion scan mode and continuous A/D conversion scan mode. • Power-down mode. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 26 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake up the system from suspend mode (with all clocks deactivated). interrupt 0 interrupt 1 APB EVENT ROUTER interrupt 2 interrupt 3 cgu wakeup CGU INTERRUPT CONTROLLER external pins internal input signals (GPIO configurable) 002aae087 Fig 8. Event router block diagram The event router has four interrupt outputs connected to the interrupt controller and one wake-up output connected to the CGU as shown in Figure 8. The output signals are activated when an event (for instance a rising edge) is detected on one of the input signals. The input signals of the event router are connected to relevant internal control signals in the system or to external signals through pins of the LPC3130/3131. This module has the following features: • Provides programmable routing of input events to multiple outputs for use as interrupts or wake up signals. • Input events can come from internal signals or from the pins that can be used as GPIO. • • • • • • • • • Inputs can be used either directly or latched (edge detected) as an event source. The active level (polarity) of the input signal for triggering events is programmable. Direct events will disappear when the input becomes inactive. Latched events will remain active until they are explicitly cleared. Each input can be masked globally for all inputs at once. Each input can be masked for each output individually. Event detect status can be read for each output separately. Event detection is fully asynchronous (no active clock required). Module can be used to generate a system wake-up from suspend mode. Remark: All pins that can be used as GPIO are connected to the event router (see Figure 8). Note that they can be used to trigger events when in normal functional mode or in GPIO mode. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 27 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.20 Random number generator The Random Number Generator (RNG) generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. This module has the following features: • True random number generator. • The random number register does not rely on any kind of reset. • The generators are free running in order to ensure randomness and security. 6.21 Serial Peripheral Interface (SPI) The SPI module is used for synchronous serial data communication with other devices which support the SPI/SSI protocol. Examples are memories, cameras, or WiFi-g. The SPI/SSI-bus is a 5-wire interface, and it is suitable for low, medium, and high data rate transfers. This module has the following features: • Supports Motorola SPI frame format with a word size of 8/16 bits. • Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size of 4 bit to 16 bit. • • • • • • • • Receive FIFO and transmit FIFO of 64 half-words each. Serial clock rate master mode maximum 45 MHz. Serial clock rate slave mode maximum 25 MHz. Support for single data access DMA. Full-duplex operation. Supports up to three slaves. Supports maskable interrupts. Supports DMA transfers. 6.22 Universal Asynchronous Receiver Transmitter (UART) The UART module supports the industry standard serial interface. This module has the following features: • • • • • • • • • LPC3130_3131_1 Programmable baud rate with a maximum of 1049 kBd. Programmable data length (5 bit to 8 bit). Implements only asynchronous UART. Transmit break character length indication. Programmable one to two stops bits in transmission. Odd/Even/Force parity check/generation. Frame error, overrun error and break detection. Automatic hardware flow control. Independent control of transmit, receive, line status, data set interrupts, and FIFOs. © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 28 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers • SIR-IrDA encoder/decoder (from 2400 to 115 kBd). • Supports maskable interrupts. • Supports DMA transfers. 6.23 Pulse Code Modulation (PCM) interface The PCM interface supports the PCM and IOM interfaces. The IOM (ISDN Oriented Modular) interface is primarily used to interconnect telecommunications ICs providing ISDN compatibility. It delivers a symmetrical full-duplex communication link containing user data, control/programming lines, and status channels. PCM (Pulse Code Modulation) is a very common method used for transmitting analog data in digital format. Most common applications of PCM are digital audio as in Audio CD and computers, digital telephony and videos. This module has the following features: • Four-wire serial interface. • Can function in both Master and Slave modes. • Supports: – PCM: Single clocking physical format. – Multi-Protocol (MP) PCM: Configurable directional per slot. – IOM-2: Extended ISDN-Oriented modular. Double clocking physical format. • • • • Twelve eight bit slots in a frame with enabling control per slot. Internal frame clock generation in master mode. Receive and transmit DMA handshaking using a request/clear protocol. Interrupt generation per frame. 6.24 LCD interface The dedicated LCD interface contains logic to interface to a 6800 (Motorola) or 8080 (Intel) compatible LCD controllers which support 4/8/16 bit modes. This module also supports a serial interface mode. The speed of the interface can be adjusted in software to match the speed of the connected LCD display. This module has the following features: • 4/8/16 bit parallel interface mode: 6800-series, 8080-series. • Serial interface mode. • Supports multiple frequencies for the 6800/8080 bus to support high- and low-speed controllers. • Supports polling the busy flag from LCD controller to off-load the CPU from polling. • Contains an 16 byte FIFO for sending control and data information to the LCD controller. • Supports maskable interrupts. • Supports DMA transfers. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 29 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.25 I2C-bus master/slave interface The LPC3130/3131 contains two I2C master/slave interfaces. This module has the following features: • I2C-bus interface 0 (I2C0): I2C0 is a standard I2C-compliant bus interface with open-drain pins. This interface supports functions described in the I2C-bus specification for speeds up to 400 kHz. This includes multi-master operation and allows powering off this device in a working system while leaving the I2C-bus functional. • I2C-bus interface 1 (I2C1): I2C1 uses standard I/O pins and is intended for use with a single-master I2C-bus and does not support powering off of this device. Standard I/Os also do not support multi-master I2C implementations. • Supports normal mode (100 kHz SCL). • Fast mode (400 kHz SCL with 24 MHz APB clock; 325 kHz with12 MHz APB clock; 175 kHz with 6 MHz APB clock). • Interrupt support. • Supports DMA transfers (single). • Four modes of operation: – Master transmitter – Master receiver – Slave transmitter – Slave receiver 6.26 LCD/NAND flash/SDRAM multiplexing The LPC3130/3131 contains a rich set of specialized hardware interfaces but the TFBGA package does not contain enough pins to allow use of all signals of all interfaces simultaneously. Therefore a pin-multiplexing scheme is created, which allows the selection of the right interface for the application. Pin multiplexing is enabled between the following interfaces: • • • • between the dedicated LCD interface and the external bus interface. between the NAND flash controller and the memory card interface. between UART and SPI. between I2STX_0 output and the PCM interface. The pin interface multiplexing is subdivided into five categories: storage, video, audio, NAND flash, and UART related pin multiplexing. Each category supports several modes, which can be selected by programming the corresponding registers in the SysCReg. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 30 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.26.1 Pin connections Table 10. Pin Name Pin descriptions of multiplexed pins Default Signal Alternate Signal EBI_NSTCS_0 EBI_NSTCS_1 EBI_CLKOUT EBI_CKE EBI_NDYCS EBI_DQM_1 EBI_A_2 EBI_A_3 EBI_A_4 EBI_A_5 EBI_A_6 EBI_A_7 EBI_A_8 EBI_A_9 EBI_A_10 EBI_A_11 EBI_A_12 EBI_A_13 EBI_A_14 Description Video related pin multiplexing mLCD_CSB mLCD_DB_1 mLCD_DB_0 mLCD_E_RD mLCD_RS mLCD_RW_WR mLCD_DB_2 mLCD_DB_3 mLCD_DB_4 mLCD_DB_5 mLCD_DB_6 mLCD_DB_7 mLCD_DB_8 mLCD_DB_9 mLCD_DB_10 mLCD_DB_11 mLCD_DB_12 mLCD_DB_13 mLCD_DB_14 LCD_CSB LCD_DB_1 LCD_DB_0 LCD_E_RD LCD_RS LCD_RW_WR LCD_DB_2 LCD_DB_3 LCD_DB_4 LCD_DB_5 LCD_DB_6 LCD_DB_7 LCD_DB_8 LCD_DB_9 LCD_DB_10 LCD_DB_11 LCD_DB_12 LCD_DB_13 LCD_DB_14 LCD_CSB — LCD chip select for external LCD controller. EBI_NSTCS_0 — EBI static memory chip select 0. LCD_DB_1 — LCD bidirectional data line 1. EBI_NSTCS_1 — EBI static memory chip select 1. LCD_DB_0 — LCD bidirectional data line 0. EBI_CLKOUT — EBI SDRAM clock signal. LCD_E_RD — LCD enable/read signal. EBI_CKE — EBI SDRAM clock enable. LCD_RS — LCD register select signal. EBI_NDYCS — EBI SDRAM chip select. LCD_RW_WR — LCD read write/write signal. EBI_DQM_1 — EBI SDRAM data mask output 1. LCD_DB_2 — LCD bidirectional data line 2. EBI_A_2 — EBI address line 2. LCD_DB_3 — LCD bidirectional data line 3. EBI_A_3 — EBI address line 3. LCD_DB_4 — LCD bidirectional data line 4. EBI_A_4 — EBI address line 4. LCD_DB_5 — LCD bidirectional data line 5. EBI_A_5 — EBI address line 5. LCD_DB_6 — LCD bidirectional data line 6. EBI_A_6 — EBI address line 6. LCD_DB_7 — LCD bidirectional data line 7. EBI_A_7 — EBI address line 7. LCD_DB_8 — LCD bidirectional data line 8. EBI_A_8 — EBI address line 8. LCD_DB_9 — LCD bidirectional data line 9. EBI_A_9 — EBI address line 9. LCD_DB_10 — LCD bidirectional data line 10. EBI_A_10 — EBI address line 10. LCD_DB_11 — LCD bidirectional data line 11. EBI_A_11 — EBI address line 11. LCD_DB_12 — LCD bidirectional data line 12. EBI_A_12 — EBI address line 12. LCD_DB_13 — LCD bidirectional data line 13. EBI_A_13 — EBI address line 13. LCD_DB_14 — LCD bidirectional data line 14. EBI_A_14 — EBI address line 14. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 31 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 10. Pin Name Pin descriptions of multiplexed pins …continued Default Signal LCD_DB_15 Alternate Signal EBI_A_15 Description LCD_DB_15 — LCD bidirectional data line 15. EBI_A_15 — EBI address line 15. mLCD_DB_15 Storage related pin multiplexing mGPIO5 mGPIO6 mGPIO7 mGPIO8 mGPIO9 mGPIO10 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 MCI_CLK MCI_CMD MCI_DAT_0 MCI_DAT_1 MCI_DAT_2 MCI_DAT_3 GPIO5 — General Purpose I/O pin 5. MCI_CLK — MCI card clock. GPIO_6 — General Purpose I/O pin 6. MCI_CMD — MCI card command input/output. GPIO7 — General Purpose I/O pin 7. MCI_DAT_0 — MCI card data input/output line 0. GPIO8 — General Purpose I/O pin 8. MCI_DAT_1 — MCI card data input/output line 1. GPIO9 — General Purpose I/O pin 9. MCI_DAT_2 — MCI card data input/output line 2. GPIO10 — General Purpose I/O pin 10. MCI_DAT_3 — MCI card data input/output line 3. NAND related pin multiplexing mNAND_RYBN0 NAND_RYBN0 mNAND_RYBN1 NAND_RYBN1 mNAND_RYBN2 NAND_RYBN2 mNAND_RYBN3 NAND_RYBN3 Audio related pin multiplexing mI2STX_DATA0 mI2STX_BCK0 mI2STX_WS0 mI2STX_CLK0 I2STX_DATA0 I2STX_BCK0 I2STX_WS0 I2STX_CLK0 PCM_DA PCM_FSC PCM_DCLK PCM_DB I2STX_DATA0 — I2S-bus interface 0 transmit data signal. PCM_DA — PCM serial data line A. I2STX_BCK0 — I2S-bus interface 0 transmit bitclock signal. PCM_FSC — PCM frame synchronization signal. I2STX_WS0 — I2S-bus interface 0 transmit word select signal. PCM_DCLK — PCM data clock output. I2STX_CLK0 — I2S-bus interface 0 transmit clock signal. PCM_DB — PCM serial data line B. UART related pin multiplexing mUART_CTS_N UART_CTS_N SPI_CS_OUT1 UART_CTS_N — UART modem control Clear-to-send signal. SPI_CS_OUT1 — SPI chip select out for slave 1 (used in master mode). mUART_RTS_N UART_RTS_N SPI_CS_OUT2 UART_RTS_N — UART modem control Request-to-Send signal. SPI_CS_OUT2 — SPI chip select out for slave 2 (used in master mode). MCI_DAT_4 MCI_DAT_5 MCI_DAT_6 MCI_DAT7 NAND_RYBN0 — NAND flash controller Read/Not busy signal 0. MCI_DAT_4 — MCI card data input/output line 4. NAND_RYBN1 — NAND flash controller Read/Not busy signal 1. MCI_DAT_5 — MCI card data input/output line 5. NAND_RYBN2 — NAND flash controller Read/Not busy signal 2. MCI_DAT_6 — MCI card data input/output line 6. NAND_RYBN3 — NAND flash controller Read/Not busy signal 3. MCI_DAT7 — MCI card data input/output line 7. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 32 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.26.2 Multiplexing between LCD and MPMC The multiplexing between the LCD interface and MPMC allows for the following two modes of operation: • MPMC-mode: SDRAM and bus-based LCD or SRAM. • LCD-mode: Dedicated LCD-Interface. The external NAND flash is accessible in both modes. The block diagram Figure 9 gives a high level overview of the modules in the chip that are involved in the pin interface multiplexing between the EBI, NAND flash controller, MPMC, and RAM-based LCD interface. LPC31xx control NAND_NCS_[0:3] NAND_RYBN[0:3] control NAND FLASH INTERFACE control (ALE, CLE) 2 2 address EBI_A_[1:0] 2 data 16 EBI_A_0_ALE EBI_A_1_CLE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE control 3 data data 16 16 EBI_D_[15:0] SUP4 EBI MPMC address 16 control address EBI_A_[15:2] 14 1 6 14 0 LCD_DB_[15:2] (LCD mode)/ EBI_A_[15:2] (MPMC mode) data LCD_DB_[15:2] 14 SYSCREG_MUX_LCD_EBI_SEL register (I/O multplexing) LCD mode LCD data LCD_DB_[1:0], control 1 6 6 MPMC mode 0 SUP8 LCD_CSB/EBI_NSTCS_0 LCD_DB_1/EBI_NSTCS_1 LCD_DB_0/EBI_CLKOUT LCD_E_RD/EBI_CKE LCD_RS/EBI_NDYCS LCD_RW_WR/EBI_DQM_1 002aae157 Fig 9. Diagram of LCD and MPMC multiplexing Figure 9 only shows the signals that are involved in pad-muxing, so not all interface signals are visible. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 33 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers The EBI unit between the NAND flash interface and the MPMC contains an arbiter that determines which interface is muxed to the outside world. Both NAND flash and SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin arbitration (see Section 6.6). 6.26.3 Supply domains As is shown in Figure 9 the EBI (NAND flash/MPMC-control/data) is connected to a different supply domain than the LCD interface. The EBI control and address signals are muxed with the LCD interface signals and are part of supply domain SUP8. The SDRAM/SRAM data lines are shared with the NAND flash through the EBI and are part of supply domain SUP4. Therefore the following rules apply for connecting memories: 1. SDRAM and bus-based LCD or SRAM: This is the MPMC mode. The supply voltage for SDRAM/SRAM/bus-based LCD and NAND flash must be the same.The dedicated LCD interface is not available in this MPMC mode. 2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage (SUP4) can be different from the LCD supply voltage (SUP8). 6.27 Timer module The LPC3130/3131 contains four fully independent timer modules, which can be used to generate interrupts after a pre-set time interval has elapsed. This module has the following features: • Each timer is a 32 bit wide down-counter with selectable pre-scale. The pre-scaler allows using either the module clock directly or the clock divided by 16 or 256. • Two modes of operation: – Free-running timer: The timer generates an interrupt when the counter reaches zero. The timer wraps around to 0xFFFFFFFF and continues counting down. – Periodic timer: The timer generates an interrupt when the counter reaches zero. It reloads the value from a load register and continues counting down from that value. An interrupt will be generated every time the counter reaches zero. This effectively gives a repeated interrupt at a regular interval. • At any time the current timer value can be read. • At any time the value in the load register may be re-written, causing the timer to restart. 6.28 Pulse Width Modulation (PWM) module This PWM can be used to generate a pulse width modulated or a pulse density modulated signal. With an external low pass filter, the module can be used to generate a low-frequency analog signal. A typical use of the output of the module is to control the backlight of an LCD display. This module has the following features: • Supports Pulse Width Modulation (PWM) with software controlled duty cycle. • Supports Pulse Density Modulation (PDM) with software controlled pulse density. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 34 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 6.29 System control registers The System Control Registers (SysCReg) module provides a register interface for some of the high-level settings in the system such as multiplexers and mode settings. This is an auxiliary module included in this overview for the sake of completeness. 6.30 I2S0/1 interfaces The I2S0/1 receive and I2S0/1 transmit modules have the following features: • • • • • Audio interface compatible with the I2S standard. I2S0/1 receive supports master mode and slave mode. I2S0/1 transmit supports master mode. Supports LSB justified words of 16, 18, 20 and 24 bits. Supports a configurable number of bit clock periods per Word Select period (up to 128 bit clock periods). • Supports DMA transfers. • Transmit FIFO (I2S transmit) or receive FIFO (I2S receive) of 4 stereo samples. • Supports single 16 bit transfers to/from the left or right FIFO. • Supports single 24 bit transfers to/from the left or right FIFO. • Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio sample, and the higher 16 bits representing the right audio sample. • Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right samples) to reduce busload. • Provides maskable interrupts for audio status: FIFO underrun/overrun/full/ half_full/not empty for left and right channel separately. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 35 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol All digital I/O pins VI VO IO Temperature values Tj Tstg Tamb Vesd junction temperature storage temperature ambient temperature electrostatic discharge voltage human body model machine model charged device model [1] [3] [2] Parameter input voltage output voltage output current Conditions Min −0.5 −0.5 Typ 4 25 +25 500 Max +3.6 +3.6 125 +150 +85 +500 +100 - Unit V V mA °C °C °C V V V VDDE_IOC = 3.3 V −40 −65 −40 −500 −100 - Electrostatic handling The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. [2] [3] LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 36 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 8. Static characteristics Table 12: Static characteristics Tamb = −40 °C to +85 °C unless otherwise specified. Symbol Supply pins VDD(IO) input/output supply voltage NAND flash controller pads (SUP4) and LCD interface (SUP8); 1.8 V mode NAND flash controller pads (SUP4) and LCD interface (SUP8); 2.8 V mode other peripherals (SUP 3) VDD(CORE) VDD(OSC_PLL) core supply voltage oscillator and PLL supply voltage ADC supply voltage (SUP1) on pin VDDA12; for 12 MHz oscillator (SUP1) on pin ADC10B_VDDA33; for 10-bit ADC (SUP 3) on pin USB_VBUS (SUP5) on pin USB_VDDA33 (SUP 3) on pin USB_VDDA33_DRV (SUP 3); driver VDDA(PLL)(1V2) PLL analog supply voltage (1.2 V) on pin USB_VDDA12_PLL (SUP1) 1.65 1.8 1.95 V Parameter Conditions Min Typ Max Unit 2.5 2.8 3.1 V 2.7 1.0 1.0 3.3 1.2 1.2 3.6 1.3 1.3 V V V VDD(ADC) 2.7 3.3 3.6 V VBUS bus supply voltage 3.0 2.7 5.0 3.3 3.3 3.6 3.6 V V V VDDA(USB)(3V3) USB analog supply voltage (3.3 V) 1.1 1.2 1.3 V Input pins and I/O pins configured as input VI VIH VIL Vhys input voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage SUP3; SUP4; SUP8 SUP3; SUP4; SUP8 SUP4; SUP8 1.8 V mode 2.8 V mode SUP3 IIL IIH Ilatch LOW-level input current HIGH-level input current I/O latch-up current VI = 0 V; no pull-up VI = VDD(IO); no pull-down −(1.5VDD(IO)) < VI < (1.5VDD(IO)) 400 550 0.1VDDE_IOC 600 850 0 0.7VDDE_IOx (x = A, B, C) VDDE_IOC V V 0.3VDDE_IOx V (x = A, B, C) V mV mV V µA µA mA LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 37 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 12: Static characteristics Tamb = −40 °C to +85 °C unless otherwise specified. Symbol Ipu Parameter pull-up current Conditions inputs with pull-up; VI = 0 SUP4/SUP8; 1.8 V mode SUP4/SUP8; 2.8 V mode SUP3 Ipd pull-down current inputs with pull-down; VI = VDD SUP4/SUP8; 1.8 V mode SUP4/SUP8; 2.8 V mode SUP3 Ci input capacitance excluding bonding pad capacitance µA µA µA pF µA µA µA Min Typ Max Unit Output pins and I/O pins configured as output VO VOH output voltage HIGH-level output voltage SUP4; SUP8; IOH = 6 mA: 1.8 V mode 2.8 V mode SUP3; IOH = 6 mA SUP3; IOH = 30 mA VOL LOW-level output voltage SUP4; SUP8 outputs; IOL = 4 mA 1.8 V mode 2.8 V mode SUP3; IOL = 4 mA IOH HIGH-level output current VDD = VDDE_IOx (x = A, B, C); VOH = VDD − 0.4 V VDD = VDDE_IOx (x = A, B, C); VOH = VDD − 0.4 V IOL LOW-level output current VDD = VDDE_IOx (x = A, B, C); VOL = 0.4 V VDD = VDDE_IOx (x = A, B, C); VOL = 0.4 V IOZ OFF-state output current VO = 0 V; VO = VDD; no pull-up/down V V V mA VDD(IO) − 0.26 VDD(IO) − 0.26 VDD(IO) − 0.38 V V V V VDD(IO) V - - mA - - mA - - mA - - 0.064 µA LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 38 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 12: Static characteristics Tamb = −40 °C to +85 °C unless otherwise specified. Symbol IOHS Parameter HIGH-level short-circuit output current LOW-level short-circuit output current output impedance Conditions VDD = VDDE_IOx (x = A, B, C); VOH = 0 V VDD = VDDE_IOx (x = A, B, C); VOH = 0 V VDD = VDDE_IOx (x = A, B, C); VOL = VDD VDD = VDDE_IOx (x = A, B, C); VOL = VDD VDD = VDDE_IOx (x = A, B, C) VDD = VDDE_IOx (x = A, B, C) I2C0-bus pins IOZ VIH VIL Vhys VOL ILI USB VIC common-mode input voltage high-speed mode full-speed/low-speed mode chirp mode Vi(dif) differential input voltage −50 800 −50 100 200 400 500 2500 600 1100 mV mV mV mV OFF-state output current HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS = 3 mA VI = VI = 5 V VO = 0 V; VO = VDD; no pull-up/down 7.25 0.298 µA V V V V µA µA Min Typ Max Unit mA mA mA mA Ω Ω IOLS Zo LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 39 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers Table 13. ADC static characteristics VDD(ADC) = 2.7 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency . Symbol VIA Cia Nres(ADC) ED EL(adj) EO EG ET Verr(O) Verr(FS) Rvsi Parameter analog input voltage analog input capacitance ADC resolution differential linearity error integral non-linearity offset error gain error absolute error offset error voltage full-scale error voltage voltage source interface resistance On pin ADC10B_GNDA. Conditions: VSSA = 0 V on pin ADC10B_GNDA, VDD(ADC) = 3.3 V. The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 10. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 10. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 10. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 10. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 10. See Figure 11. [9] [2][3][4] [2][5] [2][6] [2][7] [2][8] Conditions Min 0[1] 2 −20 - Typ - Max VDD(ADC) 10 ±1 ±1 +20 Unit V pF bit LSB LSB LSB % LSB mV mV kΩ [1] [2] [3] [4] [5] [6] [7] [8] [9] LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 40 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers offset error EO 1023 gain error EG 1022 1021 1020 1019 1018 (2) 7 code out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024 0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB = VDDA − VSSA 1024 002aac046 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 10. ADC characteristics LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 41 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers LPC31XX tbd kΩ ADCSAMPLE tbd pF tbd pF AD10B_GPA[0:3] Rvsi VEXT VSSA 002aae136 Fig 11. Suggested 10-bit ADC interface LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 42 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 9. Dynamic characteristics 9.1 LCD controller 9.1.1 Intel 8080 mode Table 14. Dynamic characteristics: LCD controller in Intel 8080 mode CL = 25 pF, Tamb = −40 °C to +85 °C, unless otherwise specified; VDD(IO) = 1.8 V and 2.8 V (SUP8). Symbol tsu(A) th(A) tcy(a) tw(en)W tw(en)R tr tf tsu(D) th(D) td(QV) tdis(Q) [1] Parameter address set-up time address hold time access cycle time write enable pulse width read enable pulse width rise time fall time data input set-up time data input hold time data output valid delay time data output disable time Conditions Min [1] [1] [1] Typ 1 × LCDCLK 2 × LCDCLK 5 × LCDCLK 2 × LCDCLK 2 × LCDCLK 2 × LCDCLK Max 5 5 - Unit ns ns ns ns ns ns ns ns ns ns ns 2 2 - −1 × LCDCLK - Timing is determined by the LCD Interface Control Register fields: INVERT_CS = 1; MI = 0; PS = 0; INVERT_E_RD = 0. See LPC3130/3131 user manual. th(A) mLCD_RS mLCD_CSB tcy(a) tsu(A) mLCD_RW_WR, mLCD_E_RD tf tsu(D) mLCD_DB[15:0] (16 bit mode), mLCD_DB[15:8] (8 bit mode), mLCD_DB[15:12] (4 bit mode) td(QV) mLCD_DB[15:0] (16 bit mode), mLCD_DB[15:8] (8 bit mode), mLCD_DB[15:12] (4 bit mode) tdis(Q) write access tr th(D) tw(en)R and tw(en)W read access 002aae207 Fig 12. LCD timing (Intel 8080 mode) LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 43 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 9.1.2 Motorola 6800 mode Table 15. Dynamic characteristics: LCD controller in Motorola 6800 mode CL = 25 pF, Tamb = −40 °C to +85 °C, unless otherwise specified; VDD(IO) = 1.8 V and 2.8 V (SUP8). Symbol tsu(A) th(A) tcy(a) tr tf tsu(D) th(D) td(QV) tdis(Q) tw(en) Parameter address set-up time address hold time access cycle time rise time fall time data input set-up time data input hold time data output valid delay time data output disable time enable pulse width read cycle write cycle [1] [1] Conditions Min 2 2 - Typ 1 × LCDCLK 2 × LCDCLK 5 × LCDCLK −1 × LCDCLK 2 × LCDCLK 2 × LCDCLK 2 × LCDCLK Max 5 5 - Unit ns ns ns ns ns ns ns ns ns ns ns Timing is derived from the LCD Interface Control Register fields: INVERT_CS = 1; MI = 1; PS = 0; INVERT_E_RD = 0. See LPC3130/3131 user manual. mLCD_CSB tcy(a) tw(en) mLCD_E_RD tr tsu(A) mLCD_RS, mLCD_RW_WR tsu(D) mLCD_DB[15:0] (16 bit mode), mLCD_DB[15:8] (8 bit mode), mLCD_DB[15:12] (4 bit mode) td(QV) mLCD_DB[15:0] (16 bit mode), mLCD_DB[15:8] (8 bit mode), mLCD_DB[15:12] (4 bit mode) tdis(Q) write access tf th(A) th(D) read access 002aae208 Fig 13. LCD timing (Motorola 6800 mode) LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 44 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 9.1.3 Serial mode Table 16. Dynamic characteristics: LCD controller serial mode CL = 25 pF, Tamb = −40 °C to +85 °C, unless otherwise specified; VDD(IO) = 1.8 V and 2.8 V (SUP8). Symbol Parameter Tcy(clk) tw(clk)H tw(clk)L tr tf tsu(A) th(A) tsu(D) th(D) tsu(S) th(S) td(QV) [1] Conditions [1] [1] [1] Min 2 2 - Typ 5 × LCDCLK 3 × LCDCLK 2 × LCDCLK 3 × LCDCLK 2 × LCDCLK 3 × LCDCLK 1 × LCDCLK −1 × LCDCLK Max 5 5 - Unit ns ns ns ns ns ns ns ns ns ns ns ns clock cycle time HIGH clock pulse width LOW clock pulse width rise time fall time address set-up time address hold time data input set-up time data input hold time chip select set-up time chip select hold time data output valid delay time Timing is determined by the LCD Interface Control Register fields: PS = 1; SERIAL_CLK_SHIFT = 3; SERIAL_READ_POS = 3. See the LPC3130/3131 user manual. tsu(S) mLCD_CSB tsu(A) mLCD_RS Tcy(clk) tw(clk)L mLCD_DB13 (serial clock) tf tr tsu(D) mLCD_DB14 (serial data in) td(QV) mLCD_DB15 (serial data out) th(D) th(A) th(S) tw(clk)H tdis(Q) 002aae209 Fig 14. LCD timing (serial mode) LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 45 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 9.2 SRAM controller Table 17. Dynamic characteristics: static external memory interface CL = 25 pF, Tamb = −40 °C to +85 °C, unless otherwise specified; VDD(IO) = 1.8 V and 2.8 V (SUP8). Symbol tCSLAV Parameter CS LOW to address valid time OE LOW to address valid time BLS LOW to address valid time CS LOW to OE LOW time CS LOW to BLS LOW time OE LOW to OE HIGH time BLS LOW to BLS HIGH time data input/output set-up time data input/output hold time CS HIGH to OE HIGH time CS HIGH to BLS HIGH time OE HIGH to address invalid time BLS HIGH to address invalid time CS LOW to data valid time CS LOW to WE LOW time CS LOW to BLS LOW time WE LOW to data valid time WE LOW to WE HIGH time BLS LOW to BLS HIGH time WE HIGH to address invalid time WE HIGH to data invalid time BLS HIGH to address invalid time BLS HIGH to data invalid time [4] [4] [4] [4][5][6] [4][5] [1] [1][2][3] [1][2][3] [1] Conditions Min - Typ 0 Max - Unit ns Common to read and write cycles Read cycle parameters tOELAV tBLSLAV tCSLOEL tCSLBLSL tOELOEH tBLSLBLSH tsu(DQ) th(DQ) tCSHOEH tCSHBLSH tOEHANV tBLSHANV 0 − WAITOEN × HCLK 0 − WAITOEN × HCLK 0 + WAITOEN × HCLK 0 + WAITOEN × HCLK (WAITRD − WAITOEN + 1) × HCLK (WAITRD − WAITOEN + 1) × HCLK 8 0 0 0 2 × HCLK 2 × HCLK ns ns ns ns ns ns ns ns ns ns ns ns [1] Write cycle parameters tCSLDV tCSLWEL tCSLBLSL tWELDV tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV tBLSHDNV 0 (WAITWEN + 1) × HCLK WAITWEN × HCLK 0 − (WAITWEN + 1) × HCLK (WAITWR − WAITWEN + 1) × HCLK (WAITWR − WAITWEN + 3) × HCLK 1 × HCLK 1 × HCLK 0 0 ns ns ns ns ns ns ns ns ns ns [1] [2] [3] [4] [5] [6] Refer to the LPC3130/3131 user manual for the programming of WAITOEN and HCLK. Refer to the LPC3130/3131 user manual for the programming of WAITRD and HCLK. (WAITRD − WAITOEN + 1) = 3 min at 60 MHz. Refer to the LPC3130/3131 user manual for the programming of WAITWEN and HCLK. Refer to the LPC3130/3131 user manual for the programming of WAITWR and HCLK. (WAITWD − WAITWEN + 1) = 3 min at 60 MHz. LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 46 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers EBI_NSTCS_X tCSLAV EBI_A_[15:0] tOELAV tCSHOEH EBI_DQM_0_NOE tOELOEH tCSLOEL tBLSLAV tOEHANV tCSHBLSH EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 tBLSLBLSH tCSLBLSL tBLSHANV EBI_D_[15:0] th(DQ) tsu(DQ) 002aae161 Fig 15. External memory read access to static memory LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 47 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers EBI_NSTCS_X tCSLAV EBI_A_[15:0] tBLSHANV tCSLDV EBI_D_[15:0] tWEHANV tWELWEH tCSLWEL tWEHDNV EBI_NWE tWELDV tBLSLBLSH tCSLBLSL EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 tBLSHDNV 002aae162 Fig 16. External memory write access to static memory LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 48 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers 9.3 SDRAM controller Table 18. Dynamic characteristics of SDR SDRAM memory interface Tamb = −40 °C to +85 °C, unless otherwise specified; VDD(IO) = 1.8 V and 2.8 V (SUP8).[1][2] Symbol foper TCLCL tCLCX tCHCX td(o) Parameter operating frequency clock cycle time clock LOW time clock HIGH time output delay time on pin EBI_CKE on pins EBI_NRAS_BLOUT, EBI_NCAS_BLOUT, EBI_NWE, EBI_NDYCS on pins EBI_DQM_1, EBI_DQM_0_NOE th(o) output hold time on pin EBI_CKE on pins EBI_NRAS_BLOUT, EBI_NCAS_BLOUT, EBI_NWE, EBI_NDYCS on pins EBI_DQM_1, EBI_DQM_0_NOE td(AV) th(A) td(QV) th(Q) tsu(D) th(D) tQZ address valid delay time address hold time data output valid delay time data output hold time data input set-up time data input hold time data output high-impedance time Conditions [3] Min - Typical - Max 3.5 3.5 Unit MHz ns ns ns ns ns 0.2 0.23 - 5 3.5 3.5 ns ns ns 2 0.1 4 - - 5 5 5 9 10