LPC3240

LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01 — 6 February 2009 Preliminary data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz. The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations, and hardware based native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB instruction cache and a 32 kB data cache. For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management. The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices. In addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs, two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single output PWMs, a motor control PWM, six general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option. 2. Features I I I I I ARM926EJS processor, running at CPU clock speeds up to 266 MHz Vector Floating Point (VFP) coprocessor. 32 kB instruction cache and a 32 kB data cache. Up to 256 kB of Internal SRAM (IRAM). Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART, or static memory. I Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC. There are no arbitration delays in the system unless two masters attempt to access the same slave at the same time. NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers I External memory controller for DDR and SDR SDRAM as well as for static devices. I Two NAND flash controllers: One for single-level NAND flash devices and the other for multi-level NAND flash devices. I Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting 74 interrupt sources. I Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be used with the SD card port, the high-speed UARTs, I2S-bus interfaces, and SPI interfaces, as well as memory-to-memory transfers. I Serial interfaces: N 10/100 Ethernet MAC with dedicated DMA Controller. N USB interface supporting either device, host (OHCI compliant), or On-The-Go (OTG) with an integral DMA controller and dedicated PLL to generate the required 48 MHz USB clock. N Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One of the standard UART’s supports IrDA. N Three additional high-speed UARTs intended for on-board communications that support baud rates up to 921 600 when using a 13 MHz main oscillator. All high-speed UARTs provide 64 byte FIFOs. N Two SPI controllers. N Two SSP controllers. N Two I2C-bus interfaces with standard open-drain pins. The I2C-bus interfaces support single master, slave, and multi-master I2C-bus configurations. N Two I2S-bus interfaces, each with separate input and output channels. Each channel can be operated independently on three pins, or both input and output channels can be used with only four pins and a shared clock. I Additional peripherals: N LCD controller supporting both STN and TFT panels, with dedicated DMA controller. Programmable display resolution up to 1024 × 768. N Secure Digital (SD) memory card interface, which conforms to the SD Memory Card Specification Version 1.01. N General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24 GP output pins, and 51 GP I/O pins. N 10 bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from three pins. Optionally, the ADC can operate as a touch screen controller. N Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator. NXP implemented the RTC in an independent on-chip power domain so it can remain active while the rest of the chip is not powered. The RTC also includes a 32 byte scratch pad memory. N 32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer includes one external capture input pin and a capture connection to the RTC clock. Interrupts may be generated using three match registers. N Six enhanced timer/counters which are architecturally identical except for the peripheral base address. Two capture inputs and two match outputs are pinned out to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs. N 32-bit millisecond timer driven from the RTC clock. This timer can generate interrupts using two match registers. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 2 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers I I I I I I I N WatchDog timer clocked by the peripheral clock. N Two single-output PWM blocks. N Motor control PWM N Keyboard scanner function allows automatic scanning of an up to 8 × 8 key matrix. N Up to 18 external interrupts. Standard ARM test/debug interface for compatibility with existing tools. Emulation Trace Buffer (ETB) with 2048 × 24 bit RAM allows trace via JTAG. Stop mode saves power while allowing many peripheral functions to restart CPU activity. On-chip crystal oscillator. An on-chip PLL allows CPU operation up to the maximum CPU rate without the requirement for a high frequency crystal. Another PLL allows operation from the 32 kHz RTC clock rather than the external crystal. Boundary scan for simplified board testing. 296 pin TFBGA package with a 15 × 15 × 0.7 mm body. 3. Applications I I I I Consumer Medical Industrial Network control 4. Ordering information Table 1. Ordering information Package Name LPC3220FET296 LPC3230FET296 LPC3240FET296 LPC3250FET296 [1] Type number[1] Description Version TFBGA296 TFBGA296 TFBGA296 TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 F = −40 °C to +85 °C temperature range. 4.1 Ordering options Table 2. Part options SRAM (kB) 128 256 256 256 10/100 Ethernet 0 0 1 1 LCD controller Temperature range (°C) 0 1 0 1 −40 to +85 −40 to +85 −40 to +85 −40 to +85 Package TFBGA296 TFBGA296 TFBGA296 TFBGA296 Type number LPC3220FET296 LPC3230FET296 LPC3240FET296 LPC3250FET296 LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 3 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 5. Block diagram ethernet PHY interface USB transceiver interface LCD panel interface 32-bit wide external memory ETHERNET 10/100 MAC 4 VFP9 ETB ETM 9 D-CACHE 32 kB D-SIDE CONTROLLER DATA master layer slave port 0 1 2 3 0 ARM 9EJS I-CACHE 32 kB I-SIDE CONTROLLER INSTRUCTION 1 DMA CONTROLLER M0 2 M1 3 5 6 USB OTG CONTROLLER LCD CONTROLLER MMU EXTERNAL MEMORY CONTROLLER port 3 port 4 port 0 5 AHB slaves SLC NAND 6 DMA MLC NAND AHB APB slaves TO APB BRIDGE SPI ×2 SRAM 256 kB ROM 16 kB SD CARD SSP ×2 I2S ×2 USB SDRAM ETB ETHERNET LCD register interfaces 7 32 bit, AHB matrix AHB APB slaves TO APB BRIDGE I2C ×2 STANDARD UART × 4 MOTOR CONTROL PWM = Master/Slave connection supported by the multilayer AHB matrix WATCHDOG TIMERS PWM TIMER ×6 ×2 AHB FAB slaves TO APB BRIDGE SYSTEM KEY DEBUG CONTROL SCANNER RTC GPIO INTERRUPT CONTROL HS UART ×3 UART CONTROL 10-BIT ADC/TS 002aae397 Fig 1. Block diagram of LPC3220/30/40/50 LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 4 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 6. Pinning information 6.1 Pinning ball A1 index area 1 A B C D E F G H J K L M N P R T U V 002aae398 2 3 4 5 6 7 8 9 10 12 14 16 18 11 13 15 17 Transparent top view Fig 2. Table 3. Pin Row A Pin configuration for SOT1048-1 (TFBGA296) Pin allocation table (TFBGA296) Pin Symbol Pin A3 Symbol I2C2_SCL MS_BS/MAT2[1] SPI2_DATIO/MOSI1/LCDVD[20] Symbol A4 A7 I2S1TX_CLK/MAT3[0] MS_DIO1/MAT0[1] A5 A8 I2C1_SCL MS_DIO0/MAT0[0] A6 A9 A10 SPI2_DATIN/MISO1/LCDVD[21]/ A11 GPIO_1 GPI_27 A13 GPO_21/U4_TX/LCDVD[3] A16 GPO_6/LCDVD[18] Row B B2 B4 B7 I2S1TX_WS/CAP3[0] MS_SCLK/MAT2[0] B5 B8 GPO_20 P0[0]/I2S1RX_CLK MS_DIO2/MAT0[2] A14 GPO_15/MCOA1/LCDFP A12 GPIO_0 A15 GPO_7/LCDVD[2] B3 B6 B9 GPO_5 I2C1_SDA SPI1_DATIO/MOSI0/MCI2 B10 SPI2_CLK/SCK1/LCDVD[23] B13 GPO_13/MCOB1/LCDDCLK B16 GPI_8/KEY_COL6/ SPI2_BUSY/ENET_RX_DV Row C C1 C4 C7 FLASH_RD USB_ATX_INT GPI_6/HSTIM_CAP/ ENET_RXD2 B11 GPIO_4/SSEL1/LCDVD[22] B14 GPO_2/MAT1[0]/LCDVD[0] B17 n.c. B12 GPO_12/MCOA2/LCDLE B15 GPI_19/U4_RX C2 C5 C8 GPO_19 USB_SE0_ VM/U5_TX MS_DIO3/MAT0[3] C3 C6 C9 GPO_0/TST_CLK1 TST_CLK2 SPI1_CLK/SCK0 LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 5 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 3. Pin Pin allocation table (TFBGA296) Pin Symbol Pin Symbol C11 GPIO_3/KEY_ROW7/ ENET_MDIO C14 GPI_2/CAP2[0]/ ENET_RXD3 C17 KEY_ROW4/ENET_TXD0 D2 D5 FLASH_ALE USB_DAT_VP/U5_RX C12 GPO_9/LCDVD[9] C15 GPI_1/SERVICE C18 KEY_ROW5/ENET_TXD1 D3 D6 GPO_14 USB_OE_TP Symbol C10 SPI1_DATIN/MISO0/GPI_25/ MCI1 C13 GPO_8/LCDVD[8] C16 GPI_0/I2S1RX_SDA Row D D1 D4 FLASH_RDY GPO_1 D7 P0[1]/I2S1RX_WS D10 GPO_16/MCOB0/LCDENAB/ LCDM D13 GPI_7/CAP4[0]/MCABORT D16 KEY_ROW3/ENET_TX_EN Row E E1 E4 E7 FLASH_IO[3] I2C2_SDA I2S1TX_SDA/MAT3[1] D8 GPO_4 D11 GPO_18/MCOA0/LCDLP D14 PWM_OUT1/LCDVD[16] D17 KEY_COL2/ENET_RX_ER E2 E5 E8 FLASH_IO[7] USB_I2C_SCL GPO_11 D9 GPIO_2/KEY_ROW6/ENET_MDC D12 GPO_3/LCDVD[1] D15 PWM_OUT2/INTSTAT/LCDVD[19] D18 KEY_COL3/ENET_CRS E3 E6 E9 FLASH_CE USB_I2C_SDA GPIO_5/SSEL0/MCI0 E10 GPO_22/U7_HRTS/LCDVD[14] E13 GPI_4/SPI1_BUSY E16 KEY_COL1/ENET_RX_CLK/ ENET_REF_CLK Row F F1 F4 F7 FLASH_IO[2] GPI_3 VDD_IOC E11 GPO_10/MCOB2/LCDPWR E14 KEY_ROW1/ENET_TXD2 E17 U7_RX/CAP0[0]/LCDVD[10]/ GPI_23 F2 F5 F8 FLASH_WR VSS_IOC VDD_IOB E12 GPI_9/KEY_COL7/ENET_COL E15 KEY_ROW0/ENET_TX_ER E18 U7_TX/MAT1[1]/LCDVD[11] F3 F6 F9 FLASH_CLE VSS_IOB VDD_IOD F10 VSS_IOD F13 VDD_IOD F16 KEY_COL5/ENET_RXD1 Row G G1 G4 G7 EMC_DYCS1 RESOUT VDD_CORE F11 VSS_IOD F14 KEY_ROW2/ENET_TXD3 F17 U6_IRRX/GPI_21 G2 G5 G8 FLASH_IO[5] VSS_IOC VSS_CORE F12 VSS_IOD F15 KEY_COL0/ENET_TX_CLK F18 U5_RX/GPI_20 G3 G6 G9 FLASH_IO[6] VDD_IOC VDD_CORE G10 VSS_CORE G13 U7_HCTS/CAP0[1]/ LCDCLKIN/GPI_22 G16 U6_IRTX Row H H1 H4 H7 EMC_OE FLASH_IO[4] VSS_CORE G11 VDD_CORE G14 DBGEN G17 SYSCLKEN/LCDVD[15] H2 H5 FLASH_IO[0] VSS_IOC G12 VSS_CORE G15 KEY_COL4/ENET_RXD0 G18 JTAG_TMS H3 H6 FLASH_IO[1] VDD_IOC H12 VSS_IOD H13 VDD_IOA LPC3220_30_40_50_1 H14 JTAG_TCK H15 U5_TX © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 6 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 3. Pin Pin allocation table (TFBGA296) Pin Symbol Pin Symbol H17 JTAG_NTRST J2 J5 EMC_A[21]/P1[21] VDD_IOC H18 JTAG_RTCK J3 J6 J12 EMC_A[22]/P1[22] VDD_EMC VDD_CORE JTAG_TDO U2_HCTS/U3_CTS/GPI_16 EMC_A[16]/P1[16] VDD_EMC Symbol H16 HIGHCORE/LCDVD[17] Row J J1 J4 J7 J13 J16 K1 K4 K7 EMC_A[20]/P1[20] EMC_A[23]/P1[23] VDD_CORE VDD_IOA JTAG_TDI EMC_A[19]/P1[19] EMC_A[17]/P1[17] VDD_EMC J14 J17 K2 K5 U3_RX/GPI_18 U3_TX EMC_A[18]/P1[18] VSS_EMC J15 J18 K3 K6 Row K K12 VSS_CORE K13 VSS_IOA K16 U1_TX Row L L1 L4 L7 EMC_A[15]/P1[15] EMC_A[1]/P1[1] VSS_CORE L12 VDD_COREFXD L13 VDD_RTCCORE L16 P0[5]/I2S0TX_SDA/LCDVD[7] Row M M1 M4 M7 EMC_A[2]/P1[2] EMC_A[8]/P1[8] VDD_CORE M2 M5 M8 EMC_A[3]/P1[3] VSS_EMC VDD_EMC M3 M6 M9 EMC_A[4]/P1[4] VDD_EMC VSS_CORE L14 VSS_RTCCORE L17 P0[6]/I2S0TX_CLK/ LCDVD[12] L15 P0[4]/I2S0RX_WS/LCDVD[6] L18 P0[7]/I2S0TX_WS/LCDVD[13] L2 L5 EMC_CKE1 VSS_EMC L3 L6 EMC_A[0]/P1[0] VDD_EMC K14 VDD_RTC K17 U2_TX/U3_DTR K15 U1_RX/CAP1[0]/GPI_15 K18 U2_RX/U3_DSR/GPI_17 M10 VSS_CORE M13 VDD_COREFXD M16 GPO_23/U2_HRTS/U3_RTS Row N N1 N4 N7 EMC_A[5]/P1[5] EMC_A[12]/P1[12] VDD_EMC M11 VDD_CORE M14 RESET M17 P0[2]/I2S0RX_SDA/ LCDVD[4] N2 N5 N8 EMC_A[6]/P1[6] VSS_EMC VDD_EMC M12 VSS_CORE M15 ONSW M18 P0[3]/I2S0RX_CLK/LCDVD[5] N3 N6 N9 EMC_A[7/P1[7] VSS_EMC VDD_EMC N10 VDD_EMC N13 VDD_AD N16 GPI_5/U3_DCD Row P P1 P4 EMC_A[9]/P1[9] EMC_DQM[1] N11 VDD_EMC N14 VDD_FUSE N17 GPI_28/U3_RI P2 P5 EMC_A[10]/P1[10] EMC_DQM[3] N12 VDD_AD N15 VDD_RTCOSC N18 GPO_17 P3 P6 EMC_A[11]/P1[11] VSS_EMC © NXP B.V. 2009. All rights reserved. LPC3220_30_40_50_1 Preliminary data sheet Rev. 01 — 6 February 2009 7 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 3. Pin P7 Pin allocation table (TFBGA296) Pin P8 Symbol VSS_EMC Pin P9 Symbol VSS_EMC Symbol VSS_EMC P10 VSS_EMC P13 VSS_AD P16 RTCX_IN Row R R1 R4 R7 EMC_A[13]/P1[13] EMC_WR EMC_D[1] P11 VSS_EMC P14 VSS_OSC P17 RTCX_OUT R2 R5 R8 EMC_A[14]/P1[14] EMC_CAS EMC_D[7] P12 EMC_BLS[3] P15 VDD_PLLUSB P18 VSS_RTCOSC R3 R6 R9 EMC_DQM[0] EMC_DYCS0 EMC_D[17]/EMC_DQS1 R10 EMC_D[24]/P2[5] R13 TS_XP R16 VSS_PLLUSB Row T T1 T4 T7 EMC_DQM[2] EMC_CLKIN EMC_D[11] R11 EMC_CS1 R14 PLL397_LOOP R17 VDD_PLLHCLK T2 T5 T8 EMC_RAS EMC_D[2] EMC_D[14] R12 EMC_BLS[2] R15 SYSX_OUT R18 VSS_PLLHCLK T3 T6 T9 EMC_CLK EMC_D[6] EMC_D[20]/P2[1] T10 EMC_D[23]/P2[4] T13 EMC_BLS[1] T16 VDD_PLL397 Row U T11 EMC_D[27]/P2[8] T14 ADIN1/TS_YM T17 SYSX_IN U2 n.c. EMC_D[3] EMC_D[15] T12 EMC_CS2 T15 VSS_PLL397 T18 VDD_OSC U3 U6 U9 EMC_CKE0 EMC_D[9] EMC_D[19]/P2[0] U4 U7 EMC_D[0] EMC_D[12] U5 U8 U10 EMC_D[22]/P2[3] U13 EMC_CS0 U16 TS_YP Row V U11 EMC_D[26]/P2[7] U14 EMC_BLS[0] U17 n.c. U12 EMC_D[30]/P2[11] U15 ADIN0/TS_XM V3 V4 V7 EMC_D[5] EMC_D[13] V5 V8 EMC_D[8] EMC_D[16]/EMC_DQS0 V6 V9 EMC_D[4] EMC_D[10] EMC_D[18]/EMC_CLK V10 EMC_D[21]/P2[2] V13 EMC_D[29]/P2[10] V16 ADIN2/TS_AUX_IN V11 EMC_D[25]/P2[6] V14 EMC_D[31]/P2[12] V12 EMC_D[28]/P2[9] V15 EMC_CS3 6.2 Pin description Table 4. Symbol ADIN0/TS_XM ADIN1/TS_YM ADIN2/TS_AUX_IN Pin description Pin U15 T14 V16 Power supply domain VDD_AD VDD_AD VDD_AD Type analog in analog in analog in Description ADC input 0/touch screen X minus ADC input 0/touch screen Y minus ADC input 2/ touch screen AUX input LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 8 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol DBGEN Pin description …continued Pin G14 L3 L4 M1 M2 M3 N1 N2 N3 M4 P1 P2 P3 N4 R1 R2 L1 K3 K4 K2 Power supply domain VDD_IOD VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC Type I: PD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Device test input (JTAG select = LOW; boundary scan = HIGH) EMC address bit 0 Port 1 GPIO bit 0 EMC address bit 1 Port 1 GPIO bit 1 EMC address bit 2 Port 1 GPIO bit 2 EMC address bit 3 Port 1 GPIO bit 3 EMC address bit 4 Port 1 GPIO bit 4 EMC address bit 5 Port 1 GPIO bit 5 EMC address bit 6 Port 1 GPIO bit 6 EMC address bit 7 Port 1 GPIO bit 7 EMC address bit 8 Port 1 GPIO bit 8 EMC address bit 9 Port 1 GPIO bit 9 EMC address bit 10 Port 1 GPIO bit 10 EMC address bit 11 Port 1 GPIO bit 11 EMC address bit 12 Port 1 GPIO bit 12 EMC address bit 13 Port 1 GPIO bit 13 EMC address bit 14 Port 1 GPIO bit 14 EMC address bit 15 Port 1 GPIO bit 15 EMC address bit 16 Port 1 GPIO bit 16 EMC address bit 17 Port 1 GPIO bit 17 EMC address bit 18 Port 1 GPIO bit 18 © NXP B.V. 2009. All rights reserved. EMC_A[0]/P1[0] EMC_A[1]/P1[1] EMC_A[2]/P1[2] EMC_A[3]/P1[3] EMC_A[4]/P1[4] EMC_A[5]/P1[5] EMC_A[6]/P1[6] EMC_A[7/P1[7] EMC_A[8]/P1[8] EMC_A[9]/P1[9] EMC_A[10]/P1[10] EMC_A[11]/P1[11] EMC_A[12]/P1[12] EMC_A[13]/P1[13] EMC_A[14]/P1[14] EMC_A[15]/P1[15] EMC_A[16]/P1[16] EMC_A[17]/P1[17] EMC_A[18]/P1[18] LPC3220_30_40_50_1 Preliminary data sheet Rev. 01 — 6 February 2009 9 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol Pin description …continued Pin K1 J1 J2 J3 J4 U14 T13 R12 P12 R5 U3 L2 T3 T4 U13 R11 T12 V15 U4 R7 T5 U5 V3 V4 T6 R8 V5 U6 V6 T7 U7 V7 T8 U8 Power supply domain VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O I O O O O I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK Description EMC address bit 19 Port 1 GPIO bit 19 EMC address bit 20 Port 1 GPIO bit 20 EMC address bit 21 Port 1 GPIO bit 21 EMC address bit 22 Port 1 GPIO bit 22 EMC address bit 23 Port 1 GPIO bit 23 Static memory byte lane 0 select Static memory byte lane 1 select Static memory byte lane 2 select Static memory byte lane 3 select SDRAM column address strobe out, active LOW Clock enable out for SDRAM bank 0 Clock enable out for SDRAM bank 1 SDRAM clock out SDRAM clock feedback EMC static memory chip select 0 EMC static memory chip select 1 EMC static memory chip select 2 EMC static memory chip select 3 EMC data bit 0 EMC data bit 1 EMC data bit 2 EMC data bit 3 EMC data bit 4 EMC data bit 5 EMC data bit 6 EMC data bit 7 EMC data bit 8 EMC data bit 9 EMC data bit 10 EMC data bit 11 EMC data bit 12 EMC data bit 13 EMC data bit 14 EMC data bit 15 EMC_A[19]/P1[19] EMC_A[20]/P1[20] EMC_A[21]/P1[21] EMC_A[22]/P1[22] EMC_A[23]/P1[23] EMC_BLS[0] EMC_BLS[1] EMC_BLS[2] EMC_BLS[3] EMC_CAS EMC_CKE0 EMC_CKE1 EMC_CLK EMC_CLKIN EMC_CS0 EMC_CS1 EMC_CS2 EMC_CS3 EMC_D[0] EMC_D[1] EMC_D[2] EMC_D[3] EMC_D[4] EMC_D[5] EMC_D[6] EMC_D[7] EMC_D[8] EMC_D[9] EMC_D[10] EMC_D[11] EMC_D[12] EMC_D[13] EMC_D[14] EMC_D[15] LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 10 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol Pin description …continued Pin V8 R9 V9 U9 T9 V10 U10 T10 R10 V11 U11 T11 V12 V13 U12 V14 R3 P4 T1 P5 R6 G1 H1 T2 Power supply domain VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC VDD_EMC Type I/O: BK I/O: BK I/O: BK I/O: BK I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P I/O: P O O O O O O O O Description EMC data bit 16 DDR data strobe 0 EMC data bit 17 DDR data strobe 1 EMC data bit 18 DDR inverted clock output EMC data bit 19 Port 2 GPIO bit 0 EMC data bit 20 Port 2 GPIO bit 1 EMC data bit 21 Port 2 GPIO bit 2 EMC data bit 22 Port 2 GPIO bit 3 EMC data bit 23 Port 2 GPIO bit 4 EMC data bit 24 Port 2 GPIO bit 5 EMC data bit 25 Port 2 GPIO bit 6 EMC data bit 26 Port 2 GPIO bit 7 EMC data bit 27 Port 2 GPIO bit 8 EMC data bit 28 Port 2 GPIO bit 9 EMC data bit 29 Port 2 GPIO bit 10 EMC data bit 30 Port 2 GPIO bit 11 EMC data bit 31 Port 2 GPIO bit 12 SDRAM data mask 0 out SDRAM data mask 1 out SDRAM data mask 2 out SDRAM data mask 3 out SDRAM active LOW chip select 0 SDRAM active LOW chip select 1 EMC static memory output enable SDRAM row address strobe, active LOW © NXP B.V. 2009. All rights reserved. EMC_D[16]/ EMC_DQS0 EMC_D[17]/ EMC_DQS1 EMC_D[18]/ EMC_CLK EMC_D[19]/P2[0] EMC_D[20]/P2[1] EMC_D[21]/P2[2] EMC_D[22]/P2[3] EMC_D[23]/P2[4] EMC_D[24]/P2[5] EMC_D[25]/P2[6] EMC_D[26]/P2[7] EMC_D[27]/P2[8] EMC_D[28]/P2[9] EMC_D[29]/P2[10] EMC_D[30]/P2[11] EMC_D[31]/P2[12] EMC_DQM[0] EMC_DQM[1] EMC_DQM[2] EMC_DQM[3] EMC_DYCS0 EMC_DYCS1 EMC_OE EMC_RAS LPC3220_30_40_50_1 Preliminary data sheet Rev. 01 — 6 February 2009 11 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol EMC_WR Pin description …continued Pin R4 D2 E3 F3 H2 H3 F1 E1 H4 G2 G3 E2 C1 D1 F2 C16 C15 C14 Power supply domain VDD_EMC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOD VDD_IOD VDD_IOD Type O O O O I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK I/O: BK O I O I I I I I I I F4 E13 N16 C7 VDD_IOC VDD_IOD VDD_IOA VDD_IOB I I I I I I I I D13 VDD_IOD I I I B16 VDD_IOD I I I I E12 VDD_IOD I I I Description EMC write strobe, active LOW Flash address latch enable Flash chip enable Flash command latch enable Flash data bus, bit 0 Flash data bus, bit 1 Flash data bus, bit 2 Flash data bus, bit 3 Flash data bus, bit 4 Flash data bus, bit 5 Flash data bus, bit 6 Flash data bus, bit 7 Flash read enable Flash ready (from flash device) Flash write enable General purpose input 0 I2S1 Receive data General purpose input 1 Boot select input General purpose input 2 Timer 2 capture input 0 Ethernet receive data 3 General purpose input 3 General purpose input 4 SPI1 busy input General purpose input 5 UART 3 data carrier detect input General purpose input 6 High-speed timer capture input Ethernet receive data 2 General purpose input 7 Timer 4 capture input 0 Motor control PWM LOW-active fast abort input General purpose input 8 Keyscan column 6 input SPI2 busy input Ethernet receive data valid input General purpose input 9 Keyscan column 7 input Ethernet collision input © NXP B.V. 2009. All rights reserved. FLASH_ALE FLASH_CE FLASH_CLE FLASH_IO[0] FLASH_IO[1] FLASH_IO[2] FLASH_IO[3] FLASH_IO[4] FLASH_IO[5] FLASH_IO[6] FLASH_IO[7] FLASH_RD FLASH_RDY FLASH_WR GPI_0/I2S1RX_SDA GPI_1/SERVICE GPI_2/CAP2[0]/ ENET_RXD3 GPI_3 GPI_4/SPI1_BUSY GPI_5/U3_DCD GPI_6/ HSTIM_CAP/ ENET_RXD2 GPI_7/CAP4[0]/ MCABORT GPI_8/KEY_COL6/ SPI2_BUSY/ ENET_RX_DV GPI_9/KEY_COL7/ ENET_COL LPC3220_30_40_50_1 Preliminary data sheet Rev. 01 — 6 February 2009 12 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol Pin description …continued Pin B15 N17 A12 A11 D9 Power supply domain VDD_IOD VDD_IOA VDD_IOD VDD_IOD VDD_IOD Type I I I I I/O I/O I/O O O C11 VDD_IOD I/O I/O I/O B11 VDD_IOD I/O I/O I/O E9 VDD_IOD I/O I/O I/O C3 D4 B14 VDD_IOC VDD_IOC VDD_IOD O O O O O D12 D8 B3 A16 A15 C13 C12 E11 VDD_IOD VDD_IOB VDD_IOC VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD O O O O O O O O O O O O O O O E8 VDD_IOB O Description General purpose input 19 UART 4 receive General purpose input 28 UART 3 ring indicator input General purpose input/output 0 General purpose input/output 1 General purpose input/output 2 Keyscan row 6 output Ethernet PHY interface clock General purpose input/output 3 Keyscan row 7 output Ethernet PHY interface data General purpose input/output 4 SSP1 Slave Select LCD data bit 22 General purpose input/output 5 SSP0 Slave Select Motor control channel 0 input General purpose output 0 Test clock 1 out General purpose output 1 General purpose output 2 Timer 1 match output 0 LCD data bit 0 General purpose output 3 LCD data bit 1 General purpose output 4 General purpose output 5 General purpose output 6 LCD data bit 18 General purpose output 7 LCD data bit 2 General purpose output 8 LCD data bit 8 General purpose output 9 LCD data bit 9 General purpose output 10 Motor control PWM channel 2, output B LCD panel power enable General purpose output 11 © NXP B.V. 2009. All rights reserved. GPI_19/U4_RX GPI_28/U3_RI GPIO_0 GPIO_1 GPIO_2/ KEY_ROW6/ ENET_MDC GPIO_3/ KEY_ROW7/ ENET_MDIO GPIO_4/ SSEL1/ LCDVD[22] GPIO_5/ SSEL0/ MCI0 GPO_0/ TST_CLK1 GPO_1 GPO_2/ MAT1[0]/ LCDVD[0] GPO_3/ LCDVD[1] GPO_4 GPO_5 GPO_6/ LCDVD[18] GPO_7/ LCDVD[2] GPO_8/ LCDVD[8] GPO_9/ LCDVD[9] GPO_10/ MCOB2/ LCDPWR GPO_11 LPC3220_30_40_50_1 Preliminary data sheet Rev. 01 — 6 February 2009 13 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol GPO_12/ MCOA2/ LCDLE GPO_13/ MCOB1/ LCDDCLK GPO_14 GPO_15/ MCOA1/ LCDFP Pin description …continued Pin B12 Power supply domain VDD_IOD Type O O O B13 VDD_IOD O O O D3 A14 VDD_IOC VDD_IOD O O O O D10 VDD_IOD O O O N18 D11 VDD_IOA VDD_IOD O O O O C2 B2 A13 VDD_IOC VDD_IOC VDD_IOD O O O O O E10 VDD_IOD O O O M16 VDD_IOA O O O H16 A5 B6 A3 E4 A4 E7 B4 VDD_IOD VDD_IOB VDD_IOB VDD_IOC VDD_IOC VDD_IOB VDD_IOB VDD_IOB O O I/O T I/O T I/O T I/O T I/O O I/O O I/O I/O Description General purpose output 12 Motor control PWM channel 2, output A LCD line end signal General purpose output 13 Motor control PWM channel 1, output B LCD clock output General purpose output 14 General purpose output 15 Motor control PWM channel 1, output A LCD frame/sync pulse General purpose output 16 Motor control PWM channel 0, output B LCD STN AC bias/TFT data enable General purpose output 17 General purpose output 18 Motor control PWM channel 0, output A LCD line sync/horizontal sync General purpose output 19 General purpose output 20 General purpose output 21 UART 4 transmit LCD data bit 3 General purpose output 22 HS UART 7 RTS out LCD data bit 14 General purpose output 23 HS UART 2 RTS out UART 3 RTS out Core voltage control out LCD data bit 17 I2C1 serial clock input/output I2C1 serial data input/output I2C2 serial clock input/output I2C2 serial data input/output I2S1 transmit clock Timer 3 match output 0 I2S1 transmit data Timer 3 match output 1 I2S1 transmit word select Timer 3 capture input 0 © NXP B.V. 2009. All rights reserved. GPO_16/ MCOB0/ LCDENAB/LCDM GPO_17 GPO_18/ MCOA0/ LCDLP GPO_19 GPO_20 GPO_21/ U4_TX/ LCDVD[3] GPO_22/ U7_HRTS/ LCDVD[14] GPO_23/ U2_HRTS/ U3_RTS HIGHCORE/ LCDVD[17] I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA I2S1TX_CLK/ MAT3[0] I2S1TX_SDA/ MAT3[1] I2S1TX_WS/ CAP3[0] LPC3220_30_40_50_1 Preliminary data sheet Rev. 01 — 6 February 2009 14 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol Pin description …continued Pin H17 H18 H14 J16 J15 G18 F15 E16 Power supply domain VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD Type I: PU O I I: PU O I: PU I I I I I D17 D18 G15 F16 E15 E14 F14 D16 C17 C18 A6 A8 A7 B8 VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD I I I I I I I I I/O T I/O T I/O T I/O T I/O T I/O T I/O T I/O T I/O T I/O T I/O T I/O T I/O: P O I/O: P O I/O: P O I/O: P O Description JTAG1 reset input JTAG1 return clock out JTAG1 clock input JTAG1 data input JTAG1 data out TAG1 test mode select input Keyscan column 0 input Ethernet transmit clock Keyscan column 1 input, Ethernet receive clock (MII mode) Ethernet reference clock (RMII mode) Keyscan column 2 input Ethernet receive error input Keyscan column 3 input Ethernet carrier sense input Keyscan column 4 input Ethernet receive data 0 Keyscan column 5 input Ethernet receive data 1 Keyscan row 0 out Ethernet transmit error Keyscan row 1 out Ethernet transmit data 2 Keyscan row 2 out Ethernet transmit data 3 Keyscan row 3 out Ethernet transmit enable Keyscan row 4 out Ethernet transmit data 0 Keyscan row 5 out Ethernet transmit data 1 MS/SD card command out Timer 2 match output 1 MS/SD card data 0 Timer 0 match output 0 MS/SD card data 1 Timer 0 match output 1 MS/SD card data 2 Timer 0 match output 2 JTAG_NTRST JTAG_RTCK JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS KEY_COL0/ ENET_TX_CLK KEY_COL1/ ENET_RX_CLK/ ENET_REF_CLK KEY_COL2/ ENET_RX_ER KEY_COL3/ ENET_CRS KEY_COL4/ ENET_RXD0 KEY_COL5/ ENET_RXD1 KEY_ROW0/ ENET_TX_ER KEY_ROW1/ ENET_TXD2 KEY_ROW2/ ENET_TXD3 KEY_ROW3/ ENET_TX_EN KEY_ROW4/ ENET_TXD0 KEY_ROW5/ ENET_TXD1 MS_BS/MAT2[1] MS_DIO0/MAT0[0] MS_DIO1/ MAT0[1] MS_DIO2/ MAT0[2] LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 15 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol MS_DIO3/ MAT0[3] MS_SCLK/ MAT2[0] n.c. Pin description …continued Pin C8 B7 B17, U17, U2 Power supply domain VDD_IOD VDD_IOD Type I/O: P O I/O O Description MS/SD card data 3 Timer 0 match output 3 MS/SD card clock output Timer 2 match output 0 not connected ONSW P0[0]/ I2S1RX_CLK P0[1]/ I2S1RX_WS P0[2]/ I2S0RX_SDA/ LCDVD[4] P0[3]/ I2S0RX_CLK/ LCDVD[5] P0[4]/ I2S0RX_WS/ LCDVD[6] P0[5]/ I2S0TX_SDA/ LCDVD[7] P0[6]/ I2S0TX_CLK/ LCDVD[12] P0[7]/ I2S0TX_WS/ LCDVD[13] PLL397_LOOP PWM_OUT1/ LCDVD[16] PWM_OUT2/INTSTAT/ LCDVD[19] RESET RESOUT RTCX_IN RTCX_OUT M15 B5 D7 M17 VDD_RTC VDD_IOB VDD_IOB VDD_IOA O I/O I/O I/O I/O I/O I/O I/O RTC match output for external power control Port 0 GPIO bit 0 I2S1 receive clock Port 0 GPIO bit 1 I2S1 receive word select Port 0 GPIO bit 2 I2S0 receive data LCD data bit 4 Port 0 GPIO bit 3 I2S0 receive clock LCD data bit 5 Port 0 GPIO bit 4 I2S0 receive word select LCD data bit 6 Port 0 GPIO bit 5 I2S0 transmit data LCD data bit 7 Port 0 GPIO bit 6 I2S0 transmit clock LCD data bit 12 Port 0 GPIO bit 7 I2S0 transmit word select LCD data bit 13 M18 VDD_IOA I/O I/O I/O L15 VDD_IOA I/O I/O I/O L16 VDD_IOA I/O I/O I/O L17 VDD_IOA I/O I/O I/O L18 VDD_IOA I/O I/O I/O R14 D14 D15 M14 G4 P16 P17 VDD_AD VDD_IOD VDD_IOD VDD_RTC VDD_IOC VDD_RTC VDD_RTC analog filter PLL397 loop filter (for external components) O O O O I O analog in analog out PWM1 out LCD data bit 16 PWM2 output/internal interrupt status[1] LCD data bit 19 Reset input, active LOW Reset out. Reflects external and WDT reset RTC oscillator input RTC oscillator output LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 16 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol SPI1_CLK/ SCK0 Pin description …continued Pin C9 C10 Power supply domain VDD_IOD VDD_IOD Type O O I/O I/O I/O I B9 VDD_IOD I/O I/O I B10 VDD_IOD I/O I/O I/O A9 VDD_IOD I/O I/O I/O A10 VDD_IOD I/O I/O I/O I/O Description SPI1 clock out SSP0 clock out SPI1 data in SSP0 MISO General purpose input bit 25 Motor control channel 1 input SPI1 data out (and optional input) SSP0 MOSI Motor control channel 2 input SPI2 clock out SSP1 clock out LCD data bit 23 SPI2 data out (and optional input) SSP1 MOSI LCD data bit 20 SPI2 data in SSP1 MISO LCD data 21 General purpose input bit 27 Clock request out for external clock source LCD data bit 15 System clock oscillator input System clock oscillator output Touchscreen X output Touchscreen Y output Test clock 2 out HS UART 1 receive Timer 1 capture input 0 General purpose input bit 15 HS UART 1 transmit HS UART 2 Clear to Send input UART 3 Clear to Send General purpose input bit 16 HS UART 2 receive UART 3 data set ready General purpose input bit 17 HS UART 2 transmit UART 3 data terminal ready out UART 3 receive General purpose input bit 18 © NXP B.V. 2009. All rights reserved. SPI1_DATIN/ MISO0/ GPI_25/ MCI1 SPI1_DATIO/ MOSI0/ MCI2 SPI2_CLK/ SCK1/ LCDVD[23] SPI2_DATIO/ MOSI1/ LCDVD[20] SPI2_DATIN/ MISO1/ LCDVD[21]/ GPI_27 SYSCLKEN/ LCDVD[15] SYSX_IN SYSX_OUT TS_XP TS_YP TST_CLK2 U1_RX/CAP1[0]/ GPI_15 G17 T17 R15 R13 U16 C6 K15 VDD_IOD VDD_AD VDD_AD VDD_AD VDD_AD VDD_IOB VDD_IOA I/O T I/O T analog in analog out I/O I/O O I/O I/O I/O U1_TX U2_HCTS/ U3_CTS/GPI_16 K16 J18 VDD_IOA VDD_IOA O I/O I I/O U2_RX/ U3_DSR/GPI_17 K18 VDD_IOA I/O I/O I/O U2_TX/U3_DTR U3_RX/ GPI_18 LPC3220_30_40_50_1 K17 J14 VDD_IOA VDD_IOD O O I/O I/O Preliminary data sheet Rev. 01 — 6 February 2009 17 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol U3_TX U5_RX/ GPI_20 U5_TX U6_IRRX/ GPI_21 U6_IRTX Pin description …continued Pin J17 F18 H15 F17 G16 G13 Power supply domain VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD VDD_IOD Type O I/O I O I/O I O I I I I E17 VDD_IOD I/O I/O I/O I/O E18 VDD_IOD O O O C4 D5 E5 E6 D6 C5 N12, N13 G7, G9, G11, J7, J12, M7, M11 L12, M13 VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_IOC VDD_AD VDD_CORE I I/O: P I/O: P I/O T I/O T I/O I/O: P I/O: P power power Description UART 3 transmit UART 5 receive General purpose input bit 20 UART 5 transmit UART 6 receive (with IrDA) General purpose input bit 21 UART 6 transmit (with IrDA) HS UART 7 CTS in Timer 0 capture input 1 LCD panel clock in General purpose input bit 22 HS UART 7 receive Timer 0 capture input 0 LCD data bit 10 General purpose input bit 23 HS UART 7 transmit Timer 1 match output 1 LCD data bit 11 Interrupt from USB ATX USB transmit data, D+ receive UART 5 receive I2C clock for USB ATX interface I2C data for USB ATX interface USB transmit enable for DAT/SE0 USB single ended zero transmit, D− Receive UART 5 transmit 3.3 V supply for ADC/touch screen 1.2 V (or 0.9 V) supply for core U7_HCTS/ CAP0[1]/ LCDCLKIN/ GPI_22 U7_RX/ CAP0[0]/ LCDVD[10]/ GPI_23 U7_TX/ MAT1[1]/ LCDVD[11] USB_ATX_INT USB_DAT_VP/ U5_RX USB_I2C_SCL USB_I2C_SDA USB_OE_TP USB_SE0_VM/ U5_TX VDD_AD VDD_CORE VDD_COREFXD VDD_COREFXD power Fixed 1.2 V supply for core LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 18 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol VDD_EMC Pin description …continued Pin J6, K6, K7, L6, M6, M8, N7, N8, N9 N10, N11 H13, J13 F8 Power supply domain VDD_EMC Type power Description 1.8 V or 2.5 V or 3.3 V supply for External Memory Controller (EMC) VDD_IOA VDD_IOB VDD_IOC VDD_IOA VDD_IOB power power power 1.8 V or 3.3 V supply for IOA domain 1.8 V or 3.3 V supply for IOB domain 1.8 V or 3.3 V supply for IOC domain F7, VDD_IOC G6, H6, J5 F13, F9 T18 T16 R17 P15 N14 K14 L13 N15 P13 G8, G10, G12, H7, K12, L7, M9, M10, M12 K5, L5, M5, N5, N6, P6, P7, P8, P9, P10, P11 K13 VDD_IOD VDD_IOD VDD_PLL397 VDD_PLLHCLK VDD_PLLUSB VDD_FUSE VDD_RTC VDD_RTCCORE VDD_RTCOSC - VDD_IOD VDD_OSC VDD_PLL397 VDD_PLLHCLK VDD_PLLUSB VDD_FUSE VDD_RTC VDD_RTCCORE VDD_RTCOSC VSS_AD VSS_CORE power power power power power power power power power power power 1.8 V to 3.3 V supply for IOD domain 1.2 V supply for main oscillator 1.2 V supply for 397x PLL 1.2 V supply for HCLK PLL 1.2 V supply for USB PLL 1.2 V supply 1.2 V supply for RTC I/O 1.2 V supply for RTC 1.2 V supply for RTC oscillator Ground for ADC/touch screen Ground for core VSS_EMC - power Ground for EMC VSS_IOA LPC3220_30_40_50_1 - power Ground for 1.8 V or 3.3 V I/O © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 19 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 4. Symbol VSS_IOB VSS_IOC Pin description …continued Pin F6 F5, G5, H5 F10, F11, F12, H12 P14 T15 R18 R16 L14 P18 Power supply domain Type power power Description Ground for 1.8 V or 3.3 V I/O for GPI_6, GPO_4, GPO_11, I2C1 Ground IOC domain VSS_IOD - power Ground IOD domain VSS_OSC VSS_PLL397 VSS_PLLHCLK VSS_PLLUSB VSS_RTCCORE VSS_RTCOSC [1] - power power power power power power Ground for main oscillator Ground for 397x PLL Ground for HCLK PLL Ground for USB PLL Ground for RTC Ground for RTC oscillator The PWM2_CTRL register controls this pin function (see LPC32x0 User manual). Table 5. Parameter I/O type Digital I/O pad types[1] Abbreviation I = input. O = output. I/O = bidirectional. I/O T = bidirectional or high impedance. Pin detail BK: pin has a bus keeper function that weakly retains the last level driven on an I/O pin when it is switched from output to input. PU: pin has a nominal 50 µA internal pull-up connected. PD: pin has a nominal 50 µA internal pull-down connected. P: pin has programmable input characteristics. [1] See LPC32x0 User manual for details. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 20 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7. Functional description 7.1 CPU and subsystems 7.1.1 CPU NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented a 32 kB instruction cache, a 32 kB data cache and a Vector Floating Point coprocessor. The ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the virtual memory capabilities required to support the multi-programming demands of modern operating systems. The basic ARM926EJ-S core V5TE instruction set includes DSP instruction extensions for native Jazelle Java Byte-code execution in hardware. The LPC3220/30/40/50 operates at CPU frequencies up to 266 MHz. 7.1.2 Vector Floating Point (VFP) coprocessor The LPC3220/30/40/50 includes a VFP co-processor providing full support for single-precision and double-precision add, subtract, multiply, divide, and multiply-accumulate operations at CPU clock speeds. It is compliant with the IEEE 754 standard for binary Floating-Point Arithmetic. This hardware floating point capability makes the microcontroller suitable for advanced motor control and DSP applications. The VFP has 3 separate pipelines for Floating-point MAC operations, divide or square root operations, and Load/Store operations. These pipelines operate in parallel and can complete execution out of order. All single-precision instructions execute in one cycle, except the divide and square root instructions. All double-precision multiply and multiply-accumulate instructions take two cycles. The VFP also provides format conversions between floating-point and integer word formats. 7.1.3 Emulation and debugging The LPC3220/30/40/50 supports emulation and debugging via a dedicated JTAG serial port. An Embedded Trace Buffer allows tracing program execution. The dedicated JTAG port allows debugging of all chip features without impact to any pins that may be used in the application. 7.1.3.1 Embedded ICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an Embedded ICE protocol converter. The Embedded ICE protocol converter converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel (DCC) function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or entering the debug state. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 21 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.1.3.2 Embedded trace buffer The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses the trace information and exports it through a narrow trace port. An internal Embedded Trace Buffer (ETB) of 2048 × 24 bits captures the trace information under software debugger control. Data from the ETB is recovered by the debug software through the JTAG port. The trace contains information about when the ARM core switches between states. Instruction shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. For data accesses either data or address or both can be traced. 7.2 AHB matrix The LPC3220/30/40/50 has a multi-layer AHB matrix for inter-block communication. AHB is an ARM defined high-speed bus, which is part of the ARM bus architecture. AHB is a high-bandwidth low-latency bus that supports multi-master arbitration and a bus grant/request mechanism. For systems that have only one (CPU), or two (CPU and DMA) bus masters a simple AHB works well. However, if a system requires multiple bus masters and the CPU needs access to external memory, a single AHB bus can cause a bottleneck. To increase performance, the LPC3220/30/40/50 uses an expanded AHB architecture known as Multi-layer AHB. A Multi-layer AHB replaces the request/grant and arbitration mechanism used in a simple AHB with an interconnect matrix that moves arbitration out toward the slave devices. Thus, if a CPU and a DMA controller want access to the same memory, the interconnect matrix arbitrates between the two when granting access to the memory. This advanced architecture allows simultaneous access by bus masters to different resources with an increase in arbitration complexity. In this architectural implementation, removing guaranteed central arbitration and allowing more than one bus master to be active at the same time provides better overall microcontroller performance. In the LPC3220/30/40/50, the multi-Layer AHB system has a separate bus for each of seven AHB Masters: • • • • • • • CPU data bus CPU instruction bus General purpose DMA Master 0 General purpose DMA Master 1 Ethernet controller USB controller LCD controller There are no arbitration delays unless two masters attempt to access the same slave at the same time. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 22 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions. A write access to FAB peripherals takes a single AHB clock and a read access to FAB peripherals takes two AHB clocks. 7.3 Physical memory map The physical memory map incorporates several distinct regions, as shown in Figure 3. When an application is running, the CPU interrupt vectors are re-mapped to allow them to reside in on-chip SRAM (IRAM). LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 23 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 4.0 GB RESERVED EMC_CS3 EMC_CS2 EMC_CS1 EMC_CS0 RESERVED 0xFFFF FFFF 0xE400 0000 0xE3FF FFFF 0xE300 0000 0xE2FF FFFF 0xE200 0000 0xE1FF FFFF 0xE100 0000 0xE0FF FFFF 0xE000 0000 0xDFFF FFFF 0xC000 0000 0xBFFF FFFF EMC_DYSC1 EMC_DYSC0 0xA000 0000 0x9FFF FFFF 0x8000 0000 0x7FFF FFFF off-chip memory 2.0 GB RESERVED 0x5000 0000 0x4FFF FFFF RESERVED peripherals on AHB matrix slave port 7 APB peripherals 1.0 GB FAB peripherals 0x4008 0000 to 0x400F FFFF 0x4000 0000 to 0x4007 FFFF 0x4000 0000 0x3FFF FFFF peripherals on AHB matrix slave port 6 RESERVED AHB peripherals 768 MB 0x3000 0000 to 0x31FF FFFF 0x3000 0000 0x2FFF FFFF RESERVED peripherals on AHB matrix slave port 5 AHB peripherals APB peripherals AHB peripherals 0x200A 0000 to 0x200B FFFF 0x2008 0000 to 0x2009 FFFF 0x2000 0000 to 0x2007 FFFF 0x2000 0000 0x1FFF FFFF RESERVED 0x1000 0000 0x0FFF FFFF IROM IRAM on-chip memory dummy space for DMA IROM or IRAM 0.0 GB 0x0C00 0000 to 0x0FFF FFFF 0x0800 0000 to 0x0BFF FFFF 0x0400 0000 to 0x07FF FFFF 0x0000 0000 to 0x03FF FFFF 0x0000 0000 002aae468 Fig 3. LPC3220_30_40_50_1 LPC3220/30/40/50 memory map © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 24 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.4 Internal memory 7.4.1 On-chip ROM The built-in 16 kB ROM contains a program which runs a boot procedure to load code from one of four external sources, UART5, SSP0 (SPI mode), EMC Static CS0 memory, or NAND FLASH. After reset, execution always begins from the internal ROM. The bootstrap software first reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot and can download a program over serial link UART5 to IRAM and transfer execution to the downloaded code. If the SERVICE pin is HIGH, the bootstrap routine jumps to normal boot. The normal boot process first tests SPI memory for boot information if present it uploads the boot code and transfers execution to the uploaded software. If the SPI is not present or no software is loaded, the bootloader will test the EMC Static CS0 memory for the presence of boot code and if present boots from static memory, If this test fails the boot loader will test external NAND flash for boot code and boot if code is present. The boot loader consumes no user memory space because it is in ROM. 7.4.2 On-chip SRAM On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8, 16, or 32 bit memory. The LPC3220/30/40/50 provides 256 kB of internal SRAM. 7.5 External memory interfaces The LPC3220/30/40/50 includes three external memory interfaces, NAND Flash controllers, Secure Digital Memory Controller, and an external memory controller for SDRAM, DDR SDRAM, and Static Memory devices. 7.5.1 NAND flash controllers The LPC3220/30/40/50 includes two NAND flash controllers, one for multi-level cell NAND flash devices and one for single-level cell NAND flash devices. The two NAND flash controllers use the same pins to interface to external NAND flash devices, so only one interface is active at a time. 7.5.1.1 Multi-Level Cell (MLC) NAND flash controller The MLC NAND flash controller interfaces to either multi-level or single-level NAND flash devices. An external NAND flash device is used to allow the bootloader to automatically load a portion of the application code into internal SRAM for execution following reset. The MLC NAND flash controller supports small (528 byte) and large (2114 byte) pages. Programmable NAND timing parameters allow support for a variety of NAND flash devices. A built-in Reed-Solomon encoder/decoder provides error detection and correction capability. A 528 byte data buffer reduces the need for CPU supervision during loading. The MLC NAND flash controller also provides DMA support. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 25 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.5.1.2 Single-Level Cell (SLC) NAND flash controller The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page transfers are supported, including a 20 byte DMA read and write FIFO. Hardware support for ECC (Error Checking and Correction) is included for the main data area. Software can correct a single bit error. 7.5.2 SD card controller The SD interface allows access to external SD memory cards. The SD card interface conforms to the SD Memory Card Specification Version 1.01. 7.5.2.1 Features • 1-bit and 4-bit data line interface support. • DMA is supported through the system DMA controller. • Provides all functions specific to the SD memory card. These include the clock generation unit, power management control, command and data transfer. 7.5.3 External memory controller The LPC3220/30/40/50 includes a memory controller that supports data bus SDRAM, DDR SDRAM, and static memory devices. The memory controller provides an interface between the system bus and external (off-chip) memory devices. The controller supports 16-bit and 32-bit wide SDR SDRAM devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes, as well as 16-bit wide data bus DDR SDRAM devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes. Two dynamic memory chip selects are supplied, supporting two groups of SDRAM: • DYCS0 in the address range 0x8000 0000 to 0x9FFF FFFF • DYCS1 in the address range 0xA000 0000 to 0xBFFF FFFF The memory controller also supports 8-bit, 16-bit, and 32-bit wide asynchronous static memory devices, including RAM, ROM, and flash, with or without asynchronous page mode. Four static memory chip selects are supplied for SRAM devices: • • • • CS0 in the address range 0xE000 0000 to 0xE0FF FFFF CS1 in the address range 0xE100 0000 to 0xE1FF FFFF CS2 in the address range 0xE200 0000 to 0xE2FF FFFF CS3 in the address range 0xE300 0000 to 0xE3FF FFFF The SDRAM controller uses three data ports to allow simultaneous requests from multiple on-chip AHB bus masters and has the following features. • Dynamic memory interface supports SDRAM, DDR-SDRAM, and low-power variants. • Read and write buffers to reduce latency and improve performance. • Static memory features include – asynchronous page mode read – programmable wait states – bus turnaround cycles – output enable and write enable delays LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 26 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers – extended wait • Power-saving modes dynamically control MPMCCKEOUT and MPMCCLKOUT. • Dynamic memory self-refresh mode supported by software. • Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is, typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16, or 32 data bits per device. • Two reset domains enable dynamic memory contents to be preserved over a soft reset. • This controller does not support synchronous static memory devices (burst mode devices). 7.6 AHB master peripherals The LPC3220/30/40/50 implements four AHB master peripherals, which include a General Purpose Direct Memory Access (GPDMA) controller, a 10/100 Ethernet Media Access Controller (MAC), a Universal Serial Bus (USB) controller, and an LCD controller. Each of these four peripherals contain an integral DMA controller optimized to support the performance demands of the peripheral. 7.6.1 General Purpose DMA (GPDMA) controller The GPDMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the same AHB master, or one area by each master. The DMA controller supports the following peripheral device transfers. • • • • • • Secure Digital (SD) Memory interface High-speed UARTs I2S0 and I2S1 ports SPI1 and SPI2 interfaces SSP0 and SSP1 interfaces Memory The DMA controls eight DMA channels with hardware prioritization. The DMA controller interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian. Incrementing or non-incrementing addressing for source and destination are supported, as well as programmable DMA burst size. Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. 7.6.2 Ethernet MAC The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 27 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.6.2.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. Wake-on-LAN power management support allows system wake-up using the receive filters or a magic frame detection filter. • Physical interface – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.6.3 USB interface The LPC3220/30/40/50 supports USB in either device, host, or OTG configuration. 7.6.3.1 USB device controller The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 28 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers condition is indicated via status registers. An interrupt is also generated if enabled. The DMA controller when enabled transfers data between the endpoint buffer and the USB RAM. Features • • • • • • • • • • • 7.6.3.2 Fully compliant with USB 2.0 full-speed specification. Supports 32 physical (16 logical) endpoints. Supports control, bulk, interrupt and isochronous endpoints. Scalable realization of endpoints at run time. Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. RAM message buffer size based on endpoint realization and maximum packet size. Supports bus-powered capability with low suspend current. Supports DMA transfer on all non-control endpoints. One duplex DMA channel serves all endpoints. Allows dynamic switching between CPU controlled and DMA modes. Double buffer implementation for bulk and isochronous endpoints. USB host controller The host controller enables data exchange with various USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies to the OHCI specification. Features • OHCI compliant. • OHCI specifies the operation and interface of the USB host controller and software driver. • The host controller has four USB states visible to the software driver: – USBOperational: Process lists and generate SOF tokens. – USBReset: Forces reset signaling on the bus, SOF disabled. – USBSuspend: Monitor USB for wake-up activity. – USBResume: Forces resume signaling on the bus. • HCCA register points to interrupt and isochronous descriptors list. • ControlHeadED and BulkHeadED registers point to control and bulk descriptors list. 7.6.3.3 USB OTG controller USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. Features • Fully compliant with On-The-Go supplement to the USB Specification 2.0 Revision 1.0. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 29 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers • Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices under software control. HNP is partially implemented in hardware. • Provides programmable timers required for HNP and SRP. • Supports slave mode operation through AHB slave interface. • Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG specification compliant ATX. 7.6.4 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024 × 768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.6.4.1 Features • • • • AHB bus master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320 × 200, 320 × 240, 640 × 200, 640 × 240, 640 × 480, 800 × 600, and 1024 × 768. Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 k color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized, for color STN and TFT. 24 bpp true-color non-palettized, for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128 × 32 bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock or from a clock input pin. • • • • • • • • • • • • LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 30 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.7 System functions To enhance the performance of the LPC3220/30/40/50 incorporates the following system functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and several power control features. These functions are described in the following sections 7.7.1 Interrupt controller The interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled and configured for high or low level triggering, or rising or falling edge triggering. Each interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt status and masked interrupt status registers allow versatile condition evaluation. In addition to peripheral functions, each of the six general purpose input/output pins and 12 of the 22 general purpose input pins are connected directly to the interrupt controller. 7.7.2 Watchdog timer The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit counter. A match register is compared to the Timer. When configured for watchdog functionality, a match drives the match output low. The match output is gated with an enable signal that gives the opportunity to generate two type of reset signal: one that only resets chip internally, and another that goes through a programmable pulse generator before it goes to the external pin RESOUT and to the internal chip reset. 7.7.2.1 Features • • • • • • Programmable 32-bit timer. Internally resets the device if not periodically reloaded. Flag to indicate that a watchdog reset has occurred. Programmable watchdog pulse output on RESOUT pin. Can be used as a standard timer if watchdog is not used. Pause control to stop counting when core is in debug state. 7.7.3 Millisecond timer The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to obtain a lower count rate. The millisecond timer includes three match registers that are compared to the Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter either continue to run, stop, or be reset. 7.7.3.1 Features • 32-bit Timer/Counter, running from the 32 kHz RTC clock. • Counter or Timer operation. • Three 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Pause control to stop counting when core is in debug state. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 31 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.7.4 Clocking and power control features 7.7.4.1 Clocking Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed and some peripherals do this automatically. The LPC3220/30/40/50 supports three operational modes, two of which are specifically designed to reduce power consumption. The modes are: Run mode, Direct run mode, and Stop mode.These three operational modes give control over processing speed and power consumption. In addition, clock rates to different functional blocks may be changed by switching clock sources, changing PLL values, or altering clock divider configurations. This allows a trade-off of power versus processing speed based on application requirements. 7.7.4.2 Crystal oscillator The main oscillator is the basis for the clocks most chip functions use by default. Optionally, many functions can be clocked instead by the output of a PLL (with a fixed 397x rate multiplication) which runs from the RTC oscillator. In this mode, the main oscillator may be turned off unless the USB interface is enabled. If a SYSCLK frequency other than 13 MHz is required in the application, or if the USB block is not used, the main oscillator may be used with a frequency of between 1 MHz and 20 MHz. 7.7.4.3 PLLs The LPC3220/30/40/50 includes three PLLs: The 397x PLL allows boosting the RTC frequency to 13.008896 MHz for use as the primary system clock. The USB PLL provides the 48 MHz clock required by the USB block, and the HCLK PLL provides the basis for the CPU clock, the AHB bus clock, and the main peripheral clock. The 397x PLL multiplies the 32768 Hz RTC clock by 397 to obtain a 13.008896 MHz clock. The 397x PLL is designed for low power operation and low jitter. This PLL requires an external RC loop filter for proper operation. The HCLK PLL accepts an input clock from either the main oscillator or the output of the 397x PLL. The USB PLL only accepts an input clock from the main oscillator.The USB input clock runs through a divide-by-N pre-divider before entering the USB PLL. The input to the HCLK and USB PLLs may initially be divided down by a pre-divider value ‘N’, which may have the values 1, 2, 3, or 4. This pre-divider can allow a greater number of possibilities for the output frequency. Following the PLL input divider is the PLL multiplier. This can multiply the pre-divider output by a value ‘M’, in the range of 1 through 256. The resulting frequency must be in the range of 156 MHz to 320 MHz. The multiplier works by dividing the output of a Current Controlled Oscillator (CCO) by the value of M, then using a phase detector to compare the divided CCO output to the pre-divider output. The error value is used to adjust the CCO frequency. At the PLL output, there is a post-divider that can be used to bring the CCO frequency down to the desired PLL output frequency. The post-divider value can divide the CCO output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 32 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers output to be used directly. The maximum PLL output frequency supported by the CPU is 266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock has strict requirements for nominal frequency (500 ppm) and jitter (500 ps). 7.7.4.4 Power control modes The LPC3220/30/40/50 supports three operational modes, two of which are specifically designed to reduce power consumption. The modes are: Run mode, Direct Run mode, and Stop mode. Run mode is the normal operating mode for applications that require the CPU, AHB bus, or any peripheral function other than the USB block to run faster than the main oscillator frequency. In Run mode, the CPU can run at up to 266 MHz and the AHB bus can run at up to 133 MHz. Direct Run mode allows reducing the CPU and AHB bus rates in order to save power. Direct Run mode can also be the normal operating mode for applications that do not require the CPU, AHB bus, or any peripheral function other than the USB block to run faster than the main oscillator frequency. Direct Run mode is the default mode following chip reset. Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals other than the USB block. 7.7.4.5 Reset Reset is accomplished by an active LOW signal on the RESET input pin. A reset pulse with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the oscillator to start up and stabilize after VDD reaches operational voltage. An internal reset with a minimum duration of 10 clock pulses will also be applied if the watchdog timer generates an internal device reset. The RESET pin is located in the RTC power domain. This means that the RTC power must be present for an external reset to have any effect. The RTC power domain nominally runs from 1.2 V, but the RESET pin can be driven as high as 1.95 V. 7.8 Communication peripheral interfaces In addition to the Ethernet MAC and USB interfaces there are many more serial communication peripheral interfaces available on the LPC3220/30/40/50. Here is a list of the serial communication interfaces: • • • • • Seven UARTs; four standard UARTs and three high-speed UARTs Two SPI serial I/O controllers Two SSP serial I/O controllers Two I2C serial I/O controllers Two I2S audio controllers A short functional description of each of these peripherals is provided in the following sections. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 33 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.8.1 UARTs The LPC3220/30/40/50 contains seven UARTs. Four are standard UARTs, and three are high-speed UARTs. 7.8.1.1 Standard UARTs The four standard UARTs are compatible with the INS16Cx50. These UARTs support rates up to 460800 bit/s from a 13 MHz peripheral clock. Features • • • • • Each standard UART has 64 byte Receive and Transmit FIFOs. Receiver FIFO trigger points at 16, 32 , 48 , and 60 Bytes. Transmitter FIFO trigger points at 0, 4 , 8, and 16 Bytes. Register locations conform to the “550” industry standard. Each standard UART has a fractional rate pre-divider and an internal baud rate generator. auto-clock mode shuts off the clock to the UART when it is idle. • The standard UARTs support three clocking modes: on, off, and auto-clock. The • UART 6 includes an IrDA mode to support infrared communication. • The standard UARTs are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800) bit/s. • Each UART includes an internal loopback mode. 7.8.1.2 High-speed UARTs The three high-speed UARTs are designed to support rates up to 921600 bit/s from a 13 MHz peripheral clock for on-board communication in low noise conditions. This is accomplished by changing the over sampling from 16× to 14× and altering the rate generation logic. Features • • • • • Each high-speed UART has 64 byte Receive and Transmit FIFOs. Receiver FIFO trigger points at 1, 4, 8, 16, 32, and 48 Byte. Transmitter FIFO trigger points at 0, 4, and 8 Byte. Each high-speed UART has an internal baud rate generator. The high-speed UARTs are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s. parity, and no flow control as a the communications protocol. • The three high speed UARTs only support (8N1) 8-bit data word length, 1-stop bit, no • Each UART includes an internal loopback mode. 7.8.2 SPI serial I/O controller The LPC3220/30/40/50 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire serial interface that is able to interface with a large range of serial peripheral or memory devices (SPI mode 0 to 3 compatible slave devices). LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 34 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. The SPI implementation on the LPC3220/30/40/50 does not support operation as a slave. 7.8.2.1 Features • • • • • • • • • • • • Supports slaves compatible with SPI modes 0 to 3. Half duplex synchronous transfers. DMA support for data transmit and receive. 1-bit to 16-bit word length. Choice of LSB or MSB first data transmission. 64 × 16-bit input or output FIFO. Bit rates up to 52 Mbit/s. Busy input function. DMA time out interrupt to allow detection of end of reception when using DMA. Timed interrupt to facilitate emptying the FIFO at the end of a transmission. SPI clock and data pins may be used as general purpose pins if the SPI is not used. Slave selects can be supported using GPO or GPIO pins 7.8.3 SSP serial I/O controller The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.8.3.1 Features • Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses • • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame Maximum SPI bus data bit rate of 1⁄2 (Master mode) and 1⁄12 (Slave mode) of the input clock rate • DMA transfers supported by GPDMA 7.8.4 I2C-bus serial I/O controller There are two I2C-bus interfaces in the LPC32x0 family of controllers. These I2C blocks can be configured as a master, multi-master or slave supporting up to 400 kHz. The I2C blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit and receive. An interrupt signal is available from each block. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 35 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are only available when the controller is configured as a Master/Slave device and is operating in a multi-master environment. Separate TX FIFOs are needed in a multi-master because a controller might have a message queued for transmission when an external master addresses it to be come a slave-transmitter, a second source of data is needed. Note that the I2C clock must be enabled in the I2CCLK_CTRL register before using the I2C. The I2C clock can be disabled between communications, if used as a single master I2C-bus interface, software has full control of when I2C communication is taking place on the bus. 7.8.4.1 Features • The two I2C-bus blocks are standard I2C-bus compliant interfaces that may be used in Single-master, Multi-master or Slave modes. • Programmable clock to allow adjustment of I2C-bus transfer rates. • Bidirectional data transfer. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. 7.8.5 I2S-bus audio controller The I2S-bus provides a standard communication interface for digital audio applications The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. Each I2S connection can act as a master or a slave. The master connection determines the frequency of the clock line and all other slaves are driven by this clock source. The two I2S-bus interfaces on the LPC3220/30/40/50 provides a separate transmit and receive channel, providing a total of two transmit channels and two receive channels. Each I2S channel supports monaural or stereo formatted data. 7.8.5.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • Supports standard sampling frequencies (8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz). • Word select period can be configured in master mode (separately for I2S input and output). • Two 8 word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop, and mute options separately for I2S input and I2S output. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 36 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.9 Other peripherals In addition to the communication peripherals there are many general purpose peripherals available in the LPC3220/30/40/50. Here is a list of the general purpose peripherals. • • • • • • • • GPI/O Keyboard scanner Touch screen controller and 10-bit Analog-to-Digital-Converter Real-time clock High-speed timer Four general purpose 32-bit timer/external event counters Two simple PWMs One motor control PWM A short functional description of each of these peripherals is provided in the following sections. 7.9.1 General purpose parallel I/O Some device pins that are not dedicated to a specific peripheral function have been designed to be general purpose inputs, outputs, or input/outputs. Also, some pins may be configured either as a specific peripheral function or a general purpose input, output, or input/output. A total of 51 pins can potentially be used as general purpose input/outputs, 24 as general purpose outputs, and 22 as general purpose inputs. GPIO pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of GPIO and GPO outputs controlled by that register simultaneously. The value of the output register for standard GPIOs and GPO pins may be read back, as well as the current actual state of the port pins. In addition to GPIO pins on port 0, port 1, and port 2, there are 22 GPI, 24 GPO, and six GPIO pins. When the SDRAM bus is configured for 16 data bits, 13 of the remaining SDRAM data pins may be used as GPIOs. 7.9.1.1 Features • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • A single register selects direction for pins that support both input and output modes. • Direction control of individual bits. • For input/output pins, both the programmed output state and the actual pin state can be read. • There are a total of 12 general purpose inputs, 24 general purpose outputs, and six general purpose input/outputs. • Additionally, 13 SDRAM data lines may be used as GPIOs if a 16-bit SDRAM interface is used (rather than a 32-bit interface). LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 37 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.9.2 Keyboard scanner The keyboard scanner function can automatically scan a keyboard of up to 64 keys in an 8 × 8 matrix. In operation, the keyboard scanner’s internal state machine will normally be in an idle state, with all KEY_ROWn pins set high, waiting for a change in the column inputs to indicate that one or more keys have been pressed. When a keypress is detected, the matrix is scanned by setting one output pin high at a time and reading the column inputs. After de-bouncing, the keypad state is stored and an interrupt is generated. The keypad is then continuously scanned waiting for ‘extra key pressed’ or ‘key released’. Any new keypad state is scanned and stored into the matrix registers followed by a new interrupt request to the interrupt controller. It is possible to detect and separate up to 64 multiple keys pressed. 7.9.2.1 Features • Supports up to 64 keys in 8 × 8 matrix. • Programmable de-bounce period. • A key press can wake up the CPU from Stop mode. 7.9.3 Touch screen controller and 10-bit ADC The LPC3220/30/40/50 microcontrollers includes Touch Screen Controller (TSC) hardware, which automatically measures and determines the X and Y coordinates where a touch screen is pressed. In addition, the TSC can measure an analog input signal on the AUX_IN pin. Optionally, the TSC can operate as an Analog-to-Digital Converter (ADC). The ADC supports three channels and uses 10-bit successive approximation to produce results with a resolution of 10 bits in 11 clock cycles. The analog portion of the ADC has its own power supply to enhance the low noise characteristics of the converter. This voltage is only supplied internally when the core has voltage. However, the ADC block is not affected by any difference in ramp-up time for VDD_AD and VDD_CORE voltage supplies. 7.9.3.1 Features • • • • • Measurement range of 0 V to VDD_AD (nominally 3.3 V). Low noise ADC. 10-bit resolution. Three input channels. Uses 32 kHz RTC clock or peripheral clock. 7.9.4 Real-Time Clock (RTC) and battery RAM The RTC runs at 32768 Hz using a very low power oscillator. The RTC counts seconds and can generate alarm interrupts that can wake up the device from Stop mode. The RTC clock can also clock the 397x PLL, the Millisecond Timer, the ADC, the Keyboard Scanner and the PWMs. The RTC up-counter value represents a number of seconds elapsed since second 0, which is an application determined time. The RTC counter will reach maximum value after about 136 years. The RTC down-counter is initiated with all ones. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 38 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Two 32-bit match registers are readable and writable by the processor. A match will result in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be triggered by a match event, and cause an external power supply to turn on all of the operating voltages, as a way to startup after power has been removed. The RTC block is implemented in a separate voltage domain. The block is supplied via a separate supply pin from a battery or other power source. The RTC block also contains 32 words (128 Bytes) of very low voltage SRAM. This SRAM is able to hold its contents down to the minimum RTC operating voltage. 7.9.4.1 Features • • • • • Measures the passage of time in seconds. 32-bit up and down seconds counters. Ultra-low power design to support battery powered systems. Dedicated 32 kHz oscillator. An output pin is included to assist in waking up when the chip has had power removed to all functions except the RTC. • Two 32-bit match registers with interrupt option. • 32 words (128 Bytes) of very low voltage SRAM. • The RTC and battery RAM power have an independent power domain and dedicated supply pins, which can be powered from a battery or power supply. Remark: The LPC3220/30/40/50 will run at voltages down to 0.9 V at frequencies below 14 MHz. However, the ARM core cannot access the RTC registers and battery RAM when the core supply voltage is at 0.9 V and the RTC supply is at 1.2 V. 7.9.5 Enhanced 32-bit timers/external event counters The LPC3220/30/40/50 includes six 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.9.5.1 Features • A 32-bit Timer/Counter with a programmable 32-bit pre-scaler. • Counter or Timer operation. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – continuous operation with optional interrupt generation on match – stop timer on match with optional interrupt generation – reset timer on match with optional interrupt generation • Up to four external outputs corresponding to match registers, with the following capabilities: LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 39 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers – set LOW on match – set HIGH on match – toggle on match – do nothing on match 7.9.6 High-speed timer The high-speed timer block is clocked by the main peripheral clock. The clock is first divided down in a 16-bit programmable pre-scale counter which clocks a 32-bit timer/counter. The high-speed timer includes three match registers that are compared to the timer/counter value. A match can generate an interrupt and cause the timer/counter to either continue to run, stop, or be reset. The high-speed timer also includes two capture registers that can take a snapshot of the timer/counter value when an input signal transitions. A capture event may also generate an interrupt. 7.9.6.1 Features • • • • 32-bit timer/counter with programmable 16-bit pre-scaler. Counter or timer operation. Two 32-bit capture registers. Three 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Pause control to stop counting when core is in debug state. 7.9.7 Pulse Width Modulators (PWMs) The LPC3220/30/40/50 provides two simple PWMs. They are clocked separately by either the main peripheral clock or the 32 kHz RTC clock. Both PWMs have a duty cycle programmable in 255 steps. 7.9.7.1 Features • • • • Clocked by the main peripheral clock or the 32 kHz RTC clock. Programmable 4-bit pre-scaler. Duty cycle programmable in 255 steps. Output frequency up to 50 kHz when using a 13 MHz peripheral clock. 7.9.8 Motor control pulse width modulator The Motor Control PWM (MCPWM) provides a set of features for three-phase AC and DC motor control applications in a single peripheral. The MCPWM can also be configured for use in other generalized timing, counting, capture, and compare applications. 7.9.8.1 Features • 32-bit timer • 32-bit period register LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 40 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers • • • • • 32-bit pulse-width (match) register 10-bit dead-time register and an associated 10-bit dead-time counter 32-bit capture register Two PWM (match) outputs (pins MCOA0/1/2 and MCOB0/1/2) with opposite polarities Period interrupt, pulse-width interrupt, and capture interrupt 8. Basic architecture The LPC3220/30/40/50 is a general purpose ARM926EJ-S 32-bit microprocessor with a 32 kB instruction cache and a 32 kB data cache. The microcontroller offers high performance and very low power consumption. The ARM architecture is based on RISC principles, which results in the instruction set and related decode mechanism being much simpler than equivalent micro programmed CISCs. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. The ARM926EJ-S core employs a 5-stage pipeline so processing and memory system accesses can occur continuously. At any one point in time, several operations are in progress: subsequent instruction fetch, next instruction decode, instruction execution, memory access, and write-back. The combination of architectural enhancements gives the ARM9 about 30 % better performance than an ARM7 running at the same clock rate: • Approximately 1.3 clocks per instruction for the ARM926 compared to 1.9 clocks per instruction for ARM7TDMI. • Approximately 1.1 Dhrystone MIPS/MHz for the ARM926 compared to 0.9 Dhrystone MIPS/MHz for ARM7TDMI. The ARM926EJ-S processor also employs an operational state known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb state is the use of a super-reduced instruction set. Essentially, the ARM926EJ-S processor core has two instruction sets: 1. The standard 32-bit ARM set 2. The 16-bit Thumb set The Thumb set’s smaller 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining many of ARM’s 32-bit performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates using the same 32-bit register set as ARM code. Thumb code size is up to 65 % smaller than ARM code size, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. Additionally, the ARM926EJ-S core includes enhanced DSP instructions and multiplier, as well as an enhanced 32-bit MAC block. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 41 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V2) VDD(EMC) Parameter supply voltage (1.2 V) external memory controller supply voltage input/output supply voltage analog input voltage input voltage supply current ground current storage temperature total power dissipation (per package) electrostatic discharge voltage max. junction temp 125 °C max. ambient temp 85 °C HBM CDM [1] [7] Conditions Notes Min [2] [3] Max +1.4 +4.6 +4.6 +4.6 +4.6 +2.4 +4.6 100 100 +150 1.12 +2000 +500 Unit V V V V V V V mA mA °C W V V −0.5 −0.5 −0.5 −0.5 −0.5 −0.5 −0.5 −65 VDDA(3V3) analog supply voltage (3.3 V) VDD(IO) VIA VI IDD ISS Tstg Ptot(pack) Vesd [4] [5] 1.8 V pins 3.3 V pins per supply pin per ground pin [6] [6] [8] [9] The following applies to Table 6: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Core, PLL, oscillator, and RTC supplies; applies to pins VDD_CORE, VDD_COREFXD, VDD_OSC, VDD_PLL397, VDD_PLLHCLK, VDD_PLLUSB, VDD_RTC, VDD_RTCCORE, and VDD_RTCOSC. I/O pad supply; applies to domains VDD_EMC and VDD_IOC. Applies to VDD_AD pins. Applies to pins in the following domains VDD_IOA, VDD_IOB, and VDD_IOD. Including voltage on outputs in 3-state mode. Based on package heat transfer, not device power consumption. Calculated package thermal resistance (ThetaJA): 35.766 °C/W (with JEDEC Test Board and 0 m/s airflow, ± 15 % accuracy). Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. Charge device model per AEC-Q100-011. [2] [3] [4] [5] [6] [7] [8] [9] LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 42 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10. Static characteristics Table 7. Static characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol VDD(1V2) Parameter supply voltage (1.2 V) Conditions core supply voltage for full performance; up to 266 MHz range core supply voltage for normal performance; up to 208 MHz range core supply voltage for reduced power; up to 14 MHz CPU RTC supply voltage PLL and oscillator supply voltage VDD(EMC) external memory in 1.8 V range controller supply voltage in 2.5 V range in 3.3 V range VDD(IO) input/output supply voltage in 1.8 V range in 3.3 V range applies to pins in VDD_AD power domain VDD_CORE = 1.2 V; Tamb = 25 °C; I-cache enabled; CPU clock = 208 MHz; all peripherals enabled VDD_CORE = 0.9 V; Tamb = 25 °C; CPU clock = 13 MHz VDD_CORE = 0.9 V; Tamb = 25 °C; CPU clock = stopped internally VDD_RTC = VDD_RTCCORE = VDD_RTCOSC = 1.2 V; Tamb = 25 °C; [8][10] [2] Min 1.31 Typ[1] 1.35 Max 1.39 Unit V [2] 1.1 1.2 1.39 V [2] 0.9 - 1.39 V [3] [4] 0.9 1.1 1.7 1.2 1.8 2.5 3.3 1.8 3.3 3.3 1.39 1.39 1.95 2.7 3.6 1.95 3.6 3.6 V V V V V V V V [6] [5][6] [7] 2.3 2.7 1.7 2.7 2.7 VDDA(3V3) analog supply voltage (3.3 V) Run, direct Run, and Stop modes IDD(run) Run mode supply current - 80 - mA IDD(drun) direct Run mode supply current Stop mode supply current RTC supply current - 7 - mA IDD(stop) - - 500 µA IDD(RTC) - 4 - µA Input pins and I/O pins configured as input VI VIH VIL Vhys input voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage 1.8 V inputs 3.3 V inputs 1.8 V inputs 3.3 V inputs 1.8 V inputs 3.3 V inputs LPC3220_30_40_50_1 0 0.7 × VDD(IO) 0.7 × VDD(IO) 0.1 × VDD(IO) 0.1 × VDD(IO) - VDD(IO) 0.3 × VDD(IO) 0.3 × VDD(IO) V V V V V V V © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 43 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 7. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol IIL IIH Ilatch Ipu Parameter LOW-level input current HIGH-level input current I/O latch-up current pull-up current Conditions VI = 0 V; no pull-up VI = VDD(IO); no pull-down −(1.5VDD(IO)) < VI < (1.5VDD(IO)) 1.8 V inputs with pull-up; VI = 0 V 3.0 V inputs with pull-up; VI = 0 V Ipd pull-down current 1.8 V inputs with pull-down; VI = VDD(IO) 3.0 V inputs with pull-down; VI = VDD(IO) Ci input capacitance Excluding bonding pad capacitance [8][9] [10][11] [8] Min 6 25 5 25 - Typ[1] 12 50 12 50 - Max 1 1 100 22 80 22 85 3.3 Unit µA µA mA µA µA µA µA pF [8] Output pins and I/O pins configured as output VO VOH VOL IOH output voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current 1.8 V outputs; IOH = −1 mA 3.0 V outputs; IOH = −4 mA 1.8 V outputs; IOL = 4 mA 3.0 V outputs; IOL = 4 mA VDD(IO) = 1.8 V; VOH = VDD(IO) − 0.4 V VDD(IO) = 3.3 V; VOH = VDD(IO) − 0.4 V IOL IOZ IOHS IOLS LOW-level output current OFF-state output current HIGH-level short-circuit output current LOW-level short-circuit output current VDD(IO) = 1.8 V; VOL = 0.4 V VDD(IO) = 3.3 V; VOL = 0.4 V VO = 0 V; VO = VDD(IO); no pull-up/down VDD(IO) = 1.8 V; VOH = 0 V VDD(IO) = 3.3 V; VOH = 0 V VDD(IO) = 1.8 V; VOL = VDD(IO) VDD(IO) = 3.3 V; VOL = VDD(IO) Zo EMC pins VI VIH input voltage HIGH-level input voltage 1.8 V inputs 3.3 V inputs [8][10] [8][13] [13] [8] [8][12] 0 VDD(IO) − 0.4 VDD(IO) − 0.4 −3.3 −6.5 1.5 3 40 40 0 0.7 × VDD(EMC) 0.7 × VDD(EMC) - VDD(IO) 0.4 0.4 1 66 183 34 105 60 60 VDD(EMC) - V V V V V mA mA mA mA µA mA mA mA mA Ω Ω V V V [12] [12] [12] [12] [8][12] output impedance VDD(IO) = 1.8 V VDD(IO) = 3.3 V LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 44 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 7. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol VIL Vhys IIL IIH Ilatch Ipu Parameter LOW-level input voltage hysteresis voltage LOW-level input current HIGH-level input current I/O latch-up current pull-up current Conditions 1.8 V inputs 3.3 V inputs 1.8 V inputs 2.8 V inputs VI = 0 V; no pull-up VI = VDD(EMC); no pull-down −(1.5VDD(EMC)) < VI < (1.5VDD(EMC)) 1.8 V inputs with pull-up; VI = 0 2.8 V inputs with pull-up; VI = 0 Ipd pull-down current 1.8 V inputs with pull-down; VI = VDD(EMC) 3.0 V inputs with pull-down; VI = VDD(EMC) Ci VO VOH VOL IOH input capacitance output voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current 1.8 V outputs; IOH = −1 mA 3.0 V outputs; IOH = −4 mA 1.8 V outputs; IOL = 4 mA 3.0 V outputs; IOL = 4 mA VDD(EMC) = 1.8 V; VOH = VDD(EMC) − 0.4 V VDD(EMC) = 2.8 V; VOH = VDD(EMC) − 0.4 V IOL LOW-level output current VDD(EMC) = 1.8 V; VOL = 0.4 V VDD(EMC) = 2.8 V; VOL = 0.4 V IOZ IOHS IOLS OFF-state output current HIGH-level short-circuit output current LOW-level short-circuit output current VO = 0 V; VO = VDD(EMC); no pull-up/down VDD(EMC) = 1.8 V; VOH = 0 V VDD(EMC) = 2.8 V; VOH =0 V VDD(EMC) = 1.8 V; VOL = VDD(EMC) VDD(EMC) = 2.8 V; VOL = VDD(EMC) Zo output impedance VDD(EMC) = 1.8 V VDD(EMC) = 3.0 V LPC3220_30_40_50_1 Min 0.4 0.55 [8] Typ[1] 62 169 51 155 40 35 Max 0.3 × VDD(EMC) 0.3 × VDD(EMC) 0.6 0.85 0.3 0.3 100 107 271 93 266 2.1 VDD(EMC) 0.3 0.3 0.3 −49 −81 49 86 58 45 Unit V V V V µA µA mA µA µA µA µA pF V V V V V mA mA mA mA µA mA mA mA mA Ω Ω 34 97 23 73 - [8] Excluding bonding pad capacitance [8][9] [10][11] [12] [12] [12] [12] [8][12] 0 VDD(EMC) − 0.3 VDD(EMC) − 0.3 −6 −6 [8][12] 6 6 [8] 35 32 [13] [8][12] © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 45 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 7. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol I2C VI VIH VIL IIL IIH Ilatch Ci VOL IOL IOZ IOLS pins input voltage HIGH-level input voltage LOW-level input voltage LOW-level input current HIGH-level input current I/O latch-up current input capacitance LOW-level output voltage LOW-level output current OFF-state output current LOW-level short-circuit output current 1.8 V inputs 3.3 V inputs 1.8 V inputs 3.3 V inputs VI = 0 V; no pull-up VI = VDD(IO); no pull-down −(1.5VDD(IO)) < VI < (1.5VDD(IO)) Excluding bonding pad capacitance 1.8 V outputs; IOL = 4 mA 3.3 V outputs; IOL = 4 mA VDD(IO) = 1.8 V; VOL = 0.4 V VDD(IO) = 3.3 V; VOL = 0.4 V VO = 0 V; VO = VDD(IO); no pull-up/down VDD(IO) = 1.8 V; VOL = VDD(IO) VDD(IO) = 3.3 V; VOL = VDD(IO) ONSW pin VO VOH VOL IOH IOL IOZ IOHS IOLS Zo Reset pin LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Parameter Conditions [8] [10] Min 0 0.7 × VDD(IO) 0.7 × VDD(IO) [8] Typ[1] - Max 5.5V 0.3 × VDD(IO) 0.3 × VDD(IO) 10 10 100 1.6 0.4 0.4 10 40 40 Unit V V V V V µA µA mA pF V V mA mA µA mA mA - [8] [12] [12] [8][12] 3 3 [8] - [8][13] output voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current OFF-state output current HIGH-level short-circuit output current LOW-level short-circuit output current output impedance 1.2 V outputs; IOH = −1 mA 1.2 V outputs; IOL = 4 mA VOH = VDD(1V2) − 0.4 V VOL = 0.4 V VO = 0 V; VO = VDD(1V2); no pull-up/down VDD(1V2) = 1.8 V; VOH = 0 V VOL = VDD(1V2) VDD(1V2) = 1.2 V [13] [8][9] [10][11] [12] 0 VDD(1V2) − 0.4 −4 3 40 - VDD(1V2) 0.4 1.5 −135 135 60 V V V mA mA µA mA mA Ω [12] [8][12] [8][12] [8] [8][13] Preliminary data sheet Rev. 01 — 6 February 2009 46 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 7. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol VI VIH VIL IIL IIH IOZ Ilatch [1] [2] [3] [4] [5] [6] [7] [8] [9] Parameter input voltage Conditions [8] [10] Min 0 0.7 × VDD(1V2) [8] [8] Typ[1] - Max 1.95 0.7 × VDD(1V2) 1 1 1 100 Unit V V V µA µA µA mA HIGH-level input voltage 1.2 V inputs LOW-level input voltage LOW-level input current OFF-state output current I/O latch-up current 1.2 V inputs VI = 0 V; no pull-up VO = 0 V; VO = VDD; no pull-up/down −(1.5VDD) < VI < (1.5VDD) HIGH-level input current VI = VDD; no pull-down - [8] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. Applies to VDD_CORE pins. Applies to pins VDD_RTC, VDD_RTCCORE, and VDD_RTCOSC. Applies to pins VDD_COREFXD, VDD_OSC, VDD_PLL397, VDD_PLLHCLK, and VDD_PLLUSB. Applies to VDD_EMC for SDR SDRAM and SRAM controllers Applies to VDD_EMC, and VDD_IOC domain. Applies to VDD_IOA, VDD_IOB, VDD_IOD voltage domains. Voltage domains VDD_IOA, VDD_IOB, VDD_IOD must operate at the same voltage; VDD_IOA = VDD_IOB = VDD_IOD. Referenced to the applicable VDD for the pin. Including voltage on outputs in 3-state mode. [10] The applicable VDD voltage for the pin must be present. [11] 3-state outputs go into 3-state mode when VDD(3V0) is grounded. [12] Accounts for 100 mV voltage drop in all supply lines. [13] Allowed as long as the current limit does not exceed the maximum current allowed by the device. 10.1 Power supply sequencing The LPC32x0 has no power sequencing requirements, that is, VDD(1V2), VDD(EMC), VDD(IO), and VDDA(3V3) can be switched on or off independent of each other. An internal circuit takes care that the system correctly powers up in the absence of core power. During IO power-up this circuit takes care that the system is powered in a defined mode. The same is valid for core power-down. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 47 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.2 ADC static characteristics Table 8. ADC static characteristics VDDA(3V3) = 3.3 V; Tamb = 25°C unless otherwise specified; ADC clock frequency 4.5 MHz. Symbol VIA Cia ED EL(adj) EO EG ET Rvsi [1] [2] [3] [4] [5] [6] [7] Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance Conditions Min 0 [1][2][3] [1][4] [1][5] [1][6] [1][7] Typ ±0.5 ±0.6 ±1 ±0.3 - Max VDDA(3V3) 1 ±1 ±1 ±3 ±0.6 ±4 40 Unit V pF LSB LSB LSB % LSB kΩ - Conditions: VSSA = 0 V (on pin VSS_AD); VDDA(3V3) = 3.3 V (on pin VDD_AD). The ADC is monotonic; there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 4. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 4. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 4. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 4. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 48 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers offset error EO 1023 gain error EG 1022 1021 1020 1019 1018 (2) 7 code out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024 0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB = VDDA(3V3) − VSSA 1024 002aae434 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 49 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11. Dynamic characteristics 11.1 Clocking and I/O port pins Table 9. Dynamic characteristics Tamb = −40 °C to +85 °C, unless otherwise specified.[1] Symbol Reset tw(RESET)ext External clock fext Port pins tr tf [1] [2] [3] Parameter external RESET pulse width external clock frequency rise time fall time Conditions [2] Min 10 1 - Typ 13 5 5 Max 20 - Unit ms MHz ns ns [3] Parameters are valid over operating temperature range unless otherwise specified. After supply voltages are stable Supplied by an external crystal. 11.2 Static memory controller Table 10. Dynamic characteristics: static external memory interface CL = 25 pF, Tamb = 20 °C, VDD(EMC) = 1.8 V. Symbol TCLCL tCSLAV tOELAV tBLSLAV tCSLOEL tCSLBLSL tOELOEH tBLSLBLSH tsu(DQ) th(DQ) tCSHOEH tCSHBLSH tOEHANV tBLSHANV tCSLDV tCSLWEL tCSLBLSL tWELDV Parameter clock cycle time CS LOW to address valid time OE LOW to address valid time BLS LOW to address valid time CS LOW to OE LOW time CS LOW to BLS LOW time OE LOW to OE HIGH time BLS LOW to BLS HIGH time data input/output set-up time data input/output hold time CS HIGH to OE HIGH time CS HIGH to BLS HIGH time OE HIGH to address invalid time BLS HIGH to address invalid time CS LOW to data valid time CS LOW to WE LOW time CS LOW to BLS LOW time WE LOW to data valid time [6] [6] [6] [8] [8] [4] [4][5] [4][5] [4] [4] Notes Min [3] Typ 9.6 0 0 − WAITOEN × TCLCL 0 − WAITOEN × TCLCL 0 + WAITOEN × TCLCL 0 + WAITOEN × TCLCL (WAITRD − WAITOEN + 1) × TCLCL (WAITRD − WAITOEN + 1) × TCLCL 0 0 0 1 × TCLCL 1 × TCLCL 0 (WAITWEN + 1) × TCLCL (WAITWEN + 1) × TCLCL 0 − (WAITWEN + 1) × TCLCL Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Common to read and write cycles - Read cycle parameters Write cycle parameters LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 50 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 10. Dynamic characteristics: static external memory interface …continued CL = 25 pF, Tamb = 20 °C, VDD(EMC) = 1.8 V. Symbol tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV tBLSHDNV [1] [2] [3] [4] [5] [6] [7] [8] Parameter WE LOW to WE HIGH time BLS LOW to BLS HIGH time WE HIGH to address invalid time WE HIGH to data invalid time BLS HIGH to address invalid time BLS HIGH to data invalid time Notes Min [6][7] [6][7] Typ (WAITWR − WAITWEN + 1) × TCLCL (WAITWR − WAITWEN + 1) × TCLCL 1 × TCLCL 1 × TCLCL 1 × TCLCL 1 × TCLCL Max - Unit ns ns ns ns ns ns - VOH = VDD(EMC) − 0.3, VOL = 0.3 V. VIH = 0.7 x VDD(EMC), VIL = 0.3 x VDD(EMC) V. TCLCL = 1/HCLK Refer to the LPC32x0 user manual EMCStaticWaitOen0-3 register for the programming of WAITOEN value. Refer to the LPC32x0 user manual EMCStaticWaitRd0-3 register for the programming of WAITRD value. Refer to the LPC32x0 user manual EMCStaticWaitWen0-3 register for the programming of WAITWEN value. Refer to the LPC32x0 user manual EMCStaticWaitWr0-3 register for the programming of WAITWR value. Earliest of CS HIGH, OE HIGH, address change to data invalid. EMC_A[23:0] tCSLAV EMC_CS[3:0] tOELAV tCSLOEL tOELOEH EMC_OE tBLSLAV tCSLBLSL tBLSLBLSH EMC_BLS[3:0] tsu(DQ) EMC_D[31:0] 002aae402 tOEHANV tCSHOEH tCSHBLSH tBLSHANV th(DQ) Fig 5. External memory read access LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 51 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers EMC_A[23:0] tCSLAV EMC_CS[3:0] tCSLDV tWELDV EMC_D[31:0] tWEHDNV tWEHANV tWELWEH EMC_WR tBLSHDNV tBLSHANV tBLSLBLSH EMC_BLS[3:0] 002aae469 tCSLWEL tCSLBLSL Fig 6. External memory write access LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 52 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.3 SDR SDRAM Controller Table 11. EMC SDR SDRAM memory interface dynamic characteristics Tamb = −40 °C to +85 °C, unless otherwise specified.[1][3] Symbol foper tCK tCL tCH td(V)ctrl th(ctrl) td(AV) th(A) td(QV) th(Q) tsu(D) th(D) tQZ [1] [2] [3] [4] [5] [6] Parameter operating frequency clock cycle time CK LOW-level width CK HIGH-level width control valid delay time control hold time address valid delay time address hold time data output valid delay time data output hold time data input set-up time data input hold time data output high-impedance time [5][6] [5][6] [6] [6] [6] [6] [4] Min - Typical[2] 104 9.6 4.8 4.8 (CMD_DLY × 0.25) + 2.7 (CMD_DLY × 0.25) + 1.2 (CMD_DLY × 0.25) + 3.2 (CMD_DLY × 0.25) + 1.2 (CMD_DLY × 0.25) + 3.5 (CMD_DLY × 0.25) + 1.2 0.6 0.9 - Max 133 < tCK Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns Parameters are valid over operating temperature range unless otherwise specified. Typical values valid for EMC pads set to high slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or low slew rate: VDD_EMC = 3.3 V, VDD_CORE = 1.2 V. All min or max values valid for EMC pads set to high slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or low slew rate: VDD_EMC = 3.3 V, VDD_CORE = 1.2 V. foper = 1/tCK. Applies to signals: EMC_DQM[3:0], EMC_DYCSm, EMC_RAS, EMC_CAS, EMC_WR, EMC_CKEm. CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External memory controller (EMC) chapter in LPC32x0 User manual. tCK tCH EMC_CLK tCL td(V)ctrl, td(AV), td(QV) th(ctrl), th(Q), th(A) output signal (O) tQZ tsu(D) th(D) input signal (I) 002aae420 Fig 7. SDR SDRAM signal timing 11.4 DDR SDRAM controller LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 53 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 12. EMC DDR SDRAM memory interface dynamic characteristics[1] CL = 25 pF; Tamb = 25 °C. Symbol Parameter foper tCK tCL tCH td(V)ctrl th(ctrl) td(AV) th(A) tsu(Q) operating frequency clock cycle time CK LOW-level width CK HIGH-level width control valid delay time control hold time address valid delay time address hold time data output set-up time EMC_D and EMC_DQM to EMC_DQS out EMC_D and EMC_DQM to EMC_DQS out for WRITE command for WRITE command for DQS out for DQS in for DQS in for DQS in [4] [2][3] [2][3] [2] [2] Conditions Min - Typical 104 9.6 0.5 × tCK 0.5 × tCK (CMD_DLY × 0.25) + 1.5 (CMD_DLY × 0.25) − 1.5 (CMD_DLY × 0.25) + 1.5 (CMD_DLY × 0.25) − 1.5 0.275 × tCK Max - Unit MHz ns ns ns ns ns ns ns ns th(Q) data output hold time - 0.225 × tCK - ns tDQSH tDQSL tDQSS tDSS tDSH td(DQS) tsu(D) th(D) tWPRE tWPST tRPRE tRPST [1] [2] [3] [4] DQS HIGH time DQS LOW time WRITE command to first DQS latching transition time DQS falling edge to CK set-up time DQS falling edge hold time from CK DQS delay time data input set-up time data input hold time write preamble time write postamble time read preamble time read postamble time - 0.5 × tCK 0.5 × tCK tCK + (CMD_DLY × 0.25) 0.5 × tCK 0.5 × tCK DQS_DELAY 0.3 0.5 - ns ns ns ns ns ns ns ns ns ns ns ns All values valid for EMC pads set to high slew rate at 1.8 V. CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External memory controller (EMC) chapter in LPC32x0 User manual. Applies to signals EMC_DQM[1:0], EMC_DYCSm, EMC_RAS, EMC_CAS, EMC_WR, EMC_CKEm. DQS_DELAY, see LPC32x0 user manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on configuring this value. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 54 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers tCK EMC_CLK td(AV); td(V)ctrl EMC control and address signals tCH tCL th(A); th(ctl) valid 002aae436 Fig 8. DDR control timing parameters EMC_CLK tDSS command WRITE tDQSS EMC_DQSm tWPRE tsu(Q) th(Q) EMC_D[31:0], EMC_DQM[1:0] 002aae437 tDSH tDQSL tDQSH tWPST Fig 9. DDR write timing parameters EMC_CLK command READ tRPRE tRPST EMC_DQSm td(DQS) delayed EMC_DQSm(1) tsu(D) EMC_D[31:0] th(D) 002aae438 (1) The delay of the EMC_DQSm signal is determined by the DQS_DELAY settings. See LPC32x0 user manual, External Memory Controller Chapter, section DDR DQS delay calibration for details on configuring this value. Fig 10. DDR read timing parameters LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 55 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.5 Ethernet Table 13. Symbol Tcy(clk) tv(Q) tQZ tsu(D) th(D) Dynamic characteristics: Ethernet MAC pins Parameter clock cycle time data output valid time data output high-impedance time data input set-up time data input hold time Conditions on pin ENET_MDC Min Typ Max Unit ns ns ns ns ns Ethernet MAC signals for MIIM on pin ENET_MDIO; MDIO write on pin ENET_MDIO; MDIO read on pin ENET_MDIO; MDIO read on pin ENET_RXD; RMII receive input on pin ENET_CRS; RMII carrier sense input on pin ENET_RXER; RMII receive error input th(D) data input hold time on pin ENET_RXD; RMII receive input on pin ENET_CRS; RMII carrier sense input on pin ENET_RXER; RMII receive error input td(QV) data output valid delay time on pin ENET_TXD; RMII transmit output on pin ENET_TXEN; RMII transmit enable th(Q) data output hold time on pin ENET_TXD; RMII transmit output on pin ENET_TXEN; RMII transmit enable Ethernet MAC signals for RMII tsu(D) data input set-up time ns ns ns ns ns ns ns ns ns ns LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 56 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Tcy(clk) ENET_MDC tv(Q) ENET_MDIO(O) tQZ tsu(D) th(D) ENET_MDIO(I) 002aad990 Fig 11. Ethernet MAC MIIM timing ENET_REF_CLK td(QV) ENET_TX_EN ENET_TXD[3:0] th(Q) tsu(D) ENET_CRS ENET_RXD[3:0] ENET_RX_ER th(D) 002aae439 Fig 12. Ethernet RMII timing 11.6 USB controller Table 14. Dynamic characteristics USB digital I/O pins VDD(IO) = 3.3 V; Tamb = −40 °C to +85 °C, unless otherwise specified.[1] Symbol tTIO tTOI [1] Parameter bus turnaround time (I/O) bus turnaround time (O/I) Conditions OE_N/INT_N to DAT/VP and SE0/VM OE_N/INT_N to DAT/VP and SE0/VM Min - Typ 7 0 Max - Unit ns ns Parameters are valid over operating temperature range unless otherwise specified. LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 57 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers USB_OE_TP tTIO USB_DAT_VP USB_SE0_VM tTOI input output input 002aae440 Fig 13. USB bus turnaround time 11.7 Secure Digital (SD) card interface Table 15. Dynamic characteristics: SD card pin interface Tamb = −40 °C to +85 °C for industrial applications; VDD(IO) over specified ranges.[1] Symbol Parameter Tcy(clk) tsu(D) th(D) td(QV) th(Q) [1] [2] Conditions on pin MS_SCLK; Data transfer mode on pin MS_SCLK; Identification mode on pins MS_BS, MS_DIO[3:0] as inputs on pins MS_BS, MS_DIO[3:0] as inputs on pins MS_BS, MS_DIO[3:0] as outputs on pins MS_BS, MS_DIO[3:0] as outputs Min - Typ[2] 2.7 0 9.7 7.7 Max 25 400 - Unit MHz kHz ns ns ns ns clock cycle time data input set-up time data input hold time data output valid delay time data output hold time Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. Tcy(clk) MS_SCLK td(QV) MS_BS (O) MS_DIO[3:0](O) th(Q) tsu(D) MS_BS (I) MS_DIO[3:0] (I) th(D) 002aae441 Fig 14. SD card pin interface timing LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 58 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.8 MLC NAND flash memory controller Table 16. Dynamic characteristics of the MLC NAND flash memory controller Tamb = −40 °C to +85 °C. Symbol tCELREL tRC tREH tRHZ tRP tREHRBL tWB tWC tWH tWP [1] [2] [3] [4] [5] [6] [7] [8] Parameter CE LOW to RE LOW time RE cycle time RE HIGH hold time RE HIGH to output high-impedance time RE pulse width RE HIGH to R/B LOW time WE HIGH to R/B LOW time WE cycle time WE HIGH hold time WE pulse width [1][2] [1][5][6] [1][5][6] [1][5][7] [1][5] [1][8] [1][8] [1][3][4] [1][3][4] [1][3] Min - Typ THCLK × CEAD THCLK × (RL + 1) + THCLK × (RH − RL) THCLK × (RH − RL) THCLK × (RH − RL) + THCLK × RHZ THCLK × (RL + 1) THCLK × BD THCLK × BD THCLK × (WH − WL) THCLK × (WL + 1) Max - Unit ns ns ns ns ns ns ns ns ns ns THCLK × (WL + 1) + THCLK × (WH − WL) - THCLK = 1/HCLK CEAD = bitfield TCEA_DELAY[1:0] in register MLC_TIME_REG[25:24] WL = bitfield WR_LOW[3:0] in register MLC_TIME_REG[3:0] WH = bitfield WR_HIGH[3:0] in register MLC_TIME_REG[7:4] RL = bitfield RD_LOW[3:0] in register MLC_TIME_REG[11:8] RH = bitfield RD_HIGH [3:0] in register MLC_TIME_REG[15:12] RHZ = bitfield NAND_TA[2:0] in register MLC_TIME_REG[18:16] BD = bitfield BUSY_DELAY[4:0] in register MLC_TIME_REG[23:19] FLASH_CE tWC tWP tWH FLASH_WR FLASH_IO[7:0] D0 D1 Dn 10h tWB FLASH_RDY (R/B) 002aae442 Fig 15. MLC NAND flash controller write timing (writing to NAND flash) LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 59 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers FLASH_CE tCELREL tRC tRP tREH FLASH_RD tRHZ FLASH_IO[7:0] D0 D1 D2 D3 002aae443 Fig 16. MLC NAND flash controller read timing (reading from NAND flash) 11.9 SLC NAND flash memory controller Table 17. Dynamic characteristics of SLC NAND flash memory controller Tamb = −40 °C to +85 °C. Symbol tALS tALH tAR tCEA tCS tCH tCLS tCLH tCLR tDH Parameter ALE set-up time ALE hold time ALE to RE delay time CE access time CE set-up time CE hold time CLE set-up time CLE hold time CLE to RE delay time data hold time Conditions read write read write read write read write read write read write read write read write read write output from NAND controller; read output from NAND controller; write [1][3][7] [1][2][6] [1][3] [1][2][4][6][8] [1][3] [1][2][4][6][8] [1][2][4][6][8] [1][2][6] [1][7] [1][2][4][6] Min - Typ THCLK × (Rsu + Rw) THCLK × (Wsu + Ww) THCLK × Rh THCLK × Wh THCLK × Rsu THCLK × Wsu THCLK × (Rsu + Rw) THCLK × (Wsu + Ww) THCLK × (Rsu + Rw) THCLK × (Wsu + Ww) THCLK × Rh THCLK × Wh THCLK × (Rsu + Rw) THCLK × (Wsu + Ww) THCLK × Rh THCLK × Wh THCLK × Rsu THCLK × Wsu THCLK × Rh Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns - THCLK × Wh - ns LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 60 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Table 17. Dynamic characteristics of SLC NAND flash memory controller …continued Tamb = −40 °C to +85 °C. Symbol tDS Parameter data set-up time Conditions output from NAND controller; read output from NAND controller; write tIR tRC tREA tREH tRHOH output high-impedance to RE LOW time RE cycle time RE access time RE high hold time RE HIGH to output hold time read write read read read input hold for flash controller; read input hold for flash controller; write tRHZ tRP tRR tWB tWC tWH tWHR tWP tREHRBL [1] [2] [3] [4] [5] [6] [7] [8] [9] [1][2] [1][4] [1][2][3] [1][2][6] [1][2][4][6][8] Min - Typ THCLK × (Rsu + Rw) Max - Unit ns - THCLK × (Wsu + Ww) - - THCLK × Rsu THCLK × Wsu THCLK × (Rsu + Rw + Rh) THCLK × Rw THCLK × (Rsu + Rh) 0 - ns ns ns ns ns - - 0 - - RE HIGH to output high-impedance time RE pulse width ready to RE LOW time WE HIGH to R/B LOW time WE cycle time WE HIGH hold time WE HIGH to RE LOW time WE pulse width RE HIGH to R/B LOW time read read read write write write write write write [1] - THCLK × Rh THCLK × Rw THCLK × Rsu THCLK × Ww THCLK × (Wsu + Wh) THCLK × (Wsu + Wh) THCLK × Ww THCLK × Ww - ns ns ns ns ns ns ns ns ns [1][4] [1][2][3] [1][8] [1][6][7][8] [1][6][7] [1][6][7] [1][8] [1][8] THCLK × (Wsu + Ww + Wh) - THCLK = 1/HCLK Rsu = bitfield R_SETUP[3:0] in register SLC_TAC[3:0] for reads Rh = bitfield R_HOLD[3:0] in register SLC_TAC[7:4] for reads Rw = bitfield R_WIDTH[3:0] in register SLC_TAC[11:8] for reads Rb = bitfield R_RDY[3:0] in register SLC_TAC[15:12] for reads Wsu = bitfield W_SETUP[3:0] in register SLC_TAC[19:16] for writes Wh = bitfield W_HOLD[3:0] in register SLC_TAC[23:20] for writes Ww = bitfield W_WIDTH[3:0] in register SLC_TAC[27:24] for writes Wb = bitfield W_RDY[3:0] in register SLC_TAC[31:28] for writes LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 61 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers tCS FLASH_CE tCH tCS tCH tCLS FLASH_CLE tCLH tCLS tCLH tWP tWP tWH tWP tWH tWC FLASH_WR tALS FLASH_ALE tALH tALS tALH tALS tDS FLASH_IO[7:0] tDH tDS tDH tDS tDH D0 D1 Dn command address FLASH_RDY tWB command address data 002aae444 Fig 17. MLC NAND flash memory write timing (writing to NAND flash) LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 62 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers tALS FLASH_ALE tCLS FLASH_CLE tALH tALS tALH tCLH tCLS FLASH_RDY tWP FLASH_WR tWB tWP tWH tRR tAR FLASH_RD tCLR tDS FLASH_IO[7:0] tDH tDS tDH tDS tDH D0 tREA D1 D2 D3 tRHZ tRP tREH tRC tRHOH command address tCS FLASH_CE tCH tCS tCEA tCOH command address data 002aae445 Fig 18. MLC NAND Flash memory read timing (reading from NAND flash) LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 63 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers tCS FLASH_CE tCLS FLASH_CLE tWP tCH tCEA tCOH tCLH tCLR FLASH_WR FLASH_RD tWHR tRHOH tDS tDH status tIR tREA command data tRHZ FLASH_IO[7:0] 70 h 002aae446 Fig 19. MLC NAND flash memory status timing 11.10 SPI and SSP Controller 11.10.1 SPI Table 18. Dynamic characteristics of SPI pins on SPI master controller Tamb = −40 °C to +85 °C. Symbol TSPICYC SPI1 tSPIDSU tSPIDH tSPIDV tSPIOH SPI2 tSPIDSU tSPIDH tSPIDV tSPIOH [1] Parameter SPI cycle time SPI data set-up time SPI data hold time SPI enable to output data valid time SPI output data hold time SPI data set-up time SPI data hold time SPI enable to output data valid time SPI output data hold time [1] Min 2 × THCLK - Typ 6 0 2 0 10 0 2 0 Max 256 × THCLK - Unit ns ns ns ns ns ns ns ns ns Common to SPI1 and SPI2 THCLK = period time of SPI IP block input clock (HCLK) LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 64 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.10.2 SSP Table 19. Dynamic characteristics of SSP controller pins in SPI mode Tamb = −40 °C to +85 °C. Symbol TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV tSPIOH TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV tSPIOH tSPIDSU tSPIDH tSPIQV tSPIOH tSPIDSU tSPIDH tSPIQV tSPIOH Parameter SPI cycle time SPICLK HIGH time SPICLK LOW time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time SPI cycle time SPICLK HIGH time SPICLK LOW time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time Min Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSP 0 in SPI master mode SSP 1 in SPI master mode SSP0 in SPI slave mode SSP1 in SPI slave mode LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 65 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.10.3 Timing diagrams for SPI and SSP (in SPI mode) TSPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) tSPICLKH tSPICLKL SPI1/2_CLK or SCK0/1 (CPOL = 1) tSPIQV SPI1/2_DATAIO or MOSI0/1 DATA VALID DATA VALID tSPIDSU SPI1/2_DATAIN or MISO0/1 DATA VALID tSPIDH tSPIOH DATA VALID 002aae457 Fig 20. SPI master timing (CPHA = 0) TSPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) tSPICLKH tSPICLKL SPI1/2_CLK or SCK0/1 (CPOL = 1) tSPIQV SPI1/2_DATAIO or MOSI0/1 DATA VALID DATA VALID tSPIDSU SPI1/2_DATAIN or MISO0/1 DATA VALID tSPIDH tSPIOH DATA VALID 002aae454 Fig 21. SPI master timing (CPHA = 1) LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 66 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers TSPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) tSPICLKH tSPICLKL SPI1/2_CLK or SCK0/1 (CPOL = 1) tSPIDSU SPI1/2_DATAIO or MOSI0/1 DATA VALID tSPIQV SPI1/2_DATAIN or MISO0/1 DATA VALID DATA VALID tSPIDH DATA VALID tSPIOH 002aae458 Fig 22. SPI slave timing (CPHA = 0) TSPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) tSPICLKH tSPICLKL SPI1/2_CLK or SCK0/1 (CPOL = 1) tSPIDSU SPI1/2_DATAIO or MOSI0/1 DATA VALID tSPIQV SPI1/2_DATAIN or MISO0/1 DATA VALID DATA VALID tSPIDH DATA VALID tSPIOH 002aae459 Fig 23. SPI slave timing (CPHA = 1) LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 67 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 12. Package outline TFBGA296: plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 e V U T R P N M L K J H G F E D C B A b ∅v ∅w M M CAB C C y1 C y e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.4 0.3 A2 0.80 0.65 b 0.5 0.4 D 15.1 14.9 E 15.1 14.9 e 0.8 e1 13.6 e2 13.6 v 0.15 w 0.08 y 0.12 y1 0.1 OUTLINE VERSION SOT1048-1 REFERENCES IEC JEDEC MO-216 JEITA EUROPEAN PROJECTION ISSUE DATE 07-10-19 07-11-02 Fig 24. Package outline SOT1048-1 (TFBGA296) LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 68 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 13. Abbreviations Table 20. Acronym ADC AHB AMBA APB CISC DDR SDRAM DMA DSP ETM FAB FIFO FIQ GPIO I/O IRQ HS IrDA JTAG LCD MAC MIIM OHCI OTG PHY PLL PWM RAM RMII SE0 SDR SDRAM SPI SSI SSP TFT TTL STN UART USB Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Complex Instruction Set Computer Double Data Rate Synchronous Dynamic Random Access Memory Direct Memory Access Digital Signal Processing Embedded Trace Macrocell Fast Access Bus First In, First Out Fast Interrupt Request General Purpose Input/Output Input/Output Interrupt Request High-Speed Infrared Data Association Joint Test Action Group Liquid Crystal Display Media Access Control Media Independent Interface Management Open Host Controller Interface On-The-Go Physical Layer Phase-Locked Loop Pulse Width Modulator Random Access Memory Reduced Media Independent Interface Single Ended Zero Single Data Rate Synchronous Dynamic Random Access Memory Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Thin Film Transistor Transistor-Transistor Logic Super Twisted Nematic Universal Asynchronous Receiver/Transmitter Universal Serial Bus LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 69 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 14. Revision history Table 21. Revision history Release date 20090206 Data sheet status Preliminary data sheet Change notice Supersedes Document ID LPC3220_30_40_50_1 LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 70 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 71 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 17. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.3.1 7.1.3.2 7.2 7.2.1 7.2.2 7.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.1.1 7.5.1.2 7.5.2 7.5.2.1 7.5.3 7.6 7.6.1 7.6.2 7.6.2.1 7.6.3 7.6.3.1 7.6.3.2 7.6.3.3 7.6.4 7.6.4.1 7.7 7.7.1 7.7.2 7.7.2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 21 CPU and subsystems . . . . . . . . . . . . . . . . . . . 21 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Vector Floating Point (VFP) coprocessor . . . . 21 Emulation and debugging . . . . . . . . . . . . . . . . 21 Embedded ICE . . . . . . . . . . . . . . . . . . . . . . . . 21 Embedded trace buffer . . . . . . . . . . . . . . . . . . 22 AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 APB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Physical memory map . . . . . . . . . . . . . . . . . . 23 Internal memory . . . . . . . . . . . . . . . . . . . . . . . 25 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 25 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 25 External memory interfaces . . . . . . . . . . . . . . 25 NAND flash controllers . . . . . . . . . . . . . . . . . . 25 Multi-Level Cell (MLC) NAND flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Single-Level Cell (SLC) NAND flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SD card controller . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 External memory controller. . . . . . . . . . . . . . . 26 AHB master peripherals . . . . . . . . . . . . . . . . . 27 General Purpose DMA (GPDMA) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . 27 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 28 USB device controller . . . . . . . . . . . . . . . . . . . 28 USB host controller. . . . . . . . . . . . . . . . . . . . . 29 USB OTG controller . . . . . . . . . . . . . . . . . . . . 29 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 30 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 System functions . . . . . . . . . . . . . . . . . . . . . . 31 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 31 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 31 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7.3 7.7.3.1 7.7.4 7.7.4.1 7.7.4.2 7.7.4.3 7.7.4.4 7.7.4.5 7.8 7.8.1 7.8.1.1 7.8.1.2 7.8.2 7.8.2.1 7.8.3 7.8.3.1 7.8.4 7.8.4.1 7.8.5 7.8.5.1 7.9 7.9.1 7.9.1.1 7.9.2 7.9.2.1 7.9.3 7.9.3.1 7.9.4 7.9.4.1 7.9.5 7.9.5.1 7.9.6 7.9.6.1 7.9.7 7.9.7.1 7.9.8 7.9.8.1 8 9 10 10.1 10.2 11 11.1 11.2 11.3 Millisecond timer . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking and power control features . . . . . . . Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power control modes . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communication peripheral interfaces . . . . . . UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard UARTs . . . . . . . . . . . . . . . . . . . . . . High-speed UARTs . . . . . . . . . . . . . . . . . . . . SPI serial I/O controller . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSP serial I/O controller. . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus serial I/O controller . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S-bus audio controller . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other peripherals . . . . . . . . . . . . . . . . . . . . . . General purpose parallel I/O . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard scanner . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Touch screen controller and 10-bit ADC . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock (RTC) and battery RAM . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-speed timer . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulators (PWMs) . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motor control pulse width modulator . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic architecture . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Power supply sequencing . . . . . . . . . . . . . . . ADC static characteristics . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Clocking and I/O port pins . . . . . . . . . . . . . . . Static memory controller . . . . . . . . . . . . . . . . SDR SDRAM Controller . . . . . . . . . . . . . . . . . 31 31 32 32 32 32 33 33 33 34 34 34 34 35 35 35 35 36 36 36 37 37 37 38 38 38 38 38 39 39 39 40 40 40 40 40 40 41 42 43 47 48 50 50 50 53 continued >> LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 72 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 53 56 57 58 59 60 64 64 65 66 68 69 70 71 71 71 71 71 71 72 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.10.1 11.10.2 11.10.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 DDR SDRAM controller . . . . . . . . . . . . . . . . . Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB controller. . . . . . . . . . . . . . . . . . . . . . . . . Secure Digital (SD) card interface . . . . . . . . . MLC NAND flash memory controller . . . . . . . SLC NAND flash memory controller . . . . . . . . SPI and SSP Controller . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing diagrams for SPI and SSP (in SPI mode) . . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 February 2009 Document identifier: LPC3220_30_40_50_1