LPC4322JBD144551

LPC435x/3x/2x/1x 32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 3 — 6 December 2012 Preliminary data sheet 1. General description The LPC435x/3x/2x/1x are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI), advanced configurable peripherals such as the State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. The LPC435x/3x/2x/1x operate at CPU frequencies of up to 204 MHz. The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is upward code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor, designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz performance with a simple instruction set and reduced code size. 2. Features and benefits  Cortex-M4 Processor core  ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.  ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.  ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).  Hardware floating-point unit.  Non-maskable Interrupt (NMI) input.  JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.  Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.  System tick timer.  Cortex-M0 Processor core  ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4 application processor.  Running at frequencies of up to 204 MHz.  JTAG LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller     LPC435X_3X_2X_1X Preliminary data sheet  Built-in NVIC. On-chip memory  Up to 1 MB on-chip dual bank flash memory with flash accelerator.  16 kB on-chip EEPROM data memory.  136 kB SRAM for code and data use.  Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.  64 kB ROM containing boot code and on-chip software drivers.  64 bit of general-purpose One-Time Programmable (OTP) memory. Configurable digital peripherals  Serial GPIO (SGPIO) interface.  State Configurable Timer (SCT) subsystem on AHB.  Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCT, and ADC0/1. Serial interfaces  Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.  10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).  One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY.  One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.  USB interface electrical test software included in ROM USB stack.  One 550 UART with DMA support and full modem interface.  Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface.  Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge See Figure 1 and Ref. 1.  Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.  One SPI controller.  One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.  One standard I2C-bus interface with monitor mode and with standard I/O pins.  Two I2S interfaces, each with DMA support and with one input and one output. Digital peripherals  External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.  LCD controller with DMA support and a programmable display resolution of up to 1024 H  768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping. Available on parts LPC4357/53 only.  Secure Digital Input Output (SD/MMC) card interface. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 2 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller      LPC435X_3X_2X_1X Preliminary data sheet  Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.  Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.  GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.  Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.  Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  Four general-purpose timer/counters with capture and match capabilities.  One motor control Pulse Width Modulator (PWM) for three-phase motor control.  One Quadrature Encoder Interface (QEI).  Repetitive Interrupt timer (RI timer).  Windowed watchdog timer (WWDT).  Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.  Alarm timer; can be battery powered. Analog peripherals  One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.  Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC. Unique ID for each device. Clock generation unit  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz internal RC oscillator trimmed to 2 % accuracy over temperature and voltage (1 % accuracy for Tamb = 0 °C to 85 °C).  Ultra-low power Real-Time Clock (RTC) crystal oscillator.  Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL.  Clock output. Power  Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the core supply and the RTC power domain.  RTC power domain can be powered separately by a 3 V battery supply.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.  Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.  Brownout detect with four separate thresholds for interrupt and forced reset.  Power-On Reset (POR). Available as LQFP208, LQFP144, LBGA256, or TFBGA100 packages. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 3 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 3. Applications     LPC435X_3X_2X_1X Preliminary data sheet Motor control Power management White goods RFID readers  Embedded audio applications  Industrial automation  e-metering All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 4 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4357JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4357JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC4353FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4353JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4353JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC4337FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4337JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4337JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1 LPC4337JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4333FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4333JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4333JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1 LPC4333JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4327JBD144 LQFP144 LPC4327JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4325JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm LPC4325JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4323JBD144 LQFP144 LPC4323JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4322JBD144 LQFP144 LPC4322JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4317JBD144 LQFP144 LPC4317JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4315JBD144 LQFP144 LPC4315JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4313JBD144 LQFP144 LPC4313JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC4312JBD144 LQFP144 LPC4312JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm LPC435X_3X_2X_1X Preliminary data sheet Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 SOT926-1 SOT926-1 SOT486-1 SOT926-1 SOT486-1 SOT926-1 SOT486-1 SOT926-1 SOT486-1 SOT926-1 SOT486-1 SOT926-1 SOT486-1 SOT926-1 SOT486-1 SOT926-1 SOT486-1 SOT926-1 © NXP B.V. 2012. All rights reserved. 5 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 4.1 Ordering options GPIO Temperature range[1] ADC channels QEI PWM USB1 (Host, Device)/ ULPI interface USB0 (Host, Device, OTG) Ethernet LCD Total SRAM Flash bank B Flash total Flash bank A Ordering options Type number Table 2. LPC4357FET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 F 164 LPC4357JET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 164 LPC4357JBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 142 LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes yes yes 8 F 164 LPC4353JET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes yes yes 8 J 164 LPC4353JBD208 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes yes yes 8 J 142 LPC4337FET256 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes yes yes 8 F 164 LPC4337JET256 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes yes yes 8 J 164 LPC4337JBD144 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes yes no 8 J 83 LPC4337JET100 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes no no 4 J 49 LPC4333FET256 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes yes yes 8 F 164 LPC4333JET256 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes yes yes 8 J 164 LPC4333JBD144 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes yes no 8 J 83 LPC4333JET100 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes no no 4 J 49 LPC4327JBD144 1 MB 512 kB 512 kB 136 kB no no yes no/no yes no 8 J 83 LPC4327JET100 1 MB 512 kB 512 kB 136 kB no no yes no/no no no 4 J 49 LPC4325JBD144 768 kB 384 kB 384 kB 136 kB no no yes no/no yes no 8 J 83 LPC4325JET100 768 kB 384 kB 384 kB 136 kB no no yes no/no no no 4 J 49 LPC4323JBD144 512 kB 256 kB 256 kB 104 kB no no yes no/no yes no 8 J 83 LPC4323JET100 512 kB 256 kB 256 kB 104 kB no no yes no/no no no 4 J 49 LPC4322JBD144 512 kB 512 kB 0 kB 104 kB no no yes no/no yes no 8 J 83 LPC4322JET100 512 kB 512 kB 0 kB 104 kB no no yes no/no no no 4 J 49 LPC4317JBD144 1 MB 512 kB 512 kB 136 kB no no no no/no yes no 8 J 83 LPC4317JET100 1 MB 512 kB 512 kB 136 kB no no no no/no no no 4 J 49 LPC4315JBD144 768 kB 384 kB 384 kB 136 kB no no no no/no yes no 8 J 83 LPC4315JET100 768 kB 384 kB 384 kB 136 kB no no no no/no no no 4 J 49 LPC4313JBD144 512 kB 256 kB 256 kB 104 kB no no no no/no yes no 8 J 83 LPC4313JET100 512 kB 256 kB 256 kB 104 kB no no no no/no no no 4 J 49 LPC4312JBD144 512 kB 512 kB 0 kB 104 kB no no no no/no yes no 8 J 83 LPC4312JET100 512 kB 512 kB 0 kB 104 kB no no no no/no no no 4 J 49 [1] J = -40 °C to +105 °C; F = -40 °C to +85 °C. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 6 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 5. Block diagram LPC435x/3x/2x/1x TEST/DEBUG INTERFACE TEST/DEBUG INTERFACE ARM CORTEX-M0 HIGH-SPEED PHY ARM CORTEX-M4 system bus D-code bus I-code bus DMA ETHERNET(1) 10/100 MAC IEEE 1588 HIGH-SPEED USB0(1) HOST/ DEVICE/OTG HIGH-SPEED USB1(1) HOST/DEVICE LCD(1) SD/ MMC masters slaves AHB MULTILAYER MATRIX slaves BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE BRIDGE 64 kB ROM 32 kB LOCAL SRAM 40 kB LOCAL SRAM RI TIMER I2C1 CGU ALARM TIMER USART0 MOTOR CONTROL PWM(1) USART2 10-bit DAC CCU1 BACKUP REGISTERS UART1 I2C0 USART3 C_CAN0 CCU2 POWER MODE CONTROL SSP0 I2S0 TIMER2 10-bit ADC0 RGU TIMER0 I2S1 CONFIGURATION REGISTERS TIMER3 10-bit ADC1 TIMER1 C_CAN1 WWDT SCU GPIO INTERRUPTS EVENT ROUTER SSP1 OTP MEMORY QEI(1) RTC RTC OSC GIMA 12 MHz IRC GPIO GROUP0 INTERRUPT RTC POWER DOMAIN 32 kB AHB SRAM 16 kB + 16 kB AHB SRAM 16 kB EEPROM 512/256 kB FLASH A 512/256 kB FLASH B SCT EMC HS GPIO SPI SGPIO SPIFI GPIO GROUP1 INTERRUPT = connected to DMA 002aah234 (1) Not available on all parts. See Table 2. Fig 1. LPC435x/3x/2x/1x Block diagram LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 7 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 6. Pinning information 6.1 Pinning LPC435x/3xFET256 ball A1 index area 2 1 4 3 6 5 8 7 10 9 12 11 14 13 ball A1 index area 16 LPC433x/2x/1xFET100 1 15 A 2 3 4 5 6 7 8 A B C B E C D F D G E H J F L G K M H N J P R K T 002aah179 002aah177 Transparent top view Transparent top view Pin configuration TFBGA100 package 108 104 109 LPC4357/53FBD208 Fig 4. LPC433x/2x/1xFBD144 144 37 1 52 53 1 208 72 002aah180 Pin configuration LQFP208 package Fig 5. 36 157 73 Fig 3. 105 Pin configuration LBGA256 package 156 Fig 2. 9 10 002aah181 Pin configuration LQFP144 package 6.2 Pin description On the LPC435x/3x/2x/1x, digital pins are grouped into 16 ports, named P0 to P9 and PA to PF, with up to 20 pins used per port. Each digital pin can support up to eight different digital functions, including General Purpose I/O (GPIO), selectable through the System Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port assigned to it. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 8 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Type 32 Description [1] LQFP144 47 Reset state LQFP208 TFBGA100 Pin name Pin description LBGA256 Table 3. Multiplexed digital pins P0_0 P0_1 L3 M2 G2 G1 50 34 [2] [2] N; PU N; PU I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). I/O SGPIO0 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O GPIO0[1] — General purpose digital input/output pin. I/O SSP1_MOSI — Master Out Slave in for SSP1. I ENET_COL — Ethernet Collision detect (MII interface). I/O SGPIO1 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). P1_0 P2 LPC435X_3X_2X_1X Preliminary data sheet H1 54 38 [2] N; PU I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O GPIO0[4] — General purpose digital input/output pin. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. I/O EMC_A5 — External memory address line 5. - R — Function reserved. - R — Function reserved. I/O SSP0_SSEL — Slave Select for SSP0. I/O SGPIO7 — General purpose digital input/output pin. I/O EMC_D12 — External memory data line 12. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 9 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_2 P1_3 P1_4 58 42 R3 P5 T3 LPC435X_3X_2X_1X Preliminary data sheet K1 J1 J2 60 61 64 43 44 47 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type K2 Description [1] LQFP144 R2 Reset state LQFP208 P1_1 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_7 — SCT output 7. Match output 3 of timer 1. I/O EMC_A6 — External memory address line 6. I/O SGPIO8 — General purpose digital input/output pin. - R — Function reserved. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved. I/O EMC_D13 — External memory data line 13. I/O GPIO0[9] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_6 — SCT output 6. Match output 2 of timer 1. I/O EMC_A7 — External memory address line 7. I/O SGPIO9 — General purpose digital input/output pin. - R — Function reserved. I/O SSP0_MOSI — Master Out Slave in for SSP0. - R — Function reserved. I/O EMC_D14 — External memory data line 14. I/O GPIO0[10] — General purpose digital input/output pin. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. I/O SGPIO10 — General purpose digital input/output pin. O EMC_OE — LOW active Output Enable signal. O USB0_IND1 — USB0 port indicator LED control output 1. I/O SSP1_MISO — Master In Slave Out for SSP1. - R — Function reserved. O SD_RST — SD/MMC reset signal for MMC4.4 card. I/O GPIO0[11] — General purpose digital input/output pin. O CTOUT_9 — SCT output 9. Match output 3 of timer 3. I/O SGPIO11 — General purpose digital input/output pin. O EMC_BLS0 — LOW active Byte Lane select signal 0. O USB0_IND0 — USB0 port indicator LED control output 0. I/O SSP1_MOSI — Master Out Slave in for SSP1. I/O EMC_D15 — External memory data line 15. O SD_VOLT1 — SD/MMC bus voltage select output 1. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 10 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_6 P1_7 65 48 T4 T5 K4 G4 67 69 49 50 [2] [2] [2] N; PU N; PU N; PU Type J4 Description [1] LQFP144 R5 Reset state LQFP208 P1_5 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO1[8] — General purpose digital input/output pin. O CTOUT_10 — SCT output 10. Match output 3 of timer 3. - R — Function reserved. O EMC_CS0 — LOW active Chip Select 0 signal. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). I/O SSP1_SSEL — Slave Select for SSP1. I/O SGPIO15 — General purpose digital input/output pin. O SD_POW — SD/MMC power monitor output. I/O GPIO1[9] — General purpose digital input/output pin. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. - R — Function reserved. O EMC_WE — LOW active Write Enable signal. - R — Function reserved. O EMC_BLS0 — LOW active Byte Lane select signal 0. I/O SGPIO14 — General purpose digital input/output pin. I/O SD_CMD — SD/MMC command signal. I/O GPIO1[0] — General purpose digital input/output pin. I U1_DSR — Data Set Ready input for UART1. O CTOUT_13 — SCT output 13. Match output 3 of timer 3. I/O EMC_D0 — External memory data line 0. O USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active HIGH). Add a pull-down resistor to disable the power switch at reset. This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts. LPC435X_3X_2X_1X Preliminary data sheet - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 11 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_9 P1_10 P1_11 71 51 T7 R8 T9 LPC435X_3X_2X_1X Preliminary data sheet J5 H6 J7 73 75 77 52 53 55 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type H5 Description [1] LQFP144 R7 Reset state LQFP208 P1_8 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO1[1] — General purpose digital input/output pin. O U1_DTR — Data Terminal Ready output for UART1. O CTOUT_12 — SCT output 12. Match output 3 of timer 3. I/O EMC_D1 — External memory data line 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. O SD_VOLT0 — SD/MMC bus voltage select output 0. I/O GPIO1[2] — General purpose digital input/output pin. O U1_RTS — Request to Send output for UART1. O CTOUT_11 — SCT output 11. Match output 3 of timer 2. I/O EMC_D2 — External memory data line 2. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SD_DAT0 — SD/MMC data bus line 0. I/O GPIO1[3] — General purpose digital input/output pin. I U1_RI — Ring Indicator input for UART1. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. I/O EMC_D3 — External memory data line 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SD_DAT1 — SD/MMC data bus line 1. I/O GPIO1[4] — General purpose digital input/output pin. I U1_CTS — Clear to Send input for UART1. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. I/O EMC_D4 — External memory data line 4. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SD_DAT2 — SD/MMC data bus line 2. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 12 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_13 P1_14 P1_15 78 56 R10 R11 T12 LPC435X_3X_2X_1X Preliminary data sheet H8 J8 K8 83 85 87 60 61 62 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type K7 Description [1] LQFP144 R9 Reset state LQFP208 P1_12 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO1[5] — General purpose digital input/output pin. I U1_DCD — Data Carrier Detect input for UART1. - R — Function reserved. I/O EMC_D5 — External memory data line 5. I T0_CAP1 — Capture input 1 of timer 0. - R — Function reserved. I/O SGPIO8 — General purpose digital input/output pin. I/O SD_DAT3 — SD/MMC data bus line 3. I/O GPIO1[6] — General purpose digital input/output pin. O U1_TXD — Transmitter output for UART1. - R — Function reserved. I/O EMC_D6 — External memory data line 6. I T0_CAP0 — Capture input 0 of timer 0. - R — Function reserved. I/O SGPIO9 — General purpose digital input/output pin. I SD_CD — SD/MMC card detect input. I/O GPIO1[7] — General purpose digital input/output pin. I U1_RXD — Receiver input for UART1. - R — Function reserved. I/O EMC_D7 — External memory data line 7. O T0_MAT2 — Match output 2 of timer 0. - R — Function reserved. I/O SGPIO10 — General purpose digital input/output pin. - R — Function reserved. I/O GPIO0[2] — General purpose digital input/output pin. O U2_TXD — Transmitter output for USART2. I/O SGPIO2 — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). O T0_MAT1 — Match output 1 of timer 0. - R — Function reserved. I/O EMC_D8 — External memory data line 8. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 13 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_17 P1_18 P1_19 90 64 M8 N12 M11 LPC435X_3X_2X_1X Preliminary data sheet H10 J10 K9 93 95 96 66 67 68 [2] [3] [2] [2] N; PU N; PU N; PU N; PU Type H9 Description [1] LQFP144 M7 Reset state LQFP208 P1_16 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO0[3] — General purpose digital input/output pin. I U2_RXD — Receiver input for USART2. I/O SGPIO3 — General purpose digital input/output pin. I ENET_CRS — Ethernet Carrier Sense (MII interface). O T0_MAT0 — Match output 0 of timer 0. - R — Function reserved. I/O EMC_D9 — External memory data line 9. I ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). I/O GPIO0[12] — General purpose digital input/output pin. I/O U2_UCLK — Serial clock input/output for USART2 in synchronous mode. - R — Function reserved. I/O ENET_MDIO — Ethernet MIIM data input and output. I T0_CAP3 — Capture input 3 of timer 0. O CAN1_TD — CAN1 transmitter output. I/O SGPIO11 — General purpose digital input/output pin. - R — Function reserved. I/O GPIO0[13] — General purpose digital input/output pin. I/O U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. - R — Function reserved. O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). O T0_MAT3 — Match output 3 of timer 0. I CAN1_RD — CAN1 receiver input. I/O SGPIO12 — General purpose digital input/output pin. I/O EMC_D10 — External memory data line 10. I ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). I/O SSP1_SCK — Serial clock for SSP1. - R — Function reserved. - R — Function reserved. O CLKOUT — Clock output pin. - R — Function reserved. O I2S0_RX_MCLK — I2S receive master clock. I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 14 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P2_0 100 70 T16 G10 108 75 [2] [2] N; PU N; PU Type K10 Description [1] LQFP144 M10 Reset state LQFP208 P1_20 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1. - R — Function reserved. O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). I T0_CAP2 — Capture input 2 of timer 0. - R — Function reserved. I/O SGPIO13 — General purpose digital input/output pin. I/O EMC_D11 — External memory data line 11. I/O SGPIO4 — General purpose digital input/output pin. O U0_TXD — Transmitter output for USART0. See Table 4 for ISP mode. I/O EMC_A13 — External memory address line 13. O USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active HIGH). Add a pull-down resistor to disable the power switch at reset. This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts. P2_1 N15 LPC435X_3X_2X_1X Preliminary data sheet G7 116 81 [2] N; PU I/O GPIO5[0] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP0 — Capture input 0 of timer 3. O ENET_MDC — Ethernet MIIM clock. I/O SGPIO5 — General purpose digital input/output pin. I U0_RXD — Receiver input for USART0. See Table 4 for ISP mode. I/O EMC_A12 — External memory address line 12. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). I/O GPIO5[1] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP1 — Capture input 1 of timer 3. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 15 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P2_3 121 84 J12 D8 127 87 [2] [3] N; PU N; PU Type F5 Description [1] LQFP144 M15 Reset state LQFP208 P2_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O SGPIO6 — General purpose digital input/output pin. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O EMC_A11 — External memory address line 11. O USB0_IND1 — USB0 port indicator LED control output 1. I/O GPIO5[2] — General purpose digital input/output pin. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. I T3_CAP2 — Capture input 2 of timer 3. O EMC_CS1 — LOW active Chip Select 1 signal. I/O SGPIO12 — General purpose digital input/output pin. I/O I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). O U3_TXD — Transmitter output for USART3. See Table 4 for ISP mode. I CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. I/O GPIO5[3] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT0 — Match output 0 of timer 3. O USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active HIGH). Add a pull-down resistor to disable the power switch at reset. This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts. P2_4 K11 LPC435X_3X_2X_1X Preliminary data sheet D9 128 88 [3] N; PU I/O SGPIO13 — General purpose digital input/output pin. I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). I U3_RXD — Receiver input for USART3. See Table 4 for ISP mode. I CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. I/O GPIO5[4] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT1 — Match output 1 of timer 3. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 16 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 131 91 [3] N; PU Type D10 Description [1] LQFP144 K14 Reset state LQFP208 P2_5 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O SGPIO14 — General purpose digital input/output pin. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. I USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur. P2_6 P2_7 P2_8 K16 H14 J16 LPC435X_3X_2X_1X Preliminary data sheet G9 C10 C6 137 138 140 95 96 98 [2] [2] [2] N; PU N; PU N; PU I ADCTRIG1 — ADC trigger input 1. I/O GPIO5[5] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT2 — Match output 2 of timer 3. O USB0_IND0 — USB0 port indicator LED control output 0. I/O SGPIO7 — General purpose digital input/output pin. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O EMC_A10 — External memory address line 10. O USB0_IND0 — USB0 port indicator LED control output 0. I/O GPIO5[6] — General purpose digital input/output pin. I CTIN_7 — SCT input 7. I T3_CAP3 — Capture input 3 of timer 3. O EMC_BLS1 — LOW active Byte Lane select signal 1. I/O GPIO0[7] — General purpose digital input/output pin. If this pin is pulled LOW at reset, the part enters ISP mode or boots from an external source (see Table 4 and Table 5). O CTOUT_1 — SCT output 1. Match output 3 of timer 3. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. I/O EMC_A9 — External memory address line 9. - R — Function reserved. - R — Function reserved. O T3_MAT3 — Match output 3 of timer 3. - R — Function reserved. I/O SGPIO15 — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_0 — SCT output 0. Match output 0 of timer 0. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O EMC_A8 — External memory address line 8. I/O GPIO5[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 17 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P2_10 P2_11 P2_12 144 102 G16 F16 E15 LPC435X_3X_2X_1X Preliminary data sheet E8 A9 B9 146 148 153 104 105 106 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type B10 Description [1] LQFP144 H16 Reset state LQFP208 P2_9 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_3 — SCT output 3. Match output 3 of timer 0. I/O U3_BAUD — Baud pin for USART3. I/O EMC_A0 — External memory address line 0. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO0[14] — General purpose digital input/output pin. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. O U2_TXD — Transmitter output for USART2. I/O EMC_A1 — External memory address line 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO1[11] — General purpose digital input/output pin. O CTOUT_5 — SCT output 5. Match output 3 of timer 3. I U2_RXD — Receiver input for USART2. I/O EMC_A2 — External memory address line 2. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO1[12] — General purpose digital input/output pin. O CTOUT_4 — SCT output 4. Match output 3 of timer 3. - R — Function reserved. I/O EMC_A3 — External memory address line 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O U2_UCLK — Serial clock input/output for USART2 in synchronous mode. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 18 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_0 P3_1 156 108 F13 G11 LPC435X_3X_2X_1X Preliminary data sheet A8 F7 161 163 112 114 [2] [2] [2] N; PU N; PU N; PU Type A10 Description [1] LQFP144 C16 Reset state LQFP208 P2_13 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO1[13] — General purpose digital input/output pin. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. - R — Function reserved. I/O EMC_A4 — External memory address line 4. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O I2S0_RX_MCLK — I2S receive master clock. I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O I2S0_TX_MCLK — I2S transmit master clock. I/O SSP0_SCK — Serial clock for SSP0. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I CAN0_RD — CAN receiver input. O USB1_IND1 — USB1 Port indicator LED control output 1. I/O GPIO5[8] — General purpose digital input/output pin. - R — Function reserved. O LCD_VD15 — LCD data. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 19 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_3 P3_4 166 116 B14 A15 LPC435X_3X_2X_1X Preliminary data sheet A7 B8 169 171 118 119 [2] [4] [2] OL; PU N; PU N; PU Type G6 Description [1] LQFP144 F11 Reset state LQFP208 P3_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O CAN0_TD — CAN transmitter output. O USB1_IND0 — USB1 Port indicator LED control output 0. I/O GPIO5[9] — General purpose digital input/output pin. - R — Function reserved. O LCD_VD14 — LCD data. - R — Function reserved. - R — Function reserved. I/O SPI_SCK — Serial clock for SPI. I/O SSP0_SCK — Serial clock for SSP0. O SPIFI_SCK — Serial clock for SPIFI. O CGU_OUT1 — CGU spare clock output 1. - R — Function reserved. O I2S0_TX_MCLK — I2S transmit master clock. I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O GPIO1[14] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SPIFI_SIO3 — I/O lane 3 for SPIFI. O U1_TXD — Transmitter output for UART 1. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O LCD_VD13 — LCD data. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 20 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_6 P3_7 P3_8 173 121 B13 C11 C10 LPC435X_3X_2X_1X Preliminary data sheet C7 D7 E7 174 176 179 122 123 124 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type B7 Description [1] LQFP144 C12 Reset state LQFP208 P3_5 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO1[15] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SPIFI_SIO2 — I/O lane 2 for SPIFI. I U1_RXD — Receiver input for UART 1. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O I2S1_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O LCD_VD12 — LCD data. I/O GPIO0[6] — General purpose digital input/output pin. I/O SPI_MISO — Master In Slave Out for SPI. I/O SSP0_SSEL — Slave Select for SSP0. I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1. - R — Function reserved. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SPI_MOSI — Master Out Slave In for SPI. I/O SSP0_MISO — Master In Slave Out for SSP0. I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0. I/O GPIO5[10] — General purpose digital input/output pin. I/O SSP0_MOSI — Master Out Slave in for SSP0. - R — Function reserved. - R — Function reserved. - R — Function reserved. I SPI_SSEL — Slave Select for SPI. Note that this pin in an input pin only. The SPI in master mode cannot drive the CS input on the slave. Any GPIO pin can be used for SPI chip select in master mode. I/O SSP0_MOSI — Master Out Slave in for SSP0. I/O SPIFI_CS — SPIFI serial flash chip select. I/O GPIO5[11] — General purpose digital input/output pin. I/O SSP0_SSEL — Slave Select for SSP0. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 21 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P4_1 P4_2 P4_3 1 1 A1 D3 C2 LPC435X_3X_2X_1X Preliminary data sheet - - - 3 12 10 3 8 7 [2] [5] [2] [5] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 D5 Reset state LQFP208 P4_0 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO2[0] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. I NMI — External interrupt input to NMI. - R — Function reserved. - R — Function reserved. O LCD_VD13 — LCD data. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. - R — Function reserved. I/O GPIO2[1] — General purpose digital input/output pin. O CTOUT_1 — SCT output 1. Match output 3 of timer 3. O LCD_VD0 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD19 — LCD data. O U3_TXD — Transmitter output for USART3. I ENET_COL — Ethernet Collision detect (MII interface). AI ADC0_1 — ADC0 and ADC1, input channel 1. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I/O GPIO2[2] — General purpose digital input/output pin. O CTOUT_0 — SCT output 0. Match output 0 of timer 0. O LCD_VD3 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD12 — LCD data. I U3_RXD — Receiver input for USART3. I/O SGPIO8 — General purpose digital input/output pin. I/O GPIO2[3] — General purpose digital input/output pin. O CTOUT_3 — SCT output 3. Match output 3 of timer 0. O LCD_VD2 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD21 — LCD data. I/O U3_BAUD — Baud pin for USART3. I/O SGPIO9 — General purpose digital input/output pin. AI ADC0_0 — DAC, ADC0 and ADC1, input channel 0. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 22 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P4_5 P4_6 14 9 D2 C1 LPC435X_3X_2X_1X Preliminary data sheet - - 15 17 10 11 [5] [2] [2] N; PU N; PU N; PU Type - Description [1] LQFP144 B1 Reset state LQFP208 P4_4 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO2[4] — General purpose digital input/output pin. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. O LCD_VD1 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD20 — LCD data. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SGPIO10 — General purpose digital input/output pin. O DAC — DAC output. Configure the pin as GPIO input and use the analog function select register in the SCU to select the DAC. I/O GPIO2[5] — General purpose digital input/output pin. O CTOUT_5 — SCT output 5. Match output 3 of timer 3. O LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT). - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SGPIO11 — General purpose digital input/output pin. I/O GPIO2[6] — General purpose digital input/output pin. O CTOUT_4 — SCT output 4. Match output 3 of timer 3. O LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SGPIO12 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 23 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P4_8 P4_9 P4_10 21 14 E2 L2 M3 LPC435X_3X_2X_1X Preliminary data sheet - - - 23 48 51 15 33 35 [2] [2] [2] [2] O; PU N; PU N; PU N; PU Type - Description [1] LQFP144 H4 Reset state LQFP208 P4_7 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. O LCD_DCLK — LCD panel clock. I GP_CLKIN — General purpose clock input to the CGU. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. - R — Function reserved. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. O LCD_VD9 — LCD data. - R — Function reserved. I/O GPIO5[12] — General purpose digital input/output pin. O LCD_VD22 — LCD data. O CAN1_TD — CAN1 transmitter output. I/O SGPIO13 — General purpose digital input/output pin. - R — Function reserved. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. O LCD_VD11 — LCD data. - R — Function reserved. I/O GPIO5[13] — General purpose digital input/output pin. O LCD_VD15 — LCD data. I CAN1_RD — CAN1 receiver input. I/O SGPIO14 — General purpose digital input/output pin. - R — Function reserved. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. O LCD_VD10 — LCD data. - R — Function reserved. I/O GPIO5[14] — General purpose digital input/output pin. O LCD_VD14 — LCD data. - R — Function reserved. I/O SGPIO15 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 24 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P5_1 P5_2 P5_3 53 37 P3 R4 T8 LPC435X_3X_2X_1X Preliminary data sheet - - - 55 63 76 39 46 54 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 N3 Reset state LQFP208 P5_0 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO2[9] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I/O EMC_D12 — External memory data line 12. - R — Function reserved. I U1_DSR — Data Set Ready input for UART 1. I T1_CAP0 — Capture input 0 of timer 1. - R — Function reserved. - R — Function reserved. I/O GPIO2[10] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. I/O EMC_D13 — External memory data line 13. - R — Function reserved. O U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I T1_CAP1 — Capture input 1 of timer 1. - R — Function reserved. - R — Function reserved. I/O GPIO2[11] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. I/O EMC_D14 — External memory data line 14. - R — Function reserved. O U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I T1_CAP2 — Capture input 2 of timer 1. - R — Function reserved. - R — Function reserved. I/O GPIO2[12] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. I/O EMC_D15 — External memory data line 15. - R — Function reserved. I U1_RI — Ring Indicator input for UART 1. I T1_CAP3 — Capture input 3 of timer 1. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 25 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P5_5 P5_6 P5_7 80 57 P10 T13 R12 LPC435X_3X_2X_1X Preliminary data sheet - - - 81 89 91 58 63 65 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 P9 Reset state LQFP208 P5_4 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO2[13] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I/O EMC_D8 — External memory data line 8. - R — Function reserved. I U1_CTS — Clear to Send input for UART 1. O T1_MAT0 — Match output 0 of timer 1. - R — Function reserved. - R — Function reserved. I/O GPIO2[14] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. I/O EMC_D9 — External memory data line 9. - R — Function reserved. I U1_DCD — Data Carrier Detect input for UART 1. O T1_MAT1 — Match output 1 of timer 1. - R — Function reserved. - R — Function reserved. I/O GPIO2[15] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. I/O EMC_D10 — External memory data line 10. - R — Function reserved. O U1_TXD — Transmitter output for UART 1. O T1_MAT2 — Match output 2 of timer 1. - R — Function reserved. - R — Function reserved. I/O GPIO2[7] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I/O EMC_D11 — External memory data line 11. - R — Function reserved. I U1_RXD — Receiver input for UART 1. O T1_MAT3 — Match output 3 of timer 1. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 26 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_1 P6_2 105 73 R15 L13 LPC435X_3X_2X_1X Preliminary data sheet G5 J9 107 111 74 78 [2] [2] [2] N; PU N; PU N; PU Type H7 Description [1] LQFP144 M12 Reset state LQFP208 P6_0 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. O I2S0_RX_MCLK — I2S receive master clock. - R — Function reserved. - R — Function reserved. I/O I2S0_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO3[0] — General purpose digital input/output pin. O EMC_DYCS1 — SDRAM chip select 1. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. - R — Function reserved. I T2_CAP0 — Capture input 2 of timer 2. - R — Function reserved. - R — Function reserved. I/O GPIO3[1] — General purpose digital input/output pin. O EMC_CKEOUT1 — SDRAM clock enable 1. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. - R — Function reserved. I T2_CAP1 — Capture input 1 of timer 2. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 27 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 113 79 [2] N; PU Type - Description [1] LQFP144 P15 Reset state LQFP208 P6_3 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO3[2] — General purpose digital input/output pin. O USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that the VBUS signal must be driven (active HIGH). Add a pull-down resistor to disable the power switch at reset. This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts. P6_4 P6_5 P6_6 R16 P16 L14 LPC435X_3X_2X_1X Preliminary data sheet F6 F9 - 114 117 119 80 82 83 [2] [2] [2] N; PU N; PU N; PU I/O SGPIO4 — General purpose digital input/output pin. O EMC_CS1 — LOW active Chip Select 1 signal. - R — Function reserved. I T2_CAP2 — Capture input 2 of timer 2. - R — Function reserved. - R — Function reserved. I/O GPIO3[3] — General purpose digital input/output pin. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. O U0_TXD — Transmitter output for USART0. O EMC_CAS — LOW active SDRAM Column Address Strobe. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO3[4] — General purpose digital input/output pin. O CTOUT_6 — SCT output 6. Match output 2 of timer 1. I U0_RXD — Receiver input for USART0. O EMC_RAS — LOW active SDRAM Row Address Strobe. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO0[5] — General purpose digital input/output pin. O EMC_BLS1 — LOW active Byte Lane select signal 1. I/O SGPIO5 — General purpose digital input/output pin. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). - R — Function reserved. I T2_CAP3 — Capture input 3 of timer 2. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 28 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_8 P6_9 P6_10 123 85 H13 J15 H15 LPC435X_3X_2X_1X Preliminary data sheet - F8 - 125 139 142 86 97 100 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 J13 Reset state LQFP208 P6_7 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I/O EMC_A15 — External memory address line 15. I/O SGPIO6 — General purpose digital input/output pin. O USB0_IND1 — USB0 port indicator LED control output 1. I/O GPIO5[15] — General purpose digital input/output pin. O T2_MAT0 — Match output 0 of timer 2. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O EMC_A14 — External memory address line 14. I/O SGPIO7 — General purpose digital input/output pin. O USB0_IND0 — USB0 port indicator LED control output 0. I/O GPIO5[16] — General purpose digital input/output pin. O T2_MAT1 — Match output 1 of timer 2. - R — Function reserved. - R — Function reserved. I/O GPIO3[5] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O EMC_DYCS0 — SDRAM chip select 0. - R — Function reserved. O T2_MAT2 — Match output 2 of timer 2. - R — Function reserved. - R — Function reserved. I/O GPIO3[6] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. - R — Function reserved. O EMC_DQMOUT1 — Data mask 1 used with SDRAM and static devices. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 29 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_12 P7_0 P7_1 143 101 G15 B16 C14 LPC435X_3X_2X_1X Preliminary data sheet - - - 145 158 162 103 110 113 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type C9 Description [1] LQFP144 H12 Reset state LQFP208 P6_11 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO3[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O EMC_CKEOUT0 — SDRAM clock enable 0. - R — Function reserved. O T2_MAT3 — Match output 3 of timer 2. - R — Function reserved. - R — Function reserved. I/O GPIO2[8] — General purpose digital input/output pin. O CTOUT_7 — SCT output 7. Match output 3 of timer 1. - R — Function reserved. O EMC_DQMOUT0 — Data mask 0 used with SDRAM and static devices. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO3[8] — General purpose digital input/output pin. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. - R — Function reserved. O LCD_LE — Line end signal. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SGPIO4 — General purpose digital input/output pin. I/O GPIO3[9] — General purpose digital input/output pin. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O LCD_VD19 — LCD data. O LCD_VD7 — LCD data. - R — Function reserved. O U2_TXD — Transmitter output for USART2. I/O SGPIO5 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 30 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P7_3 P7_4 P7_5 165 115 C13 C8 A7 LPC435X_3X_2X_1X Preliminary data sheet - - - 167 189 191 117 132 133 [2] [2] [5] [5] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 A16 Reset state LQFP208 P7_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO3[10] — General purpose digital input/output pin. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O LCD_VD18 — LCD data. O LCD_VD6 — LCD data. - R — Function reserved. I U2_RXD — Receiver input for USART2. I/O SGPIO6 — General purpose digital input/output pin. I/O GPIO3[11] — General purpose digital input/output pin. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. - R — Function reserved. O LCD_VD17 — LCD data. O LCD_VD5 — LCD data. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO3[12] — General purpose digital input/output pin. O CTOUT_13 — SCT output 13. Match output 3 of timer 3. - R — Function reserved. O LCD_VD16 — LCD data. O LCD_VD4 — LCD data. O TRACEDATA[0] — Trace data, bit 0. - R — Function reserved. - R — Function reserved. AI ADC0_4 — ADC0 and ADC1, input channel 4. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I/O GPIO3[13] — General purpose digital input/output pin. O CTOUT_12 — SCT output 12. Match output 3 of timer 3. - R — Function reserved. O LCD_VD8 — LCD data. O LCD_VD23 — LCD data. O TRACEDATA[1] — Trace data, bit 1. - R — Function reserved. - R — Function reserved. AI ADC0_3 — ADC0 and ADC1, input channel 3. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 31 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P7_7 P8_0 P8_1 194 134 B6 E5 H5 LPC435X_3X_2X_1X Preliminary data sheet - - - 201 2 34 140 - - [2] [5] [3] [3] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 C7 Reset state LQFP208 P7_6 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO3[14] — General purpose digital input/output pin. O CTOUT_11 — SCT output 1. Match output 3 of timer 2. - R — Function reserved. O LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). - R — Function reserved. O TRACEDATA[2] — Trace data, bit 2. - R — Function reserved. - R — Function reserved. I/O GPIO3[15] — General purpose digital input/output pin. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. - R — Function reserved. O LCD_PWR — LCD panel power enable. - R — Function reserved. O TRACEDATA[3] — Trace data, bit 3. O ENET_MDC — Ethernet MIIM clock. I/O SGPIO7 — General purpose digital input/output pin. AI ADC1_6 — ADC1 and ADC0, input channel 6. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I/O GPIO4[0] — General purpose digital input/output pin. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). - R — Function reserved. I MCI2 — Motor control PWM channel 2, input. I/O SGPIO8 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O T0_MAT0 — Match output 0 of timer 0. I/O GPIO4[1] — General purpose digital input/output pin. O USB0_IND1 — USB0 port indicator LED control output 1. - R — Function reserved. I MCI1 — Motor control PWM channel 1, input. I/O SGPIO9 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O T0_MAT1 — Match output 1 of timer 0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 32 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P8_3 P8_4 P8_5 36 - J3 J2 J1 LPC435X_3X_2X_1X Preliminary data sheet - - - 37 39 40 - - - [3] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 K4 Reset state LQFP208 P8_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO4[2] — General purpose digital input/output pin. O USB0_IND0 — USB0 port indicator LED control output 0. - R — Function reserved. I MCI0 — Motor control PWM channel 0, input. I/O SGPIO10 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O T0_MAT2 — Match output 2 of timer 0. I/O GPIO4[3] — General purpose digital input/output pin. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. - R — Function reserved. O LCD_VD12 — LCD data. O LCD_VD19 — LCD data. - R — Function reserved. - R — Function reserved. O T0_MAT3 — Match output 3 of timer 0. I/O GPIO4[4] — General purpose digital input/output pin. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. - R — Function reserved. O LCD_VD7 — LCD data. O LCD_VD16 — LCD data. - R — Function reserved. - R — Function reserved. I T0_CAP0 — Capture input 0 of timer 0. I/O GPIO4[5] — General purpose digital input/output pin. I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0. - R — Function reserved. O LCD_VD6 — LCD data. O LCD_VD8 — LCD data. - R — Function reserved. - R — Function reserved. I T0_CAP1 — Capture input 1 of timer 0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 33 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P8_7 P8_8 P9_0 43 - K1 L1 T1 LPC435X_3X_2X_1X Preliminary data sheet - - - 45 49 59 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 K3 Reset state LQFP208 P8_6 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO4[6] — General purpose digital input/output pin. I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. - R — Function reserved. O LCD_VD5 — LCD data. O LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). - R — Function reserved. - R — Function reserved. I T0_CAP2 — Capture input 2 of timer 0. I/O GPIO4[7] — General purpose digital input/output pin. O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. - R — Function reserved. O LCD_VD4 — LCD data. O LCD_PWR — LCD panel power enable. - R — Function reserved. - R — Function reserved. I T0_CAP3 — Capture input 3 of timer 0. - R — Function reserved. I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CGU_OUT0 — CGU spare clock output 0. O I2S1_TX_MCLK — I2S1 transmit master clock. I/O GPIO4[12] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. - R — Function reserved. - R — Function reserved. - R — Function reserved. I ENET_CRS — Ethernet Carrier Sense (MII interface). I/O SGPIO0 — General purpose digital input/output pin. I/O SSP0_SSEL — Slave Select for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 34 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P9_2 P9_3 P9_4 66 - N8 M6 N10 LPC435X_3X_2X_1X Preliminary data sheet - - - 70 79 92 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 N6 Reset state LQFP208 P9_1 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO4[13] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I ENET_RX_ER — Ethernet receive error (MII interface). I/O SGPIO1 — General purpose digital input/output pin. I/O SSP0_MISO — Master In Slave Out for SSP0. I/O GPIO4[14] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I ENET_RXD3 — Ethernet receive data 3 (MII interface). I/O SGPIO2 — General purpose digital input/output pin. I/O SSP0_MOSI — Master Out Slave in for SSP0. I/O GPIO4[15] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB1_IND1 — USB1 Port indicator LED control output 1. - R — Function reserved. - R — Function reserved. I ENET_RXD2 — Ethernet receive data 2 (MII interface). I/O SGPIO9 — General purpose digital input/output pin. O U3_TXD — Transmitter output for USART3. - R — Function reserved. O MCOB0 — Motor control PWM channel 0, output B. O USB1_IND0 — USB1 Port indicator LED control output 0. - R — Function reserved. I/O GPIO5[17] — General purpose digital input/output pin. O ENET_TXD2 — Ethernet transmit data 2 (MII interface). I/O SGPIO4 — General purpose digital input/output pin. I U3_RXD — Receiver input for USART3. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 35 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 98 69 [2] N; PU Type - Description [1] LQFP144 M9 Reset state LQFP208 P9_5 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. O MCOA1 — Motor control PWM channel 1, output A. O USB1_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active high). Add a pull-down resistor to disable the power switch at reset. This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts. P9_6 PA_0 PA_1 L11 L12 J14 LPC435X_3X_2X_1X Preliminary data sheet - - - 103 126 134 72 - - [2] [2] [3] N; PU N; PU N; PU - R — Function reserved. I/O GPIO5[18] — General purpose digital input/output pin. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O SGPIO3 — General purpose digital input/output pin. O U0_TXD — Transmitter output for USART0. I/O GPIO4[11] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. I USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current condition; this signal monitors over-current on the USB1 bus (external circuitry required to detect over-current condition). - R — Function reserved. - R — Function reserved. I ENET_COL — Ethernet Collision detect (MII interface). I/O SGPIO8 — General purpose digital input/output pin. I U0_RXD — Receiver input for USART0. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O I2S1_RX_MCLK — I2S1 receive master clock. O CGU_OUT1 — CGU spare clock output 1. - R — Function reserved. I/O GPIO4[8] — General purpose digital input/output pin. I QEI_IDX — Quadrature Encoder Interface INDEX input. - R — Function reserved. O U2_TXD — Transmitter output for USART2. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 36 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PA_3 PA_4 PB_0 136 - H11 G13 B15 LPC435X_3X_2X_1X Preliminary data sheet - - - 147 151 164 - - - [3] [3] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 K15 Reset state LQFP208 PA_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O GPIO4[9] — General purpose digital input/output pin. I QEI_PHB — Quadrature Encoder Interface PHB input. - R — Function reserved. I U2_RXD — Receiver input for USART2. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O GPIO4[10] — General purpose digital input/output pin. I QEI_PHA — Quadrature Encoder Interface PHA input. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_9 — SCT output 9. Match output 3 of timer 3. - R — Function reserved. I/O EMC_A23 — External memory address line 23. I/O GPIO5[19] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_10 — SCT output 10. Match output 3 of timer 3. O LCD_VD23 — LCD data. - R — Function reserved. I/O GPIO5[20] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 37 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PB_2 PB_3 PB_4 175 - B12 A13 B11 LPC435X_3X_2X_1X Preliminary data sheet - - - 177 178 180 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 A14 Reset state LQFP208 PB_1 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. O LCD_VD22 — LCD data. - R — Function reserved. I/O GPIO5[21] — General purpose digital input/output pin. O CTOUT_6 — SCT output 6. Match output 2 of timer 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. O LCD_VD21 — LCD data. - R — Function reserved. I/O GPIO5[22] — General purpose digital input/output pin. O CTOUT_7 — SCT output 7. Match output 3 of timer 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. O LCD_VD20 — LCD data. - R — Function reserved. I/O GPIO5[23] — General purpose digital input/output pin. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. O LCD_VD15 — LCD data. - R — Function reserved. I/O GPIO5[24] — General purpose digital input/output pin. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 38 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PB_6 PC_0 PC_1 181 - A6 D4 E4 LPC435X_3X_2X_1X Preliminary data sheet - - - - 7 9 - - - [2] [5] [5] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 A12 Reset state LQFP208 PB_5 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4. O LCD_VD14 — LCD data. - R — Function reserved. I/O GPIO5[25] — General purpose digital input/output pin. I CTIN_7 — SCT input 7. O LCD_PWR — LCD panel power enable. - R — Function reserved. - R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3. O LCD_VD13 — LCD data. - R — Function reserved. I/O GPIO5[26] — General purpose digital input/output pin. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. O LCD_VD19 — LCD data. - R — Function reserved. AI ADC0_6 — ADC0 and ADC1, input channel 6. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. - R — Function reserved. I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. - R — Function reserved. I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface). O LCD_DCLK — LCD panel clock. - R — Function reserved. - R — Function reserved. I/O SD_CLK — SD/MMC card clock. AI ADC1_1 — ADC1 and ADC0, input channel 1. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. - R — Function reserved. I U1_RI — Ring Indicator input for UART 1. O ENET_MDC — Ethernet MIIM clock. I/O GPIO6[0] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP0 — Capture input 0 of timer 3. O SD_VOLT0 — SD/MMC bus voltage select output 0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 39 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_3 PC_4 13 - F5 F4 - - 11 16 - - [2] [5] [2] N; PU N; PU N; PU Type - Description [1] LQFP144 F6 Reset state LQFP208 PC_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. - R — Function reserved. I U1_CTS — Clear to Send input for UART 1. O ENET_TXD2 — Ethernet transmit data 2 (MII interface). I/O GPIO6[1] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O SD_RST — SD/MMC reset signal for MMC4.4 card. I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. - R — Function reserved. O U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O GPIO6[2] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O SD_VOLT1 — SD/MMC bus voltage select output 1. AI ADC1_0 — DAC, ADC1 and ADC0, input channel 0. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. - R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4. - R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). PC_5 G4 LPC435X_3X_2X_1X Preliminary data sheet - 20 - [2] N; PU I/O GPIO6[3] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP1 — Capture input 1 of timer 3. I/O SD_DAT0 — SD/MMC data bus line 0. - R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3. - R — Function reserved. O ENET_TX_ER — Ethernet Transmit Error (MII interface). I/O GPIO6[4] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP2 — Capture input 2 of timer 3. I/O SD_DAT1 — SD/MMC data bus line 1. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 40 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_7 PC_8 PC_9 22 - G5 N4 K2 LPC435X_3X_2X_1X Preliminary data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 H6 Reset state LQFP208 PC_6 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. - R — Function reserved. I ENET_RXD2 — Ethernet receive data 2 (MII interface). I/O GPIO6[5] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP3 — Capture input 3 of timer 3. I/O SD_DAT2 — SD/MMC data bus line 2. - R — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. - R — Function reserved. I ENET_RXD3 — Ethernet receive data 3 (MII interface). I/O GPIO6[6] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT0 — Match output 0 of timer 3. I/O SD_DAT3 — SD/MMC data bus line 3. - R — Function reserved. I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0. - R — Function reserved. I ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). I/O GPIO6[7] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT1 — Match output 1 of timer 3. I SD_CD — SD/MMC card detect input. - R — Function reserved. I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. - R — Function reserved. I ENET_RX_ER — Ethernet receive error (MII interface). I/O GPIO6[8] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT2 — Match output 2 of timer 3. O SD_POW — SD/MMC power monitor output. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 41 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_11 PC_12 PC_13 - - L5 L6 M1 LPC435X_3X_2X_1X Preliminary data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 M5 Reset state LQFP208 PC_10 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. I U1_DSR — Data Set Ready input for UART 1. - R — Function reserved. I/O GPIO6[9] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT3 — Match output 3 of timer 3. I/O SD_CMD — SD/MMC command signal. - R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI data line direction. I U1_DCD — Data Carrier Detect input for UART 1. - R — Function reserved. I/O GPIO6[10] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SD_DAT4 — SD/MMC data bus line 4. - R — Function reserved. - R — Function reserved. O U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. - R — Function reserved. I/O GPIO6[11] — General purpose digital input/output pin. I/O SGPIO11 — General purpose digital input/output pin. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SD_DAT5 — SD/MMC data bus line 5. - R — Function reserved. - R — Function reserved. O U1_TXD — Transmitter output for UART 1. - R — Function reserved. I/O GPIO6[12] — General purpose digital input/output pin. I/O SGPIO12 — General purpose digital input/output pin. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O SD_DAT6 — SD/MMC data bus line 6. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 42 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_0 PD_1 PD_2 - - N2 P1 R1 LPC435X_3X_2X_1X Preliminary data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 N1 Reset state LQFP208 PC_14 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. - R — Function reserved. I U1_RXD — Receiver input for UART 1. - R — Function reserved. I/O GPIO6[13] — General purpose digital input/output pin. I/O SGPIO13 — General purpose digital input/output pin. O ENET_TX_ER — Ethernet Transmit Error (MII interface). I/O SD_DAT7 — SD/MMC data bus line 7. - R — Function reserved. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. O EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices. - R — Function reserved. I/O GPIO6[14] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO4 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O EMC_CKEOUT2 — SDRAM clock enable 2. - R — Function reserved. I/O GPIO6[15] — General purpose digital input/output pin. O SD_POW — SD/MMC power monitor output. - R — Function reserved. I/O SGPIO5 — General purpose digital input/output pin. - R — Function reserved. O CTOUT_7 — SCT output 7. Match output 3 of timer 1. I/O EMC_D16 — External memory data line 16. - R — Function reserved. I/O GPIO6[16] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO6 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 43 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_4 PD_5 PD_6 - - T2 P6 R6 LPC435X_3X_2X_1X Preliminary data sheet - - - - - 68 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 P4 Reset state LQFP208 PD_3 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. O CTOUT_6 — SCT output 7. Match output 2 of timer 1. I/O EMC_D17 — External memory data line 17. - R — Function reserved. I/O GPIO6[17] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO7 — General purpose digital input/output pin. - R — Function reserved. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. I/O EMC_D18 — External memory data line 18. - R — Function reserved. I/O GPIO6[18] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO8 — General purpose digital input/output pin. - R — Function reserved. O CTOUT_9 — SCT output 9. Match output 3 of timer 3. I/O EMC_D19 — External memory data line 19. - R — Function reserved. I/O GPIO6[19] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO9 — General purpose digital input/output pin. - R — Function reserved. O CTOUT_10 — SCT output 10. Match output 3 of timer 3. I/O EMC_D20 — External memory data line 20. - R — Function reserved. I/O GPIO6[20] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO10 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 44 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_8 PD_9 PD_10 72 - P8 T11 P11 LPC435X_3X_2X_1X Preliminary data sheet - - - 74 84 86 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 T6 Reset state LQFP208 PD_7 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. I/O EMC_D21 — External memory data line 21. - R — Function reserved. I/O GPIO6[21] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO11 — General purpose digital input/output pin. - R — Function reserved. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. I/O EMC_D22 — External memory data line 22. - R — Function reserved. I/O GPIO6[22] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO12 — General purpose digital input/output pin. - R — Function reserved. O CTOUT_13 — SCT output 13. Match output 3 of timer 3. I/O EMC_D23 — External memory data line 23. - R — Function reserved. I/O GPIO6[23] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO13 — General purpose digital input/output pin. - R — Function reserved. I CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. O EMC_BLS3 — LOW active Byte Lane select signal 3. - R — Function reserved. I/O GPIO6[24] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 45 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_12 PD_13 PD_14 88 - N11 T14 R13 LPC435X_3X_2X_1X Preliminary data sheet - - - 94 97 99 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 N9 Reset state LQFP208 PD_11 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. - R — Function reserved. O EMC_CS3 — LOW active Chip Select 3 signal. - R — Function reserved. I/O GPIO6[25] — General purpose digital input/output pin. I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. O EMC_CS2 — LOW active Chip Select 2 signal. - R — Function reserved. I/O GPIO6[26] — General purpose digital input/output pin. - R — Function reserved. O CTOUT_10 — SCT output 10. Match output 3 of timer 3. - R — Function reserved. - R — Function reserved. I CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. O EMC_BLS2 — LOW active Byte Lane select signal 2. - R — Function reserved. I/O GPIO6[27] — General purpose digital input/output pin. - R — Function reserved. O CTOUT_13 — SCT output 13. Match output 3 of timer 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. O EMC_DYCS2 — SDRAM chip select 2. - R — Function reserved. I/O GPIO6[28] — General purpose digital input/output pin. - R — Function reserved. O CTOUT_11 — SCT output 11. Match output 3 of timer 2. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 46 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_16 PE_0 PE_1 101 - R14 P14 N14 LPC435X_3X_2X_1X Preliminary data sheet - - - 104 106 112 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 T15 Reset state LQFP208 PD_15 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. - R — Function reserved. I/O EMC_A17 — External memory address line 17. - R — Function reserved. I/O GPIO6[29] — General purpose digital input/output pin. I SD_WP — SD/MMC card write protect input. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O EMC_A16 — External memory address line 16. - R — Function reserved. I/O GPIO6[30] — General purpose digital input/output pin. O SD_VOLT2 — SD/MMC bus voltage select output 2. O CTOUT_12 — SCT output 12. Match output 3 of timer 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O EMC_A18 — External memory address line 18. I/O GPIO7[0] — General purpose digital input/output pin. O CAN1_TD — CAN1 transmitter output. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O EMC_A19 — External memory address line 19. I/O GPIO7[1] — General purpose digital input/output pin. I CAN1_RD — CAN1 receiver input. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 47 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_3 PE_4 PE_5 115 - K12 K13 N16 LPC435X_3X_2X_1X Preliminary data sheet - - - 118 120 122 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 M14 Reset state LQFP208 PE_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I ADCTRIG0 — ADC trigger input 0. I CAN0_RD — CAN receiver input. - R — Function reserved. I/O EMC_A20 — External memory address line 20. I/O GPIO7[2] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CAN0_TD — CAN transmitter output. I ADCTRIG1 — ADC trigger input 1. I/O EMC_A21 — External memory address line 21. I/O GPIO7[3] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I NMI — External interrupt input to NMI. - R — Function reserved. I/O EMC_A22 — External memory address line 22. I/O GPIO7[4] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_3 — SCT output 3. Match output 3 of timer 0. O U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I/O EMC_D24 — External memory data line 24. I/O GPIO7[5] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 48 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_7 PE_8 PE_9 124 - F15 F14 E16 LPC435X_3X_2X_1X Preliminary data sheet - - - 149 150 152 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 M16 Reset state LQFP208 PE_6 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. I U1_RI — Ring Indicator input for UART 1. I/O EMC_D25 — External memory data line 25. I/O GPIO7[6] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_5 — SCT output 5. Match output 3 of timer 3. I U1_CTS — Clear to Send input for UART1. I/O EMC_D26 — External memory data line 26. I/O GPIO7[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_4 — SCT output 4. Match output 3 of timer 3. I U1_DSR — Data Set Ready input for UART 1. I/O EMC_D27 — External memory data line 27. I/O GPIO7[8] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. I U1_DCD — Data Carrier Detect input for UART 1. I/O EMC_D28 — External memory data line 28. I/O GPIO7[9] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 49 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_11 PE_12 PE_13 154 - D16 D15 G14 LPC435X_3X_2X_1X Preliminary data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type - Description [1] LQFP144 E14 Reset state LQFP208 PE_10 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. O U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I/O EMC_D29 — External memory data line 29. I/O GPIO7[10] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_12 — SCT output 12. Match output 3 of timer 3. O U1_TXD — Transmitter output for UART 1. I/O EMC_D30 — External memory data line 30. I/O GPIO7[11] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_11 — SCT output 11. Match output 3 of timer 2. I U1_RXD — Receiver input for UART 1. I/O EMC_D31 — External memory data line 31. I/O GPIO7[12] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. I/O I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). O EMC_DQMOUT3 — Data mask 3 used with SDRAM and static devices. I/O GPIO7[13] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 50 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_15 PF_0 PF_1 - - E13 D12 E11 LPC435X_3X_2X_1X Preliminary data sheet - - - - 159 - - - - [2] [2] [2] [2] N; PU N; PU O; PU N; PU Type - Description [1] LQFP144 C15 Reset state LQFP208 PE_14 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. O EMC_DYCS3 — SDRAM chip select 3. I/O GPIO7[14] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CTOUT_0 — SCT output 0. Match output 0 of timer 0. I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). O EMC_CKEOUT3 — SDRAM clock enable 3. I/O GPIO7[15] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SSP0_SCK — Serial clock for SSP0. I GP_CLKIN — General purpose clock input to the CGU. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O I2S1_TX_MCLK — I2S1 transmit master clock. - R — Function reserved. - R — Function reserved. I/O SSP0_SSEL — Slave Select for SSP0. - R — Function reserved. I/O GPIO7[16] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO0 — General purpose digital input/output pin. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 51 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PF_3 PF_4 PF_5 168 - E10 D10 E9 LPC435X_3X_2X_1X Preliminary data sheet - H4 - 170 172 190 - 120 - [2] [2] [2] [5] N; PU N; PU O; PU N; PU Type - Description [1] LQFP144 D11 Reset state LQFP208 PF_2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. O U3_TXD — Transmitter output for USART3. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved. I/O GPIO7[17] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO1 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I U3_RXD — Receiver input for USART3. I/O SSP0_MOSI — Master Out Slave in for SSP0. - R — Function reserved. I/O GPIO7[18] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO2 — General purpose digital input/output pin. - R — Function reserved. I/O SSP1_SCK — Serial clock for SSP1. I GP_CLKIN — General purpose clock input to the CGU. O TRACECLK — Trace clock. - R — Function reserved. - R — Function reserved. - R — Function reserved. O I2S0_TX_MCLK — I2S transmit master clock. I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. - R — Function reserved. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. I/O SSP1_SSEL — Slave Select for SSP1. O TRACEDATA[0] — Trace data, bit 0. I/O GPIO7[19] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO4 — General purpose digital input/output pin. - R — Function reserved. AI ADC1_4 — ADC1 and ADC0, input channel 4. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 52 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PF_7 PF_8 192 - B7 E6 LPC435X_3X_2X_1X Preliminary data sheet - - 193 - - - [5] [5] [5] N; PU N; PU N; PU Type - Description [1] LQFP144 E7 Reset state LQFP208 PF_6 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1. O TRACEDATA[1] — Trace data, bit 1. I/O GPIO7[20] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO5 — General purpose digital input/output pin. I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. AI ADC1_3 — ADC1 and ADC0, input channel 3. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. - R — Function reserved. I/O U3_BAUD — Baud pin for USART3. I/O SSP1_MOSI — Master Out Slave in for SSP1. O TRACEDATA[2] — Trace data, bit 2. I/O GPIO7[21] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO6 — General purpose digital input/output pin. I/O I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. AI/ O ADC1_7 — ADC1 and ADC0, input channel 7 or band gap output. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. - R — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. O TRACEDATA[3] — Trace data, bit 3. I/O GPIO7[22] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO7 — General purpose digital input/output pin. - R — Function reserved. AI ADC0_2 — ADC0 and ADC1, input channel 2. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 53 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PF_10 PF_11 203 - A3 A2 LPC435X_3X_2X_1X Preliminary data sheet - - 205 207 - - [5] [5] [5] N; PU N; PU N; PU Type - Description [1] LQFP144 D6 Reset state LQFP208 PF_9 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. O CTOUT_1 — SCT output 1. Match output 3 of timer 3. - R — Function reserved. I/O GPIO7[23] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO3 — General purpose digital input/output pin. - R — Function reserved. AI ADC1_2 — ADC1 and ADC0, input channel 2. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. - R — Function reserved. O U0_TXD — Transmitter output for USART0. - R — Function reserved. - R — Function reserved. I/O GPIO7[24] — General purpose digital input/output pin. - R — Function reserved. I SD_WP — SD/MMC card write protect input. - R — Function reserved. AI ADC0_5 — ADC0 and ADC1, input channel 5. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. - R — Function reserved. I U0_RXD — Receiver input for USART0. - R — Function reserved. - R — Function reserved. I/O GPIO7[25] — General purpose digital input/output pin. - R — Function reserved. O SD_VOLT2 — SD/MMC bus voltage select output 2. - R — Function reserved. AI ADC1_5 — ADC1 and ADC0, input channel 5. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 54 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 62 45 Type LQFP144 K3 Description [1] LQFP208 N5 Reset state TFBGA100 Pin name Pin description …continued LBGA256 Table 3. Clock pins CLK0 CLK1 CLK2 CLK3 T10 D14 P12 LPC435X_3X_2X_1X Preliminary data sheet - K6 - - 141 - - 99 - [4] [4] [4] [4] O; PU O; PU O; PU O; PU O EMC_CLK0 — SDRAM clock 0. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. I/O SD_CLK — SD/MMC card clock. O EMC_CLK01 — SDRAM clock 0 and clock 1 combined. I/O SSP1_SCK — Serial clock for SSP1. I ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). O EMC_CLK1 — SDRAM clock 1. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CGU_OUT0 — CGU spare clock output 0. - R — Function reserved. O I2S1_TX_MCLK — I2S1 transmit master clock. O EMC_CLK3 — SDRAM clock 3. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. I/O SD_CLK — SD/MMC card clock. O EMC_CLK23 — SDRAM clock 2 and clock 3 combined. O I2S0_TX_MCLK — I2S transmit master clock. I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O EMC_CLK2 — SDRAM clock 2. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CGU_OUT1 — CGU spare clock output 1. - R — Function reserved. I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 55 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 41 28 Type A6 Description [1] LQFP144 L4 Reset state LQFP208 Pin name TFBGA100 Pin description …continued LBGA256 Table 3. Debug pins DBGEN [2] I I JTAG interface control signal. Also used for boundary scan. I; F I Test Clock for JTAG interface (default) or Serial Wire (SW) clock. TCK/SWDCLK J5 H2 38 27 [2] TRST M4 B4 42 29 [2] I; PU I Test Reset for JTAG interface. I; PU I Test Mode Select for JTAG interface (default) or SW debug data input/output. Test Data Out for JTAG interface (default) or SW trace output. TMS/SWDIO K6 C4 44 30 [2] TDO/SWO K5 H3 46 31 [2] O I; PU I Test Data In for JTAG interface. O J4 G3 35 26 [2] USB0_DP F2 E1 26 18 [6] - I/O USB0 bidirectional D+ line. Do not add an external series resistor. USB0_DM G2 E2 28 20 [6] - I/O USB0 bidirectional D line. Do not add an external series resistor. USB0_VBUS F1 E3 29 21 [6] - I/O VBUS pin (power on USB cable). This pin includes an internal pull-down resistor of 64 k (typical)  16 k. I Indicates to the transceiver whether connected as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this pin has an internal pull-up resistor. TDI USB0 pins [7] USB0_ID H2 F1 30 22 [8] - USB0_RREF H1 F3 32 24 [8] - USB1_DP F12 E9 129 89 [9] - I/O USB1 bidirectional D+ line. Add an external series resistor of 33  +/- 2 %. USB1_DM G12 E10 130 90 [9] - I/O USB1 bidirectional D line. Add an external series resistor of 33  +/- 2 %. I2C0_SCL L15 D6 132 92 [10] I; F I/O I2C clock input/output. Open-drain output (for I2C-bus compliance). I2C0_SDA L16 E6 133 93 [10] I; F I/O I2C data input/output. Open-drain output (for I2C-bus compliance). 12.0 k (accuracy 1 %) on-board resistor to ground for current reference. USB1 pins I2C-bus pins Reset and wake-up pins RESET D9 B6 185 128 [11] I; IA I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. WAKEUP0 A9 A4 187 130 [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration of at least 45 ns wakes up the part. - [11] Input 0 of the event monitor. WAKEUP1 A10 - - I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration of at least 45 ns wakes up the part. Input 1 of the event monitor. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 56 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - - [11] - [11] I; IA Type - Description [1] LQFP144 C9 Reset state LQFP208 WAKEUP2 TFBGA100 Pin name Pin description …continued LBGA256 Table 3. I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration of at least 45 ns wakes up the part. Input 2 of the event monitor. WAKEUP3 D8 LPC435X_3X_2X_1X Preliminary data sheet - - I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration of at least 45 ns wakes up the part. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 57 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP144 E3 A2 8 6 [8] I; IA I ADC input channel 0. Shared between 10-bit ADC0/1 and DAC. ADC0_1/ ADC1_1 C3 A1 4 2 [8] I; IA I ADC input channel 1. Shared between 10-bit ADC0/1. ADC0_2/ ADC1_2 A4 B3 206 143 [8] I; IA I ADC input channel 2. Shared between 10-bit ADC0/1. ADC0_3/ ADC1_3 B5 A3 200 139 [8] I; IA I ADC input channel 3. Shared between 10-bit ADC0/1. ADC0_4/ ADC1_4 C6 - 199 138 [8] I; IA I ADC input channel 4. Shared between 10-bit ADC0/1. ADC0_5/ ADC1_5 B3 - 208 144 [8] I; IA I ADC input channel 5. Shared between 10-bit ADC0/1. ADC0_6/ ADC1_6 A5 - 204 142 [8] I; IA I ADC input channel 6. Shared between 10-bit ADC0/1. ADC0_7/ ADC1_7 C5 - 197 136 [8] I; IA I ADC input channel 7. Shared between 10-bit ADC0/1. RTC_ALARM A11 C3 186 129 [11] - O RTC controlled output. RTCX1 A8 A5 182 125 [8] - I Input to the RTC 32 kHz ultra-low power oscillator circuit. RTCX2 B8 B5 183 126 [8] - O Output from the RTC 32 kHz ultra-low power oscillator circuit. O O Event monitor sample output. Type LQFP208 ADC0_0/ ADC1_0/DAC [1] TFBGA100 Description LBGA256 Pin name Reset state Table 3. ADC pins RTC SAMPLE B9 - - - [11] Crystal oscillator pins XTAL1 D1 B1 18 12 [8] - I Input to the oscillator circuit and internal clock generator circuits. XTAL2 E1 C1 19 13 [8] - O Output from the oscillator amplifier. Power and ground pins USB0_VDDA 3V3_DRIVER F3 D1 24 16 - - Separate analog 3.3 V power supply for driver. USB0 _VDDA3V3 G3 D2 25 17 - - USB 3.3 V separate power supply voltage. USB0_VSSA _TERM H3 D3 27 19 - - Dedicated analog ground for clean reference for termination resistors. USB0_VSSA _REF G1 F2 31 23 - - Dedicated clean analog ground for generation of reference currents and voltages. VDDA B4 B2 198 137 - - Analog power supply and ADC reference voltage. VBAT B10 C5 184 127 - - RTC power supply: 3.3 V on this pin supplies power to the RTC. VDDREG F10, F9, L8, L7 E4, E5, F4 135, 188, 195, 82, 33 94, 131, 59, 25 - Main regulator power supply. Tie the VDDREG and VDDIO pins to a common power supply to ensure the same ramp-up time for both supply voltages. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 58 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - - Type - Description [1] LQFP144 E8 Reset state LQFP208 VPP TFBGA100 Pin name Pin description …continued LBGA256 Table 3. [12] - - OTP programming voltage. - - I/O power supply. Tie the VDDREG and VDDIO pins to a common power supply to ensure the same ramp-up time for both supply voltages. VDDIO D7, F10, E12, K5 F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 6, 52, 57, 102, 110, 155, 160, 202 5, 36, 41, 71, 77, 107, 111, 141 [12] VSS G9, H7, J10, J11, K8 - - [13] - - Ground. VSSIO C4, D13, G6, G7, G8, H8, H9, J8, J9, K9, K10, M13, P7, P13 5, 56, 109, 157 4, 40, 76, 109 [13] - - Ground. VSSA B2 196 135 - - Analog ground. C8, D4, D5, G8, J3, J6 C2 [1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset without boot code operation. [2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength. [3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels, and hysteresis; high drive strength. [4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed digital I/O functions with TTL levels and hysteresis. [5] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP register. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 59 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller [6] 5 V tolerant transparent analog pad. [7] For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS = 0.2 V when it is no longer driven. [8] Transparent analog pad. Not 5 V tolerant. [9] Pad provides USB functions; 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. [11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis. [12] On the LQFP208, VPP is internally connected to VDDIO. [13] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 60 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-CODE bus, and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC435x/3x/2x/1x use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. An ARM Cortex-M0 co-processor is included in the LPC435x/3x/2x/1x, capable of off-loading the main ARM Cortex-M4 application processor. Most peripheral interrupts are connected to both processors. The processors communicate with each other via an interprocessor communication protocol. 7.2 ARM Cortex-M4 processor The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated in the core. The processor includes a NVIC with up to 53 interrupts. 7.3 ARM Cortex-M0 co-processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M0 co-processor uses a 3-stage pipeline von Neumann architecture and a small but powerful instruction set providing high-end processing hardware. The co-processor incorporates a NVIC with 32 interrupts. 7.4 Interprocessor communication The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on using shared SRAM as mailbox and one processor raising an interrupt on the other processor's NVIC, for example after it has delivered a new message in the mailbox. The receiving processor can reply by raising an interrupt on the sending processor's NVIC to acknowledge the message. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 61 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.5 AHB multilayer matrix HIGH-SPEED PHY TEST/DEBUG INTERFACE TEST/DEBUG INTERFACE ARM CORTEX-M4 ARM CORTEX-M0 System IDbus code code bus bus DMA 0 ETHERNET USB0 USB1 LCD SD/ MMC masters 1 slaves 256/512 kB FLASH A 256/512 kB FLASH B 16 kB EEPROM 64 kB ROM 32 kB LOCAL SRAM 40 kB LOCAL SRAM 32 kB AHB SRAM 16 kB AHB SRAM 16 kB AHB SRAM SPIFI EXTERNAL MEMORY CONTROLLER AHB PERIPHERALS REGISTER INTERFACES APB, RTC DOMAIN PERIPHERALS AHB MULTILAYER MATRIX = master-slave connection Fig 6. 002aah080 AHB multilayer matrix master and slave connections 7.6 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 62 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.6.1 Features • ARM Cortex-M4 core: – Controls system exceptions and peripheral interrupts – Support for up to 53 vectored interrupts – Eight programmable interrupt priority levels with hardware priority level masking – Relocatable vector table – Non-Maskable Interrupt (NMI) – Software interrupt generation • ARM Cortex-M0 core: – Support for up to 32 interrupts – Four programmable interrupt priority levels with hardware priority level masking 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.7 System Tick timer (SysTick) The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. 7.8 Event router The event router combines various internal signals, interrupts, and the external interrupt pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down, and Deep power-down modes. Individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router. The event router can be battery powered. The following events if enabled in the event router can create a wake-up signal from sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt: • External pins WAKEUP0/1/2/3 and RESET • Alarm timer, RTC (32 kHz oscillator running) The following events if enabled in the event router can create a wake-up signal from sleep mode only and/or create an interrupt: • • • • WWDT, BOD interrupts C_CAN0/1 and QEI interrupts Ethernet, USB0, USB1 signals Selected outputs of combined timers (SCT and timer0/1/3) Remark: Any interrupt can wake up the ARM Cortex-M4 from sleep mode if enabled in the NVIC. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 63 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.9 Global Input Multiplexer Array (GIMA) The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers, event router, or the ADCs. 7.9.1 Features • • • • • Single selection of a source. Signal inversion. Can capture a pulse if the input event source is faster than the target clock. Synchronization of input event and target clock. Single-cycle pulse generation for target. 7.10 On-chip static RAM The LPC435x/3x/2x/1x support up to 136 kB SRAM with separate bus master access for higher throughput and individual power control for low power operation. 7.11 On-chip flash memory The LPC435x/3x/2x/1x contain up to 1 MB of dual-bank flash program memory. With dual-bank flash memory, the user code can write or erase one flash bank while reading the other flash bank without interruption. A two-port flash accelerator maximizes the flash performance. In-System Programming (ISP) and In-Application Programming (IAP) routines for programming the flash memory are provided in the Boot ROM. 7.12 EEPROM The LPC435x/3x/2x/1x contain 16 kB of on-chip byte-erasable and byte-programmable EEPROM memory. The EEPROM memory is divided into 128 pages. The user can access pages 1 through 127. Page 128 is protected. 7.13 Boot ROM The internal ROM memory is used to store the boot code of the LPC435x/3x/2x/1x. After a reset, the ARM processor will start its code execution from this memory. The boot ROM memory includes the following features: • The ROM memory size is 64 kB. • Supports booting from external static memory such as NOR flash, SPI flash, quad SPI flash, USB0, and USB1. • Includes API for OTP programming. • Includes a flexible USB device stack that supports Human Interface Device (HID), Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 64 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Several boot modes are available if P2_7 is LOW on reset depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1. Table 4. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC BOOT_SRC BOOT_SRC bit 3 bit 2 bit 1 BOOT_SRC Description bit 0 Pin state 0 0 0 0 Boot source is defined by the reset state of P1_1, P1_2, P2_8 pins, and P2_9. See Table 5. USART0 0 0 0 1 Enter ISP mode using USART0 pins P2_0 and P2_1. SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI interface using pins P3_3 to P3_8. EMC 8-bit 0 0 1 1 Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. USB0 0 1 1 0 Boot from USB0. USB1 0 1 1 1 Boot from USB1. SPI (SSP) 1 0 0 0 Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7 (function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]. USART3 1 0 0 1 Enter ISP mode using USART3 pins P2_3 and P2_4. [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Remark: Pin functions for SPIFI and SSP0 boot are different. Table 5. Boot mode when OPT BOOT_SRC bits are zero Boot mode Pins Description P2_9 P2_8 P1_2 P1_1 USART0 LOW LOW LOW LOW Enter ISP mode using USART0 pins P2_0 and P2_1. SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI interface on P3_3 to P3_8[1]. EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. USB0 LOW HIGH LOW HIGH Boot from USB0 LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 65 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 5. Boot mode when OPT BOOT_SRC bits are zero Boot mode Pins Description P2_9 P2_8 P1_2 P1_1 USB1 LOW HIGH HIGH LOW Boot from USB1. SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7 (function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]. USART3 HIGH LOW LOW LOW Enter ISP mode using USART3 pins P2_3 and P2_4. [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Remark: Pin functions for SPIFI and SSP0 boot are different. 7.14 Memory mapping The memory map shown in Figure 7 and Figure 8 is global to both the Cortex-M4 and the Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between both processors. Each processor uses its own ARM private bus memory map for the NVIC and other system functions. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 66 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC435x/3x/2x/1x 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus reserved 128 MB SPIFI data 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved peripheral bit band alias region reserved 0xE000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 SGPIO SPI reserved high-speed GPIO reserved reserved 0x2000 0000 0x1F00 0000 0x1E00 0000 0x1D00 0000 0x1C00 0000 16 MB static external memory CS3 reserved 16 MB static external memory CS2 APB peripherals #3 16 MB static external memory CS1 reserved 16 MB static external memory CS0 APB peripherals #2 reserved reserved APB peripherals #1 0x1B08 0000 0x1B04 0000 0x1B00 0000 reserved 256 kB flash B APB peripherals #0 256 kB flash B clocking/reset peripherals RTC domain peripherals 256 kB flash A 256 kB flash A 0x1040 0000 0x1008 A000 256 MB dynamic external memory DYCS1 64 MB SPIFI data 128 MB dynamic external memory DYCS0 reserved 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4005 0000 0x4004 0000 0x4000 0000 0x3000 0000 0x2800 0000 reserved 0x2400 0000 64 kB ROM 32 MB AHB SRAM bit banding reserved 0x2200 0000 reserved 32 kB + 8 kB local SRAM 0x1008 0000 0x2004 4000 16 kB EEPROM reserved reserved 4 x 16 kB AHB SRAM 0x1000 8000 0x1000 0000 0x400F 2000 0x4001 2000 AHB peripherals 1 GB reserved 0x1041 0000 0x400F 4000 reserved 0x1800 0000 0x1400 0000 0x400F 8000 0x4006 0000 reserved 0x1A00 0000 0x4010 0000 reserved 0x1A08 0000 0x1A04 0000 0x4010 1000 local SRAM/flash/SPIFI data/ROM external static memory banks 32 kB local SRAM 0 GB 256 MB shadow area 0x2004 0000 0x2001 0000 0x2000 0000 0x1000 0000 0x0000 0000 002aah182 Fig 7. LPC435x/3x/2x/1x Memory mapping (overview) LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 67 of 151 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 0x400E 5000 reserved 0x400E 4000 ADC1 0x400E 3000 ADC0 0x400E 2000 C_CAN0 0x400E 1000 DAC 0x400E 0000 0x400C 8000 I2C1 0x400C 7000 0xFFFF FFFF APB3 peripherals external memories and ARM private bus 0x6000 0000 reserved peripheral bit band alias region reserved SGPIO GIMA Rev. 3 — 6 December 2012 QEI 0x400C 5000 SSP1 0x400C 4000 timer3 0x400C 3000 timer2 0x400C 2000 USART3 0x400C 1000 USART2 reserved 0x400C 0000 0x400B 0000 RI timer APB3 peripherals reserved reserved 0x400A 4000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 I2S1 I2S0 I2C0 0x4400 0000 reserved APB2 peripherals APB1 peripherals reserved APB1 peripherals reserved motor control PWM APB0 peripherals reserved GPIO GROUP1 interrupt GPIO GROUP0 interrupt GPIO interrupts clocking/reset peripherals RTC domain peripherals 68 of 151 © NXP B.V. 2012. All rights reserved. 0x4008 6000 SCU 0x4008 5000 timer1 0x4008 4000 timer0 0x4008 3000 SSP0 0x4008 2000 UART1 w/ modem SRAM, flash, EEPROM memories, SPIFI data, ROM external memory banks 0x4008 1000 USART0 256 MB memory shadow area 0x4008 0000 WWDT APB0 peripherals 0x4005 3000 0x4005 2000 CCU1 0x4005 1000 CGU 0x4005 0000 reserved 0x4005 0000 0x4004 7000 RTC/event monitor 0x4004 6000 OTP controller 0x4004 5000 event router 0x4004 4000 CREG 0x4004 3000 0x4010 2000 0x4010 1000 0x4010 0000 0x400F 8000 reserved RGU CCU2 0x4200 0000 reserved high-speed GPIO 0x4006 0000 0x4005 4000 0x400F 4000 RTC domain peripherals 0x400F 2000 power mode control 0x4004 2000 0x400F 1000 backup registers 0x4004 1000 0x400F 0000 alarm timer 0x400E 0000 0x400D 0000 reserved 0x400C 0000 ethernet 0x400B 0000 reserved 0x400A 0000 EEPROM controller flash B controller 0x4009 0000 flash A controller 0x4008 0000 0x4006 0000 reserved 0x4004 0000 0x4002 0000 0x4001 2000 0x4001 0000 0x4000 F000 0x4000 E000 0x4000 D000 0x4000 C000 0x4000 9000 LCD 0x4000 8000 USB1 0x4004 0000 0x4000 7000 USB0 0x4000 6000 0x4002 0000 EMC 0x4000 5000 0x4000 0000 SD/MMC 0x4000 4000 SPIFI 0x4000 3000 DMA 0x4000 2000 reserved 0x4000 1000 SCT 0x4000 0000 0x4005 0000 reserved AHB peripherals 0x1000 0000 0x0000 0000 AHB peripherals 002aah183 Fig 8. LPC435x/3x/2x/1x Memory mapping (peripherals) LPC435x/3x/2x/1x 0x4008 A000 0x4008 9000 0x4008 8000 0x4008 7000 C_CAN1 APB2 peripherals clocking reset control peripherals reserved 32-bit ARM Cortex-M4/M0 microcontroller All information provided in this document is subject to legal disclaimers. SPI 0x400C 6000 0x400A 5000 NXP Semiconductors LPC435X_3X_2X_1X Preliminary data sheet LPC435x/3x/2x/1x 0x400F 0000 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.15 One-Time Programmable (OTP) memory The OTP provides 64 bit of memory for general purpose use. 7.16 General Purpose I/O (GPIO) The LPC435x/3x/2x/1x provide eight GPIO ports with up to 31 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on reset. The input buffer must be turned on in the system control block SFS register before the GPIO input can be read. 7.16.1 Features • Accelerated GPIO functions: – GPIO registers are located on the AHB so that the fastest possible I/O timing can be achieved. – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte and half-word addressable. – Entire port value can be written in one instruction. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • Direction control of individual bits. • Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request (GPIO interrupts). • Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO group0 and group1 interrupts). 7.17 Configurable digital peripherals 7.17.1 State Configurable Timer (SCT) subsystem The SCT allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCT are shared with the capture and match inputs/outputs of the 32-bit general purpose counter/timers. The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: • State variable • Limit, halt, stop, and start conditions • Values of Match/Capture registers, plus reload or capture control values LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 69 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller In the two-counter case, the following operational elements are global to the SCT, but the last three can use match conditions from either counter: • • • • • 7.17.1.1 Clock selection Inputs Events Outputs Interrupts Features • • • • • Two 16-bit counters or one 32-bit counter. Counters clocked by bus clock or selected input. Up counters or up-down counters. State variable allows sequencing across multiple counter cycles. The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state. • Events control outputs, interrupts, and DMA requests. – Match register 0 can be used as an automatic limit. – In bi-directional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs. • Selected events can limit, halt, start, or stop a counter. • Supports: – 8 inputs – 16 outputs – 16 match/capture registers – 16 events – 32 states – Match register 0 to 5 support a fractional component for the dither engine 7.17.2 Serial GPIO (SGPIO) The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate serial stream processing. 7.17.2.1 Features • Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to serial data conversion. • 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value from a pin or an output value to a pin with every cycle of a shift clock. • Each slice is double-buffered. • Interrupt is generated on a full FIFO, shift clock, or pattern match. • Slices can be concatenated to increase buffer size. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 70 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Each slice has a 32-bit pattern match filter. 7.18 AHB peripherals 7.18.1 General Purpose DMA The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.18.1.1 Features • Eight DMA channels. Each channel can support a unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • Two AHB bus masters for transferring data. These interfaces transfer data when a DMA request goes active. Master 1 can access memories and peripherals, master 0 can access memories only. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.18.2 SPI Flash Interface (SPIFI) The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM Cortex-M4 processor with little performance penalty compared to parallel flash devices with higher pin count. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 71 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Simple sequences of commands handle erasing and programming. Many serial flash devices use a half-duplex command-driven SPI protocol for device setup and initialization and then move to a half-duplex, command-driven 4-bit protocol for normal operation. Different serial flash vendors and devices accept or require different commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.18.2.1 Features • • • • Interfaces to serial flash memory in the main memory map. Supports classic and 4-bit bidirectional serial protocols. Half-duplex protocol compatible with various vendors and devices. Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second. • Supports DMA access. 7.18.3 SD/MMC card interface The SD/MMC card interface supports the following modes to control: • • • • Secure Digital memory (SD version 3.0) Secure Digital I/O (SDIO version 2.0) Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1) MultiMedia Cards (MMC version 4.4) 7.18.4 External Memory Controller (EMC) Remark: The EMC is available on all LPC435x/3x/2x/1x parts. The following memory bus widths are supported: • • • • LBGA256 packages: 32 bit TFBGA100 packages: 8 bit LQFP208 packages: 16 bit LQFP144 packages: 16 bit The LPC435x/3x/2x/1x EMC is a Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. Table 6. Function LPC435X_3X_2X_1X Preliminary data sheet EMC pinout for different packages LBGA256 TFBGA100 LQFP208 A EMC_A[23:0] EMC_A[13:0] EMC_A[23:0] EMC_A[15:0] D EMC_D[31:0] EMC_D[7:0] EMC_D[15:0] EMC_D[15:0] BLS EMC_BLS[3:0] EMC_BLS0 EMC_BLS[1:0] EMC_BLS[1:0] CS EMC_CS[3:0] EMC_CS0 EMC_CS[1:0] EMC_CS[1:0] All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 LQFP144 © NXP B.V. 2012. All rights reserved. 72 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 6. 7.18.4.1 EMC pinout for different packages Function LBGA256 TFBGA100 LQFP208 LQFP144 OE EMC_OE EMC_OE EMC_OE EMC_OE WE EMC_WE EMC_WE EMC_WE EMC_WE CKEOUT EMC_ CKEOUT[3:0] EMC_ CKEOUT[1:0] EMC_ CKEOUT[1:0] EMC_ CKEOUT[1:0] CLK EMC_CLK[3:0]; EMC_CLK01, EMC_CLK23 EMC_CLK0, EMC_CLK3; EMC_CLK01, EMC_CLK23 EMC_CLK0, EMC_CLK3; EMC_CLK01, EMC_CLK23 EMC_CLK0, EMC_CLK3; EMC_CLK01, EMC_CLK23 DQMOUT EMC_ DQMOUT[3:0] - EMC_ DQMOUT[1:0] EMC_ DQMOUT[1:0] DYCS EMC_ DYCS[3:0] EMC_DYCS[1:0] EMC_DYCS[1:0] EMC_DYCS[1:0] CAS EMC_CAS EMC_CAS EMC_CAS EMC_CAS RAS EMC_RAS EMC_RAS EMC_RAS EMC_RAS Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and NOR flash, with or without asynchronous page mode. • • • • • Low transaction latency. Read and write buffers to reduce latency and to improve performance. 8/16/32 data and 24 address lines wide static memory support. 16 bit and 32 bit wide chip select SDRAM memory support. Static memory features include: – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. Those are typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 73 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.18.5 High-speed USB Host/Device/OTG interface (USB0) Remark: USB0 is available on the following parts: LPC435x, LPC433x, LPC432x. USB0 is not available on the LPC431x parts. The USB OTG module allows the LPC435x/3x/2x/1x to connect directly to a USB Host such as a PC (in device mode) or to a USB Device in host mode. 7.18.5.1 Features • • • • • • • • • • • • Contains UTMI+ compliant high-speed transceiver (PHY). Complies with Universal Serial Bus specification 2.0. Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals. Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. Supports interrupts. Supports Start Of Frame (SOF) frame length adjust. This module has its own, integrated DMA engine. USB interface electrical test software included in ROM USB stack. 7.18.6 High-speed USB Host/Device interface with ULPI (USB1) Remark: USB1 is available on the following parts: LPC435x and LPC433x. USB1 is not available on the LPC432x and LPC431x parts. The USB1 interface can operate as a full-speed USB Host/Device interface or can connect to an external ULPI PHY for High-speed operation. 7.18.6.1 Features • • • • Complies with Universal Serial Bus specification 2.0. • • • • • Supports all full-speed USB-compliant peripherals. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals if connected to external ULPI PHY. Supports interrupts. Supports Start Of Frame (SOF) frame length adjust. This module has its own, integrated DMA engine. USB interface electrical test software included in ROM USB stack. 7.18.7 LCD controller Remark: The LCD controller is only available on parts LPC435x. LCD is not available on parts LPC433x, LPC432x, and LPC431x. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 74 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller The LCD controller provides all of the necessary control signals to interface directly to various color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of the displayed data) while still supporting many colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time required to operate the display. 7.18.7.1 Features • • • • AHB master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320  200, 320  240, 640  200, 640  240, 640  480, 800  600, and 1024  768. • • • • • • • • • • • • Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized for color STN and TFT. 24 bpp true-color non-palettized for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.18.8 Ethernet Remark: The ethernet controller is available on parts LPC435x and LPC433x. Ethernet is not available on parts LPC432x and LPC431x. 7.18.8.1 Features • 10/100 Mbit/s • DMA support • Power management remote wake-up frame and magic packet detection LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 75 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation. – Back-pressure support for half-duplex operation. – Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation. • Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE 1588-2008 v2). 7.19 Digital serial peripherals 7.19.1 UART1 Remark: The LPC435x/3x/2x/1x contain one UART with standard transmit and receive data lines. UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.19.1.1 Features • • • • • Maximum UART data bit rate of 8 MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • Equipped with standard modem interface signals. This module also provides full support for hardware flow control. • Support for RS-485/9-bit/EIA-485 mode (UART1). • DMA support. 7.19.2 USART0/2/3 Remark: The LPC435x/3x/2x/1x contain three USARTs. In addition to standard transmit and receive data lines, the USARTs support a synchronous mode. The USARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 76 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.19.2.1 Features • • • • • Maximum UART data bit rate of 8 MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • • • • • Support for RS-485/9-bit/EIA-485 mode. USART3 includes an IrDA mode to support infrared communication. All USARTs have DMA support. Support for synchronous mode at a data bit rate of up to 8 Mbit/s. Smart card mode conforming to ISO7816 specification 7.19.3 SPI serial I/O controller Remark: The LPC435x/3x/2x/1x contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.19.3.1 Features • • • • • • Maximum SPI data bit rate Compliant with SPI specification Synchronous, serial, full duplex communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate 8 bits to 16 bits per transfer 7.19.4 SSP serial I/O controller Remark: The LPC435x/3x/2x/1x contain two SSP controllers. The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.19.4.1 Features • Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s (master) and 15 Mbit/s (slave) LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 77 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA 7.19.5 I2C-bus interface Remark: The LPC435x/3x/2x/1x each contain two I2C-bus interfaces. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (for example an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.19.5.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • • • • • • I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.19.6 I2S interface Remark: The LPC435x/3x/2x/1x each contain two I2S-bus interfaces. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 78 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.19.6.1 Features • The I2S interfaces has separate input/output channels, each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96, 192) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests controlled by programmable buffer levels. The DMA requests are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. 7.19.7 C_CAN Remark: The LPC435x/3x/2x/1x each contain two C_CAN controllers. Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a high level of reliability. 7.19.7.1 Features • • • • • • • Conforms to protocol version 2.0 parts A and B. Supports bit rate of up to 1 Mbit/s. Supports 32 Message Objects. Each Message Object has its own identifier mask. Provides programmable FIFO mode (concatenation of Message Objects). Provides maskable interrupts. Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. • Provides programmable loop-back mode for self-test operation. 7.20 Counter/timers and motor control 7.20.1 General purpose 32-bit timers/external event counters Remark: The LPC435x/3x/2x/1x include four 32-bit timer/counters. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 79 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event can also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 7.20.2 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input causes the PWM to release all motor drive outputs immediately . At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 7.20.3 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user code can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.20.3.1 Features • • • • • LPC435X_3X_2X_1X Preliminary data sheet Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with “less than” interrupt. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 80 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • • • • • Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). 7.20.4 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare function can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.20.4.1 Features • 32-bit counter. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This mechanism allows for combinations not possible with a simple compare. 7.20.5 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.20.5.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) uses the IRC as the clock source. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 81 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.21 Analog peripherals 7.21.1 Analog-to-Digital Converter (ADC0/1) Remark: The LPC435x/3x/2x/1x contain two 10-bit ADCs. 7.21.1.1 Features • • • • • • • 10-bit successive approximation analog to digital converter. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 to VDDA. Sampling frequency up to 400 kSamples/s. Burst conversion mode for single or multiple inputs. Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer outputs 8 or 15, or the PWM output MCOA2. • Individual result registers for each A/D channel to reduce interrupt overhead. • DMA support. 7.21.2 Digital-to-Analog Converter (DAC) 7.21.2.1 Features • • • • 10-bit resolution Monotonic by design (resistor string architecture) Controllable conversion speed Low power consumption 7.22 Peripherals in the RTC power domain 7.22.1 RTC The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power when the CPU does not access its registers, especially in the reduced power modes. A separate 32 kHz oscillator clocks the RTC. The oscillator produces a 1 Hz internal time reference and is powered by its own power supply pin, VBAT. 7.22.1.1 Features • Measures the passage of time to maintain a calendar and clock. Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. • Ultra-low power design to support battery powered systems. Less than required for battery operation. Uses power from the CPU power supply when it is present. • • • • LPC435X_3X_2X_1X Preliminary data sheet Dedicated battery power supply pin. RTC power supply is isolated from the rest of the chip. Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution. Periodic interrupts can be generated from increments of any field of the time registers. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 82 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Alarm interrupt can be generated for a specific date/time. 7.22.1.2 Event monitor/recorder The event monitor/recorder allows recording and creating a time stamp of events related to the WAKEUP pins. Sensors report changes to the state of the WAKEUP pins, and the event monitor/recorder stores records of such events. The event recorder can be powered by the backup battery. The event monitor/recorder can monitor the integrity of the device and record any tampering events. Features • Supports three digital event inputs in the VBAT power domain. • An event is defined as a level change at the digital event inputs. • For each event channel, two timestamps mark the first and the last occurrence of an event. Each channel also has a dedicated counter tracking the total number of events. Timestamp values are taken from the RTC. • Runs in VBAT power domain, independent of system power supply. The event/recorder/monitor can therefore operate in Deep power-down mode. • • • • Low power consumption. Interrupt available if system is running. A qualified event can be used as a wake-up trigger. State of event interrupts accessible by software through GPIO. 7.22.2 Alarm timer The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled. The alarm timer is part of the RTC power domain and can be battery powered. 7.23 System control 7.23.1 Configuration registers (CREG) The following settings are controlled in the configuration register block: • • • • • • • BOD trip settings Oscillator output DMA-to-peripheral muxing Ethernet mode Memory mapping Timer/USART inputs Enabling the USB controllers In addition, the CREG block contains the part identification and part configuration information. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 83 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.23.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. For pins that support a digital and analog function, the ADC function select registers in the SCU enable the analog function. A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are located on separate pads and are not controlled through the SCU. In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that select the pin interrupts are located in the SCU. 7.23.3 Clock Generation Unit (CGU) The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be unrelated in frequency and phase and can have different clock sources within the CGU. One CGU base clock is routed to the CLKOUT pins. The base clock that generates the CPU clock is referred to as CCLK. Multiple branch clocks are derived from each base clock. The branch clocks offer flexible control for power-management purposes. All branch clocks are outputs of one of two Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. 7.23.4 Internal RC oscillator (IRC) The IRC is used as the clock source for the WWDT and/or as the clock that drives the PLLs and the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC435x/3x/2x/1x use the IRC as the clock source. The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and PLL0USB or PLL0AUDIO as needed if an external boot source is selected. 7.23.5 PLL0USB (for USB0) PLL0 is a dedicated PLL for the USB0 High-speed controller. PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz. 7.23.6 PLL0AUDIO (for audio) The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This PLL accepts an input clock frequency derived from an external oscillator or internal IRC. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired output frequency. The output frequency can be set as a multiple of the sampling frequency fs to 32fs, 64fs, 128  fs, 256  fs, 384  fs, 512  fs and the sampling frequency fs can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other frequencies are possible as well using the integrated fractional divider. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 84 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.23.7 System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz. This range is possible through an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset. After reset, software can enable the PLL. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.23.8 Reset Generation Unit (RGU) The RGU allows generation of independent reset signals for individual blocks and peripherals on the LPC435x/3x/2x/1x. 7.23.9 Power Management Controller (PMC) The PMC controls the power to the cores, peripherals, and memories. The LPC435x/3x/2x/1x support the following power modes in order from highest to lowest power consumption: 1. Active mode 2. Sleep mode 3. Power-down modes: a. Deep-sleep mode b. Power-down mode c. Deep power-down mode Active mode and sleep mode apply to the state of the core. In a dual-core system, either core can be in active or sleep mode independently of the other core. If the core is in Active mode, it is fully operational and can access peripherals and memories as configured by software. If the core is in Sleep mode, it receives no clocks, but peripherals and memories remain running. Either core can enter sleep mode from active mode independently of the other core and while the other core remains in active mode or is in sleep mode. Power-down modes apply to the entire system. In the Power-down modes, both cores and all peripherals except for peripherals in the always-on power domain are shut down. Memories can remain powered for retaining memory contents as defined by the individual power-down mode. Either core in active mode can put the part into one of the three power down modes if the core is enabled to do so. If both cores are enabled for putting the system into power-down, then the system enters power-down only once both cores have received a WFI or WFE instruction. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 85 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. The interrupt is captured in the NVIC and an event is captured in the Event router. Both cores can wake up from sleep mode independently of each other. Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down, is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer. When waking up from Deep power-down mode, the part resets and attempts to boot. 7.23.10 Power control The LPC435x/3x/2x/1x feature several independent power domains to control power to the core and the peripherals (see Figure 9). The RTC and its associated peripherals (the alarm timer, the CREG block, the OTP controller, the back-up registers, and the event router) are located in the RTC power-domain. The main regulator or a battery supply can power the RTC. A power selector switch ensures that the RTC block is always powered on. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 86 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC43xx VDDIO to I/O pads to cores VSS REGULATOR to memories, peripherals, oscillators, PLLs VDDREG MAIN POWER DOMAIN ULTRA LOW-POWER REGULATOR VBAT to RTC domain peripherals RESET/WAKE-UP CONTROL to RTC I/O pads (Vps) RESET WAKEUP0/1/2/3 BACKUP REGISTERS RTCX1 RTCX2 32 kHz OSCILLATOR REAL-TIME CLOCK ALARM ALWAYS-ON/RTC POWER DOMAIN DAC VDDA VSSA ADC ADC POWER DOMAIN OTP VPP OTP POWER DOMAIN USB0_VDDA3V_DRIVER USB0_VDDA3V3 USB0 USB0 POWER DOMAIN 002aag378 Fig 9. Power domains 7.23.11 Code security (Code Read Protection - CRP) CRP enables different levels of security so that access to the on-chip flash and use of the JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by CRP. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 87 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller There are three levels of the Code Read Protection: • In level CRP1, access to the chip via the JTAG is disabled. Partial flash updates are allowed (excluding flash sector 0) using a limited set of the ISP commands. This level is useful when CRP is required and flash field updates are needed. CRP1 does prevent the user code from erasing all sectors. • In level CRP2, access to the chip via the JTAG is disabled. Only a full flash erase and update using a reduced set of the ISP commands is allowed. • In level CRP3, any access to the chip via the JTAG pins or the ISP is disabled. This mode also disables the ISP override using P2_7 pin. If necessary, the application code must provide a flash update mechanism using the IAP calls or using the reinvoke ISP command to enable flash update via USART0. See Table 5 CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.24 Serial Wire Debug/JTAG Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four watch points. Remark: Serial Wire Debug is supported for the ARM Cortex-M4 only, The ARM Cortex-M0 coprocessor supports JTAG debug. A standard ARM Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex-M0 cores separately or both cores simultaneously. Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the RGU block. LPC43xx TCK TMS TRST TDI TCK TMS TRST TDI ARM Cortex-M0 TDO JTAG ID = 0x0BA0 1477 TDO DBGEN RESET TCK ARM Cortex-M4 TMS TRST TDI TDO JTAG ID = 0x4BA0 0477 DBGEN = HIGH RESET = HIGH 002aah448 Fig 10. Dual-core debug configuration LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 88 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(REG)(3V3) regulator supply voltage (3.3 V) on pin VDDREG 0.5 3.6 V VDD(IO) input/output supply voltage on pin VDDIO 0.5 3.6 V VDDA(3V3) analog supply voltage (3.3 V) on pin VDDA 0.5 3.6 V VBAT battery supply voltage on pin VBAT 0.5 3.6 V Vprog(pf) polyfuse programming voltage on pin VPP 0.5 3.6 V VI input voltage when VDD(IO)  2.2 V 0.5 5.5 V ADC/DAC pins and digital I/O pins configured for an analog function 0.5 VDDA(3V3) V USB0 pins USB0_DP; USB0_DM;USB0_VBUS 0.3 5.2 V USB0 pins USB0_ID; USB0_RREF 0.3 3.6 V USB1 pins USB1_DP and USB1_DM 0.3 5.2 V [2] 5 V tolerant digital I/O pins IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(IO)) < VI < (1.5VDD(IO)); - 100 mA Tstg storage temperature 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins  2000 V Tj < 125 C [1] [3] [4] The following applies to the limiting values: a) Absolute maximum ratings state the extreme limits that the product can withstand without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. Conditions for functional operation of the part are shown in Table 11 “Static characteristics”. b) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Dependent on package type. [4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 89 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 8. Thermal characteristics VDD = 2.2 V to 3.6 V. Symbol Parameter Tj(max) maximum junction temperature Table 9. Conditions Min Typ Max Unit - - 125 C Thermal resistance (LQFP packages) Symbol Parameter Thermal resistance in C/W ±15 % Conditions LQFP144 Rth(j-a) Rth(j-c) 31 Single-layer (4.5 in  3 in); 50 still air 39 11 10 thermal resistance from junction to case Table 10. Thermal resistance value (BGA packages) Symbol Parameter Conditions Thermal resistance in C/W ±15 % LBGA256 Rth(j-a) thermal resistance from JEDEC (4.5 in  4 in); 29 junction to ambient still air 8-layer (4.5 in  3 in); still air Rth(j-c) LPC435X_3X_2X_1X Preliminary data sheet LQFP208 thermal resistance from JEDEC (4.5 in  4 in); still 38 junction to ambient air thermal resistance from junction to case All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 TFBGA100 46 24 37 14 11 © NXP B.V. 2012. All rights reserved. 90 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit 2.2 - 3.6 V 2.2 - 3.6 V 2.2 - 3.6 V Supply pins VDD(IO) input/output supply voltage VDD(REG)(3V3) regulator supply voltage (3.3 V) VDDA(3V3) analog supply voltage (3.3 V) VBAT battery supply voltage [2] 2.2 - 3.6 V Vprog(pf) polyfuse programming voltage on pin VPP (for OTP) [3] 2.7 - 3.6 V Iprog(pf) polyfuse programming current on pin VPP; OTP programming time  1.6 ms - - 30 mA IDD(REG)(3V3) regulator supply current Active mode; ARM (3.3 V) Cortex-M0 core in reset; code [2] on pin VDDA while(1){} executed from RAM; all peripherals disabled; PLL1 enabled IDD(REG)(3V3) CCLK = 12 MHz [4] CCLK = 60 MHz [4] CCLK = 120 MHz [4] CCLK = 180 MHz [4] CCLK = 204 MHz [4] 9.3 - mA 26 - mA - 46 - mA - 66 - mA - 75 - mA [4][5] - 6.2 - mA deep-sleep mode [4] - 145 - A power-down mode [4] - 23 - A [4][6] - 0.05 - A [4] - 3.0 - A [7] - 0.1 nA regulator supply current after WFE/WFI instruction (3.3 V) executed from RAM; all peripherals disabled; ARM Cortex-M0 core in reset sleep mode deep power-down mode deep power-down mode; VBAT floating IBAT - battery supply current LPC435X_3X_2X_1X Preliminary data sheet VBAT = 3.0 V; VDD(REG)(3V3) = 3.3 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 91 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IBAT Parameter battery supply current Conditions VDD(REG)(3V3) = 3.3 V; VBAT = 3.6 V deep-sleep mode IBAT IDD(IO) IDD(ADC) battery supply current I/O supply current ADC supply current Min Typ[1] Max Unit - 1.5 - A - 1.5 - A - 1.5 - A - 3.0 - A 1.5 - A [8] power-down mode [8] deep power-down mode [8] Deep power-down mode; RTC running; VDD(REG)(3V3) floating; VBAT = 3.3 V VDD(REG)(3V3) = VBAT = 3.3 V - deep sleep mode - - A power-down mode - - A deep power-down mode - - A deep sleep mode [10] - 0.4 - A power-down mode [10] - 0.4 - A deep power-down mode [10] - 0.007 - A V RESET pin VIH HIGH-level input voltage [9] 0.8  (Vps  0.35) 5.5 VIL LOW-level input voltage [9] 0.5 0.3  (Vps  V 0.1) Vhys hysteresis voltage [9] 0.05  (Vps  0.35) - V - - 2 pF - Standard I/O pins - normal drive strength CI input capacitance ILL LOW-level leakage current VI = 0 V; on-chip pull-up resistor disabled - 3 - nA ILH HIGH-level leakage current VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.5 - nA VI = 5 V; Tamb = 105 °C - 40 - nA IOZ OFF-state output current VO = 0 V to VDD(IO); on-chip pull-up/down resistors disabled; absolute value - 3 - nA VI input voltage pin configured to provide a digital function; 0 - 5.5 V 0 - 3.6 V 0 - VDD(IO) V 0.7  VDD(IO) - 5.5 V VDD(IO)  2.2 V VDD(IO) = 0 V VO output voltage VIH HIGH-level input voltage LPC435X_3X_2X_1X Preliminary data sheet output active All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 92 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit LOW-level input voltage 0.5 - 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V VOH HIGH-level output voltage IOH = 6 mA VDD(IO)  0.4 - - V VOL LOW-level output voltage IOL = 6 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(IO)  0.4 V 6 - - mA IOL LOW-level output current VOL = 0.4 V 6 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [11] - - 86.5 mA IOLS LOW-level short-circuit output current drive LOW; connected to VDD(IO) [11] - - 76.5 mA Ipd pull-down current VI = 5 V [13] - 93 - A - 62 - A - 10 - Symbol Parameter VIL Conditions [14] [15] Ipu pull-up current VI = 0 V [13] [14] [15] VDD(IO) < VI  5 V Rs series resistance on I/O pins with analog function; analog function enabled A  200 I/O pins - high drive strength CI input capacitance - - 2 pF ILL LOW-level leakage current VI = 0 V; on-chip pull-up resistor disabled - 3 - nA IOZ OFF-state output current VO = 0 V to VDD(IO); on-chip pull-up/down resistors disabled; absolute value - 3 - nA VI input voltage pin configured to provide a digital function; 0 - 5.5 V VDD(IO)  2.2 V VDD(IO) = 0 V 0 - 3.6 V 0 - VDD(IO) V HIGH-level input voltage 0.7  VDD(IO) - 5.5 V VIL LOW-level input voltage 0.5 - 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V VO output voltage VIH LPC435X_3X_2X_1X Preliminary data sheet output active All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 93 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Ipd Parameter pull-down current Min Typ[1] Max Unit - 62 - A - 62 - A - 10 - A VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.6 - nA VI = 5 V; Tamb = 105 °C - 65 - nA Conditions VI = VDD(IO) [13] [14] [15] Ipu pull-up current VI = 0 V [13] [14] [15] VDD(IO) < VI  5 V I/O pins - high drive strength: standard drive mode ILH HIGH-level leakage current IOH HIGH-level output current VOH = VDD(IO)  0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [11] - - 32 mA IOLS LOW-level short-circuit output current [11] - - 32 mA VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.7 - nA drive LOW; connected to VDD(IO) I/O pins - high drive strength: medium drive mode ILH HIGH-level leakage current VI = 5 V; Tamb = 105 °C - 70 - nA IOH HIGH-level output current VOH = VDD(IO)  0.4 V 8 - - mA IOL LOW-level output current VOL = 0.4 V 8 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [11] - - 65 mA IOLS LOW-level short-circuit output current [11] - - 63 mA VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.6 - nA VI = 5 V; Tamb = 105 °C - 63 - nA drive LOW; connected to VDD(IO) I/O pins - high drive strength: high drive mode ILH HIGH-level leakage current IOH HIGH-level output current VOH = VDD(IO)  0.4 V 14 - - mA IOL LOW-level output current VOL = 0.4 V 14 - - mA LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 94 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit - - 113 mA - - 110 mA VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.6 - nA VI = 5 V; Tamb = 105 °C - 63 - nA Conditions IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [11] IOLS LOW-level short-circuit output current [11] drive LOW; connected to VDD(IO) I/O pins - high drive strength: ultra-high drive mode ILH HIGH-level leakage current IOH HIGH-level output current VOH = VDD(IO)  0.4 V 20 - - mA IOL LOW-level output current VOL = 0.4 V 20 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [11] - - 165 mA IOLS LOW-level short-circuit output current [11] - - 156 mA - - 2 pF drive LOW; connected to VDD(IO) I/O pins - high-speed CI input capacitance ILL LOW-level leakage current VI = 0 V; on-chip pull-up resistor disabled - 3 - nA ILH HIGH-level leakage current VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.5 - nA VI = 5 V; Tamb = 105 °C - 40 - nA IOZ OFF-state output current VO = 0 V to VDD(IO); on-chip pull-up/down resistors disabled; absolute value - 3 - nA VI input voltage pin configured to provide a digital function; VDD(IO)  2.2 V 0 - 5.5 V VDD(IO) = 0 V 0 - 3.6 V 0 - VDD(IO) V VO output voltage VIH HIGH-level input voltage 0.7  VDD(IO) - 5.5 V VIL LOW-level input voltage 0.5 - 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V VOH HIGH-level output voltage VDD(IO)  0.4 - - V LPC435X_3X_2X_1X Preliminary data sheet output active IOH = 8 mA All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 95 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOL LOW-level output voltage IOL = 8 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(IO)  0.4 V 8 - - mA IOL LOW-level output current VOL = 0.4 V 8 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [11] - - 86 mA IOLS LOW-level short-circuit output current drive LOW; connected to VDD(IO) [11] - - 76 mA Ipd pull-down current VI = VDD(IO) [13] - 62 - A - 62 - A - 0 - A [14] [15] Ipu pull-up current VI = 0 V [13] [14] [15] VDD(IO) < VI  5 V Open-drain I2C0-bus pins VIH HIGH-level input voltage 0.7  VDD(IO) - - V VIL LOW-level input voltage 0.5 0.14 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V VOL LOW-level output voltage IOLS = 3 mA - - 0.4 V ILI input leakage current VI = VDD(IO) [12] VI = 5 V - 4.5 - A - - 10 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 - 1.2 V Vo(XTAL2) output voltage on pin XTAL2 0.5 - 1.2 V Cio input/output capacitance - - 0.8 pF VDD(IO)  2.2 V 0 - 5.5 V VDD(IO) = 0 V 0 - 3.6 V 64 80 k [16] USB0 pins[17] VI input voltage on pins USB0_DP; USB0_DM; USB0_VBUS Rpd pull-down resistance on pin USB0_VBUS 48 VIC common-mode input voltage high-speed mode 50 200 500 mV full-speed/low-speed mode 800 - 2500 mV chirp mode 50 - 600 mV LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 96 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Vi(dif) differential input voltage USB1 pins Min Typ[1] Max Unit 100 400 1100 mV [17] - - 10 A [18] - - 5.25 V Conditions (USB1_DP/USB1_DM)[17] IOZ OFF-state output current 0 V < VI < 3.3 V VBUS bus supply voltage VDI differential input sensitivity voltage (D+)  (D) 0.2 - - V VCM differential common mode voltage range includes VDI range 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed RL of 1.5 k to 3.6 V - - 0.18 V VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND ZDRV driver output with 33  series resistor; impedance for driver steady state drive which is not high-speed capable [19] - - 20 pF 36 - 44.1  [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. [3] Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure the same ramp-up time for both supply voltages. [4] VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb = 25 C. [5] PLL1 disabled; IRC running; CCLK = 12 MHz. [6] VBAT = 3.6 V. [7] Tamb = -40 °C to +105 °C; VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 204 MHz; in active mode, sleep mode; deep-sleep mode, power-down mode, and deep power-down mode. [8] On pin VBAT; Tamb = 25 C. [9] Vps corresponds to the output of the power switch (see Figure 9) which is determined by the greater of VBAT and VDD(Reg)(3V3). [10] VDDA(3V3) = 3.3 V; Tamb = 25 C. [11] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [12] To VSS. [13] The values specified are simulated and absolute values. [14] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level. [15] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO). [16] The parameter value specified is a simulated value excluding bond capacitance. [17] For USB operation 3.0 V  VDD((IO)  3.6 V. Guaranteed by design. [18] VDD(IO) present. [19] Includes external resistors of 33   1 % on D+ and D. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 97 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.1 Power consumption 002aah445 100 IDDREG(3V3) IDDREG(3V3) (mA) 80 204 MHz 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 2.2 2.4 2.6 2.8 3 3.2 3.4 VDD(REG)(3V3) (V) 3.6 Conditions: Tamb = 25 C; executing code while (1){} from SRAM; M0 core in reset; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 11. Typical supply current versus regulator supply voltage VDD(REEG)(3V3) in active mode 002aah446 100 IDDREG(3V3) IDDREG(3V3) (mA) (mA) 80 204 MHz 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 -40 -20 0 20 40 60 80 100 temperature (°C) 120 Conditions: VDD(REG)(3V3) = 3.2 V; executing code while (1){} from SRAM; M0 core in reset; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 12. Typical supply current versus temperature in active mode LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 98 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah447 100 IDDREG(3V3) IDDREG(3V3) (mA) (mA) +105 °C C +90 °C C +25 °C C +0°C C 0 -40 °C C 80 60 40 20 0 12 60 108 156 frequency (MHz) 204 Conditions: active mode entered executing code while (1){} from SRAM; M0 core in reset; VDD(REG)(3V3) = 3.2 V; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 13. Typical supply current versus core frequency in active mode; code executed from SRAM 002aah386 20 IDD(REG)(3V3) ( (mA) 16 12 8 4 0 -40 -20 0 20 40 60 80 100 temperature (°C) 120 Conditions: VDD(REG)(3V3) = 3.0 V; internal pull-up resistors disabled; M0 core in reset; system PLL disabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. CCLK = 12 MHz. Fig 14. Typical supply current versus temperature in sleep mode LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 99 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah410 1.6 IDD(REG)(3V3) (μA) (mA) 002aah412 300 IDD(REG)(3V3) (μA)(μA) 240 1.2 180 0.8 120 0.4 60 0 -40 0 40 80 temperature (°C) 0 -40 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. 40 80 temperature (°C) 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 15. Typical supply current versus temperature in Deep-sleep mode Fig 16. Typical supply current versus temperature in Power-down mode 002aah424 25 IDD(REG)(3V3)/IBAT (μA) 0 002aah415 30 IBAT IBAT (μA) 25 20 20 15 15 10 IIBAT BAT IDD(REG)(3V3) 10 5 0 -40 5 -20 0 20 40 60 80 100 temperature (°C) 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. VBAT = VDD(REG)(3V3) + 0.4 V. Fig 17. Typical supply current versus temperature in Deep power-down mode LPC435X_3X_2X_1X Preliminary data sheet 0 -40 -20 0 20 40 60 80 100 temperature (°C) 120 Conditions: VBAT = 3.6 V. VDD(REG)(3V3) not present. Fig 18. Typical battery supply current versus temperature All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 100 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah379 100 IBAT (μA) 80 60 40 20 0 -0.4 -0.2 0 0.2 0.4 VBAT - VDD(REG)(3V3) (V) 0.6 Conditions: VDD(REG)(3V3) = 3.0 V; VBAT = 2.6 V to 3.6 V; CCLK = 12 MHz. Remark: The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. Fig 19. Typical battery supply current in Active mode 10.2 Peripheral power consumption The typical power consumption at T = 25 C for each individual peripheral is measured as follows: 1. Enable all branch clocks and measure the current IDD(REG)(3V3). 2. Disable the branch clock to the peripheral to be measured and keep all other branch clocks enabled. 3. Calculate the difference between measurement 1 and 2. The result is the peripheral power consumption. Table 12. Peripheral power consumption Peripheral LPC435X_3X_2X_1X Preliminary data sheet Branch clock IDD(REG)(3V3) in mA Branch clock frequency = 48 MHz Branch clock frequency = 96 MHz M0 core CLK_M4_M0APP 3.3 6.6 I2C1 CLK_APB3_I2C1 0.01 0.01 I2C0 CLK_APB1_I2C0 < 0.01 0.02 DAC CLK_APB3_DAC 0.01 0.02 ADC0 CLK_APB3_ADC0 0.07 0.07 ADC1 CLK_APB3_ADC1 0.07 0.07 CAN0 CLK_APB3_CAN0 0.17 0.17 CAN1 CLK_APB1_CAN1 0.16 0.15 MOTOCON CLK_APB1_MOTOCON 0.04 0.04 I2S CLK_APB1_I2S 0.09 0.08 SPIFI CLK_SPIFI, CLK_M4_SPIFI 1.14 2.29 All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 101 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 12. Peripheral power consumption Peripheral LPC435X_3X_2X_1X Preliminary data sheet Branch clock IDD(REG)(3V3) in mA Branch clock frequency = 48 MHz Branch clock frequency = 96 MHz GPIO CLK_M4_GPIO 0.72 1.43 LCD CLK_M4_LCD 0.91 1.82 ETHERNET CLK_M4_ETHERNET 1.06 2.15 UART0 CLK_M4_UART0, CLK_APB0_UART0 0.24 0.43 UART1 CLK_M4_UART1, CLK_APB0_UART1 0.24 0.43 UART2 CLK_M4_UART2, CLK_APB2_UART2 0.26 0.5 UART3 CLK_M4_USART3, CLK_APB2_UART3 0.27 0.45 TIMER0 CLK_M4_TIMER0 0.08 0.15 TIMER1 CLK_M4_TIMER1 0.09 0.15 TIMER2 CLK_M4_TIMER2 0.1 0.19 TIMER3 CLK_M4_TIMER3 0.08 0.16 SDIO CLK_M4_SDIO, CLK_SDIO 0.66 1.17 SCT CLK_M4_SCT 0.66 1.3 SSP0 CLK_M4_SSP0, CLK_APB0_SSP0 0.13 0.23 SSP1 CLK_M4_SSP1, CLK_APB2_SSP1 0.14 0.27 DMA CLK_M4_DMA 1.81 3.61 WWDT CLK_M4_WWDT 0.03 0.09 QEI CLK_M4_QEI 0.28 0.55 USB0 CLK_M4_USB0, CLK_USB0 1.9 3.9 USB1 CLK_M4_USB1, CLK_USB1 3.02 5.69 RITIMER CLK_M4_RITIMER 0.05 0.1 EMC CLK_M4_EMC, CLK_M4_EMC_DIV 3.94 7.95 SCU CLK_M4_SCU 0.1 0.21 CREG CLK_M4_CREG 0.35 0.7 Flash bank A CLK_M4_FLASHA 1.47 2.97 Flash bank B CLK_M4_FLASHB 1.4 2.84 SGPIO CLK_PERIPH_SGPIO SPI CLK_SPI All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 102 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.3 Electrical pin characteristics 002aah368 3.6 VOH (V) 002aah359 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.2 2.8 3.2 -40 °C +25 °C +85 °C +105 °C 2.8 2.4 2.4 2 2 0 16 32 48 64 80 IOH (mA) 96 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Preliminary data sheet 6 12 18 24 30 IOH (mA) 36 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 20. Standard I/O pins; typical LOW level output current IOL versus LOW level output voltage VOL LPC435X_3X_2X_1X 0 Fig 21. Standard I/O pins; typical HIGH level output voltage VOL versus HIGH level output current IOH All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 103 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah360 15 -40 °C +25 °C +85 °C +105 °C IOL (mA) 12 002aah361 25 -40 °C +25 °C +85 °C +105 °C IOL (mA) 20 9 15 6 10 3 5 0 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 0 -40 °C +25 °C +85 °C +105 °C 32 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah362 40 IOL (mA) 0.1 002aah363 60 -40 °C +25 °C +85 °C +105 °C IOL (mA) 45 24 30 16 15 8 0 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive; EHD = 0x2. 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra high-drive; EHD = 0x3. Fig 22. High-drive pins; typical LOW level output current IOL versus LOW level output voltage VOL LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 104 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah364 3.6 VOH (V) 002aah367 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.2 2.8 -40 °C +25 °C +85 °C +105 °C 3.2 2.8 2.4 2.4 2 2 0 4 8 12 16 20 IOH (mA) 24 0 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 16 24 32 40 IOH (mA) 48 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah368 3.6 VOH (V) 8 002aah369 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.2 2.8 -40 °C +25 °C +85 °C +105 °C 3.2 2.8 2.4 2.4 2 2 0 16 32 48 64 80 IOH (mA) 96 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive; EHD = 0x2. 0 20 40 60 80 100 IOH (mA) 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra high-drive; EHD = 0x3. Fig 23. High-drive pins; typical HIGH level output voltage VOH versus HGH level output current IOH LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 105 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah422 20 IIpu pu (μA) 0 +105 °C C +25 °C C -40 °C C -20 -40 -60 -80 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature. Fig 24. Pull-up current Ipu versus input voltage VI 002aah418 120 IIpd pd (μA) -40 °C C +25 °C C +105 °C C 90 60 30 0 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature. Fig 25. Pull-down current Ipd versus input voltage VI LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 106 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.4 BOD and band gap static characteristics Table 13. BOD static characteristics[1] Tamb = 25 C; simulated values for nominal processing. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion - 2.25 - V de-assertion - 2.33 - V assertion - 2.35 - V de-assertion - 2.43 - V assertion - 2.95 - V de-assertion - 3.03 - V assertion - 3.05 - V de-assertion - 3.13 - V interrupt level 1 interrupt level 2 interrupt level 3 reset level 0 assertion - 1.9 - V de-assertion - 1.98 - V assertion - 2.0 - V de-assertion - 2.08 - V assertion - 2.1 - V de-assertion - 2.18 - V assertion - 2.2 - V de-assertion - 2.28 - V reset level 1 reset level 2 reset level 3 [1] Interrupt and reset levels are selected by writing to the BODLV1/2 bits in the control register CREGE0, see the LPC43xx user manual. Table 14. Band gap characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified Symbol Vref(bg) [1] Parameter Conditions Min Typ Max Unit Tamb = 40 C to +105 C [1] band gap reference voltage - 673  2 % - mV Tamb = 0 C to +90 C [1] - 673  1.6 % - mV Characterized for typical samples. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 107 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11. Dynamic characteristics 11.1 Flash/EEPROM memory Table 15. Flash characteristics Tamb = 40 C to +105 C, unless otherwise specified. VDD(REG)(3V3) = 2,2 V to 3.6 V for read operations; VDD(REG)(3V3) = 2.7 V to 3.6 V for erase/program operations. Symbol Parameter Conditions Nendu endurance sector erase/program retention time tret ter erase time tprog programming time Min Typ Max Unit 10000 - - cycles page erase/program; page in large sector 1000 - - cycles page erase/program; page in small sector 10000 - - cycles powered 10 - - years unpowered 10 - - years page, sector, or multiple consecutive sectors - 50 - ms - 1 - ms [1] [2] [1] Number of erase/program cycles. [2] Programming times are given for writing 512 bytes from RAM to the flash. Data must be written to the flash in blocks of 512 bytes. Table 16. EEPROM characteristics Tamb = 40 C to +105 C; VDD(REG)(3V3) = 2.7 V to 3.6 V. Symbol Parameter Typ Max Unit 800 1500 1600 kHz clock frequency Nendu endurance 100 000 - - cycles tret retention time - 20 - years ta access time read - 120 - ns erase/program; fclk = 1500 kHz - 1.99 - ms erase/program; fclk = 1600 kHz - 1.87 - ms [1] Preliminary data sheet Min fclk twait LPC435X_3X_2X_1X Conditions wait time read; RPHASE1 [1] 35 - - ns read; RPHASE2 [1] 70 - - ns write; PHASE1 [1] 20 - - ns write; PHASE2 [1] 40 - - ns write; PHASE3 [1] 10 - - ns See the LPC43xx user manual how to program the wait states for the different read (RPHASEx) and erase/program phases (PHASEx) All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 108 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.2 Wake-up times Table 17. Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep power-down modes Tamb = 40 C to +105 C Symbol Parameter twake Conditions Typ[1] Min Max Unit - 5  Tcy(clk) - ns from Deep-sleep and Power-down mode 12 51 - s from Deep power-down mode - 200 - μs after reset - 200 - μs [2] wake-up time from Sleep mode [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Tcy(clk) = 1/CCLK with CCLK = CPU clock frequency. 11.3 External clock for oscillator in slave mode Remark: The input voltage on the XTAL1/2 pins must be  1.2 V (see Table 11). For connecting the oscillator to the XTAL pins, also see Section 13.2 and Section 13.4. Table 18. Dynamic characteristic: external clock Tamb = 40 C to +105 C; VDD(IO) over specified ranges.[1] Symbol Parameter Conditions Min Max Unit fosc oscillator frequency 1 25 MHz Tcy(clk) clock cycle time 40 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 Tcy(clk)  0.6 ns tCLCX clock LOW time Tcy(clk)  0.4 Tcy(clk)  0.6 ns [1] Parameters are valid over operating temperature range unless otherwise specified. tCHCX tCLCX Tcy(clk) 002aag698 Fig 26. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 109 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.4 Crystal oscillator Table 19. Dynamic characteristic: oscillator Tamb = 40 C to +105 C; VDD(IO) over specified ranges; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Low-frequency mode (1-20 tjit(per) Conditions Typ[2] Max Unit MHz)[5] period jitter time High-frequency mode (20 - 25 tjit(per) Min 5 MHz crystal [3][4] - 13.2 - ps 10 MHz crystal - 6.6 - ps 15 MHz crystal - 4.8 - ps - 4.3 - ps - 3.7 - ps MHz)[6] period jitter time 20 MHz crystal [3][4] 25 MHz crystal [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [3] Indicates RMS period jitter. [4] PLL-induced jitter is not included. [5] Select HF = 0 in the XTAL_OSC_CTRL register. [6] Select HF = 1 in the XTAL_OSC_CTRL register. 11.5 IRC oscillator Table 20. Dynamic characteristic: IRC oscillator 2.2 V  VDD(REG)(3V3)  3.6 V Symbol Parameter Conditions Min Typ[1] Max Unit fosc(RC) internal RC oscillator frequency -40 C  Tamb  0 C 11.76 12.0 12.24 MHz 0 C  Tamb  85 C 11.88 12.0 12.12 MHz 85 C  Tamb  105 C 11.76 12.0 12.24 MHz [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.6 RTC oscillator See Section 13.3 for connecting the RTC oscillator to an external clock source. Table 21. Dynamic characteristic: RTC oscillator Tamb = 40 C to +105 C; 2.2 V  VDD(REG)(3V3)  3.6 V or 2.2 V  VBAT  3.6 V[1] LPC435X_3X_2X_1X Preliminary data sheet Symbol Parameter Conditions Min Typ[1] Max Unit fi input frequency - - 32.768 - kHz ICC(osc) oscillator supply current 280 800 nA [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 110 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.7 I2C-bus Table 22. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +105 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [3][4][5][6] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Standard-mode tLOW tHIGH tHD;DAT tSU;DAT LOW period of the SCL clock HIGH period of the SCL clock [2][3][7] data hold time [8][9] data set-up time Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns [1] Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details. [2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed. [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [7] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [9] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 111 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 27. I2C-bus pins clock timing 11.8 I2S-bus interface Table 23. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data refer to I2S0 and I2S1 pins. Simulated values. Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time - 4 - ns tf fall time - 4 - ns tWH pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK 36 - - ns tWL pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK 36 - - ns - 4.4 - ns - 4.3 - ns 0 - output data output valid time on pin I2Sx_TX_SDA tv(Q) [1] on pin I2Sx_TX_WS input tsu(D) data input set-up time on pin I2Sx_RX_SDA [1] - on pin I2Sx_RX_WS th(D) data input hold time on pin I2Sx_RX_SDA on pin I2Sx_RX_WS [1] LPC435X_3X_2X_1X Preliminary data sheet 0.20 [1] ns ns - 3.7 - ns - 3.9 - ns Clock to the I2S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I2S-bus interface PCLK = BASE_APB1_CLK / 12. I2S clock cycle time Tcy(clk) = 79.2 ns, corresponds to the SCK signal in the I2S-bus specification. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 112 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) tf tr I2Sx_TX_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_TX_WS 002aag497 tv(Q) Fig 28. I2S-bus timing (transmit) Tcy(clk) tf tr I2Sx_RX_SCK tWH tWL I2Sx_RX_SDA tsu(D) th(D) I2Sx_RX_WS tsu(D) 002aag498 tsu(D) Fig 29. I2S-bus timing (receive) 11.9 USART interface Table 24. Dynamic characteristics: USART interface Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values. Symbol Parameter Conditions Min Typ Max Unit Tcy(clk) clock cycle time on pins Ux_UCLK - 0.1 - s data output valid time on pin Ux_TXD - 6.5 - ns output tv(Q) LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 113 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.10 SSP interface Table 25. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values. Symbol Tcy(clk) Parameter clock cycle time Conditions Min Typ Max Unit - 40 - ns when only transmitting - 20 - ns in SPI mode 13.3 - - ns full-duplex mode [1] SSP master tDS data set-up time tDH data hold time in SPI mode 3.5 - - ns tv(Q) data output valid time in SPI mode - - 6.0 ns th(Q) data output hold time in SPI mode - - 0 ns 120 - - ns SSP slave Tcy(PCLK) PCLK cycle time Tcy(clk) clock cycle time 10 tDS data set-up time in SPI mode - 10.5 - ns tDH data hold time in SPI mode - 1 - ns tv(Q) data output valid time in SPI mode - 4.0 - ns th(Q) data output hold time in SPI mode - 0.2 - ns [2] ns [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). [2] Tcy(clk) = 12  Tcy(PCLK). LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 114 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 30. SSP master timing in SPI mode LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 115 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) tclk(H) tclk(L) tDS tDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 31. SSP slave timing in SPI mode LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 116 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.11 External memory interface Table 26. Dynamic characteristics: Static external memory interface CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Symbol Parameter[1] Conditions Min Typ Max Unit 3.1 - 1.6 ns 0.6 + Tcy(clk)  WAITOEN - 1.3 + Tcy(clk)  WAITOEN ns 0.7 - 1.8 ns Read cycle parameters tCSLAV CS LOW to address valid time tCSLOEL CS LOW to OE LOW time tCSLBLSL CS LOW to BLS LOW time [2] PB = 1 0.6 + (WAITRD  WAITOEN + 1)  Tcy(clk) 0.4 + ns (WAITRD  WAITOEN + 1)  Tcy(clk) memory access time - - 16 + (WAITRD  WAITOEN +1)  Tcy(clk) ns th(D) data input hold time 16 - - ns tCSHBLSH CS HIGH to BLS HIGH time PB = 1 0.4 - 1.9 ns tCSHOEH CS HIGH to OE HIGH time 0.4 - 1.4 ns tOEHANV OE HIGH to address invalid PB = 1 2.0 - 2.6 ns tCSHEOR CS HIGH to end of read time [3] 2.0 - 0 ns tCSLSOR CS LOW to start of read time [4] 0 - 1.8 ns tOELOEH OE LOW to OE HIGH time tam [2] Write cycle parameters tCSLAV CS LOW to address valid time 3.1 - 1.6 ns tCSLDV CS LOW to data valid time 3.1 - 1.5 ns tCSLWEL CS LOW to WE LOW time PB = 1 1.5 - 0.2 ns tCSLBLSL CS LOW to BLS LOW time PB = 1 0.7 - 1.8 ns 0.6 + (WAITWR  WAITWEN + 1)  Tcy(clk) 0.4 + ns (WAITWR  WAITWEN + 1)  Tcy(clk) tWELWEH WE LOW to WE HIGH time PB = 1 [2] tWEHDNV WE HIGH to data invalid time PB = 1 [2] 0.9 + Tcy(clk) - 2.3 + Tcy(clk) ns tWEHEOW WE HIGH to end of write time PB = 1 [2] 0.4 + Tcy(clk) - 0.3 + Tcy(clk) ns tCSLBLSL CS LOW to BLS LOW PB = 0 0.7 - 1.8 ns tBLSLBLSH BLS LOW to BLS HIGH time PB = 0 [2] 0.9 + (WAITWR  WAITWEN + 1)  Tcy(clk) 0.1 + ns (WAITWR  WAITWEN + 1)  Tcy(clk) tBLSHEOW BLS HIGH to end of write time [2] 1.9 + Tcy(clk) 0.5 + Tcy(clk) LPC435X_3X_2X_1X Preliminary data sheet [5] PB = 0 - ns [5] All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 117 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 26. Dynamic characteristics: Static external memory interface …continued CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Symbol Parameter[1] Conditions tBLSHDNV BLS HIGH to data invalid time PB = 0 tCSHEOW CS HIGH to end of write time tBLSHDNV BLS HIGH to data invalid time tWEHANV WE HIGH to address invalid PB = 1 time PB = 1 Min Typ Max Unit [2] 2.5 + Tcy(clk) - 1.4 + Tcy(clk) ns [5] 2.0 - 0 ns 2.5 - 1.4 ns 0.9 + Tcy(clk) - 2.4 + Tcy(clk) ns [1] Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges. [2] Tcy(clk) = 1/CCLK (see LPC43xx User manual). [3] End Of Read (EOR): longest of tCSHOEH, tOEHANV, tCSHBLSH. [4] Start Of Read (SOR): longest of tCSLAV, tCSLOEL, tCSLBLSL. [5] End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH. EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSHOEH tBLSHEOW tCSLBLSL tBLSLBLSH EMC_BLSn EMC_WE tCSLDV tam tCSHEOR tCSLSOR tBLSHDNV th(D) EMC_Dn SOR EOR EOW 002aag699 Fig 32. External static memory read/write access (PB = 0) LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 118 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSLBLSL tCSHOEH tCSLBLSL EMC_BLSn tCSHBLSH tCSLWEL tWELWEH tWEHEOW EMC_WE tBLSHDNV tam tCSHEOR th(D) tCSLSOR tCSLDV tWEHDNV EMC_Dn SOR EOR EOW 002aag700 Fig 33. External static memory read/write access (PB = 1) LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 119 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 27. Dynamic characteristics: Dynamic external memory interface Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; VDD(IO) =3.3 V  10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0. Symbol Parameter Min Typ Max Unit Tcy(clk) clock cycle time 8.4 - - ns 3.1 + 0.5  Tcy(clk) 5.1 + 0.5  Tcy(clk) ns - ns 4.9 + 0.5  Tcy(clk) ns Common to read and write cycles td(DYCSV) dynamic chip select valid delay time - th(DYCS) dynamic chip select hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) td(RASV) row address strobe valid delay time - th(RAS) row address strobe hold time 0.5 + 0.5  Tcy(clk) 1.1 + 0.5  Tcy(clk) td(CASV) column address strobe valid delay time - th(CAS) column address strobe hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) td(WEV) write enable valid delay time - th(WE) write enable hold time 1.3 + 0.5  Tcy(clk) 1.4 + 0.5  Tcy(clk) td(DQMOUTV) DQMOUT valid delay time - th(DQMOUT) DQMOUT hold time 0.2 + 0.5  Tcy(clk) 0.8 + 0.5  Tcy(clk) td(AV) address valid delay time - th(A) address hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) - ns td(CKEOUTV) CKEOUT valid delay time - 3.1 + 0.5  Tcy(clk) 5.1 + 0.5  Tcy(clk) ns th(CKEOUT) CKEOUT hold time 0.5  Tcy(clk) 0.7 + 0.5  Tcy(clk) - ns 3.1 + 0.5  Tcy(clk) 2.9 + 0.5  Tcy(clk) 3.2 + 0.5  Tcy(clk) 3.1 + 0.5  Tcy(clk) 3.8 + 0.5  Tcy(clk) - ns 4.6 + 0.5  Tcy(clk) ns - ns 5.9 + 0.5  Tcy(clk) ns - ns 5.0 + 0.5  Tcy(clk) ns - ns 6.3 + 0.5  Tcy(clk) ns Read cycle parameters tsu(D) data input set-up time 1.5 0.5 - ns th(D) data input hold time - 0.8 2.2 ns Write cycle parameters td(QV) data output valid delay time - 3.8 + 0.5  Tcy(clk) 6.2 + 0.5  Tcy(clk) ns th(Q) data output hold time 0.5  Tcy(clk) 0.7 + 0.5  Tcy(clk) - ns Table 28. Dynamic characteristics: Dynamic external memory interface; EMC_CLK[3:0] delay values Tamb = 40 C to 105 C; VDD(IO) =3.3 V  10 %; 2.2 V  VDD(REG)(3V3)  3.6 V. Symbol Parameter Conditions td delay time delay value CLKn_DELAY = 0 [1] LPC435X_3X_2X_1X Preliminary data sheet Min Typ Max Unit [1] 0.0 0.0 0.0 ns CLKn_DELAY = 1 [1] 0.4 0.5 0.8 ns CLKn_DELAY = 2 [1] 0.7 1.0 1.7 ns CLKn_DELAY = 3 [1] 1.1 1.6 2.5 ns CLKn_DELAY = 4 [1] 1.4 2.0 3.3 ns CLKn_DELAY = 5 [1] 1.7 2.6 4.1 ns CLKn_DELAY = 6 [1] 2.1 3.1 4.9 ns CLKn_DELAY = 7 [1] 2.5 3.6 5.8 ns Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC43xx User manual). The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 120 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_CLKn delay > 0 EMC_CLKn delay td; programmable CLKn_DELAY Tcy(clk) EMC_CLKn delay = 0 td(xV) - td EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) - td th(x) td(QV) - td td(QV) th(Q) - td th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read; delay > 0 tsu(D) th(D) EMC_D[31:0] read; delay = 0 002aag703 For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 28 . Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK register. Fig 34. SDRAM timing LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 121 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.12 USB interface Table 29. Dynamic characteristics: USB0 and USB1 pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO), unless otherwise specified; 3.0 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 35 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 35 2 - +5 ns tJR1 receiver jitter to next transition 18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns tEOPR1 EOP width at receiver must reject as EOP; see Figure 35 [1] 40 - - ns tEOPR2 EOP width at receiver must accept as EOP; see Figure 35 [1] 82 - - ns [1] Characterized but not implemented as production test. Guaranteed by design. TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 35. Differential data-to-EOP transition skew and EOP width LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 122 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Static characteristics: USB0 PHY pins[1] Table 30. Symbol Parameter Conditions Min Typ Max Unit - 68 - mW - 18 - mA High-speed mode Pcons [2] power consumption IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER; [3] total supply current IDDD during transmit - 31 - mA during receive - 14 - mA with driver tri-stated - 14 - mA - 7 - mA - 15 - mW digital supply current Full-speed/low-speed mode Pcons IDDA(3V3) analog supply current (3.3 V) IDDD [2] power consumption on pin USB0_VDDA3V3_DRIVER; total supply current - 3.5 - mA during transmit - 5 - mA during receive - 3 - mA with driver tri-stated - 3 - mA - 3 - mA - 24 - A with driver tri-stated - 24 - A with OTG functionality enabled - 3 - mA - 30 - A for VBUS valid 4.4 - - V for session end 0.2 - 0.8 V for A valid 0.8 - 2 V for B valid 2 - 4 V for session end - 150 10 mV A valid - 200 10 mV B valid - 200 10 mV digital supply current Suspend mode IDDA(3V3) analog supply current (3.3 V) IDDD digital supply current VBUS detector outputs Vth threshold voltage Vhys [1] hysteresis voltage Characterized but not implemented as production test. [2] Total average power consumption. [3] The driver is active only 20 % of the time. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 123 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.13 Ethernet Table 31. Dynamic characteristics: Ethernet Tamb = 40 C to 105 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit [1] - 50 MHz clock duty cycle [1] 50 50 % tsu set-up time for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 4 - ns th hold time for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 2 - ns clock frequency for ENET_TX_CLK [1] - 25 MHz clock duty cycle [1] 50 50 % tsu set-up time for ENET_TXDn, ENET_TX_EN, ENET_TX_ER [1][2] 4 - ns th hold time for ENET_TXDn, ENET_TX_EN, ENET_TX_ER [1][2] 2 - ns fclk clock frequency for ENET_RX_CLK [1] - 25 MHz clk clock duty cycle [1] 50 50 % tsu set-up time for ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 4 - ns th hold time for ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 2 - ns RMII mode clock frequency fclk clk for ENET_RX_CLK MII mode fclk clk [1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input capacitance of the receiving device. [2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or output level. ENET_RX_CLK ENET_TX_CLK ENET_RXD[n] ENET_RX_DV ENET_RX_ER ENET_TXD[n] ENET_TX_EN ENET_TX_ER tsu th 002aag210 Fig 36. Ethernet timing LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 124 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.14 SD/MMC Table 32. Dynamic characteristics: SD/MMC Tamb = 40 C to 105 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V, CL = 20 pF. Simulated values. Symbol Parameter Conditions Min Max Unit fclk clock frequency on pin SD_CLK; data transfer mode 40 - MHz tsu(D) data input set-up time on pins SD_CMD, SD_DATn as inputs 16 - ns th(D) data input hold time on pins SD_CMD, SD_DATn as inputs 2 - ns td(QV) data output valid delay time on pins SD_CMD, SD_DATn as outputs - 12 ns th(Q) data output hold time on pins SD_CMD, SD_DATn as outputs 0.3 - ns Tcy(clk) SD_CLK td(QV) th(Q) SD_CMD (O) SD_DATn (O) tsu(D) th(D) SD_CMD (I) SD_DATn (I) 002aag204 Fig 37. SD/MMC timing 11.15 LCD Table 33. Dynamic characteristics: LCD Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values. Symbol Parameter LPC435X_3X_2X_1X Preliminary data sheet Conditions Min Typ Max Unit on pin LCD_DCLK - 50 - MHz fclk clock frequency td(QV) data output valid delay time - - 17 ns th(Q) data output hold time 8.5 - - ns All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 125 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.16 SPIFI Table 34. Dynamic characteristics: SPIFI Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. CL = 10 pF. Simulated values. Symbol Parameter Min Max Unit Tcy(clk) clock cycle time 9.6 - ns tDS data set-up time 3.4 - ns tDH data hold time  - ns tv(Q) data output valid time - 8 ns th(Q) data output hold time 5 - ns Tcy(clk) tclk(H) tclk(L) SPIFI_SCK tv(Q) SPIFI data out DATA VALID th(Q) DATA VALID tDS SPIFI data in DATA VALID tDH DATA VALID 002aah409 Fig 38. SPIFI timing LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 126 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 12. ADC/DAC electrical characteristics Table 35. ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA(3V3) V Cia analog input capacitance - - 2 pF ED differential linearity error - 0.8 - LSB - 1.0 - LSB - 0.8 - LSB - 1.5 - LSB - 0.15 - LSB - 0.15 - LSB - 0.3 - % - 0.35 - % - 3 - LSB 2.2 V  VDDA(3V3) < 2.7 V - 4 - LSB see Figure 40 - - 1/(7  fclk(ADC)  Cia) k - - 1.2 M - - 4.5 MHz - - 400 kSamples/s 1.5 MSamples/s 2.7 V  VDDA(3V3)  3.6 V [1][2] 2.2 V  VDDA(3V3) < 2.7 V EL(adj) integral non-linearity 2.7 V  VDDA(3V3)  3.6 V [3] 2.2 V  VDDA(3V3) < 2.7 V offset error EO 2.7 V  VDDA(3V3)  3.6 V [4] 2.2 V  VDDA(3V3) < 2.7 V gain error EG 2.7 V  VDDA(3V3)  3.6 V [5] 2.2 V  VDDA(3V3) < 2.7 V absolute error ET Rvsi voltage source interface resistance Ri input resistance fclk(ADC) ADC clock frequency fs sampling frequency 2.7 V  VDDA(3V3)  3.6 V [6] [7][8] 10-bit resolution; 11 clock cycles 2-bit resolution; 3 clock cycles [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 39. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 39. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 39. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 39. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 39. [7] Tamb = 25 C. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 2 k + 1 / (fs  Cia). LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 127 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA(3V3) − VSSA 1024 002aaf959 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 39. 10-bit ADC characteristics LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 128 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Rvsi LPC43xx 2 kΩ (analog pin) 2.2 kΩ (multiplexed pin) ADC0_n/ADC1_n Rs ADC COMPARATOR Cia = 2 pF VEXT VSS 002aah084 Rs < 1/((7  fclk(ADC)  Cia)  2 k Fig 40. ADC interface to pins Table 36. DAC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified Symbol Parameter Conditions ED differential linearity error 2.7 V  VDDA(3V3)  3.6 V [1] 2.2 V  VDDA(3V3) < 2.7 V EL(adj) integral non-linearity code = 0 to 975 [1] Min Typ Max Unit - 0.8 - LSB - 1.0 - LSB - 1.0 - LSB 2.7 V  VDDA(3V3)  3.6 V 2.2 V  VDDA(3V3) < 2.7 V EO offset error 2.7 V  VDDA(3V3)  3.6 V EG gain error 2.7 V  VDDA(3V3)  3.6 V - 1.5 - LSB [1] - 0.8 - LSB - 1.0 - LSB [1] - 0.3 - % - 1.0 - % - - 200 pF 1 - - k 2.2 V  VDDA(3V3) < 2.7 V 2.2 V  VDDA(3V3) < 2.7 V CL load capacitance RL load resistance ts settling time [1] [1] In the DAC CR register, bit BIAS = 0 (see the LPC43xx user manual). [2] Settling time is calculated within 1/2 LSB of the final value. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 0.4 s © NXP B.V. 2012. All rights reserved. 129 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13. Application information 13.1 LCD panel signal usage Table 37. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin used LCD function LCD_VD[23:8] - - - - - - LCD_VD7 - - P8_4 UD[7] P8_4 UD[7] LCD_VD6 - - P8_5 UD[6] P8_5 UD[6] LCD_VD5 - - P8_6 UD[5] P8_6 UD[5] LCD_VD4 - - P8_7 UD[4] P8_7 UD[4] LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3] LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2] LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1] LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0] LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP LCD_ENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE LCD_PWR P7_7 CDPWR P7_7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN Table 38. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin used LCD function LCD_VD[23:16] - - - - - - LCD_VD15 - - PB_4 LD[7] PB_4 LD[7] LCD_VD14 - - PB_5 LD[6] PB_5 LD[6] LCD_VD13 - - PB_6 LD[5] PB_6 LD[5] LCD_VD12 - - P8_3 LD[4] P8_3 LD[4] LCD_VD11 P4_9 LD[3] P4_9 LD[3] P4_9 LD[3] LCD_VD10 P4_10 LD[2] P4_10 LD[2] P4_10 LD[2] LCD_VD9 P4_8 LD[1] P4_8 LD[1] P4_8 LD[1] LCD_VD8 P7_5 LD[0] P7_5 LD[0] P7_5 LD[0] LCD_VD7 - - UD[7] P8_4 UD[7] LCD_VD6 - - P8_5 UD[6] P8_5 UD[6] LCD_VD5 - - P8_6 UD[5] P8_6 UD[5] LCD_VD4 - - P8_7 UD[4] P8_7 UD[4] LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3] LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 130 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 38. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin used LCD function LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2] LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1] LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0] LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP LCD_ENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN Table 39. External pin LCD panel connections for TFT panels TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin LCD used function LCD_VD23 PB_0 BLUE3 PB_0 BLUE4 PB_0 BLUE4 BLUE7 LCD_VD22 PB_1 BLUE2 PB_1 BLUE3 PB_1 BLUE3 BLUE6 LCD_VD21 PB_2 BLUE1 PB_2 BLUE2 PB_2 BLUE2 BLUE5 LCD_VD20 PB_3 BLUE0 PB_3 BLUE1 PB_3 BLUE1 BLUE4 LCD_VD19 - - P7_1 BLUE0 P7_1 BLUE0 BLUE3 LPC43xx pin used LCD function LCD_VD18 - - - - P7_2 intensity LCD_VD17 - - - - - - P7_3 BLUE1 LCD_VD16 - - - - - - P7_4 BLUE0 LCD_VD15 PB_4 GREEN3 PB_4 GREEN5 PB_4 GREEN4 PB_4 GREEN7 LCD_VD14 PB_5 GREEN2 PB_5 GREEN4 PB_5 GREEN3 PB_5 GREEN6 LCD_VD13 PB_6 GREEN1 PB_6 GREEN3 PB_6 GREEN2 PB_6 GREEN5 LCD_VD12 P8_3 GREEN0 P8_3 GREEN2 P8_3 GREEN1 P8_3 GREEN4 LCD_VD11 - P4_9 GREEN1 P4_9 GREEN0 P4_9 GREEN3 - BLUE2 LCD_VD10 - - P4_10 GREEN0 P4_10 intensity P4_10 GREEN2 LCD_VD9 - - - - - - P4_8 GREEN1 LCD_VD8 - - - - - - P7_5 GREEN0 LCD_VD7 P8_4 RED3 P8_4 RED4 P8_4 RED4 P8_4 RED7 LCD_VD6 P8_5 RED2 P8_5 RED3 P8_5 RED3 P8_5 RED6 LCD_VD5 P8_6 RED1 P8_6 RED2 P8_6 RED2 P8_6 RED5 LCD_VD4 P8_7 RED0 P8_7 RED1 P8_7 RED1 P8_7 RED4 LCD_VD3 - - P4_2 RED0 P4_2 RED0 P4_2 RED3 LCD_VD2 - - - - P4_3 intensity P4_3 RED2 LCD_VD1 - - - - - - P4_4 RED1 LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 131 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 39. External pin LCD panel connections for TFT panels TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC43xx pin used LPC43xx pin used LPC43xx pin LCD used function LCD function LCD function LPC43xx pin used LCD function LCD_VD0 - - - - - - P4_1 RED0 LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP LCDENAB/ LCDM P4_6 LCDENAB/ P4_6 LCDM LCD_ENAB P4_6 /LCDM LCDENAB/ P4_6 LCDM LCD_FP P4_5 LCDENAB/ LCDM LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN 13.2 Crystal oscillator The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see LPC43xx user manual). The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The oscillator can operate in one of two modes: slave mode and oscillation mode. • In slave mode, couple the input clock signal with a capacitor of 100 pF (CC in Figure 41), with an amplitude of at least 200 mV (RMS). The XTAL2 pin in this configuration can be left unconnected. • External components and models used in oscillation mode are shown in Figure 42, and in Table 40 and Table 41. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (L, CL and RS represent the fundamental frequency). Capacitance CP in Figure 42 represents the parallel package capacitance and must not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the crystal manufacturer. Table 40. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency 2 MHz 4 MHz 8 MHz LPC435X_3X_2X_1X Preliminary data sheet Maximum crystal series resistance RS External load capacitors CX1, CX2 < 200  33 pF, 33 pF < 200  39 pF, 39 pF < 200  56 pF, 56 pF < 200  18 pF, 18 pF < 200  39 pF, 39 pF < 200  56 pF, 56 pF < 200  18 pF, 18 pF < 200  39 pF, 39 pF All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 132 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 40. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency Maximum crystal series resistance RS External load capacitors CX1, CX2 12 MHz < 160  18 pF, 18 pF < 160  39 pF, 39 pF 16 MHz < 120  18 pF, 18 pF < 80  33 pF, 33 pF < 100  18 pF, 18 pF < 80  33 pF, 33 pF 20 MHz Table 41. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz < 80  18 pF, 18 pF 20 MHz < 80  39 pF, 39 pF < 100  47 pF, 47 pF LPC43xx XTAL1 Ci 100 pF Cg 002aag379 Fig 41. Slave mode operation of the on-chip oscillator LPC43xx L XTAL1 XTAL2 = CL CP XTAL RS CX1 CX2 002aag380 Fig 42. Oscillator modes with external crystal model used for CX1/CX2 evaluation LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 133 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13.3 RTC oscillator In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and CRTCX2 are CRTCX1/2 = 20 (typical)  4 pF. An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of 5 pF to 10 pF. LPC43xx RTCX1 RTCX2 XTAL CRTCX1 CRTCX2 002aah083 Fig 43. RTC 32 kHz oscillator circuit 13.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case of third overtone crystal usage have a common ground plane. Also connect the external components to the ground plain. To keep the noise coupled in via the PCB as small as possible, make loops and parasitics as small as possible. Choose smaller values of CX1 and CX2 if parasitics increase in the PCB layout. Ensure that no high-speed or high-drive signals are near the RTCX1/2 signals. 13.5 Standard I/O pin configuration Figure 44 shows the possible pin modes for standard I/O pins with analog input function: • • • • • • Digital output driver enabled/disabled Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Digital input: Input buffer enabled/disabled Analog input The default configuration for standard I/O pins is input buffer disabled and pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 134 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller VDDIO ESD enable output driver data output from core PIN slew rate bit EHS input buffer enable bit EZI data input to core glitch filter filter select bit ZIF pull-up enable bit EPUN ESD pull-down enable bit EPD analog I/O VSSIO 002aah028 The glitch filter rejects pulses of typical 12 ns width. Fig 44. Standard I/O pin configuration with analog input 13.5.1 Reset pin configuration VDD(IO) VDD(IO) VDD(IO) Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aag702 Fig 45. Reset pin configuration LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 135 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 14. Package outline LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm A B D SOT740-2 ball A1 index area A2 A E A1 detail X C e1 e y y1 C ∅v M C A B b 1/2 e ∅w M C T R e P N M L K J e2 H G 1/2 e F E D C B A ball A1 index area 1 3 2 5 4 7 6 9 8 11 10 13 12 15 14 16 X 5 0 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.55 0.45 0.35 1.1 0.9 0.55 0.45 17.2 16.8 17.2 16.8 1 15 15 0.25 0.1 0.12 0.35 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT740-2 --- MO-192 --- EUROPEAN PROJECTION ISSUE DATE 05-06-16 05-08-04 Fig 46. Package outline LBGA256 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 136 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM θ Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 28.1 27.9 0.5 HD HE 30.15 30.15 29.85 29.85 L Lp v w y ZD ZE θ 1 0.75 0.45 0.12 0.08 0.08 1.43 1.08 1.43 1.08 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT459-1 136E30 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-06 03-02-20 Fig 47. Package outline of the LQFP208 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 137 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm B D SOT926-1 A ball A1 index area A2 E A A1 detail X e1 e ∅v ∅w b 1/2 e C M M C A B C y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 0.8 7.2 7.2 0.15 0.05 0.08 0.1 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT926-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 05-12-09 05-12-22 Fig 48. Package outline of the TFBGA100 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 138 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.5 HD HE 22.15 22.15 21.85 21.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT486-1 136E23 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-14 03-02-20 Fig 49. Package outline for the LQFP144 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 139 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 15. Soldering Footprint information for reflow soldering of LBGA256 package SOT740-2 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 1.00 0.450 0.450 0.600 Hx Hy 17.500 17.500 sot740-2_fr Fig 50. Reflow soldering of the LBGA256 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 140 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 31.300 31.300 28.300 28.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 28.500 28.500 31.550 31.550 sot459-1_fr Fig 51. Reflow soldering of the LQFP208 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 141 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 23.300 23.300 20.300 20.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 20.500 20.500 23.550 23.550 sot486-1_fr Fig 52. Reflow soldering of the LQFP144 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 142 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926-1 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.80 0.330 0.400 0.480 9.400 9.400 sot926-1_fr Fig 53. Reflow soldering of the TFBGA100 package LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 143 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 16. Abbreviations Table 42. LPC435X_3X_2X_1X Preliminary data sheet Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus API Application Programming Interface BOD BrownOut Detection CAN Controller Area Network CMAC Cipher-based Message Authentication Code CSMA/CD Carrier Sense Multiple Access with Collision Detection DAC Digital-to-Analog Converter DC-DC Direct Current-to-Direct Current DMA Direct Memory Access GPIO General Purpose Input/Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group LCD Liquid Crystal Display LSB Least Significant Bit MAC Media Access Control MCU MicroController Unit MIIM Media Independent Interface Management n.c. not connected OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLL Phase-Locked Loop PMC Power Mode Control PWM Pulse Width Modulator RIT Repetitive Interrupt Timer RMII Reduced Media Independent Interface SDRAM Synchronous Dynamic Random Access Memory SIMD Single Instruction Multiple Data SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TCP/IP Transmission Control Protocol/Internet Protocol TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter ULPI UTMI+ Low Pin Interface All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 144 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 42. Abbreviations …continued Acronym Description USART Universal Synchronous Asynchronous Receiver/Transmitter USB Universal Serial Bus UTMI USB2.0 Transceiver Macrocell Interface 17. References [1] LPC435X_3X_2X_1X Preliminary data sheet ES_LPC435x/3x/2x/1x (LPC435x_3x_2x_1x errata). All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 145 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 18. Revision history Table 43. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC435X_3X_2X_1X v.3 20121206 - Modifications: LPC4357_53_37_33 v.2.1 Modifications: LPC4357_53_37_33 v.2 LPC435X_3X_2X_1X Preliminary data sheet Preliminary data sheet LPC4357_53_37_33 v.2.1 • • • • • • • • • • • TFBGA180 packages removed. • • SPIFI maximum data rate changed to 52 MB per second. • • • Table 14 “Band gap characteristics” added. • • • OTP memory size changed to 64 bit. Part LPC432x and LPC431x added. SCT dither engine added and SCT bi-directional event enable features added. Figure 10 “Dual-core debug configuration” added. T = 105 °C data added in Figure 20 to Figure 23. Change symbol names and parameter names in Table 21. Parameter ILH updated for condition VI = 5 V and Tamb = 25 °C/105 °C in Table 11. Power consumption data added in Section 10.1. SPIFI dynamic characteristics added in Section 11.16. IRC accuracy corrected to  2 % for Tamb = -40 °C to 0 °C and Tamb = 85 °C to 105 °C. Pull-up and Pull-down current data (Figure 24 and Figure 25) updated with data for Tamb = 105 °C. Recommendation for VBAT use added: The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. Section 7.23.9 “Power Management Controller (PMC)” added. Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to ADC0 and ADC1. See Table 3. Use of C_CAN peripheral restricted in Section 2. ADC channels limited to a total of 8 channels shared between ADC0 and ADC1. 20120904 Preliminary data sheet - LPC4357_53_37_33 v.2 • SSP0 boot pin functions corrected in Table 5 and Table 4. Pin P3_3 = SSP0_SCK, pin P3_6 = SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI. • • • • SWD removed for ARM Cortex-M0. BOD de-assertion levels added in Table 13. Peripheral power consumption data added in Table 12. Minimum value for all supply voltages changed to -0.5 V in Table 7. 20120711 Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 LPC4357_53 v.1 © NXP B.V. 2012. All rights reserved. 146 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 43. Revision history …continued Document ID Modifications: LPC4357_53 v.1 LPC435X_3X_2X_1X Preliminary data sheet Release date Data sheet status • • • Change notice Supersedes Data sheet status changed to preliminary. Parts LPC4337 and LPC4333 added. Minimum value of VI for conditions “USB0 pins USB0_DP; USB0_DM; USB0_VBUS”, “USB0 pins USB0_ID; USB0_RREF”, and “USB1 pins USB1_DP and USB1_DM” changed to 0.3 V in Table 6. • • Section 10.2 added. • • • • • AES removed. Available on parts LPC43Sxx only. Table 8 “Thermal resistance (LQFP packages)” and Table 9 “Thermal resistance value (BGA packages)” added. Dynamic characteristics of the SD/MMC controller updated in Table 30. Dynamic characteristics of the LCD controller updated in Table 31. Dynamic characteristics of the SSP controller updated in Table 23. Parameters IIL and IIH renamed to ILL and ILH in Table 10. 20120604 Objective data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 - © NXP B.V. 2012. All rights reserved. 147 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. LPC435X_3X_2X_1X Preliminary data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 148 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 149 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 61 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 61 7.2 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 61 7.3 ARM Cortex-M0 co-processor . . . . . . . . . . . . 61 7.4 Interprocessor communication . . . . . . . . . . . . 61 7.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 62 7.6 Nested Vectored Interrupt Controller (NVIC) . 62 7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 63 7.7 System Tick timer (SysTick) . . . . . . . . . . . . . . 63 7.8 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.9 Global Input Multiplexer Array (GIMA) . . . . . . 64 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.10 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 64 7.11 On-chip flash memory . . . . . . . . . . . . . . . . . . 64 7.12 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.13 Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.14 Memory mapping . . . . . . . . . . . . . . . . . . . . . . 66 7.15 One-Time Programmable (OTP) memory . . . 69 7.16 General Purpose I/O (GPIO) . . . . . . . . . . . . . 69 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.17 Configurable digital peripherals . . . . . . . . . . . 69 7.17.1 State Configurable Timer (SCT) subsystem . . 69 7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.17.2 Serial GPIO (SGPIO) . . . . . . . . . . . . . . . . . . . 70 7.17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.18 AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 71 7.18.1 General Purpose DMA . . . . . . . . . . . . . . . . . 71 7.18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.18.2 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 71 7.18.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.18.3 SD/MMC card interface . . . . . . . . . . . . . . . . . 72 7.18.4 External Memory Controller (EMC). . . . . . . . . 72 7.18.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.18.5 High-speed USB Host/Device/OTG interface (USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.18.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.18.6 7.18.6.1 7.18.7 7.18.7.1 7.18.8 7.18.8.1 7.19 7.19.1 7.19.1.1 7.19.2 7.19.2.1 7.19.3 7.19.3.1 7.19.4 7.19.4.1 7.19.5 7.19.5.1 7.19.6 7.19.6.1 7.19.7 7.19.7.1 7.20 7.20.1 7.20.1.1 7.20.2 7.20.3 7.20.3.1 7.20.4 7.20.4.1 7.20.5 7.20.5.1 7.21 7.21.1 7.21.1.1 7.21.2 7.21.2.1 7.22 7.22.1 7.22.1.1 7.22.1.2 7.22.2 7.23 7.23.1 7.23.2 7.23.3 7.23.4 High-speed USB Host/Device interface with ULPI (USB1). . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD controller . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital serial peripherals. . . . . . . . . . . . . . . . . UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART0/2/3 . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI serial I/O controller . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSP serial I/O controller. . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/timers and motor control . . . . . . . . . General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motor control PWM . . . . . . . . . . . . . . . . . . . . Quadrature Encoder Interface (QEI) . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Repetitive Interrupt (RI) timer. . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Windowed WatchDog Timer (WWDT) . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog peripherals . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC0/1) . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-to-Analog Converter (DAC). . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripherals in the RTC power domain . . . . . . RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event monitor/recorder . . . . . . . . . . . . . . . . . Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . System control . . . . . . . . . . . . . . . . . . . . . . . . Configuration registers (CREG) . . . . . . . . . . . System Control Unit (SCU) . . . . . . . . . . . . . . Clock Generation Unit (CGU) . . . . . . . . . . . . Internal RC oscillator (IRC) . . . . . . . . . . . . . . 74 74 74 75 75 75 76 76 76 76 77 77 77 77 77 78 78 78 79 79 79 79 79 80 80 80 80 81 81 81 81 82 82 82 82 82 82 82 82 83 83 83 83 84 84 84 continued >> LPC435X_3X_2X_1X Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 6 December 2012 © NXP B.V. 2012. All rights reserved. 150 of 151 LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.23.5 7.23.6 7.23.7 7.23.8 7.23.9 7.23.10 7.23.11 7.24 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 12 13 13.1 13.2 13.3 13.4 13.5 13.5.1 14 15 16 17 18 19 19.1 PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 84 PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 84 System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 85 Reset Generation Unit (RGU). . . . . . . . . . . . . 85 Power Management Controller (PMC) . . . . . . 85 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 86 Code security (Code Read Protection - CRP) 87 Serial Wire Debug/JTAG. . . . . . . . . . . . . . . . . 88 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 89 Thermal characteristics . . . . . . . . . . . . . . . . . 90 Static characteristics. . . . . . . . . . . . . . . . . . . . 91 Power consumption . . . . . . . . . . . . . . . . . . . . 98 Peripheral power consumption . . . . . . . . . . . 101 Electrical pin characteristics . . . . . . . . . . . . . 103 BOD and band gap static characteristics . . . 107 Dynamic characteristics . . . . . . . . . . . . . . . . 108 Flash/EEPROM memory . . . . . . . . . . . . . . . 108 Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 109 External clock for oscillator in slave mode . . 109 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 110 IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 110 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 110 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 112 USART interface. . . . . . . . . . . . . . . . . . . . . . 113 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 114 External memory interface . . . . . . . . . . . . . . 117 USB interface . . . . . . . . . . . . . . . . . . . . . . . 122 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ADC/DAC electrical characteristics . . . . . . . 127 Application information. . . . . . . . . . . . . . . . . 130 LCD panel signal usage . . . . . . . . . . . . . . . . 130 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 132 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 134 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . 134 Standard I/O pin configuration . . . . . . . . . . . 134 Reset pin configuration . . . . . . . . . . . . . . . . . 135 Package outline . . . . . . . . . . . . . . . . . . . . . . . 136 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 144 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Revision history . . . . . . . . . . . . . . . . . . . . . . . 146 Legal information. . . . . . . . . . . . . . . . . . . . . . 148 Data sheet status . . . . . . . . . . . . . . . . . . . . . 148 19.2 19.3 19.4 20 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 148 149 149 150 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 December 2012 Document identifier: LPC435X_3X_2X_1X