LPC43S70FET256551

LPC43S70 32-bit ARM Cortex-M4 + 2 x M0 MCU; 282 kB SRAM; Ethernet; two HS USBs; 80 Msps 12-bit ADC; configurable peripherals, AES engine Rev. 1.2 — 15 March 2016 Product data sheet 1. General description The LPC43S70 are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM Cortex-M0 coprocessor and an ARM Cortex-M0 subsystem for managing peripherals, 282 kB of SRAM, advanced configurable peripherals such as the State Configurable Timer (SCTimer/PWM) and the Serial General Purpose I/O (SGPIO) interface, security features with AES engine, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals including a high-speed 12-bit ADC. The LPC43S70 operate at CPU frequencies of up to 204 MHz. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M4 with floating-point unit is often referred to as M4F. The LPC43S70 include an application ARM Cortex-M0 coprocessor and a second ARM Cortex-M0 subsystem for managing the SGPIO and SPI peripherals. The ARM Cortex-M0 core is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance with a simple instruction set and reduced code size. The Cortex-M0 does not support hardware multiply. 2. Features and benefits  Main Cortex-M4 processor  ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.  Built-in Memory Protection Unit (MPU) supporting eight regions.  Built-in Nested Vectored Interrupt Controller (NVIC).  Hardware floating-point unit.  Non-maskable Interrupt (NMI) input.  JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.  Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.  System tick timer.  Cortex-M0 coprocessor LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller      LPC43S70 Product data sheet  ARM Cortex-M0 coprocessor capable of off-loading the main ARM Cortex-M4 processor.  Running at frequencies of up to 204 MHz.  JTAG and built-in NVIC. Cortex-M0 subsystem  ARM Cortex-M0 processor controlling the SPI and SGPIO peripherals residing on a separate AHB multilayer matrix with direct access to 2 kB + 16 kB of SRAM.  Running at frequencies of up to 204 MHz.  Connected via a core-to-core bridge to the main AHB multilayer matrix and the main ARM Cortex-M4 processor.  JTAG and built-in NVIC. On-chip memory  264 kB SRAM for code and data use on the main AHB multilayer matrix plus 18 kB of SRAM on the Cortex-M0 subsystem.  Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.  64 kB ROM containing boot code and on-chip software drivers.  64-bit of One-Time Programmable (OTP) memory for general-purpose use.  Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage. One bank can store an encrypted key for decoding the boot image. AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API. Configurable digital peripherals  Serial GPIO (SGPIO) interface.  State Configurable Timer (SCT) subsystem on AHB.  Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCT, and ADC0/1. Serial interfaces  Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.  10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).  One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY.  One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.  USB interface electrical test software included in ROM USB stack.  One 550 UART with DMA support and full modem interface.  Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface.  Two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge. See Figure 1 and Ref. 1.  Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.  One SPI controller. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 2 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller     LPC43S70 Product data sheet  One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.  One standard I2C-bus interface with monitor mode and with standard I/O pins.  Two I2S interfaces, each with DMA support and with one input and one output. Digital peripherals  External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.  LCD controller with DMA support and a programmable display resolution of up to 1024 H  768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping.  Secure Digital Input Output (SD/MMC) card interface.  Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB slaves.  164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open-drain mode.  GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.  Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.  Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  Four general-purpose timer/counters with capture and match capabilities.  One motor control Pulse Width Modulator (PWM) for three-phase motor control.  One Quadrature Encoder Interface (QEI).  Repetitive Interrupt timer (RI timer).  Windowed watchdog timer (WWDT).  Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.  Alarm timer; can be battery powered. Analog peripherals  One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s. LBGA256 package only.  Two 8-channel, 10-bit ADCs (ADC0/1) with DMA support and a data conversion rate of 400 kSamples/s for a total of 16 independent channels. The 10-bit ADCs are only available on the LBGA256 package.  One 6-channel, 12-bit high-speed ADC (ADCHS) with DMA support and a data conversion rate of 80 MSamples/s. Unique ID for each device. Clock generation unit  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and voltage.  Ultra-low power Real-Time Clock (RTC) crystal oscillator. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 3 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller  Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.  Clock output.  Power  Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the core supply and the RTC power domain.  RTC power domain can be powered separately by a 3 V battery supply.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.  Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.  Brownout detect with four separate thresholds for interrupt and forced reset.  Power-On Reset (POR).  Available as LBGA256 and TFBGA100 packages. 3. Applications     LPC43S70 Product data sheet Motor control Power management White goods RFID readers  Embedded audio applications  Industrial automation  e-metering All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 4 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC43S70FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC43S70FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 4.1 Ordering options Table 2. Ordering options Total SRAM LCD Ethernet USB0 (Host, Device, OTG) USB1 (Host, Device)/ ULPI interface 10-bit ADC channels ADC0/ADC1 12-bit ADC channels PWM QEI GPIO Package Type number LPC43S70FET256 282 kB yes yes yes yes/yes 8/8 6 yes yes 164 LBGA256 LPC43S70FET100 282 kB no yes yes yes/no n/a 3 no no 49 TFBGA100 LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 5 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 5. Block diagram slaves LPC43S70 SUBSYSTEM AHB MULTILAYER MATRIX system bus masters 2 kB LOCAL SRAM 16 kB LOCAL SRAM ARM CORTEX-M0 SPI SUBSYSTEM SGPIO TEST/DEBUG INTERFACE CORE-CORE BRIDGE TEST/DEBUG INTERFACE MPU FPU TEST/DEBUG INTERFACE HIGH-SPEED PHY ARM CORTEX-M4 system bus D-code bus I-code bus ETHERNET 10/100 MAC IEEE 1588 DMA HIGH-SPEED USB0 HOST/ DEVICE/OTG HIGH-SPEED USB1 HOST/DEVICE LCD(1) SD/ MMC ARM CORTEX-M0 masters master AHB MULTILAYER MATRIX slaves BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE BRIDGE 128 kB LOCAL SRAM 72 kB LOCAL SRAM 64 kB ROM RI TIMER I2C1 CGU ALARM TIMER USART0 MOTOR CONTROL PWM USART2 10-bit DAC CCU1 BACKUP REGISTERS UART1 I2C0 USART3 C_CAN0 CCU2 POWER MODE CONTROL SSP0 I2S0 TIMER2 10-bit ADC0 RGU SPIFI TIMER0 I2S1 CONFIGURATION REGISTERS TIMER3 10-bit ADC1 EVENT ROUTER EMC TIMER1 C_CAN1 SSP1 OTP MEMORY 12-bit ADC (ADCHS) WWDT SCT QEI SCU GPIO INTERRUPTS 32 kB AHB SRAM 16 +16 kB AHB SRAM RTC RTC OSC GIMA 12 MHz IRC GPIO GROUP0 INTERRUPT HS GPIO AES ENCRYPTION/ DECRYPTION RTC POWER DOMAIN GPIO GROUP1 INTERRUPT = connected to GPDMA aaa-016379 (1) Not available on all parts (see Table 2). Fig 1. LPC43S70 Block diagram LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 6 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 6. Pinning information 6.1 Pinning LPC43S70FET256 ball A1 index area 2 1 4 3 6 5 8 7 10 9 12 11 14 13 ball A1 index area 16 LPC43S70FET100 1 15 A 2 3 4 5 6 7 8 A B C B E C D F D G E H J F L G K M H N J P R K T aaa-016396 aaa-016618 Transparent top view Transparent top view Fig 2. 9 10 Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA100 package 6.2 Pin description On the LPC43S70, digital pins are grouped into 16 ports, named P0 to P9 and PA to PF, with up to 20 pins used per port. Each digital pin can support up to eight different digital functions, including General Purpose I/O (GPIO), selectable through the System Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port assigned to it. Not all functions listed in Table 3 are available on all packages. See Table 2 for availability of USB0, USB1, Ethernet, and LCD functions. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 7 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Type Description [2] TFBGA100 LBGA256 Symbol Reset state Table 3. Pin description LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Multiplexed digital pins P0_0 P0_1 L3 M2 G2 G1 [3] [3] I; PU I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). I/O SGPIO0 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I; PU I/O GPIO0[1] — General purpose digital input/output pin. I/O SSP1_MOSI — Master Out Slave in for SSP1. I ENET_COL — Ethernet Collision detect (MII interface). I/O SGPIO1 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). I/O P1_0 P1_1 P2 R2 LPC43S70 Product data sheet H1 K2 [3] [3] I; PU I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. GPIO0[4] — General purpose digital input/output pin. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. I/O EMC_A5 — External memory address line 5. - R — Function reserved. - R — Function reserved. I/O SSP0_SSEL — Slave Select for SSP0. I/O SGPIO7 — General purpose digital input/output pin. - R — Function reserved. I; PU I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_7 — SCT output 7. Match output 3 of timer 1. I/O EMC_A6 — External memory address line 6. I/O SGPIO8 — General purpose digital input/output pin. - R — Function reserved. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 8 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_3 P1_4 P1_5 K1 P5 T3 R5 LPC43S70 Product data sheet J1 J2 J4 [3] [3] [3] [3] Type R3 Description [2] TFBGA100 P1_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO0[9] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_6 — SCT output 6. Match output 2 of timer 1. I/O EMC_A7 — External memory address line 7. I/O SGPIO9 — General purpose digital input/output pin. - R — Function reserved. I/O SSP0_MOSI — Master Out Slave in for SSP0. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO0[10] — General purpose digital input/output pin. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. I/O SGPIO10 — General purpose digital input/output pin. O EMC_OE — LOW active Output Enable signal. O USB0_IND1 — USB0 port indicator LED control output 1. I/O SSP1_MISO — Master In Slave Out for SSP1. - R — Function reserved. O SD_RST — SD/MMC reset signal for MMC4.4 card. I; PU I/O GPIO0[11] — General purpose digital input/output pin. O CTOUT_9 — SCT output 9. Match output 1 of timer 2. I/O SGPIO11 — General purpose digital input/output pin. O EMC_BLS0 — LOW active Byte Lane select signal 0. O USB0_IND0 — USB0 port indicator LED control output 0. I/O SSP1_MOSI — Master Out Slave in for SSP1. - R — Function reserved. O SD_VOLT1 — SD/MMC bus voltage select output 1. I; PU I/O GPIO1[8] — General purpose digital input/output pin. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. - R — Function reserved. O EMC_CS0 — LOW active Chip Select 0 signal. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). I/O SSP1_SSEL — Slave Select for SSP1. I/O SGPIO15 — General purpose digital input/output pin. O SD_POW — SD/MMC power monitor output. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 9 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_7 K4 T5 G4 [3] [3] Type T4 Description [2] TFBGA100 P1_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[9] — General purpose digital input/output pin. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. - R — Function reserved. O EMC_WE — LOW active Write Enable signal. - R — Function reserved. - R — Function reserved. I/O SGPIO14 — General purpose digital input/output pin. I/O SD_CMD — SD/MMC command signal. I; PU I/O GPIO1[0] — General purpose digital input/output pin. I U1_DSR — Data Set Ready input for UART1. O CTOUT_13 — SCT output 13. Match output 1 of timer 3. I/O EMC_D0 — External memory data line 0. O USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active HIGH). Add a pull-down resistor to disable the power switch at reset. This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts. P1_8 P1_9 R7 T7 LPC43S70 Product data sheet H5 J5 [3] [3] - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO1[1] — General purpose digital input/output pin. O U1_DTR — Data Terminal Ready output for UART1. O CTOUT_12 — SCT output 12. Match output 0 of timer 3. I/O EMC_D1 — External memory data line 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. O SD_VOLT0 — SD/MMC bus voltage select output 0. I; PU I/O GPIO1[2] — General purpose digital input/output pin. O U1_RTS — Request to Send output for UART1. O CTOUT_11 — SCT output 11. Match output 3 of timer 2. I/O EMC_D2 — External memory data line 2. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SD_DAT0 — SD/MMC data bus line 0. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 10 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_11 P1_12 P1_13 H6 T9 R9 R10 LPC43S70 Product data sheet J7 K7 H8 [3] [3] [3] [3] Type R8 Description [2] TFBGA100 P1_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[3] — General purpose digital input/output pin. I U1_RI — Ring Indicator input for UART1. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. I/O EMC_D3 — External memory data line 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SD_DAT1 — SD/MMC data bus line 1. I; PU I/O GPIO1[4] — General purpose digital input/output pin. I U1_CTS — Clear to Send input for UART1. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. I/O EMC_D4 — External memory data line 4. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SD_DAT2 — SD/MMC data bus line 2. I; PU I/O GPIO1[5] — General purpose digital input/output pin. I U1_DCD — Data Carrier Detect input for UART1. - R — Function reserved. I/O EMC_D5 — External memory data line 5. I T0_CAP1 — Capture input 1 of timer 0. - R — Function reserved. I/O SGPIO8 — General purpose digital input/output pin. I/O SD_DAT3 — SD/MMC data bus line 3. I; PU I/O GPIO1[6] — General purpose digital input/output pin. O U1_TXD — Transmitter output for UART1. - R — Function reserved. I/O EMC_D6 — External memory data line 6. I T0_CAP0 — Capture input 0 of timer 0. - R — Function reserved. I/O SGPIO9 — General purpose digital input/output pin. I SD_CD — SD/MMC card detect input. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 11 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_15 P1_16 P1_17 J8 T12 M7 M8 LPC43S70 Product data sheet K8 H9 H10 [3] [3] [3] [4] Type R11 Description [2] TFBGA100 P1_14 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[7] — General purpose digital input/output pin. I U1_RXD — Receiver input for UART1. - R — Function reserved. I/O EMC_D7 — External memory data line 7. O T0_MAT2 — Match output 2 of timer 0. - R — Function reserved. I/O SGPIO10 — General purpose digital input/output pin. - R — Function reserved. I; PU I/O GPIO0[2] — General purpose digital input/output pin. O U2_TXD — Transmitter output for USART2. I/O SGPIO2 — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). O T0_MAT1 — Match output 1 of timer 0. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO0[3] — General purpose digital input/output pin. I U2_RXD — Receiver input for USART2. I/O SGPIO3 — General purpose digital input/output pin. I ENET_CRS — Ethernet Carrier Sense (MII interface). O T0_MAT0 — Match output 0 of timer 0. - R — Function reserved. - R — Function reserved. I ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). I; PU I/O GPIO0[12] — General purpose digital input/output pin. I/O U2_UCLK — Serial clock input/output for USART2 in synchronous mode. - R — Function reserved. I/O ENET_MDIO — Ethernet MIIM data input and output. I T0_CAP3 — Capture input 3 of timer 0. O CAN1_TD — CAN1 transmitter output. I/O SGPIO11 — General purpose digital input/output pin. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 12 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_19 P1_20 J10 M11 M10 K9 K10 [3] [3] [3] Type N12 Description [2] TFBGA100 P1_18 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O I/O U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. - R — Function reserved. O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). O T0_MAT3 — Match output 3 of timer 0. I CAN1_RD — CAN1 receiver input. I/O SGPIO12 — General purpose digital input/output pin. - R — Function reserved. I; PU I T16 G10 [3] ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). I/O SSP1_SCK — Serial clock for SSP1. - R — Function reserved. - R — Function reserved. O CLKOUT — Clock output pin. - R — Function reserved. O I2S0_RX_MCLK — I2S receive master clock. I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I; PU I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1. - R — Function reserved. O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). I T0_CAP2 — Capture input 2 of timer 0. - R — Function reserved. I/O SGPIO13 — General purpose digital input/output pin. P2_0 GPIO0[13] — General purpose digital input/output pin. I; PU I/O R — Function reserved. SGPIO4 — General purpose digital input/output pin. O U0_TXD — Transmitter output for USART0. I/O EMC_A13 — External memory address line 13. O USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active HIGH). Add a pull-down resistor to disable the power switch at reset. This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts. LPC43S70 Product data sheet I/O GPIO5[0] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP0 — Capture input 0 of timer 3. O ENET_MDC — Ethernet MIIM clock. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 13 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P2_2 P2_3 P2_4 G7 M15 J12 K11 LPC43S70 Product data sheet F5 D8 D9 [3] [3] [4] [4] Type N15 Description [2] TFBGA100 P2_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O SGPIO5 — General purpose digital input/output pin. I U0_RXD — Receiver input for USART0. I/O EMC_A12 — External memory address line 12. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). I/O GPIO5[1] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP1 — Capture input 1 of timer 3. - R — Function reserved. I; PU I/O SGPIO6 — General purpose digital input/output pin. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O EMC_A11 — External memory address line 11. O USB0_IND1 — USB0 port indicator LED control output 1. I/O GPIO5[2] — General purpose digital input/output pin. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. I T3_CAP2 — Capture input 2 of timer 3. - R — Function reserved. I; PU I/O SGPIO12 — General purpose digital input/output pin. I/O I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). O U3_TXD — Transmitter output for USART3. I CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. I/O GPIO5[3] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT0 — Match output 0 of timer 3. I USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that Vbus must be driven (active HIGH). I; PU I/O SGPIO13 — General purpose digital input/output pin. I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). I U3_RXD — Receiver input for USART3. I CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. I/O GPIO5[4] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT1 — Match output 1 of timer 3. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 14 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller D10 [4] Type K14 Description [2] TFBGA100 P2_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O SGPIO14 — General purpose digital input/output pin. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. I USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur. P2_6 P2_7 P2_8 K16 H14 J16 LPC43S70 Product data sheet G9 C10 C6 [3] [3] [3] I ADCTRIG1 — ADC trigger input 1. I/O GPIO5[5] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT2 — Match output 2 of timer 3. O USB0_IND0 — USB0 port indicator LED control output 0. I; PU I/O SGPIO7 — General purpose digital input/output pin. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O EMC_A10 — External memory address line 10. O USB0_IND0 — USB0 port indicator LED control output 0. I/O GPIO5[6] — General purpose digital input/output pin. I CTIN_7 — SCT input 7. I T3_CAP3 — Capture input 3 of timer 3. - R — Function reserved. I; PU I/O GPIO0[7] — General purpose digital input/output pin. If this pin is pulled LOW at reset, the part enters ISP mode using USART0. O CTOUT_1 — SCT output 1. Match output 1 of timer 0. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. I/O EMC_A9 — External memory address line 9. - R — Function reserved. - R — Function reserved. O T3_MAT3 — Match output 3 of timer 3. - R — Function reserved. I; PU I/O SGPIO15 — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_0 — SCT output 0. Match output 0 of timer 0. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O EMC_A8 — External memory address line 8. I/O GPIO5[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 15 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P2_10 P2_11 P2_12 B10 G16 F16 E15 LPC43S70 Product data sheet E8 A9 B9 [3] [3] [3] [3] Type H16 Description [2] TFBGA100 P2_9 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_3 — SCT output 3. Match output 3 of timer 0. I/O U3_BAUD — Baud pin for USART3. I/O EMC_A0 — External memory address line 0. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO0[14] — General purpose digital input/output pin. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. O U2_TXD — Transmitter output for USART2. I/O EMC_A1 — External memory address line 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO1[11] — General purpose digital input/output pin. O CTOUT_5 — SCT output 5. Match output 1 of timer 1. I U2_RXD — Receiver input for USART2. I/O EMC_A2 — External memory address line 2. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO1[12] — General purpose digital input/output pin. O CTOUT_4 — SCT output 4. Match output 0 of timer 1. - R — Function reserved. I/O EMC_A3 — External memory address line 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O U2_UCLK — Serial clock input/output for USART2 in synchronous mode. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 16 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_0 A10 F13 A8 [3] [3] Type C16 Description [2] TFBGA100 P2_13 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O I CTIN_4 — SCT input 4. Capture input 2 of timer 1. - R — Function reserved. I/O EMC_A4 — External memory address line 4. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. I; PU I/O P3_2 G11 F11 LPC43S70 Product data sheet F7 G6 [3] [3] I2S0_RX_SCK — I2S receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O I2S0_RX_MCLK — I2S receive master clock. I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O I2S0_TX_MCLK — I2S transmit master clock. I/O SSP0_SCK — Serial clock for SSP0. - R — Function reserved. - R — Function reserved. P3_1 GPIO1[13] — General purpose digital input/output pin. R — Function reserved. I; PU I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I CAN0_RD — CAN receiver input. O USB1_IND1 — USB1 Port indicator LED control output 1. I/O GPIO5[8] — General purpose digital input/output pin. - R — Function reserved. O LCD_VD15 — LCD data. - R — Function reserved. I; PU I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O CAN0_TD — CAN transmitter output. O USB1_IND0 — USB1 Port indicator LED control output 0. I/O GPIO5[9] — General purpose digital input/output pin. - R — Function reserved. O LCD_VD14 — LCD data. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 17 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_4 P3_5 P3_6 A7 A15 C12 B13 LPC43S70 Product data sheet B8 B7 C7 [5] [3] [3] [3] Type B14 Description [2] TFBGA100 P3_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O SPI_SCK — Serial clock for SPI. I/O SSP0_SCK — Serial clock for SSP0. O SPIFI_SCK — Serial clock for SPIFI. O CGU_OUT1 — CGU spare clock output 1. - R — Function reserved. O I2S0_TX_MCLK — I2S transmit master clock. I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I; PU I/O GPIO1[14] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SPIFI_SIO3 — I/O lane 3 for SPIFI. O U1_TXD — Transmitter output for UART 1. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O LCD_VD13 — LCD data. I; PU I/O GPIO1[15] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SPIFI_SIO2 — I/O lane 2 for SPIFI. I U1_RXD — Receiver input for UART 1. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O I2S1_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O LCD_VD12 — LCD data. I; PU I/O GPIO0[6] — General purpose digital input/output pin. I/O SPI_MISO — Master In Slave Out for SPI. I/O SSP0_SSEL — Slave Select for SSP0. I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1. - R — Function reserved. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 18 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_8 P4_0 P4_1 D7 C10 D5 A1 E7 - - [3] [3] [3] [6] [13] LPC43S70 Product data sheet Type C11 Description [2] TFBGA100 P3_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O SPI_MOSI — Master Out Slave In for SPI. I/O SSP0_MISO — Master In Slave Out for SSP0. I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0. I/O GPIO5[10] — General purpose digital input/output pin. I/O SSP0_MOSI — Master Out Slave in for SSP0. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. I SPI_SSEL — Slave Select for SPI. Note that this pin in an input pin only. The SPI in master mode cannot drive the CS input on the slave. Any GPIO pin can be used for SPI chip select in master mode. I/O SSP0_MOSI — Master Out Slave in for SSP0. I/O SPIFI_CS — SPIFI serial flash chip select. I/O GPIO5[11] — General purpose digital input/output pin. I/O SSP0_SSEL — Slave Select for SSP0. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO2[0] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. I NMI — External interrupt input to NMI. - R — Function reserved. - R — Function reserved. O LCD_VD13 — LCD data. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. - R — Function reserved. I; PU I/O GPIO2[1] — General purpose digital input/output pin. O CTOUT_1 — SCT output 1. Match output 1 of timer 0. O LCD_VD0 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD19 — LCD data. O U3_TXD — Transmitter output for USART3. I ENET_COL — Ethernet Collision detect (MII interface). AI ADC0_1 — ADC0, input channel 1. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 19 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P4_3 - C2 - [3] [6] [13] P4_4 P4_5 B1 D2 LPC43S70 Product data sheet - - [6] [3] Type D3 Description [2] TFBGA100 P4_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO2[2] — General purpose digital input/output pin. O CTOUT_0 — SCT output 0. Match output 0 of timer 0. O LCD_VD3 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD12 — LCD data. I U3_RXD — Receiver input for USART3. I/O SGPIO8 — General purpose digital input/output pin. I; PU I/O GPIO2[3] — General purpose digital input/output pin. O CTOUT_3 — SCT output 3. Match output 3 of timer 0. O LCD_VD2 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD21 — LCD data. I/O U3_BAUD — Baud pin for USART3. I/O SGPIO9 — General purpose digital input/output pin. AI ADC0_0 — ADC0, input channel 0. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU I/O GPIO2[4] — General purpose digital input/output pin. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. O LCD_VD1 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD20 — LCD data. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SGPIO10 — General purpose digital input/output pin. O DAC — DAC output. Configure the pin as GPIO input and use the analog function select register in the SCU to select the DAC. I; PU I/O GPIO2[5] — General purpose digital input/output pin. O CTOUT_5 — SCT output 5. Match output 1 of timer 1. O LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT). - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SGPIO11 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 20 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P4_7 P4_8 - H4 E2 - - [3] [3] [3] Type C1 Description [2] TFBGA100 P4_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O O; PU O CTOUT_4 — SCT output 4. Match output 0 of timer 1. O LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SGPIO12 — General purpose digital input/output pin. O LCD_DCLK — LCD panel clock. I GP_CLKIN — General purpose clock input to the CGU. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I; PU - L2 LPC43S70 Product data sheet - [3] R — Function reserved. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. O LCD_VD9 — LCD data. - R — Function reserved. I/O GPIO5[12] — General purpose digital input/output pin. O LCD_VD22 — LCD data. O CAN1_TD — CAN1 transmitter output. I/O P4_9 GPIO2[6] — General purpose digital input/output pin. I; PU - SGPIO13 — General purpose digital input/output pin. R — Function reserved. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. O LCD_VD11 — LCD data. - R — Function reserved. I/O GPIO5[13] — General purpose digital input/output pin. O LCD_VD15 — LCD data. I CAN1_RD — CAN1 receiver input. I/O SGPIO14 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 21 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P5_0 P5_1 P5_2 - N3 P3 R4 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type M3 Description [2] TFBGA100 P4_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. O LCD_VD10 — LCD data. - R — Function reserved. I/O GPIO5[14] — General purpose digital input/output pin. O LCD_VD14 — LCD data. - R — Function reserved. I/O SGPIO15 — General purpose digital input/output pin. I; PU I/O GPIO2[9] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I/O EMC_D12 — External memory data line 12. - R — Function reserved. I U1_DSR — Data Set Ready input for UART 1. I T1_CAP0 — Capture input 0 of timer 1. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO2[10] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. I/O EMC_D13 — External memory data line 13. - R — Function reserved. O U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I T1_CAP1 — Capture input 1 of timer 1. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO2[11] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. I/O EMC_D14 — External memory data line 14. - R — Function reserved. O U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I T1_CAP2 — Capture input 2 of timer 1. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 22 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P5_4 P5_5 P5_6 - P9 P10 T13 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type T8 Description [2] TFBGA100 P5_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO2[12] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. I/O EMC_D15 — External memory data line 15. - R — Function reserved. I U1_RI — Ring Indicator input for UART 1. I T1_CAP3 — Capture input 3 of timer 1. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO2[13] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I/O EMC_D8 — External memory data line 8. - R — Function reserved. I U1_CTS — Clear to Send input for UART 1. O T1_MAT0 — Match output 0 of timer 1. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO2[14] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. I/O EMC_D9 — External memory data line 9. - R — Function reserved. I U1_DCD — Data Carrier Detect input for UART 1. O T1_MAT1 — Match output 1 of timer 1. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO2[15] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. I/O EMC_D10 — External memory data line 10. - R — Function reserved. O U1_TXD — Transmitter output for UART 1. O T1_MAT2 — Match output 2 of timer 1. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 23 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_0 P6_1 P6_2 - M12 R15 L13 LPC43S70 Product data sheet H7 G5 J9 [3] [3] [3] [3] Type R12 Description [2] TFBGA100 P5_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO2[7] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I/O EMC_D11 — External memory data line 11. - R — Function reserved. I U1_RXD — Receiver input for UART 1. O T1_MAT3 — Match output 3 of timer 1. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O I2S0_RX_MCLK — I2S receive master clock. - R — Function reserved. - R — Function reserved. I/O I2S0_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[0] — General purpose digital input/output pin. O EMC_DYCS1 — SDRAM chip select 1. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. - R — Function reserved. I T2_CAP0 — Capture input 2 of timer 2. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[1] — General purpose digital input/output pin. O EMC_CKEOUT1 — SDRAM clock enable 1. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. - R — Function reserved. I T2_CAP1 — Capture input 1 of timer 2. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 24 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_4 P6_5 P6_6 - R16 P16 L14 LPC43S70 Product data sheet F6 F9 - [3] [3] [3] [3] Type P15 Description [2] TFBGA100 P6_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[2] — General purpose digital input/output pin. I USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that the VBUS signal must be driven (active HIGH). I/O SGPIO4 — General purpose digital input/output pin. O EMC_CS1 — LOW active Chip Select 1 signal. - R — Function reserved. I T2_CAP2 — Capture input 2 of timer 2. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[3] — General purpose digital input/output pin. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. O U0_TXD — Transmitter output for USART0. O EMC_CAS — LOW active SDRAM Column Address Strobe. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[4] — General purpose digital input/output pin. O CTOUT_6 — SCT output 6. Match output 2 of timer 1. I U0_RXD — Receiver input for USART0. O EMC_RAS — LOW active SDRAM Row Address Strobe. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO0[5] — General purpose digital input/output pin. O EMC_BLS1 — LOW active Byte Lane select signal 1. I/O SGPIO5 — General purpose digital input/output pin. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). - R — Function reserved. I T2_CAP3 — Capture input 3 of timer 2. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 25 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_8 P6_9 P6_10 - H13 J15 H15 LPC43S70 Product data sheet - F8 - [3] [3] [3] [3] Type J13 Description [2] TFBGA100 P6_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O EMC_A15 — External memory address line 15. I/O SGPIO6 — General purpose digital input/output pin. O USB0_IND1 — USB0 port indicator LED control output 1. I/O GPIO5[15] — General purpose digital input/output pin. O T2_MAT0 — Match output 0 of timer 2. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. I/O EMC_A14 — External memory address line 14. I/O SGPIO7 — General purpose digital input/output pin. O USB0_IND0 — USB0 port indicator LED control output 0. I/O GPIO5[16] — General purpose digital input/output pin. O T2_MAT1 — Match output 1 of timer 2. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[5] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O EMC_DYCS0 — SDRAM chip select 0. - R — Function reserved. O T2_MAT2 — Match output 2 of timer 2. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[6] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. - R — Function reserved. O EMC_DQMOUT1 — Data mask 1 used with SDRAM and static devices. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 26 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_12 P7_0 P7_1 C9 G15 B16 C14 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type H12 Description [2] TFBGA100 P6_11 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O EMC_CKEOUT0 — SDRAM clock enable 0. - R — Function reserved. O T2_MAT3 — Match output 3 of timer 2. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO2[8] — General purpose digital input/output pin. O CTOUT_7 — SCT output 7. Match output 3 of timer 1. - R — Function reserved. O EMC_DQMOUT0 — Data mask 0 used with SDRAM and static devices. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[8] — General purpose digital input/output pin. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. - R — Function reserved. O LCD_LE — Line end signal. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SGPIO4 — General purpose digital input/output pin. I; PU I/O GPIO3[9] — General purpose digital input/output pin. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O LCD_VD19 — LCD data. O LCD_VD7 — LCD data. - R — Function reserved. O U2_TXD — Transmitter output for USART2. I/O SGPIO5 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 27 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P7_3 P7_4 P7_5 - C13 C8 A7 LPC43S70 Product data sheet - - - [3] [3] [6] [6] Type A16 Description [2] TFBGA100 P7_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[10] — General purpose digital input/output pin. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O LCD_VD18 — LCD data. O LCD_VD6 — LCD data. - R — Function reserved. I U2_RXD — Receiver input for USART2. I/O SGPIO6 — General purpose digital input/output pin. I; PU I/O GPIO3[11] — General purpose digital input/output pin. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. - R — Function reserved. O LCD_VD17 — LCD data. O LCD_VD5 — LCD data. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[12] — General purpose digital input/output pin. O CTOUT_13 — SCT output 13. Match output 1 of timer 3. - R — Function reserved. O LCD_VD16 — LCD data. O LCD_VD4 — LCD data. O TRACEDATA[0] — Trace data, bit 0. - R — Function reserved. - R — Function reserved. AI ADC0_4 — ADC0, input channel 4. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU I/O GPIO3[13] — General purpose digital input/output pin. O CTOUT_12 — SCT output 12. Match output 0 of timer 3. - R — Function reserved. O LCD_VD8 — LCD data. O LCD_VD23 — LCD data. O TRACEDATA[1] — Trace data, bit 1. - R — Function reserved. - R — Function reserved. AI ADC0_3 — ADC0, input channel 3. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 28 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P7_7 - B6 - [3] [6] [13] P8_0 E5 - [4] [13] P8_1 H5 LPC43S70 Product data sheet - [4] Type C7 Description [2] TFBGA100 P7_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[14] — General purpose digital input/output pin. O CTOUT_11 — SCT output 1. Match output 3 of timer 2. - R — Function reserved. O LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). - R — Function reserved. O TRACEDATA[2] — Trace data, bit 2. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO3[15] — General purpose digital input/output pin. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. - R — Function reserved. O LCD_PWR — LCD panel power enable. - R — Function reserved. O TRACEDATA[3] — Trace data, bit 3. O ENET_MDC — Ethernet MIIM clock. I/O SGPIO7 — General purpose digital input/output pin. AI ADC1_6 — ADC1, input channel 6. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU I/O GPIO4[0] — General purpose digital input/output pin. I USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). - R — Function reserved. I MCI2 — Motor control PWM channel 2, input. I/O SGPIO8 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O T0_MAT0 — Match output 0 of timer 0. I; PU I/O GPIO4[1] — General purpose digital input/output pin. O USB0_IND1 — USB0 port indicator LED control output 1. - R — Function reserved. I MCI1 — Motor control PWM channel 1, input. I/O SGPIO9 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O T0_MAT1 — Match output 1 of timer 0. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 29 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P8_3 P8_4 P8_5 - J3 J2 J1 LPC43S70 Product data sheet - - - [4] [3] [3] [3] Type K4 Description [2] TFBGA100 P8_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO4[2] — General purpose digital input/output pin. O USB0_IND0 — USB0 port indicator LED control output 0. - R — Function reserved. I MCI0 — Motor control PWM channel 0, input. I/O SGPIO10 — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O T0_MAT2 — Match output 2 of timer 0. I; PU I/O GPIO4[3] — General purpose digital input/output pin. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. - R — Function reserved. O LCD_VD12 — LCD data. O LCD_VD19 — LCD data. - R — Function reserved. - R — Function reserved. O T0_MAT3 — Match output 3 of timer 0. I; PU I/O GPIO4[4] — General purpose digital input/output pin. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. - R — Function reserved. O LCD_VD7 — LCD data. O LCD_VD16 — LCD data. - R — Function reserved. - R — Function reserved. I T0_CAP0 — Capture input 0 of timer 0. I; PU I/O GPIO4[5] — General purpose digital input/output pin. I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0. - R — Function reserved. O LCD_VD6 — LCD data. O LCD_VD8 — LCD data. - R — Function reserved. - R — Function reserved. I T0_CAP1 — Capture input 1 of timer 0. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 30 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [3] Type K3 Description [2] TFBGA100 P8_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. - R — Function reserved. O LCD_VD5 — LCD data. O LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). - R — Function reserved. - R — Function reserved. I P8_7 P8_8 P9_0 K1 L1 T1 LPC43S70 Product data sheet - - - [3] [3] [3] GPIO4[6] — General purpose digital input/output pin. I; PU I/O T0_CAP2 — Capture input 2 of timer 0. GPIO4[7] — General purpose digital input/output pin. O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. - R — Function reserved. O LCD_VD4 — LCD data. O LCD_PWR — LCD panel power enable. - R — Function reserved. - R — Function reserved. I T0_CAP3 — Capture input 3 of timer 0. I; PU - R — Function reserved. I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CGU_OUT0 — CGU spare clock output 0. O I2S1_TX_MCLK — I2S1 transmit master clock. I; PU I/O GPIO4[12] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. - R — Function reserved. - R — Function reserved. - R — Function reserved. I ENET_CRS — Ethernet Carrier Sense (MII interface). I/O SGPIO0 — General purpose digital input/output pin. I/O SSP0_SSEL — Slave Select for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 31 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [3] Type N6 Description [2] TFBGA100 P9_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O O MCOA2 — Motor control PWM channel 2, output A. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I ENET_RX_ER — Ethernet receive error (MII interface). I/O SGPIO1 — General purpose digital input/output pin. I/O P9_2 P9_3 P9_4 N8 M6 N10 LPC43S70 Product data sheet - - - [3] [3] [3] GPIO4[13] — General purpose digital input/output pin. I; PU I/O SSP0_MISO — Master In Slave Out for SSP0. GPIO4[14] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I ENET_RXD3 — Ethernet receive data 3 (MII interface). I/O SGPIO2 — General purpose digital input/output pin. I/O SSP0_MOSI — Master Out Slave in for SSP0. I; PU I/O GPIO4[15] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB1_IND1 — USB1 Port indicator LED control output 1. - R — Function reserved. - R — Function reserved. I ENET_RXD2 — Ethernet receive data 2 (MII interface). I/O SGPIO9 — General purpose digital input/output pin. O U3_TXD — Transmitter output for USART3. I; PU - R — Function reserved. O MCOB0 — Motor control PWM channel 0, output B. O USB1_IND0 — USB1 Port indicator LED control output 0. - R — Function reserved. I/O GPIO5[17] — General purpose digital input/output pin. O ENET_TXD2 — Ethernet transmit data 2 (MII interface). I/O SGPIO4 — General purpose digital input/output pin. I U3_RXD — Receiver input for USART3. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 32 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P9_6 - L11 - [3] [3] Type M9 Description [2] TFBGA100 P9_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU O MCOA1 — Motor control PWM channel 1, output A. O USB1_VBUS_EN — USB1 VBUS power enable. - R — Function reserved. I/O GPIO5[18] — General purpose digital input/output pin. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O SGPIO3 — General purpose digital input/output pin. O U0_TXD — Transmitter output for USART0. I; PU I/O L12 - [3] MCOB1 — Motor control PWM channel 1, output B. I USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current condition; this signal monitors over-current on the USB1 bus (external circuitry required to detect over-current condition). - R — Function reserved. - R — Function reserved. I ENET_COL — Ethernet Collision detect (MII interface). I/O SGPIO8 — General purpose digital input/output pin. J14 LPC43S70 Product data sheet - [4] U0_RXD — Receiver input for USART0. I; PU - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O I2S1_RX_MCLK — I2S1 receive master clock. O CGU_OUT1 — CGU spare clock output 1. PA_1 GPIO4[11] — General purpose digital input/output pin. O I PA_0 R — Function reserved. I; PU I/O R — Function reserved. GPIO4[8] — General purpose digital input/output pin. I QEI_IDX — Quadrature Encoder Interface INDEX input. - R — Function reserved. O U2_TXD — Transmitter output for USART2. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 33 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PA_3 PA_4 PB_0 - H11 G13 B15 LPC43S70 Product data sheet - - - [4] [4] [3] [3] Type K15 Description [2] TFBGA100 PA_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO4[9] — General purpose digital input/output pin. I QEI_PHB — Quadrature Encoder Interface PHB input. - R — Function reserved. I U2_RXD — Receiver input for USART2. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU I/O GPIO4[10] — General purpose digital input/output pin. I QEI_PHA — Quadrature Encoder Interface PHA input. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_9 — SCT output 9. Match output 1 of timer 2. - R — Function reserved. I/O EMC_A23 — External memory address line 23. I/O GPIO5[19] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. O LCD_VD23 — LCD data. - R — Function reserved. I/O GPIO5[20] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 34 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PB_2 PB_3 PB_4 - B12 A13 B11 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type A14 Description [2] TFBGA100 PB_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. O LCD_VD22 — LCD data. - R — Function reserved. I/O GPIO5[21] — General purpose digital input/output pin. O CTOUT_6 — SCT output 6. Match output 2 of timer 1. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. O LCD_VD21 — LCD data. - R — Function reserved. I/O GPIO5[22] — General purpose digital input/output pin. O CTOUT_7 — SCT output 7. Match output 3 of timer 1. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. O LCD_VD20 — LCD data. - R — Function reserved. I/O GPIO5[23] — General purpose digital input/output pin. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. O LCD_VD15 — LCD data. - R — Function reserved. I/O GPIO5[24] — General purpose digital input/output pin. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 35 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PB_6 - A6 - [3] [6] [13] PC_0 D4 - [6] [13] PC_1 E4 LPC43S70 Product data sheet - [3] Type A12 Description [2] TFBGA100 PB_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4. O LCD_VD14 — LCD data. - R — Function reserved. I/O GPIO5[25] — General purpose digital input/output pin. I CTIN_7 — SCT input 7. O LCD_PWR — LCD panel power enable. - R — Function reserved. I; PU - R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3. O LCD_VD13 — LCD data. - R — Function reserved. I/O GPIO5[26] — General purpose digital input/output pin. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. O LCD_VD19 — LCD data. - R — Function reserved. AI ADC0_6 — ADC0, input channel 6. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU - R — Function reserved. I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. - R — Function reserved. I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface). O LCD_DCLK — LCD panel clock. - R — Function reserved. - R — Function reserved. I/O SD_CLK — SD/MMC card clock. AI ADC1_1 — ADC1 and ADC0, input channel 1. Configure the pin as input (USB_ULPI_CLK) and use the ADC function select register in the SCU to select the ADC. I; PU I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. - R — Function reserved. I U1_RI — Ring Indicator input for UART 1. O ENET_MDC — Ethernet MIIM clock. I/O GPIO6[0] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP0 — Capture input 0 of timer 3. O SD_VOLT0 — SD/MMC bus voltage select output 0. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 36 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_3 PC_4 - F5 F4 - - [3] [6] [3] Type F6 Description [2] TFBGA100 PC_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. - R — Function reserved. I U1_CTS — Clear to Send input for UART 1. O ENET_TXD2 — Ethernet transmit data 2 (MII interface). I/O GPIO6[1] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O SD_RST — SD/MMC reset signal for MMC4.4 card. I; PU I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. - R — Function reserved. O U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O GPIO6[2] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. O SD_VOLT1 — SD/MMC bus voltage select output 1. AI ADC1_0 — ADC1, input channel 0. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU - R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4. - R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). PC_5 G4 LPC43S70 Product data sheet - [3] I/O GPIO6[3] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP1 — Capture input 1 of timer 3. I/O SD_DAT0 — SD/MMC data bus line 0. I; PU - R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3. - R — Function reserved. O ENET_TX_ER — Ethernet Transmit Error (MII interface). I/O GPIO6[4] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP2 — Capture input 2 of timer 3. I/O SD_DAT1 — SD/MMC data bus line 1. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 37 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_7 PC_8 PC_9 - G5 N4 K2 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type H6 Description [2] TFBGA100 PC_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. - R — Function reserved. I ENET_RXD2 — Ethernet receive data 2 (MII interface). I/O GPIO6[5] — General purpose digital input/output pin. - R — Function reserved. I T3_CAP3 — Capture input 3 of timer 3. I/O SD_DAT2 — SD/MMC data bus line 2. I; PU - R — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. - R — Function reserved. I ENET_RXD3 — Ethernet receive data 3 (MII interface). I/O GPIO6[6] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT0 — Match output 0 of timer 3. I/O SD_DAT3 — SD/MMC data bus line 3. I; PU - R — Function reserved. I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0. - R — Function reserved. I ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). I/O GPIO6[7] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT1 — Match output 1 of timer 3. I SD_CD — SD/MMC card detect input. I; PU - R — Function reserved. I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. - R — Function reserved. I ENET_RX_ER — Ethernet receive error (MII interface). I/O GPIO6[8] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT2 — Match output 2 of timer 3. O SD_POW — SD/MMC power monitor output. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 38 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_11 - L5 - [3] [3] Type M5 Description [2] TFBGA100 PC_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. I U1_DSR — Data Set Ready input for UART 1. - R — Function reserved. I/O GPIO6[9] — General purpose digital input/output pin. - R — Function reserved. O T3_MAT3 — Match output 3 of timer 3. I/O SD_CMD — SD/MMC command signal. I; PU - PC_13 L6 M1 LPC43S70 Product data sheet - - [3] [3] R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI data line direction. I U1_DCD — Data Carrier Detect input for UART 1. - R — Function reserved. I/O GPIO6[10] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O PC_12 R — Function reserved. SD_DAT4 — SD/MMC data bus line 4. I; PU - R — Function reserved. - R — Function reserved. O U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. - R — Function reserved. I/O GPIO6[11] — General purpose digital input/output pin. I/O SGPIO11 — General purpose digital input/output pin. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SD_DAT5 — SD/MMC data bus line 5. I; PU - R — Function reserved. - R — Function reserved. O U1_TXD — Transmitter output for UART 1. - R — Function reserved. I/O GPIO6[12] — General purpose digital input/output pin. I/O SGPIO12 — General purpose digital input/output pin. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O SD_DAT6 — SD/MMC data bus line 6. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 39 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_0 PD_1 PD_2 - N2 P1 R1 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type N1 Description [2] TFBGA100 PC_14 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. I U1_RXD — Receiver input for UART 1. - R — Function reserved. I/O GPIO6[13] — General purpose digital input/output pin. I/O SGPIO13 — General purpose digital input/output pin. O ENET_TX_ER — Ethernet Transmit Error (MII interface). I/O SD_DAT7 — SD/MMC data bus line 7. I; PU - R — Function reserved. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. O EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices. - R — Function reserved. I/O GPIO6[14] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO4 — General purpose digital input/output pin. I; PU - R — Function reserved. - R — Function reserved. O EMC_CKEOUT2 — SDRAM clock enable 2. - R — Function reserved. I/O GPIO6[15] — General purpose digital input/output pin. O SD_POW — SD/MMC power monitor output. - R — Function reserved. I/O SGPIO5 — General purpose digital input/output pin. I; PU - R — Function reserved. O CTOUT_7 — SCT output 7. Match output 3 of timer 1. I/O EMC_D16 — External memory data line 16. - R — Function reserved. I/O GPIO6[16] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO6 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 40 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_4 PD_5 PD_6 - T2 P6 R6 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type P4 Description [2] TFBGA100 PD_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. O CTOUT_6 — SCT output 7. Match output 2 of timer 1. I/O EMC_D17 — External memory data line 17. - R — Function reserved. I/O GPIO6[17] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO7 — General purpose digital input/output pin. I; PU - R — Function reserved. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. I/O EMC_D18 — External memory data line 18. - R — Function reserved. I/O GPIO6[18] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO8 — General purpose digital input/output pin. I; PU - R — Function reserved. O CTOUT_9 — SCT output 9. Match output 1 of timer 2. I/O EMC_D19 — External memory data line 19. - R — Function reserved. I/O GPIO6[19] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO9 — General purpose digital input/output pin. I; PU - R — Function reserved. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. I/O EMC_D20 — External memory data line 20. - R — Function reserved. I/O GPIO6[20] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO10 — General purpose digital input/output pin. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 41 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_8 PD_9 PD_10 - P8 T11 P11 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type T6 Description [2] TFBGA100 PD_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. I/O EMC_D21 — External memory data line 21. - R — Function reserved. I/O GPIO6[21] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO11 — General purpose digital input/output pin. I; PU - R — Function reserved. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. I/O EMC_D22 — External memory data line 22. - R — Function reserved. I/O GPIO6[22] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO12 — General purpose digital input/output pin. I; PU - R — Function reserved. O CTOUT_13 — SCT output 13. Match output 1 of timer 3. I/O EMC_D23 — External memory data line 23. - R — Function reserved. I/O GPIO6[23] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. I/O SGPIO13 — General purpose digital input/output pin. I; PU - R — Function reserved. I CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. O EMC_BLS3 — LOW active Byte Lane select signal 3. - R — Function reserved. I/O GPIO6[24] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 42 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_12 PD_13 PD_14 - N11 T14 R13 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type N9 Description [2] TFBGA100 PD_11 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. O EMC_CS3 — LOW active Chip Select 3 signal. - R — Function reserved. I/O GPIO6[25] — General purpose digital input/output pin. I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. - R — Function reserved. I; PU - R — Function reserved. - R — Function reserved. O EMC_CS2 — LOW active Chip Select 2 signal. - R — Function reserved. I/O GPIO6[26] — General purpose digital input/output pin. - R — Function reserved. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. - R — Function reserved. I; PU - R — Function reserved. I CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. O EMC_BLS2 — LOW active Byte Lane select signal 2. - R — Function reserved. I/O GPIO6[27] — General purpose digital input/output pin. - R — Function reserved. O CTOUT_13 — SCT output 13. Match output 1 of timer 3. - R — Function reserved. I; PU - R — Function reserved. - R — Function reserved. O EMC_DYCS2 — SDRAM chip select 2. - R — Function reserved. I/O GPIO6[28] — General purpose digital input/output pin. - R — Function reserved. O CTOUT_11 — SCT output 11. Match output 3 of timer 2. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 43 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_16 PE_0 PE_1 - R14 P14 N14 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type T15 Description [2] TFBGA100 PD_15 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. I/O EMC_A17 — External memory address line 17. - R — Function reserved. I/O GPIO6[29] — General purpose digital input/output pin. I SD_WP — SD/MMC card write protect input. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. - R — Function reserved. I; PU - R — Function reserved. - R — Function reserved. I/O EMC_A16 — External memory address line 16. - R — Function reserved. I/O GPIO6[30] — General purpose digital input/output pin. O SD_VOLT2 — SD/MMC bus voltage select output 2. O CTOUT_12 — SCT output 12. Match output 0 of timer 3. - R — Function reserved. I; PU - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O EMC_A18 — External memory address line 18. I/O GPIO7[0] — General purpose digital input/output pin. O CAN1_TD — CAN1 transmitter output. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O EMC_A19 — External memory address line 19. I/O GPIO7[1] — General purpose digital input/output pin. I CAN1_RD — CAN1 receiver input. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 44 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_3 PE_4 PE_5 - K12 K13 N16 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type M14 Description [2] TFBGA100 PE_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I ADCTRIG0 — ADC trigger input 0. I CAN0_RD — CAN receiver input. - R — Function reserved. I/O EMC_A20 — External memory address line 20. I/O GPIO7[2] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CAN0_TD — CAN transmitter output. I ADCTRIG1 — ADC trigger input 1. I/O EMC_A21 — External memory address line 21. I/O GPIO7[3] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. I NMI — External interrupt input to NMI. - R — Function reserved. I/O EMC_A22 — External memory address line 22. I/O GPIO7[4] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_3 — SCT output 3. Match output 3 of timer 0. O U1_RTS — Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I/O EMC_D24 — External memory data line 24. I/O GPIO7[5] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 45 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_7 PE_8 PE_9 - F15 F14 E16 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type M16 Description [2] TFBGA100 PE_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. I U1_RI — Ring Indicator input for UART 1. I/O EMC_D25 — External memory data line 25. I/O GPIO7[6] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_5 — SCT output 5. Match output 1 of timer 1. I U1_CTS — Clear to Send input for UART1. I/O EMC_D26 — External memory data line 26. I/O GPIO7[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_4 — SCT output 4. Match output 0 of timer 0. I U1_DSR — Data Set Ready input for UART 1. I/O EMC_D27 — External memory data line 27. I/O GPIO7[8] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. I U1_DCD — Data Carrier Detect input for UART 1. I/O EMC_D28 — External memory data line 28. I/O GPIO7[9] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 46 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_11 PE_12 PE_13 - D16 D15 G14 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type E14 Description [2] TFBGA100 PE_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. O U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. I/O EMC_D29 — External memory data line 29. I/O GPIO7[10] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_12 — SCT output 12. Match output 0 of timer 3. O U1_TXD — Transmitter output for UART 1. I/O EMC_D30 — External memory data line 30. I/O GPIO7[11] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_11 — SCT output 11. Match output 3 of timer 2. I U1_RXD — Receiver input for UART 1. I/O EMC_D31 — External memory data line 31. I/O GPIO7[12] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. I/O I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). O EMC_DQMOUT3 — Data mask 3 used with SDRAM and static devices. I/O GPIO7[13] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 47 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_15 PF_0 PF_1 - E13 D12 E11 LPC43S70 Product data sheet - - - [3] [3] [3] [3] Type C15 Description [2] TFBGA100 PE_14 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. - R — Function reserved. O EMC_DYCS3 — SDRAM chip select 3. I/O GPIO7[14] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I; PU - R — Function reserved. O; PU O CTOUT_0 — SCT output 0. Match output 0 of timer 0. I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). O EMC_CKEOUT3 — SDRAM clock enable 3. I/O GPIO7[15] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. I/O SSP0_SCK — Serial clock for SSP0. I GP_CLKIN — General purpose clock input to the CGU. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O I2S1_TX_MCLK — I2S1 transmit master clock. I; PU - R — Function reserved. - R — Function reserved. I/O SSP0_SSEL — Slave Select for SSP0. - R — Function reserved. I/O GPIO7[16] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO0 — General purpose digital input/output pin. - R — Function reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 48 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PF_3 PF_4 PF_5 - E10 D10 E9 LPC43S70 Product data sheet - H4 - [3] [3] [3] [6] Type D11 Description [2] TFBGA100 PF_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. O U3_TXD — Transmitter output for USART3. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved. I/O GPIO7[17] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO1 — General purpose digital input/output pin. - R — Function reserved. I; PU - R — Function reserved. O; PU I U3_RXD — Receiver input for USART3. I/O SSP0_MOSI — Master Out Slave in for SSP0. - R — Function reserved. I/O GPIO7[18] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO2 — General purpose digital input/output pin. - R — Function reserved. I/O SSP1_SCK — Serial clock for SSP1. I GP_CLKIN — General purpose clock input to the CGU. O TRACECLK — Trace clock. - R — Function reserved. - R — Function reserved. - R — Function reserved. O I2S0_TX_MCLK — I2S transmit master clock. I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I; PU - R — Function reserved. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. I/O SSP1_SSEL — Slave Select for SSP1. O TRACEDATA[0] — Trace data, bit 0. I/O GPIO7[19] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO4 — General purpose digital input/output pin. - R — Function reserved. AI ADC1_4 — ADC1, input channel 4. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 49 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PF_7 PF_8 - B7 E6 - - [6] [6] [6] [13] LPC43S70 Product data sheet Type E7 Description [2] TFBGA100 PF_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1. O TRACEDATA[1] — Trace data, bit 1. I/O GPIO7[20] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO5 — General purpose digital input/output pin. I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. AI ADC1_3 — ADC1, input channel 3. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU - R — Function reserved. I/O U3_BAUD — Baud pin for USART3. I/O SSP1_MOSI — Master Out Slave in for SSP1. O TRACEDATA[2] — Trace data, bit 2. I/O GPIO7[21] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO6 — General purpose digital input/output pin. I/O I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. AI/ O ADC1_7 — ADC1, input channel 7 or band gap output. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU - R — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. O TRACEDATA[3] — Trace data, bit 3. I/O GPIO7[22] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO7 — General purpose digital input/output pin. - R — Function reserved. AI ADC0_2 — ADC0, input channel 2. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 50 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [6] [13] PF_10 A3 - [6] [13] PF_11 A2 - [6] [13] LPC43S70 Product data sheet Type D6 Description [2] TFBGA100 PF_9 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. O CTOUT_1 — SCT output 1. Match output 1 of timer 0. - R — Function reserved. I/O GPIO7[23] — General purpose digital input/output pin. - R — Function reserved. I/O SGPIO3 — General purpose digital input/output pin. - R — Function reserved. AI ADC1_2 — ADC1, input channel 2. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU - R — Function reserved. O U0_TXD — Transmitter output for USART0. - R — Function reserved. - R — Function reserved. I/O GPIO7[24] — General purpose digital input/output pin. - R — Function reserved. I SD_WP — SD/MMC card write protect input. - R — Function reserved. AI ADC0_5 — ADC0, input channel 5. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. I; PU - R — Function reserved. I U0_RXD — Receiver input for USART0. - R — Function reserved. - R — Function reserved. I/O GPIO7[25] — General purpose digital input/output pin. - R — Function reserved. O SD_VOLT2 — SD/MMC bus voltage select output 2. - R — Function reserved. AI ADC1_5 — ADC1, input channel 5. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 51 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller K3 Type TFBGA100 N5 Description [2] LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Clock pins CLK0 CLK1 CLK2 CLK3 T10 D14 P12 - K6 - [5] [5] [5] [5] O; PU O; PU O; PU O; PU O EMC_CLK0 — SDRAM clock 0. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. I/O SD_CLK — SD/MMC card clock. O EMC_CLK01 — SDRAM clock 0 and clock 1 combined. I/O SSP1_SCK — Serial clock for SSP1. I ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). O EMC_CLK1 — SDRAM clock 1. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CGU_OUT0 — CGU spare clock output 0. - R — Function reserved. O I2S1_TX_MCLK — I2S1 transmit master clock. O EMC_CLK3 — SDRAM clock 3. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. I/O SD_CLK — SD/MMC card clock. O EMC_CLK23 — SDRAM clock 2 and clock 3 combined. O I2S0_TX_MCLK — I2S transmit master clock. I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O EMC_CLK2 — SDRAM clock 2. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CGU_OUT1 — CGU spare clock output 1. - R — Function reserved. I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. Debug pins LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 52 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller A6 [3] I Type L4 Description [2] TFBGA100 DBGEN LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I JTAG interface control signal. Also used for boundary scan. To use the part in functional mode, connect this pin in one of the following ways: • Leave DBGEN open. The DBGEN pin is pulled up internally by a 50 kΩ resistor. • • Tie DBGEN to VDDIO. Pull DBGEN up to VDDIO with an external pull-up resistor. TCK/SWDCLK J5 H2 [3] TRST M4 B4 [3] I; PU I Test Reset for JTAG interface. TMS/SWDIO K6 C4 [3] I; PU I Test Mode Select for JTAG interface (default) or SW debug data input/output. TDO/SWO K5 H3 [3] O TDI J4 G3 [3] I; PU I Test Data In for JTAG interface. F2 E1 [7] - USB0 bidirectional D+ line. - I/O USB0 bidirectional D line. - I/O VBUS pin (power on USB cable). This pin includes an internal pull-down resistor of 64 k (typical)  16 k. I Indicates to the transceiver whether connected as an A-device (USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this pin has an internal pull-up resistor. I; F I O Test Clock for JTAG interface (default) or Serial Wire (SW) clock. Test Data Out for JTAG interface (default) or SW trace output. USB0 pins USB0_DP USB0_DM G2 E2 [7] USB0_VBUS F1 E3 [7] I/O [8] USB0_ID H2 F1 [9] - USB0_RREF H1 F3 [9] - USB1_DP F12 E9 [10] - I/O USB1 bidirectional D+ line. USB1_DM G12 E10 [10] - I/O USB1 bidirectional D line. I2C0_SCL L15 D6 [11] I; F I/O I2C clock input/output. Open-drain output (for I2C-bus compliance). I2C0_SDA L16 E6 [11] I; F I/O I2C data input/output. Open-drain output (for I2C-bus compliance). 12.0 k (accuracy 1 %) on-board resistor to ground for current reference. USB1 pins I2C-bus pins Reset and wake-up pins RESET D9 B6 [12] I; IA I External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin does not have an internal pull-up. WAKEUP0 A9 A4 [12] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration > 45 ns wakes up the part. This pin does not have an internal pull-up. WAKEUP1 A10 - [12] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration > 45 ns wakes up the part. This pin does not have an internal pull-up. WAKEUP2 C9 - [12] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration > 45 ns wakes up the part. This pin does not have an internal pull-up. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 53 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [12] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration > 45 ns wakes up the part. This pin does not have an internal pull-up. E3 A2 [9] I; IA I 12-bit high-speed ADC input channel 0. Type D8 [2] TFBGA100 WAKEUP3 Description LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. ADC pins ADCHS_0 ADCHS_1 C3 A1 [9] I; IA I 12-bit high-speed ADC input channel 1. ADCHS_2 A4 B3 [9] I; IA I 12-bit high-speed ADC input channel 2. ADCHS_3 A5 - [9] I; IA I 12-bit high-speed ADC input channel 3. ADCHS_4 C6 - [9] I; IA I 12-bit high-speed ADC input channel 4. ADCHS_5 B3 - [9] I; IA I 12-bit high-speed ADC input channel 5. I; IA I/O 12-bit high-speed ADC reference voltage output or negative differential input. ADCHS_NEG B5 A3 [9] ADC0_7 C5 - [9] I; IA I 10-bit ADC0 input channel 7. RTC_ALARM A11 C3 [12] - O RTC controlled output. This pin has an internal pull-up. The reset state of this pin is LOW after POR. For all other types of reset, the reset state depends on the state of the RTC alarm interrupt. RTCX1 A8 A5 [9] - I Input to the RTC 32 kHz ultra-low power oscillator circuit. B5 [9] - O Output from the RTC 32 kHz ultra-low power oscillator circuit. RTC RTCX2 B8 Crystal oscillator pins XTAL1 D1 B1 [9] - I Input to the oscillator circuit and internal clock generator circuits. XTAL2 E1 C1 [9] - O Output from the oscillator amplifier. Power and ground pins USB0_VDDA 3V3_DRIVER F3 D1 - - Separate analog 3.3 V power supply for driver. USB0 _VDDA3V3 G3 D2 - - USB 3.3 V separate power supply voltage. USB0_VSSA _TERM H3 D3 - - Dedicated analog ground for clean reference for termination resistors. USB0_VSSA _REF G1 F2 - - Dedicated clean analog ground for generation of reference currents and voltages. VDDA B4 B2 - - Analog power supply and 10-bit ADC reference voltage. VBAT B10 C5 - - RTC power supply: 3.3 V on this pin supplies power to the RTC. VDDREG F10, F9, L8, L7 E4, E5, F4 - Main regulator power supply. Tie the VDDREG and VDDIO pins to a common power supply to ensure the same ramp-up time for both supply voltages. VPP E8 - - OTP programming voltage. LPC43S70 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 54 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller VDDIO D7, F10, E12, K5 F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 VDD - - VSS G9, H7, J10, J11, K8 VSSIO VSSA Type Description [2] Reset state LBGA256 Symbol TFBGA100 Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. - - I/O power supply. Tie the VDDREG and VDDIO pins to a common power supply to ensure the same ramp-up time for both supply voltages. - - - Ground. C4, D13, G6, G7, G8, H8, H9, J8, J9, K9, K10, M13, P7, P13 C8, D4, D5, G8, J3, J6 - - Ground. B2 C2 - - Analog ground. B9 - - - n.c. Power supply for main regulator, I/O, and OTP. Not connected [1] - = not pinned out. [2] I = input, O = output, AI/O analog input/output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDD(IO)); F = floating. Reset state reflects the pin state at reset without boot code operation. [3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength. [4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V) providing digital I/O functions with TTL levels, and hysteresis; high drive strength. [5] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V) providing high-speed digital I/O functions with TTL levels and hysteresis. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 55 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller [6] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP register. [7] 5 V tolerant transparent analog pad. [8] For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS = 0.2 V when it is no longer driven. [9] Transparent analog pad. Not 5 V tolerant. [10] Pad provides USB functions (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V). It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. [12] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis. [13] To minimize interference on the 12-bit ADC signal lines, do not configure the digital signal as output when using the 12-bit ADC. See Table 45. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 56 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC43S70 use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. An ARM Cortex-M0 coprocessor is included in the LPC43S70, capable of off-loading the main ARM Cortex-M4 application processor. Most peripheral interrupts are connected to both processors. The processors communicate with each other via an interprocessor communication protocol. 7.2 ARM Cortex-M4 processor The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated in the core. The processor includes a NVIC with up to 53 interrupts. 7.3 ARM Cortex-M0 processors The ARM Cortex-M0 processors are general purpose, 32-bit microprocessors, which offer high performance and very low power consumption. The ARM Cortex-M0 processor uses a 3-stage pipeline von Neumann architecture and a small but powerful instruction set providing high-end processing hardware. The processors each incorporate an NVIC with 32 interrupts. 7.3.1 ARM Cortex-M0 coprocessor The M0 coprocessor resides on the same AHB multi-layer matrix as the main Cortex-M0 core. The coprocessor can be used to off-load multiple tasks from the main Cortex-M4 processor. 7.3.2 ARM Cortex-M0 subsytem The Cortex-M0 subsystem can be used to manage the SGPIO and SPI peripherals on the M0 subsystem multilayer matrix but any other peripheral as well. The M0 subsystem is separated by a bridge from the main AHB matrix. The M0 subsystem AHB matrix has two SRAM blocks which allows to run the Cortex-M0 subsytem at full speed independently from the main matrix. One application of using the subsystem is to reduce power, for example when the main matrix runs at a very low speed and the M0 subsystem monitors activity and increases the main matrix speed when needed. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 57 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller One of the two SRAM blocks connected to the subsystem AHB matrix is typically used for code running on the M0 subsystem and the other SRAM block for data. This allows other bus masters to access the data SRAM without interrupting the M0 processor instruction fetches and thereby stalling the M0 subsystem. The M0 subsystem matrix runs at an asynchronous speed from the main matrix. This allows to operate the SGPIO at any desired frequency. The M0 subsystem can control the SGPIO in a deterministic way, without incurring latency that occurs when the M4 controls the SGPIO through a bridge. 7.4 Interprocessor communication The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on using shared SRAM as mailbox and one processor raising an interrupt on the other processor's NVIC, for example after it has delivered a new message in the mailbox. The receiving processor can reply by raising an interrupt on the sending processor's NVIC to acknowledge the message. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 58 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.5 AHB multilayer matrix TEST/DEBUG INTERFACE TEST/DEBUG INTERFACE ARM CORTEX-M4 ARM CORTEX-M0 System IDbus code code bus bus HIGH-SPEED PHY DMA 0 ETHERNET USB0 USB1 LCD SD/ MMC masters 1 slaves 64 kB ROM 128 kB LOCAL SRAM 72 kB LOCAL SRAM SPIFI SGPIO 32 kB AHB SRAM 16 kB + 16 kB AHB SRAM EXTERNAL MEMORY CONTROLLER AHB PERIPHERALS REGISTER INTERFACES APB, RTC DOMAIN PERIPHERALS AHB MULTILAYER MATRIX = master-slave connection Fig 4. 002aaf873 AHB multilayer matrix master and slave connections 7.6 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 59 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Each ARM Cortex-M0 coprocessor has its own NVIC with 32 vectored interrupts. Most peripheral interrupts are shared between the two Cortex-M0cores and the Cortex-M4 NVICs. 7.6.1 Features • ARM Cortex-M4 NVIC: – Controls system exceptions and peripheral interrupts. – Up to 53 vectored interrupts. – Eight programmable interrupt priority levels with hardware priority level masking. – Relocatable vector table. – Non-Maskable Interrupt (NMI). – Software interrupt generation. • ARM Cortex-M0 and ARM Cortex-M0 subsystem NVIC: – Control system exceptions and peripheral interrupts. – Up to 32 vectored interrupts. – Four programmable priority levels with hardware priority level masking. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.7 System Tick timer (SysTick) The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a dedicated SYSTICK exception, typically at 10 ms interval. Remark: The SysTick is not included in the ARM Cortex-M0 core. 7.8 Event router The event router combines various internal signals, interrupts, and the external interrupt pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down, and Deep power-down modes. Individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router. The event router can be battery powered. The following events if enabled in the event router can create a wake-up signal and/or an interrupt: • • • • • LPC43S70 Product data sheet External pins WAKEUP0/1/2/3 and RESET Alarm timer, RTC, WWDT, BOD interrupts C_CAN and QEI interrupts Ethernet, USB0, USB1 signals Selected outputs of combined timers (SCT and timer0/1/3) All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 60 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.9 Global Input Multiplexer Array (GIMA) The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers, event router, or the ADCs. 7.9.1 Features • • • • • Single selection of a source. Signal inversion. Can capture a pulse if the input event source is faster than the target clock. Synchronization of input event and target clock. Single-cycle pulse generation for target. 7.10 On-chip static RAM The LPC43S70 support 200 kB local SRAM and an additional 64 kB AHB SRAM with separate bus master access for higher throughput and individual power control for low power operation. See Section 7.22.9.1 “Memory retention in Power-down modes”. 7.11 In-System Programming (ISP) In-System programming (ISP) is programming or reprogramming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. This can be done when the part resides in the end-user board. ISP allows to load data into on-chip SRAM and execute code from on-chip SRAM. 7.12 Boot ROM The internal ROM memory is used to store the boot code of the LPC43S70. After a reset, the ARM processor will start its code execution from this memory. The boot ROM memory includes the following features: • ROM memory size is 64 kB. • Supports booting from UART interfaces and external static memory such as NOR flash, SPI flash, quad SPI flash. • Includes APIs for OTP and AES programming. • Includes a flexible USB device stack that supports Human Interface Device (HID), Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers. Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 61 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 4. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC BOOT_SRC BOOT_SRC bit 3 bit 2 bit 1 BOOT_SRC Description bit 0 Pin state 0 0 0 0 Boot source is defined by the reset state of P1_1, P1_2, P2_8 pins, and P2_9. See Table 5. USART0 0 0 0 1 Boot from device connected to USART0 using pins P2_0 and P2_1. SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI interface using pins P3_3 to P3_8. EMC 8-bit 0 0 1 1 Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. USB0 0 1 1 0 Boot from USB0. USB1 0 1 1 1 Boot from USB1. SPI (SSP) 1 0 0 0 Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7 (function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]. USART3 1 0 0 1 Boot from device connected to USART3 using pins P2_3 and P2_4. [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Remark: Pin functions for SPIFI and SSP0 boot are different. Table 5. Boot mode when OPT BOOT_SRC bits are zero Boot mode Pins Description P2_9 P2_8 P1_2 P1_1 USART0 LOW LOW LOW LOW Boot from device connected to USART0 using pins P2_0 and P2_1. SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI interface on P3_3 to P3_8[1]. EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. USB0 LOW HIGH LOW HIGH Boot from USB0 USB1 LOW HIGH HIGH LOW Boot from USB1. SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7 (function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]. USART3 HIGH LOW LOW LOW Boot from device connected to USART3 using pins P2_3 and P2_4. [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 62 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Remark: Pin functions for SPIFI and SSP0 boot are different. 7.13 Memory mapping The memory map shown in Figure 5 and Figure 6 is global to both the Cortex-M4 and the Cortex-M0 processors and all SRAM is shared between both processors. Each processor uses its own ARM private bus memory map for the NVIC and other system functions. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 63 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC43S70 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus reserved SPIFI data 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved peripheral bit band alias region reserved 0xE000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 SGPIO SPI reserved high-speed GPIO reserved reserved 0x2000 0000 0x1F00 0000 0x1E00 0000 0x1D00 0000 0x1C00 0000 12-bit ADC (ADCHS) 16 MB static external memory CS3 APB peripherals #3 16 MB static external memory CS2 reserved 16 MB static external memory CS1 APB peripherals #2 16 MB static external memory CS0 reserved APB peripherals #1 reserved reserved APB peripherals #0 0x1800 0000 0x1400 0000 clocking/reset peripherals 16 kB M0 SUBSYSTEM SRAM RTC domain peripherals SPIFI data reserved 256 MB dynamic external memory DYCS1 64 kB ROM 128 MB dynamic external memory DYCS0 reserved 32 kB local SRAM 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4005 0000 0x4004 0000 0x4000 0000 0x3000 0000 0x2800 0000 0x2400 0000 32 MB AHB SRAM bit banding 0x2200 0000 32 kB + 8 kB local SRAM reserved reserved 16 kB AHB SRAM 32 kB local SRAM 16 kB AHB SRAM 0x2001 0000 0x1008 0000 0x1001 8000 0x400F 2000 reserved 0x1008 A000 0x1002 0000 0x400F 4000 0x4001 2000 AHB peripherals 1 GB reserved 0x1009 2000 0x400F 8000 0x4006 0000 2 kB M0 SUBSYSTEM SRAM 0x1041 0000 0x1040 0000 0x4010 0000 reserved 0x1800 4800 0x1800 4000 0x4010 1000 16 kB AHB SRAM 96 kB local SRAM 16 kB AHB SRAM 0x1000 0000 local SRAM/ external static memory banks 0 GB 256 MB shadow area 0x2000 C000 0x2000 8000 0x2000 4000 0x2000 0000 0x1000 0000 0x0000 0000 aaa-016397 Fig 5. LPC43S70 Memory mapping (overview) LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 64 of 157 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 0x400E 5000 reserved 0x400E 4000 10-bit ADC1 0x400E 3000 10-bit ADC0 0x400E 2000 C_CAN0 0x400E 1000 DAC 0x400E 0000 0x400C 8000 I2C1 0x400C 7000 0x400C 6000 QEI Rev. 1.2 — 15 March 2016 timer2 0x400C 2000 USART3 0x400C 1000 USART2 0x400C 0000 0x400B 0000 RI timer APB2 peripherals reserved reserved 12-bit ADC (ADCHS) APB3 peripherals reserved C_CAN1 APB2 peripherals reserved APB1 peripherals reserved motor control PWM APB0 peripherals GPIO GROUP1 interrupt reserved GPIO GROUP0 interrupt GPIO interrupts clocking/reset peripherals SCU 0x4008 5000 timer1 0x4008 4000 timer0 0x4008 3000 SSP0 0x4008 2000 UART1 w/ modem 0x4008 1000 USART0 0x4008 0000 WWDT RTC domain peripherals APB0 peripherals 0x4010 1000 RGU 0x4005 3000 CCU2 0x4005 2000 CCU1 0x4005 1000 CGU 0x4005 0000 0x4010 0000 reserved 0x400F 4000 0x4004 7000 RTC 0x4004 6000 0x400F 2000 OTP controller 0x4004 5000 event router 0x4004 4000 CREG 0x4004 3000 0x400F 1000 0x400F 0000 RTC domain peripherals 0x400E 0000 power mode control 0x4004 2000 backup registers 0x4004 1000 alarm timer 0x4004 0000 0x400A 0000 ethernet 0x4001 2000 0x4001 0000 0x4009 0000 reserved 0x4000 9000 0x4008 0000 LCD 0x4000 8000 USB1 0x4000 7000 USB0 0x4000 6000 EMC 0x4000 5000 SD/MMC 0x4000 4000 SPIFI 0x4000 3000 0x400D 0000 0x400C 0000 0x400B 0000 0x4006 0000 0x4005 0000 0x4004 0000 reserved 0x4001 2000 AHB peripherals 0x4000 0000 SRAM memories external memory banks AHB peripherals DMA 0x4000 2000 reserved 0x4000 1000 SCT 0x4000 0000 0x0000 0000 65 of 157 © NXP B.V. 2016. All rights reserved. aaa-016398 Fig 6. LPC43S70 Memory mapping (peripherals) LPC43S70 0x4008 6000 0x4010 2000 clocking reset control peripherals 0x400F 8000 high-speed GPIO APB1 peripherals 0x4200 0000 0x4006 0000 0x4005 4000 reserved reserved I2S1 I2S0 I2C0 0x4400 0000 reserved 32-bit ARM Cortex-M4/M0 microcontroller All information provided in this document is subject to legal disclaimers. 0x400C 3000 0x4008 A000 0x4008 9000 0x4008 8000 0x4008 7000 peripheral bit band alias region SPI SSP1 0x400A 0000 0x6000 0000 reserved SGPIO timer3 0x400A 1000 external memories and ARM private bus GIMA 0x400C 4000 0x400A 4000 0x400A 3000 0x400A 2000 0xFFFF FFFF APB3 peripherals reserved 0x400C 5000 0x400A 5000 NXP Semiconductors LPC43S70 Product data sheet LPC43S70 0x400F 0000 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.14 One-Time Programmable (OTP) memory The OTP provides 64 bit of memory for general-purpose use. 256 bit of OTP memory are available to store two AES keys in two memory banks. One bank is encrypted. 7.15 General Purpose I/O (GPIO) The LPC43S70 provide 8 GPIO ports with up to 31 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. All GPIO pins default to inputs with pull-up resistors enabled on reset. 7.15.1 Features • Accelerated GPIO functions: – GPIO registers are located on the AHB so that the fastest possible I/O timing can be achieved. – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte and half-word addressable. – Entire port value can be written in one instruction. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request (GPIO interrupts). • Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO group0 and group1 interrupts). 7.16 Configurable digital peripherals 7.16.1 State Configurable Timer (SCT) subsystem The SCT allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCT are shared with the capture and match inputs/outputs of the 32-bit general purpose counter/timers. The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: • State variable • Limit, halt, stop, and start conditions • Values of Match/Capture registers, plus reload or capture control values LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 66 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller In the two-counter case, the following operational elements are global to the SCT, but the last three can use match conditions from either counter: • • • • • 7.16.1.1 Clock selection Inputs Events Outputs Interrupts Features • • • • • • • • Two 16-bit counters or one 32-bit counter. Counter(s) clocked by bus clock or selected input. Up counter(s) or up-down counter(s). State variable allows sequencing across multiple counter cycles. Event combines input or output condition and/or counter match in a specified state. Events control outputs and interrupts. Selected event(s) can limit, halt, start, or stop a counter. Supports: – 8 inputs (one input connected internally) – 16 outputs – 16 match/capture registers – 16 events – 32 states 7.16.2 Serial GPIO (SGPIO) The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate serial stream processing. 7.16.2.1 Features • Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to serial data conversion. • 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value from a pin or an output value to a pin with every cycle of a shift clock. • • • • Each slice is double-buffered. Interrupt is generated on a full FIFO, shift clock, or pattern match. Slices can be concatenated to increase buffer size. Each slice has a 32-bit pattern match filter. 7.17 AHB peripherals 7.17.1 AES decryption/encryption The hardware AES engine can decode and encode data using the AES algorithm in conjunction with a 128-bit key. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 67 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller The AES encryption and decryption features are accessible through the ROM-based AES API. 7.17.1.1 Features • On-chip API support for AES encryption and decryption. • Two 128-bit OTP memories for AES key storage and customer use.One OTP memory bank is encrypted. • • • • • • Random number generator (RNG) accessible through AES API. Unique ID for each device. Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI). Secure storage of encryption and decryption keys. Support for CMAC hash calculation to authenticate encrypted data. AES engine supports the following modes: – Electronic Code Block (ECB) mode (encryption and decryption) with 128-bit key. – Cypher Block Chaining (CBC) mode (encryption and decryption) with 128-bit key. • The AES engine is compliant with the FIPS (Federal Information Processing Standard) Publication 197, Advanced Encryption Standard (AES). • Random Number Generator (RNG) is supported by the AES API and passes the following tests: – diehard – FIPS_140-1 – NIST • Data is processed in little endian mode. This means that the first byte read from flash is integrated into the AES codeword as least significant byte. The 16th byte read from flash is the most significant byte of the first AES codeword. • AES peak engine performance of 0.5 byte/clock cycle. • DMA transfers supported through the GPDMA. 7.17.2 General Purpose DMA (GPDMA) The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.17.2.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 68 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • Two AHB bus masters for transferring data. These interfaces transfer data when a DMA request goes active. Master 1 can access memories and peripherals (except SGPIO and SPI). Master 0 can access memories on the main AHB matrix and peripherals and memories on the M0SUB bus. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.17.3 SPI Flash Interface (SPIFI) The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM Cortex-M4 processor with little performance penalty compared to parallel flash devices with higher pin count. After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Erasure and programming are handled by simple sequences of commands. Many serial flash devices use a half-duplex command-driven SPI protocol for device setup and initialization and then move to a half-duplex, command-driven 4-bit protocol for normal operation. Different serial flash vendors and devices accept or require different commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.17.3.1 Features • • • • • LPC43S70 Product data sheet Interfaces to serial flash memory in the main memory map. Supports classic and 4-bit bidirectional serial protocols. Half-duplex protocol compatible with various vendors and devices. Data rates of up to 52 MB per second. Supports DMA access. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 69 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.17.4 SD/MMC card interface The SD/MMC card interface supports the following modes to control: • • • • Secure Digital memory (SD version 3.0) Secure Digital I/O (SDIO version 2.0) Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1) MultiMedia Cards (MMC version 4.4) 7.17.5 External Memory Controller (EMC) The LPC43S70 EMC is a Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. 7.17.5.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • • • • • Low transaction latency. Read and write buffers to reduce latency and to improve performance. 8/16/32 data and 24 address lines wide static memory support. 16 bit and 32 bit wide chip select SDRAM memory support. Static memory features include: – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. • SDRAM clock can run at full or half the Cortex-M4 core frequency. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.17.6 High-speed USB Host/Device/OTG interface (USB0) The USB OTG module allows the LPC43S70 to connect directly to a USB Host such as a PC (in device mode) or to a USB Device in host mode. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 70 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.17.6.1 Features • • • • • • • • Contains UTMI+ compliant transceiver (PHY). Complies with Universal Serial Bus specification 2.0. Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals. Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. • Supports interrupts. • This module has its own, integrated DMA engine. • USB interface electrical test software included in ROM USB stack. 7.17.7 High-speed USB Host/Device interface with ULPI (USB1) The USB1 interface can operate as a full-speed USB Host/Device interface or can connect to an external ULPI PHY for High-speed operation. 7.17.7.1 Features • • • • Complies with Universal Serial Bus specification 2.0. • • • • Supports all full-speed USB-compliant peripherals. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals if connected to external ULPI PHY. Supports interrupts. This module has its own, integrated DMA engine. USB interface electrical test software included in ROM USB stack. 7.17.8 LCD controller Remark: The LCD controller is available on the LPC4370FET256 parts. See Table 2. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 71 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.17.8.1 Features • • • • AHB master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320  200, 320  240, 640  200, 640  240, 640  480, 800  600, and 1024  768. • • • • • • • • • • • • Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized for color STN and TFT. 24 bpp true-color non-palettized for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.17.9 Ethernet 7.17.9.1 Features • • • • 10/100 Mbit/s DMA support Power management remote wake-up frame and magic packet detection Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation. – Back-pressure support for half-duplex operation. – Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation. • Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE 1588-2008 v2). LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 72 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.18 Digital serial peripherals 7.18.1 UART1 The LPC43S70 contain one UART with standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.18.1.1 Features • • • • • Maximum UART data bit rate of 8 MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • Equipped with standard modem interface signals. This module also provides full support for hardware flow control. • Support for RS-485/9-bit/EIA-485 mode (UART1). • DMA support. 7.18.2 USART0/2/3 The LPC43S70 contain three USARTs. In addition to standard transmit and receive data lines, the USARTs support a synchronous mode. The USARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.18.2.1 Features • • • • • Maximum UART data bit rate of 8 MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • • • • LPC43S70 Product data sheet Support for RS-485/9-bit/EIA-485 mode. USART3 includes an IrDA mode to support infrared communication. All USARTs have DMA support. Support for synchronous mode at a data bit rate of up to 8 Mbit/s. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 73 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Smart card mode conforming to ISO7816 specification 7.18.3 SPI serial I/O controller The LPC43S70 contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.18.3.1 Features • • • • • • Maximum SPI data bit rate 25 MHz in master and slave modes. Compliant with SPI specification Synchronous, serial, full duplex communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate 8 bits to 16 bits per transfer 7.18.4 SSP serial I/O controller Remark: The LPC43S70 contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.18.4.1 Features • Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s (master) and 15 Mbit/s (slave). • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA 7.18.5 I2C-bus interface Remark: The LPC43S70 each contain two I2C-bus interfaces. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 74 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.18.5.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • • • • • • I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.18.6 I2S interface Remark: The LPC43S70 each contain two I2S-bus interfaces. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.18.6.1 Features • Both I2S interfaces have separate input/output channels, each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96, 192) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests for each I2S interface, controlled by programmable buffer levels. These are connected to the GPDMA block. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 75 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. 7.18.7 C_CAN Remark: The LPC43S70 each contain two C_CAN controllers. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge. See Figure 1. Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of reliability. 7.18.7.1 Features • • • • • • • Conforms to protocol version 2.0 parts A and B. Supports bit rate of up to 1 Mbit/s. Supports 32 Message Objects. Each Message Object has its own identifier mask. Provides programmable FIFO mode (concatenation of Message Objects). Provides maskable interrupts. Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. • Provides programmable loop-back mode for self-test operation. 7.19 Counter/timers and motor control 7.19.1 General purpose 32-bit timers/external event counters The LPC43S70 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.19.1.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 76 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 7.19.2 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 7.19.3 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.19.3.1 Features • • • • • • • • • • Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with “less than” interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 77 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.19.4 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.19.4.1 Features • 32-bit counter. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 7.19.5 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.19.5.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. 7.20 Analog peripherals 7.20.1 12-bit high-speed Analog-to-Digital Converter (ADCHS) 7.20.1.1 Features • • • • • • LPC43S70 Product data sheet 12-bit high-speed ADC. Six single-sided input channels or one differential input channel. Descriptor based conversion sequence for single or multiple inputs. Integrated 14-bit timer. Automatic high/low threshold detection. Power-down mode. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 78 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • • • • Measurement range of 0 V to 1.2 V. 12-bit conversion rate of 80 MSamples/s. Conversion on transition on input pin or various internal signals. Output FIFO with DMA support. 7.20.2 10-bit Analog-to-Digital Converter (ADC0/1) 7.20.2.1 Features • • • • • • • 10-bit successive approximation analog to digital converter. Input multiplexing among 8 pins per ADC for a total of 16 individual channels. Power-down mode. Measurement range 0 to VDDA. Sampling frequency up to 400 kSamples/s. Burst conversion mode for single or multiple inputs. Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer outputs 8 or 15, or the PWM output MCOA2. • Individual result registers for each A/D channel to reduce interrupt overhead. • DMA support. 7.20.3 Digital-to-Analog Converter (DAC) 7.20.3.1 Features • • • • 10-bit resolution Monotonic by design (resistor string architecture) Controllable conversion speed Low power consumption 7.21 Peripherals in the RTC power domain 7.21.1 RTC The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially reduced power modes. The RTC is clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference. The RTC is powered by its own power supply pin, VBAT. 7.21.1.1 Features • Measures the passage of time to maintain a calendar and clock. Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. • Ultra-low power design to support battery powered systems. Uses power from the CPU power supply when it is present. • Dedicated battery power supply pin. • RTC power supply is isolated from the rest of the chip. • Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 79 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Periodic interrupts can be generated from increments of any field of the time registers. • Alarm interrupt can be generated for a specific date/time. 7.21.2 Alarm timer The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled. The alarm timer is part of the RTC power domain and can be battery powered. 7.22 System control 7.22.1 Configuration registers (CREG) The following settings are controlled in the configuration register block: • • • • • • • BOD trip settings Oscillator output DMA-to-peripheral muxing Ethernet mode Memory mapping Timer/USART inputs Enabling the USB controllers In addition, the CREG block contains the part identification and part configuration information. 7.22.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. For pins that support a digital and analog function, the ADC function select registers in the SCU enable the analog function. A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are located on separate pads and are not controlled through the SCU. In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that select the pin interrupts are located in the SCU. 7.22.3 Clock Generation Unit (CGU) The Clock Generator Unit (CGU) generates several base clocks. The CGU outputs are unrelated in frequency and phase and can have different clock sources within the CGU. One CGU output is routed to the CLKOUT pins. Within each clock area there may be multiple branch clocks, which offers very flexible control for power-management purposes. All branch clocks are outputs of one of two Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 80 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.22.4 Internal RC oscillator (IRC) The IRC is used as the clock source for the WWDT and/or as the clock that drives the PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC43S70 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.22.5 PLL0USB (for USB0) PLL0 is a dedicated PLL for the USB0 High-speed controller. PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz. 7.22.6 PLL0AUDIO (for audio) The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This PLL accepts an input clock frequency derived from an external oscillator or internal IRC. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired output frequency. The output frequency can be set as a multiple of the sampling frequency fs to 32fs, 64fs, 128  fs, 256  fs, 384  fs, 512  fs and the sampling frequency fs can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other frequencies are possible as well. 7.22.7 System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.22.8 Reset Generation Unit (RGU) The RGU allows generation of independent reset signals for individual blocks and peripherals on the LPC43S70. 7.22.9 Power control The LPC43S70 feature several independent power domains to control power to the core and the peripherals (see Figure 7). The RTC and its associated peripherals (the alarm timer, the CREG block, the OTP controller, the back-up registers, and the event router) are located in the RTC power-domain which can be powered by a battery supply or the main regulator. A power selector switch ensures that the RTC block is always powered on. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 81 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC43Sxx VDDIO to I/O pads to cores VSS REGULATOR to memories, peripherals, oscillators, PLLs VDDREG MAIN POWER DOMAIN ULTRA LOW-POWER REGULATOR VBAT to RTC domain peripherals RESET/WAKE-UP CONTROL to RTC I/O pads (Vps) RESET WAKEUP0/1/2/3 BACKUP REGISTERS RTCX1 RTCX2 32 kHz OSCILLATOR REAL-TIME CLOCK ALARM ALWAYS-ON/RTC POWER DOMAIN DAC VDDA VSSA ADC ADC POWER DOMAIN OTP VPP OTP POWER DOMAIN USB0_VDDA3V_DRIVER USB0_VDDA3V3 USB0 USB0 POWER DOMAIN aaa-016399 Fig 7. Power domains 7.22.9.1 Memory retention in Power-down modes Table 6 shows which parts of the SRAM memory are preserved in Sleep mode and the various power-down modes. In addition, all FIFO memory contained in the peripheral blocks (USB0/1, LCD, CAN, Ethernet, USART0/2/3, UART) is retained in Sleep mode and Deep-sleep mode but not in Power-down mode and Deep-power-down mode. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 82 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 6. Memory retention Mode 128 kB local SRAM starting at 0x1000 0000 64 kB Local 8 kB local SRAM SRAM starting starting at at 0x1009 0000 0x1008 0000 16 + 2 kB M0 subsystem SRAM starting at location 0x1800 0000 64 kB AHB SRAM starting at 0x2000 0000 256 byte backup registers at 0x4004 1000 (RTC power domain) Sleep mode yes yes yes yes yes yes Deep-sleep mode yes yes yes yes yes yes Power-down mode no no yes no no yes Power-down mode no with M0SUB SRAM maintained no yes yes no yes Deep power-down no mode no no no no yes 7.22.9.2 Power Management Controller (PMC) The PMC controls the power to the cores, peripherals, and memories. The LPC43S70 support the following power modes in order from highest to lowest power consumption: 1. Active mode 2. Sleep mode 3. Power-down modes: a. Deep-sleep mode b. Power-down mode c. Deep power-down mode Active mode and sleep mode apply to the state of the core. In a multi-core system, any core can be in active or sleep mode independently of the other core. If the core is in Active mode, it is fully operational and can access peripherals and memories as configured by software. If the core is in Sleep mode, it receives no clocks, but peripherals and memories can remain running. Any core can enter sleep mode from active mode independently of the other cores and while the other cores remain in active mode or are in sleep mode. Power-down modes apply to the entire system. In the Power-down modes, all cores and all peripherals except for peripherals in the always-on power domain are shut down. Memories can remain powered for retaining memory contents as defined by the individual power-down mode. Any core in active mode can put the part into one of the three power down modes if the core is enabled to do so. If both the M4 core and the two M0 cores are enabled for power-down, then the system enters power-down only once all three cores have received a WFI or WFE instruction. Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. An interrupt is captured in the NVIC and an event is captured in the Event router. Both cores can wake up from sleep mode independently of each other. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 83 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down, is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer. When waking up from Deep power-down mode, the part resets and attempts to boot. After booting, the M4 core is in active mode and both M0 cores remain in the reset state until the reset is released by software. 7.23 Serial Wire Debug/JTAG Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four watch points. The ARM Cortex-M0 coprocessors support JTAG boundary scan only. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 84 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(REG)(3V3) regulator supply voltage (3.3 V) on pin VDDREG 0.5 3.6 V VDD(IO) input/output supply voltage on pin VDDIO 0.5 3.6 V VDDA(3V3) analog supply voltage (3.3 V) on pin VDDA 0.5 3.6 V VBAT battery supply voltage on pin VBAT 0.5 3.6 V Vprog(pf) polyfuse programming voltage on pin VPP 0.5 3.6 V VI input voltage only valid when the VDD(IO)  2.2 V 5 V tolerant I/O pins 0.5 5.5 V ADC/DAC pins and digital I/O pins configured for an analog function 0.5 VDDA(3V3) V USB0 pins USB0_DP; USB0_DM;USB0_VBUS 0.3 5.25 V USB0 pins USB0_ID; USB0_RREF 0.3 3.6 V USB1 pins USB1_DP and USB1_DM 0.3 5.25 V [2] IDD supply current per supply pin [3] - 100 mA ISS ground current per ground pin [3] - 100 mA Ilatch I/O latch-up current (0.5VDD(IO)) < VI < (1.5VDD(IO)); - 100 mA Tstg storage temperature 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins +2000 V Tj < 125 C [1] [4] [5] The following applies to the limiting values: a) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not guaranteed. The conditions for functional operation are specified in Table 10. [2] Including voltage on outputs in 3-state mode. [3] The peak current is limited to 25 times the corresponding maximum current. [4] Dependent on package type. [5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 85 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 8. Thermal characteristics VDD = 2.2 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Parameter Tj(max) maximum junction temperature Table 9. Symbol Conditions Min Typ Max Unit - - 125 C Thermal resistance value (BGA package) Parameter Conditions Thermal resistance in C/W ±15 % LBGA256 Rth(j-a) Rth(j-c) TFBGA100 thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 29 46 8-layer (4.5 in  3 in); still air 24 37 thermal resistance from junction to case 14 11 LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 86 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10. Static characteristics Table 10. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit 2.2 - 3.6 V 2.2 - 3.6 V Supply pins VDD(IO) input/output supply voltage VDD(REG)(3V3) regulator supply voltage (3.3 V) VDDA(3V3) analog supply voltage (3.3 V) [2] on pin VDDA 2.2 - 3.6 V on pins USB0_VDDA3V3_ DRIVER and USB0_VDDA3V3 3.0 3.3 3.6 V battery supply voltage [2] 2.2 - 3.6 V Vprog(pf) polyfuse programming voltage on pin VPP (for OTP) [3] 2.7 - 3.6 V Iprog(pf) polyfuse programming current on pin VPP; OTP programming time  1.6 ms - - 30 mA IDD(REG)(3V3) regulator supply current Active mode; M0 cores in (3.3 V) reset; code - 6.6 - mA 25.3 - mA VBAT while(1){} executed from RAM; all peripherals disabled; PLL1 enabled IDD(REG)(3V3) CCLK = 12 MHz [4] CCLK = 60 MHz [4] CCLK = 120 MHz [4] - 48.4 - mA CCLK = 180 MHz [4] - 72.0 - mA CCLK = 204 MHz [4] - 81.5 - mA [4][5] - 5.0 - mA deep-sleep mode [4] - 30 - A power-down mode [4] - 15 - A power-down mode with M0SUB SRAM retained [4] - - A regulator supply current after WFE/WFI instruction (3.3 V) executed from RAM; all peripherals disabled;M0 cores in reset sleep mode [4][6] - 0.03 - A deep power-down mode; VBAT floating [4] - 2 - A active mode; VBAT = 3.2 V; VDD(REG)(3V3) = 3.6 V. [7] - 0 - nA deep power-down mode IBAT LPC43S70 Product data sheet battery supply current 20 All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 87 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IBAT Parameter battery supply current Conditions VDD(REG)(3V3) = 3.3 V; VBAT = 3.6 V deep-sleep mode IDD(IO) I/O supply current power-down mode [8] deep power-down mode [8] deep sleep mode IDDA Analog supply current on pin VDDA; Typ[1] Max Unit - 2 - A - 2 - A - 2 - A - 1 - A - 1 - A [9] - 0.05 - A [11] - 0.4 - power-down mode deep power-down mode Min [8] A deep sleep mode power-down mode [11] - 0.4 - deep power-down mode [11] - 0.007 - A A RESET,RTC_ALARM, WAKEUPn pins VIH HIGH-level input voltage [10] 0.8  (Vps  0.35) 5.5 VIL LOW-level input voltage [10] 0 0.3  (Vps  V 0.1) Vhys hysteresis voltage [10] 0.05  (Vps  0.35) - V Vo output voltage [10] - Vps - 0.2 - V - - 5.2 pF - V Standard I/O pins - normal drive strength CI input capacitance ILL LOW-level leakage current VI = 0 V; on-chip pull-up resistor disabled - 3 - nA ILH HIGH-level leakage current VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V - - 20 nA IOZ OFF-state output current VO = 0 V to VDD(IO); on-chip pull-up/down resistors disabled; absolute value - 3 - nA VI input voltage pin configured to provide a digital function; 0 - 5.5 V 0 - 3.6 V 0 - VDD(IO) V VDD(IO)  2.2 V VDD(IO) = 0 V VO output voltage VIH HIGH-level input voltage 0.7  VDD(IO) - 5.5 V VIL LOW-level input voltage 0 - 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V LPC43S70 Product data sheet output active All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 88 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOH HIGH-level output voltage IOH = 6 mA VDD(IO)  0.4 - - V VOL LOW-level output voltage IOL = 6 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(IO)  0.4 V 6 - - mA IOL LOW-level output current VOL = 0.4 V 6 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [12] - - 86.5 mA IOLS LOW-level short-circuit output current drive LOW; connected to VDD(IO) [12] - - 76.5 mA Ipd pull-down current VI = 5 V [14] - 93 - A - 62 - A - 10 - [15] [16] Ipu pull-up current VI = 0 V [14] [15] [16] VDD(IO) < VI  5 V Rs series resistance on I/O pins with analog function; analog function enabled A  200 I/O pins - high drive strength CI input capacitance ILL LOW-level leakage current ILH HIGH-level leakage current - - 2 pF VI = 0 V; on-chip pull-up resistor disabled - 3 - nA VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V - - 20 nA - 3 - nA 0 - 5.5 V IOZ OFF-state output current VO = 0 V to VDD(IO); on-chip pull-up/down resistors disabled; absolute value VI input voltage pin configured to provide a digital function; VDD(IO)  2.2 V VDD(IO) = 0 V 0 - 3.6 V 0 - VDD(IO) V HIGH-level input voltage 0.7  VDD(IO) - 5.5 V VIL LOW-level input voltage 0 - 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V VO output voltage VIH LPC43S70 Product data sheet output active All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 89 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Ipd Parameter pull-down current Conditions VI = VDD(IO) [14] Min Typ[1] Max Unit - 62 - A - 62 - A - 10 - A [15] [16] Ipu pull-up current VI = 0 V [14] [15] [16] VDD(IO) < VI  5 V I/O pins - high drive strength: standard drive mode IOH HIGH-level output current VOH = VDD(IO)  0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [12] - - 32 mA IOLS LOW-level short-circuit output current [12] - - 32 mA drive LOW; connected to VDD(IO) I/O pins - high drive strength: medium drive mode IOH HIGH-level output current VOH = VDD(IO)  0.4 V 8 - - mA IOL LOW-level output current VOL = 0.4 V 8 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [12] - - 65 mA IOLS LOW-level short-circuit output current [12] - - 63 mA drive LOW; connected to VDD(IO) I/O pins - high drive strength: high drive mode IOH HIGH-level output current VOH = VDD(IO)  0.4 V 14 - - mA IOL LOW-level output current VOL = 0.4 V 14 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [12] - - 113 mA IOLS LOW-level short-circuit output current [12] - - 110 mA drive LOW; connected to VDD(IO) I/O pins - high drive strength: ultra-high drive mode IOH HIGH-level output current VOH = VDD(IO)  0.4 V 20 - - mA IOL LOW-level output current VOL = 0.4 V 20 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [12] - - 165 mA IOLS LOW-level short-circuit output current [12] - - 156 mA - - 2 pF drive LOW; connected to VDD(IO) I/O pins - high-speed CI LPC43S70 Product data sheet input capacitance All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 90 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit ILL LOW-level leakage current VI = 0 V; on-chip pull-up resistor disabled - 3 - nA ILH HIGH-level leakage current VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V - - 20 nA - 3 - nA 0 - 5.5 V IOZ OFF-state output current VO = 0 V to VDD(IO); on-chip pull-up/down resistors disabled; absolute value VI input voltage pin configured to provide a digital function; VDD(IO)  2.2 V VDD(IO) = 0 V 0 - 3.6 V 0 - VDD(IO) V HIGH-level input voltage 0.7  VDD(IO) - 5.5 V VIL LOW-level input voltage 0 - 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V VOH HIGH-level output voltage IOH = 8 mA VDD(IO)  0.4 - - V VOL LOW-level output voltage IOL = 8 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(IO)  0.4 V 8 - - mA IOL LOW-level output current VOL = 0.4 V 8 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [12] - - 86 mA IOLS LOW-level short-circuit output current drive LOW; connected to VDD(IO) [12] - - 76 mA Ipd pull-down current VI = VDD(IO) [14] - 62 - A - 62 - A - 0 - A VO output voltage VIH output active [15] [16] pull-up current Ipu VI = 0 V [14] [15] [16] VDD(IO) < VI  5 V Open-drain I2C0-bus pins VIH HIGH-level input voltage 0.7  VDD(IO) - - V VIL LOW-level input voltage 0 0.14 0.3  VDD(IO) V LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 91 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Vhys hysteresis voltage VOL LOW-level output voltage IOLS = 3 mA ILI input leakage current VI = VDD(IO) [13] VI = 5 V Min Typ[1] Max Unit 0.1  VDD(IO) - - V - - 0.4 V - 4.5 - A - - 10 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 - 1.2 V Vo(XTAL2) output voltage on pin XTAL2 0.5 - 1.2 V Cio input/output capacitance - - 0.8 pF 0 - 5.25 V [17] USB0 pins[18] VI input voltage on pins USB0_DP; USB0_DM; USB0_VBUS VDD(IO)  2.2 V 0 - 3.6 V Rpd pull-down resistance on pin USB0_VBUS VDD(IO) = 0 V 48 64 80 k VIC common-mode input voltage high-speed mode 50 200 500 mV full-speed/low-speed mode 800 - 2500 mV chirp mode 50 - 600 mV 100 400 1100 mV [18] - - 10 A [19] - - 5.25 V differential input voltage Vi(dif) USB1 pins (USB1_DP/USB1_DM)[18] IOZ OFF-state output current VBUS bus supply voltage VDI differential input sensitivity voltage (D+)  (D) 0.2 - - V VCM differential common mode voltage range includes VDI range 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed - - 0.18 V LPC43S70 Product data sheet 0 V < VI < 3.3 V RL of 1.5 k to 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 92 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND - - 20 pF ZDRV driver output with 33  series resistor; impedance for driver steady state drive which is not high-speed capable 36 - 44.1  [20] [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. See Figure 15. [3] Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure the same ramp-up time for both supply voltages. [4] VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb = 25 C. [5] PLL1 disabled; IRC running; CCLK = 12 MHz. [6] VBAT = 3.6 V. [7] VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz. [8] On pin VBAT; Tamb = 25 C. [9] VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V. Input leakage increases when VDD(IO) is floating or grounded. It is recommended to keep VDD(REG)(3V3) and VDD(IO) powered in deep power-down mode. [10] Vps corresponds to the output of the power switch (see Figure 7) which is determined by the greater of VBAT and VDD(Reg)(3V3). [11] VDDA(3V3) = 3.3 V; Tamb = 25 C. [12] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [13] To VSS. [14] The values specified are simulated and absolute values. [15] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level. [16] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO). [17] The parameter value specified is a simulated value excluding bond capacitance. [18] For USB operation 3.0 V  VDD((IO)  3.6 V. Guaranteed by design. [19] VDD(IO) present. [20] Includes external resistors of 33   1 % on D+ and D. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 93 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.1 Power consumption 002aah611 100 IDD(REG)(3V3) IDD(REG)(3V3) (mA) (mA) 204 MHz 80 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 2.2 2.4 2.6 2.8 3 3.2 3.4 VDD(REG)(3V3) (V) 3.6 Conditions: Tamb = 25 C; active mode entered executing code while(1){} from SRAM; M0 cores in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 8. Typical supply current versus regulator supply voltage VDD(REG)(3V3) in active mode 002aah612 100 IDD(REG)(3V3) IDD(REG)(3V3) (mA) (mA) 204 MHz 80 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V, Active mode entered executing code while(1){} from SRAM;M0 cores in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 9. LPC43S70 Product data sheet Typical supply current versus temperature in Active mode All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 94 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah613 100 IDD(REG)(3V3) IDD(REG)(3V3) (mA) (mA) 85 °C C 25 °C C -40 °C C 80 60 40 20 0 12 36 60 84 108 132 156 180 CCLK frequency (MHz) 204 Conditions: VDD(REG)(3V3) = 3.3 V; Active mode entered executing code while(1){} from SRAM;M0 cores in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 10. Typical supply current versus frequency in Active mode 002aah153 10 IDD(REG)(3V3) ( (mA) 8 6 4 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; M0 cores in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled; core clock CCLK = 12 MHz. Fig 11. Typical supply current versus temperature in Sleep mode LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 95 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah154 300 IDD(REG)(3V3) )( (μA) 240 180 120 60 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 12. Typical supply current versus temperature in Deep-sleep mode 002aah155 50 IDD(REG)(3V3) )( (μA) 40 30 20 10 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 13. Typical supply current versus temperature in Power-down mode LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 96 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah156 10 IDD(REG)(3V3) DD(REG (μA) 8 6 4 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 14. Typical supply current versus temperature in Deep power-down mode 002aah150 80 IBAT (μA) 60 40 20 0 -0.4 -0.2 0 0.2 0.4 VBAT - VDD(REG)(3V3) (V) 0.6 Conditions: VDD(REG)(3V3) = 3.0 V; CCLK = 12 MHz. Fig 15. Typical battery supply current in Active mode LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 97 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah157 10 IBAT (μA) 8 6 VBAT = 3.6 V 3.0 V 2.2 V 4 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3), VDD(IO) floating. Fig 16. Typical battery supply versus temperature in Deep power-down mode 10.2 Peripheral power consumption The typical power consumption at T = 25 C for each individual peripheral is measured as follows: 1. Enable all branch clocks and measure the current IDD(REG)(3V3). 2. Disable the branch clock to the peripheral to be measured and keep all other branch clocks enabled. 3. Calculate the difference between measurement 1 and 2. The result is the peripheral power consumption. Table 11. Peripheral power consumption Peripheral Branch clock IDD(REG)(3V3) in mA Branch clock Branch clock frequency = 48 MHz frequency = 96 MHz M0 subsystem core LPC43S70 Product data sheet CLK_PERIPH_CORE 2.4 4.8 M0 coprocessor CLK_M4_M0APP 3.3 6.6 I2C1 CLK_APB3_I2C1 0.01 0.02 I2C0 CLK_APB1_I2C0 0.02 0.01 DAC CLK_APB3_DAC 0.01 0.02 ADC0 (10-bit) CLK_APB3_ADC0 0.05 0.05 ADC1 (10-bit) CLK_APB3_ADC1 0.04 0.04 CAN0 CLK_APB3_CAN0 0.17 0.17 CAN1 CLK_APB1_CAN1 0.17 0.17 MOTOCON CLK_APB1_MOTOCON 0.05 0.05 I2S CLK_APB1_I2S 0.11 0.11 SPIFI CLK_SPIFI, CLK_M4_SPIFI 0.95 1.85 All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 98 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Peripheral power consumption Peripheral Branch clock IDD(REG)(3V3) in mA Branch clock Branch clock frequency = 48 MHz frequency = 96 MHz GPIO LPC43S70 Product data sheet CLK_M4_GPIO 0.66 1.31 LCD CLK_M4_LCD 0.85 1.72 ETHERNET CLK_M4_ETHERNET 1.05 2.09 UART0 CLK_M4_UART0, CLK_APB0_UART0 0.3 0.38 UART1 CLK_M4_UART1, CLK_APB0_UART1 0.27 0.48 UART2 CLK_M4_UART2, CLK_APB2_UART2 0.27 0.47 UART3 CLK_M4_USART3, CLK_APB2_UART3 0.29 0.49 TIMER0 CLK_M4_TIMER0 0.07 0.14 TIMER1 CLK_M4_TIMER1 0.07 0.14 TIMER2 CLK_M4_TIMER2 0.07 0.15 TIMER3 CLK_M4_TIMER3 0.06 0.11 SDIO CLK_M4_SDIO, CLK_SDIO 0.79 1.37 SCT CLK_M4_SCT 0.52 1.05 SSP0 CLK_M4_SSP0, CLK_APB0_SSP0 0.12 0.21 SSP1 CLK_M4_SSP1, CLK_APB2_SSP1 0.15 0.28 DMA CLK_M4_DMA 1.88 3.71 WWDT CLK_M4_WWDT 0.05 0.08 QEI CLK_M4_QEI 0.33 0.68 USB0 CLK_M4_USB0, CLK_USB0 1.46 3.32 USB1 CLK_M4_USB1, CLK_USB1 2.83 5.03 RITIMER CLK_M4_RITIMER 0.04 0.08 EMC CLK_M4_EMC, CLK_M4_EMC_DIV 3.6 6.97 SCU CLK_M4_SCU 0.09 0.23 CREG CLK_M4_CREG 0.37 0.72 SGPIO CLK_PERIPH_SGPIO 0.1 0.17 SPI CLK_SPI 0.07 0.11 All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 99 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 12. Peripheral power consumption 12-bit ADCHS Peripheral Branch clock IDD(REG)(3V3) in mA Branch clock Branch clock frequency = 39 MHz frequency = 78 MHz Conditions ADCHS (12-bit ADC) CLK_ADCHS, CLK_M4_ADCH 1.1 2.3 Peripheral power consumption; no ADC conversions ADCHS (12-bit ADC) CLK_ADCHS, CLK_M4_ADCH 28.5 41.6 Peripheral power consumption; ADC converting samples at CLK_ADCHS frequency 10.3 BOD and band gap static characteristics Table 13. BOD static characteristics[1] Tamb = 25 C; simulated values for nominal processing. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion - 2.75 - V de-assertion - 2.92 - V assertion - 2.85 - V de-assertion - 3.00 - V assertion - 2.95 - V de-assertion - 3.12 - V assertion - 3.05 - V de-assertion - 3.19 - V interrupt level 1 interrupt level 2 interrupt level 3 reset level 0 assertion - 1.70 - V de-assertion - 1.85 - V assertion - 1.80 - V de-assertion - 1.95 - V assertion - 1.90 - V de-assertion - 2.05 - V assertion - 2.00 - V de-assertion - 2.15 - V reset level 1 reset level 2 reset level 3 [1] LPC43S70 Product data sheet Interrupt and reset levels are selected by writing to the BODLV1/2 bits in the control register CREGE0, see the LPC43xx user manual. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 100 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 14. Band gap characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified Symbol Vref(bg) [1] LPC43S70 Product data sheet Parameter band gap reference voltage [1] Min Typ Max Unit 0.621 0.6425 0.664 V Based on characterization, not tested in production. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 101 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.4 Electrical pin characteristics 002aah030 15 -40 °C 25 °C 85 °C IOL (mA) 12 9 6 3 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 17. Normal-drive pins; typical LOW level output current IOL versus LOW level output voltage VOL 002aah039 3.6 VOH (V) 3.2 2.8 T = 85 °C 25 °C -40 °C 2.4 2.0 0 12 24 36 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 18. Normal-drive pins; typical HIGH level output voltage VOH versus HGH level output current IOH LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 102 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah040 15 -40 °C 25 °C 85 °C IOL (mA) 12 002aah041 25 IOL (mA) 20 9 15 6 10 3 5 0 -40 °C 25 °C 85 °C 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 0 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah043 40 IOL (mA) 0.1 002aah044 60 IOL (mA) 32 -40 °C 25 °C 85 °C 24 -40 °C 25 °C 85 °C 45 30 16 15 8 0 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive; EHD = 0x2. 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra high-drive; EHD = 0x3. Fig 19. High-drive pins; typical LOW level output current IOL versus LOW level output voltage VOL LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 103 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah047 3.6 VOH (V) 002aah048 3.6 VOH (V) 3.2 3.2 -40 °C 25 °C 85 °C 2.8 -40 °C 25 °C 85 °C 2.8 2.4 2.4 2.0 2.0 0 8 16 24 0 16 32 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 002aah049 3.6 48 IOH (mA) VOH (V) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah050 3.6 VOH (V) 3.2 3.2 -40 °C 25 °C 85 °C 2.8 -40 °C 25 °C 85 °C 2.8 2.4 2.4 2.0 2.0 0 32 64 96 0 IOH (mA) 40 80 120 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; high-drive; EHD = 0x2. Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; ultra high-drive; EHD = 0x3. Fig 20. High-drive pins; typical HIGH level output voltage VOH versus HGH level output current IOH LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 104 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aag625 +20 Ipu (μA) 0 -20 T = 25 °C -40 °C -40 -60 -80 0 1 2 3 4 5 VI (V) Conditions: VDD(IO)) = 3.3 V. Simulated values. Values at T = 25 C are typical values. Values at T = 40 C correspond to minimum values. Fig 21. Typical pull-up current Ipu versus input voltage VI 002aag626 120 Ipd (μA) 90 60 T =25 °C -40 °C 30 0 0 1 2 3 4 5 VI (V) Conditions: VDD(IO)) = 3.3 V. Simulated values. Values at T = 25 C are typical values. Values at T = 40 C correspond to maximum values. Fig 22. Typical pull-down current Ipd versus input voltage VI LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 105 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11. Dynamic characteristics 11.1 Wake-up times Table 15. Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep power-down modes Tamb = 40 C to +85 C Symbol Parameter twake Min Typ[1] 3 Tcy(clk) 5  Tcy(clk) - ns from Deep-sleep and Power-down mode 12 51 - s from Deep power-down mode - 250 - s after reset - 250 - s Conditions [2] wake-up time from Sleep mode Max Unit [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Tcy(clk) = 1/CCLK with CCLK = CPU clock frequency. 11.2 External clock for oscillator in slave mode Remark: The input voltage on the XTAL1/2 pins must be  1.2 V (see Table 10). For connecting the oscillator to the XTAL pins, also see Section 13.2 and Section 13.4. Table 16. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(IO) over specified ranges.[1] Symbol Parameter fosc Tcy(clk) Min Max Unit oscillator frequency 1 25 MHz clock cycle time 40 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 Tcy(clk)  0.6 ns tCLCX clock LOW time Tcy(clk)  0.4 Tcy(clk)  0.6 ns [1] Conditions Parameters are valid over operating temperature range unless otherwise specified. tCHCX tCLCX Tcy(clk) 002aag698 Fig 23. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 106 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.3 Crystal oscillator Table 17. Dynamic characteristic: oscillator Tamb = 40 C to +85 C; VDD(IO) over specified ranges; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Low-frequency mode (1 MHz - 20 tjit(per) period jitter time period jitter time Typ[2] Max Unit MHz)[5] 5 MHz crystal [3][4] - 13.2 - ps 10 MHz crystal - 6.6 - ps 15 MHz crystal - 4.8 - ps - 4.3 - ps - 3.7 - ps High-frequency mode (20 MHz - 25 tjit(per) Min MHz)[6] 20 MHz crystal [3][4] 25 MHz crystal [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [3] Indicates RMS period jitter. [4] PLL-induced jitter is not included. [5] Select HF = 0 in the XTAL_OSC_CTRL register. [6] Select HF = 1 in the XTAL_OSC_CTRL register. 11.4 IRC oscillator Table 18. Dynamic characteristic: IRC oscillator Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.82 12.0 12.18 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.5 GPCLKIN Table 19. Dynamic characteristic: GPCLKIN Tamb = 25 C; 2.4 V  VDD(REG)(3V3)  3.6 V Symbol Parameter Min Typ Max Unit GP_CLKIN input frequency - - 25 MHz 11.6 I/O pins Table 20. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; 2.7 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit Standard I/O pins - normal drive strength tr LPC43S70 Product data sheet rise time pin configured as output; EHS = 1 [2][3] 1.0 - 2.5 ns 0.9 - 2.5 ns 1.9 - 4.3 ns tf fall time pin configured as output; EHS = 1 [2][3] tr rise time pin configured as output; EHS = 0 [2][3] All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 107 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 20. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; 2.7 V  VDD(IO)  3.6 V. Symbol Parameter tf tr tf fall time rise time fall time Conditions Min Typ Max Unit pin configured as output; EHS = 0 [2][3] 1.9 - 4.0 ns pin configured as input [4] 0.3 - 1.3 ns pin configured as input [4] 0.2 - 1.2 ns I/O pins - high drive strength tr rise time pin configured as output; standard drive mode (EHD = 0x0) [2][5] 4.3 - 7.9 ns tf fall time pin configured as output; standard drive mode (EHD = 0x0) [2][5] 4.7 - 8.7 ns tr rise time pin configured as output; medium drive mode (EHD = 0x1) [2][5] 3.2 - 5.7 ns tf fall time pin configured as output; medium drive mode (EHD = 0x1) [2][5] 3.2 - 5.5 ns tr rise time pin configured as output; high drive mode (EHD = 0x2) [2][5] 2.9 - 4.9 ns tf fall time pin configured as output; high drive mode (EHD = 0x2) [2][5] 2.5 - 3.9 ns tr rise time pin configured as output; ultra-high drive mode (EHD = 0x3) [2][5] 2.8 - 4.7 ns tf fall time pin configured as output; ultra-high drive mode (EHD = 0x3) [2][5] 2.4 - 3.4 ns tr rise time pin configured as input [4] 0.3 - 1.3 ns pin configured as input [4] 0.2 - 1.2 ns pin configured as output; EHS = 1 [2][3] 350 - 670 ps pin configured as output; EHS = 1 [2][3] 450 - 730 ps pin configured as output; EHS = 0 [2][3] 1.0 - 1.9 ns tf fall time I/O pins - high-speed tr tf tr LPC43S70 Product data sheet rise time fall time rise time tf fall time pin configured as output; EHS = 0 [2][3] 1.0 - 2.0 ns tr rise time pin configured as input [4] 0.3 - 1.3 ns pin configured as input [4] 0.2 - 1.2 ns tf fall time [1] Simulated data. [2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between 80 % and 20 % of the full output signal level. [3] The slew rate is configured in the system control block in the SFSP registers using the EHS bit. See the LPC43xx user manual. [4] CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level. [5] The drive modes are configured in the system control block in the SFSP registers using the EHD bit. See the LPC43xx user manual. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 108 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.7 RTC oscillator Table 21. Dynamic characteristic: RTC oscillator Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V or 2.2 V  VBAT  3.6 V[1]; typical CRTCX1/2 = 20 pF; also see Section 13.3. Symbol Parameter Conditions Min fi(RTC) RTC input frequency - - IDD(RTC) RTC supply current Typ[2] Max Unit 32.768 - kHz 280 800 nA [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.8 I2C-bus Table 22. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s [3][4][5][6] fall time tf Standard-mode tLOW tHIGH tHD;DAT tSU;DAT [1] LOW period of the SCL clock HIGH period of the SCL clock [2][3][7] data hold time [8][9] data set-up time Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details. [2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed. [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 109 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller allow for this when considering bus timing. [7] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [9] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 24. I2C-bus pins clock timing 11.9 I2S-bus interface Table 23. Dynamic characteristics: I2S-bus interface pins Tamb = 25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data refer to I2S0 and I2S1 pins. Simulated values. Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time - 4 - ns tf fall time - 4 - ns tWH pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK 36 - - ns tWL pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK 36 - - ns - 4.4 - ns - 4.3 - ns 0 - output tv(Q) data output valid time on pin I2Sx_TX_SDA [1] on pin I2Sx_TX_WS input tsu(D) data input set-up time on pin I2Sx_RX_SDA [1] - on pin I2Sx_RX_WS th(D) data input hold time on pin I2Sx_RX_SDA on pin I2Sx_RX_WS LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 0.20 [1] ns ns - 3.7 - ns - 3.9 - ns © NXP B.V. 2016. All rights reserved. 110 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Clock to the I2S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I2S-bus interface PCLK = BASE_APB1_CLK / 12. I2S clock cycle time Tcy(clk) = 79.2 ns; corresponds to the SCK signal in the I2S-bus specification. [1] Tcy(clk) tf tr I2Sx_TX_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_TX_WS 002aag497 tv(Q) Fig 25. I2S-bus timing (transmit) Tcy(clk) tf tr I2Sx_RX_SCK tWH tWL I2Sx_RX_SDA tsu(D) th(D) I2Sx_RX_WS tsu(D) 002aag498 th(D) Fig 26. I2S-bus timing (receive) 11.10 USART interface Table 24. USART dynamic characteristics Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. EHS = 1 for all pins. Simulated values. Symbol Parameter Min Max Unit USART master (in synchronous mode) LPC43S70 Product data sheet tsu(D) data input set-up time 26.6 - ns th(D) data input hold time 0 - ns tv(Q) data output valid time 0 8.8 ns All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 111 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 24. USART dynamic characteristics Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. EHS = 1 for all pins. Simulated values. Symbol Parameter Min Max Unit USART slave (in synchronous mode) tsu(D) data input set-up time 1.2 - ns th(D) data input hold time 0.4 - ns tv(Q) data output valid time 5.5 24 ns Tcy(clk) SCLK (FES = 1) SCLK (FES = 0) tv(Q) tv(Q) START TXD BIT0 th(D) tsu(D) START RXD BIT1 BIT0 BIT1 aaa-016717 Fig 27. USART timing LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 112 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.11 SSP interface Table 25. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Sampled at 10 % and 90 % of the signal level; EHS = 1 for all pins. Simulated values. Symbol Parameter Conditions Min Typ Max Unit 1/(25.5  106) - - s when only transmitting 1/(51  - - s 13.6 - - ns SSP master Tcy(clk) clock cycle time [1] full-duplex mode 106) tDS data set-up time in SPI mode tDH data hold time in SPI mode 3.8 - - ns tv(Q) data output valid time in SPI mode - - 6.0 ns th(Q) data output hold time in SPI mode 1.1 - - ns tlead lead time continuous transfer mode Tcy(clk) + 3.2 - Tcy(clk) + 6.1 ns SPI mode; CPOL = 0; CPHA = 1 0.5  Tcy(clk) + 3.2 - 0.5  Tcy(clk) + 6.1 ns SPI mode; CPOL = 1; CPHA = 0 Tcy(clk) + 3.2 - Tcy(clk) + 6.1 SPI mode; CPOL = 1; CPHA = 1 0.5  Tcy(clk) + 3.2 - 0.5  Tcy(clk) + 6.1 ns synchronous serial frame mode 0.5  Tcy(clk) + 3.2 - 0.5  Tcy(clk) + 6.1 ns microwire frame format Tcy(clk) + 3.2 - Tcy(clk) + 6.1 ns continuous transfer mode 0.5  Tcy(clk) - - ns SPI mode; CPOL = 0; CPHA = 1 Tcy(clk) - - ns SPI mode; CPOL = 1; CPHA = 0 0.5  Tcy(clk) - - ns SPI mode; CPOL = 1; CPHA = 1 Tcy(clk) - - ns synchronous serial frame mode Tcy(clk) - - ns microwire frame format 0.5  Tcy(clk) - - ns SPI mode; CPOL = 0; CPHA = 0 tlag lag time ns SPI mode; CPOL = 0; CPHA = 0 LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 113 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 25. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Sampled at 10 % and 90 % of the signal level; EHS = 1 for all pins. Simulated values. Symbol Parameter Conditions Min Typ Max Unit td delay time continuous transfer mode - 0.5  Tcy(clk) - ns SPI mode; CPOL = 0; CPHA = 1 - n/a - ns SPI mode; CPOL = 1; CPHA = 0 - 0.5  Tcy(clk) - ns SPI mode; CPOL = 1; CPHA = 1 - n/a - ns synchronous serial frame mode - Tcy(clk) - ns microwire frame format - n/a - ns - - 204 MHz 1/(11 106) - - s SPI mode; CPOL = 0; CPHA = 0 SSP slave PCLK Peripheral clock frequency Tcy(clk) clock cycle time [2] tDS data set-up time in SPI mode 1.15 - - ns tDH data hold time in SPI mode 0.5 - - ns tv(Q) data output valid time in SPI mode - - [4  (1/PCLK)] + 3 ns th(Q) data output hold time in SPI mode 5.1 - - ns tlead lead time continuous transfer mode Tcy(clk) + 2.2 - - ns SPI mode; CPOL = 0; CPHA = 1 0.5  Tcy(clk) + 2.2 - - ns SPI mode; CPOL = 1; CPHA = 0 Tcy(clk) + 2.2 - - ns SPI mode; CPOL = 1; CPHA = 1 0.5  Tcy(clk) + 2.2 - - ns synchronous serial frame mode 0.5  Tcy(clk) + 2.2 - - ns microwire frame format Tcy(clk) + 2.2 - - ns SPI mode; CPOL = 0; CPHA = 0 LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 114 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 25. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Sampled at 10 % and 90 % of the signal level; EHS = 1 for all pins. Simulated values. Symbol Parameter Conditions Min Typ Max Unit tlag lag time continuous transfer mode 0.5Tcy(clk) + 0.2 - - ns SPI mode; CPOL = 0; CPHA = 1 Tcy(clk) + 0.2 - - ns SPI mode; CPOL = 1; CPHA = 0 0.5  Tcy(clk) + 0.2 - - ns SPI mode; CPOL = 1; CPHA = 1 Tcy(clk) + 0.2 - - ns synchronous serial frame mode Tcy(clk) + 0.2 - - ns microwire frame format 0.5  Tcy(clk) - - ns - 0.5  Tcy(clk) - ns SPI mode; CPOL = 0; CPHA = 1 - n/a - ns SPI mode; CPOL = 1; CPHA = 0 - 0.5  Tcy(clk) - ns SPI mode; CPOL = 1; CPHA = 1 - n/a - ns synchronous serial frame mode - Tcy(clk) - ns microwire frame format - n/a - ns SPI mode; CPOL = 0; CPHA = 0 delay time td continuous transfer mode SPI mode; CPOL = 0; CPHA = 0 [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). [2] Tcy(clk) 12  Tcy(PCLK). LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 115 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.12 SPI interface Table 26. Dynamic characteristics: SPI Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values. Symbol Parameter Tcy(PCLK) PCLK cycle time Tcy(clk) clock cycle time Conditions Min Typ Max 5 [1] Unit ns 40 - - ns Master tDS data set-up time 7.2 - - ns tDH data hold time 0 - - ns tv(Q) data output valid time - - 3.7 ns th(Q) data output hold time - - 1.2 ns tDS data set-up time 1.2 - - ns tDH data hold time 3 x Tcy(PCLK) + 0.54 - - ns tv(Q) data output valid time - - 3 x Tcy(PCLK) + 9.7 ns th(Q) data output hold time - - 2 x Tcy(PCLK) + 7.1 ns Slave [1] Tcy(clk) = 8/BASE_SPI_CLK. Tcy(PCLK) = 1/BASE_SPI_CLK. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 116 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.13 SSP/SPI timing diagrams Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI (CPHA = 0) tv(Q) th(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) DATA VALID (LSB) DATA VALID (MSB) IDLE tDH tDS MISO (CPHA = 0) MOSI (CPHA = 1) td tlag tlead DATA VALID DATA VALID (MSB) DATA VALID (LSB) tv(Q) th(Q) DATA VALID (LSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID DATA VALID (MSB) DATA VALID (MSB) aaa-013462 Fig 28. SSP master mode timing (SPI mode) LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 117 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 29. SSP slave timing in SPI mode LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 118 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.14 SPIFI Table 27. Dynamic characteristics: SPIFI Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. CL = 20 pF. Sampled at 90 % and 10 % of the signal level. EHS = 1 for all pins. Simulated values. Symbol Parameter Min Max Unit Tcy(clk) clock cycle time 9.6 - ns tDS data set-up time 2.8 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 2.6 ns th(Q) data output hold time 0.8 - ns Tcy(clk) SPIFI_SCK tv(Q) SPIFI data out DATA VALID th(Q) DATA VALID tDS SPIFI data in DATA VALID tDH DATA VALID 002aah409 Fig 30. SPIFI timing 11.15 SGPIO timing The following considerations apply to SGPIO timing: • SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK. To guarantee that no samples are missed, all input signals should have a duration of at least one SGPIO_CLOCK cycle plus the set-up and hold times. • When an external clock input is used to generate output data, synchronization causes a latency of at least one SGPIO_CLOCK cycle. The maximum output data rate is one output every two SGPIO_CLOCK cycles. • Synchronization also causes a latency of one SGPIO_CLOCK cycle when sampling several inputs. This may cause inputs with very similar timings to be sampled with a difference of one SGPIO_CLOCK cycle. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 119 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 28. Dynamic characteristics: SGPIO Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values. Symbol Parameter Min Typ Max Unit tsu(D) data input set-up time th(D) data input hold time [1] 2 - - ns TSGPIO + 2 - - ns data input set-up time sampled by SGPIO_CLOCK [1] tsu(D) TSGPIO + 2 - - ns th(D) data input hold time [1] TSGPIO + 2 - - ns tv(Q) data output valid time [1] - - 2 x TSGPIO ns data output hold time [1] TSGPIO - tv(Q) data output valid time sampled by SGPIO_CLOCK [1] -3 - 3 ns th(Q) data output hold time sampled by SGPIO_CLOCK [1] -3 - 3 ns th(Q) [1] Conditions sampled by SGPIO_CLOCK ns SGPIO_CLOCK is the internally generated SGPIO clock. TSGPIO = 1/fSGPIO_CLOCK. SGPIO_CLOCK CLKINext sync(CLKINext) = CLKINi th(D) tsu(D) DIN DINi sync(DIN) DINi tv(Q) CLKout th(Q) Dout DQi 002aah668 Fig 31. SGPIO timing LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 120 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.16 External memory interface Table 29. Dynamic characteristics: Static asynchronous external memory interface CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses. Symbol Parameter[1] Conditions Min Typ Max Uni t 3.1 - 1.6 ns 0.6 + Tcy(clk)  WAITOEN - 1.3 + Tcy(clk)  WAITOEN ns 0.7 - 1.8 ns 0.6 + (WAITRD  WAITOEN + 1)  Tcy(clk) - 0.4 + ns (WAITRD  WAITOEN + 1)  Tcy(clk) Read cycle parameters tCSLAV CS LOW to address valid time tCSLOEL CS LOW to OE LOW time tCSLBLSL CS LOW to BLS LOW time [2] PB = 1 [2] tOELOEH OE LOW to OE HIGH time tam memory access time - - 16 + (WAITRD  WAITOEN +1)  Tcy(clk) ns th(D) data input hold time 16 - - ns tCSHBLSH CS HIGH to BLS HIGH time PB = 1 0.4 - 1.9 ns tCSHOEH CS HIGH to OE HIGH time 0.4 - 1.4 ns tOEHANV OE HIGH to address invalid PB = 1 tCSHEOR CS HIGH to end of read time [3] tCSLSOR CS LOW to start of read time [4] 2.0 - 2.6 ns 2.0 - 0 ns 0 - 1.8 ns Write cycle parameters tCSLAV CS LOW to address valid time 3.1 - 1.6 ns tCSLDV CS LOW to data valid time 3.1 - 1.5 ns tCSLWEL CS LOW to WE LOW time 1.5+ - 0.2+ ns PB = 1 (WAITWEN + 1)  Tcy(clk) (WAITWEN + 1)  Tcy(clk) tCSLBLSL CS LOW to BLS LOW time PB = 1 0.7 - 1.8 tWELWEH WE LOW to WE HIGH time PB = 1 [2] 0.6 + (WAITWR  WAITWEN + 1)  Tcy(clk) - 0.4 + ns (WAITWR  WAITWEN + 1)  Tcy(clk) tWEHDNV WE HIGH to data invalid time PB = 1 [2] 0.9 + Tcy(clk) - 2.3 + Tcy(clk) ns tWEHEOW WE HIGH to end of write time PB = 1 [2] 0.4 + Tcy(clk) - 0.3 + Tcy(clk) ns CS LOW to BLS LOW PB = 0 0.7+ - 1.8+ ns tCSLBLSL [5] (WAITWEN + 1)  Tcy(clk) LPC43S70 Product data sheet ns All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 (WAITWEN + 1)  Tcy(clk) © NXP B.V. 2016. All rights reserved. 121 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 29. Dynamic characteristics: Static asynchronous external memory interface …continued CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses. Symbol Parameter[1] tBLSLBLSH BLS LOW to BLS HIGH time PB = 0 tBLSHEOW BLS HIGH to end of write time PB = 0 tBLSHDNV BLS HIGH to data invalid time PB = 0 tCSHEOW CS HIGH to end of write time tBLSHDNV BLS HIGH to data invalid time tWEHANV WE HIGH to address invalid PB = 1 time Conditions Min Typ Max Uni t [2] 0.9 + (WAITWR  WAITWEN + 1)  Tcy(clk) - ns 0.1 + (WAITWR  WAITWEN + 1)  Tcy(clk) [2] 1.9 + Tcy(clk) - 0.5 + Tcy(clk) ns [2] 2.5 + Tcy(clk) - 1.4 + Tcy(clk) ns [5] 2.0 - 0 ns 2.5 - 1.4 ns 0.9 + Tcy(clk) - 2.4 + Tcy(clk) ns [5] PB = 1 [1] Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges. [2] Tcy(clk) = 1/CCLK (see LPC43xx User manual). [3] End Of Read (EOR): longest of tCSHOEH, tOEHANV, tCSHBLSH. [4] Start Of Read (SOR): longest of tCSLAV, tCSLOEL, tCSLBLSL. [5] End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH. EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSHOEH tBLSHEOW tCSLBLSL tBLSLBLSH EMC_BLSn EMC_WE tCSLDV tam tCSHEOR tCSLSOR tBLSHDNV th(D) EMC_Dn SOR EOR EOW 002aag699 Fig 32. External static memory read/write access (PB = 0) LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 122 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSLBLSL tCSHOEH tCSLBLSL EMC_BLSn tCSHBLSH tCSLWEL tWELWEH tWEHEOW EMC_WE tBLSHDNV tam tCSHEOR th(D) tCSLSOR tCSLDV tWEHDNV EMC_Dn SOR EOR EOW 002aag700 Fig 33. External static memory read/write access (PB = 1) LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 123 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 30. Dynamic characteristics: Dynamic external memory interface Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; VDD(IO) =3.3 V  10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0. Symbol Parameter Min Typ Max Unit Tcy(clk) clock cycle time 8.4 - - ns 3.1 + 0.5  Tcy(clk) 5.1 + 0.5  Tcy(clk) ns - ns 4.9 + 0.5  Tcy(clk) ns Common to read and write cycles td(DYCSV) DYCS delay time - th(DYCS) DYCS hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) td(RASV) row address strobe valid delay time - th(RAS) row address strobe hold time 0.5 + 0.5  Tcy(clk) 1.1 + 0.5  Tcy(clk) td(CASV) column address strobe valid delay time - th(CAS) column address strobe hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) td(WEV) WE valid delay time - th(WE) WE hold time 1.3 + 0.5  Tcy(clk) 1.4 + 0.5  Tcy(clk) td(DQMOUTV) DQMOUT valid delay time - th(DQMOUT) DQMOUT hold time 0.2 + 0.5  Tcy(clk) 0.8 + 0.5  Tcy(clk) td(AV) address valid delay time - th(A) address hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) - ns td(CKEOUTV) CKEOUT valid delay time - 3.1 + 0.5  Tcy(clk) 5.1 + 0.5  Tcy(clk) ns th(CKEOUT) CKEOUT hold time 0.5  Tcy(clk) 0.7 + 0.5  Tcy(clk) - ns 3.1 + 0.5  Tcy(clk) 2.9 + 0.5  Tcy(clk) 3.2 + 0.5  Tcy(clk) 3.1 + 0.5  Tcy(clk) 3.8 + 0.5  Tcy(clk) - ns 4.6 + 0.5  Tcy(clk) ns - ns 5.9 + 0.5  Tcy(clk) ns - ns 5.0 + 0.5  Tcy(clk) ns - ns 6.3 + 0.5  Tcy(clk) ns Read cycle parameters tsu(D) data input set-up time 1.5 0.5 - ns th(D) data input hold time 2.2 0.8 - ns Write cycle parameters td(QV) data output valid delay time - 3.8 + 0.5  Tcy(clk) 6.2 + 0.5  Tcy(clk) ns th(Q) data output hold time 0.5  Tcy(clk) 0.7 + 0.5  Tcy(clk) - ns Table 31. Dynamic characteristics: Dynamic external memory interface; EMC_CLK[3:0] delay values Tamb = 40 C to 85 C; VDD(IO) =3.3 V  10 %; 2.2 V  VDD(REG)(3V3)  3.6 V. Symbol Parameter Conditions td delay time delay value CLKn_DELAY = 0 [1] LPC43S70 Product data sheet Min Typ Max Unit [1] 0.0 0.0 0.0 ns CLKn_DELAY = 1 [1] 0.4 0.5 0.8 ns CLKn_DELAY = 2 [1] 0.7 1.0 1.7 ns CLKn_DELAY = 3 [1] 1.1 1.6 2.5 ns CLKn_DELAY = 4 [1] 1.4 2.0 3.3 ns CLKn_DELAY = 5 [1] 1.7 2.6 4.1 ns CLKn_DELAY = 6 [1] 2.1 3.1 4.9 ns CLKn_DELAY = 7 [1] 2.5 3.6 5.8 ns Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC43xx User manual). The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY. All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 124 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_CLKn delay > 0 EMC_CLKn delay td; programmable CLKn_DELAY Tcy(clk) EMC_CLKn delay = 0 td(xV) - td EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) - td th(x) td(QV) - td td(QV) th(Q) - td th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read; delay > 0 tsu(D) th(D) EMC_D[31:0] read; delay = 0 002aag703 For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 31. Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK register. Fig 34. SDRAM timing LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 125 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.17 USB interface Table 32. Dynamic characteristics: USB0 and USB1 pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO); 3.0 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 4 - 20 ns tf fall time 10 % to 90 % 4 - 20 ns tFRFM differential rise and fall time matching tr / tf 90 - 111.11 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 35 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 35 2 - +5 ns tJR1 receiver jitter to next transition 18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns tEOPR1 EOP width at receiver must reject as EOP; see Figure 35 [1] 40 - - ns tEOPR2 EOP width at receiver must accept as EOP; see Figure 35 [1] 82 - - ns [1] Characterized but not implemented as production test. Guaranteed by design. TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 35. Differential data-to-EOP transition skew and EOP width LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 126 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 33. Symbol Static characteristics: USB0 PHY pins[1] Parameter Conditions Min Typ Max Unit - 68 - mW - 18 - mA High-speed mode Pcons [2] power consumption IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER; [3] total supply current IDDD during transmit - 31 - mA during receive - 14 - mA with driver tri-stated - 14 - mA - 7 - mA - 15 - mW digital supply current Full-speed/low-speed mode Pcons IDDA(3V3) analog supply current (3.3 V) IDDD [2] power consumption on pin USB0_VDDA3V3_DRIVER; total supply current - 3.5 - mA during transmit - 5 - mA during receive - 3 - mA with driver tri-stated - 3 - mA - 3 - mA - 24 - A with driver tri-stated - 24 - A with OTG functionality enabled - 3 - mA - 30 - A 4.4 - - V digital supply current Suspend mode IDDA(3V3) analog supply current (3.3 V) IDDD digital supply current VBUS detector outputs threshold voltage Vth Vhys [1] hysteresis voltage for VBUS valid for session end 0.2 - 0.8 V for A valid 0.8 - 2 V for B valid 2 - 4 V for session end - 150 10 mV A valid - 200 10 mV B valid - 200 10 mV Characterized but not implemented as production test. [2] Total average power consumption. [3] The driver is active only 20 % of the time. 11.18 Ethernet Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply with the IEEE standard 802.3. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 127 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 34. Dynamic characteristics: Ethernet Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit [1] - 50 MHz clock duty cycle [1] 50 50 % tsu set-up time for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 4 - ns th hold time for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 2 - ns clock frequency for ENET_TX_CLK [1] - 25 MHz [1] RMII mode clock frequency fclk clk for ENET_RX_CLK MII mode fclk clk clock duty cycle 50 50 % tsu set-up time for ENET_TXDn, ENET_TX_EN, ENET_TX_ER [1][2] 4 - ns th hold time for ENET_TXDn, ENET_TX_EN, ENET_TX_ER [1][2] 2 - ns fclk clock frequency for ENET_RX_CLK [1] - 25 MHz clock duty cycle [1] 50 50 % tsu set-up time for ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 4 - ns th hold time for ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] 2 - ns clk [1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input capacitance of the receiving device. [2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or output level. ENET_RX_CLK ENET_TX_CLK ENET_RXD[n] ENET_RX_DV ENET_RX_ER ENET_TXD[n] ENET_TX_EN ENET_TX_ER tsu th 002aag210 Fig 36. Ethernet timing LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 128 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.19 SD/MMC Table 35. Dynamic characteristics: SD/MMC Tamb = 40 C to 85 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V, CL = 20 pF. SAMPLE_DELAY = 0x9, DRV_DELAY = 0xD in the SDDELAY register sampled at 90 % and 10 % of the signal level, EHS = 1 for SD_CLK pin, EHS = 1 for SD_DATn and SD_CMD pins. Simulated values. Symbol Parameter Conditions Min Max Unit 52 MHz 3.9 - ns fclk clock frequency on pin SD_CLK; data transfer mode tsu(D) data input set-up time on pins SD_DATn as inputs on pins SD_CMD as inputs 5.2 - ns th(D) data input hold time on pins SD_DATn as inputs 0.4 - ns on pins SD_CMD as inputs 0 - ns td(QV) data output valid delay time on pins SD_DATn as outputs 15.3 ns on pins SD_CMD as outputs - 16 ns th(Q) data output hold time on pins SD_DATn as outputs 4 - ns on pins SD_CMD as outputs 4 - ns Tcy(clk) SD_CLK td(QV) th(Q) SD_CMD (O) SD_DATn (O) tsu(D) th(D) SD_CMD (I) SD_DATn (I) 002aag204 Fig 37. SD/MMC timing 11.20 LCD Table 36. Dynamic characteristics: LCD Tamb = 25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values. Symbol Parameter LPC43S70 Product data sheet fclk clock frequency td(QV) data output valid delay time th(Q) data output hold time Conditions Min Typ Max Unit on pin LCD_DCLK - 50 - MHz - 17 ns All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 8.5 - ns © NXP B.V. 2016. All rights reserved. 129 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 12. ADC/DAC electrical characteristics Table 37. 12-bit ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter VDC DC input common mode level Cin input capacitance Ri Conditions Min Typ Max Unit 0.1 0.5 0.9 V single ended - 4.5 - pF input resistance single ended; per selected positive or negative input pin - 5 - k Vi(range) input voltage range differential, peak-to-peak 0.72 0.8 0.88 V fc(ADC) ADC conversion frequency 12-bit resolution - - 80 MSamples/s fc(ADC) = 10 Msamples/s; fin = 1 MHz; bias current bits CRS[3:0] = 0000[1] INL integral non-linearity - 1.1 - LSB DNL differential non-linearity - 0.7 - LSB ENOB effective number of bits - 10.4 - - SNR signal-to-noise ratio - 64.0 - dB THD total harmonic distortion - -73 - dB SFDR spurious free dynamic range - 80 - dB HD2 second harmonic distortion - -84 - dB HD3 third harmonic distortion - -75 - dB fc(ADC) = 60 Msamples/s; fin = 1 MHz; bias current bits CRS[3:0] = 0011[1] INL integral non-linearity - 1.2 - LSB DNL differential non-linearity - 0.7 - LSB ENOB effective number of bits - 10.1 - - SNR signal-to-noise ratio - 63 - dB THD total harmonic distortion - -72 - dB SFDR spurious free dynamic range - 75 - dB HD2 second harmonic distortion - -79 - dB HD3 third harmonic distortion - -75 - dB [1] fin = signal input frequency. The bias current is programmable. Higher bias current allows for a higher ADC conversion frequency at higher power consumption. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 130 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 38. 10-bit ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max VIA Cia ED differential linearity error 2.7 V  VDDA(3V3)  3.6 V EL(adj) integral non-linearity analog input voltage 0 - VDDA(3V3) V analog input capacitance - - 2 pF [1][2] - 0.8 - LSB - 1.0 - LSB [3] - 0.8 - LSB 2.2 V  VDDA(3V3) < 2.7 V 2.7 V  VDDA(3V3)  3.6 V - 1.5 - LSB [4] - 0.15 - LSB - 0.15 - LSB [5] - 0.3 - % - 0.35 - % - 3 - LSB LSB 2.2 V  VDDA(3V3) < 2.7 V EO offset error EG gain error 2.7 V  VDDA(3V3)  3.6 V 2.2 V  VDDA(3V3) < 2.7 V 2.7 V  VDDA(3V3)  3.6 V 2.2 V  VDDA(3V3) < 2.7 V 2.7 V  VDDA(3V3)  3.6 V ET absolute error Rvsi voltage source interface see Figure 39 resistance Ri input resistance fclk(ADC) ADC clock frequency fc(ADC) ADC conversion frequency [6] 2.7 V  VDDA(3V3)  3.6 V [7][8] 10-bit resolution; 11 clock cycles Unit - 4 - - - 1/(7  fclk(ADC) k  Cia) - - 1.2 M - - 4.5 MHz - - 400 kSamples/s 1.5 MSamples/s 2-bit resolution; 3 clock cycles [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 38. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 38. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 38. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 38. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 38. [7] Tamb = 25 C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 2 pF. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 2 k + 1 / (fs  Cia). LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 131 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA(3V3) − VSSA 1024 002aaf959 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. (6) VDDA refers to VDDA(3V3) on pin VDDA and VSSA to analog ground on pin VSSA. Fig 38. 10-bit ADC characteristics LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 132 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Rvsi LPC43Sxx 2 kΩ (analog pin) 2.2 kΩ (multiplexed pin) ADC0_n/ADC1_n Rs ADC COMPARATOR Cia = 2 pF VEXT VSS aaa-016400 Rs  1/((7  fclk(ADC)  Cia)  2 k Fig 39. ADC interface to pins Table 39. DAC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified Symbol ED Parameter Conditions differential linearity error 2.7 V  VDDA(3V3)  3.6 V [1] 2.2 V  VDDA(3V3) < 2.7 V EL(adj) integral non-linearity code = 0 to 975 [1] Min Typ Max Unit - 0.8 - LSB - 1.0 - LSB - 1.0 - LSB - 1.5 - LSB - 0.8 - LSB - 1.0 - LSB - 0.3 - % - 1.0 - % - - 200 pF 1 - - k 2.7 V  VDDA(3V3)  3.6 V 2.2 V  VDDA(3V3) < 2.7 V offset error EO 2.7 V  VDDA(3V3)  3.6 V [1] 2.2 V  VDDA(3V3) < 2.7 V gain error EG 2.7 V  VDDA(3V3)  3.6 V [1] 2.2 V  VDDA(3V3) < 2.7 V CL load capacitance RL load resistance [1] settling time ts [1] In the DAC CR register, bit BIAS = 0 (see the LPC43xx user manual). [2] Settling time is calculated within 1/2 LSB of the final value. LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 0.4 s © NXP B.V. 2016. All rights reserved. 133 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13. Application information 13.1 LCD panel signal usage Table 40. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin used LCD function LCD_VD[23:8] - - - - - - LCD_VD7 - - P8_4 UD[7] P8_4 UD[7] LCD_VD6 - - P8_5 UD[6] P8_5 UD[6] LCD_VD5 - - P8_6 UD[5] P8_6 UD[5] LCD_VD4 - - P8_7 UD[4] P8_7 UD[4] LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3] LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2] LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1] LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0] LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP LCD_ENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE LCD_PWR P7_7 CDPWR P7_7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN Table 41. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin used LCD function LCD_VD[23:16] - - - - - - LCD_VD15 - - PB_4 LD[7] PB_4 LD[7] LCD_VD14 - - PB_5 LD[6] PB_5 LD[6] LCD_VD13 - - PB_6 LD[5] PB_6 LD[5] LCD_VD12 - - P8_3 LD[4] P8_3 LD[4] LCD_VD11 P4_9 LD[3] P4_9 LD[3] P4_9 LD[3] LCD_VD10 P4_10 LD[2] P4_10 LD[2] P4_10 LD[2] LCD_VD9 P4_8 LD[1] P4_8 LD[1] P4_8 LD[1] LCD_VD8 P7_5 LD[0] P7_5 LD[0] P7_5 LD[0] LCD_VD7 - - UD[7] P8_4 UD[7] LCD_VD6 - - P8_5 UD[6] P8_5 UD[6] LCD_VD5 - - P8_6 UD[5] P8_6 UD[5] LCD_VD4 - - P8_7 UD[4] P8_7 UD[4] LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3] LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 134 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 41. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin used LCD function LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2] LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1] LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0] LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP LCD_ENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM P4_6 LCDENAB/ LCDM LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN Table 42. External pin LCD panel connections for TFT panels TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC43xx pin used LCD function LPC43xx pin used LCD function LPC43xx pin LCD used function LPC43xx pin used LCD function LCD_VD23 PB_0 BLUE3 PB_0 BLUE4 PB_0 BLUE4 PB_0 BLUE7 LCD_VD22 PB_1 BLUE2 PB_1 BLUE3 PB_1 BLUE3 PB_1 BLUE6 LCD_VD21 PB_2 BLUE1 PB_2 BLUE2 PB_2 BLUE2 PB_2 BLUE5 LCD_VD20 PB_3 BLUE0 PB_3 BLUE1 PB_3 BLUE1 PB_3 BLUE4 LCD_VD19 - - P7_1 BLUE0 P7_1 BLUE0 P7_1 BLUE3 LCD_VD18 - - - - P7_2 intensity P7_2 BLUE2 LCD_VD17 - - - - - - P7_3 BLUE1 LCD_VD16 - - - - - - P7_4 BLUE0 LCD_VD15 PB_4 GREEN3 PB_4 GREEN5 PB_4 GREEN4 PB_4 GREEN7 LCD_VD14 PB_5 GREEN2 PB_5 GREEN4 PB_5 GREEN3 PB_5 GREEN6 LCD_VD13 PB_6 GREEN1 PB_6 GREEN3 PB_6 GREEN2 PB_6 GREEN5 LCD_VD12 P8_3 GREEN0 P8_3 GREEN2 P8_3 GREEN1 P8_3 GREEN4 LCD_VD11 - P4_9 GREEN1 P4_9 GREEN0 P4_9 GREEN3 - LCD_VD10 - - P4_10 GREEN0 P4_10 intensity P4_10 GREEN2 LCD_VD9 - - - - - - P4_8 GREEN1 LCD_VD8 - - - - - - P7_5 GREEN0 LCD_VD7 P8_4 RED3 P8_4 RED4 P8_4 RED4 P8_4 RED7 LCD_VD6 P8_5 RED2 P8_5 RED3 P8_5 RED3 P8_5 RED6 LCD_VD5 P8_6 RED1 P8_6 RED2 P8_6 RED2 P8_6 RED5 LCD_VD4 P8_7 RED0 P8_7 RED1 P8_7 RED1 P8_7 RED4 LCD_VD3 - - P4_2 RED0 P4_2 RED0 P4_2 RED3 LCD_VD2 - - - - P4_3 intensity P4_3 RED2 LCD_VD1 - - - - - - P4_4 RED1 LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 135 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 42. External pin LCD panel connections for TFT panels TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC43xx pin used LPC43xx pin used LPC43xx pin LCD used function LCD function LCD function LPC43xx pin used LCD function LCD_VD0 - - - - - - P4_1 RED0 LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP LCDENAB/ LCDM P4_6 LCDENAB/ P4_6 LCDM LCD_ENAB P4_6 /LCDM LCDENAB/ P4_6 LCDM LCD_FP P4_5 LCDENAB/ LCDM LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN 13.2 Crystal oscillator The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see LPC43xx user manual). The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The oscillator can operate in one of two modes: slave mode and oscillation mode. • In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (CC in Figure 40), with an amplitude of at least 200 mV (rms). The XTAL2 pin in this configuration can be left unconnected. • External components and models used in oscillation mode are shown in Figure 41, and in Table 43 and Table 44. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 41 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the crystal manufacturer. Table 43. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency 2 MHz 4 MHz 8 MHz LPC43S70 Product data sheet Maximum crystal series resistance RS External load capacitors CX1, CX2 < 200  33 pF, 33 pF < 200  39 pF, 39 pF < 200  56 pF, 56 pF < 200  18 pF, 18 pF < 200  39 pF, 39 pF < 200  56 pF, 56 pF < 200  18 pF, 18 pF < 200  39 pF, 39 pF All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 136 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 43. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency Maximum crystal series resistance RS External load capacitors CX1, CX2 12 MHz < 160  18 pF, 18 pF < 160  39 pF, 39 pF 16 MHz < 120  18 pF, 18 pF < 80  33 pF, 33 pF > LPC43S70 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 15 March 2016 © NXP B.V. 2016. All rights reserved. 156 of 157 LPC43S70 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.21.2 Alarm timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.22 System control . . . . . . . . . . . . . . . . . . . . . . . . 80 7.22.1 Configuration registers (CREG) . . . . . . . . . . . 80 7.22.2 System Control Unit (SCU). . . . . . . . . . . . . . . 80 7.22.3 Clock Generation Unit (CGU) . . . . . . . . . . . . . 80 7.22.4 Internal RC oscillator (IRC). . . . . . . . . . . . . . . 81 7.22.5 PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 81 7.22.6 PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 81 7.22.7 System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.22.8 Reset Generation Unit (RGU). . . . . . . . . . . . . 81 7.22.9 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.22.9.1 Memory retention in Power-down modes . . . . 82 7.22.9.2 Power Management Controller (PMC) . . . . . . 83 7.23 Serial Wire Debug/JTAG. . . . . . . . . . . . . . . . . 84 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 85 9 Thermal characteristics . . . . . . . . . . . . . . . . . 86 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 87 10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 94 10.2 Peripheral power consumption . . . . . . . . . . . . 98 10.3 BOD and band gap static characteristics . . . 100 10.4 Electrical pin characteristics . . . . . . . . . . . . . 102 11 Dynamic characteristics . . . . . . . . . . . . . . . . 106 11.1 Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 106 11.2 External clock for oscillator in slave mode . . 106 11.3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 107 11.4 IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107 11.5 GPCLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.6 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.7 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 109 11.8 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.9 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 110 11.10 USART interface. . . . . . . . . . . . . . . . . . . . . . 111 11.11 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 113 11.12 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.13 SSP/SPI timing diagrams . . . . . . . . . . . . . . . 117 11.14 SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.15 SGPIO timing . . . . . . . . . . . . . . . . . . . . . . . . 119 11.16 External memory interface . . . . . . . . . . . . . . 121 11.17 USB interface . . . . . . . . . . . . . . . . . . . . . . . 126 11.18 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.19 SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.20 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12 ADC/DAC electrical characteristics . . . . . . . 130 13 Application information. . . . . . . . . . . . . . . . . 134 13.1 LCD panel signal usage . . . . . . . . . . . . . . . . 134 13.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 136 13.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 138 13.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . 138 13.5 13.6 13.7 13.8 13.9 13.9.1 13.9.2 13.9.3 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Standard I/O pin configuration . . . . . . . . . . . Reset pin configuration . . . . . . . . . . . . . . . . Suggested USB interface solutions . . . . . . . Minimizing interference between digital signals and 12-bit ADC signals . . . . . . . . . . 12-bit ADCHS input selection . . . . . . . . . . . Inverting single-ended circuit . . . . . . . . . . . . Non-inverting single-ended circuit with gain = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-inverting single-ended circuit for input 0 V to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 139 139 142 142 144 145 146 147 149 151 152 153 154 154 154 154 155 155 156 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 March 2016 Document identifier: LPC43S70