LPC51U68
32-bit ARM Cortex-M0+ MCU; 96 KB SRAM; 256 KB flash,
Crystal-less USB operation, Flexcomm Interface, 32-bit
counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC,
Temperature sensor
Rev. 1.5 — 13 January 2020
Product data sheet
1. General description
The LPC51U68 are ARM Cortex-M0+ based microcontrollers for embedded applications.
These devices include 96 KB of on-chip SRAM, 256 KB on-chip flash, full-speed USB
device interface, an I2S, three general-purpose timers, one versatile timer with PWM and
many other capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate
Timer (MRT), a Windowed Watchdog Timer (WWDT), eight flexible serial communication
peripherals (each of which can be a USART, SPIs, or I2C interface), one 12-bit 5.0
Msamples/sec ADC, and a temperature sensor.
The LPC51U68 LQFP64 devices are pin-function compatible with LPC5410x and
LPC5411x devices in the same package/pinout versions.
2. Features and benefits
ARM Cortex-M0+ processor, running at a frequency of up to 150 MHz.
Single cycle multiplier.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) with a selection of sources.
Serial Wire Debug (SWD) with 4 breakpoints and 2 watchpoints.
System tick timer.
On-Chip memory:
256 KB on-chip flash programming memory with flash accelerator and 256 Byte
page write and erase.
Up to 96 KB total SRAM composed of up to 64 KB main SRAM, plus an additional
32 KB SRAM.
ROM API support:
Flash In-Application Programming (IAP) and In-System Programming (ISP).
ROM-based USB drivers (HID, CDC, MSC, DFU). Flash updates via USB.
Booting from valid user code in flash, USART, SPI, and I2C.
Legacy, Single, and Dual image boot.
LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Serial interfaces:
Eight Flexcomm Interface serial peripherals. Each can be selected by software to
be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S
interface, for a total of 2 channel pairs. Each Flexcomm Interface includes a FIFO
that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A
variety of clocking options are available to each Flexcomm Interface, and include a
shared Fractional Rate Generator.
I2C supports Fast mode and Fast-mode Plus with data rates of up to 1 Mbit/s and
with multiple address recognition and monitor mode. Two sets of true open drain
I2C pins also support high-speed Mode (up to 3.4 Mbit/s) as a slave.
USB 2.0 full-speed host or device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode using software library.
See Technical note TN00035 for more details.
Digital peripherals:
DMA controller with 18 channels and 16 programmable triggers, able to access all
memories and DMA-capable peripherals.
Up to 48 General-Purpose I/O (GPIO) pins. Most GPIOs have configurable
pull-up/pull-down resistors, open-drain mode, and input inverter.
GPIO registers are located on AHB for fast access.
Up to four GPIOs can be selected as pin interrupts (PINT), triggered by rising,
falling or both input edges.
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
CRC engine.
Analog peripherals:
12-bit ADC with 12 input channels and with multiple internal and external trigger
inputs and sample rates of up to 5.0 MS/s. The ADC supports two independent
conversion sequences.
Integrated temperature sensor connected to the ADC.
Timers
Three standard general purpose timers/counters, four of which support up to 4
capture inputs and 4 compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests.
One SCTimer/PWM (SCT) 8 input and 8 output functions (including capture and
match). Inputs and outputs can be routed to/from external pins and internally
to/from selected peripherals. Internally, the SCT supports 10 captures/matches, 10
events and 10 states.
32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including deep power-down, with 1 ms resolution.
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
Windowed Watchdog timer (WWDT).
Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be
used to wake up the device from most low power modes.
LPC51U68
Product data sheet
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Clock generation:
Internal FRO oscillator, factory trimmed for accuracy, that can optionally be used as
a system clock as well as other purposes. This oscillator provides a selectable 48
MHz or 96 MHz output, and a 12 MHz output (divided down from the selected
higher frequency) that can optionally be used as a system clock as well as other
purposes.
External clock input for up to 25 MHz.
Watchdog oscillator with a frequency range of 6 kHz to 1.5 MHz.
32 kHz low-power RTC oscillator.
System PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency external clock. May be run from the internal FRO 12 MHz
output, the external clock input CLKIN, or the RTC oscillator.
Clock output function with divider that can reflect many internal clocks.
Frequency measurement unit for measuring the frequency of any on-chip or
off-chip clock signal.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption.
Reduced power modes: sleep mode, deep-sleep mode, and deep power-down
mode.
Wake-up from deep-sleep mode on activity on USART, SPI, and I2C peripherals
when operating as slaves.
Wake-up from sleep, deep-sleep and deep power-down modes from the RTC
alarm.
The Micro-tick Timer can wake-up the device from most reduced power modes by
using the watchdog oscillator when no other on-chip resources are running, for
ultra-low power wake-up.
Power-On Reset (POR).
Brownout detect.
JTAG boundary scan supported.
Unique device serial number for identification.
Single power supply 1.62 V to 3.6 V.
Operating temperature range of -40°C to +105°C.
Available as LQFP64 and LQFP48 packages.
LPC51U68
Product data sheet
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Rev. 1.5 — 13 January 2020
© NXP Semiconductors N.V. 2020. All rights reserved.
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3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC51U68JBD48
LQFP48
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm
SOT313-2
LPC51U68JBD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm
SOT314-2
3.1 Ordering options
Table 2.
Ordering options
Type number
Flash in KB
SRAM in KB
GPIO
SRAMX
SRAM0
Total
LPC51U68JBD48
256
32
64
96
37
LPC51U68JBD64
256
32
64
96
48
4. Marking
Terminal 1
index area
n
Terminal 1 index area
Fig 1.
1
aaa-011231
aaa-015675
LQFP48 and LQFP64 package marking
LPC51U68
Product data sheet
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32-bit ARM Cortex-M0+ microcontroller
The LPC51U68 LQFP48 and LQFP64 packages have the following top-side marking:
•
•
•
•
•
First line: LPC51U68
Second line: JBD48
Third line: xx xx
Fourth line: xxxyy
Fifth: wwxR[x]
– yyww: Date code with yy = year and ww = week.
– xR = Boot code version and device revision.
•
•
•
•
First line: LPC51U68
Second line: JBD64
Third line: xxxxxxxxxxxx
Fourth line: xxxyywwx[R]x
– yyww: Date code with yy = year and ww = week.
– xR = Boot code version and device revision.
Table 3.
Device revision table
Device revision
Revision description
0A
Initial device revision with boot code version 18.0.
LPC51U68
Product data sheet
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Rev. 1.5 — 13 January 2020
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32-bit ARM Cortex-M0+ microcontroller
5. Block diagram
Serial Wire
Debug
JTAG
boundary scan
USB bus
CLKIN
CLKOUT
RESET
DEBUG INTERFACE
POWER-ON-RESET
USB FS
DEVICE
CONTROLLER
ARM
CORTEX M0+
CLOCK GENERATION,
BROWNOUT DETECT
POWER CONTROL,
AND OTHER
INTERNAL OSCILLATOR
SYSTEM FUNCTIONS
SYSTEM
DMA
CONTROLLER
SYSTEM PLL
FLASH
ACCELERATOR
FLASH
256 KB
BOOT AND DRIVER
ROM 32 KB
SRAMX
32 KB
SRAM0
64 KB
DMA
REGISTERS
GPIO
SCTIMER/PWM
USB
REGISTERS
CRC
ENGINE
FLEXCOMM Interfaces
0 THROUGH 4(1)
FLEXCOMM Interfaces
5 THROUGH 7(1)
ADC: 5 Ms/s, 12 BIT, 12 ch.
MULTILAYER AHB MATRIX
TEMPERATURE SENSOR
2x 32-BIT TIMER (TIMER 3)
ASYNC APB
BRIDGE
APB
BRIDGE 0
GPIO PIN INTERRUPTS
APB
BRIDGE 1
SYSTEM FUNCTIONS: CLOCKING,
RESET, POWER, FLASH, ETC.
2x 32-BIT TIMER (TIMER 0, 1)
I/O CONFIGURATION
WATCHDOG
OSCILLATOR
WINDOWED
WATCHDOG
MICRO TICK
TIMER
GPIO GROUP INTERRUPTS 0 AND 1
PERIPHERAL INPUT MUXES
MULTI-RATE TIMER
FREQUENCY MEASUREMENT UNIT
PMU REGISTERS
FLASH REGISTERS
RTC Power Domain
REAL TIME
CLOCK,
ALARM AND
WAKEUP
32.768 kHz
OSCILLATOR
FRACTIONAL RATE GENERATOR
aaa-028910
Fig 2.
LPC51U68 Block diagram
LPC51U68
Product data sheet
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32-bit ARM Cortex-M0+ microcontroller
6. Pinning information
33 RTCXIN
34 VDD
35 RTCXOUT
36 PIO0_2
37 PIO0_3
38 PIO0_4
39 PIO0_5
40 PIO0_6
41 PIO0_7
42 PIO1_11
43 PIO0_8
44 PIO0_9
45 PIO0_10
46 PIO0_11
47 PIO0_12
48 PIO0_13
6.1 Pinning
PIO0_14 49
32 PIO0_1
PIO0_15 50
31 PIO0_0
PIO1_12 51
30 PIO1_10
SWCLK/ PIO0_16 52
29 PIO1_9
SWDIO/ PIO0_17 53
28 PIO1_8
PIO1_13 54
27 PIO1_7
VSS 55
26 PIO1_6
VDD 56
25 VSS
LPC51U68
PIO1_2 16
PIO1_1 15
PIO1_0 14
PIO0_31 13
PIO0_30 12
17 PIO1_3
PIO0_29 11
18 PIO1_4
RESET 64
PIO1_17 10
PIO0_22 63
VSS 9
19 PIO1_5
VDD 8
20 VSSA
PIO1_15 62
PIO1_16 7
PIO0_21 61
USB_DM 6
21 VREFN
USB_DP 5
22 VREFP
PIO0_20 60
PIO0_26 4
PIO0_19 59
PIO0_25 3
23 VDDA
PIO0_24 2
24 VDD
PIO0_18 58
PIO0_23 1
PIO1_14 57
aaa-028915
Fig 3.
LPC51U68
Product data sheet
LQFP64 Pin configuration
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Rev. 1.5 — 13 January 2020
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LPC51U68
Product data sheet
37 PIO0_14
38 PIO0_15
39 SWCLK/PIO0_16
40 SWDIO/PIO0_17
41 VSS
42 VDD
43 PIO0_18
44 PIO0_19
45 PIO0_20
46 PIO0_21
PIO0_23
1
36 PIO0_13
PIO0_24
2
35 PIO0_12
PIO0_25
3
34 PIO0_11
PIO0_26
4
33 PIO0_10
USB_DP
5
32 PIO0_9
USB_DM
6
PIO0_29
7
PIO0_30
8
29 PIO0_6
PIO0_31
9
28 PIO0_5
PIO1_0 10
27 PIO0_4
PIO1_1 11
26 RTCXOUT
PIO1_2 12
25 RTCXIN
31 PIO0_8
PIO0_1 24
PIO0_0 23
PIO1_8 22
30 PIO0_7
PIO1_7 21
PIO1_6 20
VSS 19
VDD 18
VDDA 17
VSSA 16
PIO1_5 15
PIO1_4 14
LPC51U68
PIO1_3 13
Fig 4.
47 PIO0_22
48 RESET
32-bit ARM Cortex-M0+ microcontroller
aaa-028916
LQFP48 Pin configuration
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32-bit ARM Cortex-M0+ microcontroller
6.2 Pin description
On the LPC51U68, digital pins are grouped into two ports. Each digital pin may support up
to four different digital functions and one analog function, including General Purpose I/O
(GPIO).
Pin description
31
23
Reset state [1]
48-pin
PIO0_0
64-pin
Symbol
[2]
Description
Type
Table 4.
PU I/O
PIO0_0 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm Interface 0 USART RXD
function.
I/O
FC0_RXD_SDA_MOSI — Flexcomm Interface 0: USART RXD, I2C SDA, SPI
MOSI.
I/O
FC3_CTS_SDA_SSEL0 — Flexcomm Interface 3: USART CTS, I2C SDA, SPI
SSEL0.
I
CTimer0_CAP0 — 32-bit CTimer0 capture input 0.
R — Reserved.
O
PIO0_1
32
24
[2]
PU I/O
SCT0_OUT3 — SCT0 output 3. PWM output 3.
PIO0_1 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm Interface 0 USART TXD
function.
I/O
FC0_TXD_SCL_MISO — Flexcomm Interface 0: USART TXD, I2C SCL, SPI MISO.
I/O
FC3_RTS_SCL_SSEL1 — Flexcomm Interface 3: USART RTS, I2C SCL, SPI
SSEL1.
I
CTimer0_CAP1 — 32-bit CTimer0 capture input 1.
R — Reserved.
O
PIO0_2
PIO0_3
PIO0_4
36
37
38
-
-
27
[2]
[2]
[2]
PU I/O
SCT0_OUT1 — SCT0 output 1. PWM output 1.
PIO0_2 — General-purpose digital input/output pin.
I/O
FC0_CTS_SDA_SSEL0 — Flexcomm Interface 0: USART CTS, I2C SDA, SPI
SSEL0.
I/O
FC3_SSEL3 — Flexcomm Interface 3: SPI SSEL3.
PU I/O
PIO0_3 — General-purpose digital input/output pin.
I/O
FC0_RTS_SCL_SSEL1 — Flexcomm Interface 0: USART RTS, I2C SCL, SPI
SSEL1.
I/O
FC2_SSEL2 — Flexcomm Interface 2: SPI SSEL2.
O
CTimer1_MAT3 — 32-bit CTimer1 match output 3.
PU I/O
PIO0_4 — General-purpose digital input/output pin.
Remark: The state of this pin at Reset in conjunction with PIO0_31 and PIO1_6 will
determine the boot source for the part or if ISP handler is invoked. See the Boot
Process chapter in UM11071 for more details.
LPC51U68
Product data sheet
I/O
FC0_SCK — Flexcomm Interface 0: USART or SPI clock.
I/O
FC3_SSEL2 — Flexcomm Interface 3: SPI SSEL2.
I
CTimer0_CAP2 — 32-bit CTimer0 capture input 2.
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32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
PIO0_6
39
28
40
29
Reset state [1]
48-pin
PIO0_5
64-pin
Symbol
[2]
[2]
Description
Type
Table 4.
PU I/O
PIO0_5 — General-purpose digital input/output pin.
I/O
FC6_RXD_SDA_MOSI_DATA — Flexcomm Interface 6: USART RXD, I2C SDA,
SPI MOSI, I2S data.
O
SCT0_OUT6 — SCT0 output 6. PWM output 6.
O
CTimer0_MAT0 — 32-bit CTimer0 match output 0.
PU I/O
I/O
PIO0_6 — General-purpose digital input/output pin.
FC6_TXD_SCL_MISO_WS — Flexcomm Interface 6: USART TXD, I2C SCL, SPI
MISO, I2S WS.
R — Reserved.
O
CTimer0_MAT1 — 32-bit CTimer0 match output 1.
R — Reserved.
I
PIO0_7
41
30
[2]
PU I/O
UTICK_CAP0 — Micro-tick timer capture input 0.
PIO0_7 — General-purpose digital input/output pin.
I/O
FC6_SCK — Flexcomm Interface 6: USART, SPI, or I2S clock.
O
SCT0_OUT0 — SCT0 output 0. PWM output 0.
O
CTimer0_MAT2 — 32-bit CTimer0 match output 2.
R — Reserved.
I
PIO0_8
43
31
[2]
PU I/O
I/O
PIO0_9
44
32
[2]
CTimer0_CAP2 — 32-bit CTimer0 capture input 2.
PIO0_8 — General-purpose digital input/output pin.
FC2_RXD_SDA_MOSI — Flexcomm Interface 2: USART RXD, I2C SDA, SPI
MOSI.
O
SCT0_OUT1 — SCT0 output 1. PWM output 1.
O
CTimer0_MAT3 — 32-bit CTimer0 match output 3.
PU I/O
I/O
PIO0_9 — General-purpose digital input/output pin.
FC2_TXD_SCL_MISO — Flexcomm Interface 2: USART TXD, I2C SCL, SPI MISO.
O
SCT0_OUT2 — SCT0 output 2. PWM output 2.
I
CTimer3_CAP0 — 32-bit CTimer3 capture input 0.
R — Reserved.
I/O
PIO0_10
PIO0_11
45
46
LPC51U68
Product data sheet
33
34
[2]
[2]
PU I/O
FC3_CTS_SDA_SSEL0 — Flexcomm Interface 3: USART CTS, I2C SDA, SPI
SSEL0.
PIO0_10 — General-purpose digital input/output pin.
I/O
FC2_SCK — Flexcomm Interface 2: USART or SPI clock.
O
SCT0_OUT3 — SCT0 output 3. PWM output 3.
O
CTimer3_MAT0 — 32-bit CTimer3 match output 0.
PU I/O
PIO0_11 — General-purpose digital input/output pin. In ISP mode, this pin is set to
the Flexcomm 3 SPI SCK function.
I/O
FC3_SCK — Flexcomm Interface 3: USART or SPI clock.
I/O
FC6_RXD_SDA_MOSI_DATA — Flexcomm Interface 6: USART RXD, I2C SDA,
SPI MOSI, I2S DATA.
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32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
PIO0_13
PIO0_14/
TCK
47
35
48
49
36
37
Reset state [1]
48-pin
PIO0_12
64-pin
Symbol
[2]
[2]
[2]
Description
Type
Table 4.
PU I/O
PIO0_12 — General-purpose digital input/output pin. In ISP mode, this pin is set to
the Flexcomm 3 SPI MOSI function.
I/O
FC3_RXD_SDA_MOSI — Flexcomm Interface 3: USART RXD, I2C SDA, SPI
MOSI.
I/O
FC6_TXD_SCL_MISO_WS — Flexcomm Interface 6: USART TXD, I2C SCL, SPI
MISO, I2S WS.
PU I/O
PIO0_13 — General-purpose digital input/output pin. In ISP mode, this pin is set to
the Flexcomm 3 SPI MISO function.
I/O
FC3_TXD_SCL_MISO — Flexcomm Interface 3: USART TXD, I2C SCL, SPI MISO.
O
SCT0_OUT4 — SCT0 output 4. PWM output 4.
PU I/O
PIO0_14 — General-purpose digital input/output pin. In boundary scan mode: TCK
(Test Clock In). In ISP mode, this pin is set to the Flexcomm 3 SPI SSELN0 function.
I/O
FC3_CTS_SDA_SSEL0 — Flexcomm Interface 3: USART CTS, I2C SDA, SPI
SSEL0.
O
SCT0_OUT5 — SCT0 output 5. PWM output 5.
R — Reserved.
R — Reserved.
I/O
PIO0_15/
TDO
50
38
[2]
PU I/O
I/O
FC1_SCK — Flexcomm Interface 1: USART or SPI clock.
PIO0_15 — General-purpose digital input/output pin. In boundary scan mode: TDO
(Test Data Out).
FC3_RTS_SCL_SSEL1 — Flexcomm Interface 3: USART RTS, I2C SCL, SPI
SSEL1.
R — Reserved.
R — Reserved.
R — Reserved.
I/O
SWCLK/
PIO0_16
52
39
[2]
PU I/O
FC4_SCK — Flexcomm Interface 4: USART or SPI clock.
PIO0_16 — General-purpose digital input/output pin.
I/O
FC3_SSEL2 — Flexcomm Interface 3: SPI SSEL2.
I/O
FC6_CTS_SDA_SSEL0 — Flexcomm Interface 6: USART CTS, I2C SDA, SPI
SSEL0.
O
CTimer3_MAT1 — 32-bit CTimer3 match output 1.
R — Reserved.
I/O
SWCLK — Serial Wire Clock. JTAG Test Clock. This is the default function after
booting.
R — Reserved.
LPC51U68
Product data sheet
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Rev. 1.5 — 13 January 2020
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32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
53
40
Reset state [1]
48-pin
SWDIO/
PIO0_17
64-pin
Symbol
[2]
Description
Type
Table 4.
PU I/O
PIO0_17 — General-purpose digital input/output pin.
I/O
FC3_SSEL3 — Flexcomm Interface 3: SPI SSEL3.
I/O
FC6_RTS_SCL_SSEL1 — Flexcomm Interface 6: USART RTS, I2C SCL, SPI
SSEL1.
O
CTimer3_MAT2 — 32-bit CTimer3 match output 2.
R — Reserved.
I/O
PIO0_18/
TRST
PIO0_19/
TDI
PIO0_20/
TMS
PIO0_21
PIO0_22
PIO0_23
58
59
60
61
63
1
43
44
45
46
47
1
[2]
[2]
[2]
[2]
[2]
[3]
SWDIO — Serial Wire Debug I/O. This is the default function after booting.
PU I/O
PIO0_18 — General-purpose digital input/output pin. In boundary scan mode: TRST
(Test Reset).
I/O
FC5_TXD_SCL_MISO — Flexcomm Interface 5: USART TXD, I2C SCL, SPI MISO.
O
SCT0_OUT0 — SCT0 output 0. PWM output 0.
O
CTimer0_MAT0 — 32-bit CTimer0 match output 0.
PU I/O
I/O
FC5_SCK — Flexcomm Interface 5: USART or SPI clock.
O
SCT0_OUT1 — SCT0 output 1. PWM output 1.
O
CTimer0_MAT1 — 32-bit CTimer0 match output 1.
PU I/O
PIO0_20 — General-purpose digital input/output pin. In boundary scan mode: TMS
(Test Mode Select).
I/O
FC5_RXD_SDA_MOSI — Flexcomm Interface 5: USART RXD, I2C SDA, SPI
MOSI.
I/O
FC0_SCK — Flexcomm Interface 0: USART or SPI clock.
I
CTimer3_CAP0 — 32-bit CTimer3 capture input 0.
PU I/O
PIO0_21 — General-purpose digital input/output pin.
O
CLKOUT — Clock output.
I/O
FC0_TXD_SCL_MISO — Flexcomm Interface 0: USART TXD, I2C SCL, SPI MISO.
O
CTimer3_MAT0 — 32-bit CTimer3 match output 0.
PU I/O
Z
PIO0_19 — General-purpose digital input/output pin. In boundary scan mode: TDI
(Test Data In).
PIO0_22 — General-purpose digital input/output pin.
I
CLKIN — Clock input.
I/O
FC0_RXD_SDA_MOSI — Flexcomm Interface 0: USART RXD, I2C SDA, SPI
MOSI.
O
CTimer3_MAT3 — 32-bit CTimer3 match output 3.
I/O
PIO0_23 — General-purpose digital input/output pin. In ISP mode, this pin is set to
the Flexcomm 1 I2C SCL function.
I/O
FC1_RTS_SCL_SSEL1 — Flexcomm Interface 1: USART CTS, I2C SCL, SPI
SSEL1.
R — Reserved.
I
CTimer0_CAP0 — 32-bit CTimer0 capture input 0.
R — Reserved.
I
LPC51U68
Product data sheet
UTICK_CAP1 — Micro-tick timer capture input 1.
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32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
2
2
[3]
Description
Type
48-pin
PIO0_24
64-pin
Symbol
Reset state [1]
Table 4.
Z
I/O
PIO0_24 — General-purpose digital input/output pin. In ISP mode, this pin is set to
the Flexcomm 1 I2C SDA function.
I/O
FC1_CTS_SDA_SSEL0 — Flexcomm Interface 1: USART CTS, I2C SDA, SPI
SSEL0.
R — Reserved.
I
CTimer0_CAP1 — 32-bit CTimer0 capture input 1.
R — Reserved.
PIO0_25
3
3
[3]
Z
O
CTimer0_MAT0 — 32-bit CTimer0 match output 0.
I/O
PIO0_25 — General-purpose digital input/output pin.
I/O
FC4_RTS_SCL_SSEL1 — Flexcomm Interface 4: USART CTS, I2C SCL, SPI
SSEL1.
I/O
FC6_CTS_SDA_SSEL0 — Flexcomm Interface 6: USART CTS, I2C SDA, SPI
SSEL0.
I
CTimer0_CAP2 — 32-bit CTimer0 capture input 2.
R — Reserved.
PIO0_26
4
4
[3]
Z
I
CTimer1_CAP1 — 32-bit CTimer1 capture input 1.
I/O
PIO0_26 — General-purpose digital input/output pin.
I/O
FC4_CTS_SDA_SSEL0 — Flexcomm Interface 4: USART CTS, I2C SDA, SPI
SSEL0.
R — Reserved.
I
PIO0_29/
ADC0_0
11
7
[4]
CTimer0_CAP3 — 32-bit CTimer0 capture input 3.
PU I/O; PIO0_29/ADC0_0 — General-purpose digital input/output pin. ADC input channel 0
AI
if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O
FC1_RXD_SDA_MOSI — Flexcomm Interface 1: USART RXD, I2C SDA, SPI
MOSI.
O
SCT0_OUT2 — SCT0 output 2. PWM output 2.
O
CTimer0_MAT3 — 32-bit CTimer0 match output 3.
R — Reserved.
I
CTimer0_CAP1 — 32-bit CTimer0 capture input 1.
R — Reserved.
O
PIO0_30/
ADC0_1
12
8
[4]
CTimer0_MAT1 — 32-bit CTimer0 match output 1.
PU I/O; PIO0_30/ADC0_1 — General-purpose digital input/output pin. ADC input channel 1
AI
if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O
FC1_TXD_SCL_MISO — Flexcomm Interface 1: USART TXD, I2C SCL, SPI MISO.
O
SCT0_OUT3 — SCT0 output 3. PWM output 3.
O
CTimer0_MAT2 — 32-bit CTimer0 match output 2.
R — Reserved.
I
LPC51U68
Product data sheet
CTimer0_CAP2 — 32-bit CTimer0 capture input 2.
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32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
13
9
Reset state [1]
48-pin
PIO0_31/
ADC0_2
64-pin
Symbol
[4]
Description
Type
Table 4.
PU I/O; PIO0_31/ADC0_2 — General-purpose digital input/output pin. ADC input channel 2
AI
if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
Remark: This pin is also used to invoke ISP mode after device reset. Secondary
selection of boot source for ISP mode also uses PIO0_4 and PIO1_6. See the Boot
Process chapter in UM11071 for more details.
R — Reserved.
I/O
FC2_CTS_SDA_SSEL0 — Flexcomm Interface 2: USART CTS, I2C SDA, SPI
SSEL0.
R — Reserved.
R — Reserved.
PIO1_0/
ADC0_3
14
10
[4]
I
CTimer0_CAP3 — 32-bit CTimer0 capture input 3.
O
CTimer0_MAT3 — 32-bit CTimer0 match output 3.
PU I/O; PIO1_0/ADC0_3 — General-purpose digital input/output pin. ADC input channel 3 if
AI
the DIGIMODE bit is set to 0 in the IOCON register for this pin.
R — Reserved.
I/O
FC2_RTS_SCL_SSEL1 — Flexcomm Interface 2: USART RTS, I2C SCL, SPI
SSEL1.
O
CTimer3_MAT1 — 32-bit CTimer3 match output 1.
R — Reserved.
I
PIO1_1/
ADC0_4
15
11
[4]
CTimer0_CAP0 — 32-bit CTimer0 capture input 0.
PU I/O; PIO1_1/ADC0_4 — General-purpose digital input/output pin. ADC input channel 4 if
AI
the DIGIMODE bit is set to 0 in the IOCON register for this pin.
R — Reserved.
R — Reserved.
PIO1_2/
ADC0_5
16
LPC51U68
Product data sheet
12
[4]
O
SCT0_OUT4 — SCT0 output 4. PWM output 4.
I/O
FC5_SSEL2 — Flexcomm Interface 5: SPI SSEL2.
I/O
FC4_TXD_SCL_MISO — Flexcomm Interface 4: USART TXD, I2C SCL, SPI MISO.
PU I/O; PIO1_2/ADC0_5 — General-purpose digital input/output pin. ADC input channel 5 if
AI
the DIGIMODE bit is set to 0 in the IOCON register for this pin.
I/O
MCLK — MCLK input or output for I2S and/or digital microphone.
I/O
FC7_SSEL3 — Flexcomm Interface 7: SPI SSEL3.
O
SCT0_OUT5 — SCT0 output 5. PWM output 5.
I/O
FC5_SSEL3 — Flexcomm Interface 5: SPI SSEL3.
I/O
FC4_RXD_SDA_MOSI — Flexcomm Interface 4: USART RXD, I2C SDA, SPI
MOSI.
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LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
17
13
Reset state [1]
48-pin
PIO1_3/
ADC0_6
64-pin
Symbol
[4]
Description
Type
Table 4.
PU I/O; PIO1_3/ADC0_6 — General-purpose digital input/output pin. ADC input channel 6 if
AI
the DIGIMODE bit is set to 0 in the IOCON register for this pin.
R — Reserved.
I/O
FC7_SSEL2 — Flexcomm Interface 7: SPI SSEL2.
O
SCT0_OUT6 — SCT0 output 6. PWM output 6.
R — Reserved.
PIO1_4/
ADC0_7
18
14
[4]
I/O
FC3_SCK — Flexcomm Interface 3: USART or SPI clock.
I
CTimer0_CAP1 — 32-bit CTimer0 capture input 1.
O
USB_UP_LED — USB port 2 GoodLink LED indicator. It is LOW when the device is
configured (non-control endpoints enabled). It is HIGH when the device is not
configured or during global suspend.
PU I/O; PIO1_4/ADC0_7 — General-purpose digital input/output pin. ADC input channel 7 if
AI
the DIGIMODE bit is set to 0 in the IOCON register for this pin.
R — Reserved.
I/O
FC7_RTS_SCL_SSEL1 — Flexcomm Interface 7: USART RTS, I2C SCL, SPI
SSEL1.
O
SCT0_OUT7 — SCT0 output 7. PWM output 7.
R — Reserved.
PIO1_5/
ADC0_8
19
15
[4]
I/O
FC3_TXD_SCL_MISO — Flexcomm Interface 3: USART TXD, I2C SCL, SPI MISO.
O
CTimer0_MAT1 — 32-bit CTimer0 match output 1.
PU I/O; PIO1_5/ADC0_8 — General-purpose digital input/output pin. ADC input channel 8 if
AI
the DIGIMODE bit is set to 0 in the IOCON register for this pin.
R — Reserved.
I/O
FC7_CTS_SDA_SSEL0 — Flexcomm Interface 7: USART CTS, I2C SDA, SPI
SSEL0.
I
CTimer1_CAP0 — 32-bit CTimer1 capture input 0.
R — Reserved.
O
CTimer1_MAT3 — 32-bit CTimer1 match output 3.
R — Reserved.
O
LPC51U68
Product data sheet
USB_FRAME — USB start-of-frame signal derived from host signaling.
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32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
26
20
Reset state [1]
48-pin
PIO1_6/
ADC0_9
64-pin
Symbol
[4]
Description
Type
Table 4.
PU I/O; PIO1_6/ADC0_9 — General-purpose digital input/output pin. ADC input channel 9 if
AI
the DIGIMODE bit is set to 0 in the IOCON register for this pin.
Remark: This pin is also used as part of secondary selection of boot source for ISP
mode after device reset, in connection with PIO0_31 and PIO0_4. See the Boot
Process chapter in UM11071 for more details.
R — Reserved.
I/O
FC7_SCK — Flexcomm Interface 7: USART, SPI, or I2S clock.
I
CTimer1_CAP2 — 32-bit CTimer1 capture input 2.
R — Reserved.
O
CTimer1_MAT2 — 32-bit CTimer1 match output 2.
R — Reserved.
I
PIO1_7/
ADC0_10
27
21
[4]
USB_VBUS — Monitors the presence of USB bus power. This signal must be HIGH
for USB reset to occur.
PU I/O; PIO1_7/ADC0_10 — General-purpose digital input/output pin. ADC input channel
AI
10 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
R — Reserved.
I/O
FC7_RXD_SDA_MOSI_DATA — Flexcomm Interface 7: USART RXD, I2C SDA,
SPI MOSI, I2S DATA.
O
CTimer1_MAT2 — 32-bit CTimer1 match output 2.
R — Reserved.
I
PIO1_8/
ADC0_11
28
22
[4]
CTimer1_CAP2 — 32-bit CTimer1 capture input 2.
PU I/O; PIO1_8/ADC0_11 — General-purpose digital input/output pin. ADC input channel 11
AI
if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
R — Reserved.
I/O
FC7_TXD_SCL_MISO_WS — Flexcomm Interface 7: USART TXD, I2C SCL, SPI
MISO, I2S WS.
O
CTimer1_MAT3 — 32-bit CTimer1 match output 3.
R — Reserved.
I
PIO1_9
29
-
[2]
PU I/O
CTimer1_CAP3 — 32-bit CTimer1 capture input 3.
PIO1_9 — General-purpose digital input/output pin.
R — Reserved.
I/O
FC3_RXD_SDA_MOSI — Flexcomm Interface 3: USART RXD, I2C SDA, SPI
MOSI.
I
CTimer0_CAP2 — 32-bit CTimer0 capture input 2.
R — Reserved.
R — Reserved.
O
LPC51U68
Product data sheet
USB_UP_LED — USB port 2 GoodLink LED indicator. It is LOW when the device is
configured (non-control endpoints enabled). It is HIGH when the device is not
configured or during global suspend.
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NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
30
-
Reset state [1]
48-pin
PIO1_10
64-pin
Symbol
[2]
Description
Type
Table 4.
PU I/O
PIO1_10 — General-purpose digital input/output pin.
R — Reserved.
I/O
FC6_TXD_SCL_MISO_WS — Flexcomm Interface 6: USART TXD, I2C SCL, SPI
MISO, I2S WS.
O
SCT0_OUT4 — SCT0 output 4. PWM output 4.
I/O
FC1_SCK — Flexcomm Interface 1: USART or SPI clock.
R — Reserved.
R — Reserved.
I
PIO1_11
42
-
[2]
PU I/O
USB_FRAME — USB start-of-frame signal derived from host signaling.
PIO1_11 — General-purpose digital input/output pin.
R — Reserved.
I/O
FC6_RTS_SCL_SSEL1 — Flexcomm Interface 6: USART RTS, I2C SCL, SPI
SSEL1.
I
CTimer1_CAP0 — 32-bit CTimer1 capture input 0.
I/O
FC4_SCK — Flexcomm Interface 4: USART or SPI clock.
R — Reserved.
R — Reserved.
I
PIO1_12
51
-
[2]
PU I/O
USB_VBUS — Monitors the presence of USB bus power. This signal must be HIGH
for USB reset to occur.
PIO1_12 — General-purpose digital input/output pin.
R — Reserved.
PIO1_13
54
-
[2]
I/O
FC5_RXD_SDA_MOSI — Flexcomm Interface 5: USART RXD, I2C SDA, SPI
MOSI.
O
CTimer1_MAT0 — 32-bit CTimer1 match output 0.
I/O
FC7_SCK — Flexcomm Interface 7: USART, SPI, or I2S clock.
I
UTICK_CAP2 — Micro-tick timer capture input 2.
PU I/O
PIO1_13 — General-purpose digital input/output pin.
R — Reserved.
I/O
PIO1_14
57
-
[2]
FC5_TXD_SCL_MISO — Flexcomm Interface 5: USART TXD, I2C SCL, SPI MISO.
O
CTimer1_MAT1 — 32-bit CTimer1 match output 1.
I/O
FC7_RXD_SDA_MOSI_DATA — Flexcomm Interface 7: USART RXD, I2C SDA,
SPI MOSI, I2S DATA.
PU I/O
PIO1_14 — General-purpose digital input/output pin.
R — Reserved.
LPC51U68
Product data sheet
I/O
FC2_RXD_SDA_MOSI — Flexcomm Interface 2: USART RXD, I2C SDA, SPI
MOSI.
O
SCT0_OUT7 — SCT0 output 7. PWM output 7.
I/O
FC7_TXD_SCL_MISO_WS — Flexcomm Interface 7: USART TXD, I2C SCL, SPI
MISO, I2S WS.
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LPC51U68
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32-bit ARM Cortex-M0+ microcontroller
Pin description …continued
62
-
Reset state [1]
48-pin
PIO1_15
64-pin
Symbol
[2]
Description
Type
Table 4.
PU I/O
PIO1_15 — General-purpose digital input/output pin.
R — Reserved.
PIO1_16
7
-
[2]
O
SCT0_OUT5 — SCT0 output 5. PWM output 5.
I
CTimer1_CAP3 — 32-bit CTimer1 capture input 3.
I/O
FC7_CTS_SDA_SSEL0 — Flexcomm Interface 7: USART CTS, I2C SDA, SPI
SSEL0.
PU I/O
PIO1_16 — General-purpose digital input/output pin.
R — Reserved.
PIO1_17
10
-
[2]
O
CTimer0_MAT0 — 32-bit CTimer0 match output 0.
I
CTimer0_CAP0 — 32-bit CTimer0 capture input 0.
I/O
FC7_RTS_SCL_SSEL1 — Flexcomm Interface 7: USART RTS, I2C SCL, SPI
SSEL1.
PU I/O
PIO1_17 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
R — Reserved.
USB_DP
USB_DM
5
6
I/O
MCLK — MCLK input or output for I2S and/or digital microphone.
I
UTICK_CAP3 — Micro-tick timer capture input 3.
5
[6]
F
I/O
USB0 bidirectional D+ line.
6
[6]
F
I/O
USB0 bidirectional D- line.
[5]
PU I
External reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. Wakes up the part from deep power-down mode.
RESETN
64
48
RTCXIN
33
25
-
-
RTC oscillator input.
RTCXOUT
35
26
-
-
RTC oscillator output.
VREFP
22
-
-
-
ADC positive reference voltage. On LQFP48, VREFP is internally tied to the VDDA
pin.
VREFN
21
-
-
-
ADC negative reference voltage. On LQFP48, VREFN is internally tied to the VDDA
pin.
VDDA
23
17
-
-
Analog supply voltage.
VDD
8, 18,
24, 42
34,
56
-
-
Single 1.62 V to 3.6 V power supply powers internal digital functions and I/Os.
VSS
9, 19,
25, 41
55
-
-
Ground.
VSSA
20
-
-
Analog ground.
LPC51U68
Product data sheet
16
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32-bit ARM Cortex-M0+ microcontroller
[1]
PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VDD). Z = high impedance; pull-up or pull-down disabled, AI = analog
input, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation. For pin states in the
different power modes, see Section 6.2.2 “Pin states in different power modes”. For termination on unused pins, see Section 6.2.1
“Termination of unused pins”.
[2]
5 V tolerant pad with programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength. See Figure 29. Pulse width of spikes or glitches suppressed by input
filter is from 3 ns to 16 ns (simulated value).
[3]
True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode
Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not
disturb the I2C lines. Open-drain configuration applies to all functions on this pin.
[4]
5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When
configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[5]
Reset pad.5 V tolerant pad with glitch filter with hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to
20 ns (simulated value)
[6]
5 V tolerant transparent analog pad.
6.2.1 Termination of unused pins
Table 5shows how to terminate pins that are not used in the application. In many cases,
unused pins should be connected externally or configured correctly by software to
minimize the overall power consumption of the part.
Unused pins with GPIO function should be configured as outputs set to LOW with their
internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the
GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0
to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.
In addition, it is recommended to configure all GPIO pins that are not bonded out on
smaller packages as outputs driven LOW with their internal pull-up disabled.
Table 5.
Termination of unused pins
Pin
Default
state[1]
RESET
I; PU
Recommended termination of unused pins
The RESET pin can be left unconnected if the application does not use it.
all PIOn_m (not open-drain) I; PU
Can be left unconnected if driven LOW and configured as GPIO output with pull-up
disabled by software.
PIOn_m (I2C open-drain)
IA
Can be left unconnected if driven LOW and configured as GPIO output by software.
USB_DP
F
If USB interface is not used, pin can be left unconnected except in deep
power-down mode where it must be externally pulled low.
USB_DM
F
If USB interface is not used, pin can be left unconnected except in deep
power-down mode where it must be externally pulled low.
RTCXIN
-
Connect to ground. When grounded, the RTC oscillator is disabled.
RTCXOUT
-
Can be left unconnected.
VREFP
-
Tie to VDD.
VREFN
-
Tie to VSS.
VDDA
-
Tie to VDD.
VSSA
-
Tie to VSS.
[1]
I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating
LPC51U68
Product data sheet
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Rev. 1.5 — 13 January 2020
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LPC51U68
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32-bit ARM Cortex-M0+ microcontroller
6.2.2 Pin states in different power modes
Table 6.
Pin states in different power modes
Pin
Active
Sleep
Deep-sleep
Deep power-down
As configured in the
IOCON[1].
Default: internal pull-up enabled. Floating.
PIO0_23 to PIO0_26 (open-drain
I2C-bus pins)
As configured in the
IOCON[1].
Floating.
RESET
Reset function enabled. Default: input, internal pull-up enabled.
PIOn_m pins (not I2C)
[1]
Default and programmed pin states are retained in sleep and deep-sleep modes.
7. Functional description
7.1 ARM Cortex-M0+ co-processor
The ARM Cortex-M0+ co-processor offers high performance and very low power
consumption. This processor uses a 2-stage pipeline von Neumann architecture and a
small but powerful instruction set providing high-end processing hardware. The processor
includes a single-cycle multiplier, an NVIC with 32 interrupts, and a separate system tick
timer.
7.2 Nested Vectored Interrupt Controller (NVIC) for Cortex-M0+
The NVIC is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for
low interrupt latency and efficient processing of late arriving interrupts.
7.2.1 Features
•
•
•
•
•
•
Controls system exceptions and peripheral interrupts.
32 vectored interrupt slots.
Four programmable interrupt priority levels, with hardware priority level masking.
Relocatable vector table using VTOR.
Non-Maskable Interrupt (NMI).
Software interrupt generation.
7.2.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
7.3 System Tick timer (SysTick)
The ARM Cortex-M0+ cores include a system tick timer (SysTick) that is intended to
generate a dedicated SYSTICK exception. The clock source for the SysTick can be the
system clock or the SYSTICK clock.
7.4 On-chip static RAM
The LPC51U68 supports 96 KB SRAM with separate bus master access for higher
throughput and individual power control for low-power operation.
LPC51U68
Product data sheet
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LPC51U68
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32-bit ARM Cortex-M0+ microcontroller
7.5 On-chip flash
The LPC51U68 supports 256 KB of on-chip flash memory.
7.6 On-chip ROM
The 32 KB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming.
• ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB is
supported.
• Supports booting from valid user code in flash, USART, SPI, and I2C.
• Legacy, Single, and Dual image boot.
7.7 Memory mapping
The LPC51U68 incorporates several distinct memory regions. The APB peripheral area is
64 KB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated
4 KB of space simplifying the address decoding.
Figure 5 shows the overall map of the entire address space from the user program
viewpoint following reset.
LPC51U68
Product data sheet
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LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Memory space
APB peripherals
0xFFFF FFFF
(reserved)
private peripheral bus(1)
(reserved)
ADC
0xE010 0000
(reserved)
0xE000 0000
ISP-AP interface
0x4400 0000
(reserved)
(reserved)
Flexcomm Interface 7
(reserved)
AHB
peripherals
(reserved)
0x4200 0000
Flexcomm Interface 6
0x400A 1000
Flexcomm Interface 5
CRC engine
0x4008 0000
(reserved)
0x4006 0000
(reserved)
Asynchronous
APB peripherals
High Speed GPIO
0x4004 0000
APB peripherals on
APB bridge 1
0x4002 0000
see APB
memory
map figure
APB peripherals on
APB bridge 0
0x4000 0000
(reserved)
0x2400 0000
(reserved)
0x2200 0000
(reserved)
0x2002 8000
(reserved)
0x2002 0000
(reserved)
Flexcomm Interface 4
Flexcomm Interface 3
Flexcomm Interface 2
Flexcomm Interface 1
Flexcomm Interface 0
SCTimer / PWM
FS USB device
(reserved)
DMA controller
(reserved)
(reserved)
0x400A 1000
0x400A 0000
0x4009 D000
0x4009 C000
0x4009 9000
0x4009 8000
0x4009 7000
0x4009 6000
0x4009 5000
0x4009 1000
0x4009 0000
0x4008 C000
0x4008 B000
0x4008 A000
0x4008 9000
0x4008 8000
0x4008 7000
0x4008 6000
0x4008 5000
0x4008 4000
0x4008 3000
0x4008 2000
0x4008 1000
0x2001 0000
SRAM0
(64 KB)
0x2000 0000
(reserved)
0x0400 8000
SRAMX
(32 KB)
0x0400 0000
(reserved)
0x0300 8000
Boot ROM
0x0300 0000
(reserved)
Flash memory
256 KB
0x0004 0000
0x0000 0000
active interrupt vectors
0x0000 00C0
0x0000 0000
aaa-028911
[1] The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.
[2] The total size of flash and SRAM is part dependent. See Table 1 on page 4.
Fig 5.
LPC51U68 Memory mapping
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APB bridge 0
APB bridge 1
0x4001 FFFF
31-15
(reserved)
14
Micro-tick timer
13
Multi-rate timer
12
Watchdog timer
11-10
(reserved)
9
CTIMER 1
8
CTIMER 0
7-6
(reserved)
5
Input muxes
4
Pin Interrupts (PINT)
3
GINT 1
2
GINT 0
1
IOCON
2
Syscon
0x4003 FFFF
0x4000 F000
0x4000 E000
0x4000 D000
0x4000 C000
0x4000 A000
31-21
(reserved)
20
Flash controller
19-13
(reserved)
12
RTC
11-9
(reserved)
8
(reserved)
7-0
(reserved)
0x4000 9000
0x4000 8000
0x4003 5000
0x4003 4000
0x4002 D000
0x4002 C000
0x4002 9000
0x4002 8000
0x4002 0000
0x4000 6000
0x4000 5000
0x4000 4000
Asynchronous APB bridge
0x4005 FFFF
0x4000 3000
0x4000 2000
31-10
(reserved)
9
(reserved)
8
CTIMER 3
7-1
(reserved)
0
Asynch. Syscon
0x4000 1000
0x4000 0000
0x4004 A000
0x4004 9000
0x4004 8000
0x4004 1000
0x4004 0000
aaa-028913
Fig 6.
LPC51U68 APB Memory map
7.8 System control
7.8.1 Clock sources
The LPC51U68 supports two external and three internal clock sources:
•
•
•
•
•
The Free Running Oscillator (FRO).
Watchdog oscillator (WDTOSC).
External clock source from the digital I/O pin CLKIN.
External RTC 32.768 kHz clock.
Output of the system PLL.
7.8.1.1 FRO
The internal FRO can be used as a CPU clock or a clock source to the system PLL. On
power-up, or any chip reset, the LPC51U68 uses an internal 12 MHz FRO as the clock
source. Software may later switch to one of the available clock sources. A selectable 48
MHz or 96 MHz FRO is also available as a clock source.
The 48 MHz FRO can be used as a clock source to the USB.
The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.
7.8.1.2 Watchdog oscillator (WDTOSC)
The watchdog oscillator is a low-power internal oscillator. The WDTOSC can be used to
provide a clock to the WWDT and to the entire chip. The watchdog oscillator has a
selectable frequency in the range of 6 kHz to 1.5 MHz.
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7.8.1.3 Clock input
An external square-wave clock source (up to 25 MHz) can be supplied on the digital I/O
pin CLKIN.
7.8.1.4 RTC Oscillator
An external RTC (32.768 kHz) can be used to create the main clock when the PLL input or
output is selected as the clock source to the main clock.
7.8.1.5 System PLL
The system PLL allows CPU operation up to the maximum CPU rate without the need for
a high-frequency external clock. The system PLL can run from the internal FRO 12 MHz
output, the external clock input CLKIN, or the RTC oscillator.
The system PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The
input frequency is multiplied up to a high frequency with a Current Controlled Oscillator
(CCO) The PLL can be enabled or disabled by software.
7.8.2 Clock Generation
The system control block facilitates the clock generation. Many clocking variations are
possible. Figure 7 gives an overview of the potential clock options.
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fro_12m
clk_in
wdt_clk
fro_hf
00
01
pll_clk
32k_clk
10
11
00
10
main_clk
11
(1)
CPU CLOCK
DIVIDER
(1)
main_clk
Main clock select B
MAINCLKSELB[1:0]
Main clock select A
MAINCLKSELA[1:0]
000
001
pll_clk
fro_hf
010
111
“none”
fro_12m
clk_in
wdt_clk
32k_clk
“none”
000
001
system clock to
CPU, AHB bus,
Sync APB, etc.
AHBCLKDIV
to ADC
ADC CLOCK
DIVIDER
ADCCLKDIV
ADC clock select
ADCCLKSEL[2:0]
SYSTEM PLL
(PLL0)
010
011
111
fro_hf
pll_clk
System PLL
settings
000
001
main_clk
PLL clock select
SYSPLLCLKSEL[2:0]
010
“none”
to FS USB
USB CLOCK
DIVIDER
111
USBCLKDIV
main_clk
fro_12m
00
01
USB clock select
USBCLKSEL[2:0]
to async
APB bridge
fro_hf
pll_clk
main_clk
(1)
APB clock select B
ASYNCAPBCLKSELB[1:0]
000
001
010
“none”
MCLK pin
(output)
MCLK
DIVIDER
111
MCLKDIV
MCLK clock select
MCLKCLKSEL[2:0]
(1): synchronized multiplexer,
see register descriptions for details.
to CLK32K of all
Flexcomm Interfaces
32k_clk
(1 per device)
main_clk
clk_in
wdt_clk
fro_hf
pll_clk
fro_12m
32k_clk
“none”
000
001
010
011
100
101
110
111
main_clk
pll_clk
fro_12m
CLKOUT
DIVIDER
fro_hf
“none”
fro_12
000
001
fro_hf
pll_clk
010
011
111
FRG CLOCK
DIVIDER
CLKOUTDIV
CLKOUT select
CLKOUTSELA[2:0]
Fig 7.
CLKOUT
FRG clock select
FRGCLKSEL[2:0]
(1 per Flexcomm Interface)
FRGCTRL[15:0]
mclk_in
frg_clk
“none”
000
001
fcn_fclk
(function clock
010 of Flexcomm [n]
011 (up to 8 Flexcomm
interfaces on
100
these devices)
111
Function clock select
FXCOMCLKSEL[n][2:0]
aaa-028912
LPC51U68 clock generation
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Table 9 describes signals on the clocking diagram.
Table 7.
Clocking diagram signal name descriptions
Name
Description
32k_clk
The 32 kHz output of the RTC oscillator. The 32 kHz clock must be enabled in the RTCOSCCTRL register.
clk_in
This is the internal clock that comes from the main CLK_IN pin function. That function must be connected to the
pin by selecting it in the IOCON block.
frg_clk
The output of the Fractional Rate Generator.
fro_12m
The 12 MHz output of the currently selected on-chip FRO oscillator.
fro_hf
The currently selected FRO high speed output. This may be either 96 MHz or 48 MHz.
main_clk
The main clock used by the CPU and AHB bus, and potentially many others.
mclk_in
The MCLK input function, when it is connected to a pin by selecting it in the IOCON block.
pll_clk
The output of the PLL.
wdt_clk
The output of the watchdog oscillator, which has a selectable target frequency. It must also be enabled in the
PDRINCFG0 register.
“none”
A tied-off source that should be selected to save power when the output of the related multiplexer is not used.
7.8.3 Brownout detection
The LPC51U68 includes a monitor for the voltage level on the VDD pin. If this voltage falls
below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In
addition, a separate threshold levels can be selected to cause chip reset and interrupt.
7.8.4 Safety
The LPC51U68 includes a Windowed WatchDog Timer (WWDT), which can be enabled
by software after reset. Once enabled, the WWDT remains locked and cannot be modified
in any way until a reset occurs.
7.9 Code security (Code Read Protection - CRP)
This feature of the LPC51U68 allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry can be invoked by pulling a pin on the LPC51U68 LOW on reset.
This pin is called the ISP entry pin.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. CRP3 fully disables any access to the chip via SWD and ISP. It is up to the user’s
application to provide (if needed) flash update mechanism using IAP calls or a call to
reinvoke ISP command to enable a flash update via USART.
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4. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code
can be disabled (No_ISP mode). For details, see the LPC51U68 user manual.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
7.10 Power control
The LPC51U68 support a variety of power control features. In Active mode, when the chip
is running, power and clocks to selected peripherals can be adjusted for power
consumption. In addition, there are four special modes of processor power reduction with
different peripherals running: sleep mode, deep-sleep mode, and deep power-down
mode, activated by the power mode configure API.
7.10.1 Sleep mode
In sleep mode, the system clock to the CPU is stopped and execution of instructions is
suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be
clocked can continue operation during Sleep mode and may generate interrupts to cause
the processor to resume execution. Sleep mode eliminates dynamic power used by the
processor itself, memory systems and related controllers, internal buses, and unused
peripherals. The processor state and registers, peripheral registers, and internal SRAM
values are maintained, and the logic levels of the pins remain static.
7.10.2 Deep-sleep mode
In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All
analog blocks are powered down by default but can be selected to keep running through
the power API if needed as wake-up sources. The main clock and all peripheral clocks are
disabled by default. The flash memory is put in standby mode.
Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power
used by the processor itself, memory systems and related controllers, and internal buses.
The processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB, SPI,
I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left running in deep sleep
mode The FRO, RTC oscillator, and the watchdog oscillator can be left running. In some
cases, DMA can operate in deep-sleep mode. For more details, see LPC51U68 user
manual.
7.10.3 Deep power-down mode
In deep power-down mode, power is shut off to the entire chip except for the RTC power
domain and the RESET pin. The LPC51U68 can wake up from deep power-down mode
via the RESET pin and the RTC alarm. The ALARM1HZ flag in RTC control register
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generates an RTC wake-up interrupt request, which can wake up the part. During deep
power-down mode, the contents of the SRAM and registers are not retained. All functional
pins are tri-stated in deep power-down mode.
Table 8 shows the peripheral configuration in reduced power modes.
Table 8.
Peripheral configuration in reduced power modes
Peripheral
Reduced power mode
Sleep
Deep-sleep
Deep power-down
FRO
Software configured Software configured
Off
Flash
Software configured Standby
Off
BOD
Software configured Software configured
Off
PLL
Software configured Off
Off
Watchdog osc and
WWDT
Software configured Software configured
Off
Micro-tick Timer
Software configured Software configured
Off
DMA
Active
USART
Software configured Off; but can create a wake-up interrupt in synchronous Off
slave mode or 32 kHz clock mode
Configurable some for operations, see Section 7.8.2
Off
SPI
Software configured Off; but can create a wake-up interrupt in slave mode
Off
I2C
Software configured Off; but can create a wake-up interrupt in slave mode
Off
USB
Software configured Software configured
Off
Other digital peripherals Software configured Off
Off
RTC oscillator
Software configured
Software configured Software configured
Table 9 shows the wake-up sources for reduced power modes.
Table 9.
Wake-up sources for reduced power modes
Power mode Wake-up source
Conditions
Sleep
Any interrupt
Enable interrupt in NVIC.
HWWAKE
Certain Flexcomm Interface activity.
Pin interrupts
Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers.
Deep-sleep
BOD interrupt
BOD reset
Watchdog interrupt
Watchdog reset
Reset pin
LPC51U68
Product data sheet
•
•
•
Enable interrupt in NVIC and STARTER0 registers.
Enable interrupt in BODCTRL register.
Configure the BOD to keep running in this mode with the power API.
Enable reset in BODCTRL register.
•
•
•
•
•
•
•
Enable the watchdog oscillator in the PDRUNCFG0 register.
Enable the watchdog interrupt in NVIC and STARTER0 registers.
Enable the watchdog in the WWDT MOD register and feed.
Enable interrupt in WWDT MOD register.
Configure the WDTOSC to keep running in this mode with the power API.
Enable the watchdog oscillator in the PDRUNCFG0 register.
Enable the watchdog and watchdog reset in the WWDT MOD register and feed.
Always available.
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Table 9.
Wake-up sources for reduced power modes
Power mode Wake-up source
RTC 1 Hz alarm timer
RTC 1 kHz timer
time-out and alarm
Micro-tick timer
(intended for ultra-low
power wake-up from
deep-sleep mode
Deep
power-down
Conditions
•
•
•
•
•
Enable the RTC 1 Hz oscillator in the RTCOSCCTRL register.
•
•
•
•
•
•
Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.
Enable the RTC bus clock in the AHBCLKCTRL0 register.
Start RTC alarm timer by writing a time-out value to the RTC COUNT register.
Enable the RTCALARM interrupt in the STARTER0 register.
Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL
register.
Enable the RTC wake-up interrupt in the STARTER0 register.
Enable the watchdog oscillator in the PDRUNCFG0 register.
Enable the Micro-tick timer clock by writing to the AHBCLKCTRL1 register.
Start the Micro-tick timer by writing UTICK CTRL register.
Enable the Micro-tick timer interrupt in the STARTER0 register.
I2C interrupt
Interrupt from I2C in slave mode.
SPI interrupt
Interrupt from SPI in slave mode.
USART interrupt
Interrupt from USART in slave or 32 kHz mode.
USB need clock
interrupt
Interrupt from USB when activity is detected that requires a clock.
HWWAKE
Certain Flexcomm Interface activity.
RTC 1 Hz alarm timer
RTC 1 kHz timer
time-out and alarm
Reset pin
LPC51U68
Product data sheet
•
•
•
Enable the RTC 1 Hz oscillator in the RTC CTRL register.
•
•
Enable the RTC bus clock in the AHBCLKCTRL0 register.
Start RTC alarm timer by writing a time-out value to the RTC COUNT register.
Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the
RTCOSCCTRL register.
Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.
Always available.
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7.11 General Purpose I/O (GPIO)
The LPC51U68 provides two GPIO ports with a total of 48 GPIO pins.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The current level
of a port pin can be read back no matter what peripheral is selected for that pin.
See Table 4 for the default state on reset.
7.11.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set, clear, and toggle registers allow a single instruction set, clear or toggle of
any number of bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt
request.
• One GPIO group interrupt can be triggered by a combination of any pin or pins.
7.12 Pin interrupt/pattern engine
The pin interrupt block configures up to eight pins from all digital pins for providing four
external interrupts connected to the NVIC. The pattern match engine can be used in
conjunction with software to create complex state machines based on pin inputs. Any
digital pin, independent of the function selected through the switch matrix can be
configured through the SYSCON block as an input to the pin interrupt or pattern match
engine. The registers that control the pin interrupt or pattern match engine are located on
the I/O+ bus for fast single-cycle access.
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7.12.1 Features
• Pin interrupts:
– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as
edge-sensitive or level-sensitive interrupt requests. Each request creates a
separate interrupt in the NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH-active or LOW-active.
– Level-sensitive interrupt pins can be HIGH-active or LOW-active.
– Pin interrupts can wake up the device from sleep mode and deep-sleep mode.
• Pattern match engine:
– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute
to a boolean expression. The boolean expression consists of specified levels
and/or transitions on various combinations of these pins.
– Each bit slice minterm (product term) comprising of the specified boolean
expression can generate its own, dedicated interrupt request.
– Any occurrence of a pattern match can also be programmed to generate an RXEV
notification to the CPU. The RXEV signal can be connected to a pin.
– Pattern match can be used in conjunction with software to create complex state
machines based on pin inputs.
– Pattern match engine facilities wake-up only from active and sleep modes.
7.13 AHB peripherals
7.13.1 DMA controller
The DMA controller allows peripheral-to memory, memory-to-peripheral, and
memory-to-memory transactions. Each DMA stream provides unidirectional DMA
transfers for a single source and destination.
7.13.1.1 Features
• 18 channels, 16 of which are connected to peripheral DMA requests. These come
from the Flexcomm Interfaces (USART, SPI, I2C, and I2S).
•
•
•
•
•
•
•
LPC51U68
Product data sheet
DMA operations can be triggered by on-chip or off-chip events.
Priority is user selectable for each channel (up to eight priority levels).
Continuous priority arbitration.
Address cache with four entries.
Efficient use of data bus.
Supports single transfers up to 1,024 words.
Address increment options allow packing and/or unpacking data.
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7.14 Digital serial peripherals
7.14.1 USB 2.0 device controller
7.14.1.1 Features
•
•
•
•
•
•
USB2.0 full-speed device controller.
Supports ten physical (five logical) endpoints including one control endpoint.
Supports Single and double-buffering.
Supports Crystal-less operation and calibration of FRO using USB frames.
Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
Link Power Management (LPM) supported.
7.14.2 Flexcomm Interface serial communication
Each Flexcomm Interface provides a choice of peripheral functions, one of which the user
must choose before the function can be configured and used.
7.14.2.1 Features
•
•
•
•
•
USART with asynchronous operation or synchronous master or slave operation.
SPI master or slave, with up to four slave selects.
I2C, including separate master, slave, and monitor functions.
Flexcomm Interfaces 6 and 7 support I2S function.
Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I2C
function does not use the FIFO.
7.14.3 USART
7.14.3.1 Features
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
• Maximum bit rates of 6.25 Mbit/s in asynchronous mode.
• Maximum data rates of 20 Mbit/s in synchronous master mode and 16 Mbit/s in
synchronous slave mode.
•
•
•
•
•
•
•
Multiprocessor/multidrop (9-bit) mode with software address compare.
RS-485 transceiver output enable.
Autobaud mode for automatic baud rate detection.
Parity generation and checking: odd, even, or none.
Software selectable oversampling from 5 to 16 clocks in asynchronous mode.
One transmit and one receive data buffer.
RTS/CTS for hardware signaling for automatic flow control. Software flow control can
be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output.
• Received data and status can optionally be read from a single register.
• Break generation and detection.
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•
•
•
•
Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
Built-in Baud Rate Generator with auto-baud function.
A fractional rate divider is shared among all USARTs.
Interrupts available for FIFO receive level reached, FIFO transmit level reached,
Transmit Idle, change in receiver break detect, Framing error, Parity error, Overrun,
Underrun, Delta CTS detect, and receiver sample noise detected.
• Loopback mode for testing of data and flow control.
• In synchronous slave mode, wakes up the part from deep-sleep mode.
• Special operating mode allows operation at up to 9600 baud using the 32.768 kHz
RTC oscillator as the UART clock. This mode can be used while the device is in
deep-sleep mode and can wake-up the device when a character is received.
• USART transmit and receive functions work with the system DMA controller.
• Activity on the USART synchronous slave mode allows wake-up from deep-sleep
mode on any enabled interrupt
7.14.4 SPI serial I/O controller
7.14.4.1 Features
• Master and slave operation.
• Maximum data rate of 71 Mbit/s in master mode and 15 Mbit/s in slave mode for SPI
functions.
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or
DMA set-up.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data. This allows very
versatile operation, including “any length” frames.
• Four Slave Select input/outputs with selectable polarity and flexible usage.
• Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any
enabled interrupt.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
7.14.5 I2C-bus interface
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example, an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and
can be controlled by more than one bus master connected to it.
7.14.6 Features
• Independent Master, Slave, and Monitor functions.
• Bus speeds supported:
LPC51U68
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– Standard mode, up to 100 kbits/s.
– Fast-mode, up to 400 kbits/s.
– Fast-mode Plus, up to 1 Mbits/s (on specific I2C pins).
– High speed mode, 3.4 Mbits/s as a Slave only (on specific I2C pins).
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I2C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C bus addresses.
•
•
•
•
10-bit addressing supported with software assist.
Supports System Management Bus (SMBus).
Separate DMA requests for Master, Slave, and Monitor functions.
No chip clocks are required in order to receive and compare an address as a Slave,
so this event can wake up the device from deep-sleep mode.
7.14.7 I2S-bus interface
The I2S bus provides a standard communication interface for streaming data transfer
applications such as digital audio or data collection. The I2S bus specification defines a
3-wire serial bus, having one data, one clock, and one word select/frame trigger signal,
providing single or dual (mono or stereo) audio data transfer as well as other
configurations. In the LPC51U68, the I2S function is included in Flexcomm Interface 6 and
Flexcomm Interface 7. Each of these Flexcomm Interfaces implement four I2S channel
pairs.
The I2S interface within one Flexcomm Interface provides at least one channel pair that
can be configured as a master or a slave. Other channel pairs, if present, always operate
as slaves. All of the channel pairs within one Flexcomm Interface share one set of I2S
signals, and are configured together for either transmit or receive operation, using the
same mode, same data configuration and frame configuration. All such channel pairs can
participate in a time division multiplexing (TDM) arrangement. For cases requiring an
MCLK input and/or output, this is handled outside of the I2S block in the system level
clocking scheme.
7.14.7.1 Features
• A Flexcomm Interface may implement one or more I2S channel pairs, the first of which
could be a master or a slave, and the rest of which would be slaves. All channel pairs
are configured together for either transmit or receive and other shared attributes. The
number of channel pairs is defined for each Flexcomm Interface, and may be from 0
to 4.
• Configurable data size for all channels within one Flexcomm Interface, from 4 bits to
32 bits. Each channel pair can also be configured independently to act as a single
channel (mono as opposed to stereo operation).
• All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and
word select/frame trigger (WS), and data line (SDA).
• Data for all I2S traffic within one Flexcomm Interface uses the Flexcomm Interface
FIFO. The FIFO depth is 8 entries.
• Left justified and right justified data modes.
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• DMA support using FIFO level triggering.
• TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is
supported. Each channel pair can act as any data slot. Multiple channel pairs can
participate as different slots on one TDM data line.
• The bit clock and WS can be selectively inverted.
• Sampling frequencies supported depends on the specific device configuration and
applications constraints (e.g. system clock frequency, PLL availability, etc.) but
generally supports standard audio data rates. See the data rates section in I2S
chapter (UM11071) to calculate clock and sample rates.
Remark: The Flexcomm Interface function clock frequency should not be above 48 MHz.
7.15 Standard counter/timers (CTimer 0, 1, 3)
The LPC51U68 includes three general-purpose 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.15.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also generate an
interrupt.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs per timer corresponding to match registers with the
following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
• PWM mode using up to three match channels for PWM output.
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7.15.2 SCTimer/PWM subsystem
The SCTimer/PWM is a flexible timer module capable of creating complex PWM
waveforms and performing other advanced timing and control operations with minimal or
no CPU intervention.
The SCTimer/PWM can operate as a single 32-bit counter or as two independent, 16-bit
counters in uni-directional or bi-directional mode. It supports a selection of match registers
against which the count value can be compared, and capture registers where the current
count value can be recorded when some pre-defined condition is detected.
The SCTimer/PWM module supports multiple separate events that can be defined by the
user based on some combination of parameters including a match on one of the match
registers, and/or a transition on one of the SCTimer/PWM inputs or outputs, the direction
of count, and other factors.
Every action that the SCTimer/PWM block can perform occurs in direct response to one of
these user-defined events without any software overhead. Any event can be enabled to:
• Start, stop, or halt the counter.
• Limit the counter which means to clear the counter in unidirectional mode or change
its direction in bi-directional mode.
• Set, clear, or toggle any SCTimer/PWM output.
• Force a capture of the count value into any capture registers.
• Generate an interrupt of DMA request.
7.15.2.1 Features
• The SCTimer/PWM Supports:
– Eight inputs.
– Eight outputs.
– Ten match/capture registers.
– Ten events.
– Ten states.
• Counter/timer features:
– Each SCTimer/PWM is configurable as two 16-bit counters or one 32-bit counter.
– Counters clocked by system clock or selected input.
– Configurable number of match and capture registers. Up to five match and capture
registers total.
– Ten events.
– Ten states.
– Upon match and/or an input or output transition create the following events:
interrupt; stop, limit, halt the timer or change counting direction; toggle outputs;
change the state.
– Counter value can be loaded into capture register triggered by a match or
input/output toggle.
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• PWM features:
– Counters can be used in conjunction with match registers to toggle outputs and
create time-proportioned PWM signals.
– Up to eight single-edge or four dual-edge PWM outputs with independent duty
cycle and common PWM cycle length.
• Event creation features:
– The following conditions define an event: a counter match condition, an input (or
output) condition such as an rising or falling edge or level, a combination of match
and/or input/output condition.
– Selected events can limit, halt, start, or stop a counter or change its direction.
– Events trigger state changes, output toggles, interrupts, and DMA transactions.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• State control features:
– A state is defined by events that can happen in the state while the counter is
running.
– A state changes into another state as a result of an event.
– Each event can be assigned to one or more states.
– State variable allows sequencing across multiple counter cycles.
7.15.3 Windowed WatchDog Timer (WWDT)
The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a
programmable time if it enters an erroneous state. When enabled, a watchdog reset is
generated if the user program fails to feed (reload) the Watchdog within a predetermined
amount of time.
7.15.3.1 Features
• Internally resets chip if not reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Programmable 24-bit timer with internal fixed pre-scaler.
• Selectable time period from 1,024 watchdog clocks (TWDCLK × 256 × 4) to over 67
million watchdog clocks (TWDCLK × 224 × 4) in increments of four watchdog clocks.
• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
• Incorrect feed sequence causes immediate watchdog event if enabled.
• The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
• Flag to indicate Watchdog reset.
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• The Watchdog clock (WDCLK) source is a selectable frequency in the range of 6 kHz
to 1.5 MHz. The accuracy of this clock is limited to +/- 40% over temperature, voltage,
and silicon processing variations.
• The Watchdog timer can be configured to run in deep-sleep mode.
• Debug mode.
7.15.4 RTC timer
The RTC block has two timers: main RTC timer, and high-resolution/wake-up timer. The
main RTC timer is a 32-bit timer that uses a 1 Hz clock and is intended to run continuously
as a real-time clock. When the timer value reaches a match value, an interrupt is raised.
The alarm interrupt can also wake up the part from any low power mode, if enabled.
The high-resolution or wake-up timer is a 16-bit timer that uses a 1 kHz clock and
operates as a one-shot down timer. When the timer is loaded, it starts counting down to 0
at which point an interrupt is raised. The interrupt can be used to wake-up the part from
any low power modes. This timer is intended to be used for timed wake-up from
deep-sleep or deep power-down modes. The high-resolution wake-up timer can be
disabled to conserve power if not used.
The RTC timer uses the 32.768 kHz clock input to create a 1 Hz or 1 kHz clock.
7.15.4.1 Features
• The RTC oscillator has the following clock outputs:
– 32.768 kHz clock, selectable for system clock and CLKOUT pin.
– 1 Hz clock for RTC timing.
– 1 kHz clock for high-resolution RTC timing.
• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.
• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution
with a more that one minute maximum time-out period.
• RTC alarm and high-resolution/wake-up timer time-out each generate independent
interrupt requests. Either time-out can wake up the part from any of the low power
modes, including deep power-down.
7.15.5 Multi-Rate Timer (MRT)
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval, and each channel
operates independently from the other channels.
7.15.5.1 Features
• 24-bit interrupt timer.
• Four channels independently counting down from individually set values.
• Repeat interrupt, one-shot interrupt, and one-shot bus stall modes.
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7.15.6 Micro-tick timer (UTICK)
The ultra-low power Micro-tick Timer, running from the Watchdog oscillator, can be used
to wake up the device from low power modes.
7.15.6.1 Features
•
•
•
•
Ultra simple timer.
Write once to start.
Interrupt or software polling.
Four capture registers that can be triggered by external pin transitions.
7.16 12-bit Analog-to-Digital Converter (ADC)
The ADC supports a resolution of 12-bit and fast conversion rates of up to 5.0
Msamples/s. Sequences of analog-to-digital conversions can be triggered by multiple
sources. Possible trigger sources are the SCTimer/PWM, external pins, and the ARM
TXEV interrupt.
The ADC supports a variable clocking scheme with clocking synchronous to the system
clock or independent, asynchronous clocking for high-speed conversions
The ADC includes a hardware threshold compare function with zero-crossing detection.
The threshold crossing interrupt is connected internally to the SCTimer/PWM inputs for
tight timing control between the ADC and the SCTimer/PWM.
7.16.1 Features
•
•
•
•
•
•
12-bit successive approximation analog to digital converter.
Input multiplexing up to 12 pins.
Two configurable conversion sequences with independent triggers.
Optional automatic high/low threshold comparison and “zero crossing” detection.
Measurement range VREFN to VREFP (not to exceed VDDA voltage level).
12-bit conversion rate of 5.0 MHz. Options for reduced resolution at higher conversion
rates.
• Burst conversion mode for single or multiple inputs.
• Synchronous or asynchronous operation. Asynchronous operation maximizes
flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger
latency and can eliminate uncertainty and jitter in response to a trigger.
• A temperature sensor is connected as an alternative input for ADC channel 0.
7.17 Temperature sensor
The temperature sensor transducer uses an intrinsic pn-junction diode reference and
outputs a Complement To Absolute Temperature (VCTAT) voltage. The output voltage
varies inversely with device temperature with an absolute accuracy of better than 3 C
over the full temperature range (-40 C to +105 C). The temperature sensor is only
approximately linear with a slight curvature. The output voltage is measured over different
ranges of temperatures and fit with linear-least-square lines.
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After power-up, the temperature sensor output must be allowed to settle to its stable value
before it can be used as an accurate ADC input.
For an accurate measurement of the temperature sensor by the ADC, the ADC must be
configured in single-channel burst mode. The last value of a nine-conversion (or more)
burst provides an accurate result.
7.18 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M0+. Serial wire debug
and trace functions are supported. The ARM Cortex-M0+ is configured to support up to
four breakpoints and two watch points. In addition, JTAG boundary scan mode is
provided.
The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,
execute the boot code, restart from address 0x0000 0000, and break at the user entry
point.
The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the
SWD functions by default.
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8. Limiting values
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
VDD
supply voltage (core and on pin VDD
external rail)
VDDA
analog supply voltage
on pin VDDA
Vref
reference voltage
on pin VREFP
input voltage
VI
[2]
Max
Unit
0.5
+4.6
V
0.5
+4.6
V
0.5
+4.6
V
[6][7]
0.5
+5.0
V
[5]
0.5
+5.0
V
0.5
+5.0
V
0.5
VDD
V
-
only valid when the VDD > 1.8 V;
Min
5 V tolerant I/O pins
VI
input voltage
on I2C open-drain pins
USB_DM,
USB_DP pins
[8][9]
VIA
analog input voltage
on digital pins configured for an
analog function
IDD
total supply current
per supply pin
[3]
-
60
mA
[3]
-
60
mA
-
100
mA
ISS
total ground current
per ground pin
Ilatch
I/O latch-up current
(0.5VDD) < VI < (1.5VDD);
Tj < 125 C
Vi(rtcx)
32.768 kHz oscillator
input voltage
[2]
0.5
+4.6
V
Tstg
storage temperature
[9]
65
+150
C
Tj(max)
maximum junction
temperature
-
+150
C
Ptot(pack)
total power dissipation
(per package)
based on package heat transfer,
not device power consumption
-
1.5
W
VESD
electrostatic discharge
voltage
human body model; all pins
2000
V
[3]
[1]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 20.
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 20) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3]
The peak current is limited to 25 times the corresponding maximum current.
[4]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[5]
VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[6]
Applies to all 5 V tolerant I/O pins except true open-drain pins.
[7]
Including the voltage on outputs in 3-state mode.
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[8]
An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
[9]
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[10] Dependent on package type.
9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = T amb + P D R th j – a
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 11.
Thermal resistance
Symbol Parameter
Conditions
Max/Min
Unit
JEDEC (4.5 in 4 in); still air
58 15 %
C/W
Single-layer (4.5 in 3 in); still air 81 15 %
C/W
18 15 %
C/W
LQFP64 Package
Rth(j-a)
thermal resistance from
junction to ambient
Rth(j-c)
thermal resistance from
junction to case
LQFP48 Package
Rth(j-a)
Rth(j-c)
LPC51U68
Product data sheet
thermal resistance from
junction to ambient
JEDEC (4.5 in 4 in); still air
67 15 %
C/W
Single-layer (4.5 in 3 in); still air 81 15 %
C/W
15 15 %
C/W
thermal resistance from
junction to case
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10. Static characteristics
10.1 General operating conditions
Table 12. General operating conditions
Tamb = −40 °C to +105 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
fclk
clock frequency
internal CPU/system clock
-
-
150
MHz
For USB full-speed device
operation
12
-
150
MHz
1.62
-
3.6
V
VDD
supply voltage (core
and external rail)
VDDA
analog supply voltage
Vrefp
ADC positive reference
voltage
For USB operation only
3.0
-
3.6
V
1.62
-
3.6
V
VDDA 2 V
2.0
-
VDDA
V
VDDA < 2 V
VDDA
-
VDDA
V
RTC oscillator pins
Vi(rtcx)
32.768 kHz oscillator
input voltage
on pin RTCXIN
0.5
-
+3.6
V
Vo(rtcx)
32.768 kHz oscillator
output voltage
on pin RTCXOUT
0.5
-
+3.6
V
[1]
Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.
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10.2 CoreMark data
Table 13. CoreMark score
Tamb = 25°C, VDD = 3.3V
Parameter
Conditions
Typ
Unit
ARM Cortex-M0+ in active mode
CoreMark score
CoreMark score
CoreMark code executed from SRAMX;
CCLK = 12 MHz
[1][2][3][5][6]
2.0
(Iterations/s) / MHz
CCLK = 48 MHz
[1][2][3][5][6]
2.0
(Iterations/s) / MHz
CCLK = 96 MHz
[1][2][3][5][6]
2.0
(Iterations/s) / MHz
CCLK = 150 MHz
[1][2][3][5][6]
2.0
(Iterations/s) / MHz
[1][2][3][4][6]
2.0
(Iterations/s) / MHz
CCLK = 48 MHz; 3 system clock flash
access time.
[1][2][3][4][6]
1.9
(Iterations/s) / MHz
CCLK = 96 MHz; 6 system clock flash
access time.
[1][2][3][4][6]
1.7
(Iterations/s) / MHz
CCLK = 150 MHz; 7 system clock flash
access time.
[1][2][3][4][6]
1.64
(Iterations/s) / MHz
CoreMark code executed from flash;
CCLK = 12 MHz; 1 system clock flash
access time.
[1]
Clock source FRO. PLL disabled.
[2]
Characterized through bench measurements using typical samples.
[3]
Compiler settings: Keil μVision v.5.17., optimization level 3, optimized for time ON.
[4]
See the FLASHCFG register in the LPC51U68 User Manual for system clock flash access time settings.
[5]
Flash is powered down
[6]
SRAM0 and SRAMX powered.
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aaa-028917
3
Coremark score
(iterations/s / MHz)
2.6
2.2
M0+ SRAM
1.8
M0+ Flash
1.4
1
12
24
36
48
60
72
84
96
Frequency (MHz)
108
Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled; See
the FLASHCFG register in the LPC51U68, UM11071 User Manual for system clock flash access
time settings. Measured with Keil uVision 5.17. Optimization level 3, optimized for time ON.
12 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
24 MHz, 36 MHz, 60 MHz, 72 MHz, 84 MHz, and 100 MHz: FRO enabled; PLL enabled.
Fig 8.
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Typical CoreMark score
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10.3 Power consumption
Power measurements in active, sleep, and deep-sleep modes were performed under the
following conditions:
•
•
•
•
Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
Configure GPIO pins as outputs using the GPIO DIR register.
Write 1 to the GPIO CLR register to drive the outputs LOW.
All peripherals disabled.
Table 14. Static characteristics: Power consumption in active mode
Tamb = −40 °C to +105 °C, unless otherwise specified.1.62 V ≤ VDD ≤ 3.6 V.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
ARM Cortex-M0+ in active mode
IDD
supply current
supply current
IDD
CoreMark code executed from
SRAMX; flash powered down:
CCLK = 12 MHz
[2][3][4][6][7]
-
1.1
-
mA
CCLK = 48 MHz
[2][3][4][6][7]
-
3.0
-
mA
CCLK = 96 MHz
[2][3][4][6]
-
7.1
-
mA
CCLK = 150 MHz
[2][3][4][6]
-
11.0
-
mA
[2][3][4][5][7]
-
1.3
-
mA
CCLK = 48 MHz; 3 system clock
flash access time.
[2][3][4][5][7]
-
3.6
-
mA
CCLK = 96 MHz; 7 system clock
flash access time.
[2][3][4][5]
-
8.0
-
mA
CCLK = 150 MHz; 7 system clock
flash access time.
[2][3][4][5]
-
14.0
-
mA
CoreMark code executed from flash;
CCLK = 12 MHz; 1 system clock
flash access time.
[1]
Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.
[2]
Clock source FRO. PLL disabled.
[3]
Characterized through bench measurements using typical samples.
[4]
Compiler settings: Keil μVision 5.17., optimization level 0, optimized for time off.
[5]
Prefetch disabled in FLASHCFG register. SRAM0 powered. SRAMX powered down. All peripheral clocks disabled.
[6]
Flash is powered down; SRAM0 and SRAMX are powered. All peripheral clocks disabled.
[7]
Characterized using low power regulation mode.
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LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
aaa-028918
180
μA/MHz
160
140
120
100
M0+ FLASH
80
M0+ SRAM
60
12
24
36
48
60
72
84
96
Frequency (MHz)
108
Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled; Prefetch disabled in FLASHCFG
register. See the FLASHCFG register in the LPC51U68, UM11071 User Manual for system clock flash access time settings.
SRAM0 and SRAMX powered. Measured with Keil uVision 5.17. Optimization level 0, optimized for time OFF.
12 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
24 MHz, 36 MHz, 60 MHz, 72 MHz, 84 MHz, and 100 MHz: FRO enabled; PLL enabled.
Fig 9.
CoreMark power consumption: typical A/MHz
Table 15. Static characteristics: Power consumption in sleep mode
Tamb = −40 °C to +105 °C, unless otherwise specified.1.62 V ≤ VDD ≤ 3.6 V.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
ARM Cortex-M0+ in sleep mode
IDD
supply current
CCLK = 12 MHz
[2][3]
-
900
-
A
CCLK = 48 MHz
[2][3]
-
1.6
-
mA
CCLK = 96 MHz
[2][3]
-
3.0
-
mA
[1]
Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.
[2]
Characterized through bench measurements using typical samples.
[3]
Clock source FRO. PLL disabled. All SRAM powered. Compiler settings: Keil μVision 5.17., optimization level 0, optimized for time off.
Table 16. Static characteristics: Power consumption in deep-sleep and deep power-down modes
Tamb = −40 °C to +105 °C, 1.62 V ≤. VDD ≤ 2.0 V; unless otherwise specified.
Symbol
Parameter
Conditions
IDD
supply current
Deep-sleep mode. Flash is powered down.
SRAM0 (64 KB) powered. Tamb = 25 C
Min
Typ[1][2]
Max[3] Unit
-
10
17
SRAM0 (64 KB) powered. Tamb = 105 C
A
167
Deep power-down mode;
RTC oscillator input grounded (RTC oscillator disabled).
Tamb = 25 C
LPC51U68
Product data sheet
-
290
330
nA
Tamb = 105 C
-
-
6
A
RTC oscillator running with external crystal.
-
390
-
nA
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NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
[1]
Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).
[2]
Characterized through bench measurements using typical samples. VDD = 1.62 V.
[3]
Guaranteed by characterization, not tested in production. VDD = 2.0 V.
Table 17. Static characteristics: Power consumption in deep-sleep and deep power-down modes
Tamb = −40 °C to +105 °C, 2.7 V ≤. VDD ≤ 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
IDD
supply current Deep-sleep mode. Flash is powered down.
SRAM0 (64 KB) powered. Tamb = 25 C
Min
Typ[1][2] Max[3] Unit
-
12
19
-
182
SRAM0 (64 KB) powered. Tamb = 105 C
A
Deep power-down mode;
RTC oscillator input grounded (RTC oscillator disabled).
Tamb = 25 C
-
360
470
nA
Tamb = 105 C
-
-
10
A
RTC oscillator running with external crystal.
-
450
-
nA
[1]
Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).
[2]
Characterized through bench measurements using typical samples. VDD = 3.3 V.
[3]
Tested in production, VDD = 3.6 V.
aaa-022166
80
IDD
(μA)
60
3.6V
3.3V
1.8V
1.62V
40
20
0
-40
-10
20
50
80
Temperature (°C)
110
Conditions: SRAM0 disabled except SRAMX (32 KB).
Fig 10. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD
LPC51U68
Product data sheet
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32-bit ARM Cortex-M0+ microcontroller
aaa-022167
8
IDD
(μA)
6
3.6V
3.3V
1.8V
1.62V
4
2
0
-40
-10
20
50
80
Temperature (°C)
110
Conditions: RTC disabled (RTC oscillator input grounded)
Fig 11. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD
LPC51U68
Product data sheet
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LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Table 18. Typical peripheral power consumption[1][2][3]
VDD = 3.3 V; Tamb = 25 °C
Peripheral
IDD in uA
FRO (12 MHz, 48 MHz, 96 MHz)
100.0
WDT OSC
2.0
Flash
200.0
BOD
2.0
[1]
The supply current per peripheral is measured as the difference in supply current between the peripheral
block enabled and the peripheral block disabled using PDRUNCFG0/1 registers. All other blocks are
disabled and no code accessing the peripheral is executed.
[2]
The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and 96 MHz.
[3]
Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.
Table 19. Typical AHB/APB peripheral power consumption [3][4][5]
Tamb = 25 °C, VDD = 3.3 V;
Peripheral
IDD in uA/MHz
IDD in uA/MHz
IDD in uA/MHz
AHB peripheral
CPU: 12 MHz, sync
APB bus: 12 MHz
CPU: 48 MHz, sync
APB bus: 48 MHz
CPU: 96MHz, sync
APB bus: 96 MHz
USB
2.09
2.09
2.09
Temperature sensor
0.02
0.01
0.01
GPIO0
[1]
0.65
0.65
0.65
GPIO1
[1]
0.56
0.56
0.56
DMA
0.34
0.43
0.43
CRC
0.50
0.54
0.54
ADC0
1.65
1.67
1.67
4.01
4.05
4.04
1.1
1.2
1.2
SCTimer/PWM
Flexcomm Interface 0 (USART, SPI,
I2C)
I2C)
1.2
1.2
1.2
Flexcomm Interface 2 (USART, SPI, I2C)
1.2
1.2
1.2
Flexcomm Interface 3 (USART, SPI, I2C)
1.1
1.1
1.1
Flexcomm Interface 4 (USART, SPI,
I2C)
1.2
1.2
1.2
Flexcomm Interface 5 (USART, SPI,
I2C)
Flexcomm Interface1 (USART, SPI,
1.3
1.3
1.3
Flexcomm Interface 6 (USART, SPI, I2C, I2S)
1.3
1.3
1.3
I2C, I2S)
1.3
1.3
1.4
CPU: 12 MHz, sync
APB bus: 12 MHz
CPU: 48 MHz, sync
APB bus: 48 MHz
CPU: 96MHz, sync
APB bus: 96 MHz
Flexcomm Interface 7 (USART, SPI,
Sync APB peripheral
INPUTMUX
[1]
0.87
0.93
0.93
IOCON
[1]
5.04
5.12
5.12
PINT
1.26
1.26
1.26
GINT
1.20
1.20
1.20
WWDT
0.28
0.32
0.32
RTC
0.65
0.65
0.66
MRT
0.26
0.34
0.34
UTICK
0.13
0.16
0.16
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NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Table 19. Typical AHB/APB peripheral power consumption [3][4][5]
Tamb = 25 °C, VDD = 3.3 V;
Peripheral
IDD in uA/MHz
IDD in uA/MHz
IDD in uA/MHz
CTimer0
0.52
0.50
0.50
CTimer1
0.39
0.46
0.47
Fractional Rate Generator
0.46
0.44
0.44
Async APB peripheral
CPU: 12 MHz, Async
APB bus: 12 MHz
CPU: 48 MHz, sync
APB bus: 12 MHz[2]
CPU: 96MHz,
Async APB bus: 12
MHz[2]
CTimer3
0.36
0.36
0.36
[1]
Turn off the peripheral when the configuration is done.
[2]
For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a
higher frequency.
[3]
The supply current per peripheral is measured as the difference in supply current between the peripheral
block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1, and
PDRUNCFG0 registers. All other blocks are disabled and no code accessing the peripheral is executed.
[4]
The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and 96 MHz.
[5]
Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.
10.4 Pin characteristics
Table 20. Static characteristics: pin characteristics
Tamb = −40 °C to +105 °C, unless otherwise specified. 1.62 V ≤ VDD ≤ 3.6 V unless otherwise specified. Values tested in
production unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
0.8 VDD
-
5.0
V
0.5
-
0.3 VDD V
RESET pin
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
Vhys
0.05 VDD -
-
V
-
3.0
180
nA
3.0
180
nA
-
3.0
180
nA
VDD 1.8 V
0
-
5.0
V
VDD = 0 V
0
-
3.6
V
1.62 V VDD < 2.7 V
1.5
-
5.0
V
2.7 V VDD 3.6 V
2.0
-
5.0
V
1.62 V VDD < 2.7 V
0.5
-
+0.4
V
2.7 V VDD 3.6 V
0.5
-
+0.8
V
0.1 VDD
-
-
V
[1][14]
hysteresis voltage
Standard I/O pins
Input characteristics
IIL
LOW-level input current
VI = 0 V; on-chip pull-up resistor
disabled.
IIH
HIGH-level input current
VI = VDD; VDD = 3.6 V; for RESETN
pin.
IIH
HIGH-level input current
VI = VDD; on-chip pull-down resistor
disabled
VI
input voltage
pin configured to provide a digital
function;
VIH
VIL
Vhys
HIGH-level input voltage
LOW-level input voltage
[14]
hysteresis voltage
LPC51U68
Product data sheet
[3]
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LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Table 20. Static characteristics: pin characteristics …continued
Tamb = −40 °C to +105 °C, unless otherwise specified. 1.62 V ≤ VDD ≤ 3.6 V unless otherwise specified. Values tested in
production unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Output characteristics
VO
output voltage
output active
0
-
VDD
V
IOZ
OFF-state output current
VO = 0 V; VO = VDD; on-chip
pull-up/pull-down resistors disabled
-
3
180
nA
VOH
HIGH-level output voltage IOH = 4 mA; 1.62 V VDD < 2.7 V
VDD 0.4
-
-
V
VOL
LOW-level output voltage IOL = 4 mA; 1.62 V VDD < 2.7 V
-
-
0.4
V
-
-
0.4
V
4.0
-
-
mA
6.0
-
-
mA
4.0
-
-
mA
IOH = 6 mA; 2.7 V VDD 3.6 V
VDD 0.4
IOL = 6 mA; 2.7 V VDD 3.6 V
IOH
HIGH-level output current VOH = VDD 0.4 V;
1.62 V VDD < 2.7 V
VOH = VDD 0.4 V;
2.7 V VDD 3.6 V
IOL
LOW-level output current VOL = 0.4 V; 1.62 V VDD < 2.7 V
IOHS
HIGH-level short-circuit
output current
1.62 V VDD < 2.7 V
drive HIGH; connected to
ground;
2.7 V VDD 3.6 V
LOW-level short-circuit
output current
1.62 V VDD < 2.7 V
drive LOW; connected to
VDD
2.7 V VDD 3.6 V
VOL = 0.4 V; 2.7 V VDD 3.6 V
IOLS
[2][4]
[2][4]
6.0
-
-
mA
-
-
35
mA
-
-
87
mA
-
-
30
mA
-
-
77
mA
25
80
A
80
100
A
Weak input pull-up/pull-down characteristics
Ipd
pull-down current
VI = VDD
[2]
VI = 5 V
Ipu
pull-up current
VI = 0 V
VDD < VI < 5 V
[2][7]
25
80
A
6
30
A
Open-drain I2C pins
VIH
HIGH-level input voltage
1.62 V VDD < 2.7 V
0.7 VDD
-
-
V
2.7 V VDD 3.6 V
0.7 VDD
-
-
V
VIL
LOW-level input voltage
1.62 V VDD < 2.7 V
0
-
0.3 VDD V
2.7 V VDD 3.6 V
0
-
0.3 VDD V
0.1 VDD
-
-
V
Vhys
ILI
IOL
hysteresis voltage
input leakage current
LOW-level output
current
LPC51U68
Product data sheet
-
2.5
3.5
A
VI = 5 V
-
5.5
10
A
VOL = 0.4 V; pin configured for
standard mode or fast mode
4.0
-
-
mA
VOL = 0.4V; pin configured for
Fast-mode Plus
20
-
-
mA
[5]
VI = VDD
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LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Table 20. Static characteristics: pin characteristics …continued
Tamb = −40 °C to +105 °C, unless otherwise specified. 1.62 V ≤ VDD ≤ 3.6 V unless otherwise specified. Values tested in
production unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
USB_DM and USB_DP pins
VI
input voltage
0
-
VDD
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
Vhys
hysteresis voltage
0.4
-
-
V
Zout
output impedance
[11]
33.0
-
44
Ω
VOH
HIGH-level output voltage
[12]
2.8
-
-
V
VOL
LOW-level output voltage
[13]
IOH
IOL
-
-
0.3
V
HIGH-level output current VOH = VDD 0.3 V
[9][10]
38
-
74
mA
VOH = VDD 0.3 V
[10][11]
6.0
9.0
mA
LOW-level output current VOL = 0.3 V
[9][10]
38
-
74
mA
VOL = 0.3 V
[10][11]
6.0
9.0
mA
IOLS
LOW-level short-circuit
output current
drive LOW; pad connected to
ground
[10]
IOHS
HIGH-level short-circuit
output current
drive HIGH; pad connected to
ground
[10]
-
-
100
mA
I2C-bus pins
[8]
-
-
6.0
pF
pins with digital functions only
[6]
-
-
2.0
pF
Pins with digital and analog
functions
[6]
-
-
7.0
pF
-
-
100
mA
Pin capacitance
Cio
input/output capacitance
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.
[2]
Based on characterization. Not tested in production.
[3]
With respect to ground.
[4]
Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[5]
To VSS.
[6]
The values specified are simulated and absolute values, including package/bondwire capacitance.
[7]
The weak pull-up resistor is connected to the VDD rail and pulls up the I/O pin to the VDD level.
[8]
The value specified is a simulated value, excluding package/bondwire capacitance.
[9]
Without 33 Ω 2 % series external resistor.
[10] The parameter values specified are simulated and absolute values.
[11] With 33 Ω 2 % series external resistor.
[12] With 15 KΩ 5 % resistor to VSS.
[13] With 1.5 KΩ 5% resistor to 3.6 V external pull-up.
[14] Guaranteed by design, not tested in production.
LPC51U68
Product data sheet
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LPC51U68
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32-bit ARM Cortex-M0+ microcontroller
VDD
IOL
Ipd
+
-
pin PIO0_n
A
IOH
Ipu
-
+
pin PIO0_n
A
aaa-010819
Fig 12. Pin input/output current measurement
10.4.1 Electrical pin characteristics
aaa-017309
60
-40C
25C
90C
105C
IOL
(mA)
50
aaa-017310
60
IOL
(mA)
-40C
25C
90C
105C
45
40
30
30
20
15
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
Conditions: VDD = 1.8 V; on pins PIO0_23 to PIO0_26.
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
Conditions: VDD = 3.3 V; on pins PIO0_23 to PIO0_26.
Fig 13. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage
VOL
LPC51U68
Product data sheet
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Rev. 1.5 — 13 January 2020
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LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
aaa-017311
12
IOL
(mA)
aaa-017312
15
-40C
25C
90C
105C
IOL
(mA)
10
12
-40C
90C
25C
105C
8
9
6
6
4
3
2
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
0
Conditions: VDD = 1.8 V; on standard port pins.
0.1
0.2
0.3
0.4
0.5
VOL (V)
0.6
Conditions: VDD = 3.3 V; on standard port pins.
Fig 14. Typical LOW-level output current IOL versus LOW-level output voltage VOL
aaa-017313
1.8
VOH
(V)
1.7
aaa-017314
3.5
VOH
(V)
3.2
1.6
2.9
-40C
25C
90C
105C
1.5
-40C
25C
90C
105C
2.6
1.4
2.3
1.3
1.2
2
0
2.4
4.8
7.2
9.6
IOH (mA)
12
Conditions: VDD = 1.8 V; on standard port pins.
0
7
14
21
28
IOH (mA)
35
Conditions: VDD = 3.3 V; on standard port pins.
Fig 15. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH
LPC51U68
Product data sheet
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Rev. 1.5 — 13 January 2020
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55 of 95
LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
aaa-017315
40
Ipu
(μA)
aaa-017316
50
Ipu
(μA)
30
20
10
0
-10
-40C
25C
90C
105C
-20
-40C
25C
90C
105C
-30
-50
-40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VI (V)
-70
0.0
3.5
Conditions: VDD = 1.8 V; on standard port pins.
1.0
2.0
3.0
4.0
VI (V)
5.0
Conditions: VDD = 3.3 V; on standard port pins.
Fig 16. Typical pull-up current IPU versus input voltage VI
aaa-017317
70
Ipd
(μA)
56
80
42
60
28
40
25C
-40C
90C
105C
14
0
0.0
aaa-017318
100
Ipd
(μA)
105C
90C
25C
-40C
20
0
0.7
1.4
2.1
2.8
VI (V)
3.5
Conditions: VDD = 1.8V; on standard port pins.
0
1
2
3
4
VI (V)
5
Conditions: VDD = 3.3 V; on standard port pins.
Fig 17. Typical pull-down current IPD versus input voltage VI
LPC51U68
Product data sheet
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LPC51U68
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32-bit ARM Cortex-M0+ microcontroller
11. Dynamic characteristics
11.1 Flash memory
Table 21. Flash characteristics
Tamb = −40 °C to +105 °C, unless otherwise specified. 1.62 V ≤ VDD ≤ 3.6 V unless otherwise
specified.
Min
Typ[1]
Max
Unit
10000
-
-
cycles
page erase/program; page
in a sector
1000
-
-
cycles
powered
10
-
-
years
unpowered
10
-
-
years
page, sector, or multiple
consecutive sectors
-
100
-
ms
-
1
-
ms
Symbol
Parameter
Conditions
Nendu
endurance
sector erase/program
retention time
tret
ter
erase time
tprog
programming
time
[2]
[3]
[1]
Typical ratings are not guaranteed.
[2]
Number of erase/program cycles.
[3]
Programming times are given for writing 256 bytes from RAM to the flash.
11.2 I/O pins
For I/O pins that are configured as input only, there is no limitation on the rise and fall
times.
Table 22. Dynamic characteristic: I/O pins[1]
Tamb = −40 °C to +85 °C unless otherwise specified; 1.62 V ≤ VDD ≤ 3.6 V unless otherwise
specified.
Symbol Parameter Conditions
Min
Typ
Max
Unit
Standard I/O pins - normal drive strength
tr
tf
rise time
fall time
pin configured as output; SLEW = 1 (fast
mode);
[2][3]
2.7 V VDD 3.6 V
1.0
-
2.5
ns
1.62 V VDD 1.98 V
1.6
-
3.8
ns
0.9
-
2.5
ns
1.7
-
4.1
ns
2.7 V VDD 3.6 V
1.9
-
4.3
ns
1.62 V VDD 1.98 V
2.9
-
7.8
ns
pin configured as output; SLEW = 1 (fast
mode);
[2][3]
2.7 V VDD 3.6 V
1.62 V VDD 1.98 V
tr
LPC51U68
Product data sheet
rise time
pin configured as output; SLEW = 0
(standard mode);
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Rev. 1.5 — 13 January 2020
[2][3]
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Table 22. Dynamic characteristic: I/O pins[1]
Tamb = −40 °C to +85 °C unless otherwise specified; 1.62 V ≤ VDD ≤ 3.6 V unless otherwise
specified.
Symbol Parameter Conditions
tf
fall time
Min
Typ
Max
Unit
1.9
-
4.0
ns
[2][3]
pin configured as output; SLEW = 0
(standard mode);
2.7 V VDD 3.6 V
1.62 V VDD 1.98 V
tr
rise time
pin configured as input
[4]
tf
fall time
pin configured as input
[4]
2.7
-
6.7
ns
0.3
-
1.3
ns
0.2
-
1.2
ns
[1]
Simulated data.
[2]
Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between
80 % and 20 % of the full output signal level.
[3]
The slew rate is configured in the IOCON block the SLEW bit. See the LPC51U68 UM11071 user manual.
[4]
CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.
11.3 Wake-up process
Table 23. Dynamic characteristic: Typical wake-up times from low power modes
VDD = 3.3 V;Tamb = 25 °C; using FRO as the system clock.
Symbol Parameter
twake
Min
Typ[1]
Max Unit
[2][3]
-
2.0
-
[2][3][5]
-
19
-
s
[4][5]
-
1.2
-
ms
Conditions
wake-up
time
from Sleep mode
from Deep-sleep mode
from deep power-down mode;
RTC disabled; using RESET pin.
s
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2]
The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up
from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)
wake-up handler.
[3]
FRO enabled, all peripherals off. PLL disabled.
[4]
RTC disabled. Wake up from deep power-down causes the part to go through entire reset
process. The wake-up time measured is the time between when the RESET pin is triggered to wake the
device up and when a GPIO output pin is set in the reset handler.
[5]
FRO disabled.
11.4 System PLL
Table 24. PLL lock times and current
Tamb = −40 °C to +105 °C. VDD = 1.62 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
PLL configuration: input frequency 12 MHz; output frequency 75 MHz
tlock(PLL)
IDD(PLL)
PLL lock time
PLL current
PLL set-up procedure followed
when locked
[2]
-
-
400
s
[1][3]
-
-
550
A
PLL configuration: input frequency 12 MHz; output frequency 100 MHz
tlock(PLL)
PLL lock time
PLL set-up procedure followed
IDD(PLL)
PLL current
when locked
[2]
-
-
400
s
[1][3]
-
-
750
A
PLL configuration: input frequency 32.768 kHz; output frequency 75 MHz
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Table 24. PLL lock times and current
Tamb = −40 °C to +105 °C. VDD = 1.62 V to 3.6 V.
Symbol
tlock(PLL)
IDD(PLL)
Parameter
PLL lock time
PLL current
Conditions
when locked
Min
Typ Max
Unit
[1]
-
-
6250
s
[1][3]
-
-
450
A
PLL configuration: input frequency 32.768 kHz; output frequency 100 MHz
tlock(PLL)
IDD(PLL)
LPC51U68
Product data sheet
PLL lock time
PLL current
when locked
[1]
-
-
6250
s
[1][3]
-
-
560
A
[1]
Data based on characterization results, not tested in production.
[2]
PLL set-up requires high-speed start-up and transition to normal mode. Lock times are only valid when
high-speed start-up settings are applied followed by normal mode settings. The procedure for setting up the
PLL is described in the LPC51U68 user manual.
[3]
PLL current measured using lowest CCO frequency to obtain the desired output frequency.
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Table 25. Dynamic characteristics of the PLL[1]
Tamb = −40 °C to +105 °C. VDD = 1.62 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
input frequency
-
32.768 kHz
-
25 MHz
-
fo
output frequency
for PLL clkout output
1.2
-
150
MHz
do
output duty cycle
for PLL clkout output
46
-
54
%
fCCO
CCO frequency
-
-
-
150
MHz
1
2
4
ns
Reference clock input
Fin
Clock output
[2]
Lock detector output
lock(PFD)
PFD lock criterion
[3]
-
Dynamic parameters at fout = fCCO = 100 MHz; standard bandwidth settings
Jrms-interval
Jpp-period
RMS interval jitter
peak-to-peak, period jitter
fref = 10 MHz
[4][5]
-
15
30
ps
fref = 10 MHz
[4][5]
-
40
80
ps
[1]
Data based on characterization results, not tested in production.
[2]
Excluding under- and overshoot which may occur when the PLL is not in lock.
[3]
A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion
means lock output is HIGH.
[4]
Actual jitter dependent on amplitude and spectrum of substrate noise.
[5]
Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.
11.5 FRO
The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.
Table 26. Dynamic characteristic: FRO
Tamb = −40 °C to +105 °C; 1.62 V ≤ VDD ≤ 3.6 V
Symbol
Parameter
Min[2]
Typ[1]
Max[2]
Unit
fosc(FRO)
FRO clock frequency
11.88
12
12.12
MHz
fosc(FRO)
FRO clock frequency
47.52
48
48.48
MHz
fosc(FRO)
FRO clock frequency
95.04
96
96.96
MHz
[1]
Tested in production.The values listed are at room temperature (25 C).
[2]
Data based on characterization results, not tested in production.
11.6 RTC oscillator
See Section 13.5 for connecting the RTC oscillator to an external clock source.
Table 27. Dynamic characteristic: RTC oscillator
Tamb = −40 °C to +105 °C; 1.62 V ≤ VDD ≤ 3.6 V[1]
Symbol
Parameter
Min
Typ
Max
Unit
fi
input frequency
-
32.768
-
kHz
[1]
LPC51U68
Product data sheet
Parameters are valid over operating temperature range unless otherwise specified.
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11.7 Watchdog oscillator
Table 28. Dynamic characteristics: Watchdog oscillator
Tamb = −40 °C to +105 °C; 1.62 V ≤ VDD ≤ 3.6 V
Symbol
Parameter
fosc(int)
internal watchdog oscillator
frequency
Dclkout
clkout duty cycle
JPP-CC
peak-peak period jitter
start-up time
tstart
[2]
Min
Typ[1]
Max
Unit
6
-
1500
kHz
48
-
52
%
[3][4]
-
1
20
ns
[4]
-
4
-
s
[1]
Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2]
The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.
[3]
Actual jitter dependent on amplitude and spectrum of substrate noise.
[4]
Guaranteed by design. Not tested in production samples.
11.8 I2C-bus
Table 29. Dynamic characteristic: I2C-bus pins[1]
Tamb = −40 °C to +105 °C; 1.62 V ≤ VDD ≤ 3.6 V[2]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
of both SDA and SCL signals
-
300
ns
20 + 0.1 Cb
300
ns
fall time
tf
[4][5][6][7]
Standard-mode
Fast-mode
Fast-mode Plus
tLOW
tHIGH
tHD;DAT
tSU;DAT
LOW period of the SCL clock
HIGH period of the SCL clock
data hold time
data set-up time
[3][4][8]
[9][10]
-
120
ns
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
[1]
Guaranteed by design. Not tested in production.
[2]
Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
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[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[8]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
tf
SDA
tSU;DAT
70 %
30 %
70 %
30 %
tHD;DAT
tf
70 %
30 %
SCL
tVD;DAT
tHIGH
70 %
30 %
70 %
30 %
70 %
30 %
tLOW
S
1 / fSCL
002aaf425
Fig 18. I2C-bus pins clock timing
11.9 I2S-bus interface
Table 30. Dynamic characteristics: I2S-bus interface pins [1][4]
Tamb = −40 °C to 105 °C; VDD = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol
Parameter
Conditions
Min
Typ[3]
Max
Unit
Common to master and slave
tWH
tWL
LPC51U68
Product data sheet
pulse width HIGH
pulse width LOW
on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]
CCLK = 1 MHz to 12 MHz
(Tcyc/2) -1 -
(Tcyc/2) +1 ns
CCLK = 48 MHz to 60 MHz
(Tcyc/2) -1 -
(Tcyc/2) +1 ns
CCLK = 96 MHz
(Tcyc/2) -1 -
(Tcyc/2) +1 ns
on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]
CCLK = 1 MHz to 12 MHz
(Tcyc/2) -1 -
(Tcyc/2) +1 ns
CCLK = 48 MHz to 60 MHz
(Tcyc/2) -1 -
(Tcyc/2) +1 ns
CCLK = 96 MHz
(Tcyc/2) -1 -
(Tcyc/2) +1 ns
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Table 30. Dynamic characteristics: I2S-bus interface pins [1][4]
Tamb = −40 °C to 105 °C; VDD = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol
Parameter
Min
Typ[3]
Max
Unit
CCLK = 1 MHz to 12 MHz
32.7
-
56.6
ns
CCLK = 48 MHz to 60 MHz
29.9
-
48.9
ns
CCLK = 96 MHz
29.0
-
47.2
ns
CCLK = 1 MHz to 12 MHz
35.1
-
61.1
ns
CCLK = 48 MHz to 60 MHz
31.9
-
51.8
ns
31.0
-
49.7
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
CCLK = 96 MHz
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
25.8
-
47.0
ns
CCLK = 48 MHz to 60 MHz
23.0
-
38.9
ns
22.2
-
37.1
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
CCLK = 96 MHz
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
1.0
-
-
ns
CCLK = 48 MHz to 60 MHz
1.0
-
-
ns
CCLK = 96 MHz
1.0
-
-
ns
CCLK = 1 MHz to 12 MHz
2.0
-
-
ns
CCLK = 48 MHz to 60 MHz
2.0
-
-
ns
CCLK = 96 MHz
2.0
-
-
ns
Conditions
Master; 1.62 V VDD 2.0 V
tv(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
on pin I2Sx_WS
CCLK = 96 MHz
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK = 96 MHz
th(D)
data input hold time
on pin I2Sx_RX_SDA
[2]
Slave; 1.62 V VDD 2.0 V
tv(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK = 96 MHz
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
on pin I2Sx_RX_WS
CCLK = 96 MHz
th(D)
data input hold time
on pin I2Sx_RX_SDA
[2]
on pin I2Sx_RX_WS
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32-bit ARM Cortex-M0+ microcontroller
Table 30. Dynamic characteristics: I2S-bus interface pins [1][4]
Tamb = −40 °C to 105 °C; VDD = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol
Parameter
Min
Typ[3]
Max
Unit
CCLK = 1 MHz to 12 MHz
24.2
-
40.8
ns
CCLK = 48 MHz to 60 MHz
22.0
-
32.2
ns
CCLK = 96 MHz
21.3
-
30.3
ns
CCLK = 1 MHz to 12 MHz
24.9
-
44.3
ns
CCLK = 48 MHz to 60 MHz
22.6
-
34.0
ns
21.8
-
31.7
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
1.7
-
-
ns
CCLK = 48 MHz to 60 MHz
1.4
-
-
ns
CCLK = 96 MHz
1.2
-
-
ns
CCLK = 1 MHz to 12 MHz
17.4
-
33.8
ns
CCLK = 48 MHz to 60 MHz
15.2
-
25.1
ns
14.5
-
23.0
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
CCLK = 96 MHz
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
0.0
-
-
ns
CCLK = 48 MHz to 60 MHz
0.0
-
-
ns
CCLK = 96 MHz
0.0
-
-
ns
CCLK = 1 MHz to 12 MHz
1.0
-
-
ns
CCLK = 48 MHz to 60 MHz
1.0
-
-
ns
CCLK = 96 MHz
1.0
-
-
ns
Conditions
Master; 2.7 V VDD 3.6 V
tv(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
on pin I2Sx_WS
CCLK = 96 MHz
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK = 96 MHz
th(D)
data input hold time
on pin I2Sx_RX_SDA
[2]
Slave; 2.7 V VDD 3.6 V
tv(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK = 96 MHz
tsu(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
on pin I2Sx_RX_WS
CCLK = 96 MHz
th(D)
data input hold time
on pin I2Sx_RX_SDA
[2]
on pin I2Sx_RX_WS
[1]
LPC51U68
Product data sheet
Based on characterization; not tested in production.
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[2]
Clock Divider register (DIV) = 0x0.
[3]
Typical ratings are not guaranteed.
[4]
The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section
in the I2S chapter (UM10912) to calculate clock and sample rates.
[5]
Based on simulation. Not tested in production.
Tcy(clk)
tf
tr
I2Sx_SCK
tWH
tWL
I2Sx_TX_SDA
tv(Q)
I2Sx_RX_SDA
tsu(D)
th(D)
I2Sx_WS
aaa-026799
tv(Q)
Fig 19. I2S-bus timing (master)
Tcy(clk)
tf
tr
I2Sx_SCK
tWH
tWL
I2Sx_TX_SDA
tv(Q)
I2Sx_RX_SDA
tsu(D)
th(D)
I2Sx_WS
tsu(D)
th(D)
aaa-026800
Fig 20. I2S-bus timing (slave)
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32-bit ARM Cortex-M0+ microcontroller
11.10 SPI interfaces
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 71 Mbit/s, and the maximum supported bit rate for SPI slave mode is 15 Mbit/s.
Table 31. SPI dynamic characteristics[1]
Tamb = −40 °C to 105 °C; VDD = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
CCLK = 1 MHz to 12 MHz
0
-
-
ns
CCLK = 48 MHz to 60 MHz
0
-
-
ns
SPI master 1.62 V VDD 2.0 V
tDS
tDH
tv(Q)
data set-up time
data hold time
data output valid time
CCLK = 96 MHz
0
-
-
ns
CCLK = 1 MHz to 12 MHz
7
-
-
ns
CCLK = 48 MHz to 60 MHz
7
-
-
ns
CCLK = 96 MHz
7
-
-
ns
CCLK = 1 MHz to 12 MHz
0
-
5
ns
CCLK = 48 MHz to 60 MHz
0
-
3
ns
CCLK = 96 MHz
0
-
2
ns
CCLK = 1 MHz to 12 MHz
1
-
-
ns
CCLK = 48 MHz to 60 MHz
1
-
-
ns
CCLK = 96 MHz
1
-
-
ns
CCLK = 1 MHz to 12 MHz
2
-
-
ns
SPI slave 1.62 V VDD 2.0 V
tDS
tDH
tv(Q)
data set-up time
data hold time
data output valid time
CCLK = 48 MHz to 60 MHz
3
-
-
ns
CCLK = 96 MHz
3
-
-
ns
CCLK = 1 MHz to 12 MHz
30
-
58
ns
CCLK = 48 MHz to 60 MHz
23
-
48
ns
CCLK = 96 MHz
21
-
45
ns
CCLK = 1 MHz to 12 MHz
3
-
-
ns
CCLK = 48 MHz to 60 MHz
4
-
-
ns
SPI master 2.7 V VDD 3.6 V
tDS
tDH
tv(Q)
data set-up time
data hold time
data output valid time
LPC51U68
Product data sheet
CCLK = 96 MHz
4
-
-
ns
CCLK = 1 MHz to 12 MHz
11
-
-
ns
CCLK = 48 MHz to 60 MHz
11
-
-
ns
CCLK = 96 MHz
10
-
-
ns
CCLK = 1 MHz to 12 MHz
0
-
5
ns
CCLK = 48 MHz to 60 MHz
0
-
3
ns
CCLK = 96 MHz
0
-
3
ns
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Table 31. SPI dynamic characteristics[1]
Tamb = −40 °C to 105 °C; VDD = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
CCLK = 1 MHz to 12 MHz
2
-
-
ns
CCLK = 48 MHz to 60 MHz
1
-
-
ns
CCLK = 96 MHz
1
-
-
ns
CCLK = 1 MHz to 12 MHz
1
-
-
ns
SPI slave 2.7 V VDD 3.6 V
tDS
data set-up time
data hold time
tDH
data output valid time
tv(Q)
CCLK = 48 MHz to 60 MHz
1
-
-
ns
CCLK = 96 MHz
1
-
-
ns
CCLK = 1 MHz to 12 MHz
20
-
44
ns
CCLK = 48 MHz to 60 MHz
15
-
32
ns
CCLK = 96 MHz
13
-
30
ns
[1]
Based on characterization; not tested in production.
[2]
Typical ratings are not guaranteed.
Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
MOSI (CPHA = 0)
tv(Q)
tv(Q)
DATA VALID (MSB)
DATA VALID
DATA VALID (MSB)
MOSI (CPHA = 1)
IDLE
DATA VALID (MSB)
DATA VALID (LSB)
IDLE
DATA VALID (MSB)
tDH
tDS
MISO (CPHA = 0)
DATA VALID (LSB)
DATA VALID
tv(Q)
tv(Q)
DATA VALID (LSB)
DATA VALID
tDS
MISO (CPHA = 1)
DATA VALID (LSB)
DATA VALID (MSB)
IDLE
DATA VALID (MSB)
DATA VALID (MSB)
IDLE
DATA VALID (MSB)
tDH
DATA VALID
aaa-014969
Fig 21. SPI master timing
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Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
MISO (CPHA = 0)
tv(Q)
tv(Q)
DATA VALID (MSB)
DATA VALID
DATA VALID (MSB)
MISO (CPHA = 1)
IDLE
DATA VALID (MSB)
DATA VALID (LSB)
IDLE
DATA VALID (MSB)
tDH
tDS
MOSI (CPHA = 0)
DATA VALID (LSB)
DATA VALID
tv(Q)
tv(Q)
DATA VALID (LSB)
DATA VALID
tDS
MOSI (CPHA = 1)
DATA VALID (LSB)
DATA VALID (MSB)
IDLE
DATA VALID (MSB)
DATA VALID (MSB)
IDLE
DATA VALID (MSB)
tDH
DATA VALID
aaa-014970
Fig 22. SPI slave timing
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11.11 USART interface
The actual USART bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for USART
master synchronous mode is 20 Mbit/s, and the maximum supported bit rate for USART
slave synchronous mode is 16 Mbit/s
Table 32. USART dynamic characteristics[1]
Tamb = −40 °C to 105 °C; VDD = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol Parameter
Min
Typ[2]
Max
Unit
CCLK = 1 MHz to 12 MHz
45
-
-
ns
CCLK = 48 MHz to 60 MHz
39
-
-
ns
Conditions
USART master (in synchronous mode) 1.62 V VDD 2.0 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
CCLK = 96 MHz
38
-
-
ns
CCLK = 1 MHz to 12 MHz
0
-
-
ns
CCLK = 48 MHz to 60 MHz
0
-
-
ns
CCLK = 96 MHz
0
-
-
ns
CCLK = 1 MHz to 12 MHz
2
-
9
ns
CCLK = 48 MHz to 60 MHz
1
-
5
ns
CCLK = 96 MHz
1
-
4
ns
CCLK = 1 MHz to 12 MHz
1
-
-
ns
CCLK = 48 MHz to 60 MHz
1
-
-
ns
CCLK = 96 MHz
1
-
-
ns
CCLK = 1 MHz to 12 MHz
2
-
-
ns
USART slave (in synchronous mode) 1.62 V VDD 2.0 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
CCLK = 48 MHz to 60 MHz
3
-
-
ns
CCLK = 96 MHz
3
-
-
ns
CCLK = 1 MHz to 12 MHz
30
-
55
ns
CCLK = 48 MHz to 60 MHz
23
-
46
ns
CCLK = 96 MHz
22
-
46
ns
CCLK = 1 MHz to 12 MHz
35
-
-
ns
CCLK = 48 MHz to 60 MHz
27
-
-
ns
USART master (in synchronous mode) 2.7 V VDD 3.6 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
LPC51U68
Product data sheet
CCLK = 96 MHz
25
-
-
ns
CCLK = 1 MHz to 12 MHz
0
-
-
ns
CCLK = 48 MHz to 60 MHz
0
-
-
ns
CCLK = 96 MHz
0
-
-
ns
CCLK = 1 MHz to 12 MHz
2
-
9
ns
CCLK = 48 MHz to 60 MHz
2
-
5
ns
CCLK = 96 MHz
1
-
4
ns
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Table 32. USART dynamic characteristics[1]
Tamb = −40 °C to 105 °C; VDD = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol Parameter
Min
Typ[2]
Max
Unit
CCLK = 1 MHz to 12 MHz
2
-
-
ns
CCLK = 48 MHz to 60 MHz
1
-
-
ns
CCLK = 96 MHz
1
-
-
ns
CCLK = 1 MHz to 12 MHz
2
-
-
ns
Conditions
USART slave (in synchronous mode) 2.7 V VDD 3.6 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
CCLK = 48 MHz to 60 MHz
1
-
-
ns
CCLK = 96 MHz
1
-
-
ns
CCLK = 1 MHz to 12 MHz
19
-
42
ns
CCLK = 48 MHz to 60 MHz
14
-
31
ns
CCLK = 96 MHz
13
-
28
ns
[1]
Based on characterization; not tested in production.
[2]
Typical ratings are not guaranteed.
Tcy(clk)
Un_SCLK (CLKPOL = 0)
Un_SCLK (CLKPOL = 1)
tv(Q)
tvQ)
START
TXD
BIT0
BIT1
tsu(D) th(D)
START
RXD
BIT1
BIT0
aaa-015074
Fig 23. USART timing
11.12 SCTimer/PWM output timing
Table 33. SCTimer/PWM output dynamic characteristics
Tamb = −40 °C to 105 °C; 1.62 V ≤ VDD ≤ 3.6 V CL = 30 pF. Simulated skew (over process, voltage,
and temperature) of any two SCT fixed-pin output signals; sampled at 10 % and 90 % of the signal
level; values guaranteed by design.
LPC51U68
Product data sheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tsk(o)
output skew time
-
-
-
2.7
ns
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11.13 USB interface characteristics
Table 34. Dynamic characteristics: USB pins (Full-Speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD, unless otherwise specified; 3.0 V ≤ VDD ≤ 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
10 % to 90 %
4.0
-
20
ns
tf
fall time
10 % to 90 %
4.0
-
20
ns
tFRFM
differential rise and fall time matching
tr / tf
90
-
111.11
%
VCRS
output signal crossover voltage
1.3
-
2.0
V
tFEOPT
source SE0 interval of EOP
see Figure 26
160
-
175
ns
tFDEOP
source jitter for differential transition
to SE0 transition
see Figure 26
2
-
+5
ns
tJR1
receiver jitter to next transition
18.5
-
+18.5
ns
tJR2
receiver jitter for paired transitions
10 % to 90 %
9
-
+9
ns
tEOPR1
EOP width at receiver
must reject as
EOP; see
Figure 26
[1]
40
-
tEOPR2
EOP width at receiver
must accept as
EOP; see
Figure 26
[1]
82
-
[1]
ns
-
ns
Characterized but not implemented as production test. Guaranteed by design.
TPERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: tFEOPT
differential data to
SE0/EOP skew
n TPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2
002aab561
Fig 24. Differential data-to-EOP transition skew and EOP width
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12. Analog characteristics
12.1 BOD
Table 35. BOD static characteristics
Tamb = 25 °C; based on characterization; not tested in production.
Symbol
Parameter
Conditions
Vth
threshold voltage
interrupt level 0
Vth
threshold voltage
Min
Typ
Max
Unit
assertion
-
1.97
-
V
de-assertion
-
2.11
-
V
interrupt level 1
assertion
-
2.36
-
V
de-assertion
-
2.51
-
V
assertion
-
1.77
-
V
de-assertion
-
1.92
-
V
assertion
-
2.66
-
V
de-assertion
-
2.80
-
V
assertion
-
1.92
-
V
de-assertion
-
2.06
-
V
reset level 1
Vth
threshold voltage
interrupt level 2
reset level 2
Vth
threshold voltage
interrupt level 3
assertion
-
2.95
-
V
de-assertion
-
3.09
-
V
assertion
-
2.21
-
V
de-assertion
-
2.36
-
V
reset level 3
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12.2 12-bit ADC characteristics
Table 36. 12-bit ADC static characteristics
Tamb = −40 °C to +105 °C; 1.62 V ≤ VDD ≤ 3.6 V; VSSA = VREFN = GND. ADC calibrated at Tamb = 25 °C.
Min
Typ[2]
Max
Unit
[3]
0
-
VDDA
V
[4]
-
5
-
pF
-
80
MHz
-
-
5.0
Msamples/s
[1][5]
-
3.0
-
LSB
2.0 V VDDA 3.6 V
2.0 V VREFP 3.6 V
fclk(ADC) = 80 MHz
[1][5]
-
3.0
-
LSB
VDDA = VREFP = 1.62 V
fclk(ADC) = 80 MHz
[1][5]
-
7.1
-
LSB
1.62 V VDDA 3.6 V
1.62 V VREFP 3.6 V
fclk(ADC) 72 MHz
[1][6]
-
5.0
-
LSB
2.0 V VDDA 3.6 V
2.0 V VREFP 3.6 V
fclk(ADC) = 80 MHz
[1][6]
-
4.0
-
LSB
VDDA = VREFP = 1.62 V
fclk(ADC) = 80 MHz
[1][6]
-
9.0
-
LSB
-
Symbol
Parameter
VIA
analog input
voltage
Cia
analog input
capacitance
fclk(ADC)
ADC clock
frequency
fs
sampling
frequency
ED
differential linearity 1.62 V VDDA 3.6 V
error
1.62 V VREFP 3.6 V
fclk(ADC) = 72 MHz
EL(adj)
Conditions
integral
non-linearity
EO
offset error
calibration enabled
[1][7]
-
1.2
Verr(FS)
full-scale error
voltage
1.62 V VDDA 2.0 V
1.62 V VREFP 2.0 V
[1][8]
-
3.5
LSB
-
2.0
LSB
17.0
-
2.0 V VDDA 3.6 V
2.0 V VREFP 3.6 V
Zi
input impedance
LPC51U68
Product data sheet
fs = 5.0 Msamples/s
[9][10]
-
mV
k
[1]
Based on characterization; not tested in production.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[3]
The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5.
[4]
Cia represents the external capacitance on the analog input channel for sampling speeds of
5.0 Msamples/s. No parasitic capacitances included.
[5]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
See Figure 25.
[6]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 25.
[7]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 25.
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[8]
The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See
Figure 25.
[9]
Tamb = 25 C; maximum sampling frequency fs = 5.0 Msamples/s and analog input capacitance Cia = 5 pF.
[10] Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including
Cia and Cio: Zi 1 / (fs Ci). See Table 20 for Cio. See Figure 26.
offset
error
EO
gain
error
EG
4095
4094
4093
4092
4091
4090
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
4090
4091
4092
4093
4094
4095
4096
VIA (LSBideal)
offset error
EO
1 LSB =
VREFP - VREFN
4096
aaa-016908
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 25. 12-bit ADC characteristics
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Table 37. ADC sampling times [1]
Tamb = -40 °C to 85 °C; 1.62 V ≤ VDDA ≤ 3.6 V; 1.62 V ≤ VDD ≤ 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
20
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
23
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
26
-
-
ns
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
0.2 kΩ Zo < 0.5 kΩ
31
-
-
ns
0.5 kΩ Zo < 1 kΩ
47
-
-
ns
1 kΩ Zo < 5 kΩ
75
-
-
ns
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 10 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
15
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
18
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
20
-
-
ns
0.2 kΩ Zo < 0.5 kΩ
24
-
-
ns
0.5 kΩ Zo < 1 kΩ
38
-
-
ns
1 kΩ Zo < 5 kΩ
62
-
-
ns
12
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
13
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
15
-
-
ns
0.2 kΩ Zo < 0.5 kΩ
19
-
-
ns
0.5 kΩ Zo < 1 kΩ
30
-
-
ns
1 kΩ Zo < 5 kΩ
48
-
-
ns
9
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
10
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
11
-
-
ns
0.2 kΩ Zo < 0.5 kΩ
13
-
-
ns
0.5 kΩ Zo < 1 kΩ
22
-
-
ns
1 kΩ Zo < 5 kΩ
36
-
-
ns
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 8 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 6 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit
ts
LPC51U68
Product data sheet
sampling time
Zo < 0.05 kΩ
[3]
43
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
46
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
50
-
-
ns
0.2 kΩ Zo < 0.5 kΩ
56
-
-
ns
0.5 kΩ Zo < 1 kΩ
74
-
-
ns
1 kΩ Zo < 5 kΩ
105
-
-
ns
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Table 37. ADC sampling times …continued[1]
Tamb = -40 °C to 85 °C; 1.62 V ≤ VDDA ≤ 3.6 V; 1.62 V ≤ VDD ≤ 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
35
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
38
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
40
-
-
ns
0.2 kΩ Zo < 0.5 kΩ
46
-
-
ns
0.5 kΩ Zo < 1 kΩ
61
-
-
ns
1 kΩ Zo < 5 kΩ
86
-
-
ns
27
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
29
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
32
-
-
ns
0.2 kΩ Zo < 0.5 kΩ
36
-
-
ns
0.5 kΩ Zo < 1 kΩ
48
-
-
ns
1 kΩ Zo < 5 kΩ
69
-
-
ns
20
-
-
ns
0.05 kΩ Zo < 0.1 kΩ
22
-
-
ns
0.1 kΩ Zo < 0.2 kΩ
23
-
-
ns
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
0.2 kΩ Zo < 0.5 kΩ
26
-
-
ns
0.5 kΩ Zo < 1 kΩ
36
-
-
ns
1 kΩ Zo < 5 kΩ
51
-
-
ns
[1]
Characterized through simulation. Not tested in production.
[2]
The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output
impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum
sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.
[3]
Zo = analog source output impedance.
12.2.1 ADC input impedance
Figure 26 shows the ADC input impedance. In this figure:
•
•
•
•
ADCx represents slow ADC input channels 6 to 11.
ADCy represents fast ADC input channels 0 to 5.
R1 and Rsw are the switch-on resistance on the ADC input channel.
If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through
Rsw to the sampling capacitor (Cia).
• If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through
R1 + Rsw to the sampling capacitor (Cia).
• Typical values, R1 = 487 , Rsw = 278
• See Table 20 for Cio.
• See Table 36 for Cia.
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ADC
R1
ADCx
Cia
Cio
Rsw
ADCy
DAC
Cio
aaa-017600
Fig 26. ADC input impedance
12.3 Temperature sensor
Table 38. Temperature sensor static and dynamic characteristics
VDD = VDDA = 1.62 V to 3.6 V
Symbol
Parameter
Conditions
DTsen
sensor
temperature
accuracy
Tamb = 40 C to +105 C
EL
linearity error
Tamb = 40 C to +105 C
ts(pu)
LPC51U68
Product data sheet
power-up
settling time
to 99% of temperature
sensor output value
[1]
Absolute temperature accuracy.
[2]
Based on simulation.
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Rev. 1.5 — 13 January 2020
[1]
[2]
Min
Typ
Max
Unit
-
-
3
C
-
-
3
C
-
10
15
s
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Table 39. Temperature sensor Linear-Least-Square (LLS) fit parameters
VDD = VDDA = 1.62 V to 3.6 V
Fit parameter
Range
Min
Typ
Tamb = 40 C to +105 C
[1]
LLS slope
LLS intercept at 0 C
-
-2.0
-
mV/C
Tamb = 40 C to +105 C
[1]
-
590.0
-
mV
[2]
521.0
-
540.0
mV
Value at 30 C
[1]
Measured over typical samples.
[2]
Measured for samples over process corners.
Max
Unit
aaa-024009
800
Vo
(mV)
LLS fit
600
400
200
0
-40
-10
20
50
80
Temperature (° C)
110
VDD = VDDA 3.3 V; measured on matrix samples.
Fig 27. LLS fit of the temperature sensor output voltage
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13. Application information
13.1 Start-up behavior
Figure 30 shows the start-up timing after reset. The FRO 12 MHz oscillator provides the
default clock at Reset and provides a clean system clock shortly after the supply pins
reach operating voltage.
FRO
starts
FRO status
internal reset
VDD
valid threshold
= 1.62 V
ta μs
tb μs
GND
boot time
supply ramp-up
time
user code
tc μs
processor status
boot code
execution
finishes;
user code starts
aaa-023995
Fig 28. Start-up timing
Table 40.
Typical start-up timing parameters
Parameter
Description
Value
ta
FRO start time
20 s
tb
Internal reset de-asserted
151 s
tc
Legacy image
931 s
Single image without CRC
904
Dual image without CRC
952
13.2 Standard I/O pin configuration
Figure 29 shows the possible pin modes for standard I/O pins:
• Digital output driver: enabled/disabled.
• Digital input: Pull-up enabled/disabled.
• Digital input: Pull-down enabled/disabled.
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• Digital input: Repeater mode enabled/disabled.
• Z mode; High impedance (no cross-bar currents for floating inputs).
The default configuration for standard I/O pins is Z mode. The weak MOS devices provide
a drive capability equivalent to pull-up and pull-down resistors.
VDD
open-drain enable
strong
pull-up
output enable
pin configured
as digital output
VDD
ESD
data output
PIN
strong
pull-down
ESD
VDD
weak
pull-up
pull-up enable
weak
pull-down
repeater
mode enable
pin configured
as digital input
pull-down enable
digital
input
glitch filter
enable
input invert
pin configured
as analog input
enable
filter
enable
analog input
analog
input
aaa-017273
The glitch filter rejects pulses of typical 12 ns width.
Fig 29. Standard I/O and RESET pin configuration
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13.3 Connecting power, clocks, and debug functions
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3.3 V
SWD connector
3.3 V
(4)
(6)
~10 kΩ - 100 kΩ
1
SWDIO/PIO0_17
2
3.3 V
~10 kΩ - 100 kΩ
SWCLK/PIO0_16
3
4
5
6
n.c.
7
8
n.c.
9
10
(6)
n.c.
RTCXIN
RESETN
C4
RTCXOUT
DGND
(1)
C3
VSS
DGND
DGND
0.1 μF
AGND
(2)
VDD (2 to 4 pins)
VSSA
3.3 V
0.01 μF
LPC51U68
DGND
PIO0_4
(3)
VDDA
ISP select pins
3.3 V
PIO0_31
10 μF
0.1 μF
PIO1_6
ADCx
(5)
DGND
(3)
VREFP
0.1 μF
3.3 V
10 μF
0.1 μF
VREFN
AGND
AGND
DGND
AGND
aaa-028919
(1) See Section 13.5 “RTC oscillator” for the values of C3 and C4.
(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the VDD pin. Add one set of decoupling
capacitors to each VDD pin.
(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and VDDA pins. The 10 μF bypass capacitor
filters the power line. Tie VDDA and VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used.
(4) Uses the ARM 10-pin interface for SWD.
(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see
Ref. 1.
(6) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by
default.
Fig 30. Power, clock, and debug connections
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13.4 I/O power consumption
I/O pins can contribute to the overall static and dynamic power consumption of the part.
If pins are configured as digital inputs with the pull-up resistor enabled, a static current can
flow depending on the voltage level at the pin. This current can be obtained using the
parameters Ipu and Ipd given in Table 20.
If pins are configured as digital outputs, the static current is obtained from parameters IOH
and IOL shown in Table 20, and any external load connected to the pin.
When an I/O pin switches in an application, it contributes to the dynamic power
consumption because the VDD supply provides the current to charge and discharge all
internal and external capacitive loads connected to the pin.
The contribution from the I/O switching current Isw can be calculated as follows for any
given switching frequency fsw if the external capacitive load (Cext) is known (see Table 20
for the internal I/O capacitance):
Isw = VDD x fsw x (Cio + Cext)
13.5 RTC oscillator
In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2
need to be connected externally on RTCXIN and RTCXOUT. See Figure 31.
LPC51U68
L
RTCXIN
RTCXOUT
=
CL
CP
XTAL
RS
CX1
CX2
aaa-018147
Fig 31. RTC oscillator components
For best results, it is very critical to select a matching crystal for the on-chip oscillator.
Load capacitance (CL), series resistance (RS), and drive level (DL) are important
parameters to consider while choosing the crystal. After selecting the proper crystal, the
external load capacitor CX1 and CX2 values can also be generally determined by the
following expression:
CX1 = CX2 = 2CL (CPad + CParasitic)
Where:
CL - Crystal load capacitance
CPad - Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF).
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CParasitic – Parasitic or stray capacitance of external circuit.
Although CParasitic can be ignored in general, the actual board layout and placement of
external components influences the optimal values of external load capacitors. Therefore,
it is recommended to fine tune the values of external load capacitors on actual hardware
board to get the accurate clock frequency. For fine tuning, output the RTC Clock to one of
the GPIOs and optimize the values of external load capacitors for minimum frequency
deviation.
13.5.1 RTC Printed Circuit Board (PCB) design guidelines
• Connect the crystal and external load capacitors on the PCB as close as possible to
the oscillator input and output pins of the chip.
• The length of traces in the oscillation circuit should be as short as possible and must
not cross other signal lines.
• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal
usage, have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through
the PCB and to keep the parasitics as small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.
13.6 Suggested USB interface solutions
The USB device can be connected to the USB as self-powered device (see Figure 32) or
bus-powered device (see Figure 33).
On the LPC51U68, the USB_VBUS pin is 5 V tolerant only when VDD is applied and at
operating voltage level. Therefore, if the USB_VBUS function is connected to the USB
connector and the device is self-powered, the USB_VBUS pin must be protected for
situations when VDD = 0 V.
If VDD is always at operating level while VBUS = 5 V, the USB_VBUS pin can be
connected directly to the VBUS pin on the USB connector.
For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin,
precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum
allowable voltage on the USB_VBUS pin in this case.
One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the
USB connector. The voltage divider ratio should be such that the USB_VBUS pin is
greater than 0.7 VDD to indicate a logic HIGH while below the 3.6 V allowable maximum
voltage.
For the following operating conditions
VBUSmax = 5.25 V
VDD = 3.6 V,
the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.
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LPCxxxx
VDD
R2
R3
USB
R1
1.5 kΩ
USB_VBUS
USB_DP
RS = 33 Ω
USB_DM
RS = 33 Ω
D+
D-
USB-B
connector
VSS
aaa-023996
Fig 32. USB interface on a self-powered device where USB_VBUS = 5 V
The internal pull-up (1.5 k) can be enabled by setting the DCON bit in the
DEVCMDSTAT register to prevent the USB from timing out when there is a significant
delay between power-up and handling USB traffic. External circuitry is not required.
LPCxxxx
VDD
USB
R1
1.5 kΩ
REGULATOR
USB_VBUS(1)
USB_VBUS(2)
USB_DP
RS = 33 Ω
USB_DM
RS = 33 Ω
VBUS
D+
D-
USB-B
connector
VSS
aaa-023997
Two options exist for connecting VBUS to the USB_VBUS pin:
(1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered.
(2) Connect the VBUS signal directly from the connector to the USB_VBUS pin. In this case, 5 V are applied to the USB_VBUS pin
while the regulator is ramping up to supply VDD. Since the USB_VBUS pin is only 5 V tolerant when VDD is at operating level,
this connection can degrade the performance of the part over its lifetime. Simulation shows that lifetime is reduced to 15 years
at Tamb = 45 °C and 8 years at Tamb = 55 °C assuming that USB_VBUS = 5 V is applied continuously while VDD = 0 V.
Fig 33. USB interface on a bus-powered device
Remark: When a self-powered circuit is used without connecting VBUS, configure the
USB_VBUS pin for GPIO (PIO1_6 or PIO1_11) and provide software that can detect the
host presence through some other mechanism before enabling USB_CONNECT and the
SoftConnect feature. Enabling the SoftConnect without host presence leads to USB
compliance failure.
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14. Package outline
LQFP48: plastic low pro le quad at package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
37
A
24
ZE
e
E HE
A A2
(A3 )
A1
w M
bp
pin 1 index
Lp
L
13
48
1
detail X
12
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
0.95
0.55
0.95
0.55
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 34. LQFP48 Package outline
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LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
1.45
1.05
1.45
1.05
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT314-2
136E10
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 35. LQFP64 Package outline
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15. Soldering
Footprint information for re ow soldering of LQFP48 package
SOT313-2
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
0.500
0.560
Ax
Ay
Bx
10.350 10.350 7.350
By
C
D1
D2
Gx
Gy
7.350
1.500
0.280
0.500
7.500
7.500
Hx
Hy
10.650 10.650
sot313-2_fr
Fig 36. LQFP48 Soldering footprint
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Footprint information for re ow soldering of LQFP64 package
SOT314-2
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
0.500
P2
Ax
Ay
Bx
By
C
0.560 13.300 13.300 10.300 10.300 1.500
D1
D2
0.280
0.400
Gx
Gy
Hx
Hy
10.500 10.500 13.550 13.550
sot314-2_fr
Fig 37. LQFP64 Soldering footprint
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16. Abbreviations
Table 41.
Abbreviations
Acronym
Description
AHB
Advanced High-performance Bus
APB
Advanced Peripheral Bus
API
Application Programming Interface
CDC
Communication Device Class
DMA
Direct Memory Access
FRO oscillator
Internal Free-Running Oscillator, tuned to the factory specified frequency
GPIO
General Purpose Input/Output
FRO
Free Running Oscillator
HID
Human Interface Device
LSB
Least Significant Bit
MCU
MicroController Unit
MSC
Mass Storage Device
PLL
Phase-Locked Loop
SPI
Serial Peripheral Interface
TCP/IP
Transmission Control Protocol/Internet Protocol
TTL
Transistor-Transistor Logic
USART
Universal Asynchronous Receiver/Transmitter
17. References
[1]
LPC51U68
Product data sheet
Technical note ADC design guidelines:
https://www.nxp.com/docs/en/supporting-information/TN00009.pdf
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18. Revision history
Table 42.
Revision history
Document ID
Release date Data sheet status
LPC51U68 v.1.5
20200113
•
LPC51U68 v.1.4
LPC51U68 v.1.3
LPC51U68 v.1.2
LPC51U68
Product data sheet
Product data sheet
LPC51U68 v.1.3
Product data sheet
-
LPC51U68 v.1.2
•
Updated Section 2 “Features and benefits”. Added text: USB 2.0 full-speed host/device
controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in
device mode using software library. See Technical note TN00035 for more details.
•
Updated VREFP, VREFN, VDDA text in Table 4 “Pin description”.
20180313
Product data sheet
-
LPC51U68 v.1.1
Updated Section 1 “General description”. Removed text.
20180309
•
•
LPC51U68 v.1.0
LPC51U68 v.1.4
Maximum CPU frequency changed from 100 MHz to 150 MHz.
20180517
•
LPC51U68 v.1.1
Product data sheet
Updated for rise and fall times for I/O pins configured as input only.
20190814
•
Change notice Supersedes
Product data sheet
-
LPC51U68 v.1.0
Updated Table 11 “Thermal resistance”.
Updated top-side markings of LQFP48 and LQFP64 packages. See Section 4 “Marking”.
20171213
Product data sheet
-
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-
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
LPC51U68
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1.5 — 13 January 2020
© NXP Semiconductors N.V. 2020. All rights reserved.
92 of 95
LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
continued >>
LPC51U68
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.5 — 13 January 2020
© NXP Semiconductors N.V. 2020. All rights reserved.
93 of 95
LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
21. Contents
1
2
3
3.1
4
5
6
6.1
6.2
6.2.1
6.2.2
7
7.1
7.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
Termination of unused pins. . . . . . . . . . . . . . . 19
Pin states in different power modes . . . . . . . . 20
Functional description . . . . . . . . . . . . . . . . . . 20
ARM Cortex-M0+ co-processor . . . . . . . . . . . 20
Nested Vectored Interrupt Controller (NVIC) for
Cortex-M0+. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 20
7.3
System Tick timer (SysTick) . . . . . . . . . . . . . . 20
7.4
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 20
7.5
On-chip flash. . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.6
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.7
Memory mapping . . . . . . . . . . . . . . . . . . . . . . 21
7.8
System control . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8.1
Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8.1.1
FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8.1.2
Watchdog oscillator (WDTOSC) . . . . . . . . . . . 23
7.8.1.3
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8.1.4
RTC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8.1.5
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8.2
Clock Generation . . . . . . . . . . . . . . . . . . . . . . 24
7.8.3
Brownout detection . . . . . . . . . . . . . . . . . . . . . 26
7.8.4
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.9
Code security (Code Read Protection - CRP) 26
7.10
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.10.1
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.10.2
Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 27
7.10.3
Deep power-down mode. . . . . . . . . . . . . . . . . 27
7.11
General Purpose I/O (GPIO) . . . . . . . . . . . . . 30
7.11.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.12
Pin interrupt/pattern engine . . . . . . . . . . . . . . 30
7.12.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.13
AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 31
7.13.1
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 31
7.13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.14
Digital serial peripherals . . . . . . . . . . . . . . . . . 32
7.14.1
USB 2.0 device controller . . . . . . . . . . . . . . . . 32
7.14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.14.2
Flexcomm Interface serial communication. . .
7.14.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.3
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.4
SPI serial I/O controller . . . . . . . . . . . . . . . . .
7.14.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.5
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . .
7.14.6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.7
I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . .
7.14.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15
Standard counter/timers (CTimer 0, 1, 3). . . .
7.15.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.2
SCTimer/PWM subsystem . . . . . . . . . . . . . . .
7.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.3
Windowed WatchDog Timer (WWDT) . . . . . .
7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.4
RTC timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.5
Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . .
7.15.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.6
Micro-tick timer (UTICK). . . . . . . . . . . . . . . . .
7.15.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16
12-bit Analog-to-Digital Converter (ADC) . . . .
7.16.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17
Temperature sensor . . . . . . . . . . . . . . . . . . . .
7.18
Emulation and debugging . . . . . . . . . . . . . . .
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
9
Thermal characteristics . . . . . . . . . . . . . . . . .
10
Static characteristics . . . . . . . . . . . . . . . . . . .
10.1
General operating conditions . . . . . . . . . . . . .
10.2
CoreMark data . . . . . . . . . . . . . . . . . . . . . . . .
10.3
Power consumption . . . . . . . . . . . . . . . . . . . .
10.4
Pin characteristics . . . . . . . . . . . . . . . . . . . . .
10.4.1
Electrical pin characteristics. . . . . . . . . . . . . .
11
Dynamic characteristics . . . . . . . . . . . . . . . . .
11.1
Flash memory . . . . . . . . . . . . . . . . . . . . . . . .
11.2
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3
Wake-up process . . . . . . . . . . . . . . . . . . . . . .
11.4
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5
FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6
RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . .
11.7
Watchdog oscillator . . . . . . . . . . . . . . . . . . . .
11.8
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.9
I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . .
11.10
SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . .
11.11
USART interface . . . . . . . . . . . . . . . . . . . . . .
11.12
SCTimer/PWM output timing . . . . . . . . . . . . .
32
32
32
32
33
33
33
33
34
34
35
35
36
36
37
37
38
38
38
38
39
39
39
39
39
40
41
42
43
43
44
45
50
53
56
56
56
57
57
58
58
59
59
60
64
67
68
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors B.V. 2020.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 January 2020
Document identifier: LPC51U68
LPC51U68
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
11.13
USB interface characteristics . . . . . . . . . . . . . 69
12
Analog characteristics . . . . . . . . . . . . . . . . . . 70
12.1
BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.2
12-bit ADC characteristics . . . . . . . . . . . . . . . 71
12.2.1
ADC input impedance. . . . . . . . . . . . . . . . . . . 74
12.3
Temperature sensor . . . . . . . . . . . . . . . . . . . . 75
13
Application information. . . . . . . . . . . . . . . . . . 77
13.1
Start-up behavior . . . . . . . . . . . . . . . . . . . . . . 77
13.2
Standard I/O pin configuration . . . . . . . . . . . . 77
13.3
Connecting power, clocks, and debug
functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
13.4
I/O power consumption. . . . . . . . . . . . . . . . . . 81
13.5
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.5.1
RTC Printed Circuit Board (PCB) design guidelines 82
13.6
Suggested USB interface solutions . . . . . . . . 82
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 84
15
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 88
17
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 89
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 90
19.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 90
19.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.4
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 91
20
Contact information. . . . . . . . . . . . . . . . . . . . . 91
21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LPC51U68
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.5 — 13 January 2020
© NXP Semiconductors N.V. 2020. All rights reserved.
95 of 95
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