LPC802
32-bit ARM Cortex-M0+ microcontroller; up to 16 KB flash and
2 KB SRAM; 12-bit ADC; Comparator;
Rev. 1.8 — 25 September 2019
Product data sheet
1. General description
The LPC802 is an ARM Cortex-M0+ based, low-cost 32-bit MCU family of processors
operating at CPU frequencies of up to 15 MHz. The LPC802 supports 16 KB of flash
memory and 2 KB of SRAM.
The peripheral complement of the LPC802 includes one I2C-bus interface, up to two
USARTs, one SPI interface, one multi-rate timer, self-wake-up timer, one general purpose
32-bit counter/timer, one 12-bit ADC, one analog comparator, function-configurable I/O
ports through a switch matrix, and up to 17 general-purpose I/O pins.
For additional documentation related to the LPC802 parts, see Section 19 “References”.
2. Features and benefits
System:
ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to
15 MHz with single-cycle multiplier and fast single-cycle I/O port.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
AHB multilayer matrix.
Serial Wire Debug (SWD) with four break points and two watch points. JTAG
boundary scan (BSDL) supported.
Memory:
16 KB on-chip EEPROM based flash programming memory.
Code Read Protection (CRP).
2 KB SRAM.
Dual I/O power (LPC802M011JDH20):
Independent supplies on each package side permitting level-shifting signals from
one off-chip voltage domain to another and/or interfacing directly to off-chip
peripherals operating at different supply levels.
The switch matrix provides level shifter functionality to allow up to two selected
signals to be routed from user-selected pins in one voltage domain to selected pins
in the alternate domain. This feature can also be used on a single supply device if
voltage level shifting is not required.
ROM API support:
Boot loader.
Supports Flash In-Application Programming (IAP).
Supports In-System Programming (ISP) through USART.
LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
LPC802
Product data sheet
On-chip ROM APIs for integer divide.
Free Running Oscillator (FRO) API.
Digital peripherals:
High-speed GPIO interface connected to the ARM Cortex-M0+ I/O bus with up to
17 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, and input inverter. GPIO direction control
supports independent set/clear/toggle of individual bits.
High-current source output driver (20 mA) on three pins.
Switch matrix for flexible configuration of each I/O pin function.
CRC engine.
Timers:
One 32-bit general purpose counter/timer, with four match outputs and three
capture inputs. Supports PWM mode, and external count.
Two channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four
programmable, fixed rates.
Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a
low-power, low-frequency internal oscillator, or an external clock input.
Windowed Watchdog timer (WWDT).
Analog peripherals:
One 12-bit ADC with up to 12 input channels with multiple internal and external
trigger inputs and with sample rates of up to 480 Ksamples/s. The ADC supports
two independent conversion sequences.
Comparator with four input pins and external or internal reference voltage.
Serial peripherals:
Two USART interfaces with pin functions assigned through the switch matrix and
one fractional baud rate generators.
One SPI controller with pin functions assigned through the switch matrix.
One I2C-bus interface. Supports Standard mode and Fast mode.
Clock generation:
Free Running Oscillator (FRO). This oscillator provides selectable
9 MHz, 12 MHz and 15 MHz outputs that can be used as a system clock. The FRO
is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C
to 70 C.
1 MHz low power oscillator can be used as a clock source.
Clock output function with divider that can reflect all internal clock sources.
Power control:
Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and
deep power-down mode.
Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and
I2C peripherals.
Wake-up from deep power-down mode on multiple pins.
Timer-controlled self wake-up from sleep, deep-sleep, and power-down modes.
Power-On Reset (POR).
Brownout detect (BOD).
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Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
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LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Unique device serial number for identification.
Single or dual power supplies (1.71 V to 3.6 V).
Operating temperature range -40 °C to +105 °C.
Available in WLCSP16, TSSOP16, TSSOP20, and HVQFN33 packages.
3. Applications
Sensor gateways
Industrial
Gaming controllers
8/16-bit applications
Consumer
Climate control
Simple motor control
Portables and wearables
Lighting
Motor control
Fire and security applications
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC802M001JDH16
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
LPC802M001JDH20
TSSOP20
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
LPC802M011JDH20
TSSOP20
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
LPC802M001JHI33
HVQFN33
HVQFN: plastic thermal enhanced very thin quad flat package; no leads; n/a
33 terminals; body 5 5 0.85 mm
LPC802UK
WLCSP16
wafer level chip-size package; 16 (4 4) bumps; 1.86 1.86 0.3 mm
SOT1393-2
4.1 Ordering options
Table 2.
Ordering options
Flash/KB
SRAM/
KB
USART
I2C
SPI
GPIO
Dual I/O power supply
Package
Type number
LPC802M001JDH16
16
2
2
1
1
13
-
TSSOP16
LPC802M001JDH20
16
2
2
1
1
17
-
TSSOP20
LPC802M011JDH20
16
2
2
1
1
16
yes
TSSOP20
LPC802M001JHI33
16
2
2
1
1
17
-
HVQFN33
LPC802UK
16
2
2
1
1
13
-
WLCSP16
LPC802
Product data sheet
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LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
5. Marking
20
Terminal 1 index area
NXP
NXP
Terminal 1 index area
1
aaa-014766
Fig 1.
TSSOP20 and TSSOP16 package markings
aaa-014382
Fig 2.
HVQFN33 package marking
Terminal 1
index area
aaa-015675
Fig 3.
WLCSP16 package marking
The LPC802 HVQFN33 packages have the following top-side marking:
• First line: LPC802M0
• Second line: xxxx
• Third line: yywwx[R]
– yyww: Date code with yy = year and ww = week.
– xR = Boot code version and device revision.
The LPC802 TSSOP20 packages typically have the following top-side marking:
• First line: LPC802
• Second line: M0y1
– y: 0 or 1
• Third line: xxxx
• Fourth line: xxywwx[R]
– yww: Date code with y = year and ww = week.
– xR = Boot code version and device revision.
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
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LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
The LPC802 TSSOP16
•
•
•
•
packages have the following top-side marking:
First line: LPC802
Second line: M001J
Third line: xxxx
Fourth line: ywwx[R]
– yww: Date code with y = year and ww = week.
– xR = Boot code version and device revision.
The LPC802 WLCSP16 packages have the following top-side marking:
• First line: LPC802
• Second line: xxxxx
• Third line: xyywwx[R]
– yyww: Date code with ww = week and yy = year.
– xR = Boot code version and device revision.
• Fourth line: xxx - yyy
Table 3.
Device revision table
Revision identifier (R)
Revision description
0A
Initial device revision with Boot ROM version 13.0
1A
Second device revision with Boot ROM version 13.1
1B
Third device revision with Boot ROM version 13.1
1C (TSSOP16 only)
Fourth device revision with Boot ROM version 13.1
1D
Fifth device revision with Boot ROM version 13.1
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
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LPC802
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32-bit ARM Cortex-M0+ microcontroller
6. Block diagram
CLKIN
ISP Access Port
RESET
DEBUG
INTERFACE
GPIOs
GPIOs AND
GPOINT
IOP bus
ARM
Cortex M0+
Clock Generation,
Power Control,
and other
System Functions
CLKOUT
Voltage Regulator
Vdd
M0
P0
Flash
interface
Flash
16 kB
Boot ROM
8 kB
P1
Multilayer
AHB Matrix
SRAM
2 kB
P2
AHB to
APB bridge
APB slave group
System control
UART 0 and 1
IOCON Registers
SPI0
SPI0
CTIMER0
I2C 0
I2C0
T0 Match/
Capture
UART0,1
Periph Input Mux Selects
COMP
Inputs
Comparator
PMU Registers
ADC inputs
and Triggers
12-bit ADC
GPIOs
Switch Matrix
Wakeup Timer
Multi-Rate Timer
LPOSc
Windowed WDT
aaa-028309
Fig 4.
LPC802 block diagram
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
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LPC802
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32-bit ARM Cortex-M0+ microcontroller
7. Pinning information
7.1 Pinning
PIO0_16/ADC_3/ACMP_I4
1
20 PIO0_14/ADC_2/ACMP_I3
PIO0_17/ADC_9
2
19 PIO0_0/ACMP_I1/TDO
PIO0_13/ADC_10
3
18 VREFP
PIO0_12
4
17 PIO0_7/ADC_1/ACMPVREF
RESET/PIO0_5
5
PIO0_4/ADC_11/TRST
6
16 VSS
15 VDD
SWCLK/PIO0_3/TCK
7
14 PIO0_8/ADC_5
SWDIO/PIO0_2/TMS
8
13 PIO0_9/ADC_4
PIO0_11/ADC_6/WKTCLKIN
9
12 PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI
TSSOP20
PIO0_10/ADC_7 10
11 PIO0_15/ADC_8
aaa-026614
Fig 5.
Pin configuration TSSOP20 - 1 package (LPC802M001JDH20 - single supply device)
PIO0_16/ADC_3/ACMP_I4
1
20 PIO0_14/ADC_2/ACMP_I3
VDDIO
2
19 PIO0_0/ACMP_I1/TDO
PIO0_13/ADC_10
3
18 VREFP
PIO0_12
4
17 PIO0_7/ADC_1/ACMPVREF
RESET/PIO0_5
5
PIO0_4/ADC_11/TRST
6
16 VSS
15 VDD
SWCLK/PIO0_3/TCK
7
14 PIO0_8/ADC_5
SWDIO/PIO0_2/TMS
8
13 PIO0_9/ADC_4
PIO0_11/ADC_6/WKTCLKIN
9
12 PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI
TSSOP20
PIO0_10/ADC_7 10
11 PIO0_15/ADC_8
aaa-026615
Fig 6.
Pin configuration TSSOP20 - 2 package with VDDIO (LPC802M011JDH20 - dual supply device)
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
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LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
PIO0_17/ADC_9
1
16 PIO0_0/ACMP_I1/TDO
PIO0_13/ADC10
2
15 VREFP
PIO0_12
3
14 PIO0_7/ADC_1/ACMPVREF
RESET/PIO0_5
4
13 VSS
TSSOP16
PIO0_4/ADC_11/nTRST 5
12 VDD
6
11 PIO0_8/ADC_5
PIO0_2/SWDIO/TMS 7
10 PIO0_9/ADC_4
PIO0_3/SWCLK/TCK
PIO0_11/ADC_6/WKTCLKIN
9
8
PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI
aaa-026619
PIO0_16/ADC_3/ACMP_I4
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
PIO0_14/ADC_2/ACMP_I3
31
30
29
28
27
26
25
terminal 1
index area
32
Pin configuration TSSOP16 package
PIO0_17/ADC_9
1
24
PIO0_13/ADC_10
2
23
VREFP
PIO0_12
3
22
PIO0_7/ADC_1/ACMPVREF
PIO0_0/ACMP_I1/TDO
RESET/PIO0_5
4
21
n.c.
PIO0_4/ADC_11/TRSTN
5
20
VDD
SWCLK/PIO0_3/TCK
6
19
PIO0_8/ADC_5
SWDIO/PIO0_2/TMS
7
18
PIO0_9/ADC_4
PIO0_11/ADC_6/WKTCLKIN
8
17
PIO0_1/ADC_0/ACMP_I2/TDI/CLKIN
9
10
11
12
13
14
15
16
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
PIO0_15/ADC_8
33 VSS
PIO0_10/ADC_7
Fig 7.
aaa-026616
Transparent top view
Fig 8.
Pin configuration HVQFN33 package
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
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LPC802
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32-bit ARM Cortex-M0+ microcontroller
7.2 Pin description
Table 4 shows the pin functions that are fixed to specific pins on each package. These
fixed-pin functions are selectable through the switch matrix between GPIO and the
comparator, ADC, SWD, and RESET pins. By default, the GPIO function is selected
except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary
scan mode only.
Movable functions for the I2C, USART, SPI, CTimer pins and other peripherals can be
assigned through the switch matrix to any pin that is not power or ground in place of the
pin’s fixed functions.
The following exceptions apply:
Do not assign more than one output to any pin. However, an output and/or one or more
inputs can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO
functionality is disabled.
Eight GPIO pins trigger a wake-up from deep power-down mode. If the part must wake up
from deep power-down mode via an external pin, do not assign any movable function to
this pin. The GPIO pins should be pulled HIGH externally before entering deep
power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit deep
power-down mode and wakes up the part.
The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to
PIO0_4 by hardware when the part is in boundary scan mode.
PIO0_2, PIO0_3, and PIO0_12 are the high drive output pins. PIO0_4, PIO0_8, PIO0_9,
PIO0_10, PIO0_11, PIO0_13, PIO0_15, and PIO0_17 are the WAKEUP pins.
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
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LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
Symbol
TSSOP20-2
TSSOP16
HVQFN33
WLCSP16
Pin description
TSSOP20-1
Table 4.
PIO0_0/
ACMP_I1/TDO
19
19
16
24
D3
[2]
Reset Type
state[1]
Description
I; PU
PIO0_0 — General-purpose port 0
input/output 0.
IO
In ISP mode, this is the U0_RXD pin (for single
supply devices).
In boundary scan mode: TDO (Test Data Out).
PIO0_1/ADC_0/
ACMP_I2/CLKIN/TDI/
12
12
9
17
A4
[2]
I; PU
A
ACMP_I1 — Analog comparator input 1.
IO
PIO0_1 — General-purpose port 0
input/output 1.
In boundary scan mode: TDI (Test Data In).
SWDIO/PIO0_2/
TMS
SWCLK/PIO0_3/
TCK
8
7
8
7
7
6
7
6
A2
B1
[3]
[3]
I; PU
I; PU
A
ACMP_I2 — Analog comparator input 2.
I
CLKIN — External clock input.
IO
SWDIO — Serial Wire Debug I/O. SWDIO is
enabled by default on this pin. In boundary
scan mode: TMS (Test Mode Select).
I/O
PIO0_2 — General-purpose port 0
input/output 2.
I
SWCLK — Serial Wire Clock. SWCLK is
enabled by default on this pin.
In boundary scan mode: TCK (Test Clock).
PIO0_4/ADC_11/
TRSTN
6
6
5
5
B2
[2]
I; PU
IO
PIO0_3 — General-purpose port 0
input/output 3.
IO
PIO0_4 — General-purpose port 0
input/output 4.
In ISP mode, this pin is the U0_TXD pin (for
single supply devices).
In boundary scan mode: TRST (Test Reset).
RESET/PIO0_5
5
5
4
4
C2
[4][5]
I; PU
A
ADC_11 — ADC input 11.
IO
RESET — External reset input: A LOW-going
pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to
take on their default states, and processor
execution to begin at address 0.
The RESET pin can be left unconnected or be
used as a GPIO or for any movable function if
an external RESET function is not needed.
PIO0_7/ADC_1/
ACMPVREF
17
17
14
22
C3
[2]
I; PU
I
PIO0_5 — General-purpose port 0
input/output 5.
IO
PIO0_7 — General-purpose port 0
input/output 7.
A
ADC_1 — ADC input 1.
ACMPVREF — Alternate reference voltage for
the analog comparator.
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
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LPC802
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32-bit ARM Cortex-M0+ microcontroller
Symbol
TSSOP20-2
TSSOP16
HVQFN33
WLCSP16
Pin description
TSSOP20-1
Table 4.
PIO0_8/ADC_5
14
14
11
19
B3
PIO0_9/ADC_4
PIO0_10/ADC_7
PIO0_11/ADC_6/
WKTCLKIN
13
10
9
13
10
9
10
-
18
9
8
8
A3
[2]
[2]
-
[2]
A1
[6]
Reset Type
state[1]
Description
I; PU
IO
PIO0_8 — General-purpose port 0
input/output 8. In ISP mode, this is the
U0_RXD pin (for dual supply devices).
A
ADC_5 — ADC input 5.
IO
PIO0_9 — General-purpose port 0
input/output 9. In ISP mode, this is the
U0_TXD pin (for dual supply devices)
A
ADC_4 — ADC input 4.
IO
PIO0_10 — General-purpose port 0
input/output 10.
A
ADC_7 — ADC input 7.
IO
PIO0_11 — General-purpose port 0
input/output 11.
A
ADC_6 — ADC input 6.
I
WKTCKLKIN — This pin can host an external
clock for the self-wake-up timer. To use the pin
as a self-wake-up timer clock input, select the
external clock in the wake-up timer CTRL
register. The external clock input is active in
sleep, deep-sleep, and power-down modes.
I; PU
I; PU
I; PU
PIO0_12
4
4
3
3
C1
[3]
I; PU
IO
PIO0_12 — General-purpose port 0
input/output 12. ISP entry pin. A LOW level on
this pin during reset starts the ISP command
handler.
PIO0_13/ADC_10
3
3
2
2
D2
[2]
I; PU
IO
PIO0_13 — General-purpose port 0
input/output 13.
A
ADC_10 — ADC input 10.
-
[2]
IO
PIO0_14 — General-purpose port 0
input/output 14.
A
ACMP_I3 — Analog comparator common
input 3.
A
ADC_2 — ADC input 2.
IO
PIO0_15 — General-purpose port 0
input/output 15.
PIO0_14/
ACMP_I3/ADC_2
PIO0_15/ADC8
20
11
20
11
-
25
-
16
-
[2]
-
[2]
I; PU
I; PU
ADC_8 — ADC input 8.
PIO0_16/
ACMP_I4/ADC_3
1
1
-
32
I; PU
IO
PIO0_16 — General-purpose port 0
input/output 16.
ACMP_I4 — Analog comparator common
input 4.
ADC_3 — ADC input 3.
PIO0_17/ADC_9
LPC802
Product data sheet
2
-
1
1
D1
[2]
I; PU
IO
PIO0_17 — General-purpose port 0
input/output 17.
A
ADC_9 — ADC input 9.
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Rev. 1.8 — 25 September 2019
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LPC802
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32-bit ARM Cortex-M0+ microcontroller
WLCSP16
TSSOP16
HVQFN33
Symbol
TSSOP20-2
Pin description
TSSOP20-1
Table 4.
Reset Type
state[1]
Description
VDD
15
15
12
20
B4
-
-
If VDDIO is present, VDD is the supply voltage
for the I/Os on the right side of the package
and the core voltage regulator. If VDDIO is not
present, VDD also supplies voltage to the I/Os
on the left side of the package.
VDDIO
-
2
-
-
-
-
-
If present, it is the supply voltage for the I/Os
on the left side of the package.
VSS
16
16
13
33[8]
VREFP
18
18
C4
-
15
23
D4
n.c.
-
-
-
10,
11,
12,
13,
14,
15,
21,
26,
27,
28,
29,
30,
31
-
-
-
Ground.
A
VREFP — ADC positive reference voltage.
Must be equal or lower than VDD.
-
no connect.
[1]
Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD
level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 15.5 “Pin states in
different power modes”. For termination on unused pins, see Section 15.4 “Termination of unused pins”.
[2]
5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When
configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
[4]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[5]
See Figure 16 for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is
not available in deep power-down mode. Use the WAKEUP pins to reset the chip and wake up from deep power-down mode.
[6]
The WKTCLKIN function is enabled in the PINENABLE0 register in the PMU. See the LPC802 user manual.
[7]
The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with
configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is
disabled.
[8]
Thermal pad for HVQFN33.
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
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LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
8. Movable functions
Movable functions for the I2C, USART, SPI, CTimer pins and other peripherals can be
assigned through the switch matrix to any pin that is not power or ground in place of the
fixed functions of the pin.
Table 5.
LPC802
Product data sheet
Movable functions (assign to pins PIO0_0 to PIO0_5, PIO0_7 to PIO0_17 through
switch matrix)
Function name
Type Description
Ux_TXD
O
Transmitter output for USART0 to USART1.
Ux_RXD
I
Receiver input for USART0 to USART1.
Ux_RTS
O
Request To Send output for USART0.
Ux_CTS
I
Clear To Send input for USART0.
Ux_SCLK
I/O
Serial clock input/output for USART0 to USART1 in synchronous mode.
SPIx_SCK
I/O
Serial clock for SPI0.
SPIx_MOSI
I/O
Master Out Slave In for SPI0.
SPIx_MISO
I/O
Master In Slave Out for SPI0.
SPIx_SSEL0
I/O
Slave select 0 for SPI0.
SPIx_SSEL1
I/O
Slave select 1 for SPI0.
I2Cx_SDA
I/O
I2C0 bus data input/output.
I2Cx_SCL
I/O
I2C0 bus clock input/output.
ACMP_O
O
Analog comparator output.
CLKOUT
O
Clock output.
GPIO_INT_BMAT O
Output of the pattern match engine.
T0_MAT0
O
Timer Match channel 0.
T0_MAT1
O
Timer Match channel 1.
T0_MAT2
O
Timer Match channel 2.
T0_MAT3
O
Timer Match channel 3.
T0_CAP0
I
Timer Capture channel 0.
T0_CAP1
I
Timer Capture channel 1.
T0_CAP2
I
Timer Capture channel 2.
LVLSHFT_IN0
I
Level shift input 0.
LVLSHFT_IN1
I
Level shift input 1.
LVLSHFT_OUT0
O
Level shift output 0.
LVLSHFT_OUT1
O
Level shift output 1.
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32-bit ARM Cortex-M0+ microcontroller
9. Functional description
9.1 ARM Cortex-M0+ core
The ARM Cortex-M0+ core runs at an operating frequency of up to 15 MHz using a
two-stage pipeline. The core revision is r0p1.
Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two
watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast
GPIO access.
The core includes a single-cycle multiplier and a system tick timer.
9.2 On-chip flash program memory
The LPC802 contain up to 16 KB of on-chip EEPROM based flash program memory.
9.3 On-chip SRAM
The LPC802 contain a total of 2 KB on-chip static RAM data memory.
9.4 On-chip ROM
The on-chip ROM contains the bootloader:
•
•
•
•
•
Boot loader.
Supports Flash In-Application Programming (IAP).
Supports In-System Programming (ISP) through USART.
On-chip ROM APIs for integer divide.
Free Running Oscillator (FRO) API.
9.5 Memory map
The LPC802 incorporates several distinct memory regions. Figure 9 shows the overall
map of the entire address space from the user program viewpoint following reset. The
interrupt vector area supports address remapping.
The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,
the system tick timer (SysTick), and the reduced power modes.
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Memory space
(reserved)
private peripheral bus
(reserved)
GPIO interrupts
GPIO
(reserved)
AHB perpherals
0xFFFF FFFF
0xE010 0000
0xA000 4000
0xA000 0000
0x5001 4000
APB perpherals
0x5000 0000
0x4008 0000
APB
peripherals
0x4000 0000
(reserved)
0x1000 0800
RAM
(reserved)
Boot ROM
(reserved)
0x5000 4000
0x5000 0000
CRC engine
0xA000 8000
AHB
peripherals
(reserved)
0x5001 4000
(reserved)
0xE000 0000
0x1000 0000
0x0F00 2000
0x0F00 0000
0x0000 4000
Flash memory
(up to 16 KB)
0x0000 0000
active interrupt vectors
0x0000 00C0
0x0000 0000
31-30
(reserved)
29
(reserved)
28
(reserved)
27
(reserved)
26
USART1
25
24
USART0
(reserved)
23
(reserved)
22
SPI
21
(reserved)
20
I2C
19
(reserved)
18
Syscon
17
16
IOCON
(reserved)
15
(reserved)
14
CTIMER 0
13
(reserved)
12
(reserved)
11
(reserved)
10
(reserved)
9
Analog Comparator
8
PMU
7
ADC
6
(reserved)
5
(reserved)
4
(reserved)
3
Switch Matrix
2
Wake-up Timer
1
Multi-Rate Timer
0
Watchdog timer
0x4007 FFFF
0x4007 8000
0x4007 4000
0x4007 0000
0x4006 C000
0x4006 8000
0x4006 4000
0x4006 0000
0x4005 C000
0x4005 8000
0x4005 4000
0x4005 0000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x4003 4000
0x4003 0000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
aaa-027121
Fig 9.
LPC802 Memory mapping
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32-bit ARM Cortex-M0+ microcontroller
9.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
9.6.1 Features
•
•
•
•
•
Nested Vectored Interrupt Controller is a part of the ARM Cortex-M0+.
Tightly coupled interrupt controller provides low interrupt latency.
Controls system exceptions and peripheral interrupts.
Supports 32 vectored interrupts.
In the LPC802, the NVIC supports vectored interrupts for each of the peripherals and
the eight pin interrupts.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the ARM exceptions SVCall and PendSV.
• Supports NMI.
9.6.2 Interrupt sources
Each peripheral device has at least one interrupt line connected to the NVIC but can have
several interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
9.7 System tick timer
The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to
generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).
9.8 I/O configuration
The IOCON block controls the configuration of the I/O pins. Each digital or mixed
digital/analog pin with the PIO0_n designator in Table 4 can be configured as follows:
• Enable or disable the weak internal pull-up and pull-down resistors.
• Select a pseudo open-drain mode. The input cannot be pulled up above VDD. The
pins are not 5 V tolerant when VDD is grounded.
• Program the input glitch filter with different filter constants using one of the IOCON
divided clock signals (IOCONCLKCDIV, see Figure 12 “LPC802 clock generation”).
You can also bypass the glitch filter.
• Invert the input signal.
• Hysteresis can be enabled or disabled.
• The switch matrix setting enables the analog input mode on pins with analog and
digital functions. Enabling the analog mode disconnects the digital functionality.
• The LPC802 uses a dual voltage I/O feature. The pins on one side of the package are
supplied by VDDIO and the pins on the other side are supplied by VDD. Each of these
two supplies can be connected to different voltages within the allowed Vdd range.
This feature allows the device to level-shift signals from one off-chip voltage domain
to another.
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• The switch matrix provides level shifter functionality to allow up to two selected
signals to be routed from user-selected pins in one voltage domain to selected pins in
the alternate domain. This feature can also be used on a single supply device if
voltage level shifting is not required.
Remark: The functionality of each I/O pin is flexible and is determined entirely through the
switch matrix. See Section 9.9 for details.
9.8.1 Standard I/O pad configuration
Figure 10 shows the possible pin modes for standard I/O pins with analog input function:
•
•
•
•
•
•
Digital output driver with configurable open-drain output.
Digital input: Weak pull-up resistor (PMOS device) enabled/disabled.
Digital input: Weak pull-down resistor (NMOS device) enabled/disabled.
Digital input: Repeater mode enabled/disabled.
Digital input: Programmable input digital filter selectable on all pins.
Analog input: Selected through the switch matrix.
VDD
VDD
open-drain enable
strong
pull-up
output enable
ESD
data output
PIN
strong
pull-down
pin configured
as digital output
driver
ESD
VSS
VDD
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pull-down enable
data input
pin configured
as digital input
select data
inverter
SWM PINENABLE for
analog input
analog input
transmission
gate
pin configured
as analog input
aaa-028401
Fig 10. Standard I/O pad configuration
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9.9 Switch Matrix (SWM)
The switch matrix controls the function of each digital or mixed analog/digital pin in a
highly flexible way by allowing to connect many functions like the USART, SPI, CTimer,
and I2C functions to any pin that is not power or ground. These functions are called
movable functions and are listed in Table 5.
Functions that need specialized pads can be enabled or disabled through the switch
matrix. These functions are called fixed-pin functions and cannot move to other pins. The
fixed-pin functions are listed in Section 7.2 “Pin description”. If a fixed-pin function is
disabled, any other movable function can be assigned to this pin.
9.10 Fast General-Purpose parallel I/O (GPIO)
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC802 use accelerated GPIO functions:
• GPIO registers are on the ARM Cortex-M0+ IO bus for fastest possible single-cycle
I/O timing, allowing GPIO toggling with rates of up to 7 MHz.
• An entire port value can be written in one instruction.
• Mask, set, and clear operations are supported for the entire port.
All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the
switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be
moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and
RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.
9.10.1 Features
• Bit level port registers allow a single instruction to set and clear any number of bits in
one write operation.
• Direction control of individual bits.
• All I/O default to GPIO inputs with internal pull-up resistors enabled after reset.
• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON block for each GPIO pin (see Figure 10).
• Direction (input/output) can be set and cleared individually.
• Pin direction bits can be toggled.
9.11 Pin interrupt
The pin interrupt block configures up to eight pins from all digital pins for providing eight
external interrupts connected to the NVIC.
Any digital pin, independently of the function selected through the switch matrix, can be
configured through the SYSCON block as input to the pin interrupt. The registers that
control the pin interrupt are on the IO+ bus for fast single-cycle access.
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9.11.1 Features
• Pin interrupts
– Up to eight pins can be selected from all digital pins as edge- or level-sensitive
interrupt requests. Each request creates a separate interrupt in the NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH- or LOW-active.
– Pin interrupts can wake up the LPC802 from sleep mode, deep-sleep mode, and
power-down mode.
9.12 USART0/1
All USART functions are movable functions and are assigned to pins through the switch
matrix.
9.12.1 Features
• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in
synchronous mode for USART functions connected to all digital pins.
• 7, 8, or 9 data bits and 1 or 2 stop bits.
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485
possible with software address detection and transceiver direction control.)
• Parity generation and checking: odd, even, or none.
• One transmit and one receive data buffer.
• RTS/CTS for hardware signaling for automatic flow control. Software flow control can
be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output.
•
•
•
•
•
•
Received data and status can optionally be read from a single register.
Break generation and detection.
Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
Built-in Baud Rate Generator.
A fractional rate divider is shared among all UARTs.
Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in
receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS
detect, and receiver sample noise detected.
• Separate data and flow control loopback modes for testing.
• Baud rate clock can also be output in asynchronous mode.
9.13 SPI0
All SPI functions are movable functions and are assigned to pins through the switch
matrix.
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9.13.1 Features
• Maximum data rates of up to 15 Mbit/s in master mode and up to 18 Mbit/s in slave
mode for SPI functions connected to all digital pins.
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data, which can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data, which allows very
versatile operation, including “any length” frames.
• One Slave Select input/output with selectable polarity and flexible usage.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
9.14 I2C-bus interface (I2C0)
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master.
9.14.1 Features
•
•
•
•
•
I2C0 supports standard and fast mode with data rates of up to 400 kbit/s.
Independent Master, Slave, and Monitor functions.
Supports both Multi-master and Multi-master with Slave functions.
Multiple I2C slave addresses supported in hardware.
One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
9.15 CTimer
9.15.1 General-purpose 32-bit timers/external event counter
The LPC802 has one general-purpose 32-bit timer/counter.
The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. The timer/counter also includes
three capture inputs to trap the timer value when an input signal transitions, optionally
generating an interrupt.
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9.15.1.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Up to three 32-bit captures can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt. The
number of capture inputs for each timer that are actually available on device pins can
vary by device.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
– Shadow registers are added for glitch-free PWM output.
• For each timer, up to 4 external outputs corresponding to match registers with the
following capabilities (the number of match outputs for each timer that are actually
available on device pins can vary by device):
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
• Up to 4 match registers can be configured for PWM operation, allowing up to 3 single
edged controlled PWM outputs. (The number of match outputs for each timer that are
actually available on device pins can vary by device.)
9.16 Multi-Rate Timer (MRT)
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with two channels. Each
channel can be programmed with an independent time interval, and each channel
operates independently from the other channels.
9.16.1 Features
• 31-bit interrupt timer
• Two channels independently counting down from individually set values
• Bus stall, repeat and one-shot interrupt modes
9.17 Windowed WatchDog Timer (WWDT)
The watchdog timer resets the controller if software fails to service the watchdog timer
periodically within a programmable time window.
9.17.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
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• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator
(WDOSC).
9.18 Self-Wake-up Timer (WKT)
The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to
this timer automatically enables the counter and launches a count-down sequence. When
the counter is used as a wake-up timer, this write can occur prior to entering a reduced
power mode.
9.18.1 Features
• 32-bit loadable down counter. Counter starts automatically when a count value is
loaded. Time-out generates an interrupt/wake up request.
• The WKT supports three clock sources: an external clock on the WKTCLKIN pin, the
low-power oscillator, and the FRO. The low-power oscillator can be used as the clock
source in sleep, deep-sleep, and power-down modes.
• The WKT can be used for waking up the part from any reduced power mode or for
general-purpose timing.
9.19 Analog comparator (ACMP)
The analog comparator with selectable hysteresis can compare voltage levels on external
pins and internal voltages.
After power-up and after switching the input channels of the comparator, the output of the
voltage ladder must be allowed to settle to its stable value before it can be used as a
comparator reference input. Settling times are given in Table 27.
The analog comparator output is a movable function and is assigned to a pin through the
switch matrix. The comparator inputs and the voltage reference are enabled through the
switch matrix.
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ext. VDDCMP VDD
LADREF
1
0
LADEN and nACOMP_PD
31
voltage
ladder out
0
COMP_VP_SEL
LADSEL
0
buf
7
ACMP_I1
ACMP_I2
ACMP_I3
ACMP_I4
VSS
internal bandgap
reference voltage
VSS
COMSTAT
ACOMP_PD
buf
n.c.
0
HYS
0
SYNC
7
DQ
DQ
to ACMP_O
1
COMPSA
COMP_VM_SEL
EDGESEL
ACOMP_RST_N
2 of 3
sampling
edge detect
S Q
R
EDGECLR or
ACOMP_RST_N
CONTROL / STATUS REGISTER BITS
COMPEDGE
(to INTERRUPT)
aaa-028402
Fig 11. Comparator block diagram
9.19.1 Features
• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input
hysteresis.
• Two selectable external voltages (VDD or ACMPVREF); fully configurable on either
positive or negative input channel.
• Internal voltage reference from band gap selectable on either positive or negative
input channel.
• 32-stage voltage ladder with the internal reference voltage selectable on either the
positive or the negative input channel.
• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V
supply voltage rail.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Interrupt output is connected to NVIC.
• Comparator level output is connected to output pin ACMP_O.
• One comparator output is internally collected to the ADC trigger input multiplexer.
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9.20 Analog-to-Digital Converter (ADC)
The ADC supports a resolution of 12 bit and fast conversion rates of up to
480 KSamples/s. Sequences of analog-to-digital conversions can be triggered by multiple
sources. Possible trigger sources are the pin triggers, the analog comparator output, and
the ARM TXEV.
The ADC includes a hardware threshold compare function with zero-crossing detection.
Remark: For best performance, select VREFP and VREFN at the same voltage levels as
VDD and VSS. When selecting VREFP and VREFN different from VDD and VSS, ensure
that the voltage midpoints are the same:
(VREFP-VREFN)/2 + VREFN = VDD/2
9.20.1 Features
•
•
•
•
•
•
•
12-bit successive approximation analog to digital converter.
12-bit conversion rate of up to 480 KSamples/s.
Two configurable conversion sequences with independent triggers.
Optional automatic high/low threshold comparison and zero-crossing detection.
Power-down mode and low-power operating mode.
Measurement range VREFN to VREFP (not to exceed VDD voltage level).
Burst conversion mode for single or multiple inputs.
9.21 CRC engine
The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
9.21.1 Features
• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x16 + x12 + x5 + 1
– CRC-16: x16 + x15 + x2 + 1
– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
• Programmable seed number setting.
• Supports CPU PIO or DMA back-to-back transfer.
• Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation.
– 16-bit write: 2-cycle operation (8-bit x 2-cycle).
– 32-bit write: 4-cycle operation (8-bit x 4-cycle).
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9.22 Clocking and power control
SYSAHBCLKCTRL
(one bit per destination)
fro
00
clk_in
01
lposc_clk
fro_div
main_clk
10
11
SYSAHBCLKDIV
“none”
001
010
clk_in
100
00
clk_in
CLKOUT
Divider
CLKOUT
011
lposc_clk
“none”
fro
000
main_clk
to CPU
(1)
Main clock select
MAINCLKSEL[1:0]
fro
to AHB peripherals, AHB
matrix, memories, etc.
main_clk
Divider
01
“none”
11
ADC Clock
Divider
to ADC
ADC clock select ADCCLKDIV
ADCCLKSEL[1:0]
CLKOUTDIV
111
CLKOUT select
CLKOUTSEL[2:0]
(1) : synchronized multiplexer, see register desriptions for details.
aaa-027119
Fig 12. LPC802 clock generation
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One for each USART (USART0 and USART1)
fro
main_clk
frg0clk
000
001
to USARTn
010
fro_div
100
“none”
111
UARTn clock select
UARTnCLKSEL[2:0]
fro
00
main_clk
“none”
01
11
Fractional Rate
Divider 0 (FRG0)
fro
main_clk
FRG0 clock select
FRG0CLKSEL[1:0]
FRG0DIV,
FRG0MULT
frg0clk
000
001
to I2C
010
fro_div
100
“none”
111
I2C clock select
I2CCLKSEL[2:0]
fro
main_clk
frg0clk
fro_div
“none”
000
001
to SPI
010
100
111
SPl clock select
SPICLKSEL[2:0]
aaa-027120
Fig 13. LPC802 clock generation (continued)
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WKT
SYSCON
system clock
WKT registers
SYSAHBCLKCTRL
(WKT clock enable)
CTRL
12 MHz
FRO
div
750 kHz
1 MHz
PDRUNCFG
(enable FRO and FRO output
FRO_PD, FROOUT_PD)
32-bit counter
COUNT
CLKSEL
SET_EXTCLK
LPOSC
PDRUNCFG
aaa-028308
WKTCLKIN
Fig 14. LPC802 WKT clocking
fro
Divide by 2
FRO OSCILLATOR
30/24/18 MHz
(default = 24 MHz)
15/12/9 MHz
(default = 12 MHz)
set_fro_frequency() API
Divide by 2
fro_div
aaa-028307
Fig 15. LPC802 FRO subsystem
Table 6.
Clocking diagram signal name descriptions
Name
Description
clk_in
The internal clock that comes from the main CLK_IN pin function. That function must be connected to the
pin by selecting it in the SWM block.
frg_clk
The output of the Fractional Rate Generator. The FRG and its source selection are shown in Figure 13.
fro_div
Divided output of the currently selected on-chip FRO oscillator. See Figure 15.
fro
The output of the currently selected on-chip FRO oscillator. See Figure 15.
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Table 6.
Clocking diagram signal name descriptions
Name
Description
main_clk
The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source
selection are shown in Figure 12.
“none”
A tied-off source that should be selected to save power when the output of the related multiplexer is not
used.
lposc_clk
The output of the 1 MHz low power oscillator. It must also be enabled in the PDRUNCFG0 register.
9.22.1 Internal oscillators
The LPC802 include two independent oscillators:
1. Free Running Oscillator.
2. Low power oscillator.
Following reset, the LPC802 operates from the FRO until switched by software allowing
the part to run without any external clock and the bootloader code to operate at a known
frequency.
See Figure 12 for an overview of the LPC802 clock generation.
9.22.1.1 Free Running Oscillator (FRO)
The FRO provides the default clock at reset and provides a clean system clock shortly
after the supply pins reach operating voltage.
• This oscillator provides a selectable 15 MHz, 12 MHz, and 9 MHz outputs that can be
used as a system clock. Also, these outputs can be divided down to 7.5 MHz, 6 MHz,
and 4.5 MHz for system clock.
• The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range
of 0 C to 70 C.
• By default, the FRO output frequency is default system (CPU) clock frequency of 12
MHz.
9.22.1.2 Low Power Oscillator (LPOsc)
The LPOsc is an independent oscillator which can be used as a system clock. The
frequency of the LPCOsc is 1 MHz.
9.22.2 Clock input
An external clock source can be supplied on the selected CLKIN pin. When selecting a
clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 12
“Static characteristics, supply pins” and Table 18 “Dynamic characteristics: I/O pins[1]”.
The maximum frequency for both clock signals is 15 MHz.
9.22.3 Clock output
The LPC802 features a clock output function that routes any oscillator or the main clock
can be selected to the CLKOUT function. The CLKOUT function can be connected to any
digital pin through the switch matrix.
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9.22.4 Power control
The LPC802 supports the ARM Cortex-M0+ sleep mode. The CPU clock rate may also be
controlled as needed by changing clock sources, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, a register is provided for shutting down the clocks to individual
on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic
power use in any peripherals that are not required for the application. Selected
peripherals have their own clock divider which provides even better power control.
9.22.4.1 Sleep mode
When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during sleep mode and may generate
interrupts to cause the processor to resume execution. sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
9.22.4.2 Deep-sleep mode
In deep-sleep mode, the LPC802 core is in sleep mode and all peripheral clocks and all
clock sources are off except for the FRO or low-power oscillator if selected. The FRO
output is disabled. In addition, all analog blocks are shut down and the flash is in standby
mode. In deep-sleep mode, the application can keep the low power oscillator and the
BOD circuit running for self-timed wakeup and BOD protection.
The LPC802 can wake up from deep-sleep mode via a reset, digital pins selected as
inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the
USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode),
or the I2C blocks (in slave mode).
Any interrupt used for waking up from deep-sleep mode must be enabled in one of the
SYSCON wake-up enable registers and the NVIC.
Deep-sleep mode saves power and allows for short wake-up times.
9.22.4.3 Power-down mode
In power-down mode, the LPC802 is in sleep mode and all peripheral clocks and all clock
sources are off except for low-power oscillator if selected. In addition, all analog blocks
and the flash are shut down. In power-down mode, the application can keep the
low-power oscillator and the BOD circuit running for self-timed wake up and BOD
protection.
The LPC802 can wake up from power-down mode via a reset, digital pins selected as
inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the
USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode),
or the I2C blocks (in slave mode).
Any interrupt used for waking up from power-down mode must be enabled in one of the
SYSCON wake-up enable registers and the NVIC.
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Power-down mode reduces power consumption compared to deep-sleep mode at the
expense of longer wake-up times.
9.22.4.4 Deep power-down mode
In deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pins. The LPC802 can wake up from deep power-down mode via eight WAKEUP pins.
See Section 9.18 “Self-Wake-up Timer (WKT)”. Five general-purpose registers are
available to store information during deep power-down mode.
The LPC802 can be prevented from entering deep power-down mode by setting a lock bit
in the PMU block. Locking out deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
When entering deep power-down mode, an external pull-up resistor is required on the
WAKEUP pins to hold it HIGH.
Table 7.
Peripheral configuration in reduced power modes
Peripheral
Sleep mode
Deep-sleep mode
Power-down mode
Deep power-down
mode
FRO
software configurable
on
off
off
FRO output
software configurable
off
off
off
Flash
software configurable
standby
off
off
BOD
software configurable
software configurable
software configurable off
LPOsc/WWDT
software configurable
software configurable
software configurable off
Digital peripherals software configurable
off
off
Wake-up buffers
software configurable (cannot
be used as wake-up source)
software configurable
(cannot be used as
wake-up source)
software configurable software configurable
(cannot be used as
wake-up source)
ADC
software configurable
off
off
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Table 8.
Wake-up sources for reduced power modes
power mode
Wake-up source
Conditions
Sleep
Any interrupt
Enable interrupt in NVIC.
Deep-sleep and
power-down
Pin interrupts
Enable pin interrupts in NVIC and STARTERP0 registers.
BOD interrupt
BOD reset
WWDT interrupt
WWDT reset
Self-Wake-up Timer
(WKT) time-out
Interrupt from
USART/SPI/I2C
peripheral
Deep power-down WAKEUP pins
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Enable interrupt in NVIC and STARTERP1 registers.
•
•
•
•
•
•
Select low-power clock for WKT clock in the WKT CTRL register.
Enable interrupt in BODCTRL register.
BOD powered in PDSLEEPCFG register.
Enable reset in BODCTRL register.
BOD powered in PDSLEEPCFG register.
Enable interrupt in NVIC and STARTERP1 registers.
WWDT running. Enable WWDT in WWDT MOD register and feed.
Enable interrupt in WWDT MOD register.
LPOsc powered in PDSLEEPCFG register.
WWDT running.
Enable reset in WWDT MOD register.
LPOsc powered in PDSLEEPCFG register.
Enable interrupt in NVIC and STARTERP1 registers.
Enable low-power oscillator in the LPOSCCLKEN register in the SYSCON
block.
Start the WKT by writing a time-out value to the WKT COUNT register.
Enable interrupt in NVIC and STARTERP1 registers.
Enable USART/I2C/SPI interrupts.
Provide an external clock signal to the peripheral.
Configure the USART in synchronous slave mode and I2C and SPI in
slave mode.
Enable the WAKEUP function in the WUENAREG register in the PMU.
9.22.5 Wake-up process
The LPC802 begin operation at power-up by using the FRO as the clock source allowing
chip operation to resume quickly. If LPOsc or external clock sources are needed by the
application, software must enable these features and wait for them to stabilize before they
are used as a clock source.
9.23 System control
9.23.1 Reset
Reset has four sources on the LPC802: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the FRO and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
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9''
9''
9''
5SX
UHVHW
(6'
QV5&
*/,7&+),/7(5
3,1
(6'
966
DDD
Fig 16. Reset pad configuration
9.23.2 Brownout detection
The LPC802 includes one reset level and three interrupt levels for monitoring the voltage
on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an
interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt
Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor
the signal by reading a dedicated status register. One threshold level can be selected to
cause a forced reset of the chip.
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9.23.3 Code security (Code Read Protection - CRP)
CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For
details, see the LPC802 user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected, fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using the
ISP entry pin as well. If necessary, the application must provide a flash update
mechanism using IAP calls or using a call to the reinvoke ISP command to enable
flash update via the USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can
be disabled. For details, see the LPC802 user manual.
9.23.4 APB interface
The APB peripherals are located on one APB bus.
9.23.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the
main static RAM, the ROM, and the APB peripherals.
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9.24 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC802 is
in reset. The JTAG boundary scan pins are selected by hardware when the part is in
boundary scan mode. See Table 4.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
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10. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
[2]
VDD
supply voltage (core and external
rail)
Vref
reference voltage
on pin VREFP
input voltage
5 V tolerant I/O pins; VDD
1.71 V
VI
analog input voltage
IDD
supply current
ISS
Ilatch
I/O latch-up current
Unit
0.5
+4.6
V
0.5
VDD
V
0.5
5.4
V
[5]
0.5
3.6
V
[6][7]
0.5
4.6
V
per supply pin (TSSOP20)
-
40
mA
per supply pin (TSSOP16)
-
30
per supply pin (HVQFN33)
-
50
on digital pins configured for an
analog function
ground current
Max
[3][4]
3 V tolerant I/O pin ACMPVREF
VIA
Min
[8]
per supply pin (WLCSP16)
-
30
per ground pin (TSSOP20)
-
40
per ground pin (TSSOP16)
-
30
per ground pin (HVQFN33)
-
50
per supply pin (WLCSP16)
-
30
(0.5VDD) < VI < (1.5VDD);
-
100
mA
65
+150
C
-
150
C
mA
Tj < 125 C
[9]
Tstg
storage temperature
Tj(max)
maximum junction temperature
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Table 9.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Ptot(pack)
Vesd
Parameter
total power dissipation (per
package)
electrostatic discharge voltage
Conditions
Min
Max
Unit
TSSOP16, based on package
heat transfer, not device power
consumption.
[11]
-
0.29
W
TSSOP16, based on package
heat transfer, not device power
consumption.
[12]
-
0.22
W
TSSOP20, based on package
heat transfer, not device power
consumption.
[11]
-
0.36
W
TSSOP20, based on package
heat transfer, not device power
consumption.
[12]
-
0.26
W
HVQFN33, based on package
heat transfer, not device power
consumption.
[11]
-
0.91
W
HVQFN33, based on package
heat transfer, not device power
consumption.
[12]
-
0.34
W
WLCSP16, based on package
heat transfer, not device power
consumption.
[11]
-
0.65
W
WLCSP16, based on package
heat transfer, not device power
consumption.
[12]
-
0.27
W
-
2000
V
human body model; all pins.
[10]
[1]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 12) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3]
Applies to all 5 V tolerant I/O pins except the 3 V tolerant pin PIO0_7.
[4]
Including the voltage on outputs in 3-state mode.
[5]
VDD present or not present.
[6]
An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
[7]
If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below
VDD without affecting the hysteresis range of the comparator function.
[8]
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[9]
Dependent on package type.
[10] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[11] JEDEC (4.5 in 4 in); still air.
[12] Single layer (4.5 in 3 in); still air.
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11. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = T amb + P D R th j – a
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 10.
Symbol
Thermal resistance
Parameter
Conditions
Max/min
Unit
TSSOP20 package
Rth(j-a)
Rth(j-c)
thermal resistance from
junction-to-ambient
JEDEC (4.5 in 4 in); still air 11015 %
C/W
single-layer (4.5 in 3 in); still 153 15 %
air
C/W
thermal resistance from
junction-to-case
2215 %
C/W
TSSOP16 package
Rth(j-a)
Rth(j-c)
thermal resistance from
junction-to-ambient
JEDEC (4.5 in 4 in); still air 13315 %
C/W
single-layer (4.5 in 3 in); still 182 15 %
air
C/W
3215 %
C/W
thermal resistance from
junction-to-ambient
JEDEC (4.5 in 4 in); still air 4315 %
C/W
single-layer (4.5 in 3 in); still 115 15 %
air
C/W
thermal resistance from
junction-to-case
1915 %
thermal resistance from
junction-to-case
HVQFN33 package
Rth(j-a)
Rth(j-c)
C/W
WLCSP16 package
Rth(j-a)
Rth(j-c)
LPC802
Product data sheet
thermal resistance from
junction-to-ambient
JEDEC (4.5 in 4 in); still air 69.215 %
C/W
single-layer (4.5 in 3 in); still 16815 %
air
C/W
1.115 %
C/W
thermal resistance from
junction-to-case
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12. Static characteristics
12.1 General operating conditions
Table 11. General operating conditions
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
fclk
clock frequency
internal CPU/system clock
-
-
15
MHz
VDD
supply voltage (core
and external rail)
1.71
-
3.6
V
2.5
-
3.6
V
1.71
-
3.6
V
For ADC operations
2.5
-
3.6
V
on pin VREFP
2.5
-
VDD
V
VDDIO
I/O rail
Vref
ADC positive reference
voltage
For ADC operations
Pin capacitance
Cio
input/output
capacitance
pins with analog and digital
functions
[2]
-
-
7.1
pF
pins with digital functions only
[2]
-
-
2.8
pF
[1]
Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.
[2]
Including bonding pad capacitance. Based on simulation, not tested in production.
12.2 Power consumption
Power measurements in active, sleep, deep-sleep, and power-down modes were
performed under the following conditions:
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIO DIR register.
• Write 1 to the GPIO CLR register to drive the outputs LOW.
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Table 12. Static characteristics, supply pins
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
IDD
supply current
Active mode; code
Min
Typ[1][2]
Max[9]
Unit
while(1){}
executed from flash;
system clock = 1 MHz
VDD = 3.3 V
[3][5][6][10]
-
0.5
-
mA
system clock = 9 MHz
VDD = 3.3 V
[3][4][5][6]
-
0.8
-
mA
system clock = 12 MHz
VDD = 3.3 V
[3][4][5][6]
-
1.0
-
mA
system clock = 15 MHz
VDD = 3.3 V
[3][4][5][6]
-
1.3
-
mA
system clock = 9 MHz
VDD = 3.3 V
[3][4][5][6]
-
0.4
-
mA
system clock = 12 MHz
VDD = 3.3 V
[3][4][5][6]
-
0.5
-
mA
system clock = 15 MHz
VDD = 3.3 V
[3][4][5][6]
-
0.6
-
mA
[3][7]
100
175
A
-
240
A
6
14
A
-
75
A
Sleep mode
supply current
IDD
Deep-sleep mode;
VDD = 3.3 V;
Tamb = 25 C
Tamb = 105 C
supply current
IDD
Power-down mode;
VDD = 3.3 V
[3][7]
-
Tamb = 25 C
Tamb = 105 C
supply current
IDD
Deep power-down mode;
VDD = 3.3 V;
[8]
Tamb = 25 C
-
0.15
0.5
A
Tamb = 105 C
-
-
7
A
[1]
Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V.
[2]
Characterized through bench measurements using typical samples.
[3]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4]
FRO enabled.
[5]
BOD disabled.
[6]
All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks disabled in system configuration block.
[7]
All oscillators and analog blocks turned off.
[8]
WAKEUP function pin pulled HIGH externally.
[9]
Tested in production, VDD = 3.6 V.
[10] LPOsc enabled, FRO disabled.
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
39 of 81
LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
DDD
,''
$
9
9
9
9
9
9
WHPSHUDWXUH&
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register.
Fig 17. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD
DDD
,''
$
9
9
9
9
WHPSHUDWXUH&
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register.
Fig 18. Power-down mode: Typical supply current IDD versus temperature for different
supply voltages VDD
LPC802
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
40 of 81
LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
DDD
,''
$
9
9
9
9
9
WHPSHUDWXUH&
WKT not running.
Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD
LPC802
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
41 of 81
LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
12.2.1 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG.
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code accessing the peripheral is executed. Measured on a typical
sample at Tamb = 25 C.
The supply currents are shown for system clock frequencies of 12 MHz and 15 MHz.
Table 13.
Power consumption for individual analog and digital blocks
Peripheral
Typical supply current in μA
Notes
System clock frequency =
n/a
12 MHz
15 MHz
FRO
74
-
-
FRO = 12MHz. FRO output disabled.
BOD
39
-
-
Independent of main clock frequency.
Flash
80
-
-
-
LPOsc
1
-
-
FRO; independent of main clock frequency.
GPIO + pin interrupt
-
40
54
GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
SWM
-
24
30
-
IOCON
-
28
36
-
CTimer
-
28
37
-
MRT
-
45
56
-
WWDT
-
31
41
-
I2C0
-
44
58
-
SPI0
-
33
42
-
USART0
-
39
46
-
USART1
-
40
50
-
Comparator ACMP
-
36
46
-
ADC
-
61
78
Digital controller only. Analog portion of the
ADC disabled in the PDRUNCFG register.
-
61
78
Combined analog and digital logic. ADC
enabled in the PDRUNCFG register and
LPWRMODE bit set to 1 in the ADC CTRL
register (ADC in low-power mode).
-
61
78
Combined analog and digital logic. ADC
enabled in the PDRUNCFG register and
LPWRMODE bit set to 0 in the ADC CTRL
register (ADC powered).
-
37
50
-
CRC
LPC802
Product data sheet
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Rev. 1.8 — 25 September 2019
© NXP Semiconductors B.V. 2019. All rights reserved.
42 of 81
LPC802
NXP Semiconductors
32-bit ARM Cortex-M0+ microcontroller
12.3 Pin characteristics
Table 14. Static characteristics, electrical pin characteristics
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Standard port pins configured as digital pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
10[2]
nA
IIH
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
0.5
10[2]
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
0.5
10[2]
nA
VI
input voltage
VDD 1.71 V; 5 V tolerant pins
except PIO0_7
0
-
5.4
V
VDD = 0 V
0
-
3.6
V
VO
output voltage
output active
0
-
VDD
V
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input voltage
-
-
0.3VDD V
Vhys
hysteresis voltage
-
0.4
-
V
VOH
HIGH-level output
voltage
VOL
IOH
LOW-level output
voltage
HIGH-level output
current
IOH = 4 mA; 2.5 V