LPC812M101FDH20FP

D D D D D R R R R R A A A A A D R R A A FT FT FT FT A A R R D D D R R A FT FT FT A A R R D D D D 32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM R R R D D D F FT FT A A Objective data sheet A Rev. 1.0 — 7 November 2012 FT FT FT FT FT LPC81xM D FT FT A A R R D D D R A FT 1. General description D R The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. 2. Features and benefits  System:  ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port.  ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  System tick timer.  Serial Wire Debug (SWD) and JTAG boundary scan modes supported.  Micro Trace Buffer (MTB) supported.  Memory:  16 kB on-chip flash programming memory with 64 Byte page write and erase.  4 kB SRAM.  ROM API support:  Boot loader.  USART drivers.  I2C drivers.  Power profiles.  Flash In-Application Programming (IAP) and In-System Programming (ISP).  Digital peripherals:  High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function.  State Configurable Timer (SCT) with input and output functions (including capture and match) assigned to pins through the switch matrix. A The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM. D D D D D R R R R R A A A A A FT FT FT FT LPC81xM FT D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D  Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator.  CRC engine.  Windowed Watchdog timer (WWDT). Analog peripherals:  Comparator with external voltage reference with pin functions assigned or enabled through the switch matrix. Serial interfaces:  Three USART interfaces with pin functions assigned through the switch matrix.  Two SPI controllers with pin functions assigned through the switch matrix.  One I2C-bus interface with pin functions assigned through the switch matrix. Clock generation:  12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  10 kHz low-power oscillator for the WKT.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input CLKIN, or the internal RC oscillator.  Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator. Power control:  Integrated PMU (Power Management Unit) to minimize power consumption.  Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.  Power-On Reset (POR).  Brownout detect. Unique device serial number for identification. Single power supply. Available as SO20 package, TSSOP20 package, TSSOP16, and DIP8 package. D FT FT A A R R D D D R A    3. Applications  8/16-bit applications  Consumer  Climate control LPC81xM Objective data sheet  Lighting  Motor control  Fire and security applications All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 2 of 67 A  R  D  FT  D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R LPC812M101FDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101FD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC812M101FDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 4.1 Ordering options Ordering options Type number Flash/kB SRAM/kB USART I2C SPI Comparator GPIO Package LPC810M021FN8 4 1 2 1 1 1 6 DIP8 LPC811M001FDH16 8 2 2 1 1 1 14 TSSOP16 LPC812M101FDH16 16 4 3 1 2 1 14 TSSOP16 LPC812M101FD20 16 4 2 1 1 1 18 SO20 LPC812M101FDH20 16 4 3 1 2 1 18 TSSOP20 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 3 of 67 A SOT403-1 R SOT097-2 D plastic dual in-line package; 8 leads (300 mil) plastic thin shrink small outline package; 16 leads; body width 4.4 mm FT DIP8 TSSOP16 A Version LPC811M001FDH16 LPC81xM F D D Description LPC810M021FN8 Table 2. A FT FT A A R R D D D Package Name FT FT FT FT Ordering information Type number A A A A R R D D D 4. Ordering information FT FT FT FT FT LPC81xM 32-bit ARM Cortex-M0+ microcontroller Table 1. A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 5. 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