LPC845M301JHI48E

LPC84x 32-bit Arm® Cortex®-M0+ microcontroller; up to 64 KB flash and 16 KB SRAM; FAIM memory; 12-bit ADC; 10-bit DACs; Comparator; Capacitive Touch Interface Rev. 2.1 — 28 October 2020 Product data sheet 1. General description The LPC84x are an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and 16 KB of SRAM. The peripheral complement of the LPC84x includes a CRC engine, four I2C-bus interfaces, up to five USARTs, up to two SPI interfaces, Capacitive Touch Interface, one multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 54 general-purpose I/O pins. For additional documentation related to the LPC84x parts, see Section 18. 2. Features and benefits  System:  Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port.  Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  System tick timer.  AHB multilayer matrix.  Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported.  Micro Trace Buffer (MTB).  Memory:  Up to 64 KB on-chip flash programming memory with 64 Byte page write and erase.  Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on power-up.  Code Read Protection (CRP)  Up to 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One 8 KB of SRAM can be used for MTB.  Bit-band addressing supported to permit atomic operations to modify a single bit.  ROM API support:  Boot loader.  Supports Flash In-Application Programming (IAP). LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller      LPC84x Product data sheet  Supports In-System Programming (ISP) through USART, SPI, and I2C.  FAIM API.  FRO API.  On-chip ROM APIs for integer divide. Digital peripherals:  High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and digital filter. GPIO direction control supports independent set/clear/toggle of individual bits.  High-current source output driver (20 mA) on four pins.  High-current sink driver (20 mA) on two true open-drain pins.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function.  CRC engine.  DMA with 25 channels and 13 trigger inputs.  Capacitive Touch Interface. Timers:  One SCTimer/PWM with five input and seven output functions (including capture and match) for timing and PWM applications. Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 8 match/captures, 8 events, and 8 states.  One 32-bit general purpose counter/timer, with four match outputs and three capture inputs. Supports PWM mode, external count, and DMA.  Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator, or an external clock input in the always-on power domain.  Windowed Watchdog timer (WWDT). Analog peripherals:  One 12-bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports two independent conversion sequences.  Comparator with five input pins and external or internal reference voltage.  Two 10-bit DACs. Serial peripherals:  Five USART interfaces with pin functions assigned through the switch matrix and two fractional baud rate generators.  Two SPI controllers with pin functions assigned through the switch matrix.  Four I2C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates on two true open-drain pins and listen mode. Three I2Cs support data rates up to 400 kbit/s on standard digital pins. Clock generation: All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 2 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller       Free Running Oscillator (FRO). This oscillator provides a selectable 18 MHz, 24 MHz, and 30 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 1.125 MHz, 1.5 MHz, 1.875 MHz, 9 MHz, 12 MHz, and 15 MHz for system clock. The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range of 0 C to 70 C.  Low power boot at 1.5 MHz using FAIM memory.  External clock input for clock frequencies of up to 25 MHz.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Low power oscillator can be used as a clock source to the watchdog timer.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input, or the internal FRO.  Clock output function with divider that can reflect all internal clock sources. Power control:  Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode.  Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and I2C peripherals.  Timer-controlled self wake-up from deep power-down mode.  Power-On Reset (POR).  Brownout detect (BOD). Unique device serial number for identification. Single power supply (1.8 V to 3.6 V). Operating temperature range -40 °C to +105 °C. Available in LQFP64, LQFP48, HVQFN48, and HVQFN33 packages. 3. Applications       LPC84x Product data sheet Sensor gateways Industrial Gaming controllers 8/16-bit applications Consumer Climate control      Simple motor control Portables and wearables Lighting Motor control Fire and security applications All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 3 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC845M301JBD64 LQFP64 Plastic low profile quad flat package; 64 leads; body 10 10  1.4 mm SOT314-2 LPC845M301JBD48 LQFP48 Plastic low profile quad flat package; 48 leads; body 7 7  1.4 mm SOT313-2 LPC845M301JHI48 HVQFN48 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; SOT619-1 48 terminals; body 7 7  0.85 mm LPC845M301JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; SOT617-11 33 terminals; body 5  5  0.85 mm LPC844M201JBD64 LQFP64 Plastic low profile quad flat package; 64 leads; body 10 10  1.4 mm SOT314-2 LPC844M201JBD48 LQFP48 Plastic low profile quad flat package; 48 leads; body 7 7  1.4 mm SOT313-2 LPC844M201JHI48 HVQFN48 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; SOT619-1 48 terminals; body 7  7  0.85 mm LPC844M201JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; SOT617-11 33 terminals; body 5  5  0.85 mm 4.1 Ordering options Table 2. Ordering options Type number Flash/KB SRAM/KB USART I2 C SPI DAC Capacitive Touch GPIO Package LPC845M301JBD64 64 16 5 4 2 2 yes 54 LQFP64 LPC845M301JBD48 64 16 5 4 2 2 yes 42 LQFP48 LPC845M301JHI48 64 16 5 4 2 2 yes 42 HVQFN48 LPC845M301JHI33 64 16 5 4 2 1 - 29 HVQFN33 LPC844M201JBD64 64 8 2 2 2 - - 54 LQFP64 LPC844M201JBD48 64 8 2 2 2 - - 42 LQFP48 LPC844M201JHI48 64 8 2 2 2 - - 42 HVQFN48 LPC844M201JHI33 64 8 2 2 2 - - 29 HVQFN33 LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 4 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 5. Marking NXP Terminal 1 index area n Terminal 1 index area aaa-014382 Fig 1. LQFP48, HVQFN48, HVQFN33 package marking Fig 2. 1 aaa-011231 LQFP64 package marking The LPC84x LQFP64 package has the following top-side marking: • First line: LPC84xMy01 – y: 3 or 2 • Second line: xxxxxx • Third line: xxxyywwx[R]x – yyww: Date code with yy = year and ww = week. – xR = Boot code version and device revision. The LPC84x LQFP48 package has the following top-side marking: • First line: 84xMy01 – y: 3 or 2 • Second line: xxxxxx • Third line: xxxyy – Date code with yy = year. • Fourth line: wwx[R]x – Date code with ww = week. – xR = Boot code version and device revision. The LPC84x HVQFN48 package has the following top-side marking: • First line: 84xMy01 – y: 3 or 2 • Second line: xxxxxx • Third line: yywwx[R]x – yyww: Date code with yy = year and ww = week. – xR = Boot code version and device revision. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 5 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The LPC84x HVQFN33 package has the following top-side marking: • First line: 84xMy – y: 3 or 2 • Second line: xxxxxx • Third line: yywwx[R]x – yyww: Date code with yy = year and ww = week. – xR = Boot code version and device revision. Table 3. Device revision table Revision identifier (R) Revision description 1A Initial device revision with Boot ROM version 13.1 LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 6 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 6. Block diagram JTAG Test and Boundary Scan interface SWD Port DEBUG INTERFACE GPIOs AND GPOINT GPIOs IOP bus ARM Cortex M0+ CLKIN XTALOUT XTALIN RESET General Purpose DMA controller M0 Clock Generation, Power Control, and other System Functions CLKOUT Voltage Regulator Vdd M1 P0 Flash interface Flash 64 kB Boot ROM 16 kB Multilayer AHB Matrix P1 SRAM/MTB 8 kB P2 SRAM 8 kB P4 SCT Timer/ PWM DMA registers CRC P3 AHB to APB bridge MTB slave interface FAIM 256-bit APB slave group IOCON Registers UARTs 0-4 UART0,1,2, 3,4 Flash Registers (NVMC) CapTouch CAPT T0 Match/ Capture CTIMER32 SPIs 0 and 1 SPI0,1 I2Cs 2 and 3 I2Cs 0 and 1 I2C0,1 Periph Input Mux Selects System control I2C2,3 COMP Inputs Comparator PMU Registers ADC Inputs and Triggers 12-bit ADC 10-bit DAC1 DAC1 outputs DAC0 outputs 10-bit DAC0 FAIM Registers PIOs Switch Matrix Wakeup Timer Multi-Rate Timer Watchdog Osc Windowed WDT Note: Yellow shaded blocks support general purpose DMA aaa-022793 Gray-shaded blocks show peripherals that can provide hardware triggers or fixed DMA requests for DMA transfers. Fig 3. LPC84x block diagram LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 7 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 7. Pinning information 49 PIO0_14/ACMP_I3/ADC_2 50 PIO0_29/DACOUT_1 51 PIO0_23/ADC_3/ACMP_I4 52 VDDA 53 VSSA 54 PIO0_30/ACMP_I5 55 PIO0_22/ADC_4 56 PIO1_20 57 PIO0_21/ADC_5 58 PIO0_20/ADC_6 59 PIO1_21 60 PIO0_19/ADC_7 61 PIO0_18/ADC_8 62 PIO1_11 63 PIO0_17/ADC_9/DACOUT_0 64 PIO1_10 7.1 Pinning PIO1_8/CAPT_YL 1 48 PIO0_0/ACMP_ I1/TDO PIO0_13/ADC_10 2 47 PIO1_7/CAPT_X8 PIO1_9/CAPT_YH 3 46 PIO0_6/ADC_1/ACMPVREF PIO0_12 4 45 PIO0_7/ADC_0 PIO0_5/RESET 5 44 PIO1_19 PIO0_4/ADC_11/TRST/WAKEUP 6 43 PIO1_18 VDD 7 42 VREFP VSS 8 41 VREFN PIO1_12 9 40 VSS PIO0_28/WKTCLKIN 10 PIO1_13 11 39 VDD SWCLK/PIO0_3/TCK 12 37 PIO1_17 PIO0_31/CAPT_X0 13 36 PIO1_16 38 PIO1_6/CAPT_X7 SWDIO/PIO0_2/TMS 14 35 PIO1_5/CAPT_6 PIO1_0/CAPT_X1 15 34 PIO0_8/XTALIN Fig 4. PIO0_1/ACMP_I2/CLKIN/TDI 32 PIO1_4/CAPT_X5 31 PIO0_15 30 PIO1_3/CAPT_X4 29 PIO0_24 28 PIO0_25 27 VDD 26 VSS 25 PIO1_15 24 PIO0_26 23 PIO1_14 22 PIO0_27 21 PIO1_2/CAPT_X3 20 PIO0_16 19 PIO1_1/CAPT_X2 18 33 PIO0_9/XTALOUT PIO0_10/I2C0_SCL 17 PIO0_11/I2C0_SDA 16 aaa-026593 Pin configuration LQFP64 package LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 8 of 100 LPC84x NXP Semiconductors 37 PIO0_14/ACMP_I3/ADC_2 38 PIO0_29/DACOUT_1 39 PIO0_23/ADC_3/ACMP_I4 40 VDDA 41 VSSA 42 PIO0_30/ACMP_I5 43 PIO0_22/ADC_4 44 PIO0_21/ADC_5 45 PIO0_20/ADC_6 46 PIO0_19/ADC_7 47 PIO0_18/ADC_8 48 PIO0_17/ADC_9/DACOUT_0 32-bit Arm Cortex-M0+ microcontroller PIO1_8/CAPT_YL 1 36 PIO0_0/ACMP_I1/TDO PIO0_13/ADC_10 2 35 PIO1_7/CAPT_X8 PIO1_9/CAPT_YH 3 34 PIO0_6/ADC_1/ACMPVREF PIO0_12 4 33 PIO0_7/ADC_0 PIO0_5/RESET 5 32 VREFP PIO0_4/ADC_11/TRST/WAKEUP 6 31 VREFN PIO0_28/WKTCLKIN 7 30 VSS SWDCLK/PIO0_3/TCK 8 29 VDD PIO0_31/CAPT_X0 9 28 PIO1_6/CAPT_X7 SWDIO/PIO0_2/TMS 10 27 PIO1_5/CAPT_X6 PIO1_0/CAPT_X1 11 26 PIO0_8/XTALIN PIO0_11/I2C0_SDA 12 Fig 5. PIO0_1/ACMP_I2/CLKIN/TDI 24 PIO1_4/CAPT_X5 23 PIO0_15 22 PIO1_3/CAPT_X4 21 PIO0_24 20 PIO0_25 19 PIO0_26 18 PIO0_27 17 PIO1_2/CAPT_X3 16 PIO0_16 15 PIO1_1/CAPT_X2 14 PIO0_10/I2C0_SCL 13 25 PIO0_9/XTALOUT aaa-026594 Pin configuration LQFP48 package LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 9 of 100 LPC84x NXP Semiconductors 37 PIO0_14/ADC_2/ACMP_I3 38 PIO0_29/DACOUT_1 39 PIO0_23/ADC_3/ACMP_I4 40 VDDA 41 VSSA 42 PIO0_30/ACMP_I5 43 PIO0_22/ADC_4 44 PIO0_21/ADC_5 45 PIO0_20/ADC_6 46 PIO0_19/ADC_7 terminal 1 index area 47 PIO0_18/ADC_8 48 PIO0_17/ADC_9/DACOUT_0 32-bit Arm Cortex-M0+ microcontroller PIO1_8/CAPT_YL 1 36 PIO0_0/ACMPIN_I1/TDO PIO0_13/ADC_10 2 35 PIO1_7/CAPT_X8 PIO1_9/CAPT_YH 3 34 PIO0_6/ADC_1/ACMPVREF PIO0_12 4 33 PIO0_7/ADC_0 PIO0_5/RESET 5 32 VREFP PIO0_4/ADC_11/TRST/WAKEUP 6 31 VREFN PIO0_28/WKTCLKIN 7 30 VSS SWDCLK/PIO0_3/TCK 8 29 VDD PIO0_31/CAPT_X0 9 28 PIO1_6/CAPT_X7 SWDIO/PIO0_2/TMS 10 27 PIO1_5/CAPT_X6 PIO1_0/CAPT_X1 11 26 PIO0_8/XTALIN PIO0_1/ACMP_I2/CLKIN/TDI 24 PIO1_4/CAPT_X5 23 PIO0_15 22 PIO1_3/CAPT_X4 21 PIO0_24 20 PIO0_25 19 PIO0_26 18 PIO0_27 17 PIO1_2/CAPT_X3 16 PIO0_16 15 PIO1_01/CAPT_X2 14 25 PIO0_9/XTALOUT PIO0_10/I2C0_SCL 13 PIO0_11/I2C0_SDA 12 aaa-026596 Transparent top view Fig 6. Pin configuration HVQFN48 package LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 10 of 100 LPC84x NXP Semiconductors PIO0_17/ADC_9/DACOUT_0 PIO0_18/ADC_8 PIO0_19/ADC_7 PIO0_20/ADC_6 PIO0_21/ADC_5 PIO0_22/ADC_4 PIO0_23/ADC_3/ACMP_I4 PIO0_14/ACMP_I3/ADC_2 31 30 29 28 27 26 25 terminal 1 index area 32 32-bit Arm Cortex-M0+ microcontroller PIO0_13/ADC_10 1 24 PIO0_0/ACMP_I1/TDO PIO0_12 2 23 PIO0_6/ADC_1/ACMPVREF PIO0_7/ADC_0 PIO0_5/RESET 3 22 PIO0_4/ADC_11/TRST/WAKEUP 4 21 VREFP PIO0_28/WKTCLKIN 5 20 VREFN SWCLK/PIO0_3/TCK 6 19 VDD SWDIO/PIO0_2/TMS 7 18 PIO0_8/XTALIN PIO0_11/I2C0_SDA 8 17 PIO0_9/XTALOUT 9 10 11 12 13 14 15 16 PIO0_10/I2C0_SCL PIO0_16 PIO0_27 PIO0_26 PIO0_25 PIO0_24 PIO0_15 PIO0_1/ACMP_I2/CLKINTDI 33 VSS aaa-026595 Transparent top view Fig 7. Pin configuration HVQFN33 package 7.2 Pin description The pin description table shows the pin functions that are fixed to specific pins on each package. See Table 4. These fixed-pin functions are selectable through the switch matrix between GPIO and the comparator, ADC, SWD, RESET, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Movable functions for the I2C, USART, SPI, CTimer, SCT pins, and other peripherals can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions. The following exceptions apply: Do not assign more than one output to any pin. However, an output and/or one or more inputs can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is disabled. Pin PIO0_4 triggers a wake-up from deep power-down mode. If the part must wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 11 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller PIO0_10 and PIO_11 are high current source pins while PIO0_2, PIO0_3, PIO0_12, and PIO0_16 are high drive output pins. The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode. Table 4. Pin description LQFP64 LQFP48 HVQFN48 HVQFN33 Symbol PIO0_0/ACMP_I1/ TDO 48 36 36 24 PIO0_1/ACMP_I2/ CLKIN/TDI 32 SWDIO/PIO0_2/ TMS SWCLK/PIO0_3/ TCK Reset Type Description state[1] [2] I; PU IO PIO0_0 — General-purpose port 0 input/output 0. In boundary scan mode: TDO (Test Data Out). 24 24 16 [2] I; PU A ACMP_I1 — Analog comparator input 1. IO PIO0_1 — General-purpose port 0 input/output 1. In boundary scan mode: TDI (Test Data In). 14 12 10 8 10 8 7 6 [4] [4] I; PU I; PU A ACMP_I2 — Analog comparator input 2. I CLKIN — External clock input. IO SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). I/O PIO0_2 — General-purpose port 0 input/output 2. I SWCLK — Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock). PIO0_4/ADC_11/ TRSTN/WAKEUP 6 6 6 4 [3] I; PU IO PIO0_3 — General-purpose port 0 input/output 3. IO PIO0_4 — General-purpose port 0 input/output 4. In boundary scan mode: TRST (Test Reset). This pin triggers a wake-up from deep power-down mode. If the part must wake up from deep power-down mode via the WAKEUP pin, do not assign any movable function to this pin and must be externally pulled HIGH before entering deep power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit deep power-down mode and wakes up the part. The WAKEUP pin can be left unconnected or be used as a GPIO or for any movable function if an external WAKEUP function is not needed. A LPC84x Product data sheet ADC_11 — ADC input 11. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 12 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 4. Pin description LQFP48 HVQFN48 HVQFN33 RESET/PIO0_5 LQFP64 Symbol 5 5 5 3 Reset Type Description state[1] [7] I; PU I RESET — External reset input: A LOW-going pulse (minimum 20 ns to maximum 50 ns) on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin triggers a wake-up from deep power-down mode. If the part must wake up from deep power-down mode via the RESET pin, do not assign any movable function to this pin and must be externally pulled HIGH before entering deep power-down mode. The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed. PIO0_6/ADC_1/ ACMPVREF PIO0_7/ADC_0 PIO0_8/XTALIN PIO0_9/XTALOUT 46 45 34 33 PIO0_10/I2C0_SCL 17 34 33 26 25 13 34 33 26 25 13 23 [10] 22 [2] 18 [8] 17 9 [8] [6] I; PU I; PU I; PU I; PU IO PIO0_5 — General-purpose port 0 input/output 5. IO PIO0_6 — General-purpose port 0 input/output 6. A ADC_1 — ADC input 1. A ACMPVREF — Alternate reference voltage for the analog comparator. IO PIO0_7 — General-purpose port 0 input/output 7. A ADC_0 — ADC input 0. IO PIO0_8 — General-purpose port 0 input/output 8. A XTALIN — Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.95 V in slave mode. See Section 14.2.2 “XTAL input”. IO PIO0_9 — General-purpose port 0 input/output 9. A XTALOUT — Output from the oscillator circuit. Inactive I; F PIO0_10 — General-purpose port 0 input/output 10 (open-drain). I2C0_SCL — Open-drain I2C-bus clock input/output. High-current sink if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_11/I2C0_SDA 16 12 12 8 [6] Inactive I; F PIO0_11 — General-purpose port 0 input/output 11 (open-drain). I2C0_SDA — Open-drain I2C-bus data input/output. High-current sink if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_12 4 4 4 2 [4] I; PU IO PIO0_12 — General-purpose port 0 input/output 12. ISP entry pin. A LOW level on this pin during reset starts the ISP command handler. PIO0_13/ADC_10 2 2 2 1 [2] I; PU IO PIO0_13 — General-purpose port 0 input/output 13. A ADC_10 — ADC input 10. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 13 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 4. Pin description LQFP48 HVQFN48 HVQFN33 PIO0_14/ ACMP_I3/ADC_2 LQFP64 Symbol 49 37 37 25 Reset Type Description state[1] [2] I; PU IO PIO0_14 — General-purpose port 0 input/output 14. A ACMP_I3 — Analog comparator common input 3. A ADC_2 — ADC input 2. PIO0_15 30 22 22 15 [5] I; PU IO PIO0_15 — General-purpose port 0 input/output 15. PIO0_16 19 15 15 10 [4] I; PU IO PIO0_16 — General-purpose port 0 input/output 16. PIO0_17/ADC_9/ DACOUT_0 63 48 48 32 [2] I; PU IO PIO0_17 — General-purpose port 0 input/output 17. A ADC_9 — ADC input 9. A DACOUT_0 — DAC Output 0. IO PIO0_18 — General-purpose port 0 input/output 18. A ADC_8 — ADC input 8. IO PIO0_19 — General-purpose port 0 input/output 19. A ADC_7 — ADC input 7. IO PIO0_20 — General-purpose port 0 input/output 20. A ADC_6 — ADC input 6. IO PIO0_21 — General-purpose port 0 input/output 21. A ADC_5 — ADC input 5. IO PIO0_22 — General-purpose port 0 input/output 22. A ADC_4 — ADC input 4. IO PIO0_23 — General-purpose port 0 input/output 23. A ADC_3 — ADC input 3. A ACMP_I4 — Analog comparator common input 4. IO PIO0_24 — General-purpose port 0 input/output 24. PIO0_18/ADC_8 61 47 47 31 [2] PIO0_19/ADC_7 60 46 46 30 [2] I; PU I; PU I; PU I; PU PIO0_20/ADC_6 58 45 45 29 [2] PIO0_21/ADC_5 57 44 44 28 [2] I; PU I; PU PIO0_22/ADC_4 55 43 43 27 [2] PIO0_23/ADC_3/ ACMP_I4 51 39 39 26 [2] PIO0_24 28 20 20 14 [5] 13 [5] I; PU In ISP mode, this is the U0_RXD pin. PIO0_25 27 19 19 I; PU IO PIO0_25 — General-purpose port 0 input/output 25. In ISP mode, this pin is the U0_TXD pin. PIO0_26 PIO0_27 23 21 18 17 18 17 12 [5] I; PU IO PIO0_26 — General-purpose port 0 input/output 26. 11 [5] I; PU IO PIO0_27 — General-purpose port 0 input/output 27. I; PU IO PIO0_28 — General-purpose port 0 input/output 28. This pin can host an external clock for the self-wake-up timer. To use the pin as a self-wake-up timer clock input, select the external clock in the wake-up timer CTRL register. The external clock input is active in all power modes, including deep power-down. IO PIO0_29 — General-purpose port 0 input/output 29. A DACOUT_1 — DAC output 1. IO PIO0_30 — General-purpose port 0 input/output 30. A ACMP_I5 — Analog comparator common input 5. PIO0_28/ WKTCLKIN 10 7 7 5 [3] PIO0_29/ DACOUT_1 50 38 38 - [5] I; PU PIO0_30/ACMP_I5 54 42 42 - [5] I; PU LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 14 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 4. Pin description HVQFN48 HVQFN33 PIO0_31/CAPT_X0 13 LQFP48 LQFP64 Symbol 9 9 - Reset Type Description state[1] [5] I; PU IO I; PU IO I; PU IO PIO0_31 — General-purpose port 0 input/output 31. CAPT_X0 — Capacitive Touch X sensor 0. PIO1_0/CAPT_X1 15 11 11 - [5] PIO1_1/CAPT_X2 18 14 14 - [5] I; PU IO I; PU IO PIO1_0 — General-purpose port 1 input/output 0. CAPT_X1 — Capacitive Touch X sensor 1. PIO1_1 — General-purpose port 1 input/output 1. CAPT_X2 — Capacitive Touch X sensor 2. PIO1_2/CAPT_X3 20 16 16 - [5] PIO1_3/CAPT_X4 29 21 21 - [5] I; PU IO I; PU IO PIO1_2 — General-purpose port 1 input/output 2. CAPT_X3 — Capacitive Touch X sensor 3. PIO1_3 — General-purpose port 1 input/output 3. CAPT_X4 — Capacitive Touch X sensor 4. PIO1_4/CAPT_X5 31 23 23 - [5] PIO1_5/CAPT_X6 35 27 27 - [5] I; PU IO I; PU IO PIO1_4 — General-purpose port 1 input/output 4. CAPT_X5 — Capacitive Touch X sensor 5. PIO1_5 — General-purpose port 1 input/output 5. CAPT_X6 — Capacitive Touch X sensor 6. PIO1_6/CAPT_X7 38 28 28 - [5] PIO1_7/CAPT_X8 47 35 35 - [5] I; PU IO I; PU IO PIO1_6 — General-purpose port 1 input/output 6. CAPT_X7 — Capacitive Touch X sensor 7. PIO1_7 — General-purpose port 1 input/output 7. CAPT_X8 — Capacitive Touch X sensor 8. PIO1_8/CAPT_YL 1 1 1 - [5] PIO1_9/CAPT_YH 3 3 3 - [5] - [5] I; PU IO PIO1_10 — General-purpose port 1 input/output 10. PIO1_8 — General-purpose port 1 input/output 8. CAPT_YL — Capacitive Touch Y Low. PIO1_9 — General-purpose port 1 input/output 9. CAPT_YH — Capacitive Touch Y High. PIO1_10 64 - - PIO1_11 62 - - - [5] I; PU IO PIO1_11 — General-purpose port 1 input/output 11. PIO1_12 9 - - - [5] I; PU IO PIO1_12 — General-purpose port 1 input/output 12. PIO1_13 11 - - - [5] I; PU IO PIO1_13 — General-purpose port 1 input/output 13. - [5] I; PU IO PIO1_14 — General-purpose port 1 input/output 14. PIO1_14 22 - - PIO1_15 24 - - - [5] I; PU IO PIO1_15 — General-purpose port 1 input/output 15. PIO1_16 36 - - - [5] I; PU IO PIO1_16 — General-purpose port 1 input/output 16. PIO1_17 37 - - - [5] I; PU IO PIO1_17 — General-purpose port 1 input/output 17. - [5] I; PU IO PIO1_18 — General-purpose port 1 input/output 18. PIO1_18 43 - - PIO1_19 44 - - - [5] I; PU IO PIO1_19 — General-purpose port 1 input/output 19. PIO1_20 56 - - - [5] I; PU IO PIO1_20 — General-purpose port 1 input/output 20. PIO1_21 59 - - - [5] I; PU IO PIO1_21 — General-purpose port 1 input/output 21. VDD 7;26;39 29 29 19 - - Supply voltage for the I/O pad ring, the and core voltage regulator. VDDA 52 40 40 VSS 8;25;40 30 30 LPC84x Product data sheet Analog supply voltage. 33[11] - - Ground. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 15 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Pin description LQFP48 HVQFN48 Reset Type Description state[1] LQFP64 Symbol HVQFN33 Table 4. VSSA 53 41 41 VREFN 41 31 31 20 - - ADC negative reference voltage. VREFP 42 32 32 21 - - ADC positive reference voltage. Must be equal or lower than VDDA. Analog ground. [1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 14.6 “Pin states in different power modes”. For termination on unused pins, see Section 14.5 “Termination of unused pins”. [2] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. This pin is active in deep power-down mode and includes a 20 ns glitch filter (active in all power modes). In deep power-down mode, pulling the WAKEUP pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other purposes, if the WKT low-power oscillator is enabled for waking up the part from deep power-down mode. See Table 20 “Dynamic characteristics: WKTCLKIN pin” for the WKTCLKIN input. [4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [6] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [7] See Figure 14 for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is available in deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from deep power-down mode. [8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system oscillator. When configured for XTALIN and XTALOUT, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [9] The WKTCLKIN function is enabled in the DPDCTRL register in the PMU. See the LPC84x user manual. [10] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is disabled. [11] Thermal pad for HVQFN33. Table 5. LPC84x Product data sheet Movable functions (assign to pins PIO0_0 to PIO0_31, PIO1_0 to PIO1_21 through switch matrix) Function name Type Description Ux_TXD O Transmitter output for USART0 to USART4. Ux_RXD I Receiver input for USART0 to USART4. Ux_RTS O Request To Send output for USART0 to USART4. Ux_CTS I Clear To Send input for USART0 to USART4. Ux_SCLK I/O Serial clock input/output for USART0 to USART4 in synchronous mode. SPIx_SCK I/O Serial clock for SPI0 and SPI1. SPIx_MOSI I/O Master Out Slave In for SPI0 and SPI1. SPIx_MISO I/O Master In Slave Out for SPI0 and SPI1. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 16 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 5. LPC84x Product data sheet Movable functions (assign to pins PIO0_0 to PIO0_31, PIO1_0 to PIO1_21 through switch matrix) Function name Type Description SPIx_SSEL0 I/O Slave select 0 for SPI0 and SPI1. SPIx_SSEL1 I/O Slave select 1 for SPI0 and SPI1. SPIx_SSEL2 I/O Slave select 2 for SPI0 and SPI1. SPIx_SSEL3 I/O Slave select 3 for SPI0 and SPI1. SCT_PIN0 I Pin input 0 to the SCT input multiplexer. SCT_PIN1 I Pin input 1 to the SCT input multiplexer. SCT_PIN2 I Pin input 2 to the SCT input multiplexer. SCT_PIN3 I Pin input 3 to the SCT input multiplexer. SCT_OUT0 O SCT output 0. SCT_OUT1 O SCT output 1. SCT_OUT2 O SCT output 2. SCT_OUT3 O SCT output 3. SCT_OUT4 O SCT output 4. SCT_OUT5 O SCT output 5. I2Cx_SDA I/O I2C1, I2C2, and I2C3 bus data input/output. I2Cx_SCL I/O I2C1, I2C2, and I2C3 bus clock input/output. ACMP_O O Analog comparator output. CLKOUT O Clock output. GPIO_INT_BMAT O Output of the pattern match engine. T0_MAT0 O Timer Match channel 0. T0_MAT1 O Timer Match channel 1. T0_MAT2 O Timer Match channel 2. T0_MAT3 O Timer Match channel 3. T0_CAP0 I Timer Capture channel 0. T0_CAP1 I Timer Capture channel 1. T0_CAP2 I Timer Capture channel 2. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 17 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8. Functional description 8.1 Arm Cortex-M0+ core The Arm Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. The core revision is r0p1. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The Arm Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.2 On-chip flash program memory The LPC84x contain up to 64 KB of on-chip flash program memory. The flash memory supports a 64 Byte page size with page write and erase. 8.3 On-chip SRAM The LPC84x contain a total of 16KB on-chip static RAM data memory in two separate SRAM blocks with one combined clock for both SRAM blocks. One 8 KB of SRAM can be used for MTB. A bit-band module is added in series with the AHB matrix to allow atomic read-modify-write operations acting on a single bit. 8.4 FAIM memory The LPC84x includes the FAIM memory and is used to configure the part at start-up. It is 128/256 bits in size and is used to configure the following: • • • • • Clocks and PMU for low-power start-up. Low power boot at 1.5 MHz using FAIM memory. Pin configuration including direction and pull- up or pull-down. Specification of pins to use for ISP entry for each serial peripheral. Select whether SWCLK and SWDIO are enabled on reset. Remark: The FAIM programming voltage range is 3.0 V  Vdd  3.6 V. 8.5 On-chip ROM The on-chip ROM contains the bootloader: • • • • • • LPC84x Product data sheet Boot loader. Supports Flash In-Application Programming (IAP). Supports In-System Programming (ISP) through USART, SPI, and I2C. On-chip ROM APIs for integer divide. FAIM API. FRO API. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 18 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.6 Memory map The LPC84x incorporates several distinct memory regions. Figure 8 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The Arm private peripheral bus includes the Arm core registers for controlling the NVIC, the system tick timer (SysTick), and the reduced power modes. Memory space (reserved) private peripheral bus (reserved) GPIO interrupts GPIO (reserved) AHB perpherals 0xFFFF FFFF RAM1 RAM0 (reserved) Boot ROM (reserved) 0x5000 C000 DMA controller 0xA000 8000 0x5000 8000 SCTimer / PWM 0xA000 4000 0x5000 4000 CRC engine 0xA000 0000 0x5000 0000 0x5001 4000 APB perpherals 0x5000 0000 0x4008 0000 APB peripherals (reserved) 0x5001 0000 MTB registers 0xE000 0000 AHB peripherals (reserved) 0x5001 4000 FAIM memory 0xE010 0000 0x4000 0000 0x1000 4000 0x1000 2000 0x1000 0000 0x0F00 4000 0x0F00 0000 0x0001 0000 Flash memory (up to 64 KB) 0x0000 0000 active interrupt vectors 0x0000 00C0 0x0000 0000 31-30 (reserved) 29 UART4 28 UART3 27 UART2 26 UART1 25 UART0 24 CapTouch 23 SPI1 22 SPI0 21 I2C1 20 I2C0 19 (reserved) 18 Syscon 17 IOCON 16 Flash controller 15 (reserved) 14 CTIMER 0 13 I2C3 12 I2C2 11 Input Multiplexing 10 (reserved) 9 Analog Comparator 8 PMU 7 ADC 6 DAC1 5 DAC0 4 FAIM controller 3 Switch Matrix 2 Wake-up Timer 1 Multi-Rate Timer 0 Watchdog timer 0x4007 FFFF 0x4007 8000 0x4007 4000 0x4007 0000 0x4006 C000 0x4006 8000 0x4006 4000 0x4006 0000 0x4005 C000 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 aaa-026589 Fig 8. LPC84x AHB Memory mapping LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 19 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.1 Features • • • • • Nested Vectored Interrupt Controller is a part of the Arm Cortex-M0+. Tightly coupled interrupt controller provides low interrupt latency. Controls system exceptions and peripheral interrupts. Supports 32 vectored interrupts. In the LPC84x, the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation using the Arm exceptions SVCall and PendSV. • Supports NMI. 8.7.2 Interrupt sources Each peripheral device has at least one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 8.8 System tick timer The Arm Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to generate a dedicated SysTick exception at a fixed time interval (typically 10 ms). 8.9 I/O configuration The IOCON block controls the configuration of the I/O pins. Each digital or mixed digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10 and PIO0_11) in Table 4 can be configured as follows: • Enable or disable the weak internal pull-up and pull-down resistors. • Select a pseudo open-drain mode. The input cannot be pulled up above VDD. The pins are not 5 V tolerant when VDD is grounded. • Program the input glitch filter with different filter constants using one of the IOCON divided clock signals (IOCONCLKCDIV, see Figure 11 “LPC84x clock generation”). You can also bypass the glitch filter. • Invert the input signal. • Hysteresis can be enabled or disabled. • For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard digital operation, for I2C standard and fast modes, or for I2C Fast mode+. • The switch matrix setting enables the analog input mode on pins with analog and digital functions. Enabling the analog mode disconnects the digital functionality. Remark: The functionality of each I/O pin is flexible and is determined entirely through the switch matrix. See Section 8.10 for details. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 20 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.9.1 Standard I/O pad configuration Figure 9 shows the possible pin modes for standard I/O pins with analog input function: • • • • • • Digital output driver with configurable open-drain output. Digital input: Weak pull-up resistor (PMOS device) enabled/disabled. Digital input: Weak pull-down resistor (NMOS device) enabled/disabled. Digital input: Repeater mode enabled/disabled. Digital input: Programmable input digital filter selectable on all pins. Analog input: Selected through the switch matrix. VDD VDD open-drain enable strong pull-up output enable ESD data output PIN pin configured as digital output driver strong pull-down ESD VSS VDD weak pull-up pull-up enable weak pull-down repeater mode enable pull-down enable PROGRAMMABLE DIGITAL FILTER data input pin configured as digital input select data inverter SWM PINENABLE for analog input analog input pin configured as analog input Fig 9. aaa-014392 Standard I/O pad configuration LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 21 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.10 Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions, for example, the USART, SPI, SCTimer/PWM, CTimer, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 5. Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in Table 4. If a fixed-pin function is disabled, any other movable function can be assigned to this pin. 8.11 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC84x use accelerated GPIO functions: • GPIO registers are on the Arm Cortex-M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 15 MHz. • An entire port value can be written in one instruction. • Mask, set, and clear operations are supported for the entire port. All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default. 8.11.1 Features • Bit level port registers allow a single instruction to set and clear any number of bits in one write operation. • Direction control of individual bits. • All I/O default to GPIO inputs with internal pull-up resistors enabled after reset except for the I2C-bus true open-drain pins PIO0_10 and PIO0_11. • Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the IOCON block for each GPIO pin (see Figure 9). • Direction (input/output) can be set and cleared individually. • Pin direction bits can be toggled. 8.12 Pin interrupt/pattern match engine The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. The pattern match engine can be used, with software, to create complex state machines based on pin inputs. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 22 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are on the IO+ bus for fast single-cycle access. 8.12.1 Features • Pin interrupts – Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active. – Pin interrupts can wake up the LPC84x from sleep mode, deep-sleep mode, and power-down mode. • Pin interrupt pattern match engine – Up to eight pins can be selected from all digital pins to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. – Each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. – Any occurrence of a pattern match can be also programmed to generate an RXEV notification to the Arm CPU. The RXEV signal can be connected to a pin. – The pattern match engine does not facilitate wake-up. 8.13 DMA controller The DMA controller can access all memories and the USART, SPI, I2C, DAC, and Capacitive Touch. DMA transfers can also be triggered by internal events like the ADC interrupts, the pin interrupts (PININT0 and PININT1), the SCTimer DMA requests, CTimer, and the DMA trigger outputs. 8.13.1 Features • Twenty five channels with each channel connected to peripheral request inputs. • DMA operations can be triggered by on-chip events or by two pin interrupts. Each DMA channel can select one trigger input from13 sources. • • • • • • LPC84x Product data sheet Priority is user selectable for each channel. Continuous priority arbitration. Address cache with two entries. Efficient use of data bus. Supports single transfers up to 1,024 words. Address increment options allow packing and/or unpacking data. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 23 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.13.2 DMA trigger input MUX (TRIGMUX) Each DMA trigger is connected to a programmable multiplexer which connects the trigger input to one of multiple trigger sources. Each multiplexer supports the same trigger sources: the ADC sequence interrupts, the SCT DMA request lines, and pin interrupts PININT0 and PININT1, and the outputs of the DMA triggers 0 and 1 for chaining DMA triggers. 8.14 USART0/1/2/3/4 All USART functions are movable functions and are assigned to pins through the switch matrix. 8.14.1 Features • Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins except the open-drain pins. • 7, 8, or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) • Parity generation and checking: odd, even, or none. • One transmit and one receive data buffer. • RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. • • • • • • Received data and status can optionally be read from a single register Break generation and detection. Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. Built-in Baud Rate Generator. A fractional rate divider is shared among all UARTs. Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. • Separate data and flow control loopback modes for testing. • Baud rate clock can also be output in asynchronous mode. 8.15 SPI0/1 All SPI functions are movable functions and are assigned to pins through the switch matrix. 8.15.1 Features • Maximum data rates of up to 30 Mbit/s in master mode and up to 18 Mbit/s in slave mode for SPI functions connected to all digital pins except the open-drain pins. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 24 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller • Data frames of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data, which can be useful while setting up an SPI memory. • Control information can optionally be written along with data, which allows very versatile operation, including “any length” frames. • One Slave Select input/output with selectable polarity and flexible usage. Remark: Texas Instruments SSI and National Microwire modes are not supported. 8.16 I2C-bus interface (I2C0/1/2/3) The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (for example, an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master. The I2C0-bus functions are fixed-pin functions. All other I2C-bus functions for I2C1/2/3 are movable functions and can be assigned through the switch matrix to any pin. However, only the true open-drain pins provide the electrical characteristics to support the full I2C-bus specification (see Ref. 3). 8.16.1 Features • I2C0 supports Fast-mode Plus with data rates of up to 1 Mbit/s in addition to standard and fast modes on two true open-drain pins. • True open-drain pins provide fail-safe operation: When the power to an I2C-bus device is switched off, the SDA and SCL pins connected to the I2C0-bus are floating and do not disturb the bus. • • • • • I2C1/2/3 support standard and fast mode with data rates of up to 400 kbit/s. Independent Master, Slave, and Monitor functions. Supports both Multi-master and Multi-master with Slave functions. Multiple I2C slave addresses supported in hardware. One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses. • 10-bit addressing supported with software assist. • Supports SMBus. 8.17 Capacitive Touch Interface The Capacitive Touch interface is designed to handle up to nine capacitive buttons in different sensor configurations, such as slider, rotary, and button matrix. It operates in sleep, deep sleep, and power-down modes, allowing very low power performance. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 25 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The Capacitive Touch module measures the change in capacitance of an electrode plate when an earth-ground connected object (for example, finger) is brought within close proximity. 8.18 SCTimer/PWM The SCTimer/PWM can perform basic 16-bit and 32-bit timer/counter functions with match outputs and external and internal capture inputs. In addition, the SCTimer/PWM can employ up to eight different programmable states, which can change under the control of events, to provide complex timing patterns. The inputs to the SCT are multiplexed between movable functions from the switch matrix and internal connections such as the ADC threshold compare interrupt, the comparator output, and the Arm core signals Arm_TXEV and DEBUG_HALTED. The signal on each SCT input is selected through the INPUT MUX. All outputs of the SCT are movable functions and are assigned to pins through the switch matrix. One SCT output can also be selected as one of the ADC conversion triggers. 8.18.1 Features • Each SCTimer/PWM supports: – Eight match/capture registers. – Eight events. – Eight states. – Five inputs. The fifth input is hard-wired to a clock source. Each input is configurable through an input multiplexer to use one of four external pins (connected through the switch matrix) or one of four internal sources. The maximum input signal frequency is 25 MHz. – Six outputs. Connected to pins through the switch matrix. • Counter/timer features: – Each SCTimer is configurable as two 16-bit counters or one 32-bit counter. – Counters can be clocked by the system clock or selected input. – Configurable as up counters or up-down counters. – Configurable number of match and capture registers. Up to eight match and capture registers total. – Upon match create the following events: interrupt; stop, limit, halt the timer or change counting direction; toggle outputs. – Counter value can be loaded into capture register triggered by a match or input/output toggle. • PWM features: – Counters can be used with match registers to toggle outputs and create time-proportioned PWM signals. – Up to six single-edge or dual-edge PWM outputs with independent duty cycle and common PWM cycle length. • Event creation features: LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 26 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller – The following conditions define an event: a counter match condition, an input (or output) condition such as a rising or falling edge or level, a combination of match and/or input/output condition. – Selected events can limit, halt, start, or stop a counter or change its direction. – Events trigger state changes, output toggles, interrupts, and DMA transactions. – Match register 0 can be used as an automatic limit. – In bidirectional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs. • State control features: – A state is defined by events that can happen in the state while the counter is running. – A state changes into another state as a result of an event. – Each event can be assigned to one or more states. – State variable allows sequencing across multiple counter cycles. • One SCTimer match output can be selected as ADC hardware trigger input. 8.18.2 SCTimer/PWM input MUX (INPUT MUX) Each input of the SCTimer/PWM is connected to a programmable multiplexer which allows to connect one of multiple internal or external sources to the input. The available sources are the same for each SCTimer/PWM input and can be selected from four pins configured through the switch matrix, the ADC threshold compare interrupt, the comparator output, and the Arm core signals Arm_TXEV and DEBUG_HALTED. 8.19 CTIMER 8.19.1 General-purpose 32-bit timers/external event counter The LPC84x has one general-purpose 32-bit timer/counter. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.19.2 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Up to three 32-bit captures can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. The number of capture inputs for each timer that are actually available on device pins can vary by device. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 27 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller – Reset timer on match with optional interrupt generation. – Shadow registers are added for glitch-free PWM output. • For each timer, up to four external outputs corresponding to match registers with the following capabilities (the number of match outputs for each timer that are actually available on device pins can vary by device): – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. • The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. • Up to four match registers can be configured for PWM operation, allowing up to three single edged controlled PWM outputs. (The number of match outputs for each timer that are actually available on device pins can vary by device.) 8.20 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 8.20.1 Features • 31-bit interrupt timer • Four channels independently counting down from individually set values • Bus stall, repeat and one-shot interrupt modes 8.21 Windowed WatchDog Timer (WWDT) The watchdog timer resets the controller if software fails to service the watchdog timer periodically within a programmable time window. 8.21.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect feed sequence causes reset or interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 28 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator (WDOSC). 8.22 Self-Wake-up Timer (WKT) The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is used as a wake-up timer, this write can occur prior to entering a reduced power mode. 8.22.1 Features • 32-bit loadable down counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request. • The WKT resides in a separate, always-on power domain. • The WKT supports three clock sources: an external clock on the WKTCLKIN pin, the low-power oscillator, and the FRO. The low-power oscillator is located in the always-on power domain, so it can be used as the clock source in deep power-down mode. • The WKT can be used for waking up the part from any reduced power mode, including deep power-down mode, or for general-purpose timing. 8.23 Analog comparator (ACMP) The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages. After power-up and after switching the input channels of the comparator, the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. Settling times are given in Table 29. The analog comparator output is a movable function and is assigned to a pin through the switch matrix. The comparator inputs and the voltage reference are enabled through the switch matrix. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 29 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller VDD COMPARATOR ANALOG BLOCK COMPARATOR DIGITAL BLOCK ACMPVREF 4 32 sync comparator level ACMP_O, ADC trigger edge detect comparator edge NVIC DACOUT_0 internal voltage reference ACMP_I[5:1] 4 aaa-027485 Fig 10. Comparator block diagram 8.23.1 Features • Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input hysteresis. • Two selectable external voltages (VDD or ACMPVREF ); fully configurable on either positive or negative input channel. • Internal voltage reference from band gap selectable on either positive or negative input channel. • 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. • Voltage ladder source voltage is selectable from an external pin or the main 3.3 V supply voltage rail. • Voltage ladder can be separately powered down for applications only requiring the comparator function. • Interrupt output is connected to NVIC. • Comparator level output is connected to output pin ACMP_O. • One comparator output is internally collected to the ADC trigger input multiplexer. 8.24 Analog-to-Digital Converter (ADC) The ADC supports a resolution of 12 bit and fast conversion rates of up to 1.2 MSamples/s. Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible trigger sources are the pin triggers, the SCT output SCT_OUT3, the analog comparator output, and the Arm TXEV. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 30 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The ADC includes a hardware threshold compare function with zero-crossing detection. Remark: For best performance, select VREFP and VREFN at the same voltage levels as VDD and VSS. When selecting VREFP and VREFN different from VDD and VSS, ensure that the voltage midpoints are the same: (VREFP-VREFN)/2 + VREFN = VDD/2 8.24.1 Features • • • • • • • • 12-bit successive approximation analog to digital converter. 12-bit conversion rate of up to 1.2 MSamples/s. Two configurable conversion sequences with independent triggers. Optional automatic high/low threshold comparison and zero-crossing detection. Power-down mode and low-power operating mode. Measurement range VREFN to VREFP (not to exceed VDD voltage level). Burst conversion mode for single or multiple inputs. Hardware calibration mode. 8.25 Digital-to-Analog Converter (DAC) The DAC supports a resolution of 10 bits. Conversions can be triggered by an external pin input or an internal timer. The DAC includes an optional automatic hardware shut-off feature which forces the DAC output voltage to zero while a HIGH level on the external DAC_SHUTOFF pin is detected. 8.25.1 Features • • • • 10-bit digital-to-analog converter. Supports DMA. Internal timer or pin external trigger for staged, jitter-free DAC conversion sequencing. Automatic hardware shut-off triggered by an external pin. 8.26 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 8.26.1 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 31 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller • Supports CPU PIO or DMA back-to-back transfer. • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle). 8.27 Clocking and power control 8.27.1 Crystal and internal oscillators The LPC84x include four independent oscillators: 1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz. 2. Free Running Oscillator. 3. Watchdog Oscillator 4. Low Power Oscillator Each oscillator, except the low-frequency oscillator, can be used for more than one purpose as required in a particular application. Following reset, the LPC84x operates from the FRO until switched by software allowing the part to run without any external crystal and the bootloader code to operate at a known frequency. See Figure 11 for an overview of the LPC84x clock generation. 8.27.1.1 Free Running Oscillator (FRO) The FRO oscillator provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage. • This oscillator provides a selectable 18 MHz, 24 MHz, and 30 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 1.125 MHz, 1.5 MHz, 1.875 MHz, 9 MHz, 12 MHz, and 15 MHz for system clock. • The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C to 70 C. • By default, the fro_oscout is 24 MHz and is divided by 2 to provide a default system (CPU) clock frequency of 12 MHz. 8.27.1.2 Crystal Oscillator (SysOsc) The crystal oscillator can be used as the clock source for the CPU, with or without using the PLL. The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 8.27.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc) The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process variations is  40%. The WDOsc is a dedicated oscillator for the windowed WWDT. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 32 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The internal low-power 10 kHz ( 40% accuracy) oscillator serves as the clock input to the WKT. This oscillator can be configured to run in all low-power modes. 8.27.2 Clock input An external clock source can be supplied on the selected CLKIN pin directly to the PLL input. When selecting a clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 13 “Static characteristics, supply pins” and Table 19 “Dynamic characteristics: I/O pins[1]”. An 1.8 V external clock source can be supplied on the XTALIN pins to the system oscillator limiting the voltage of this signal (see Section 14.2 “XTAL oscillator”). The maximum frequency for both clock signals is 25 MHz. 8.27.3 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is nominally 100 s. 8.27.4 Clock output The LPC84x features a clock output function that routes the FRO, the SysOsc, the watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can be connected to any digital pin through the switch matrix. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 33 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller sys_osc_clk clk_in fro SYSAHBCLKCTRL (one bit per destination) 00 0 external_clk 1 wd_osc_clk fro_div 01 main_clk_pre_pll 10 sys_pll0_clk 11 External clock select EXTCLKSEL[0] (1) “none” 01 main_clk main_clk Divider 10 “none” 11 Main clock select MAINCLKSEL[1:0] to AHB peripherals, AHB matrix, memories, etc. 00 to CPU (1) SYSAHBCLKDIV Main clock PLL select MAINCLKPLLSEL fro 00 external_clk wdt_osc_clk fro_div 01 11 sys_pll0_clk System PLL 10 peripheral_clk Divider pin filter(i) (1) IOCONCLKDIV(i) System PLL settings PLL clock select SYSPLLCLKSEL[1:0] SYSAHBCLKCTRL0[SCT] fro xtalin main_clk sys_osc_clk Crystal oscillator xtalout 00 sys_pll0_clk “none” fro external_clk wdt_osc_clk “none” fro 011 sys_pll0_clk CLKOUT Divider CLKOUT 111 fro_div wdt_osc_clk 100 “none” CLKOUTDIV CLKOUT select CLKOUTSEL[2:0] SYSAHBCLKCTRL1[CAPT] 000 main_clk 001 010 11 SCT clock select SCTCLKSEL[1:0] 000 sys_pll0_clk 10 to SCT input 4 SCT Clock Divider SCTCLKDIV Range select and bypass SYSOSCCTRL[1:0] main_clk 01 001 to Cap Touch 010 011 100 111 CapTouch clock select CAPTCLKSEL[2:0] fro 00 sys_pll0_clk “none” (1) : synchronized multiplexer, see register desriptions for details. 01 11 ADC Clock Divider ADC clock select ADCCLKDIV ADCCLKSEL[1:0] to ADC aaa-026590 Fig 11. LPC84x clock generation LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 34 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller One for each UART (UART0 through UART4) fro main_clk frg0clk 000 SYSAHBCLKCTRL0[UARTn] 001 to UARTn 010 frg1clk 011 fro_div 100 “none” 111 UARTn clock select UARTnCLKSEL[2:0] fro One for each l2C (I2C0 through I2C3) 00 main_clk sys_pll0_clk “none” 01 10 Fractional Rate Divider 0 (FRG0) fro main_clk 11 FRG0 clock select FRG0CLKSEL[1:0] FRG0DIV, FRG0MULT frg0clk 000 SYSAHBCLKCTRL0[I2Cn] 001 to I2Cn 010 frg1clk 011 fro_div 100 “none” 111 I2Cn clock select I2CnCLKSEL[2:0] fro main_clk sys_pll0_clk “none” 00 01 10 Fractional Rate Divider 1 (FRG1) One for each SPI (SPI0 through SPI1) 11 FRG1 clock select FRG1CLKSEL[1:0] FRG1DIV, FRG1MULT fro main_clk frg0clk frg1clk fro_div “none” 000 SYSAHBCLKCTRL0[SPln] 001 010 to SPIn 011 100 111 SPln clock select SPInCLKSEL[2:0] watchdog oscillator WWDT FRO oscillator WKT aaa-026591 Fig 12. LPC84x clock generation (continued) LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 35 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Divide by 2 0 Divide by 8 1 FAIM word0, low power boot bit 0 fro FRO Oscillator fro_oscout 1 30/24/18 MHz (default = 24 MHz) FROOSCCTRL[17] FRO_DIRECT bit set_fro_frequency() API Divide by 2 fro_div aaa-027256 Fig 13. LPC84x FRO subsystem Table 6. Clocking diagram signal name descriptions Name Description sys_osc_clk This is the internal clock that comes from external crystal oscillator through dedicated pins. frg_clk The output of the Fractional Rate Generator. The FRG and its source selection are shown in Figure 12 “LPC84x clock generation (continued)”. fro The output of the currently selected on-chip FRO oscillator. See UM11029 User manual. fro_div The FRO output. This may be either 15 MH, 12 MHz, or 9 MHz. See UM11029 User manual. main_clk The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source selection are shown in Figure 11 “LPC84x clock generation”. “none” A tied-off source that should be selected to save power when the output of the related multiplexer is not used. sys_pll0_clk The output of the System PLL. The System PLL and its source selection are shown in Figure 11 “LPC84x clock generation”. wdt_osc_clk The output of the watchdog oscillator, which has a selectable target frequency. It must also be enabled in the PDRINCFG0 register. See UM11029 User manual. xtalin Input of the main oscillator. If used, this is connected to an external crystal and load capacitor. xtalout Output of the main oscillator. If used, this is connected to an external crystal and load capacitor. clk_in This is the internal clock that comes from the main CLK_IN pin function. Connect that function to the pin by selecting it in the IOCON block. external_clk This is the internal clock that comes from the external crystal oscillator or the CLK_IN pin. 8.27.5 Power control The LPC84x supports the Arm Cortex-M0+ sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 36 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.27.5.1 Sleep mode When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep mode does not need any special sequence but re-enabling the clock to the Arm core. In sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.27.5.2 Deep-sleep mode In deep-sleep mode, the LPC84x core is in sleep mode and all peripheral clocks and all clock sources are off except for the FRO and watchdog oscillator or low-power oscillator if selected. The FRO output is disabled. In addition, all analog blocks are shut down and the flash is in standby mode. In deep-sleep mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC84x can wake up from deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive Touch, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from deep-sleep mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Deep-sleep mode saves power and allows for short wake-up times. 8.27.5.3 Power-down mode In power-down mode, the LPC84x is in sleep mode and all peripheral clocks and all clock sources are off except for watchdog oscillator or low-power oscillator if selected. In addition, all analog blocks and the flash are shut down. In power-down mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC84x can wake up from power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive Touch, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from power-down mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 8.27.5.4 Deep power-down mode In deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin and the self-wake-up timer. The LPC84x can wake up from deep power-down mode via the WAKEUP pin, RESET pin, or without an external signal by using the time-out of the self-wake-up timer (see Section 8.22). LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 37 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The LPC84x can be prevented from entering deep power-down mode by setting a lock bit in the PMU block. Locking out deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. If the part must wake up from deep power-down mode via the WAKEUP pin or RESET pin, do not assign any movable function to this pin and must be externally pulled HIGH before entering deep power-down mode. Table 7. Peripheral configuration in reduced power modes Peripheral Sleep mode Deep-sleep mode Power-down mode Deep power-down mode FRO software configurable on off off FRO output software configurable off off off Flash software configurable on off off BOD software configurable software configurable software configurable off PLL software configurable off off off SysOsc software configurable off off off WDosc/WWDT software configurable software configurable software configurable off Digital peripherals software configurable off off off WKT/low-power oscillator software configurable software configurable software configurable software configurable ADC software configurable off off off DAC0/1 software configurable off off off Capacitive Touch software configurable software configurable software configurable off Comparator software configurable off off off LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 38 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 8. Wake-up sources for reduced power modes power mode Sleep Deep-sleep and power-down Wake-up source Conditions Any interrupt Enable interrupt in NVIC. RESET pin PIO0_5 Enable the reset function in the PINENABLE0 register via switch matrix. Pin interrupts Enable pin interrupts in NVIC and STARTERP0 registers. BOD interrupt BOD reset WWDT interrupt WWDT reset Self-Wake-up Timer (WKT) time-out Interrupt from USART/SPI/I2C peripheral RESET pin PIO0_5 Interrupt from Capacitive Touch peripheral Deep power-down WAKEUP pin PIO0_4 RESET pin PIO0_5 WKT time-out • • • • • • • • • • • • • • • • • • • • Enable interrupt in NVIC and STARTERP1 registers. Enable interrupt in BODCTRL register. BOD powered in PDSLEEPCFG register. Enable reset in BODCTRL register. BOD powered in PDSLEEPCFG register. Enable interrupt in NVIC and STARTERP1 registers. WWDT running. Enable WWDT in WWDT MOD register and feed. Enable interrupt in WWDT MOD register. WDOsc powered in PDSLEEPCFG register. WWDT running. Enable reset in WWDT MOD register. WDOsc powered in PDSLEEPCFG register. Enable interrupt in NVIC and STARTERP1 registers. Enable low-power oscillator in the DPDCTRL register in the PCON block. Select low-power clock for WKT clock in the WKT CTRL register. Start the WKT by writing a time-out value to the WKT COUNT register. Enable interrupt in NVIC and STARTERP1 registers. Enable USART/I2C/SPI interrupts. Provide an external clock signal to the peripheral. Configure the USART in synchronous slave mode and I2C and SPI in slave mode. Enable the reset function in the PINENABLE0 register via switch matrix. • • • • • Enable interrupt in NVIC and STARTERP1 registers. Enable the Capacitive Touch interrupt. Switch FCLK clock source to the WDOsc. Set Capacitive Touch registers. Provide a touch event to the peripheral. Enable the WAKEUP function in the DPDCTRL register in the PMU. Enable the reset function in the DPDCTRL register in the PMU to allow wake-up in deep power-down mode. • • Enable the low-power oscillator in the DPDCTRL register in the PMU. • • Select low-power clock for WKT clock in the WKT CTRL register. Enable the low-power oscillator to keep running in deep power-down mode in the DPDCTRL register in the PMU. Start WKT by writing a time-out value to the WKT COUNT register. 8.27.6 Wake-up process The LPC84x begin operation at power-up by using the FRO as the clock source allowing chip operation to resume quickly. If the SysOsc, the external clock source, or the PLL are needed by the application, software must enable these features and wait for them to stabilize before they are used as a clock source. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 39 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.28 System control 8.28.1 Reset Reset has four sources on the LPC84x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the FRO and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. In deep power-down mode, an external pull-up resistor is required on the RESET pin. VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS aaa-004613 Fig 14. Reset pad configuration 8.28.2 Brownout detection The LPC84x includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 40 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.28.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For details, see the LPC84x user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using the ISP entry pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can be disabled. For details, see the LPC84x user manual. 8.28.4 APB interface The APB peripherals are located on one APB bus. 8.28.5 AHBLite The AHBLite connects the CPU bus of the Arm Cortex-M0+ to the flash memory, the main static RAM, the CRC, the DMA, the ROM, and the APB peripherals. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 41 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.29 Emulation and debugging Debug functions are integrated into the Arm Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The Arm Cortex-M0+ is configured to support up to four breakpoints and two watch points. The Micro Trace Buffer is implemented on the LPC84x. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the Arm SWD debug (RESET = HIGH). The Arm SWD debug port is disabled while the LPC84x is in reset. The JTAG boundary scan pins are selected by hardware when the part is in boundary scan mode (see Table 4). To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 42 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions [2] VDD supply voltage (core and external rail) VDDA Analog supply voltage on pin VDDA Vref reference voltage on pin VREFP input voltage 5 V tolerant I/O pins; VDD  1.8 V VI analog input voltage Vi(xtal) crystal input voltage IDD supply current ISS Ilatch 0.5 +4.6 V 0.5 +4.6 V VDD V 0.5 +5.5 V [5] 0.5 +5.5 V [6][7] 0.5 +4.6 V 0.5 +2.5 V per supply pin (LQFP64) - 100 mA per supply pin (LQFP48, HVQFN48) - 75 per supply pin (HVQFN33) - 50 per ground pin (LQFP64); - 100 per ground pin (LQFP48, HVQFN48) - 75 per ground pin (HVQFN33) - 100 (0.5VDD) < VI < (1.5VDD); - 100 mA 65 +150 C - 150 C [8] [2] I/O latch-up current Unit 0.5 on digital pins configured for an analog function ground current Max [3][4] on I2C open-drain pins VIA Min mA Tj < 125 C [9] Tstg storage temperature Tj(max) maximum junction temperature LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 43 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Ptot(pack) Vesd [1] Parameter Conditions total power dissipation (per package) electrostatic discharge voltage Min Max Unit LQFP64, based on package heat transfer, not device power consumption [11] - 0.66 W LQFP64, based on package heat transfer, not device power consumption [12] - 0.48 W LQFP48, based on package heat transfer, not device power consumption [11] - 0.48 W LQFP48, based on package heat transfer, not device power consumption [12] - 0.34 W HVQFN48, based on package heat transfer, not device power consumption [11] - 1.12 W HVQFN48, based on package heat transfer, not device power consumption [12] - 0.46 W HVQFN33, based on package heat transfer, not device power consumption [11] - 0.98 W HVQFN33, based on package heat transfer, not device power consumption [12] - 0.34 W - 2000 V human body model; all pins The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 13) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_10 and PIO0_11 and except the 3 V tolerant pin PIO0_6. [4] Including the voltage on outputs in 3-state mode. [5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime. [7] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below VDD without affecting the hysteresis range of the comparator function. [8] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [9] Dependent on package type. [10] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [11] JEDEC (4.5 in  4 in); still air. [12] Single layer (4.5 in  3 in); still air. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 44 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 10. Thermal resistance Symbol Parameter Conditions Max/min Unit JEDEC (4.5 in  4 in); still air 40  15 % C/W single-layer (4.5 in  3 in); still air 114  15 % C/W 20  15 % C/W JEDEC (4.5 in  4 in); still air 35  15 % C/W single-layer (4.5 in  3 in); still air 85  15 % C/W 9  15 % C/W JEDEC (4.5 in  4 in); still air 82  15 % C/W single-layer (4.5 in  3 in); still air 115  15 % C/W 30  15 % C/W JEDEC (4.5 in  4 in); still air 59  15 % C/W single-layer (4.5 in  3 in); still air 82  15 % C/W 18  15 % C/W HVQFN33 package Rth(j-a) Rth(j-c) thermal resistance from junction-to-ambient thermal resistance from junction-to-case HVQFN48 package Rth(j-a) Rth(j-c) thermal resistance from junction-to-ambient thermal resistance from junction-to-case LQFP48 package Rth(j-a) Rth(j-c) thermal resistance from junction-to-ambient thermal resistance from junction-to-case LQFP64 package Rth(j-a) Rth(j-c) thermal resistance from junction-to-ambient thermal resistance from junction-to-case LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 45 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11. Static characteristics 11.1 General operating conditions Table 11. General operating conditions Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit fclk clock frequency internal CPU/system clock - - 30 MHz VDD supply voltage (core and external rail) 1.8 - 3.6 V 3.0 - 3.6 V VDDA analog supply voltage ADC positive reference voltage Vref [3] FAIM programming only For ADC operations 2.4 - 3.6 V For DAC operations 2.7 - 3.6 V For ADC operations 2.4 - 3.6 V For DAC operations 2.7 - 3.6 V on pin VREFP 2.4 - VDDA V Oscillator pins Vi(xtal) crystal input voltage on pin XTALIN 0.5 1.8 1.95 V Vo(xtal) crystal output voltage on pin XTALOUT 0.5 1.8 1.95 V Pin capacitance Cio input/output capacitance pins with analog and digital functions [2] - - 7.1 pF I2C-bus pins [2] - - 2.5 pF pins with digital functions only [2] - - 2.8 pF [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [2] Including bonding pad capacitance. Based on simulation, not tested in production. [3] The VDD supply voltage must be 1.9 V or above when connecting an external crystal oscillator to the system oscillator. If the VDD supply voltage is below 1.9 V, an external clock source can be fed to the XTALIN by bypassing the system oscillator or the other clock sources mentioned above can be used. LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 28 October 2020 © NXP Semiconductors N.V. 2020. All rights reserved. 46 of 100 LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11.2 Power-up ramp conditions Table 12. Power-up characteristics[1] Tamb = 40 C to +105 C. Symbol Parameter Min Typ Max Unit twd Window duration - - 8 ms (time where V1