LPC8N04FHI24Z

LPC8N04 32-bit ARM Cortex®-M0+ microcontroller; 32 kB flash and 8 kB SRAM; NFC/RFID ISO 14443 type A interface Rev. 1.4 — 8 June 2018 Product data sheet 1. General description The NXP LPC8N04 is an IC optimized for an entry level Cortex-M0+ MCU with built-in NFC interface. LPC8N04 supports an effective system solution with a minimal number of external components for NFC related applications. The embedded ARM Cortex-M0+ offers flexibility to the users of this IC to implement their own dedicated solution. The LPC8N04 contains multiple features, including multiple power-down modes and a selectable CPU frequency of up to 8 MHz, for ultra-low power consumption. Users can program this LPC8N04 with the industry-wide standard solutions for ARM Cortex-M0+ processors. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. CAUTION Semiconductors are light sensitive. Exposure to light sources can cause the IC to malfunction. The IC must be protected against light. The protection must be applied to all sides of the IC. LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 2. Features and benefits  System  ARM Cortex-M0+ processor running at frequencies of up to 8 MHz  ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC)  ARM Serial Wire Debug (SWD)  System tick timer  IC reset input  Memory  32 kB on-chip flash programming memory  4 kB on-chip EEPROM of which 256 byte can be write protected  8 kB SRAM  Digital peripherals  Up to 12 General Purpose Input Output (GPIO) pins with configurable pull-up/pull-down resistors and repeater mode  GPIO pins which can be used as edge and level sensitive interrupt sources  High-current drivers/sinks (20 mA) on four GPIO pins  High-current drivers/sinks (20 mA) on two I2C-bus pins  Programmable WatchDog Timer (WDT)  Analog peripherals  Temperature sensor with 1.5 C absolute temperature accuracy between 40 C and +85 C  Communication interfaces  NFC/RFID ISO 14443 type A interface  I2C-bus interface supporting full I2C-bus specification and fast mode with a data rate of 400 kbit/s, with multiple address recognition and monitor mode  Energy harvesting functionality to power the LPC8N04.  OTA firmware update using Secondary Bootloader (SBL) library (See TN00040: LPC8N04: Encrypted Over the Air (OTA) Firmware update using NFC). OTA firmware update available on Boot ROM version 0.14.  Clock generation  8 MHz internal RC oscillator, trimmed to 2 % accuracy, which is used for the system clock  Timer oscillator operating at 32 kHz linked to the RTC timer unit  Power control  Support for 1.72 V to 3.6 V external voltages  The LPC8N04 can also be powered from the NFC field  Activation via NFC possible  Integrated Power Management Unit (PMU) for versatile control of power consumption  Four reduced power modes for ARM Cortex-M0+: sleep, deep sleep, deep power-down and battery off  Power gating for each analog peripheral for ultra-low power operation  < 50 nA IC current consumption in battery off mode at 3.0 V  Power-On Reset (POR) LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 2 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller  Unique device serial number for identification 3. Applications        Configurable LED strip/christmas tree LEDs via NFC Smart toy/interactive robot data logger Buttonless/contactless control panel Contactless diagnostic NFC e-locker Smart manufacturing NFC OTA 4. Ordering information Table 1. Ordering information Type number LPC8N04FHI24 Package Name Description Version HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4  4  0.85 mm SOT616-3 5. Marking NXP Terminal 1 index area aaa-014382 Fig 1. HVQFN24 package marking The LPC8N04 HVQFN24 package has the following top-side marking: • First line: Syww – yww: Date code with y = year and ww = week. • Second line: xxxx • Third line: LPC8N04 LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 3 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 6. Block diagram The internal block diagram of the LPC8N04 is shown in Figure 2. It consists of a Power Management Unit (PMU), clocks, timers, a digital computation and control cluster (ARM Cortex-M0+ and memories) and AHB-APB slave modules. PADS 32 kHz FRO WAKE-UP TIMER POWER PADS DIGITAL SWITCH MATRIX CLOCK SHOP EXTERNAL POWER SWITCH POR LDO (1.2 V) INTERNAL POWER SWITCHES LDO (1.6 V) 8 kB SRAM 32 kB FLASH I2C-BUS SPI TIMERS WATCHDOG SYSCONFIG GPIO 4 kB EEPROM IOCONFIG MFIO (DIGITAL) I2C-BUS 8 MHz FRO EEPROM CONTROL FLASH CONTROL PMU ARM M0+ AHB-APB BRIDGE TEMPERATURE SENSOR NFC/RFID HIGH DRIVE aaa-015348 Fig 2. LPC8N04 block diagram LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 4 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 7.1 Pinning 7.1.1 HVQFN24 package 19 LB 20 LA 21 (reserved) 22 (reserved) terminal 1 index area 23 (reserved) 24 (reserved) Figure 3 shows the pad layout of the LPC8N04 in the HVQFN24 package. PIO0_0/WAKEUP 1 18 (reserved) PIO0_1/CLKOUT 2 17 (reserved) PIO0_2/SSEL 3 16 PIO0_11/CT32B_M1/SWDIO PIO0_6/SCLK 4 PIO0_8/MISO 5 PIO0_9/MOSI 6 15 PIO0_10/CT32B_M0/SWCLK 25 VSS 14 PIO0_3/CT16B_M0 PIO0_5/SDA 12 9 RESETN PIO0_4/SCL 11 8 VSS (reserved) 10 7 VDDBAT 13 PIO0_7/CT16B_M1 aaa-015349 Transparent top view Fig 3. Table 2. Pad Symbol Pad Symbol PIO0_0/WAKEUP 13[1] PIO0_7/CT16B_M1 PIO0_1/CLKOUT 14[1] PIO0_3/CT16B_M0 PIO0_2/SSEL 15[1] PIO0_10/CT32B_M0/SWCLK 4 PIO0_6/SCLK 16[1] PIO0_11/CT32B_M1/SWDIO 5 PIO0_8/MISO 17[2] RESERVED 6 PIO0_9/MOSI 18[2] RESERVED 7 VDDBAT 19 LB 8 VSS 20 LA 9 RESETN 21[2] RESERVED RESERVED 22[2] RESERVED PIO0_4/SCL 23[2] RESERVED PIO0_5/SDA 24[2] RESERVED 3 10 11 12 Product data sheet Pad allocation table of the HVQFN24 package 1 2 LPC8N04 Pad configuration HVQFN24 [1] High source current pads; see Section 8.6.3. [2] These pads must be tied to ground. All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 5 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 3. Pad Pad description of the HVQFN24 package Symbol Type Description 7 VDDBAT supply positive supply voltage 8 VSS supply ground Supply GPIO[1] 1 2 3 14 PIO0_0 I/O GPIO WAKEUP I deep power-down mode wake-up pin[2] PIO0_1 I/O GPIO CLKOUT O clock output PIO0_2 I/O GPIO SSEL I SPI/SSP serial select line PIO0_3 I/O GPIO CT16B_M0 O 11 12 4 13 PIO0_4 I/O GPIO SCL I/O I2C-bus SCL clock line PIO0_5 I/O GPIO SDA I/O I2C-bus SDA data line PIO0_6 I/O GPIO SCLK I/O SPI/SSP serial clock line PIO0_7 I/O GPIO CT16B_M1 O 5 6 15 16 16-bit timer match output 0 16-bit timer match output 1 PIO0_8 I/O GPIO MISO O SPI/SSP master-in slave-out line PIO0_9 I/O GPIO MOSI I SPI/SSP master-out slave-in line PIO0_10 I/O GPIO CT32B_M0 O 32-bit timer match output 0 SWCLK I ARM SWD clock PIO0_11 I/O GPIO CT32B_M1 O 32-bit timer match output 1 SWDIO I/O ARM SWD I/O 20 LA A NFC antenna/coil terminal A 19 LB A NFC antenna/coil terminal B RESETN I external reset input[3] Radio Reset 9 LPC8N04 Product data sheet [1] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pads depends on the function selected through the IOCONFIG register block. [2] If external wake-up is enabled on this pad, it must be pulled HIGH before entering deep power-down mode and pulled LOW for a minimum of 100 s to exit deep power-down mode. [3] A LOW on this pad resets the device. This reset causes I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. It has weak pull-up to VDDBAT. All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 6 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8. Functional description 8.1 ARM Cortex-M0+ core Refer to the Cortex-M0+ Devices Technical Reference Manual (Ref. 1) for a detailed description of the ARM Cortex-M0+ processor. The LPC8N04 ARM Cortex-M0+ core has the following configuration: • System options – Nested Vectored Interrupt Controller (NVIC) – Fast (single-cycle) multiplier – System tick timer – Support for wake-up interrupt controller – Vector table remapping register – Reset of all registers • Debug options – Serial Wire Debug (SWD) with two watchpoint comparators and four breakpoint comparators – Halting debug is supported 8.2 Memory map Figure 4 shows the memory and peripheral address space of the LPC8N04. The only AHB peripheral device on the LPC8N04 is the GPIO module. The APB peripheral area is 512 kB in size. Each peripheral is allocated 16 kB of space. All peripheral register addresses are 32-bit word aligned. Byte and half-word addressing is not possible. All reading and writing are done per full word. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 7 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 0xFFFF FFFF (reserved) 0xE020 0000 0xE01F FFFF 0x501F FFFF (reserved) private peripheral bus 0x5001 0000 0x5000 FFFF 0xE000 0000 0xDFFF FFFF GPIO PIO0 (reserved) 0x5000 0000 0x5020 0000 0x501F FFFF AHB peripherals AHB peripherals 0x5000 0000 0x4FFF FFFF (reserved) 0x4008 0000 0x4007 FFFF (reserved) APB peripherals 0x4000 0000 0x3FFF FFFF 0x4006 0000 temperature sensor 0x4005 8000 RFID/NFC (reserved) (reserved) 0x4005 4000 0x3000 1000 0x3000 0FFF RTC timer (reserved) 4 kB EEPROM 0x3000 0000 0x2FFF FFFF (reserved) 0x1000 2000 0x1000 1FFF 0x4004 8000 system configuration 0x4004 4000 IOCONFIG 0x4004 0000 SPI/SSP 0x4003 C000 flash controller 0x4003 8000 PMU 0x4003 4000 EEPROM controller 0x4001 4000 32-bit timer (reserved) 8 kB SRAM 0x1000 0000 0x0FFF FFFF (reserved) (reserved) 0x4000 C000 16-bit timer 0x4000 4000 watchdog timer 0x4000 0000 l2C-bus (reserved) 0x0000 8000 0x0000 7FFF 32 kB on-chip flash 0x0000 0000 APB peripherals aaa-017231 Fig 4. LPC8N04 memory map 8.3 System configuration The system configuration APB block controls oscillators, start logic and clock generation of the LPC8N04. Also included in this block is a register for remapping the interrupt vector table. 8.3.1 Clock generation The LPC8N04 Clock Generator Unit (CGU) includes two independent RC oscillators. These oscillators are the System Free-Running Oscillator (SFRO) and the Timer Free-Running Oscillator (TFRO). LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 8 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The SFRO runs at 8 MHz. The system clock is derived from it and can be set to 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz or 62.5 kHz (Note: some features are not available when using the lower clock speeds). The TFRO runs at 32.768 kHz and is the clock source for the timer unit. The TFRO cannot be disabled. Following reset, the LPC8N04 starts operating at the default 500 kHz system clock frequency to minimize dynamic current consumption during the boot cycle. The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. The temperature sensor receives a fixed clock frequency, irrespective of the system clock divider settings, while the digital part uses the system clock (AHB clock 0). SYSCLKDIV[2:0] system clock (AHB clock 0) SYSTEM CLOCK DIVIDER SYSTEM FRO (8 MHz) peripheral clocks SYSAHBCLKCTRL SYSCLKTRIM fixed-frequency taps analog peripheral clocks SSPCLKDIV SPI/SSP CLOCK DIVIDER WATCHDOG CLOCK DIVIDER SPI/SSP WDT_PCLK 0 WDTSEL WDTCLKDIV PMU/always-on-domain TIMER FRO (32 kHz) wake-up timer 0 TMRCLKTRIM TMRUEN Fig 5. aaa-015352 LPC8N04 clock generator block diagram 8.3.2 Reset Reset has three sources on the LPC8N04: the RESETN pin, watchdog reset and a software reset. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 9 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.4 Power management The Power Management Unit (PMU) controls the switching between available power sources and the powering of the different voltage domains in the IC. 8.4.1 System power architecture The LPC8N04 accepts power from two different sources: from the external power supply pin VDDBAT, or from the built-in NFC/RFID rectifier. The LPC8N04 has a small automatic source selector that monitors the power inputs (VBAT and VNFC, see Figure 6) as well as pin RESETN. The PSWBAT switch is kept open until a trigger is given on pin RESETN or via the NFC field. If the trigger is given, the always-on domain, VDD_ALON, itself is powered via the PSWBAT or the PSWNFC switch: via VBAT, if VBAT > 1.72 V, or VNFC. Priority is given to VBAT when both VBAT and VNFC are present. The automatic source selector unit in the PMU decides on the powering of the internal domains based on the power source. • If a voltage > 1.72 V is detected on VBAT and not VNFC, VBAT powers the internal domains after a trigger on pin RESETN or via NFC. • If a voltage  1.72 V is detected on VBAT, and a higher voltage is detected on VNFC, the internal domains are powered from VNFC. • If a voltage > 1.72 V is detected at both VBAT and VNFC, the internal domains are powered from VBAT. • Switch over between power sources is possible. If initially both VBAT and VNFC are available, the system is powered from VBAT. If VBAT then becomes unavailable (because it is switched off externally, or by a PSWBAT/PSWNFC power switch override), the internal domains are immediately powered from VNFC. Switch over is supported in both directions. • The user can force the selection of the VBAT input by disabling the automatic power switch, which disables the automatic source selector voltage comparator. When on NFC power only (passive operation), connecting one or more 100 nF external capacitors in parallel to a GPIO pad, and setting that pad as an output driven to logic 1, is advised. Preferably a high-drive pin should be chosen and several pins can be connected in parallel. PSWNFC and PSWBAT are the power switches. PSWNFC connects power to the VDD_ALON power net when an RF field is present. PSWBAT connects power from the battery when a positive edge is detected on RESETN. If no RF power is available, the PMU can open this PSWBAT switch, effectively switching off the device. After connecting VDDBAT to a power source, the PSWBAT switch is open until a rising edge is detected on RESETN or RF power is applied. Each component of the LPC8N04 resides in one of several internal power domains, as indicated in Figure 6. The domains are VBAT, VNFC, VDD_ALON, VDD1V2 and VDD1V6. The domains VDD_ALON, VDD1V2 and VDD1V6 are powered, or not, depending on the mode of the LPC8N04. There are five modes: active, sleep, deep sleep, deep power-down and battery off. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 10 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The VDD_ALON domain contains BrownOut Detection (BOD). When enabled, if the VDD_ALON voltage drops below 1.8 V it raises a BOD interrupt. The PMU controls the active, sleep, deep sleep and deep power-down modes, and thus the power flow to the different internal components. The PMU has two LDOs powering the internal VDD1V2 and VDD1V6 voltage domains. LDO1V2 converts voltages in the range 1.72 V to 3.6 V into 1.22 V. LDO1V6 converts voltages in the range 1.72 V to 3.6 V into 1.6 V. Each LDO can be enabled separately. A 1.2 nF buffer capacitor is included at the input of the LDOs when powered via VNFC. The trigger detector (not shown in Figure 6) and power gate have a leakage of less than 50 nA to allow for long shelf life before activation. LA NFC core LB VDDBAT VNFC < 1.85 V VBAT 1.72 V to 3.6 V PSWNFC 1.6 V LDO1V6 PSWBAT ANALOG PERIPHERALS, FLASH MEMORY EEPROM MEMORY 1.72 V to 3.6 V AUTOMATIC SOURCE SELECTOR UNIT VDD_ALON ALWAYS-ON DOMAIN 75 kΩ 32 kHz FRO RESETN RTC PMU PIO0_0 WAKEUP LDO1V2 1.2 V BOD DIGITAL CORE PERIPHERALS GPREGx SFRO pin mode override if PCON.WAKEUP set, when entering Deep power-down mode aaa-019962 Fig 6. LPC8N04 power architecture The PMU states and settings of the LDOs are summarized in Table 4, and the state transitions are shown in Figure 7. Table 5 and Table 6 summarize the events that can influence wake-up from deep power-down or deep sleep modes (DEEPPDN or DEEPSLEEP to ACTIVE state transition). LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 11 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 4. IC power states State VDD_ALON DPDN[1] Sleep or Deep-sleep LDO1 1.2 V LDO2 1.6 V NOPOWER no X[2] X[2] off off ACTIVE yes 0 0 on on DEEPPDN yes 1 0 off off SLEEP/DEEPSLEEP yes 0 1 on on [1] DPDN indicates whether the system is in deep power-down mode. [2] X = don’t care. BATTERY-OFF ACTIVE SLEEP OR DEEP-SLEEP DEEP POWER-DOWN aaa-019373 Fig 7. PMU state transition diagram The power-up sequence is shown in Figure 8. Applying battery power when the PSWBAT switch is closed, or NFC power becomes available, provides the always-on part with a Power-On Reset (POR) signal. The TFRO is initiated which starts a state machine in the PMU. In the first state, the LDO1V2 powering the digital domain is started. In the second state, the LDO1V6 powering the analog domain is started which starts the flash memory. Enabling the LDO1V2, and the SFRO stabilizing, triggers the system_por. The system is now considered to be ‘on’. The system can boot when the flash memory is fully operational. The total start-up time from trigger to active mode/boot is about 2.5 ms. If there is no battery power, but there is RF power, the same procedure is followed except that PSWNFC connects power to the LDOs. The user cannot disable the TFRO as it is used by the PMU. Remark: When running without a battery, energy harvesting is limited to 2 MHz system clock. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 12 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 5. State transition events for DEEPSLEEP to ACTIVE Event Description RESETN reset asserted RTC event if the timer reaches preset value Watchdog watchdog issues interrupt or reset WAKEUP signal on WAKEUP pin RF field RF field is detected, potential NFC command input (if set in PMU) Start logic interrupt one of the enabled start logic interrupts is asserted Table 6. State transition events for DEEPPDN to ACTIVE Event Description RESETN reset asserted RTC event if the timer reaches preset value WAKEUP signal on WAKEUP pin (when enabled) RF field RF field is detected, potential NFC command input (if set in PMU) VDD_ALON off POR always-on domain start TFRO enable 1.2 V LDO SFRO starts running enable 1.6 V LDO for analog domain and flash memory SFRO stable (64 μs) power flash and digital power analog on system_por aaa-016479 Fig 8. 8.4.1.1 LPC8N04 power-up sequence Applying power to the PCB/system with battery for the first time To support long shelf life without draining the battery, the LPC8N04 is not connected to an external supply pin until RESET pin is asserted and de-asserted or the NFC field is present. Once the RESET or the NFC field is applied, the LPC8N04 is powered. 8.4.2 Power Management Unit (PMU) The Power Management Unit (PMU) partly resides in the digital power domain and partly in the always-on domain. The PMU controls the sleep, deep sleep and deep power-down modes and the power flow to the different internal circuit blocks. Five general-purpose registers in the PMU can be used to retain data during deep power-down mode. These registers are located in the always-on domain. The PMU also raises a BOD interrupt, if necessary, if VDD_ALON drops below 1.8 V. The power to the different APB analog slaves is controlled through a power-down configuration register. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 13 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The power control register selects whether an ARM Cortex-M0+ controlled power-down mode (sleep mode or deep sleep mode) or the deep power-down mode is entered. It also provides the flags for sleep or deep-sleep modes and deep power-down mode respectively. In addition, it contains the overrides for the power source selection. 8.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is a part of the ARM Cortex-M0+. The tight integration of the processor core and NVIC enables fast processing of interrupts, dramatically reducing the interrupt latency. 8.5.1 Features • • • • • NVIC that is a part of the ARM Cortex-M0+ Tightly coupled interrupt controller provides low interrupt latency Controls system exceptions and peripheral interrupts Four programmable interrupt priority levels with hardware priority level masking Software interrupt generation 8.5.2 Interrupt sources Table 7 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the NVIC. Each line may represent more than one interrupt source. There is no significance or priority about which line is connected where, except for certain standards from ARM. Table 7. LPC8N04 Product data sheet Connection of interrupt source to the NVIC Exception Vector number offset Function Flags 0 to 12 - start logic wake-up each interrupt connected to a PIO0 input pin serves as interrupts wake-up from deep-sleep mode[1] 13 - RFID/NFC RFID/NFC access detected/command received/read acknowledge 14 - RTC on/off timer RTC on/off timer event interrupt 15 - I2C-bus Slave Input (SI) (state change) 16 - CT16B 16-bit timer 17 - PMU power from NFC field detected 18 - CT32B 32-bit timer 19 - BOD brownout detection (power drop) 20 - SPI/SSP TX FIFO half empty/RX FIFO half full/ RX time-out/RX overrun 21 - TSENS temperature sensor end of conversion/low threshold/ high threshold 22 to 25 - - RESERVED 26 - WDT watchdog interrupt (WDINT) 27 - flash flash memory 28 - EEPROM EEPROM memory 29 to 30 - - RESERVED 31 - PIO0 GPIO interrupt status of port 0 All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 14 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [1] Interrupt 0 to 10 correspond to PIO0_0 to PIO0_10; interrupt 11 corresponds to RFID/NFC external access; interrupt 12 corresponds to the RTC on/off timer. 8.6 I/O configuration The I/O configuration registers control the electrical characteristics of the pads. The following features are programmable: • • • • Pin function Internal pull-up/pull-down resistor or bus keeper function Low-pass filter I2C-bus mode for pads hosting the I2C-bus function The IOCON registers control the function (GPIO or peripheral function), the input mode, and the hysteresis of all PIO0_m pins. In addition, the I2C-bus pins can be configured for different I2C-bus modes. The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a peripheral function. If the pins are GPIO pins, the GPIO0DIR registers determine whether the pin is configured as an input or output. For any peripheral function, the pin direction is controlled automatically depending on the functionality of the pin. The GPIO0DIR registers have no effect on peripheral functions. 8.6.1 PIO0 pin mode The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down resistors for each pin, or to select the repeater mode. The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. The default value is no pull-up or pull-down enabled. The repeater mode enables the pull-up resistor when the pin is at logic 1, and enables the pull-down resistor when the pin is at logic 0. This mode causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the deep power-down mode. Repeater mode is typically used to prevent a pin from floating when it is temporarily not driven. Allowing it to float could potentially use significant power. 8.6.2 PIO0 I2C-bus mode If the FUNC bits of registers PIO0_4 and PIO0_5 select the I2C-bus function, the I2C-bus pins can be configured for different I2C-bus modes: • Standard mode/fast mode I2C-bus with input glitch filter (including an open-drain output according to the I2C-bus specification) • Standard open-drain I/O functionality without input filter 8.6.3 PIO0 current source mode PIO0_3, PIO0_7, PIO0_10 and PIO0_11 are high-source pads that can deliver up to 20 mA to the load. These PIO pins can be set to either digital mode or analog current sink mode. In digital mode, the output voltage of the pad switches between VSS and VDD. In analog current drive mode, the output current sink switches between the values set by the ILO and IHI bits. The maximum pad voltage is limited to 5 V. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 15 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller CDRIVE ESD data output PIN configured as output ESD CURRENT SINK ILO[7:0] IHI[7:0] pull-up enable configured as input repeater mode enable pull-up enable data input Fig 9. aaa-015353 Pin configuration with current source mode 8.7 Fast general-purpose parallel I/O The GPIO registers control device pins that are not connected to a specific peripheral function. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC8N04 uses accelerated GPIO functions: • GPIO registers are on the ARM Cortex-M0+ I/O bus for fastest possible single-cycle I/O timing • An entire port value can be written in one instruction • Mask, set, and clear operations are supported for the entire port All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. 8.7.1 Features • Bit level port registers allow a single instruction to set and clear any number of bits in one write operation • Direction control of individual bits • After reset, all I/Os default to GPIO inputs without pull-up or pull-down resistors. The I2C-bus true open-drain pins PIO0_4 and PIO0_5 and the SWD pins PIO0_10 and PIO0_11 are exceptions • Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the IOCON block for each GPIO pin • Direction (input/output) can be set and cleared individually • Pin direction bits can be toggled LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 16 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.8 I2C-bus controller 8.8.1 Features Standard I2C-bus compliant interfaces may be configured as master, slave, or master/slave. • Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus • Programmable clock allows adjustment of I2C-bus transfer rates • Data transfer is bidirectional between masters and slaves • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus • Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer • • • • • • Supports standard mode (100 kbit/s) and fast mode (400 kbit/s) Optional recognition of up to four slave addresses Monitor mode allows observing all I2C-bus traffic, regardless of slave address The I2C-bus can be used for test and diagnostic purposes The I2C-bus contains a standard I2C-bus compliant interface with two pins Possibility to wake up LPC8N04 on matching I2C-bus slave address 8.8.2 General description Two types of data transfers are possible on the I2C-bus, depending on the state of the direction bit (R/W): 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit. The slave then transmits the data bytes to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. As a repeated START condition is also the beginning of the next serial transfer, the I2C-bus is not released. The I2C-bus interface is byte oriented and has four operating modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode. The I2C-bus interface is completely I2C-bus compliant, supporting the ability to power off the LPC8N04 independent of other devices on the same I2C-bus. The I2C-bus interface requires a minimum 2 MHz system clock to operate in normal mode, and 8 MHz for fast mode. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 17 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.8.3 I2C-bus pin description I2C-bus pin description Table 8. Pin Type Description SDA I/O I2C-bus serial data SCL I/O I2C-bus serial clock The I2C-bus pins must be configured through the PIO0_4 and PIO0_5 registers for standard mode or fast mode. The I2C-bus pins are open-drain outputs and fully compatible with the I2C-bus specification. 8.9 SPI controller 8.9.1 Features • Compatible with Motorola SPI, 4-wire Texas Instruments Synchronous Serial Interface (SSI), and National Semiconductor Microwire buses • • • • Synchronous serial communication Supports master or slave operation Eight-frame FIFOs for both transmit and receive 4-bit to 16-bit frame 8.9.2 General description The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on an SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of bidirectional data flowing between master and slave. In practice, often only one of these two data flows carries meaningful data. 8.9.3 Pin description Table 9. Pin name SPI pin description Type Interface pin SPI SSI Microwire Description SCLK I/O SCLK CLK SK serial clock SSEL I/O SSEL FS CS frame sync/slave select MISO I/O MISO DR (M) DX (S) SI (M) SO (S) master input slave output MOSI I/O MOSI DX (M) DR (S) SO (M) SI (S) master output slave input Pin detailed descriptions Serial clock — SCK/CLK/SK is a clock signal used to synchronize the transfer of data. The master drives the clock signal and the slave receives it. When SPI/SSP interface is used, the clock is programmable to be active HIGH or active LOW, otherwise it is always active HIGH. SCK only switches during a data transfer. At any other time, the SPI/SSP interface either stays in its inactive state or is not driven (remains in high-impedance state). LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 18 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Frame sync/slave select — When the SPI/SSP interface is a bus master, it drives this signal to an active state before the start of serial data. It then releases it to an inactive state after the data has been sent. The active state can be HIGH or LOW depending upon the selected bus and mode. When the SPI/SSP interface is a bus slave, this signal qualifies the presence of data from the master according to the protocol in use. When there is only one master and slave, the master signals, frame sync or slave select, can be connected directly to the corresponding slave input. When there are multiple slaves, further qualification of frame sync/slave select inputs is normally necessary to prevent more than one slave from responding to a transfer. Master Input Slave Output (MISO) — The MISO signal transfers serial data from the slave to the master. When the SPI/SSP is a slave, it outputs serial data on this signal. When the SPI/SSP is a master, it clocks in serial data from this signal. It does not drive this signal and leaves it in a high-impedance state when the SPI/SSP is a slave and not selected by FS/SSEL. Master Output Slave Input (MOSI) — The MOSI signal transfers serial data from the master to the slave. When the SPI/SSP is a master, it outputs serial data on this signal. When the SPI/SSP is a slave, it clocks in serial data from this signal. 8.10 RFID/NFC communication unit 8.10.1 Features • • • • • ISO/IEC14443A part 1 to part 3 compatible MIFARE (Ultralight) EV1 compatible NFC Forum Type 2 compatible Easy interfacing with standard user memory space READ/WRITE commands Passive operation possible 8.10.2 General description The RFID/NFC interface allows communication using 13.56 MHz proximity signaling. APB LA EEPROM SUBSYSTEM RFID ANALOG INTERFACE LB RFID ANALOG SUBSYSTEM EEPROM INTERFACE RFID MAIN CONTROLLER RFID DIGITAL SUBSYSTEM TP VDD_RFID SRAM CMDIN APB INTERFACE DATAOUT SR Register APB SLAVE SUBSYSTEM irq aaa-015354 Fig 10. Block diagram of the RFID/NFC interface LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 19 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The CMDIN, DATAOUT, Status Register (SR) and SRAM are mapped in the user memory space of the RFID core. The RFID READ and WRITE commands allow wireless communication to this shared memory. Messages can be in raw mode (user proprietary protocol) or formatted according to NFC forum type 2 NDEF messaging and ISO/IEC 11073. 8.11 16-bit timer 8.11.1 Features One 16-bit timer with a programmable 16-bit prescaler. • Timer operation • Four 16-bit match registers that allow: – Continuous operation with optional interrupt generation on match – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation • Up to two CT16B external outputs corresponding to the match registers with the following capabilities: – Set LOW on match – Set HIGH on match – Toggle on match – Do nothing on match • Up to two match registers can be configured as Pulse Width Modulation (PWM) allowing the use of up to two match outputs as single edge controlled PWM outputs 8.11.2 General description The peripheral clock (PCLK), which is derived from the system clock, clocks the timer. The timer can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock. Each timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. In PWM mode, four match registers can be used to provide a single-edge controlled PWM output on the match output pins. The use of the match registers that are not pinned out to control the PWM cycle length is recommended. 8.12 32-bit timer 8.12.1 Features One 32-bit timer with a programmable 32-bit prescaler. • Timer operation • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 20 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation • Up to two CT32B external outputs corresponding to the match registers with the following capabilities: – Set LOW on match – Set HIGH on match – Toggle on match – Do nothing on match • Up to two match registers can be configured as PWM allowing the use of up to two match outputs as single edge controlled PWM outputs 8.12.2 General description The peripheral clock (PCLK), which is derived from the system clock, clocks the timer. The timer can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock. Each timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. In PWM mode, four match registers can be used to provide a single-edge controlled PWM output on the match output pins. Use of the match registers that are not pinned out to control the PWM cycle length is recommended. 8.13 WatchDog Timer (WDT) If the microcontroller enters an erroneous state, the purpose of the WatchDog Timer (WDT) is to reset it within a reasonable amount of time. When enabled, if the user program fails to feed (or reload) the WDT within a predetermined amount of time, the WDT generates a system reset. 8.13.1 Features • If not periodically reloaded, it internally resets the microcontroller • Debug mode • Enabled by software but requires a hardware reset or a WDT reset/interrupt to be disabled • • • • If enabled, incorrect/incomplete feed sequence causes reset/interrupt Flag to indicate WDT reset Programmable 24-bit timer with internal prescaler Selectable time period from (TWDCLK  256  4) to (TWDCLK  224  4) in multiples of TWDCLK  4 • The WDT clock (WDCLK) source is a 2 MHz clock derived from the SFRO, or the external clock as set by the SYSCLKCTRL register LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 21 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.13.2 General description The WDT consists of a divide by 4 fixed prescaler and a 24-bit counter. The clock is fed to the timer via a prescaler. The timer decrements when clocked. The minimum value by which the counter is decremented is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the minimum WDT interval is (TWDCLK  256  4) and the maximum is (TWDCLK  224  4), in multiples of (TWDCLK  4). 8.14 System tick timer 8.14.1 Features • Simple 24-bit timer • Uses dedicated exception vector • Clocked internally by the system clock or the system clock divided by two 8.14.2 General description The SYSTICK timer is a part of the Cortex-M0+. The SYSTICK timer can be used to generate a fixed periodic interrupt for use by an operating system or other system. Since the SYSTICK timer is a part of the Cortex-M0+, it facilitates porting of software by providing a standard timer available on Cortex-M0+ based devices. The SYSTICK timer can be used for management software. Refer to the Cortex-M0+ Devices - Generic User Guide (Ref. 2) for details. 8.15 Real-Time Clock (RTC) timer 8.15.1 Features The Real-Time Clock (RTC) block two counters: 1. A countdown timer generating a wake-up signal when it expires 2. A continuous counter that counts seconds since power-up or the last system reset The countdown timer runs on a low speed clock and runs in an always-on power domain. The delay, as well as a clock tuning prescaler, can be configured via the APB bus. The RTC countdown timer generates both the deep power-down wake-up signal and the RTC interrupt signal (wake-up interrupt 12). The deep power-down wake-up signal is always generated, while the interrupt can be masked according to the settings in the RTCIMSC register. 8.15.2 General description The RTC module consists of two parts: 1. The RTC core module, implementing the RTC timers themselves. This module runs in the always-on VDD_ALON domain. 2. The AMBA APB slave interface. This module allows configuration of the RTC core via an APB bus. This module runs in the switched power domain. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 22 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.16 Temperature sensor 8.16.1 Features The temperature sensor block measures the chip temperature, and outputs a raw value or a calibrated value in Kelvin. 8.16.2 General description The temperature is measured using a high-precision, zoom-ADC. The analog part is able to measure a highly temperature-dependent X = Vbe / Vbe1. It determines the value of X by first applying a coarse search (successive approximation), and then a sigma-delta in a limited range. 8.17 Serial Wire Debug (SWD) The debug functions are integrated into the ARM Cortex-M0+. Serial Wire Debug (SWD) functions are supported. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watchpoints. • • • • Supports ARM SWD mode Direct debug access to all memories, registers, and peripherals No target resources are required for the debugging session Four breakpoints. Four instruction breakpoints that can also be used to remap instruction addresses for code patches. Two data comparators that can be used to remap addresses for patches to literal values • Two data watchpoints that can also be used as triggers 8.18 On-chip flash memory The LPC8N04 contains a 32 kB flash memory of which 30 kB can be used as program and data memory. The flash is organized in 32 sectors of 1 kB. Each sector consists of 16 rows of 16  32-bit words. 8.18.1 Reading from flash Reading is done via the AHB interface. The memory is mapped on the bus address space as a contiguous address space. Memory data words are seen on the bus using a little endian arrangement. 8.18.2 Writing to flash Writing to flash means copying a word of data over the AHB to the page buffer of the flash. It does not actually program the data in the memory array. This programming is done by subsequent erase and program cycles. 1. Vbe is the base-emitter voltage of a bipolar transistor. Basically, the temperature sensor measures the voltage drop over a diode formed by the base-emitter junction of a bipolar transistor. It compares the Vbe at different current levels (from which follows the Vbe). LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 23 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.18.3 Erasing/programming flash Erasing and programming are separate operations. Both are possible only on memory sectors that are unprotected and unlocked. Protect/lock information is stored inside the memory itself, so the controller is not aware of protection status. Therefore, if a program/erase operation is performed on a protected or locked sector, it does not flag an error. Protection — At exit from reset, all sectors are protected against accidental modification. To allow modification, a sector must be unprotected. It can then be protected again after that the modification is performed. Locking — Each flash sector has a lock bit. Lock bits can be set but cannot be cleared. Locked sectors cannot be erased and reprogrammed. 8.19 On-chip SRAM The LPC8N04 contains a total of 8 kB on-chip SRAM memory configured as 256  2  4  32 bit. 8.20 On-chip EEPROM The LPC8N04 contains a 4 kB EEPROM. This EEPROM is organized in 64 rows of 32  16-bit words. Of these rows, the last four contain calibration and test data and are locked. This data is either used by the bootloader after reset, or made accessible to the application via firmware Application Programming Interface (API). 8.20.1 Reading from EEPROM Reading is done via the AHB interface. The memory is mapped on the bus address space, as a contiguous address space. Memory data words are seen on the bus using a little endian arrangement. 8.20.2 Writing to EEPROM Erasing and programming is performed, as a single operation, on one or more words inside a single page. Previous write operations have transferred the data to be programmed into the memory page buffer. The page buffer tracks which words were written to (offset within the page only). Words not written to, retain their previous content. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 24 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage VI input voltage Conditions Min Max Unit 0.5 +3.6 V normal PIO pads (VDD = 0.6 V) 0.5 +3.6 V high-source PIO pads 0.5 +5.5 V LA/LB pads 0.5 +5.5 V IDD supply current per supply pin - 100 mA ISS ground supply current per supply pin - 100 mA Ilu latch-up current I/O; 0.5VDD < VI < +1.5VDD; Tj < 125 C - 100 mA Tstg storage temperature 40 +125 C Tj junction temperature - 125 C Ptot total power dissipation - 1 W VESD electrostatic discharge voltage human body model; all pins 2000 +2000 V charged device model; all pins 500 +500 V LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 25 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +85 C, unless otherwise stated. Symbol Parameter Conditions Min Typ Max Unit 1.72 3.0 3.60 V - - - A Supply pins supply voltage VDD IDD supply current voltage and clock frequency dependent IL(off) off-state leakage current IDD(pd) power-down mode supply current [1] deep power-down mode - - 50 nA - 3 - A Standard GPIO pins VIH HIGH-level input voltage 0.7  VDD - - V VIL LOW-level input voltage - - 0.3  VDD V Vhys hysteresis voltage 0.4 - - V Rpd pull-down resistance - 72 - k Rpu pull-up resistance - 73 - k HIGH-level VDD = 1.8 V [2] - 2 - mA HIGH-level VDD = 3.6 V [2] - 8 - mA LOW-level VDD = 1.8 V [2] - 4 - mA LOW-level VDD = 3.6 V [2] - 16 - mA HIGH-level VDD = 1.8 V [3] 4 - 6 mA HIGH-level VDD = 3.6 V [3] 13 - 18 mA LOW-level VDD = 1.8 V [3] 5.5 - 8 mA LOW-level VDD = 3.6 V [3] 22 - 32 mA LOW-level VDD = 1.8 V [4] 2 - 8.5 mA LOW-level VDD = 3.6 V [4] 9.5 - 38 mA falling VDD - 1.8 - V rising VDD - 1.875 - V - 75 - mV source current IS High-drive GPIO pins source current IS I2C-bus pins source current IS Brownout detect Vtrip(bo) brownout trip voltage Vhys hysteresis voltage General Rpu(int) internal pull-up resistance on pin RESETN - 100 - k Cext external capacitance on pin RESETN - - 1 nF [1] See Figure 11. [2] PIO0_0, PIO0_1, PIO0_2, PIO0_6, PIO0_8, PIO0_9. [3] PIO0_3, PIO0_7, PIO0_10, PIO0_11. [4] PIO0_4, PIO0_5. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 26 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-022790 1000 (6) IDD (μA) 800 600 (5) 400 (4) (3) (2) (1) 200 0 1.5 2 2.5 3 3.5 4 VDD (V) Plot of IDD / VDD when ARM running a while-1 loop in normal mode, no NFC field present. (1) System clock = 250 kHz (2) System clock = 500 kHz (3) System clock = 1 MHz (4) System clock = 2 MHz (5) System clock = 4 MHz (6) System clock = 8 MHz Fig 11. Active current consumption Table 12. Temperature sensor characteristics Symbol Parameter Conditions Min Typ Max Unit ICC(pd) power-down mode supply current TSENS disabled - - 1 nA Istb standby current TSENS enabled - 6 7 A ICC(oper) operating supply current TSENS converting - 10 12 A Tacc temperature accuracy 1.5 - +1.5 C Note: The absolute accuracy is valid for the factory calibration of the temperature sensor. The sensor can be user-calibrated to reach higher accuracy. Table 13. Antenna input characteristics Symbol Parameter Ci input capacitance fi input frequency [1] Conditions [1] Min Typ Max Unit - 50 - pF - 13.56 - MHz Tamb = 22 C, f = 13.56 MHz, RMS voltage between LA and LB = 1.5 V. Table 14. EEPROM characteristics Symbol Parameter Conditions Min Typ Max Unit tret(data) data retention time Tamb = 22 C 10 - - year LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 27 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11. Dynamic characteristics 11.1 I/O pins Table 15. I/O dynamic characteristics These characteristics apply to standard port pins and RESETN pin. Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns 11.2 I2C-bus Table 16. I2C-bus dynamic characteristics See UM10204 - I2C-bus specification and user manual (Ref. 3) for details. Tamb = 40 C to +85 C[1]; see the timing diagram in Figure 12. Symbol Parameter Conditions Min Typ Max Unit fSCL SCL clock frequency standard mode 0 - 100 kHz 0 - 400 kHz fast mode tf tLOW tHIGH tHD;DAT tSU;DAT fall time of both SDA and SCL signals standard mode [2][3][4] fast mode [2][3][4] LOW period of the SCL clock standard mode 4.7 - - s fast mode 1.3 - - s standard mode 4.0 - - s fast mode 0.6 - - s HIGH period of the SCL clock data hold time data set-up time - - 300 ns 20 + 0.1  Cb - 300 ns standard mode [2][5][6] 0 - - s fast mode [2][5][6] 0 - - s standard mode [7][8] 250 - - ns fast mode [7][8] 100 - - ns [1] Parameters are valid over operating temperature range unless otherwise specified. [2] A device must internally provide a hold time of at least 300 ns for the SDA signal (regarding the VIH(min) of the SCL signal). The hold time is to bridge the undefined region of the falling edge of SCL. [3] Cb = total capacitance of one bus line in pF. [4] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. It allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [5] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [6] The maximum tHD;DAT could be 3.45 s and 0.9 s for standard mode and fast mode. However, it must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see Ref. 3). Only meet this maximum if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [7] tSU;DAT is the data set-up time that is measured against the rising edge of SCL; applies to data in transmission and the acknowledge. [8] A fast mode I2C-bus device can be used in a standard-mode I2C-bus system but it must meet the requirement tSU;DAT = 250 ns. This requirement is automatically the case if the device does not stretch the LOW period of the SCL signal. If it does, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns before the SCL line is released. This procedure is in accordance with the standard-mode I2C-bus specification. Also, the acknowledge timing must meet this set-up time. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 28 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller tf tSU;DAT 70 % 30 % SDA 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 S = START condition Fig 12. I2C-bus pins clock timing 11.3 SPI interfaces Table 17. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI master tcy(clk) tSU;DAT tHD;DAT tv(Q) th(Q) full-duplex mode [1] 50 - - ns when only transmitting [1] 40 - - ns 2.4 V  VDD < 3.6 V [2] 15 - - ns 2.0 V  VDD < 2.4 V [2] 20 - - ns 1.8 V  VDD < 2.0 V [2] 24 - - ns data hold time [2] 0 - - ns data output valid time [2] - - 10 ns data output hold time [2] 0 - - ns PCLK cycle time [3][4] 0 - - ns data hold time [3][4] 3  Tcy(PCLK) + 4 - - ns data output valid time [3][4] - - 3  Tcy(PCLK) + 11 ns data output hold time [3][4] - - 2  Tcy(PCLK) + 5 clock cycle time data set-up time SPI slave Tcy(PCLK) tHD;DAT tv(Q) th(Q) [1] ns tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate tcy(clk) is a function of: a) the main clock frequency fmain b) the SPI peripheral clock divider (SSPCLKDIV) c) the SPI SCR parameter (specified in the SSP0CR0 register) d) the SPI CPSDVSR parameter (specified in the SPI clock prescale register) [2] Tamb = 40 C to +105C. [3] tcy(clk) = 12  Tcy(PCLK). [4] Tamb = 25 C for normal voltage supply: VDD = 3.3 V. LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 29 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tSU;DAT DATA VALID MISO DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tSU;DAT MISO CPHA = 1 tHD;DAT DATA VALID tHD;DAT CPHA = 0 DATA VALID aaa-024226 Fig 13. SPI master timing in SPI mode tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tSU;DAT MOSI DATA VALID tHD;DAT DATA VALID tv(Q) MISO th(Q) DATA VALID tSU;DAT MOSI DATA VALID tHD;DAT DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID aaa-024227 Fig 14. SPI slave timing in SPI mode LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 30 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm A B D SOT616-3 terminal 1 index area A A1 E c detail X e1 C 1/2 e b e 7 v w 12 y y1 C C A B C L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.5 scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A(1) 1 A1 b c 0.05 0.30 D(1) Dh E(1) Eh 4.1 2.75 4.1 2.75 0.2 0.00 0.18 3.9 5 mm 2.45 3.9 e e1 e2 0.5 2.5 2.5 L v w y y1 0.5 2.45 0.1 0.05 0.05 0.1 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC SOT616-3 JEDEC JEITA sot616-3_po European projection Issue date 16-02-17 16-07-14 MO-220 Fig 15. HVQFN24 package outline LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 31 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13. Abbreviations Table 18. LPC8N04 Product data sheet Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus API Application Programming Interface ARM Advanced RISC Machine BOD BrownOut Detection CGU Clock Generator Unit EEPROM Electrically Erasable Programmable Read-Only Memory GPIO General Purpose Input Output I2C Inter-Integrated Circuit LDO Low DropOut MISO Master Input Slave Output MOSI Master Output Slave Input NDEF NFC Data Exchange Format NFC Near Field Communication NVIC Nested Vectored Interrupt Controller PMU Power Management Unit POR Power-On Reset PWM Pulse Width Modulation RFID Radio Frequency Identification RISC Reduced Instruction Set Computer RTC Real-Time Clock SFRO System Free-Running Oscillator SI Slave Input SO Slave Output SPI Serial Peripheral Interface SR Status Register SSI Synchronous Serial Interface SSP Synchronous Serial Port SWD Serial Wire Debug TFRO Timer Free-Running Oscillator WDT WatchDog Timer All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 32 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14. References LPC8N04 Product data sheet [1] DDI0484C_cortex_m0p_r0p1_trm — Cortex-M0+ Devices - Technical Reference Manual [2] DUI0662B_cortex_m0p_r0p1_dgug — Cortex-M0+ Devices - Generic User Guide [3] UM10204 — I2C-bus specification and user manual All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 33 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 15. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC8N04 v.1.4 20180608 Product data sheet - LPC8N04 v.1.3 Modification: LPC8N04 v.1.3 Modification: LPC8N04 v.1.2 Modification: LPC8N04 v.1.1 Modification: LPC8N04 v.1.0 LPC8N04 Product data sheet • Updated Section 2 “Features and benefits”: Added text: OTA firmware update using Secondary Bootloader (SBL) library (See TN00040: LPC8N04: Encrypted Over the Air (OTA) Firmware update using NFC). OTA firmware update available on Boot ROM version 0.14. • Updated Section 5 “Marking”. 20180301 • LPC8N04 v.1.2 Product data sheet - LPC8N04 v.1.1 Added a remark to Section 8.4.1 “System power architecture”: When running without a battery, energy harvesting is limited to 2 MHz system clock. 20171211 • - Changed title to Cortex-M0+. 20180301 • Product data sheet Product data sheet - LPC8N04 v.1.0 Added text to Section 2 “Features and benefits”: Energy harvesting functionality to power the LPC8N04. 20171012 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 - © NXP Semiconductors N.V. 2018. All rights reserved. 34 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. LPC8N04 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 35 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 16.4 Licenses Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP Semiconductors IC does not include a license to any NXP patent (or other IP right) covering combinations of those products with other products, whether hardware or software. 16.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 36 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 18. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pad allocation table of the HVQFN24 package .5 Pad description of the HVQFN24 package. . . . .6 IC power states. . . . . . . . . . . . . . . . . . . . . . . . .12 State transition events for DEEPSLEEP to ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 State transition events for DEEPPDN to ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Connection of interrupt source to the NVIC . . .14 I2C-bus pin description . . . . . . . . . . . . . . . . . . .18 SPI pin description . . . . . . . . . . . . . . . . . . . . . .18 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .25 Static characteristics . . . . . . . . . . . . . . . . . . . . .26 Temperature sensor characteristics . . . . . . . . .27 Antenna input characteristics . . . . . . . . . . . . . .27 EEPROM characteristics . . . . . . . . . . . . . . . . .27 I/O dynamic characteristics . . . . . . . . . . . . . . .28 I2C-bus dynamic characteristics . . . . . . . . . . .28 Dynamic characteristics of SPI pins in SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .32 Revision history . . . . . . . . . . . . . . . . . . . . . . . .33 LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 37 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 19. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. LPC8N04 block diagram . . . . . . . . . . . . . . . . . . . .4 Pad configuration HVQFN24 . . . . . . . . . . . . . . . . .5 LPC8N04 memory map . . . . . . . . . . . . . . . . . . . . .8 LPC8N04 clock generator block diagram . . . . . . .9 LPC8N04 power architecture. . . . . . . . . . . . . . . . 11 PMU state transition diagram. . . . . . . . . . . . . . . .12 LPC8N04 power-up sequence. . . . . . . . . . . . . . .13 Pin configuration with current source mode. . . . .16 Block diagram of the RFID/NFC interface . . . . . .19 Active current consumption . . . . . . . . . . . . . . . . .27 I2C-bus pins clock timing . . . . . . . . . . . . . . . . . . .29 SPI master timing in SPI mode . . . . . . . . . . . . . .30 SPI slave timing in SPI mode . . . . . . . . . . . . . . .30 HVQFN24 package outline . . . . . . . . . . . . . . . . .31 LPC8N04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.4 — 8 June 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 38 of 39 LPC8N04 NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 20. Contents 1 2 3 4 5 6 7 7.1 7.1.1 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.1.1 8.4.2 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.8 8.8.1 8.8.2 8.8.3 8.9 8.9.1 8.9.2 8.9.3 8.10 8.10.1 8.10.2 8.11 8.11.1 8.11.2 8.12 8.12.1 8.12.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 HVQFN24 package. . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . . 7 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 System configuration . . . . . . . . . . . . . . . . . . . . 8 Clock generation. . . . . . . . . . . . . . . . . . . . . . . . 8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power management . . . . . . . . . . . . . . . . . . . . 10 System power architecture . . . . . . . . . . . . . . . 10 Applying power to the PCB/system with battery for the first time . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Management Unit (PMU). . . . . . . . . . . 13 Nested Vectored Interrupt Controller (NVIC) . 14 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 14 I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 15 PIO0 pin mode . . . . . . . . . . . . . . . . . . . . . . . . 15 PIO0 I2C-bus mode . . . . . . . . . . . . . . . . . . . . 15 PIO0 current source mode . . . . . . . . . . . . . . . 15 Fast general-purpose parallel I/O . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General description . . . . . . . . . . . . . . . . . . . . 17 I2C-bus pin description . . . . . . . . . . . . . . . . . . 18 SPI controller . . . . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General description . . . . . . . . . . . . . . . . . . . . 18 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin detailed descriptions. . . . . . . . . . . . . . . . . .18 RFID/NFC communication unit . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General description . . . . . . . . . . . . . . . . . . . . 19 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 General description . . . . . . . . . . . . . . . . . . . . 20 32-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 General description . . . . . . . . . . . . . . . . . . . . 21 8.13 WatchDog Timer (WDT). . . . . . . . . . . . . . . . . 21 8.13.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.13.2 General description . . . . . . . . . . . . . . . . . . . . 22 8.14 System tick timer . . . . . . . . . . . . . . . . . . . . . . 22 8.14.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.14.2 General description . . . . . . . . . . . . . . . . . . . . 22 8.15 Real-Time Clock (RTC) timer. . . . . . . . . . . . . 22 8.15.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.15.2 General description . . . . . . . . . . . . . . . . . . . . 22 8.16 Temperature sensor . . . . . . . . . . . . . . . . . . . . 23 8.16.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.16.2 General description . . . . . . . . . . . . . . . . . . . . 23 8.17 Serial Wire Debug (SWD) . . . . . . . . . . . . . . . 23 8.18 On-chip flash memory . . . . . . . . . . . . . . . . . . 23 8.18.1 Reading from flash. . . . . . . . . . . . . . . . . . . . . 23 8.18.2 Writing to flash . . . . . . . . . . . . . . . . . . . . . . . . 23 8.18.3 Erasing/programming flash . . . . . . . . . . . . . . 24 8.19 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 24 8.20 On-chip EEPROM . . . . . . . . . . . . . . . . . . . . . 24 8.20.1 Reading from EEPROM. . . . . . . . . . . . . . . . . 24 8.20.2 Writing to EEPROM . . . . . . . . . . . . . . . . . . . . 24 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25 10 Static characteristics . . . . . . . . . . . . . . . . . . . 26 11 Dynamic characteristics. . . . . . . . . . . . . . . . . 28 11.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.2 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.3 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 29 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 31 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 32 14 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 34 16 Legal information . . . . . . . . . . . . . . . . . . . . . . 35 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17 Contact information . . . . . . . . . . . . . . . . . . . . 36 18 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 June 2018 Document identifier: LPC8N04