LS1046ASE8T1A,557

NXP Semiconductors Data Sheet: Technical Data Document Number LS1046A Rev. 4, 06/2020 LS1046A QorIQ LS1046A, LS1026A Data Sheet Features • LS1046A has four cores and LS1026A has two cores • Four 32-bit/64-bit Arm® Cortex®-v8 A72 CPUs – Arranged as a single cluster of four cores sharing a single 2 MB L2 cache – Up to 1.8 GHz operation – Single-threaded cores with 32 KB L1 data cache and 48 KB L1 instruction cache • Hierarchical interconnect fabric – Up to 700 MHz operation • One 32-bit/64-bit DDR4 SDRAM memory controller with ECC and interleaving support – Up to 2.1 GT/s • Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: – Packet parsing, classification, and distribution (FMan) – Queue management for scheduling, packet sequencing, and congestion management (QMan) – Hardware buffer management for buffer allocation and de-allocation (BMan) – Cryptography acceleration (SEC) – IEEE 1588™ support • Additional peripheral interfaces – One Quad Serial Peripheral Interface (QSPI) controller – One Serial Peripheral Interface (SPI) controller – Integrated flash controller (IFC) supporting NAND and NOR flash – Three high-speed USB 3.0 controllers with integrated PHY – One Enhanced Secure Digital Host Controller supporting SD 3.0, eMMC 4.4, and eMMC 4.5 – Four I2C controllers – Two 16550-compliant DUARTs and six low-power UARTs (LPUARTs) – General purpose IO (GPIO), eight Flextimers – One Queue Direct Memory Access Controller (qDMA) – One Enhanced Direct Memory Access Controller (eDMA) – Global programmable interrupt controller (GIC) – Thermal monitoring unit (TMU) • 780 FC-PBGA package, 23 mm x 23 mm • Two RGMII interfaces • Eight SerDes lanes for high-speed peripheral interfaces – Three PCI Express 3.0 controllers – One Serial ATA (SATA 6 Gbit/s) controller – Up to two XFI (10 GbE) interfaces – Up to five SGMII interfaces supporting 1000 Mbps – Up to three SGMII interfaces supporting 2500 Mbps – Up to one QSGMII interface – Supports 10GBase-KR – Supports 1000Base-KX NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Table of Contents 1 Introduction.......................................................................................... 3 3.18 Enhanced secure digital host controller (eSDHC).....................136 2 Pin assignments.................................................................................... 4 3.19 JTAG controller.........................................................................145 2.1 780 BGA ball layout diagrams.................................................. 4 3.20 I2C interface.............................................................................. 148 2.2 Pinout list...................................................................................10 3.21 GPIO interface...........................................................................151 3 Electrical characteristics.......................................................................48 3.22 GIC interface............................................................................. 154 3.1 Overall DC electrical characteristics......................................... 48 3.23 High-speed serial interfaces (HSSI).......................................... 155 3.2 Power sequencing......................................................................55 4 Security fuse processor.........................................................................181 3.3 Power-down requirements.........................................................58 5 Hardware design considerations...........................................................181 3.4 Power characteristics................................................................. 58 5.1 Clock ranges.............................................................................. 181 3.5 I/O power dissipation................................................................ 61 5.2 Minimum platform frequency requirements for high-speed 3.6 Power-on ramp rate................................................................... 64 3.7 Input clocks............................................................................... 64 3.8 RESET initialization..................................................................71 3.9 DDR4 SDRAM controller.........................................................72 3.10 Ethernet interface, Ethernet management interface, IEEE Std 1588........................................................................................... 77 3.11 USB 3.0 interface...................................................................... 103 interfaces....................................................................................182 5.3 Minimum DPAA frequency requirements................................ 183 6 Thermal................................................................................................ 183 6.1 Recommended thermal model...................................................185 6.2 Temperature diode.....................................................................185 6.3 Thermal management information............................................ 185 7 Package information.............................................................................188 3.12 Integrated Flash Controller........................................................106 7.1 Package parameters for the FC-PBGA......................................188 3.13 LPUART interface.....................................................................126 7.2 Mechanical dimensions of the FC-PBGA................................. 188 3.14 DUART interface...................................................................... 127 8 Ordering information............................................................................190 3.15 Flextimer interface.....................................................................129 8.1 Part numbering nomenclature....................................................190 3.16 SPI interface.............................................................................. 131 8.2 Part marking ............................................................................. 191 3.17 QSPI interface........................................................................... 134 9 Revision history....................................................................................191 QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 2 NXP Semiconductors Introduction 1 Introduction The LS1046A is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC) design that extends the reach of the NXP value-performance line of QorIQ communications processors. Featuring power-efficient 64-bit Arm® Cortex®-A72 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.8 GHz. The LS1046A and LS1026A processors are perfectly suited for a range of embedded applications such as enterprise routers and switches, linecard controllers, network attached storage, security appliances, virtual customer premise equipment (vCPE), service providers gateways, and single board computers. This figure shows the block diagram of the chip. Arm® Cortex®-A72 32-bit/64-bit Core 32 KB 32KB KB 32 D-Cache D-Cache D-Cache 32 KB D-Cache 32 KB 32 KB KB 48 I-Cache I-Cache 32 KB I-Cache I-Cache 64-bit DDR4 Memory Controller 2 MB L2 - Cache Secure Boot CCI-400™ Coherency Fabric Trust Zone Power Management SMMUs IFC, QSPI, SPI 8x FlexTimer 3x USB3.0 w/PHY Parse, classify, distribute Watchpoint Cross Trigger 1G 1G 1/2.5/10G Buffer Manager 1G 1G 1/2.5/10G 1/2.5G 1G SATA 3.0 4x I2C, GPIO Real Time Debug PCIe 3.0 2x DUART Frame Manager PCIe 3.0 DMA Security Queue Engine (SEC) Manager PCIe 3.0 SD/SDIO/eMMC Perf Trace Monitor DPAA Hardware 4-Lane 10 GHz SerDes 4-Lane 10 GHz SerDes 6x LPUART Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect, and Debug Networking Elements Figure 1. LS1046A block diagram QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 3 Pin assignments Arm® Cortex®-A72 32-bit/64-bit Core 32 KB 32 KB KB 48 I-Cache I-Cache 32 KB I-Cache I-Cache 32 KB 32KB KB 32 D-Cache D-Cache D-Cache 32 KB D-Cache 64-bit DDR4 Memory Controller 2 MB L2 - Cache Secure Boot CCI-400™ Coherency Fabric Trust Zone Power Management SMMUs IFC, QSPI, SPI Buffer Manager 8x FlexTimer 1G 1/2.5/10G 1G 1/2.5/10G 1G 3x USB3.0 w/PHY 6x LPUART 1G 1G DPAA Hardware SATA 3.0 4x I2C, GPIO PCIe 3.0 Parse, classify, distribute 2x DUART PCIe 3.0 DMA Real Time Debug Frame Manager Security Queue Engine (SEC) Manager PCIe 3.0 SD/SDIO/eMMC Watchpoint Cross Trigger Perf Trace Monitor 1/2.5G 4-Lane 10 GHz SerDes 4-Lane 10 GHz SerDes Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect, and Debug Networking Elements Figure 2. LS1026A block diagram 2 Pin assignments 2.1 780 BGA ball layout diagrams This figure shows the complete view of the LS1046A BGA ball map diagram. Figure 4, Figure 5, Figure 6, and Figure 7 show quadrant views. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 4 NXP Semiconductors Pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A A B B C C D D E E F SEE DETAIL A F SEE DETAIL B G G H H J J K K L L M M N N P P R R T T U U V V W W Y SEE DETAIL C Y SEE DETAIL D AA AA AB AB AC AC AD AD AE AE AF AF AG AG AH AH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DDRC1 IFC DUART I2C eSPI eSDHC Interrupts Battery Backed Trust Trust System Control ASLEEP SYSCLK DDR Clocking RTC Debug DFT JTAG Analog Signals Serdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY 3 Ethernet MI 1 Ethernet MI 2 EC1 EC2 USB DIFF_SYSCLK Power Ground No Connects 24 25 26 27 28 Figure 3. Complete BGA Map for the LS1046A QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 5 Pin assignments 1 A 2 3 4 GND001 USB3_ RX_ P USB3_ RX_ M 5 6 7 8 9 10 11 12 13 14 GND002 USB3_ D_ M USB3_ VBUS IFC_ AD01 IFC_ AD03 IFC_ AD04 IFC_ AD06 IFC_ AD08 IFC_ AD09 IFC_ AD11 A B USB3_ TX_ P USB3_ TX_ M GND004 GND005 USB3_ ID USB3_ D_ P GND006 IFC_ AD00 IFC_ AD02 GND007 IFC_ AD05 IFC_ AD07 GND008 IFC_ AD10 B C GND014 GND015 USB2_ RX_ P USB2_ RX_ M GND016 USB2_ D_ M USB2_ VBUS IFC_ A17 IFC_ A18 IFC_ A20 IFC_ A21 IFC_ A23 IFC_ A25 IFC_ A27 C D USB2_ TX_ P USB2_ TX_ M GND019 GND020 USB2_ ID USB2_ D_ P GND021 IFC_ A16 GND022 IFC_ A19 IFC_ A22 GND023 IFC_ A24 IFC_ A26 D E GND028 GND029 USB1_ RX_ P USB1_ RX_ M GND030 USB1_ D_ M USB1_ VBUS EVT2_B ASLEEP EVT0_B EVT4_B EVT3_B EVT1_B IFC_ TE E F USB1_ TX_ P USB1_ TX_ M GND033 GND034 USB1_ ID USB1_ D_ P GND035 HRESET_ B PORESET_ B RESET_ REQ_B IRQ00 NC_ F12 PROG_ MTR GND036 F G GND040 GND041 USB1_ RESREF USB2_ RESREF USB3_ RESREF USB_ PWRFAULT EVT9_B TH_ VDD GND042 GND043 GND044 TA_BB_ VDD TA_ PROG_ SFP SYSCLK G H UART1_ SOUT UART1_ SIN GND047 GND048 GND049 USB_ DRVVBUS IRQ02 TH_ TPA AVDD_ PLAT AVDD_ CGA2 AVDD_ CGA1 TA_BB_ TMP_ DETECT_B TD1_ CATHODE GND050 H J UART1_ CTS_B UART1_ RTS_B IRQ03 IRQ04 IRQ05 GND057 GND058 GND059 GND060 GND061 GND062 GND063 TD1_ ANODE OVDD1 J K UART2_ SIN GND067 IIC2_ SCL GND068 IRQ06 GND069 USB_ SVDD1 USB_ HVDD1 NC_ K9 NC_ K10 NC_ K11 NC_ K12 GND070 VDD01 K L UART2_ RTS_B UART2_ SOUT IIC2_ SDA IIC3_ SCL IRQ07 GND075 USB_ SVDD2 USB_ HVDD2 NC_ L9 GND076 VDD05 GND077 VDD06 GND078 L M IIC1_ SDA UART2_ CTS_B IIC4_ SCL IIC3_ SDA IRQ08 GND084 USB_ SDVDD1 USB_ SDVDD2 GND085 VDD10 GND086 VDD11 GND087 VDD12 M N IIC1_ SCL GND093 IIC4_ SDA GND094 IRQ09 GND095 DVDD1 GND096 VDD15 GND097 VDD16 GND098 VDD17 GND099 N P SDHC_ DAT0 SDHC_ CMD SDHC_ CLK IRQ10 NC_ P5 GND105 DVDD2 NC_ P8 GND106 VDD21 GND107 VDD22 GND108 VDD23 P 1 2 3 4 5 6 7 8 9 10 11 12 DDRC1 IFC DUART I2C eSPI eSDHC Interrupts Battery Backed Trust Trust System Control ASLEEP SYSCLK DDR Clocking RTC Debug DFT JTAG Analog Signals Serdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY 3 Ethernet MI 1 Ethernet MI 2 EC1 EC2 USB DIFF_SYSCLK Power Ground No Connects 13 14 Figure 4. Detail A QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 6 NXP Semiconductors Pin assignments 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A IFC_ AD13 IFC_ AD14 IFC_ AD15 IFC_ AVD IFC_ CS1_B IFC_ CLK0 GND003 D1_ MDQ05 D1_ MDQ01 D1_ MDQS0_B D1_ MDQS0 D1_ MDQ07 D1_ MDQ03 B IFC_ AD12 GND009 IFC_ NDDQS IFC_ PAR0 GND010 IFC_ CLK1 GND011 D1_ MDQ04 D1_ MDM0 GND012 D1_ MDQ06 GND013 G1VDD01 D1_ MCKE1 B C IFC_ WE0_B IFC_ RB0_B IFC_ CS0_B IFC_ OE_B IFC_ CLE IFC_ CS3_B GND017 D1_ MDQ00 D1_ MDQS1_B D1_ MDQ14 D1_ MDQ20 D1_ MDQ02 GND018 D1_ MCKE0 C D GND024 IFC_ RB1_B IFC_ PAR1 GND025 IFC_ WP0_B IFC_ CS2_B GND026 D1_ MDQ09 D1_ MDQS1 GND027 D1_ MDQ21 D1_ MDQ16 G1VDD02 D1_ MACT_B D E IFC_BCTL IFC_ NDDDR_ CLK IFC_ PERR_B TCK TRST_B TDO GND031 D1_ MDQ08 D1_ MDQ15 D1_ MDQ17 D1_ MDM2 GND032 D1_ MBG0 D1_ MBG1 E F IRQ01 GND037 RTC GND038 TBSCAN_ EN_B TEST_ SEL_B D1_ TPA D1_ MDQ13 D1_ MDQ10 GND039 D1_ MDQS2 D1_ MDQS2_B G1VDD03 D1_ MALERT_B F G CKSTP_ OUT_B CLK_ OUT TDI TMS SENSE VDD SENSE GND GND045 D1_ MDQ12 D1_ MDQ11 D1_ MDQ18 D1_ MDQ22 GND046 D1_ MA12 D1_ MA09 G H GND051 GND052 GND053 GND054 SCAN_ MODE_B TA_ TMP_ DETECT_B GND055 D1_ MDM1 D1_ MDQ29 GND056 D1_ MDQ19 D1_ MDQ23 G1VDD04 D1_ MA11 H J OVDD2 OVDD3 OVDD4 OVDD5 JTAG_BSR_VSELDDRCLK GND064 D1_ MDQ28 GND065 D1_ MDQ25 D1_ MDM3 GND066 D1_ MA07 D1_ MA08 J K GND071 VDD02 GND072 VDD03 GND073 VDD04 GND074 NC_ K22 D1_ MDQ24 D1_ MDQ30 D1_ MDQS3_B D1_ MDQS3 G1VDD05 D1_ MA06 K L VDD07 GND079 VDD08 GND080 VDD09 GND081 NC_ L21 G1VDD06 GND082 D1_ MDQ26 D1_ MDQ31 GND083 D1_ MA05 D1_ MA04 L M GND088 VDD13 GND089 VDD14 GND090 NC_ M20 GND091 G1VDD07 GND092 D1_ MDQ27 D1_ MECC4 D1_ MECC0 G1VDD08 D1_ MA03 M N VDD18 GND100 VDD19 GND101 VDD20 GND102 NC_ N21 G1VDD09 GND103 D1_ MECC5 D1_ MECC1 GND104 D1_ MA01 D1_ MA02 N P GND109 VDD24 GND110 VDD25 GND111 NC_ P20 NC_ P21 G1VDD10 GND112 D1_ MDM8 D1_ MDQS8 D1_ MDQS8_B G1VDD11 D1_ MDIC0 P 22 23 26 27 15 16 17 18 19 20 21 24 25 DDRC1 IFC DUART I2C eSPI eSDHC Interrupts Battery Backed Trust Trust System Control ASLEEP SYSCLK DDR Clocking RTC Debug DFT JTAG Analog Signals Serdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY 3 Ethernet MI 1 Ethernet MI 2 EC1 EC2 USB DIFF_SYSCLK Power Ground No Connects A 28 Figure 5. Detail B QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 7 Pin assignments R T U V W Y AA AB AC AD AE AF 1 2 3 SDHC_ DAT2 SDHC_ DAT1 SPI_ PCS1 NC_ R4 GND113 SDHC_ DAT3 GND123 SPI_ PCS2 GND124 NC_ T5 GND125 SPI_ PCS0 SPI_ SCK SPI_ SIN NC_ U4 NC_ U5 GND135 SPI_ PCS3 GND144 SPI_ SOUT GND145 NC_ V5 GND146 EC1_ RX_ CLK EC1_ RXD3 IRQ11 EC1_ GTX_ CLK NC_ W5 TVDD EC1_ RXD2 GND160 EC1_ TXD3 4 EC1_ TXD2 5 6 7 EVDD OVDD6 8 GND114 9 VDD26 10 GND115 11 12 VDD27 GND116 13 VDD28 14 GND117 R LVDD1 LVDD2 NC_ T8 GND126 GND136 VDD37 VDD32 GND127 VDD33 GND128 VDD34 T GND137 VDD38 GND138 VDD39 GND139 U GND161 SD_ GND01 LVDD3 NC_ W7 NC_ V8 GND147 NC_ W8 NC_ W9 VDD43 GND148 VDD44 GND149 VDD45 V SD_ GND04 SVDD1 VDD49 GND156 SVDD2 SVDD3 SD_ GND05 SD1_ IMP_ CAL_RX SD2_ IMP_ CAL_RX GND162 SD_ GND11 DIFF_ SYSCLK GND168 DIFF_ SYSCLK_B SD_ GND17 W SD_ GND02 SD_ GND03 SD_ GND08 SD1_ IMP_ CAL_TX SD_ GND09 SD1_ REF_ CLK2_P SD_ GND10 NC_ AA10 AVDD_ SD1_ PLL1 GND163 Y EC1_ RXD1 EC1_ RXD0 EC1_ TXD1 GND167 EC1_ RX_ DV GND171 EC1_ TXD0 EC1_ TX_ EN SD1_ PLL2_ TPD AVDD_ SD1_ PLL2 SD_ GND15 SD1_ REF_ CLK2_N SD_ GND16 NC_ AB10 NC_ AB11 GND172 EC2_ RX_ CLK EC2_ RXD3 EC1_ GTX_ CLK125 EC2_ GTX_ CLK SD_ GND20 SD_ GND21 XVDD1 SD_ GND22 XVDD2 SD_ GND23 SD_ GND24 XVDD3 SD2_ PLL1_ TPD XVDD4 SD_ GND29 SD1_ TX0_ P SD_ GND30 SD1_ TX1_ P SD_ GND31 SD1_ TX2_ P SD1_ TX3_ P SD_ GND32 SD2_ REF_ CLK1_P SD_ GND33 EC2_ RXD2 GND176 EC2_ RXD1 EC2_ RX_ DV GND184 AG AA AC EC2_ TXD3 GND177 EC2_ RXD0 EC2_ TXD2 EC2_ TXD1 SD_ GND36 SD1_ TX0_ N SD_ GND37 SD1_ TX1_ N SD_ GND38 SD1_ TX2_ N SD1_ TX3_ N SD_ GND39 SD2_ REF_ CLK1_N SD_ GND40 EMI1_ MDIO EC2_ TXD0 GND181 SD1_ PLL2_ TPA SD_ GND43 SD_ GND44 SD_ GND45 SD_ GND46 SD_ GND47 SD_ GND48 SD1_ PLL1_ TPA SD1_ PLL1_ TPD SD2_ PLL1_ TPA EMI1_ MDC EC2_ TX_ EN EC2_ GTX_ CLK125 SD_ GND54 SD1_ RX0_ P SD_ GND55 SD1_ RX1_ P SD_ GND56 SD1_ RX2_ P SD1_ RX3_ P SD_ GND57 SD1_ REF_ CLK1_P SD_ GND58 SD_ GND62 SD1_ RX1_ N SD_ GND63 SD1_ RX2_ N SD1_ RX3_ N SD_ GND64 SD1_ REF_ CLK1_N SD_ GND65 7 8 9 GND187 AH 1 2 EMI2_ MDIO EMI2_ MDC SD_ GND61 SD1_ RX0_ N 3 4 5 6 10 11 12 DDRC1 IFC DUART I2C eSPI eSDHC Interrupts Battery Backed Trust Trust System Control ASLEEP SYSCLK DDR Clocking RTC Debug DFT JTAG Analog Signals Serdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY 3 Ethernet MI 1 Ethernet MI 2 EC1 EC2 USB DIFF_SYSCLK Power Ground No Connects AB 13 AD AE AF AG AH 14 Figure 6. Detail C QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 8 NXP Semiconductors Pin assignments 15 VDD29 16 GND118 17 VDD30 18 GND119 19 VDD31 20 22 23 AVDD_ D1 G1VDD12 GND121 NC_ T20 GND132 G1VDD13 GND142 NC_ U21 G1VDD14 GND153 G1VDD16 GND120 R GND129 VDD35 GND130 VDD36 GND131 T VDD40 GND140 VDD41 GND141 VDD42 U GND150 VDD46 GND151 VDD47 GND152 VDD48 21 SVDD5 VDD50 GND157 Y AA AB AC AD AE AF AG AH 28 D1_ MCK0_B D1_ MCK0 D1_ MCK1_B D1_ MCK1 D1_ MDIC1 D1_ MECC3 D1_ MECC2 GND134 D1_ MDQ36 D1_ MDQ37 D1_ MDQ33 G1VDD15 D1_ MDQ32 D1_ MDM4 GND155 D1_ MA00 D1_ MPAR D1_ MDQ35 D1_ MDQ38 D1_ MDQS4_B D1_ MDQS4 G1VDD17 D1_ MBA1 D1_ MDQ44 D1_ MDQ39 GND166 D1_ MBA0 D1_ MA10 D1_ MDQ45 D1_ MDQ34 G1VDD18 D1_ MRAS_B D1_ MCS0_B D1_ MWE_B D1_ MCAS_B GND133 GND143 GND154 SVDD8 SD2_ IMP_ CAL_TX GND164 D1_ MDQ52 GND165 GND169 D1_ MDQ48 D1_ MDQ53 GND170 W 27 GND122 GND159 GND158 26 D1_ MECC6 NC_ W21 VDD51 25 D1_ MECC7 V SVDD4 24 SD_ GND06 SD_ GND07 NC_ AA15 AVDD_ SD2_ PLL2 SD_ GND12 SD_ GND13 SD_ GND14 SD2_ PLL2_ TPD AVDD_ SD2_ PLL1 NC_ AB16 SD_ GND18 SD2_ REF_ CLK2_P SD2_ REF_ CLK2_N SD_ GND19 FA_ VL D1_ MDQ51 D1_ MDQ49 D1_ MDQ40 D1_ MDQ41 GND173 SD_ GND25 SD_ GND26 XVDD5 SD_ GND27 SD_ GND28 XVDD6 GND174 D1_ MDQ50 D1_ MDM6 GND175 D1_ MDQS5 D1_ MDQS5_B G1VDD19 SD2_ TX0_ P SD2_ TX1_ P SD_ GND34 SD2_ TX2_ P SD2_ TX3_ P SD_ GND35 FA_ ANALOG_ PIN D1_ MDQ54 D1_ MDQS6_B D1_ MDM5 D1_ MDQ46 GND178 D1_ MA13 D1_ MODT0 SD2_ TX0_ N SD2_ TX1_ N SD_ GND41 SD2_ TX2_ N SD2_ TX3_ N SD_ GND42 GND179 D1_ MDQ55 D1_ MDQS6 GND180 D1_ MDQ42 D1_ MDQ47 G1VDD20 D1_ MCS1_B SD_ GND49 SD_ GND50 SD_ GND51 SD_ GND52 SD_ GND53 SD2_ PLL2_ TPA GND182 D1_ MDQ59 D1_ MDQ62 D1_ MDQ57 D1_ MDQ43 GND183 D1_ MODT1 D1_ MCS3_B SD2_ RX0_ P SD2_ RX1_ P SD_ GND59 SD2_ RX2_ P SD2_ RX3_ P SD_ GND60 FA_ ANALOG_ G_V D1_ MDQ58 D1_ MDQS7_B GND185 D1_ MDQ61 GND186 G1VDD21 D1_ MCS2_B SD2_ RX0_ N SD2_ RX1_ N SD_ GND66 SD2_ RX2_ N SD2_ RX3_ N SD_ GND67 GND188 D1_ MDQ63 D1_ MDQS7 D1_ MDM7 D1_ MDQ56 D1_ MDQ60 15 16 SVDD6 SVDD7 17 18 19 20 21 22 23 24 25 R T U V W Y AA AB AC AD AE AF AG G1VDD22 26 DDRC1 IFC DUART I2C eSPI eSDHC Interrupts Battery Backed Trust Trust System Control ASLEEP SYSCLK DDR Clocking RTC Debug DFT JTAG Analog Signals Serdes 1 Serdes 2 USB3 PHY 1 USB3 PHY 2 USB PHY 3 Ethernet MI 1 Ethernet MI 2 EC1 EC2 USB DIFF_SYSCLK Power Ground No Connects AH 27 28 Figure 7. Detail D QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 9 Pin assignments 2.2 Pinout list This table provides the pinout listing for the LS1046A by bus. Primary functions are bolded in the table. Table 1. Pinout list by bus Signal Signal description Package pin number Pin type Power supply Notes DDR SDRAM Memory Interface 1 D1_MA00 Address V27 O G1VDD --- D1_MA01 Address N27 O G1VDD --- D1_MA02 Address N28 O G1VDD --- D1_MA03 Address M28 O G1VDD --- D1_MA04 Address L28 O G1VDD --- D1_MA05 Address L27 O G1VDD --- D1_MA06 Address K28 O G1VDD --- D1_MA07 Address J27 O G1VDD --- D1_MA08 Address J28 O G1VDD --- D1_MA09 Address G28 O G1VDD --- D1_MA10 Address Y28 O G1VDD --- D1_MA11 Address H28 O G1VDD --- D1_MA12 Address G27 O G1VDD --- D1_MA13 Address AD27 O G1VDD --- D1_MACT_B Activate D28 O G1VDD --- D1_MALERT_B Alert F28 I G1VDD 1, 27 D1_MBA0 Bank Select Y27 O G1VDD --- D1_MBA1 Bank Select W28 O G1VDD --- D1_MBG0 Bank Group E27 O G1VDD --- D1_MBG1 Bank Group E28 O G1VDD --- D1_MCAS_B Column Address Strobe / MA[15] AC28 O G1VDD --- D1_MCK0 Clock R28 O G1VDD --- D1_MCK0_B Clock Complement R27 O G1VDD --- D1_MCK1 Clock T28 O G1VDD --- D1_MCK1_B Clock Complement T27 O G1VDD --- D1_MCKE0 Clock Enable C28 O G1VDD 2 D1_MCKE1 Clock Enable B28 O G1VDD 2 D1_MCS0_B Chip Select AB27 O G1VDD --- D1_MCS1_B Chip Select AE28 O G1VDD --- D1_MCS2_B Chip Select / MCID[0] AG28 O G1VDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 10 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes AF28 O G1VDD --- D1_MCS3_B Chip Select / MCID[1] D1_MDIC0 Driver Impedence Calibration P28 IO G1VDD 3 D1_MDIC1 Driver Impedence Calibration U28 IO G1VDD 3 D1_MDM0 Data Mask B23 IO G1VDD --- D1_MDM1 Data Mask H22 IO G1VDD --- D1_MDM2 Data Mask E25 IO G1VDD --- D1_MDM3 Data Mask J25 IO G1VDD --- D1_MDM4 Data Mask V25 IO G1VDD --- D1_MDM5 Data Mask AD24 IO G1VDD --- D1_MDM6 Data Mask AC23 IO G1VDD --- D1_MDM7 Data Mask AH24 IO G1VDD --- D1_MDM8 Data Mask P24 IO G1VDD --- D1_MDQ00 Data C22 IO G1VDD --- D1_MDQ01 Data A23 IO G1VDD --- D1_MDQ02 Data C26 IO G1VDD --- D1_MDQ03 Data A27 IO G1VDD --- D1_MDQ04 Data B22 IO G1VDD --- D1_MDQ05 Data A22 IO G1VDD --- D1_MDQ06 Data B25 IO G1VDD --- D1_MDQ07 Data A26 IO G1VDD --- D1_MDQ08 Data E22 IO G1VDD --- D1_MDQ09 Data D22 IO G1VDD --- D1_MDQ10 Data F23 IO G1VDD --- D1_MDQ11 Data G23 IO G1VDD --- D1_MDQ12 Data G22 IO G1VDD --- D1_MDQ13 Data F22 IO G1VDD --- D1_MDQ14 Data C24 IO G1VDD --- D1_MDQ15 Data E23 IO G1VDD --- D1_MDQ16 Data D26 IO G1VDD --- D1_MDQ17 Data E24 IO G1VDD --- D1_MDQ18 Data G24 IO G1VDD --- D1_MDQ19 Data H25 IO G1VDD --- D1_MDQ20 Data C25 IO G1VDD --- D1_MDQ21 Data D25 IO G1VDD --- D1_MDQ22 Data G25 IO G1VDD --- D1_MDQ23 Data H26 IO G1VDD --- D1_MDQ24 Data K23 IO G1VDD --- D1_MDQ25 Data J24 IO G1VDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 11 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes D1_MDQ26 Data L24 IO G1VDD --- D1_MDQ27 Data M24 IO G1VDD --- D1_MDQ28 Data J22 IO G1VDD --- D1_MDQ29 Data H23 IO G1VDD --- D1_MDQ30 Data K24 IO G1VDD --- D1_MDQ31 Data L25 IO G1VDD --- D1_MDQ32 Data V24 IO G1VDD --- D1_MDQ33 Data U26 IO G1VDD --- D1_MDQ34 Data AA26 IO G1VDD --- D1_MDQ35 Data W23 IO G1VDD --- D1_MDQ36 Data U24 IO G1VDD --- D1_MDQ37 Data U25 IO G1VDD --- D1_MDQ38 Data W24 IO G1VDD --- D1_MDQ39 Data Y25 IO G1VDD --- D1_MDQ40 Data AB24 IO G1VDD --- D1_MDQ41 Data AB25 IO G1VDD --- D1_MDQ42 Data AE25 IO G1VDD --- D1_MDQ43 Data AF25 IO G1VDD --- D1_MDQ44 Data Y24 IO G1VDD --- D1_MDQ45 Data AA25 IO G1VDD --- D1_MDQ46 Data AD25 IO G1VDD --- D1_MDQ47 Data AE26 IO G1VDD --- D1_MDQ48 Data AA22 IO G1VDD --- D1_MDQ49 Data AB23 IO G1VDD --- D1_MDQ50 Data AC22 IO G1VDD --- D1_MDQ51 Data AB22 IO G1VDD --- D1_MDQ52 Data Y22 IO G1VDD --- D1_MDQ53 Data AA23 IO G1VDD --- D1_MDQ54 Data AD22 IO G1VDD --- D1_MDQ55 Data AE22 IO G1VDD --- D1_MDQ56 Data AH25 IO G1VDD --- D1_MDQ57 Data AF24 IO G1VDD --- D1_MDQ58 Data AG22 IO G1VDD --- D1_MDQ59 Data AF22 IO G1VDD --- D1_MDQ60 Data AH26 IO G1VDD --- D1_MDQ61 Data AG25 IO G1VDD --- D1_MDQ62 Data AF23 IO G1VDD --- D1_MDQ63 Data AH22 IO G1VDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 12 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes D1_MDQS0 Data Strobe A25 IO G1VDD --- D1_MDQS0_B Data Strobe A24 IO G1VDD --- D1_MDQS1 Data Strobe D23 IO G1VDD --- D1_MDQS1_B Data Strobe C23 IO G1VDD --- D1_MDQS2 Data Strobe F25 IO G1VDD --- D1_MDQS2_B Data Strobe F26 IO G1VDD --- D1_MDQS3 Data Strobe K26 IO G1VDD --- D1_MDQS3_B Data Strobe K25 IO G1VDD --- D1_MDQS4 Data Strobe W26 IO G1VDD --- D1_MDQS4_B Data Strobe W25 IO G1VDD --- D1_MDQS5 Data Strobe AC25 IO G1VDD --- D1_MDQS5_B Data Strobe AC26 IO G1VDD --- D1_MDQS6 Data Strobe AE23 IO G1VDD --- D1_MDQS6_B Data Strobe AD23 IO G1VDD --- D1_MDQS7 Data Strobe AH23 IO G1VDD --- D1_MDQS7_B Data Strobe AG23 IO G1VDD --- D1_MDQS8 Data Strobe P25 IO G1VDD --- D1_MDQS8_B Data Strobe P26 IO G1VDD --- D1_MECC0 Error Correcting Code M26 IO G1VDD --- D1_MECC1 Error Correcting Code N25 IO G1VDD --- D1_MECC2 Error Correcting Code T25 IO G1VDD --- D1_MECC3 Error Correcting Code T24 IO G1VDD --- D1_MECC4 Error Correcting Code M25 IO G1VDD --- D1_MECC5 Error Correcting Code N24 IO G1VDD --- D1_MECC6 Error Correcting Code R25 IO G1VDD --- D1_MECC7 Error Correcting Code R24 IO G1VDD --- D1_MODT0 On Die Termination AD28 O G1VDD 2 D1_MODT1 On Die Termination / MCID[2] AF27 O G1VDD 2 D1_MPAR Address Parity Out V28 O G1VDD --- D1_MRAS_B Row Address Strobe / MA[16] AA28 O G1VDD --- D1_MWE_B Write Enable / MA[14] AB28 O G1VDD --- Integrated Flash Controller IFC_A16/QSPI_A_CS0 IFC Address D8 O OVDD 1, 5 IFC_A17/QSPI_A_CS1 IFC Address C8 O OVDD 1, 5 IFC_A18/QSPI_A_SCK IFC Address C9 O OVDD 1, 5 IFC_A19/QSPI_B_CS0 IFC Address D10 O OVDD 1, 5 IFC_A20/QSPI_B_CS1 IFC Address C10 O OVDD 1, 5 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 13 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes IFC_A21/QSPI_B_SCK/ cfg_dram_type IFC Address C11 O OVDD 1, 15 IFC_A22/QSPI_A_DATA0/ IFC_WP1_B IFC Address D11 O OVDD 1 IFC_A23/QSPI_A_DATA1/ IFC_WP2_B IFC Address C12 O OVDD 1 IFC_A24/QSPI_A_DATA2/ IFC_WP3_B IFC Address D13 O OVDD 1 IFC_A25/GPIO2_25/ QSPI_A_DATA3/FTM5_CH0/ IFC_CS4_B/IFC_RB2_B IFC Address C13 O OVDD 1 IFC_A26/GPIO2_26/ FTM5_CH1/IFC_CS5_B/ IFC_RB3_B IFC Address D14 O OVDD 1 IFC_A27/GPIO2_27/ FTM5_EXTCLK/IFC_CS6_B IFC Address C14 O OVDD 1 IFC_AD00/cfg_gpinput0 IFC Address / Data B8 IO OVDD 4 IFC_AD01/cfg_gpinput1 IFC Address / Data A8 IO OVDD 4 IFC_AD02/cfg_gpinput2 IFC Address / Data B9 IO OVDD 4 IFC_AD03/cfg_gpinput3 IFC Address / Data A9 IO OVDD 4 IFC_AD04/cfg_gpinput4 IFC Address / Data A10 IO OVDD 4 IFC_AD05/cfg_gpinput5 IFC Address / Data B11 IO OVDD 4 IFC_AD06/cfg_gpinput6 IFC Address / Data A11 IO OVDD 4 IFC_AD07/cfg_gpinput7 IFC Address / Data B12 IO OVDD 4 IFC_AD08/cfg_rcw_src0 IFC Address / Data A12 IO OVDD 4 IFC_AD09/cfg_rcw_src1 IFC Address / Data A13 IO OVDD 4 IFC_AD10/cfg_rcw_src2 IFC Address / Data B14 IO OVDD 4 IFC_AD11/cfg_rcw_src3 IFC Address / Data A14 IO OVDD 4 IFC_AD12/cfg_rcw_src4 IFC Address / Data B15 IO OVDD 4 IFC_AD13/cfg_rcw_src5 IFC Address / Data A15 IO OVDD 4 IFC_AD14/cfg_rcw_src6 IFC Address / Data A16 IO OVDD 4 IFC_AD15/cfg_rcw_src7 IFC Address / Data A17 IO OVDD 4 IFC_AVD IFC Address Valid A18 O OVDD 1, 5 IFC_BCTL IFC Buffer control E15 O OVDD --- IFC_CLE/cfg_rcw_src8 IFC Command Latch Enable / Write Enable C19 O OVDD 1, 4 IFC_CLK0 IFC Clock A20 O OVDD --- IFC_CLK1 IFC Clock B20 O OVDD --- IFC_CS0_B IFC Chip Select C17 O OVDD 1, 6 IFC_CS1_B/GPIO2_10/ FTM7_CH0 IFC Chip Select A19 O OVDD 1, 6 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 14 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes IFC_CS2_B/GPIO2_11/ FTM7_CH1 IFC Chip Select D20 O OVDD 1, 6 IFC_CS3_B/GPIO2_12/ QSPI_B_DATA3/ FTM7_EXTCLK IFC Chip Select C20 O OVDD 1, 6 IFC_CS4_B/IFC_A25/ GPIO2_25/QSPI_A_DATA3/ FTM5_CH0/IFC_RB2_B IFC Chip Select C13 O OVDD 1 IFC_CS5_B/IFC_A26/ GPIO2_26/FTM5_CH1/ IFC_RB3_B IFC Chip Select D14 O OVDD 1 IFC_CS6_B/IFC_A27/ GPIO2_27/FTM5_EXTCLK IFC Chip Select C14 O OVDD 1 IFC_NDDDR_CLK IFC NAND DDR Clock E16 O OVDD --- IFC_NDDQS IFC DQS Strobe B17 IO OVDD --- IFC_OE_B/cfg_eng_use1 IFC Output Enable C18 O OVDD 1, 4 IFC_PAR0/GPIO2_13/ QSPI_B_DATA0/FTM6_CH0 IFC Address & Data Parity B18 IO OVDD --- IFC_PAR1/GPIO2_14/ QSPI_B_DATA1/FTM6_CH1 IFC Address & Data Parity D17 IO OVDD --- IFC_PERR_B/GPIO2_15/ QSPI_B_DATA2/ FTM6_EXTCLK IFC Parity Error E17 I OVDD 1 IFC_RB0_B IFC Ready / Busy CS0 C16 I OVDD 6 IFC_RB1_B IFC Ready / Busy CS1 D16 I OVDD 6 IFC_RB2_B/IFC_A25/ GPIO2_25/QSPI_A_DATA3/ FTM5_CH0/IFC_CS4_B IFC Ready/Busy CS 2 C13 I OVDD 1 IFC_RB3_B/IFC_A26/ GPIO2_26/FTM5_CH1/ IFC_CS5_B IFC Ready/Busy CS 3 D14 I OVDD 1 IFC_TE/cfg_ifc_te IFC External Transceiver Enable E14 O OVDD 1, 4 IFC_WE0_B/cfg_eng_use0 IFC Write Enable C15 O OVDD 1, 4, 26 IFC_WP0_B/cfg_eng_use2 IFC Write Protect D19 O OVDD 1, 4 IFC_WP1_B/IFC_A22/ QSPI_A_DATA0 IFC Write Protect D11 O OVDD 1 IFC_WP2_B/IFC_A23/ QSPI_A_DATA1 IFC Write Protect C12 O OVDD 1 IFC_WP3_B/IFC_A24/ QSPI_A_DATA2 IFC Write Protect D13 O OVDD 1 DUART Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 15 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes UART1_CTS_B/GPIO1_21/ UART3_SIN/FTM4_CH4/ LPUART2_SIN Clear To Send J1 I DVDD 1 UART1_RTS_B/GPIO1_19/ UART3_SOUT/ LPUART2_SOUT/FTM4_CH2 Ready to Send J2 O DVDD 1 UART1_SIN/GPIO1_17 Receive Data H2 I DVDD 1 UART1_SOUT/GPIO1_15 Transmit Data H1 O DVDD 1 UART2_CTS_B/GPIO1_22/ UART4_SIN/FTM4_CH5/ LPUART1_CTS_B/ LPUART4_SIN Clear To Send M2 I DVDD 1 UART2_RTS_B/GPIO1_20/ Ready to Send UART4_SOUT/ LPUART4_SOUT/FTM4_CH3/ LPUART1_RTS_B L1 O DVDD 1 UART2_SIN/GPIO1_18/ FTM4_CH1/LPUART1_SIN Receive Data K1 I DVDD 1 UART2_SOUT/GPIO1_16/ LPUART1_SOUT/FTM4_CH0 Transmit Data L2 O DVDD 1 UART3_SIN/UART1_CTS_B/ GPIO1_21/FTM4_CH4/ LPUART2_SIN Receive Data J1 I DVDD 1 UART3_SOUT/ UART1_RTS_B/GPIO1_19/ LPUART2_SOUT/FTM4_CH2 Transmit Data J2 O DVDD 1 UART4_SIN/UART2_CTS_B/ GPIO1_22/FTM4_CH5/ LPUART1_CTS_B/ LPUART4_SIN Receive Data M2 I DVDD 1 UART4_SOUT/ Transmit Data UART2_RTS_B/GPIO1_20/ LPUART4_SOUT/FTM4_CH3/ LPUART1_RTS_B L1 O DVDD 1 I2C IIC1_SCL Serial Clock (supports PBL) N1 IO DVDD 7, 8 IIC1_SDA Serial Data (supports PBL) M1 IO DVDD 7, 8 IIC2_SCL/GPIO4_2/ Serial Clock SDHC_CD_B/FTM3_QD_PHA K3 IO DVDD 7, 8 IIC2_SDA/GPIO4_3/ SDHC_WP/FTM3_QD_PHB L3 IO DVDD 7, 8 IIC3_SCL/GPIO4_10/EVT5_B/ Serial Clock USB2_DRVVBUS/FTM8_CH0 L4 IO DVDD 7, 8 IIC3_SDA/GPIO4_11/EVT6_B/ Serial Data USB2_PWRFAULT/ FTM8_CH1 M4 IO DVDD 7, 8 Serial Data Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 16 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes IIC4_SCL/GPIO4_12/EVT7_B/ Serial Clock USB3_DRVVBUS/ FTM3_FAULT M3 IO DVDD 7, 8 IIC4_SDA/GPIO4_13/EVT8_B/ Serial Data USB3_PWRFAULT/ FTM3_EXTCLK N3 IO DVDD 7, 8 SPI Interface SPI_PCS0/GPIO2_00/ SDHC_DAT4/SDHC_VS SPI Chip Select U1 O OVDD 1 SPI_PCS1/GPIO2_01/ SDHC_DAT5/ SDHC_CMD_DIR SPI Chip Select R3 O OVDD 1 SPI_PCS2/GPIO2_02/ SDHC_DAT6/ SDHC_DAT0_DIR SPI Chip Select T3 O OVDD 1 SPI_PCS3/GPIO2_03/ SDHC_DAT7/ SDHC_DAT123_DIR SPI Chip Select V1 O OVDD 1 SPI_SCK SPI Clock U2 O OVDD 1 SPI_SIN/ SDHC_CLK_SYNC_IN Master In Slave Out U3 I OVDD 1 SPI_SOUT/ SDHC_CLK_SYNC_OUT Master Out Slave In V3 IO OVDD --- eSDHC SDHC_CD_B/IIC2_SCL/ GPIO4_2/FTM3_QD_PHA Command K3 I DVDD 1 SDHC_CLK/GPIO2_09/ LPUART3_CTS_B/ LPUART6_SIN/ FTM4_QD_PHB Host to Card Clock P3 O EVDD 1 SDHC_CLK_SYNC_IN/ SPI_SIN IN U3 I OVDD 1 SDHC_CLK_SYNC_OUT/ SPI_SOUT OUT V3 O OVDD 1 SDHC_CMD/GPIO2_04/ LPUART3_SOUT/FTM4_CH6 Command/Response P2 IO EVDD --- SDHC_CMD_DIR/SPI_PCS1/ GPIO2_01/SDHC_DAT5 DIR R3 O OVDD 1 SDHC_DAT0/GPIO2_05/ FTM4_CH7/LPUART3_SIN Data P1 IO EVDD --- SDHC_DAT0_DIR/SPI_PCS2/ DIR GPIO2_02/SDHC_DAT6 T3 O OVDD 1 SDHC_DAT1/GPIO2_06/ LPUART5_SOUT/ R2 IO EVDD --- Data Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 17 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes FTM4_FAULT/ LPUART2_RTS_B SDHC_DAT123_DIR/ SPI_PCS3/GPIO2_03/ SDHC_DAT7 DIR V1 O OVDD 1 SDHC_DAT2/GPIO2_07/ LPUART2_CTS_B/ LPUART5_SIN/ FTM4_EXTCLK Data R1 IO EVDD --- SDHC_DAT3/GPIO2_08/ LPUART6_SOUT/ FTM4_QD_PHA/ LPUART3_RTS_B Data T1 IO EVDD --- SDHC_DAT4/SPI_PCS0/ GPIO2_00/SDHC_VS Data U1 IO OVDD --- SDHC_DAT5/SPI_PCS1/ GPIO2_01/SDHC_CMD_DIR Data R3 IO OVDD --- SDHC_DAT6/SPI_PCS2/ GPIO2_02/SDHC_DAT0_DIR Data T3 IO OVDD --- SDHC_DAT7/SPI_PCS3/ GPIO2_03/ SDHC_DAT123_DIR Data V1 IO OVDD --- SDHC_VS/SPI_PCS0/ GPIO2_00/SDHC_DAT4 VS U1 O OVDD 1 SDHC_WP/IIC2_SDA/ GPIO4_3/FTM3_QD_PHB Write Protect L3 I DVDD 1 Programmable Interrupt Controller EVT9_B Event 9 G7 IO OVDD 1, 6, 7 IRQ00 External Interrupt F11 I OVDD 1 IRQ01 External Interrupt F15 I OVDD 1 IRQ02 External Interrupt H7 I OVDD 1 IRQ03/GPIO1_23/FTM3_CH7 External Interrupt J3 I DVDD 1 IRQ04/GPIO1_24/FTM3_CH0 External Interrupt J4 I DVDD 1 IRQ05/GPIO1_25/FTM3_CH1 External Interrupt J5 I DVDD 1 IRQ06/GPIO1_26/FTM3_CH2 External Interrupt K5 I DVDD 1 IRQ07/GPIO1_27/FTM3_CH3 External Interrupt L5 I DVDD 1 IRQ08/GPIO1_28/FTM3_CH4 External Interrupt M5 I DVDD 1 IRQ09/GPIO1_29/FTM3_CH5 External Interrupt N5 I DVDD 1 IRQ10/GPIO1_30/FTM3_CH6 External Interrupt P4 I DVDD 1 IRQ11/GPIO1_31 External Interrupt W3 I LVDD 1 I TA_BB_VDD --- Battery Backed Trust TA_BB_TMP_DETECT_B Battery Backed Tamper Detect H12 Trust Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 18 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal TA_TMP_DETECT_B Signal description Package pin number Pin type H20 I OVDD 1 Tamper Detect Power supply Notes System Control HRESET_B Hard Reset F8 IO OVDD 7, 28 PORESET_B Power On Reset F9 I OVDD --- RESET_REQ_B Reset Request F10 O OVDD 1, 5 E9 O OVDD 1 G14 I OVDD 22 J20 I OVDD 22 F17 I OVDD 1 Power Management ASLEEP/GPIO1_13 Asleep SYSCLK SYSCLK System Clock DDR Clocking DDRCLK DDR Controller Clock RTC RTC/GPIO1_14 Real Time Clock Debug CKSTP_OUT_B RSVD G15 - OVDD 6, 7 CLK_OUT Clock Out G16 O OVDD --- EVT0_B Event 0 E10 IO OVDD 9 EVT1_B Event 1 E13 IO OVDD --- EVT2_B Event 2 E8 IO OVDD --- EVT3_B Event 3 E12 IO OVDD --- EVT4_B Event 4 E11 IO OVDD --- EVT5_B/IIC3_SCL/GPIO4_10/ Event 5 USB2_DRVVBUS/FTM8_CH0 L4 IO DVDD --- EVT6_B/IIC3_SDA/GPIO4_11/ Event 6 USB2_PWRFAULT/ FTM8_CH1 M4 IO DVDD --- EVT7_B/IIC4_SCL/GPIO4_12/ Event 7 USB3_DRVVBUS/ FTM3_FAULT M3 IO DVDD --- EVT8_B/IIC4_SDA/GPIO4_13/ Event 8 USB3_PWRFAULT/ FTM3_EXTCLK N3 IO DVDD --- DFT JTAG_BSR_VSEL An IEEE 1149.1 JTAG Compliance Enable pin. 0: normal operation. 1: To be compliant to the 1149.1 specification for boundary scan functions. The JTAG compliant state is documented in the BSDL. J19 I OVDD 24, 25 SCAN_MODE_B Reserved H19 I OVDD 10, 25 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 19 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes TBSCAN_EN_B An IEEE 1149.1 JTAG Compliance Enable pin. 0: To be compliant to the 1149.1 specification for boundary scan functions. The JTAG compliant state is documented in the BSDL. 1: JTAG connects to DAP controller for the Arm core debug. F19 I OVDD 20, 25 TEST_SEL_B Reserved F20 I OVDD 19, 25 TCK Test Clock E18 I OVDD --- TDI Test Data In G17 I OVDD 9 TDO Test Data Out E20 O OVDD 2 TMS Test Mode Select G18 I OVDD 9 TRST_B Test Reset E19 I OVDD 9 F21 IO 12 JTAG Analog Signals D1_TPA DDR Controller 1 Test Point Analog FA_ANALOG_G_V Reserved AG21 IO 15 FA_ANALOG_PIN Reserved AD21 IO 15 TD1_ANODE Thermal diode anode J13 IO 17 TD1_CATHODE Thermal diode cathode H13 IO 17 TH_TPA Thermal Test Point Analog H8 - - 12 SerDes 1 SD1_IMP_CAL_RX SerDes Receive Impedence Calibration Y11 I SVDD 11 SD1_IMP_CAL_TX SerDes Transmit Impedance Calibration AA6 I XVDD 16 SD1_PLL1_TPA SerDes PLL 1 Test Point Analog AF12 O AVDD_SD1_PLL1 12 SD1_PLL1_TPD SerDes Test Point Digital AF13 O XVDD 12 SD1_PLL2_TPA SerDes PLL 2 Test Point Analog AF5 O AVDD_SD1_PLL2 12 SD1_PLL2_TPD SerDes Test Point Digital AB5 O XVDD 12 SD1_REF_CLK1_N SerDes PLL 1 Reference Clock Complement AH13 I SVDD --- SD1_REF_CLK1_P SerDes PLL 1 Reference Clock AG13 I SVDD --- SD1_REF_CLK2_N SerDes PLL 2 Reference Clock Complement AB8 I SVDD --- SD1_REF_CLK2_P SerDes PLL 2 Reference Clock AA8 I SVDD --- SD1_RX0_N SerDes Receive Data (negative) AH6 I SVDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 20 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes SD1_RX0_P SerDes Receive Data (positive) AG6 I SVDD --- SD1_RX1_N SerDes Receive Data (negative) AH8 I SVDD --- SD1_RX1_P SerDes Receive Data (positive) AG8 I SVDD --- SD1_RX2_N SerDes Receive Data (negative) AH10 I SVDD --- SD1_RX2_P SerDes Receive Data (positive) AG10 I SVDD --- SD1_RX3_N SerDes Receive Data (negative) AH11 I SVDD --- SD1_RX3_P SerDes Receive Data (positive) AG11 I SVDD --- SD1_TX0_N SerDes Transmit Data (negative) AE6 O XVDD --- SD1_TX0_P SerDes Transmit Data (positive) AD6 O XVDD --- SD1_TX1_N SerDes Transmit Data (negative) AE8 O XVDD --- SD1_TX1_P SerDes Transmit Data (positive) AD8 O XVDD --- SD1_TX2_N SerDes Transmit Data (negative) AE10 O XVDD --- SD1_TX2_P SerDes Transmit Data (positive) AD10 O XVDD --- SD1_TX3_N SerDes Transmit Data (negative) AE11 O XVDD --- SD1_TX3_P SerDes Transmit Data (positive) AD11 O XVDD --- SerDes 2 SD2_IMP_CAL_RX SerDes Receive Impedence Calibration Y12 I SVDD 11 SD2_IMP_CAL_TX SerDes Transmit Impedance Calibration Y20 I XVDD 16 SD2_PLL1_TPA SerDes PLL 1 Test Point Analog AF14 O AVDD_SD2_PLL1 12 SD2_PLL1_TPD SerDes Test Point Digital AC13 O XVDD 12 SD2_PLL2_TPA SerDes PLL 2 Test Point Analog AF20 O AVDD_SD2_PLL2 12 SD2_PLL2_TPD SerDes Test Point Digital AA20 O XVDD 12 SD2_REF_CLK1_N SerDes PLL 1 Reference Clock Complement AE13 I SVDD --- SD2_REF_CLK1_P SerDes PLL 1 Reference Clock AD13 I SVDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 21 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes SD2_REF_CLK2_N SerDes PLL 2 Reference Clock Complement AB19 I SVDD --- SD2_REF_CLK2_P SerDes PLL 2 Reference Clock AB18 I SVDD --- SD2_RX0_N SerDes Receive Data (negative) AH15 I SVDD --- SD2_RX0_P SerDes Receive Data (positive) AG15 I SVDD --- SD2_RX1_N SerDes Receive Data (negative) AH16 I SVDD --- SD2_RX1_P SerDes Receive Data (positive) AG16 I SVDD --- SD2_RX2_N SerDes Receive Data (negative) AH18 I SVDD --- SD2_RX2_P SerDes Receive Data (positive) AG18 I SVDD --- SD2_RX3_N SerDes Receive Data (negative) AH19 I SVDD --- SD2_RX3_P SerDes Receive Data (positive) AG19 I SVDD --- SD2_TX0_N SerDes Transmit Data (negative) AE15 O XVDD --- SD2_TX0_P SerDes Transmit Data (positive) AD15 O XVDD --- SD2_TX1_N SerDes Transmit Data (negative) AE16 O XVDD --- SD2_TX1_P SerDes Transmit Data (positive) AD16 O XVDD --- SD2_TX2_N SerDes Transmit Data (negative) AE18 O XVDD --- SD2_TX2_P SerDes Transmit Data (positive) AD18 O XVDD --- SD2_TX3_N SerDes Transmit Data (negative) AE19 O XVDD --- SD2_TX3_P SerDes Transmit Data (positive) AD19 O XVDD --- USB3 PHY #1 USB1_D_M USB PHY HS Data (-) E6 IO - --- USB1_D_P USB PHY HS Data (+) F6 IO - --- USB1_ID USB PHY ID Detect F5 I - --- USB1_RESREF USB PHY Impedance Calibration G3 IO - 18 USB1_RX_M USB PHY SS Receive Data (-) E4 I - --- USB1_RX_P USB PHY SS Receive Data (+) E3 I - --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 22 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes USB1_TX_M USB PHY SS Transmit Data (-) F2 O - --- USB1_TX_P USB PHY SS Transmit Data (+) F1 O - --- USB1_VBUS USB PHY VBUS E7 I - --- USB3 PHY #2 USB2_D_M USB PHY HS Data (-) C6 IO - --- USB2_D_P USB PHY HS Data (+) D6 IO - --- USB2_ID USB PHY ID Detect D5 I - --- USB2_RESREF USB PHY Impedance Calibration G4 IO - 18 USB2_RX_M USB PHY SS Receive Data (-) C4 I - --- USB2_RX_P USB PHY SS Receive Data (+) C3 I - --- USB2_TX_M USB PHY SS Transmit Data (-) D2 O - --- USB2_TX_P USB PHY SS Transmit Data (+) D1 O - --- USB2_VBUS USB PHY VBUS C7 I - --- USB PHY #3 USB3_D_M USB PHY HS Data (-) A6 IO - --- USB3_D_P USB PHY HS Data (+) B6 IO - --- USB3_ID USB PHY ID Detect B5 I - --- USB3_RESREF USB PHY Impedance Calibration G5 IO - 18 USB3_RX_M USB PHY SS Receive Data (-) A4 I - --- USB3_RX_P USB PHY SS Receive Data (+) A3 I - --- USB3_TX_M USB PHY SS Transmit Data (-) B2 O - --- USB3_TX_P USB PHY SS Transmit Data (+) B1 O - --- USB3_VBUS USB PHY VBUS A7 I - --- Ethernet Management Interface 1 EMI1_MDC/GPIO3_00 Management Data Clock AG2 O LVDD 1 EMI1_MDIO/GPIO3_01 Management Data In/Out AF2 IO LVDD --- Ethernet Management Interface 2 EMI2_MDC/GPIO4_00 Management Data Clock AH4 O TVDD 1 EMI2_MDIO/GPIO4_01 Management Data In/Out AH3 IO TVDD --- W4 O LVDD 1 EC1_GTX_CLK125/GPIO3_08 Reference Clock AC3 I LVDD 1 EC1_RXD0/GPIO3_12/ FTM1_CH0 AA2 I LVDD 1 Ethernet Controller 1 EC1_GTX_CLK/GPIO3_07/ FTM1_EXTCLK Transmit Clock Out Receive Data Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 23 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes EC1_RXD1/GPIO3_11/ FTM1_CH1 Receive Data AA1 I LVDD 1 EC1_RXD2/GPIO3_10/ FTM1_CH6 Receive Data Y1 I LVDD 1 EC1_RXD3/GPIO3_09/ FTM1_CH4 Receive Data W2 I LVDD 1 EC1_RX_CLK/GPIO3_13/ FTM1_QD_PHA Receive Clock W1 I LVDD 1 EC1_RX_DV/GPIO3_14/ FTM1_QD_PHB Receive Data Valid AB1 I LVDD 1 EC1_TXD0/GPIO3_05/ FTM1_CH2 Transmit Data AB3 O LVDD 1 EC1_TXD1/GPIO3_04/ FTM1_CH3 Transmit Data AA3 O LVDD 1 EC1_TXD2/GPIO3_03/ FTM1_CH7 Transmit Data Y4 O LVDD 1 EC1_TXD3/GPIO3_02/ FTM1_CH5 Transmit Data Y3 O LVDD 1 EC1_TX_EN/GPIO3_06/ FTM1_FAULT Transmit Enable AB4 O LVDD 1, 14 AC4 O LVDD 1 EC2_GTX_CLK125/GPIO3_21 Reference Clock AG4 I LVDD 1 EC2_RXD0/GPIO3_25/ TSEC_1588_TRIG_IN2/ FTM2_CH0 Receive Data AE2 I LVDD 1 EC2_RXD1/GPIO3_24/ TSEC_1588_PULSE_OUT1/ FTM2_CH1 Receive Data AE1 I LVDD 1 EC2_RXD2/GPIO3_23/ FTM2_CH6 Receive Data AD1 I LVDD 1 EC2_RXD3/GPIO3_22/ FTM2_CH4 Receive Data AC2 I LVDD 1 EC2_RX_CLK/GPIO3_26/ TSEC_1588_CLK_IN/ FTM2_QD_PHA Receive Clock AC1 I LVDD 1 EC2_RX_DV/GPIO3_27/ TSEC_1588_TRIG_IN1/ FTM2_QD_PHB Receive Data Valid AF1 I LVDD 1 EC2_TXD0/GPIO3_18/ TSEC_1588_PULSE_OUT2/ FTM2_CH2 Transmit Data AF3 O LVDD 1 Ethernet Controller 2 EC2_GTX_CLK/GPIO3_20/ FTM2_EXTCLK Transmit Clock Out Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 24 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes EC2_TXD1/GPIO3_17/ TSEC_1588_CLK_OUT/ FTM2_CH3 Transmit Data AE4 O LVDD 1 EC2_TXD2/GPIO3_16/ TSEC_1588_ALARM_OUT1/ FTM2_CH7 Transmit Data AE3 O LVDD 1 EC2_TXD3/GPIO3_15/ TSEC_1588_ALARM_OUT2/ FTM2_CH5 Transmit Data AD3 O LVDD 1 EC2_TX_EN/GPIO3_19/ FTM2_FAULT Transmit Enable AG3 O LVDD 1, 14 DRV VBus L4 O DVDD 1 USB2_PWRFAULT/IIC3_SDA/ PWR Fault GPIO4_11/EVT6_B/ FTM8_CH1 M4 I DVDD 1 USB3_DRVVBUS/IIC4_SCL/ GPIO4_12/EVT7_B/ FTM3_FAULT M3 O DVDD 1 USB3_PWRFAULT/IIC4_SDA/ PWR Fault GPIO4_13/EVT8_B/ FTM3_EXTCLK N3 I DVDD 1 USB_DRVVBUS/GPIO4_29 USB_DRVVBUS H6 O DVDD 1 USB_PWRFAULT/GPIO4_30 USB_PWRFAULT G6 I DVDD 1 USB USB2_DRVVBUS/IIC3_SCL/ GPIO4_10/EVT5_B/ FTM8_CH0 DRV Bus DSYSCLK DIFF_SYSCLK Single Source System Clock Differential (positive) AA13 I OVDD 21 DIFF_SYSCLK_B Single Source System Clock Differential (negative) AB13 I OVDD 21 Power-On-Reset Configuration cfg_dram_type/IFC_A21/ QSPI_B_SCK Power-on-Reset Configuration C11 I OVDD 1, 15 cfg_eng_use0/IFC_WE0_B Power-on-Reset Configuration C15 I OVDD 1, 4, 26 cfg_eng_use1/IFC_OE_B Power-on-Reset Configuration C18 I OVDD 1, 4 cfg_eng_use2/IFC_WP0_B Power-on-Reset Configuration D19 I OVDD 1, 4 cfg_gpinput0/IFC_AD00 Power-on-Reset Configuration B8 I OVDD 1, 4 cfg_gpinput1/IFC_AD01 Power-on-Reset Configuration A8 I OVDD 1, 4 cfg_gpinput2/IFC_AD02 Power-on-Reset Configuration B9 I OVDD 1, 4 cfg_gpinput3/IFC_AD03 Power-on-Reset Configuration A9 I OVDD 1, 4 cfg_gpinput4/IFC_AD04 Power-on-Reset Configuration A10 I OVDD 1, 4 cfg_gpinput5/IFC_AD05 Power-on-Reset Configuration B11 I OVDD 1, 4 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 25 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes cfg_gpinput6/IFC_AD06 Power-on-Reset Configuration A11 I OVDD 1, 4 cfg_gpinput7/IFC_AD07 Power-on-Reset Configuration B12 I OVDD 1, 4 cfg_ifc_te/IFC_TE Power-on-Reset Configuration E14 I OVDD 1, 4 cfg_rcw_src0/IFC_AD08 Power-on-Reset Configuration A12 I OVDD 1, 4 cfg_rcw_src1/IFC_AD09 Power-on-Reset Configuration A13 I OVDD 1, 4 cfg_rcw_src2/IFC_AD10 Power-on-Reset Configuration B14 I OVDD 1, 4 cfg_rcw_src3/IFC_AD11 Power-on-Reset Configuration A14 I OVDD 1, 4 cfg_rcw_src4/IFC_AD12 Power-on-Reset Configuration B15 I OVDD 1, 4 cfg_rcw_src5/IFC_AD13 Power-on-Reset Configuration A15 I OVDD 1, 4 cfg_rcw_src6/IFC_AD14 Power-on-Reset Configuration A16 I OVDD 1, 4 cfg_rcw_src7/IFC_AD15 Power-on-Reset Configuration A17 I OVDD 1, 4 cfg_rcw_src8/IFC_CLE Power-on-Reset Configuration C19 I OVDD 1, 4 QSPI QSPI_A_CS0/IFC_A16 Chip Select D8 O OVDD 1, 5 QSPI_A_CS1/IFC_A17 CS1 C8 O OVDD 1, 5 QSPI_A_DATA0/IFC_A22/ IFC_WP1_B DATA0 D11 IO OVDD --- QSPI_A_DATA1/IFC_A23/ IFC_WP2_B DATA1 C12 IO OVDD --- QSPI_A_DATA2/IFC_A24/ IFC_WP3_B DATA2 D13 IO OVDD --- QSPI_A_DATA3/IFC_A25/ GPIO2_25/FTM5_CH0/ IFC_CS4_B/IFC_RB2_B DATA3 C13 IO OVDD --- QSPI_A_SCK/IFC_A18 SCK C9 O OVDD 1, 5 QSPI_B_CS0/IFC_A19 Chip Select D10 O OVDD 1, 5 QSPI_B_CS1/IFC_A20 CS1 C10 O OVDD 1, 5 QSPI_B_DATA0/IFC_PAR0/ GPIO2_13/FTM6_CH0 DATA0 B18 IO OVDD --- QSPI_B_DATA1/IFC_PAR1/ GPIO2_14/FTM6_CH1 DATA1 D17 IO OVDD --- QSPI_B_DATA2/ IFC_PERR_B/GPIO2_15/ FTM6_EXTCLK DATA2 E17 IO OVDD --- QSPI_B_DATA3/IFC_CS3_B/ GPIO2_12/FTM7_EXTCLK DATA3 C20 IO OVDD --- QSPI_B_SCK/IFC_A21/ cfg_dram_type SCK C11 O OVDD 1, 15 General Purpose Input/Output GPIO1_13/ASLEEP General Purpose Input/Output E9 O OVDD 1 GPIO1_14/RTC General Purpose Input/Output F17 IO OVDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 26 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GPIO1_15/UART1_SOUT General Purpose Input/Output H1 IO DVDD --- GPIO1_16/UART2_SOUT/ LPUART1_SOUT/FTM4_CH0 General Purpose Input/Output L2 IO DVDD --- GPIO1_17/UART1_SIN General Purpose Input/Output H2 IO DVDD --- GPIO1_18/UART2_SIN/ FTM4_CH1/LPUART1_SIN General Purpose Input/Output K1 IO DVDD --- GPIO1_19/UART1_RTS_B/ UART3_SOUT/ LPUART2_SOUT/FTM4_CH2 General Purpose Input/Output J2 IO DVDD --- GPIO1_20/UART2_RTS_B/ General Purpose Input/Output UART4_SOUT/ LPUART4_SOUT/FTM4_CH3/ LPUART1_RTS_B L1 IO DVDD --- GPIO1_21/UART1_CTS_B/ UART3_SIN/FTM4_CH4/ LPUART2_SIN General Purpose Input/Output J1 IO DVDD --- GPIO1_22/UART2_CTS_B/ UART4_SIN/FTM4_CH5/ LPUART1_CTS_B/ LPUART4_SIN General Purpose Input/Output M2 IO DVDD --- GPIO1_23/IRQ03/FTM3_CH7 General Purpose Input/Output J3 IO DVDD --- GPIO1_24/IRQ04/FTM3_CH0 General Purpose Input/Output J4 IO DVDD --- GPIO1_25/IRQ05/FTM3_CH1 General Purpose Input/Output J5 IO DVDD --- GPIO1_26/IRQ06/FTM3_CH2 General Purpose Input/Output K5 IO DVDD --- GPIO1_27/IRQ07/FTM3_CH3 General Purpose Input/Output L5 IO DVDD --- GPIO1_28/IRQ08/FTM3_CH4 General Purpose Input/Output M5 IO DVDD --- GPIO1_29/IRQ09/FTM3_CH5 General Purpose Input/Output N5 IO DVDD --- GPIO1_30/IRQ10/FTM3_CH6 General Purpose Input/Output P4 IO DVDD --- GPIO1_31/IRQ11 General Purpose Input/Output W3 IO LVDD --- GPIO2_00/SPI_PCS0/ SDHC_DAT4/SDHC_VS General Purpose Input/Output U1 IO OVDD --- GPIO2_01/SPI_PCS1/ SDHC_DAT5/ SDHC_CMD_DIR General Purpose Input/Output R3 IO OVDD --- GPIO2_02/SPI_PCS2/ SDHC_DAT6/ SDHC_DAT0_DIR General Purpose Input/Output T3 IO OVDD --- GPIO2_03/SPI_PCS3/ SDHC_DAT7/ SDHC_DAT123_DIR General Purpose Input/Output V1 IO OVDD --- GPIO2_04/SDHC_CMD/ LPUART3_SOUT/FTM4_CH6 General Purpose Input/Output P2 IO EVDD --- GPIO2_05/SDHC_DAT0/ FTM4_CH7/LPUART3_SIN General Purpose Input/Output P1 IO EVDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 27 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GPIO2_06/SDHC_DAT1/ LPUART5_SOUT/ FTM4_FAULT/ LPUART2_RTS_B General Purpose Input/Output R2 IO EVDD --- GPIO2_07/SDHC_DAT2/ LPUART2_CTS_B/ LPUART5_SIN/ FTM4_EXTCLK General Purpose Input/Output R1 IO EVDD --- GPIO2_08/SDHC_DAT3/ LPUART6_SOUT/ FTM4_QD_PHA/ LPUART3_RTS_B General Purpose Input/Output T1 IO EVDD --- GPIO2_09/SDHC_CLK/ LPUART3_CTS_B/ LPUART6_SIN/ FTM4_QD_PHB General Purpose Input/Output P3 IO EVDD --- GPIO2_10/IFC_CS1_B/ FTM7_CH0 General Purpose Input/Output A19 IO OVDD --- GPIO2_11/IFC_CS2_B/ FTM7_CH1 General Purpose Input/Output D20 IO OVDD --- GPIO2_12/IFC_CS3_B/ QSPI_B_DATA3/ FTM7_EXTCLK General Purpose Input/Output C20 IO OVDD --- GPIO2_13/IFC_PAR0/ QSPI_B_DATA0/FTM6_CH0 General Purpose Input/Output B18 IO OVDD --- GPIO2_14/IFC_PAR1/ QSPI_B_DATA1/FTM6_CH1 General Purpose Input/Output D17 IO OVDD --- GPIO2_15/IFC_PERR_B/ QSPI_B_DATA2/ FTM6_EXTCLK General Purpose Input/Output E17 IO OVDD --- GPIO2_25/IFC_A25/ QSPI_A_DATA3/FTM5_CH0/ IFC_CS4_B/IFC_RB2_B General Purpose Input/Output C13 IO OVDD --- GPIO2_26/IFC_A26/ FTM5_CH1/IFC_CS5_B/ IFC_RB3_B General Purpose Input/Output D14 IO OVDD --- GPIO2_27/IFC_A27/ FTM5_EXTCLK/IFC_CS6_B General Purpose Input/Output C14 IO OVDD --- GPIO3_00/EMI1_MDC General Purpose Input/Output AG2 IO LVDD --- GPIO3_01/EMI1_MDIO General Purpose Input/Output AF2 IO LVDD --- GPIO3_02/EC1_TXD3/ FTM1_CH5 General Purpose Input/Output Y3 IO LVDD --- GPIO3_03/EC1_TXD2/ FTM1_CH7 General Purpose Input/Output Y4 IO LVDD --- GPIO3_04/EC1_TXD1/ FTM1_CH3 General Purpose Input/Output AA3 IO LVDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 28 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GPIO3_05/EC1_TXD0/ FTM1_CH2 General Purpose Input/Output AB3 IO LVDD --- GPIO3_06/EC1_TX_EN/ FTM1_FAULT General Purpose Input/Output AB4 IO LVDD --- GPIO3_07/EC1_GTX_CLK/ FTM1_EXTCLK General Purpose Input/Output W4 IO LVDD --- GPIO3_08/EC1_GTX_CLK125 General Purpose Input/Output AC3 IO LVDD --- GPIO3_09/EC1_RXD3/ FTM1_CH4 General Purpose Input/Output W2 IO LVDD --- GPIO3_10/EC1_RXD2/ FTM1_CH6 General Purpose Input/Output Y1 IO LVDD --- GPIO3_11/EC1_RXD1/ FTM1_CH1 General Purpose Input/Output AA1 IO LVDD --- GPIO3_12/EC1_RXD0/ FTM1_CH0 General Purpose Input/Output AA2 IO LVDD --- GPIO3_13/EC1_RX_CLK/ FTM1_QD_PHA General Purpose Input/Output W1 IO LVDD --- GPIO3_14/EC1_RX_DV/ FTM1_QD_PHB General Purpose Input/Output AB1 IO LVDD --- GPIO3_15/EC2_TXD3/ TSEC_1588_ALARM_OUT2/ FTM2_CH5 General Purpose Input/Output AD3 IO LVDD --- GPIO3_16/EC2_TXD2/ TSEC_1588_ALARM_OUT1/ FTM2_CH7 General Purpose Input/Output AE3 IO LVDD --- GPIO3_17/EC2_TXD1/ TSEC_1588_CLK_OUT/ FTM2_CH3 General Purpose Input/Output AE4 IO LVDD --- GPIO3_18/EC2_TXD0/ TSEC_1588_PULSE_OUT2/ FTM2_CH2 General Purpose Input/Output AF3 IO LVDD --- GPIO3_19/EC2_TX_EN/ FTM2_FAULT General Purpose Input/Output AG3 IO LVDD --- GPIO3_20/EC2_GTX_CLK/ FTM2_EXTCLK General Purpose Input/Output AC4 IO LVDD --- GPIO3_21/EC2_GTX_CLK125 General Purpose Input/Output AG4 IO LVDD --- GPIO3_22/EC2_RXD3/ FTM2_CH4 General Purpose Input/Output AC2 IO LVDD --- GPIO3_23/EC2_RXD2/ FTM2_CH6 General Purpose Input/Output AD1 IO LVDD --- GPIO3_24/EC2_RXD1/ TSEC_1588_PULSE_OUT1/ FTM2_CH1 General Purpose Input/Output AE1 IO LVDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 29 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GPIO3_25/EC2_RXD0/ TSEC_1588_TRIG_IN2/ FTM2_CH0 General Purpose Input/Output AE2 IO LVDD --- GPIO3_26/EC2_RX_CLK/ TSEC_1588_CLK_IN/ FTM2_QD_PHA General Purpose Input/Output AC1 IO LVDD --- GPIO3_27/EC2_RX_DV/ TSEC_1588_TRIG_IN1/ FTM2_QD_PHB General Purpose Input/Output AF1 IO LVDD --- GPIO4_00/EMI2_MDC General Purpose Input/Output AH4 IO TVDD --- GPIO4_01/EMI2_MDIO General Purpose Input/Output AH3 IO TVDD --- GPIO4_10/IIC3_SCL/EVT5_B/ General Purpose Input/Output USB2_DRVVBUS/FTM8_CH0 L4 IO DVDD --- GPIO4_11/IIC3_SDA/EVT6_B/ General Purpose Input/Output USB2_PWRFAULT/ FTM8_CH1 M4 IO DVDD --- GPIO4_12/IIC4_SCL/EVT7_B/ General Purpose Input/Output USB3_DRVVBUS/ FTM3_FAULT M3 IO DVDD --- GPIO4_13/IIC4_SDA/EVT8_B/ General Purpose Input/Output USB3_PWRFAULT/ FTM3_EXTCLK N3 IO DVDD --- GPIO4_2/IIC2_SCL/ General Purpose Input/Output SDHC_CD_B/FTM3_QD_PHA K3 IO DVDD --- GPIO4_29/USB_DRVVBUS General Purpose Input/Output H6 IO DVDD --- GPIO4_3/IIC2_SDA/ SDHC_WP/FTM3_QD_PHB General Purpose Input/Output L3 IO DVDD --- GPIO4_30/USB_PWRFAULT General Purpose Input/Output G6 IO DVDD --- FTM1_CH0/EC1_RXD0/ GPIO3_12 Channel 0 AA2 IO LVDD --- FTM1_CH1/EC1_RXD1/ GPIO3_11 Channel 1 AA1 IO LVDD --- FTM1_CH2/EC1_TXD0/ GPIO3_05 Channel 2 AB3 IO LVDD --- FTM1_CH3/EC1_TXD1/ GPIO3_04 Channel 3 AA3 IO LVDD --- FTM1_CH4/EC1_RXD3/ GPIO3_09 Channel 4 W2 IO LVDD --- FTM1_CH5/EC1_TXD3/ GPIO3_02 Channel 5 Y3 IO LVDD --- FTM1_CH6/EC1_RXD2/ GPIO3_10 Channel 6 Y1 IO LVDD --- FTM1_CH7/EC1_TXD2/ GPIO3_03 Channel 7 Y4 IO LVDD --- Frequency Timer Module Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 30 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes FTM1_EXTCLK/ EC1_GTX_CLK/GPIO3_07 External Clock W4 I LVDD 1 FTM1_FAULT/EC1_TX_EN/ GPIO3_06 Fault AB4 I LVDD 1 FTM1_QD_PHA/ EC1_RX_CLK/GPIO3_13 Phase A W1 I LVDD 1 FTM1_QD_PHB/EC1_RX_DV/ Phase B GPIO3_14 AB1 I LVDD 1 FTM2_CH0/EC2_RXD0/ GPIO3_25/ TSEC_1588_TRIG_IN2 Channel 0 AE2 IO LVDD --- FTM2_CH1/EC2_RXD1/ GPIO3_24/ TSEC_1588_PULSE_OUT1 Channel 1 AE1 IO LVDD --- FTM2_CH2/EC2_TXD0/ GPIO3_18/ TSEC_1588_PULSE_OUT2 Channel 2 AF3 IO LVDD --- FTM2_CH3/EC2_TXD1/ GPIO3_17/ TSEC_1588_CLK_OUT Channel 3 AE4 IO LVDD --- FTM2_CH4/EC2_RXD3/ GPIO3_22 Channel 4 AC2 IO LVDD --- FTM2_CH5/EC2_TXD3/ GPIO3_15/ TSEC_1588_ALARM_OUT2 Channel 5 AD3 IO LVDD --- FTM2_CH6/EC2_RXD2/ GPIO3_23 Channel 6 AD1 IO LVDD --- FTM2_CH7/EC2_TXD2/ GPIO3_16/ TSEC_1588_ALARM_OUT1 Channel 7 AE3 IO LVDD --- FTM2_EXTCLK/ EC2_GTX_CLK/GPIO3_20 External Clock AC4 I LVDD 1 FTM2_FAULT/EC2_TX_EN/ GPIO3_19 Fault AG3 I LVDD 1 FTM2_QD_PHA/ EC2_RX_CLK/GPIO3_26/ TSEC_1588_CLK_IN Phase A AC1 I LVDD 1 FTM2_QD_PHB/EC2_RX_DV/ Phase B GPIO3_27/ TSEC_1588_TRIG_IN1 AF1 I LVDD 1 FTM3_CH0/IRQ04/GPIO1_24 Channel 0 J4 IO DVDD --- FTM3_CH1/IRQ05/GPIO1_25 Channel 1 J5 IO DVDD --- FTM3_CH2/IRQ06/GPIO1_26 Channel 2 K5 IO DVDD --- FTM3_CH3/IRQ07/GPIO1_27 Channel 3 L5 IO DVDD --- FTM3_CH4/IRQ08/GPIO1_28 Channel 4 M5 IO DVDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 31 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes FTM3_CH5/IRQ09/GPIO1_29 Channel 5 N5 IO DVDD --- FTM3_CH6/IRQ10/GPIO1_30 Channel 6 P4 IO DVDD --- FTM3_CH7/IRQ03/GPIO1_23 Channel 7 J3 IO DVDD --- FTM3_EXTCLK/IIC4_SDA/ GPIO4_13/EVT8_B/ USB3_PWRFAULT External Clock N3 I DVDD 1 FTM3_FAULT/IIC4_SCL/ GPIO4_12/EVT7_B/ USB3_DRVVBUS Fault M3 I DVDD 1 FTM3_QD_PHA/IIC2_SCL/ GPIO4_2/SDHC_CD_B Phase A K3 I DVDD 1 FTM3_QD_PHB/IIC2_SDA/ GPIO4_3/SDHC_WP Phase B L3 I DVDD 1 FTM4_CH0/UART2_SOUT/ GPIO1_16/LPUART1_SOUT Channel 0 L2 IO DVDD --- FTM4_CH1/UART2_SIN/ GPIO1_18/LPUART1_SIN Channel 1 K1 IO DVDD --- FTM4_CH2/UART1_RTS_B/ GPIO1_19/UART3_SOUT/ LPUART2_SOUT Channel 2 J2 IO DVDD --- FTM4_CH3/UART2_RTS_B/ GPIO1_20/UART4_SOUT/ LPUART4_SOUT/ LPUART1_RTS_B Channel 3 L1 IO DVDD --- FTM4_CH4/UART1_CTS_B/ GPIO1_21/UART3_SIN/ LPUART2_SIN Channel 4 J1 IO DVDD --- FTM4_CH5/UART2_CTS_B/ GPIO1_22/UART4_SIN/ LPUART1_CTS_B/ LPUART4_SIN Channel 5 M2 IO DVDD --- FTM4_CH6/SDHC_CMD/ GPIO2_04/LPUART3_SOUT Channel 6 P2 IO EVDD --- FTM4_CH7/SDHC_DAT0/ GPIO2_05/LPUART3_SIN Channel 7 P1 IO EVDD --- FTM4_EXTCLK/SDHC_DAT2/ External Clock GPIO2_07/LPUART2_CTS_B/ LPUART5_SIN R1 I EVDD 1 FTM4_FAULT/SDHC_DAT1/ GPIO2_06/LPUART5_SOUT/ LPUART2_RTS_B R2 I EVDD 1 T1 I EVDD 1 Fault FTM4_QD_PHA/SDHC_DAT3/ Phase A GPIO2_08/LPUART6_SOUT/ LPUART3_RTS_B Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 32 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description FTM4_QD_PHB/SDHC_CLK/ Phase B GPIO2_09/LPUART3_CTS_B/ LPUART6_SIN Package pin number Pin type Power supply Notes P3 I EVDD 1 FTM5_CH0/IFC_A25/ GPIO2_25/QSPI_A_DATA3/ IFC_CS4_B/IFC_RB2_B Channel 0 C13 IO OVDD --- FTM5_CH1/IFC_A26/ GPIO2_26/IFC_CS5_B/ IFC_RB3_B Channel 1 D14 IO OVDD --- FTM5_EXTCLK/IFC_A27/ GPIO2_27/IFC_CS6_B External Clock C14 I OVDD 1 FTM6_CH0/IFC_PAR0/ GPIO2_13/QSPI_B_DATA0 Channel 0 B18 IO OVDD --- FTM6_CH1/IFC_PAR1/ GPIO2_14/QSPI_B_DATA1 Channel 1 D17 IO OVDD --- FTM6_EXTCLK/IFC_PERR_B/ External Clock GPIO2_15/QSPI_B_DATA2 E17 I OVDD 1 FTM7_CH0/IFC_CS1_B/ GPIO2_10 Channel 0 A19 IO OVDD --- FTM7_CH1/IFC_CS2_B/ GPIO2_11 Channel 1 D20 IO OVDD --- FTM7_EXTCLK/IFC_CS3_B/ GPIO2_12/QSPI_B_DATA3 External Clock C20 I OVDD 1 FTM8_CH0/IIC3_SCL/ GPIO4_10/EVT5_B/ USB2_DRVVBUS Channel 0 L4 IO DVDD --- FTM8_CH1/IIC3_SDA/ GPIO4_11/EVT6_B/ USB2_PWRFAULT Channel 1 M4 IO DVDD --- LPUART LPUART1_CTS_B/ UART2_CTS_B/GPIO1_22/ UART4_SIN/FTM4_CH5/ LPUART4_SIN Clear to send M2 I DVDD 1 LPUART1_RTS_B/ UART2_RTS_B/GPIO1_20/ UART4_SOUT/ LPUART4_SOUT/FTM4_CH3 Request to send L1 O DVDD 1 LPUART1_SIN/UART2_SIN/ GPIO1_18/FTM4_CH1 Receive data K1 I DVDD 1 LPUART1_SOUT/ UART2_SOUT/GPIO1_16/ FTM4_CH0 Transmit data L2 IO DVDD --- LPUART2_CTS_B/ SDHC_DAT2/GPIO2_07/ Clear to send R1 I EVDD 1 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 33 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes LPUART5_SIN/ FTM4_EXTCLK LPUART2_RTS_B/ SDHC_DAT1/GPIO2_06/ LPUART5_SOUT/ FTM4_FAULT Request to send R2 O EVDD 1 LPUART2_SIN/ UART1_CTS_B/GPIO1_21/ UART3_SIN/FTM4_CH4 Receive data J1 I DVDD 1 LPUART2_SOUT/ UART1_RTS_B/GPIO1_19/ UART3_SOUT/FTM4_CH2 Transmit data J2 IO DVDD --- LPUART3_CTS_B/ SDHC_CLK/GPIO2_09/ LPUART6_SIN/ FTM4_QD_PHB Clear to send P3 I EVDD 1 LPUART3_RTS_B/ SDHC_DAT3/GPIO2_08/ LPUART6_SOUT/ FTM4_QD_PHA Request to send T1 O EVDD 1 LPUART3_SIN/SDHC_DAT0/ GPIO2_05/FTM4_CH7 Receive data P1 I EVDD 1 LPUART3_SOUT/ SDHC_CMD/GPIO2_04/ FTM4_CH6 Transmit data P2 IO EVDD --- LPUART4_SIN/ UART2_CTS_B/GPIO1_22/ UART4_SIN/FTM4_CH5/ LPUART1_CTS_B Receive data M2 I DVDD 1 LPUART4_SOUT/ UART2_RTS_B/GPIO1_20/ UART4_SOUT/FTM4_CH3/ LPUART1_RTS_B Transmit data L1 IO DVDD --- LPUART5_SIN/SDHC_DAT2/ Receive data GPIO2_07/LPUART2_CTS_B/ FTM4_EXTCLK R1 I EVDD 1 LPUART5_SOUT/ SDHC_DAT1/GPIO2_06/ FTM4_FAULT/ LPUART2_RTS_B Transmit data R2 IO EVDD --- LPUART6_SIN/SDHC_CLK/ Receive data GPIO2_09/LPUART3_CTS_B/ FTM4_QD_PHB P3 I EVDD 1 LPUART6_SOUT/ SDHC_DAT3/GPIO2_08/ FTM4_QD_PHA/ LPUART3_RTS_B T1 IO EVDD --- Transmit data TSEC_1588 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 34 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes TSEC_1588_ALARM_OUT1/ EC2_TXD2/GPIO3_16/ FTM2_CH7 Alarm Out AE3 O LVDD 1 TSEC_1588_ALARM_OUT2/ EC2_TXD3/GPIO3_15/ FTM2_CH5 Alarm Out AD3 O LVDD 1 TSEC_1588_CLK_IN/ EC2_RX_CLK/GPIO3_26/ FTM2_QD_PHA Clock In AC1 I LVDD 1 TSEC_1588_CLK_OUT/ EC2_TXD1/GPIO3_17/ FTM2_CH3 Clock Out AE4 O LVDD 1 TSEC_1588_PULSE_OUT1/ EC2_RXD1/GPIO3_24/ FTM2_CH1 Pulse Out AE1 O LVDD 1 TSEC_1588_PULSE_OUT2/ EC2_TXD0/GPIO3_18/ FTM2_CH2 Pulse Out AF3 O LVDD 1 TSEC_1588_TRIG_IN1/ EC2_RX_DV/GPIO3_27/ FTM2_QD_PHB Trigger In AF1 I LVDD 1 TSEC_1588_TRIG_IN2/ EC2_RXD0/GPIO3_25/ FTM2_CH0 Trigger In AE2 I LVDD 1 Power and Ground Signals GND001 GND A2 --- --- --- GND002 GND A5 --- --- --- GND003 GND A21 --- --- --- GND004 GND B3 --- --- --- GND005 GND B4 --- --- --- GND006 GND B7 --- --- --- GND007 GND B10 --- --- --- GND008 GND B13 --- --- --- GND009 GND B16 --- --- --- GND010 GND B19 --- --- --- GND011 GND B21 --- --- --- GND012 GND B24 --- --- --- GND013 GND B26 --- --- --- GND014 GND C1 --- --- --- GND015 GND C2 --- --- --- GND016 GND C5 --- --- --- GND017 GND C21 --- --- --- GND018 GND C27 --- --- --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 35 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GND019 GND D3 --- --- --- GND020 GND D4 --- --- --- GND021 GND D7 --- --- --- GND022 GND D9 --- --- --- GND023 GND D12 --- --- --- GND024 GND D15 --- --- --- GND025 GND D18 --- --- --- GND026 GND D21 --- --- --- GND027 GND D24 --- --- --- GND028 GND E1 --- --- --- GND029 GND E2 --- --- --- GND030 GND E5 --- --- --- GND031 GND E21 --- --- --- GND032 GND E26 --- --- --- GND033 GND F3 --- --- --- GND034 GND F4 --- --- --- GND035 GND F7 --- --- --- GND036 GND F14 --- --- --- GND037 GND F16 --- --- --- GND038 GND F18 --- --- --- GND039 GND F24 --- --- --- GND040 GND G1 --- --- --- GND041 GND G2 --- --- --- GND042 GND G9 --- --- --- GND043 GND G10 --- --- --- GND044 GND G11 --- --- --- GND045 GND G21 --- --- --- GND046 GND G26 --- --- --- GND047 GND H3 --- --- --- GND048 GND H4 --- --- --- GND049 GND H5 --- --- --- GND050 GND H14 --- --- --- GND051 GND H15 --- --- --- GND052 GND H16 --- --- --- GND053 GND H17 --- --- --- GND054 GND H18 --- --- --- GND055 GND H21 --- --- --- GND056 GND H24 --- --- --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 36 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GND057 GND J6 --- --- --- GND058 GND J7 --- --- --- GND059 GND J8 --- --- --- GND060 GND J9 --- --- --- GND061 GND J10 --- --- --- GND062 GND J11 --- --- --- GND063 GND J12 --- --- --- GND064 GND J21 --- --- --- GND065 GND J23 --- --- --- GND066 GND J26 --- --- --- GND067 GND K2 --- --- --- GND068 GND K4 --- --- --- GND069 GND K6 --- --- --- GND070 GND K13 --- --- --- GND071 GND K15 --- --- --- GND072 GND K17 --- --- --- GND073 GND K19 --- --- --- GND074 GND K21 --- --- --- GND075 GND L6 --- --- --- GND076 GND L10 --- --- --- GND077 GND L12 --- --- --- GND078 GND L14 --- --- --- GND079 GND L16 --- --- --- GND080 GND L18 --- --- --- GND081 GND L20 --- --- --- GND082 GND L23 --- --- --- GND083 GND L26 --- --- --- GND084 GND M6 --- --- --- GND085 GND M9 --- --- --- GND086 GND M11 --- --- --- GND087 GND M13 --- --- --- GND088 GND M15 --- --- --- GND089 GND M17 --- --- --- GND090 GND M19 --- --- --- GND091 GND M21 --- --- --- GND092 GND M23 --- --- --- GND093 GND N2 --- --- --- GND094 GND N4 --- --- --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 37 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GND095 GND N6 --- --- --- GND096 GND N8 --- --- --- GND097 GND N10 --- --- --- GND098 GND N12 --- --- --- GND099 GND N14 --- --- --- GND100 GND N16 --- --- --- GND101 GND N18 --- --- --- GND102 GND N20 --- --- --- GND103 GND N23 --- --- --- GND104 GND N26 --- --- --- GND105 GND P6 --- --- --- GND106 GND P9 --- --- --- GND107 GND P11 --- --- --- GND108 GND P13 --- --- --- GND109 GND P15 --- --- --- GND110 GND P17 --- --- --- GND111 GND P19 --- --- --- GND112 GND P23 --- --- --- GND113 GND R5 --- --- --- GND114 GND R8 --- --- --- GND115 GND R10 --- --- --- GND116 GND R12 --- --- --- GND117 GND R14 --- --- --- GND118 GND R16 --- --- --- GND119 GND R18 --- --- --- GND120 GND R20 --- --- --- GND121 GND R23 --- --- --- GND122 GND R26 --- --- --- GND123 GND T2 --- --- --- GND124 GND T4 --- --- --- GND125 GND T6 --- --- --- GND126 GND T9 --- --- --- GND127 GND T11 --- --- --- GND128 GND T13 --- --- --- GND129 GND T15 --- --- --- GND130 GND T17 --- --- --- GND131 GND T19 --- --- --- GND132 GND T21 --- --- --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 38 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GND133 GND T23 --- --- --- GND134 GND T26 --- --- --- GND135 GND U6 --- --- --- GND136 GND U8 --- --- --- GND137 GND U10 --- --- --- GND138 GND U12 --- --- --- GND139 GND U14 --- --- --- GND140 GND U16 --- --- --- GND141 GND U18 --- --- --- GND142 GND U20 --- --- --- GND143 GND U23 --- --- --- GND144 GND V2 --- --- --- GND145 GND V4 --- --- --- GND146 GND V6 --- --- --- GND147 GND V9 --- --- --- GND148 GND V11 --- --- --- GND149 GND V13 --- --- --- GND150 GND V15 --- --- --- GND151 GND V17 --- --- --- GND152 GND V19 --- --- --- GND153 GND V21 --- --- --- GND154 GND V23 --- --- --- GND155 GND V26 --- --- --- GND156 GND W12 --- --- --- GND157 GND W18 --- --- --- GND158 GND W20 --- --- --- GND159 GND W22 --- --- --- GND160 GND Y2 --- --- --- GND161 GND Y5 --- --- --- GND162 GND Y13 --- --- --- GND163 GND Y14 --- --- --- GND164 GND Y21 --- --- --- GND165 GND Y23 --- --- --- GND166 GND Y26 --- --- --- GND167 GND AA4 --- --- --- GND168 GND AA14 --- --- --- GND169 GND AA21 --- --- --- GND170 GND AA24 --- --- --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 39 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes GND171 GND AB2 --- --- --- GND172 GND AB12 --- --- --- GND173 GND AB26 --- --- --- GND174 GND AC21 --- --- --- GND175 GND AC24 --- --- --- GND176 GND AD2 --- --- --- GND177 GND AD4 --- --- --- GND178 GND AD26 --- --- --- GND179 GND AE21 --- --- --- GND180 GND AE24 --- --- --- GND181 GND AF4 --- --- --- GND182 GND AF21 --- --- --- GND183 GND AF26 --- --- --- GND184 GND AG1 --- --- --- GND185 GND AG24 --- --- --- GND186 GND AG26 --- --- --- GND187 GND AH2 --- --- --- GND188 GND AH21 --- --- --- SD_GND01 Serdes core logic GND Y6 --- --- 23 SD_GND02 Serdes core logic GND Y7 --- --- 23 SD_GND03 Serdes core logic GND Y8 --- --- 23 SD_GND04 Serdes core logic GND Y9 --- --- 23 SD_GND05 Serdes core logic GND Y10 --- --- 23 SD_GND06 Serdes core logic GND Y15 --- --- 23 SD_GND07 Serdes core logic GND Y16 --- --- 23 SD_GND08 Serdes core logic GND AA5 --- --- 23 SD_GND09 Serdes core logic GND AA7 --- --- 23 SD_GND10 Serdes core logic GND AA9 --- --- 23 SD_GND11 Serdes core logic GND AA12 --- --- 23 SD_GND12 Serdes core logic GND AA17 --- --- 23 SD_GND13 Serdes core logic GND AA18 --- --- 23 SD_GND14 Serdes core logic GND AA19 --- --- 23 SD_GND15 Serdes core logic GND AB7 --- --- 23 SD_GND16 Serdes core logic GND AB9 --- --- 23 SD_GND17 Serdes core logic GND AB14 --- --- 23 SD_GND18 Serdes core logic GND AB17 --- --- 23 SD_GND19 Serdes core logic GND AB20 --- --- 23 SD_GND20 Serdes core logic GND AC5 --- --- 23 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 40 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes SD_GND21 Serdes core logic GND AC6 --- --- 23 SD_GND22 Serdes core logic GND AC8 --- --- 23 SD_GND23 Serdes core logic GND AC10 --- --- 23 SD_GND24 Serdes core logic GND AC11 --- --- 23 SD_GND25 Serdes core logic GND AC15 --- --- 23 SD_GND26 Serdes core logic GND AC16 --- --- 23 SD_GND27 Serdes core logic GND AC18 --- --- 23 SD_GND28 Serdes core logic GND AC19 --- --- 23 SD_GND29 Serdes core logic GND AD5 --- --- 23 SD_GND30 Serdes core logic GND AD7 --- --- 23 SD_GND31 Serdes core logic GND AD9 --- --- 23 SD_GND32 Serdes core logic GND AD12 --- --- 23 SD_GND33 Serdes core logic GND AD14 --- --- 23 SD_GND34 Serdes core logic GND AD17 --- --- 23 SD_GND35 Serdes core logic GND AD20 --- --- 23 SD_GND36 Serdes core logic GND AE5 --- --- 23 SD_GND37 Serdes core logic GND AE7 --- --- 23 SD_GND38 Serdes core logic GND AE9 --- --- 23 SD_GND39 Serdes core logic GND AE12 --- --- 23 SD_GND40 Serdes core logic GND AE14 --- --- 23 SD_GND41 Serdes core logic GND AE17 --- --- 23 SD_GND42 Serdes core logic GND AE20 --- --- 23 SD_GND43 Serdes core logic GND AF6 --- --- 23 SD_GND44 Serdes core logic GND AF7 --- --- 23 SD_GND45 Serdes core logic GND AF8 --- --- 23 SD_GND46 Serdes core logic GND AF9 --- --- 23 SD_GND47 Serdes core logic GND AF10 --- --- 23 SD_GND48 Serdes core logic GND AF11 --- --- 23 SD_GND49 Serdes core logic GND AF15 --- --- 23 SD_GND50 Serdes core logic GND AF16 --- --- 23 SD_GND51 Serdes core logic GND AF17 --- --- 23 SD_GND52 Serdes core logic GND AF18 --- --- 23 SD_GND53 Serdes core logic GND AF19 --- --- 23 SD_GND54 Serdes core logic GND AG5 --- --- 23 SD_GND55 Serdes core logic GND AG7 --- --- 23 SD_GND56 Serdes core logic GND AG9 --- --- 23 SD_GND57 Serdes core logic GND AG12 --- --- 23 SD_GND58 Serdes core logic GND AG14 --- --- 23 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 41 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes SD_GND59 Serdes core logic GND AG17 --- --- 23 SD_GND60 Serdes core logic GND AG20 --- --- 23 SD_GND61 Serdes core logic GND AH5 --- --- 23 SD_GND62 Serdes core logic GND AH7 --- --- 23 SD_GND63 Serdes core logic GND AH9 --- --- 23 SD_GND64 Serdes core logic GND AH12 --- --- 23 SD_GND65 Serdes core logic GND AH14 --- --- 23 SD_GND66 Serdes core logic GND AH17 --- --- 23 SD_GND67 Serdes core logic GND AH20 --- --- 23 SENSEGND GND Sense pin G20 --- --- --- OVDD1 General I/O supply J14 --- OVDD --- OVDD2 General I/O supply J15 --- OVDD --- OVDD3 General I/O supply J16 --- OVDD --- OVDD4 General I/O supply J17 --- OVDD --- OVDD5 General I/O supply J18 --- OVDD --- OVDD6 General I/O supply R7 --- OVDD --- DVDD1 UART/I2C supply N7 --- DVDD --- DVDD2 UART/I2C supply P7 --- DVDD --- EVDD eSDHC supply R6 --- EVDD --- LVDD1 Ethernet controller 1 & 2 supply T7 --- LVDD --- LVDD2 Ethernet controller 1 & 2 supply U7 --- LVDD --- LVDD3 Ethernet controller 1 & 2 supply V7 --- LVDD --- TVDD 1.2 V / LVDD supply for MDIO interface for 10G Fman (EC2) W6 --- TVDD --- G1VDD01 DDR supply B27 --- G1VDD --- G1VDD02 DDR supply D27 --- G1VDD --- G1VDD03 DDR supply F27 --- G1VDD --- G1VDD04 DDR supply H27 --- G1VDD --- G1VDD05 DDR supply K27 --- G1VDD --- G1VDD06 DDR supply L22 --- G1VDD --- G1VDD07 DDR supply M22 --- G1VDD --- G1VDD08 DDR supply M27 --- G1VDD --- G1VDD09 DDR supply N22 --- G1VDD --- G1VDD10 DDR supply P22 --- G1VDD --- G1VDD11 DDR supply P27 --- G1VDD --- G1VDD12 DDR supply R22 --- G1VDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 42 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes G1VDD13 DDR supply T22 --- G1VDD --- G1VDD14 DDR supply U22 --- G1VDD --- G1VDD15 DDR supply U27 --- G1VDD --- G1VDD16 DDR supply V22 --- G1VDD --- G1VDD17 DDR supply W27 --- G1VDD --- G1VDD18 DDR supply AA27 --- G1VDD --- G1VDD19 DDR supply AC27 --- G1VDD --- G1VDD20 DDR supply AE27 --- G1VDD --- G1VDD21 DDR supply AG27 --- G1VDD --- G1VDD22 DDR supply AH27 --- G1VDD --- SVDD1 SerDes1 core logic supply W10 --- SVDD --- SVDD2 SerDes1 core logic supply W13 --- SVDD --- SVDD3 SerDes1 core logic supply W14 --- SVDD --- SVDD4 SerDes1 core logic supply W15 --- SVDD --- SVDD5 SerDes1 core logic supply W16 --- SVDD --- SVDD6 SerDes1 core logic supply Y17 --- SVDD --- SVDD7 SerDes1 core logic supply Y18 --- SVDD --- SVDD8 SerDes1 core logic supply Y19 --- SVDD --- XVDD1 SerDes1 transceiver supply AC7 --- XVDD --- XVDD2 SerDes1 transceiver supply AC9 --- XVDD --- XVDD3 SerDes1 transceiver supply AC12 --- XVDD --- XVDD4 SerDes1 transceiver supply AC14 --- XVDD --- XVDD5 SerDes1 transceiver supply AC17 --- XVDD --- XVDD6 SerDes1 transceiver supply AC20 --- XVDD --- FA_VL Reserved AB21 --- FA_VL 15 PROG_MTR Reserved F13 --- PROG_MTR 15 TA_PROG_SFP SFP Fuse Programming Override supply G13 --- TA_PROG_SFP --- TH_VDD Thermal Monitor Unit supply G8 --- TH_VDD --- VDD01 Supply for cores and platform K14 --- VDD --- VDD02 Supply for cores and platform K16 --- VDD --- VDD03 Supply for cores and platform K18 --- VDD --- VDD04 Supply for cores and platform K20 --- VDD --- VDD05 Supply for cores and platform L11 --- VDD --- VDD06 Supply for cores and platform L13 --- VDD --- VDD07 Supply for cores and platform L15 --- VDD --- VDD08 Supply for cores and platform L17 --- VDD --- VDD09 Supply for cores and platform L19 --- VDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 43 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes VDD10 Supply for cores and platform M10 --- VDD --- VDD11 Supply for cores and platform M12 --- VDD --- VDD12 Supply for cores and platform M14 --- VDD --- VDD13 Supply for cores and platform M16 --- VDD --- VDD14 Supply for cores and platform M18 --- VDD --- VDD15 Supply for cores and platform N9 --- VDD --- VDD16 Supply for cores and platform N11 --- VDD --- VDD17 Supply for cores and platform N13 --- VDD --- VDD18 Supply for cores and platform N15 --- VDD --- VDD19 Supply for cores and platform N17 --- VDD --- VDD20 Supply for cores and platform N19 --- VDD --- VDD21 Supply for cores and platform P10 --- VDD --- VDD22 Supply for cores and platform P12 --- VDD --- VDD23 Supply for cores and platform P14 --- VDD --- VDD24 Supply for cores and platform P16 --- VDD --- VDD25 Supply for cores and platform P18 --- VDD --- VDD26 Supply for cores and platform R9 --- VDD --- VDD27 Supply for cores and platform R11 --- VDD --- VDD28 Supply for cores and platform R13 --- VDD --- VDD29 Supply for cores and platform R15 --- VDD --- VDD30 Supply for cores and platform R17 --- VDD --- VDD31 Supply for cores and platform R19 --- VDD --- VDD32 Supply for cores and platform T10 --- VDD --- VDD33 Supply for cores and platform T12 --- VDD --- VDD34 Supply for cores and platform T14 --- VDD --- VDD35 Supply for cores and platform T16 --- VDD --- VDD36 Supply for cores and platform T18 --- VDD --- VDD37 Supply for cores and platform U9 --- VDD --- VDD38 Supply for cores and platform U11 --- VDD --- VDD39 Supply for cores and platform U13 --- VDD --- VDD40 Supply for cores and platform U15 --- VDD --- VDD41 Supply for cores and platform U17 --- VDD --- VDD42 Supply for cores and platform U19 --- VDD --- VDD43 Supply for cores and platform V10 --- VDD --- VDD44 Supply for cores and platform V12 --- VDD --- VDD45 Supply for cores and platform V14 --- VDD --- VDD46 Supply for cores and platform V16 --- VDD --- VDD47 Supply for cores and platform V18 --- VDD --- Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 44 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes VDD48 Supply for cores and platform V20 --- VDD --- VDD49 Supply for cores and platform W11 --- VDD --- VDD50 Supply for cores and platform W17 --- VDD --- VDD51 Supply for cores and platform W19 --- VDD --- TA_BB_VDD Battery Backed Security Monitor supply G12 --- TA_BB_VDD --- AVDD_CGA1 CPU Cluster Group A PLL1 supply H11 --- AVDD_CGA1 --- AVDD_CGA2 CPU Cluster Group A PLL2 supply H10 --- AVDD_CGA2 --- AVDD_PLAT Platform PLL supply H9 --- AVDD_PLAT --- AVDD_D1 DDR1 PLL supply R21 --- AVDD_D1 --- AVDD_SD1_PLL1 SerDes1 PLL 1 supply AA11 --- AVDD_SD1_PLL1 --- AVDD_SD1_PLL2 SerDes1 PLL 2 supply AB6 --- AVDD_SD1_PLL2 --- AVDD_SD2_PLL1 SerDes2 PLL 1 supply AB15 --- AVDD_SD2_PLL1 --- AVDD_SD2_PLL2 SerDes2 PLL 2 supply AA16 --- AVDD_SD2_PLL2 --- SENSEVDD Vdd Sense pin G19 --- SENSEVDD --- USB_HVDD1 3.3 V High Supply K8 --- USB_HVDD --- USB_HVDD2 3.3 V High Supply L8 --- USB_HVDD --- USB_SDVDD1 1.0 V Analog and digital HS supply M7 --- USB_SDVDD --- USB_SDVDD2 1.0 V Analog and digital HS supply M8 --- USB_SDVDD --- USB_SVDD1 1.0 V Analog and digital SS supply K7 --- USB_SVDD --- USB_SVDD2 1.0 V Analog and digital SS supply L7 --- USB_SVDD --- NC_AA10 No Connection AA10 --- --- 12 NC_AA15 No Connection AA15 --- --- 12 NC_AB10 No Connection AB10 --- --- 12 NC_AB11 No Connection AB11 --- --- 12 NC_AB16 No Connection AB16 --- --- 12 NC_F12 No Connection F12 --- --- 12 NC_K10 No Connection K10 --- --- 12 NC_K11 No Connection K11 --- --- 12 NC_K12 No Connection K12 --- --- 12 NC_K22 No Connection K22 --- --- 12 NC_K9 No Connection K9 --- --- 12 NC_L21 No Connection L21 --- --- 12 No Connection Pins Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 45 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes NC_L9 No Connection L9 --- --- 12 NC_M20 No Connection M20 --- --- 12 NC_N21 No Connection N21 --- --- 12 NC_P20 No Connection P20 --- --- 12 NC_P21 No Connection P21 --- --- 12 NC_P5 No Connection P5 --- --- 12 NC_P8 No Connection P8 --- --- 12 NC_R4 No Connection R4 --- --- 12 NC_T20 No Connection T20 --- --- 12 NC_T5 No Connection T5 --- --- 12 NC_T8 No Connection T8 --- --- 12 NC_U21 No Connection U21 --- --- 12 NC_U4 No Connection U4 --- --- 12 NC_U5 No Connection U5 --- --- 12 NC_V5 No Connection V5 --- --- 12 NC_V8 No Connection V8 --- --- 12 NC_W21 No Connection W21 --- --- 12 NC_W5 No Connection W5 --- --- 12 NC_W7 No Connection W7 --- --- 12 NC_W8 No Connection W8 --- --- 12 NC_W9 No Connection W9 --- --- 12 1. Functionally, this pin is an output or an input, but structurally it is an I/O because it either sample configuration input during reset, is a muxed pin, or has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan. 2. This output is actively driven during reset rather than being tri-stated during reset. 3. MDIC[0] is grounded through a 162 Ω precision 1% resistor and MDIC[1] is connected to GVDD through a 162 Ω precision 1% resistor. For either full or half driver strength calibration of DDR IOs, use the same MDIC resistor value of 162 Ω. The memory controller register setting can be used to determine automatic calibration is done to full or half drive strength. These pins are used for automatic calibration of the DDR4 IOs. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 46 NXP Semiconductors Pin assignments 4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed. 5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. 6. Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply. 7. This pin is an open-drain signal. 8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply. 9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled. 10. These are test signals for factory use only and must be pulled up (100Ω to 1-kΩ) to the respective power supply for normal operation. 11. This pin requires a 200Ω ± 1% pull-up to respective power-supply. 12. Do not connect. These pins should be left floating. 14. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 15. These pins must be pulled to ground (GND). 16. This pin requires a 698Ω ± 1% pull-up to respective power-supply. 17. These pins should be tied to ground if the diode is not utilized for temperature monitoring. 18. This pin should be grounded through a 200Ω +/-1% 100ppm/°C precision resistor. 19. This pin must be pulled to OVDD through a 100-Ω to 1kΩ resistor for a four core LS1046A device and tied to ground for a two core LS1026A device. 20. In normal operation, this pin must be pulled high to OVDD with 4.7 kΩ. 21. DIFF_SYSCLK and DIFF_SYSCLK_B is tied to cfg_eng_use0, the configuration is described in section "Reset configuration word (RCW)" of QorIQ LS1046A Reference Manual. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 47 Electrical characteristics 22. This pin should be connected to ground through 2-10 kΩ resistor when not used. 23. SD_GND must be directly connected to GND. 24. This pin must be pulled down to GND with a pull down resistor of value 1 KΩ 25. This pin will not be tested using JTAG Boundary scan operation. 26. For proper clock selection, terminate cfg_eng_use0 with a pull up or pull down of 4.7 kΩ to ensure that the signal will have a valid state as soon as the IO voltage reach its operating condition. 27. When using discrete DRAM, or RDIMM, the MALERT_B pin needs a 50 ohm to 100 ohm pull-up resistor to G1VDD. 28. This pin requires a pull-up to the respective power supply so as to meet the timing requirements in Table 23 Warning See "Connection Recommendations in QorIQ LS1046A Design Checklist (AN5252)" for additional details on properly connecting these pins for specific applications. 3 Electrical characteristics This section describes the DC and AC electrical specifications for the chip. The chip is currently targeted to these specifications, some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer design specifications. 3.1 Overall DC electrical characteristics This section describes the ratings, conditions, and other characteristics. 3.1.1 Absolute maximum ratings This table provides the absolute maximum ratings. Table 2. Absolute maximum ratings1,5 Characteristic Core and platform supply voltage Symbol VDD Max Value -0.3 to 1.08 Unit V Notes 4 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 48 NXP Semiconductors Electrical characteristics Table 2. Absolute maximum ratings1,5 (continued) Characteristic PLL supply voltage (core PLL, platform, DDR) Symbol AVDD_CGA1 Max Value Unit Notes -0.3 to 1.98 V — -0.3 to 1.48 V — AVDD_CGA2 AVDD_D1 AVDD_PLAT PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SDn_PLL1 AVDD_SDn_PLL2 SFP Fuse Programming TA_PROG_SFP -0.3 to 1.98 V — Thermal Unit Monitor supply TH_VDD -0.3 to 1.98 V — Battery Backed Security Monitor supply TA_BB_VDD -0.3 to 1.08 V — IFC, SPI, IRQ[0:2], Tamper Detect, System Control, SYSCLK, DDRCLK, RTC, EVT[0:4], DFT, JTAG, DIFF_SYSCLK, CLK_OUT, QSPI, FTM[5:7], eSDHC_DAT[4:7], eSDHC_CMD/DAT0_DIR, eSDHC_DAT123_DIR, eSDHC_SYNC_IN/OUT, SDHC_VS OVDD -0.3 to 1.98 V — DUART, I2C, IRQ[3:10], USB2/3_PWRFAULT, USB2/3_DRVVBUS, EVT_B[5:8], LPUART[1:2], LPUART4, FTM3_CH[1:7], FTM4_CH[1:5], FTM8, eSDHC_CD/WP DVDD -0.3 to 3.63 V — eSDHC_DAT[0:3], eSDHC_CMD, eSDHC_CLK, FTM4_CH[6:7], LPUART[3:6] EVDD V — DDR4 DRAM I/O voltage G1VDD -0.3 to 1.32 V — Main power supply for internal circuitry of SerDes and pad power supply for SerDes receivers SVDD -0.3 to 1.08 V — Pad power supply for SerDes transmitter XVDD -0.3 to 1.48 V — Ethernet interface, Ethernet management interface 1 (EMI1), 1588, IRQ11, FTM1, FTM2, LVDD -0.3 to 2.75 V — Ethernet management interface 2 (EMI2), GPIO2 TVDD V — -0.3 to 1.98 -0.3 to 3.63 -0.3 to 1.98 -0.3 to 1.98 -0.3 to 2.75 -0.3 to 1.98 -0.3 to 1.32 USB PHY Transceiver supply voltage Storage temperature range USB_HVDD -0.3 to 3.63 V - USB_SDVDD -0.3 to 1.08 V 3 USB_SVDD -0.3 to 1.08 V 2 TSTG -55 to 150 °C -- Notes: 1. Functional operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Analog and Digital SS supply for USBPHY. 3. Analog and Digital HS supply for USBPHY. 4. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 49 Electrical characteristics Table 2. Absolute maximum ratings1,5 Characteristic Symbol Max Value Unit Notes 5. Exposing device to Absolute Maximum Ratings conditions for long periods of time may affect reliability or cause permanent damage. This table provides the absolute maximum ratings for input signal voltage levels. Table 3. Absolute maximum ratings for input signal voltage levels1 Interface Input signals Symbol DDR4 DRAM signals G1VIN Max DC V_input range Max undershoot and Uni overshoot voltage range t Note s GND to (G1VDD x 1.05) -0.3 to (G1VDD x 1.1) V 2, 3, 5 Ethernet interface, Ethernet LVIN management interface 1 (EMI1), 1588, IRQ11, FTM1, FTM2 GND to (LVDD x 1.1) -0.3 to (LVDD x 1.15) V 2, 3 IFC, SPI, IRQ[0:2], Tamper Detect, System Control, SYSCLK, DDRCLK, RTC, EVT[0:4], DFT, JTAG, DIFF_SYSCLK, CLK_OUT, QSPI, FTM[5:7], eSDHC_DAT[4:7], eSDHC_CMD/DAT0_DIR, eSDHC_DAT123_DIR, eSDHC_SYNC_IN/OUT, SDHC_VS OVIN GND to (OVDD x 1.1) -0.3 to (OVDD x 1.15) V 2, 3 DUART, I2C, IRQ[3:10], USB2/3_PWRFAULT, USB2/3_DRVVBUS, EVT_B[5:8], LPUART[1:2], LPUART4, FTM3_CH[1:7], FTM4_CH[1:5], FTM8, eSDHC_CD/WP DVIN GND to (DVDD x 1.1) -0.3 to (DVDD x 1.15) eSDHC_DAT[0:3], eSDHC_CMD, eSDHC_CLK, FTM4_CH[6:7], LPUART[3:6] EVIN GND to (EVDD x 1.1) -0.3 to (EVDD x 1.15) V 2, 3 Main power supply for internal circuitry of SerDes SnVIN GND to (SVDD x 1.05) -0.3 to (SnVDD x 1.1) V 2, 3 Ethernet management interface 2 (EMI2), GPIO2 TVIN GND to (TVDD x 1.05) -0.3 to (TVDD x 1.15) V 2, 3 USB PHY Transceiver signals USB_HVIN GND to (USB_HVDD x 1.05) -0.3 to (USB_HVDD x 1.15) V 2, 3 USB_SVIN GND to (USB_SVDD x 1.1) -0.3 to (USB_SVDD x 1.15) V 2, 3 Notes: 1. Functional operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: The input voltage level of the signals must not exceed corresponding Max DC V_input range. For example DDR4 must not exceed 5% of G1VDD. 3. Caution: (S, G, L, O, D, E, T) VIN, USB_HVIN, USB_SVIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 8. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 50 NXP Semiconductors Electrical characteristics Table 3. Absolute maximum ratings for input signal voltage levels1 Interface Input signals Symbol Max DC V_input range Max undershoot and Uni overshoot voltage range t Note s 5. Typical DDR interface uses ODT enabled mode. For tests purposes with ODT off mode, simulation should be done first so as to make sure that the overshoot signal level at the input pin does not exceed GVDD by more than 10%. The Overshoot/ Undershoot period should comply with JEDEC standards. 3.1.2 Recommended operating conditions This table provides the recommended operating conditions for this chip. NOTE The values shown are the recommended operating conditions and proper device operation outside these conditions is not guaranteed. Table 4. Recommended operating conditions Characteristic Symbol Core and platform supply voltage VDD 0.9 V core and platform supply voltage Recommended value 1.0 V ± 30 mV Unit Notes V 3, 4, 5, 8 1.8 V ± 90 mV V 9 1.35 V ± 67 mV V — 0.9 V ± 30 mV PLL supply voltage (core PLL, platform, DDR) AVDD_CGA1 AVDD_CGA2 AVDD_D1 AVDD_PLAT PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SD1_PLL1 AVDD_SD1_PLL2 AVDD_SD2_PLL1 AVDD_SD2_PLL2 SFP fuse programming TA_PROG_SFP 1.8 V ± 90 mV V 2 Thermal monitor unit supply TH_VDD 1.8 V ± 90 mV V — Battery Backed Security Monitor supply TA_BB_VDD 1.0 V ± 30 mV V 8 IFC, IRQ[0:2], Tamper Detect, System Control, SYSCLK, DDRCLK, RTC, EVT[0:4], DFT, JTAG, DIFF_SYSCLK, CLK_OUT, QSPI, FTM[5:7], SPI, SDHC_DAT[4:7], SDHC_CMD_DIR, SDHC_DAT0_DIR, SDHC_DAT123_DIR, SDHC_SYNC_IN/OUT, SDHC_VS OVDD 1.8 V ± 90 mV V — DUART, I2C, IRQ[3:10], USB2/3_PWRFAULT, DVDD USB2/3_DRVVBUS, EVT_B[5:8], LPUART[1:2], LPUART4, FTM3_CH[1:7], FTM4_CH[1:5], FTM8, SDHC_CD/WP 3.3 V ± 165 mV V — SDHC_DAT[0:3], SDHC_CMD, SDHC_CLK, FTM4_CH[6:7], LPUART3, LPUART5, LPUART6 3.3 V ±165 mV V — 0.9 V ± 30 mV EVDD 1.8 V ± 90 mV 1.8 V ± 90 mV Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 51 Electrical characteristics Table 4. Recommended operating conditions (continued) Characteristic Symbol Recommended value Unit Notes DDR4 DRAM I/O voltage G1VDD 1.2 V ± 60 mV V — Main power supply for internal circuitry of SerDes and pad power supply for SerDes receivers SVDD 1.0 V ± 50 mV V — 0.9 V + 50 mV 0.9 V - 30 mV Pad power supply for SerDes transmitters XVDD 1.35 V ± 67 mV V — Ethernet interface 1/2, Ethernet management interface 1 (EMI1), 1588, IRQ11, FTM1, FTM2 LVDD 2.5 V ± 125 mV V 1 Ethernet management interface 2 (EMI2), GPIO2 TVDD 1.8 V ± 90 mV 2.5 V ± 125 mV V 1.8 V ± 90 mV 1.2V ± 60 mV USB PHY 3.3 V high supply voltage USB_HVDD 3.3 V ± 165 mV V USB PHY analog and digital HS supply USB_SDVDD 1.0 V ± 50 mV V 7, 8 V 6, 8 GND to G1VDD V — Ethernet interface, Ethernet LVIN management interface 1 (EMI1), 1588, IRQ11, FTM1, FTM2 GND to LVDD V — IFC, SPI, IRQ[0:2], Tamper Detect, System Control, SYSCLK, DDRCLK, RTC, EVT[0:4], DFT, JTAG, DIFF_SYSCLK, CLK_OUT, QSPI, FTM[5:7], SDHC_DAT[4:7], SDHC_CMD_DIR/ DAT0_DIR, SDHC_DAT123_DIR, SDHC_SYNC_IN/OUT, SDHC_VS OVIN GND to OVDD V — DUART, I2C, IRQ[3:10], USB2/3_PWRFAULT, USB2/3_DRVVBUS, EVT_B[5:8], LPUART[1:2], LPUART4, FTM3_CH[1:7], FTM4_CH[1:5], FTM8, SDHC_CD/WP DVIN GND to DVDD V — SDHC_DAT[0:3], EVIN SDHC_CMD, SDHC_CLK, FTM4_CH[6:7], LPUART[3:6] GND to EVDD V — 0.9 V + 50 mV 0.9 V - 30 mV USB PHY analog and digital SS supply USB_SVDD 1.0 V ± 50 mV 0.9 V + 50 mV 0.9 V - 30 mV Input voltage DDR4 DRAM signals G1VIN Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 52 NXP Semiconductors Electrical characteristics Table 4. Recommended operating conditions (continued) Characteristic PHY transceiver signals Symbol Recommended value Unit Notes Main power supply for internal circuitry of SerDes SVIN GND to SVDD V — Ethernet management interface 2 (EMI2), GPIO2 TVIN GND to TVDD V — USB transceiver supply for USB PHY USB_HVIN GND to USBn_HVDD V — GND to USB_SVDD V — TA, TA = 0°C (min) to °C 10 TJ TJ = 105°C (max) TA, TA = -40°C (min) to °C 10 TJ TJ = 105°C (max) TA, TA = 0°C (min) to TJ TJ = 105°C (max) Analog and digital HS supply USB_SVIN for USB PHY Operating temperature range Normal operation Extended temperature Secure boot fuse programming °C 2 Notes: 1. RGMII is supported at 2.5 V or 1.8 V. 2. TA_PROG_SFP must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only during secure boot fuse programming, subject to the power sequencing constraints shown in Power sequencing. For all other operating conditions, TA_PROG_SFP must be tied to GND. 3. For additional information, see the core and platform supply voltage filtering section in the chip design checklist. 4. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin. 5. Operation at 1.08 V is allowable for up to 25 ms at initial power on. 6. Analog and Digital SS supply for USB PHY. 7. Analog and Digital HS supply for USB PHY. 8. For supported voltage requirement for a given part number, see Table 144. 9. AVDD_PLAT, AVDD_CGA1, AVDD_CGA2, and AVDD_D1 are measured at the input to the filter and not at the pin of the device. 10. For supported temperature range for a given part number, see Table 144. This figure shows the undershoot and overshoot voltages at the interfaces of the chip. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 53 Electrical characteristics Maximum overshoot D/E/S1/G1/L/O/T/USB*VDD VIH GND VIL Minimum undershoot Overshoot/undershoot period Notes: The overshoot/undershoot period should be less than 10% of shortest possible toggling period of the input signal or per input signal specific protocol requirement. For GPIO input signal overshoot/undershoot period, it should be less than 10% of the SYSCLK period. Figure 8. Overshoot/undershoot voltage for G1VDD/OVDD/SVDD/TVDD/ LVDD/EVDD/DVDD/ USB_HVDD/USB_SVDD See Table 4 for actual recommended core voltage. Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 4. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD, EVDD, DVDD, TVDD, and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential receivers referenced by the internally supplied reference signal as is appropriate for the JEDEC DDR4 electrical signaling standard. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. 3.1.3 Output driver characteristics This chip provides information on the characteristics of the output driver strengths. NOTE These values are preliminary estimates. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 54 NXP Semiconductors Electrical characteristics Table 5. Output drive capability Driver type Output impedance (Ω) Minimum2 DDR4 signal - Notes Maximum3 Typical 18(fullstrength mode) Supply Voltage - G1VDD = 1.2 V 1 27(halfstrength mode) Ethernet interface, Ethernet management interface 1 (EMI1), 1588, FTM1, FTM2 30 50 70 LVDD = 2.5V - 30 45 60 LVDD = 1.8V - MDC of Ethernet management interface 45 2 (EMI 2) 40 65 100 TVDD = 1.2 V - 55 75 TVDD = 1.8V - 40 60 90 TVDD = 2.5V - MDIO of Ethernet management interface 30 2 (EMI 2) 25 40 60 TVDD = 1.2 V - 33 44 TVDD = 1.8V - 25 40 57 TVDD = 2.5V - IFC, SPI, EVT[0:4], JTAG, CLK_OUT, QSPI, FTM[5:7], eSDHC_DAT[4:7], eSDHC_CMD/DAT0_DIR, eSDHC_DAT123_DIR, eSDHC_SYNC_OUT, SDHC_VS 30 45 60 OVDD = 1.8 V - eSDHC_DAT[0:3], eSDHC_CMD, eSDHC_CLK, FTM4_CH[6:7], LPUART[3:6] 45 65 90 EVDD = 3.3V - 40 55 75 EVDD = 1.8V DUART, I2C, USB2/3_DRVVBUS, EVT_B[5:8], LPUART[1:2], LPUART4, FTM3_CH[1:7], FTM4_CH[1:5], FTM8 40 55 75 DVDD = 1.8V 45 65 90 DVDD = 3.3V - 1. The drive strength of the DDR4 in half-strength mode is at Tj = 105°C and at G1VDD (min). 2. Estimated number based on best case processed device. 3. Estimated number based on worst case processed device. 3.2 Power sequencing The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. For power up, these requirements are as follows: 1. OVDD, DVDD, LVDD, EVDD, TVDD, XVDD, AVDD_CGAn, AVDD_PLAT, AVDD_D1, AVDD_SDn_PLL1, AVDD_SDn_PLL2, USB_HVDD. Drive TA_PROG_SFP = GND. • PORESET_B input must be driven asserted and held during this step. 2. VDD, SVDD, TA_BB_VDD, USB_SDVDD, USB_SVDD QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 55 Electrical characteristics • The 3.3 V (USB_HVDD) in Step 1 and 1.0 V (USB_SDVDD, USB_SVDD) in Step 2 supplies can power up in any sequence provided all these USB supplies ramp up within 95 ms with respect to each other. 3. G1VDD Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of their value. All supplies must be at their stable values within 400 ms. Negate PORESET_B input when the required assertion/hold time has been met per Table 23. • • • • NOTE While VDD is ramping up, current may be supplied from VDD through LS1046A to G1VDD. If using Trust Architecture Security Monitor battery backed features, prior to VDD ramping up to the 0.5 V level, ensure that OVDD is ramped to recommended operational voltage and SYSCLK or DIFF_SYSCLK/ DIFF_SYSCLK_B is running. These clocks should have a minimum frequency of 800 Hz and a maximum frequency not greater than the supported system clock frequency for the device. Ramp rate requirements should be met per Table 12. While XVDD is ramping, current may be supplied from XVDD through chip to SVDD. Warning Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary. For secure boot fuse programming, use the following steps: 1. After negation of PORESET_B, drive TA_PROG_SFP = 1.8 V after a required minimum delay per Table 6. 2. After fuse programming is complete, it is required to return TA_PROG_SFP = GND before the system is power cycled or powered down (VDD ramp down) per the required timing specified in Table 6. See Security fuse processor for additional details. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 56 NXP Semiconductors Electrical characteristics Warning No activity other than that required for secure boot fuse programming is permitted while TA_PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while TA_PROG_SFP = GND. This figure shows the TA_PROG_SFP timing diagram. Fuse programming 10% TA_PROG_SFP 10% TA_PROG_SFP TA_PROG_SFP 90% VDD tTA_PROG_SFP_VDD VDD 90% OVDD tTA_PROG_SFP_PROG 90% OVDD PORESET_B tTA_PROG_SFP_RST tTA_PROG_SFP_DELAY NOTE: TA_PROG_SFP must be stable at 1.8 V prior to initiating fuse programming. Figure 9. TA_PROG_SFP timing diagram This table provides information on the power-down and power-up sequence parameters for TA_PROG_SFP. Table 6. TA_PROG_SFP timing 5 Driver type Min Max Unit Notes tTA_PROG_SFP_DELAY 100 — SYSCLKs 1 tTA_PROG_SFP_PROG 0 — us 2 tTA_PROG_SFP_VDD 0 — us 3 tTA_PROG_SFP_RST 0 — us 4 Notes: 1. Delay required from the deassertion of PORESET_B to driving TA_PROG_SFP ramp up. Delay measured from PORESET_B deassertion at 90% OVDD to 10% TA_PROG_SFP ramp up. 2. Delay required from fuse programming completion to TA_PROG_SFP ramp down start. Fuse programming must complete while TA_PROG_SFP is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while TA_PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while TA_PROG_SFP = GND. After fuse programming is complete, it is required to return TA_PROG_SFP = GND. 3. Delay required from TA_PROG_SFP ramp-down complete to VDD ramp-down start. TA_PROG_SFP must be grounded to minimum 10% TA_PROG_SFP before VDD reaches 90% VDD. 4. Delay required from TA_PROG_SFP ramp-down complete to PORESET_B assertion. TA_PROG_SFP must be grounded to minimum 10% TA_PROG_SFP before PORESET_B assertion reaches 90% OVDD. 5. Only six secure boot fuse programming events are permitted per lifetime of a device. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 57 Electrical characteristics 3.3 Power-down requirements The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be started. If performing secure boot fuse programming per the requirements in Power sequencing, it is required that TA_PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Power sequencing. 3.4 Power characteristics This table provides the power dissipations of the VDD supply and SerDes supply (SVDD) for various operating platform clock frequencies versus the core and DDR clock frequencies. Table 7. LS1046A core power dissipation9 Core freque ncy (MHz) Platform/ FMan frequency (MHz) DDR frequen cy (MHz) VDD (V) SVDD (V) Junction temperatu re (ºC) Power mode Power (W) VDD 8 SVDD Total Core and platform power Notes (W)1 1800 700/800 2100 1.0 1.0 65 Typical 8.5 0.9 9.4 2, 3 85 Thermal 11.4 0.9 12.3 4, 7 Maximum 14.3 0.9 15.2 5, 6, 7 Thermal 14.4 0.9 15.3 4, 7 105 1600 700/800 2100 1.0 1.0 Maximum 17.3 0.9 18.2 5, 6, 7 65 Typical 7.7 0.9 8.7 2, 3 85 Thermal 10.7 0.9 11.6 4, 7 Maximum 13.2 0.9 14.2 5, 6, 7 Thermal 13.7 0.9 14.6 4, 7 Maximum 16.3 0.9 17.2 5, 6, 7 65 Typical 7.3 0.9 8.2 2, 3 85 Thermal 8.7 0.9 9.6 4, 7 Maximum 11.1 0.9 12.0 5, 6, 7 Thermal 10.5 0.9 11.5 4, 7 Maximum 12.9 0.9 13.8 5, 6, 7 65 Typical 6.4 0.9 7.3 2, 3, 10 85 Thermal 7.7 0.9 8.6 4, 7, 10 Maximum 9.8 0.9 10.7 5, 6, 7, 10 105 1400 600/600 2100 1.0 1.0 105 1200 400/600 1600 1.0 1.0 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 58 NXP Semiconductors Electrical characteristics Table 7. LS1046A core power dissipation9 (continued) Core freque ncy (MHz) Platform/ FMan frequency (MHz) DDR frequen cy (MHz) VDD (V) SVDD (V) Junction temperatu re (ºC) Power mode Power (W) VDD SVDD8 Total Core and platform power Notes (W)1 105 1200 400/600 1600 0.9 0.9 0.9 10.5 4, 7, 10 Maximum 11.6 0.9 12.5 5, 6, 7, 10 65 Typical 4.9 0.7 5.6 2, 3 85 Thermal 105 Thermal 9.6 5.9 0.7 6.6 4, 7 Maximum 7.4 0.7 8.2 5, 6, 7 Thermal 7.2 0.7 8.0 4, 7 Maximum 8.8 0.7 9.5 5, 6, 7 1. Combined power of VDD and SVDD with DDR controller and all SerDes banks active. Does not include I/O power. 2. Typical power assumes Dhrystone running with activity factor of 70% (on all cores) and executing DMA on the platform with 100% activity factor. 3. Typical power based on nominal, processed device. 4. Thermal power assumes Dhrystone running with activity factor of 70% (on all cores) and executing DMA on the platform at 100% activity factor. 5. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and executing DMA on the platform at 115% activity factor. 6. Maximum power is provided for power supply design sizing. 7. Thermal and maximum power are based on worst case processed device. 8. Total SVDD Power conditions: a. SerDes 1 : XFI x2, 10 Gbaud b. SerDes 1 : SGMII x2, 1.25 Gbaud c. SerDes 2 : PEX x2, 5 Gbaud 9. Power numbers are only applicable to part numbering offering from Table 144. For example: A 1.8GHz offering part when runs at 1.4GHz will have power numbers higher than listed for 1.4GHz. 10. These power numbers are valid when purchasing the 1400MHz device and running the clocks at these conditions. Table 8. LS1026A core power dissipation9 Core freque ncy (MHz) Platform/ FMan frequency (MHz) DDR frequen cy (MHz) VDD (V) SVDD (V) Junction tempera ture (ºC) Power mode Power (W) VDD SVDD 8 Total Core and platform power Notes (W)1 1800 700/800 2100 1.0 1.0 65 Typical 6.7 0.9 7.6 2, 3 85 Thermal 9.3 0.9 10.2 4, 7 Maximum 11.5 0.9 12.4 5, 6, 7 Thermal 12.3 0.9 13.2 4, 7 Maximum 14.5 0.9 15.4 5, 6, 7 65 Typical 6.2 0.9 7.1 2, 3 85 Thermal 8.7 0.9 9.6 4, 7 Maximum 10.7 0.9 11.6 5, 6, 7 Thermal 11.7 0.9 12.6 4, 7 Maximum 13.7 0.9 14.6 5, 6, 7 105 1600 700/800 2100 1.0 1.0 105 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 59 Electrical characteristics Table 8. LS1026A core power dissipation9 (continued) Core freque ncy (MHz) Platform/ FMan frequency (MHz) DDR frequen cy (MHz) VDD (V) SVDD (V) Junction tempera ture (ºC) Power mode Power (W) VDD SVDD8 Total Core and platform power Notes (W)1 1400 600/600 2100 1.0 1.0 65 Typical 6.0 0.9 6.9 2, 3 85 Thermal 7.2 0.9 8.1 4, 7 Maximum 9.1 0.9 10.0 5, 6, 7 Thermal 0.9 10.0 4, 7 Maximum 10.9 0.9 11.8 5, 6, 7 65 Typical 5.2 0.9 6.2 2, 3, 10 85 Thermal 6.4 0.9 7.3 4, 7, 10 Maximum 8.0 0.9 9.0 5, 6, 7, 10 Thermal 8.3 0.9 9.2 4, 7, 10 Maximum 9.9 0.9 10.8 5, 6, 7, 10 65 Typical 3.9 0.7 4.7 2, 3 85 Thermal 4.7 0.7 5.5 4, 7 Maximum 6.0 0.7 6.7 5, 6, 7 Thermal 6.1 0.7 6.9 4, 7 Maximum 7.3 0.7 8.1 5, 6, 7 105 1200 400/600 1600 1.0 1.0 105 1200 400/600 1600 0.9 0.9 105 9.0 1. Combined power of VDD and SVDD with DDR controller and all SerDes banks active. Does not include I/O power. 2. Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform with 100% activity factor. 3. Typical power based on nominal, processed device. 4. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at 100% activity factor. 5. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and executing DMA on the platform at 115% activity factor. 6. Maximum power is provided for power supply design sizing. 7. Thermal and maximum power are based on worst case processed device. 8. Total SVDD power conditions: a. SerDes 1 : XFI x2, 10 Gbaud b. SerDes 1 : SGMII x2, 1.25 Gbaud c. SerDes 2 : PEX x2, 5 Gbaud 9. Power numbers are only applicable to part numbering offering from Table 144. For example: A 1.8GHz offering part when runs at 1.4GHz will have power numbers higher than listed for 1.4GHz. 10. These power numbers are valid when purchasing the 1400MHz device and running the clocks at these conditions. 3.4.1 Low-power mode saving estimation See this table for low-power mode savings. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 60 NXP Semiconductors Electrical characteristics Table 9. Low-power mode savings, 65C1, 2, 3 Mode Core Core Core Core Core Units Comments Frequency = Frequency = Frequency = Frequency = Frequency = 1.2 GHz 1.2 GHz 1.4 GHz 1.6 GHz 1.8 GHz Note s (VDD =0.9V) (VDD =1.0V) (VDD =1.0V) (VDD =1.0V) (VDD =1.0V) PW15 0.71 0.74 0.77 0.88 0.99 Watts Saving realized moving from run to PW15 state, single core. Arm in STANDBYWFI/WFE PH20 0.05 0.17 0.21 0.24 0.26 Watts Saving realized moving from PW15 to PH20 state, single core. Arm in STANDBYWFI/ WFEretain LPM20 1.02 1.46 1.70 1.94 2.18 Watts Saving realized moving from PW15 to LPM20 per device 4 5 Notes: 1. Power for VDD only 2. Typical power assumes Dhrystone running with activity factor of 70% 3. Typical power based on nominal process distribution for this device. 4. PW15 power savings with 1 core. Maximum savings would be N times, where N is the number of used cores. 5. LPM20 has all platform clocks disabled. 3.5 I/O power dissipation This table provides the estimated I/O power numbers for each block: DDR, PCI Express, IFC, Ethernet controller, SGMII, eSDHC, USB, SPI, DUART, IIC, SATA, and GPIO. Note that these numbers are based on design estimates only. Table 10. IO power supply estimated values Interface Parameter Symbol Typical Unit Notes DDR4 x64 2100 MT/s data rate G1VDD (1.2 V) 990 mW 1, 2 mW 1, 7 mW 1, 2 x64 1600 MT/s data rate 860 x64 2100 MT/s data rate 761 x64 1600 MT/s data rate 660 x32 2100 MT/s data rate 740 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 61 Electrical characteristics Table 10. IO power supply estimated values (continued) PCI Express SGMII x32 1600 MT/s data rate 637 x32 2100 MT/s data rate 518 x32 1600 MT/s data rate 490 mW 1, 7 79 mW 1, 3 x2, 2.5 Gbaud 132 mW x4, 2.5 Gbaud 237 mW x1, 5 Gbaud 80 mW x2, 5 Gbaud 133 mW x4, 5 Gbaud 239 mW x1, 8 Gbaud 81 mW x2, 8 Gbaud 136 mW x4, 8 Gbaud 245 mW 77 mW x2, 1.25 Gbaud 127 mW x3, 1.25 Gbaud 177 mW x4, 1.25 Gbaud 227 mW x1, 3.125 Gbaud 79 mW x2, 3.125 Gbaud 132 mW x3, 3.125 Gbaud 184 mW x1, 2.5 Gbaud x1, 1.25 Gbaud XVDD (1.35 V) XVDD (1.35 V) 1, 3 QSGMII x1, 5 Gbaud XVDD (1.35 V) 80 mW 1, 3 XFI x1, 10 Gbaud XVDD (1.35 V) 81 mW 1, 3 136 mW 73 mW 74 mW USB_HVDD (3.3 V) 46 mW USB_SVDD (1 V) mW x2, 10 Gbaud SATA (per port) 3.0 Gbaud XVDD (1.35 V) 6.0 Gbaud USB1/USB2/USB3 x1 Super speed (per PHY) mode USB1/USB2/USB3 x1 High speed (per PHY) mode 37 USB_SDVDD (1 V) 4 mW USB_HVDD (3.3 V) 79 mW USB_SVDD (1 V) mW 0.31 USB_SDVDD (1 V) 4.9 mW 1, 3 1, 5 1, 5 IFC 16-bit, 100 MHz OVDD (1.8 V) 60 mW 1 DUART . DVDD (3.3 V) 18 mW 1 DVDD (1.8 V) 9 mW DVDD (3.3 V) 17 mW DVDD (1.8 V) 9 mW I2C . 1 SPI . OVDD (1.8 V) 8 mW 1, 9 eSDHC . EVDD (3.3 V) 19 mW 1, 9 . EVDD (1.8V) 21 mW Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 62 NXP Semiconductors Electrical characteristics Table 10. IO power supply estimated values (continued) System control . OVDD (1.8 V) 16 mW 1, 9 EC1 RGMII LVDD (2.5 V) 24 mW 1, 9 LVDD (1.8 V) 17 mW LVDD (2.5 V) 24 mW LVDD (1.8 V) 17 mW EC2 RGMII QSPI . OVDD (1.8V) 17 mW 1, 9 IEEE1588 . LVDD (2.5 V) 14 mW 1, 9 LVDD (1.8 V) 10 mW JTAG + DFT . OVDD (1.8V) 10 mW 1, 9 GPIO x8 3.3 V 5 mW 1, 4, 9 2.5 V 4 mW 1.8 V 3 mW PLL core and system (per PLL) . AVDD_CGA1, AVDD_CGA2, AVDD_PLAT (1.8 V) 30 mW 1, 9 PLL DDR . AVDD_D1 (1.8 V) 30 mW 1, 9 PLL SerDes . AVDD_SD1_PLL1, 100 AVDD_SD1_PLL2, AVDD_SD2_PLL1, AVDD_SD2_PLL2 (1.35 V) mW 1, 9 Interrupts (IRQ) . OVDD (1.8 V) 4 mW 1 DVDD (1.8 V) 9 mW DVDD (3.3 V) 18 mW LVDD (2.5 V) 2 mW LVDD (1.8 V) 1 mW LVDD (2.5 V) 3 mW LVDD (1.8 V) 2 mW TVDD (2.5 V) 3 mW TVDD (1.8 V) 2 mW TVDD (1.2 V) 2 mW Ethernet management interface 1 . Ethernet management interface 2 . TA_PROG_SFP . TA_PROG_SFP (1.8 V) 173 mW TH_VDD . TH_VDD (1.8 V) 18 mW 1 1 6 1. The typical values are estimates and based on simulations at nominal recommended voltage for the I/O power supply and assuming 105°C junction temperature. 2. Typical DDR4 power numbers are based on two Rank DIMM with 40% utilization. 3. The total power numbers of XVDD is dependent on customer application use case. This table lists all the SerDes configurations possible for the device. To get the X1VDD power numbers, the user should add the combined lanes to match to the total SerDes Lanes used, not simply multiply the power numbers by the number of lanes. 4. GPIOs are supported on OVDD, LVDD, DVDD, TVDD and EVDD power rails. 5. USB power supply pins are shared between three USB controllers. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 63 Electrical characteristics Table 10. IO power supply estimated values 6. The maximum power requirement is during programming. No active power beyond leakage levels should be drawn and the supply must be grounded when not programming. 7. Typical DDR4 power numbers are based on single Rank DIMM with 40% utilization. 9. Assuming 15 pF total capacitance load per pin. Table 11. TA_BB_VDD power dissipation Supply Maximum Unit Notes TA_BB_VDD (SoC off, 40°C) 40 μW 1 TA_BB_VDD (SoC off, 70°C) 55 μW 1 Note: 1. When SoC is off, TA_BB_VDD may be supplied by battery power to retain the Zeroizable Master Key and other trust architecture state. Board should implement a PMIC, which switches TA_BB_VDD to battery when SoC is powered down. See the Device reference manual trust architecture chapter for more information. 3.6 Power-on ramp rate This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum power-on ramp rate is required to avoid excess in-rush current. This table provides the power supply ramp rate specifications. Table 12. Power supply ramp rate Parameter Min Max Unit Notes Required ramp rate for all voltage supplies (including OVDD/DVDD/G1VDD/ SVDD/XVDD/LVDD/EVDD/TVDD all core and platform VDD supplies, TA_PROG_SFP, and all AVDD supplies.) — 25 V/ms 1, 2 Required ramp rate for TA_PROG_SFP --- 25 V/ms 1,2 Required ramp rate for USB_HVDD --- 26.7 V/ms 1,2 Notes: 1. Ramp rate is specified as a linear ramp from 10% to 90%. If non-linear (for example, exponential), the maximum rate of change from 200 mV to 500 mV is the most critical as this range might falsely trigger the ESD circuitry. 2. Over full recommended operating temperature range. See Table 4. 3.7 Input clocks QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 64 NXP Semiconductors Electrical characteristics 3.7.1 System clock (SYSCLK) This section describes the system clock DC electrical characteristics and AC timing specifications. 3.7.1.1 SYSCLK DC electrical characteristics This table provides the SYSCLK DC characteristics. Table 13. SYSCLK DC electrical characteristics Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 0.7 x OVDD — — V 1 Input low voltage VIL — — 0.3 x OVDD V 1 Input capacitance CIN — 7 12 pF — Input current (VIN= 0 V or VIN = OVDD) IIN — — ± 50 µA 2 Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 4. 2. At recommended operating conditions with OVDD= 1.8 V. See Table 4. 3.7.1.2 SYSCLK AC timing specifications This table provides the SYSCLK AC timing specifications. Table 14. SYSCLK AC timing specifications1, 5 Parameter/condition Symbol Min Typ Max Unit Notes SYSCLK frequency fSYSCLK 100.0 MHz 1 SYSCLK cycle time tSYSCLK 10.0 ns 1 SYSCLK duty cycle tKHK/tSYSCLK 40 — 60 % 1 SYSCLK slew rate — 1 — 4 V/ns 2 SYSCLK peak period jitter — — — ± 150 ps — SYSCLK jitter phase noise at -56 dBc — — — 500 kHz 3 AC Input Swing Limits at 1.8 V OVDD ΔVAC 1.08 — 1.8 V — Notes: 1. Measured at the rising edge and/or the falling edge at OVDD/2. 2. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD. 3. Phase noise is calculated as FFT of TIE jitter. 4. At recommended operating conditions with OVDD = 1.8 V. See Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 65 Electrical characteristics 3.7.1.3 USB 3.0 reference clock requirements This table summarizes the requirements of the reference clock provided to the USB 3.0 SSPHY. There are two options for the reference clock of USB PHY: SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B. The following table provides the additional requirements when SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B is used as USB REFCLK. This table can also be used for 100 MHz reference clock requirements. Table 15. Reference clock requirements Parameter Symbol Min Typ Max Unit Notes Reference clock frequency offset FREF_OFFSET -300 — 300 ppm — Reference clock random jitter (RMS) RMSJREF_CLK — — 3 ps 1, 2 Reference clock deterministic jitter DJREF_CLK — — 150 ps 3 Duty cycle DCREF_CLK 40 — 60 % — Notes: 1. 1.5 MHz to Nyquist frequency. For example, for 100 MHz reference clock, the Nyquist frequency is 50 MHz. 2. The peak-to-peak Rj specification is calculated as 14.069 times the RMS Rj for 10-12 BER. 3. DJ across all frequencies. 3.7.2 Spread-spectrum sources Spread-spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter specification given in this table considers short-term (cycle-to-cycle) jitter only. The clock generator's cycle-to-cycle output jitter should meet the chip's input cycle-tocycle jitter requirement. Frequency modulation and spread are separate concerns; the chip is compatible with spread-spectrum sources if the recommendations listed in this table are observed. Table 16. Spread-spectrum clock source recommendations1 Parameter Min Max Unit Notes Frequency modulation — 60 kHz — Frequency spread — 1.0 % — Notes: 1. At recommended operating conditions with OVDD = 1.8 V. See Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 66 NXP Semiconductors Electrical characteristics CAUTION The processor's minimum and maximum SYSCLK and core/ platform/DDR frequencies must not be exceeded, regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated core/platform/DDR frequency should use only down-spreading to avoid violating the stated limits. 3.7.3 Real-time clock timing (RTC) The real-time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an input to the Watchdog, Flextimer, 1588 Timer and snvs unit; there is no need for jitter specification. The minimum period of the RTC signal should be greater than or equal to 16x the period of the platform clock with a 50% duty cycle. There is no minimum RTC frequency; RTC may be pulled to ground, if not needed. 3.7.4 Gigabit Ethernet reference clock timing This table provides the Ethernet gigabit reference clock DC electrical characteristics with LVDD = 2.5 V / 1.8 V. Table 17. ECn_GTX_CLK125 DC electrical characteristics (LVDD = 2.5 V / 1.8 V)1 Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 0.7 x LVDD — — V 2 Input low voltage VIL — — 0.2 x LVDD V 2 Input capacitance CIN — — 6 pF — Input current (VIN = 0 V or VIN = LVDD) IIN — — ± 50 µA 3 Notes: 1. For recommended operating conditions, see Table 4. 2. The min VIL and max VIH values are based on the respective min and max VIN values found in Table 4. 3. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 4. This table provides the Ethernet gigabit reference clock AC timing specifications. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 67 Electrical characteristics Table 18. ECn_GTX_CLK125 AC timing specifications 1 Parameter/Condition Symbol Min Typical Max Unit Notes ECn_GTX_CLK125 frequency fG125 125 - 100 ppm 125 125 + 100 ppm MHz — ECn_GTX_CLK125 cycle time tG125 -- 8 -- ns — ECn_GTX_CLK125 rise and fall time tG125R/tG125F — — ns 2 ECn_GTX_CLK125 duty cycle tG125H/tG125 40 — % 3 0.75 60 1000Base-T for RGMII Notes: 1. At recommended operating conditions with LVDD = 1.8 V ± 90mV / 2.5 V ± 125 mV. See Table 4. 2. Rise times are measured from 20% of LVDD to 80% of LVDD. Fall times are measured from 80% of LVDD to 20% of LVDD. 3. ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter. See RGMII AC timing specifications for duty cycle for the 10Base-T and 100Base-T reference clocks. 3.7.5 DDR clock (DDRCLK) This section provides the DDRCLK DC electrical characteristics and AC timing specifications. 3.7.5.1 DDRCLK DC electrical characteristics This table provides the DDRCLK DC electrical characteristics. Table 19. DDRCLK DC electrical characteristics3 Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 0.7 x OVDD — — V 1 Input low voltage VIL — — 0.3 x OVDD V 1 Input capacitance CIN — 7 12 pF — Input current (VIN= 0V or VIN = OVDD) IIN — — ± 50 μA 2 Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 4. 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 4. 3. At recommended operating conditions with OVDD = 1.8 V. See Table 4. 3.7.5.2 DDRCLK AC timing specifications This table provides the DDRCLK AC timing specifications. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 68 NXP Semiconductors Electrical characteristics Table 20. DDRCLK AC timing specifications5 Parameter/Condition Symbol Min Typ Max Unit Notes DDRCLK frequency fDDRCLK 100.0 MHz 1, 2 DDRCLK cycle time tDDRCLK 10.0 ns 1, 2 DDRCLK duty cycle tKHK/tDDRCLK 40 — 60 % 2 DDRCLK slew rate — 1 — 4 V/ns 3 DDRCLK peak period jitter — — — ± 150 ps — DDRCLK jitter phase noise at -56 dBc — — — 500 kHz 4 AC Input Swing Limits at 1.8 V OVDD ΔVAC 1.08 — 1.8 V — Notes: 1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequencies do not exceed their respective maximum or minimum operating frequencies. 2. Measured at the rising edge and/or the falling edge at OVDD/2. 3. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD. 4. Phase noise is calculated as FFT of TIE jitter. 5. At recommended operating conditions with OVDD = 1.8V. See Table 4. 3.7.6 Differential system clock (DIFF_SYSCLK/DIFF_SYSCLK_B) timing specifications Single Source clocking mode requires single onboard oscillator to provide reference clock input to Differential System clock pair (DIFF_SYSCLK/DIFF_SYSCLK_B). This Differential clock pair input provides clock to Core, Platform, DDR and USB PLL's This figure shows a receiver reference diagram of the Differential System clock. DIFF_SYSCLK 100 Ohm LVDS RX DIFF_SYSCLK_B Figure 10. LVDS receiver This section provides the differential system clock DC and AC timing specifications. 3.7.6.1 Differential system clock DC electrical characteristics The differential system clock receiver voltage requirements are as specified in the Recommended operating conditions table. The differential system clock can also be single-ended. For this, DIFF_SYSCLK_B should be connected to OVDD/2. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 69 Electrical characteristics This table provides the differential system clock (DIFF_SYSCLK/DIFF_SYSCLK_B) DC specifications. Table 21. Differential system clock DC electrical characteristics1 Parameter Symbol Min Typical Max Unit Notes Input differential voltage swing Vid 100 - 600 mV 2 Input common mode voltage Vicm 50 - 1570 mV - Power supply current Icc - - 5 mA - Input capacitance Cin 1.45 1.5 1.55 pF - Note: 1. At recommended operating conditions with OVDD = 1.8 V, see Table 4 for details. 2. Input differential voltage swing (Vid) specified is equal to |VDIFF_SYSCLK_P - VDIFF_SYSCLK_N| This figure shows the differential system clock (DIFF_SYSCLK) input DC specifications. 100 mV < Input amplitude or differential peak < 600 mV (Vid) VDIFF_SYSCLK_P Vmax < 1870 mV 50 mV < Vcm < 1570 mV Vmin > -250 mV VDIFF_SYSCLK_N Figure 11. DIFF_SYSCLK input DC requirements (external DC-coupled) 3.7.6.2 Differential system clock AC timing specifications Spread spectrum clocking is not supported on differential system clock pair input. This table provides the differential system clock (DIFF_SYSCLK/DIFF_SYSCLK_B) AC specifications. Table 22. Differential system clock AC electrical characteristics1 Parameter Symbol Min Typical Max Unit Notes DIFF_SYSCLK/DIFF_SYSCLK_B frequency range tDIFF_SYSCLK - 100 - MHz - DIFF_SYSCLK/DIFF_SYSCLK_B frequency tolerance tDIFF_TOL -300 - +300 ppm - Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 70 NXP Semiconductors Electrical characteristics Table 22. Differential system clock AC electrical characteristics1 (continued) Parameter Symbol Duty cycle tDIFF_DUTY Min Typical 40 Max 50 Unit 60 % Notes - Note: 1. This is evaluated with supply noise profile at +/- 5% sine wave 2. At recommended operating conditions with OVDD = 1.8 V, see Table 4 3.7.7 Other input clocks A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem block diagram. For information about the input clock requirements of functional sourced external of the chip, such as SerDes, Ethernet management, eSDHC, and IFC, see the specific interface section. 3.8 RESET initialization This table provides the AC timing specifications for the RESET initialization timing. Table 23. RESET Initialization timing specifications Parameter/Condition Min Max Unit Notes Required assertion time of PORESET_B after all power rails are stable 1 — ms 1 Required input assertion time of HRESET_B 32 — SYSCLKs 2, 3 Maximum rise/fall time of HRESET_B — 10 SYSCLK 4, 6 Maximum rise/fall time of PORESET_B — 1 SYSCLK 4, 7 Input setup time for POR configs (other than cfg_eng_use0) with respect to negation of PORESET_B 4 — SYSCLKs 2, 5 Input hold time for all POR configs with respect to negation of PORESET_B 2 — SYSCLKs 2 Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of PORESET_B — 5 SYSCLKs 2 Notes: 1. PORESET_B must be driven asserted before the core and platform power supplies are powered up. 2. SYSCLK is the primary clock input for the chip. 3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is documented in the reference manual's "Power-on Reset Sequence" section. 4. The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. 5. For proper clock selection, terminate cfg_eng_use0 with a pull up or pull down of 4.7 kΩ to ensure that the signal will have a valid state as soon as the IO voltage reach its operating condition. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 71 Electrical characteristics Table 23. RESET Initialization timing specifications Parameter/Condition Min Max Unit Notes 6. For HRESET_B the rise/fall time should not exceed 10 SYSCLKs. Rise time refers to signal transitions from 20% to 70% of O1VDD. Fall time refers to transitions from 70% to 20% of O1VDD. 7. For PORESET_B the rise/fall time should not exceed 1 SYSCLK. Rise time refers to signal transitions from 20% to 70% of OVDD. Fall time refers to transitions from 70% to 20% of OVDD. 3.9 DDR4 SDRAM controller This section describes the DC and AC electrical specifications for the DDR4 SDRAM controller interface. Note that the required G1VDD(typ) voltage is 1.2 V when interfacing to DDR4 SDRAM. 3.9.1 DDR4 SDRAM interface DC electrical characteristics This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR4 SDRAM. Table 24. DDR4 SDRAM interface DC electrical characteristics (G1VDD = 1.2 V)1 Parameter Symbol Min Max Unit Notes Input low VIL — 0.7 x G1VDD - 0.175 V 3 Input high VIH 0.7 x G1VDD + 0.175 — V 3 I/O leakage current IOZ -200 200 μA Notes: 1. G1VDD is expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's voltage supply may or may not be from the same source. 2. VTT and VREFCA are applied directly to the DRAM device. Both VTT and VREFCA voltages must track G1VDD/2. 3. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models. 4. See the IBIS model for the complete output IV curve characteristics. 5. Output leakage is measured with all outputs disabled, 0V ≤ VOUT ≤ G1VDD 6. For recommended operating conditions, see Table 4. 3.9.2 DDR4 SDRAM interface AC timing specifications This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports DDR4 memories. Note that the required GVDD(typ) voltage is 1.2 V when interfacing to DDR4 SDRAM. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 72 NXP Semiconductors Electrical characteristics 3.9.2.1 DDR4 SDRAM interface input AC timing specifications This table provides the input AC timing specifications for the DDR controller when interfacing to DDR4 SDRAM. Table 25. DDR4 SDRAM interface input AC timing specifications 1 Parameter Symbol AC input low voltage Min Max Unit Notes VILAC — 0.7 x G1VDD - 0.175 V — VIHAC 0.7 x G1VDD + 0.175 — — ≤ 2100 MT/s data rate AC input high voltage ≤ 2100 MT/s data rate V Note: 1. For recommended operating conditions, see Table 4. This table provides the input AC timing specifications for the DDR controller when interfacing to DDR4 SDRAM. Table 26. DDR4 SDRAM interface input AC timing specifications 3 Parameter Symbol Controller skew for MDQS-MDQ/MECC Max — — 2100 MT/s data rate -80 80 1800 MT/s data rate -93 93 1600 MT/s data rate -112 112 1300 MT/s data rate -125 125 — — 2100 MT/s data rate -154 154 1800 MT/s data rate -175 175 1600 MT/s data rate -200 200 1300 MT/s data rate -250 250 Tolerated Skew for MDQS-MDQ/MECC tCISKEW Min tDISKEW Unit Notes ps 1 ps 2 Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This must be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be determined by the following equation: tDISKEW = ±(T ÷ 4 - abs (tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. For recommended operating conditions, see Table 4. This figure shows the DDR4 SDRAM interface input timing diagram. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 73 Electrical characteristics MCK[n]_B MCK[n] tMCK MDQS[n] tDISKEW D0 MDQ[x] D1 tDISKEW tDISKEW Figure 12. DDR4 SDRAM interface input timing diagram 3.9.2.2 DDR4 SDRAM interface output AC timing specifications This table contains the output AC timing targets for the DDR4 SDRAM interface. Table 27. DDR4 SDRAM interface output AC timing specifications (G1VDD = 1.2 V)7 Symbol1 Parameter Min Max Unit Notes MCK[n] cycle time tMCK 952 1538 ps 2 ADDR/CMD/CNTL output setup with respect to MCK tDDKHAS — — ps 3 2100 MT/s data rate 350 — 1800 MT/s data rate 410 — 1600 MT/s data rate 495 — 1300 MT/s data rate 606 — ADDR/CMD/CNTL output hold with respect to tDDKHAX MCK — — ps 3 2100 MT/s data rate 350 — 1800 MT/s data rate 390 — 1600 MT/s data rate 495 — 1300 MT/s data rate 606 — MCK to MDQS Skew tDDKHMH -150 150 ps 4,7 MDQ/MECC/MDM output data eye tDDKXDEYE — — ps 5 2100 MT/s data rate 320 — 1800 MT/s data rate 350 — Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 74 NXP Semiconductors Electrical characteristics Table 27. DDR4 SDRAM interface output AC timing specifications (G1VDD = 1.2 V)7 (continued) Parameter Symbol1 Min Max 1600 MT/s data rate 400 — 1300 MT/s data rate 500 — Unit Notes MDQS preamble tDDKHMP 0.9 x tMCK — ps — MDQS postamble tDDKHME 0.4 x tMCK 0.6 x tMCK ps — 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals. 3. ADDR/CMD/CNTL includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of the timing modifications enabled by the use of these bits. 5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization. 6. Note that this is required to program the start value of the DQS adjust for write leveling. 7. For recommended operating conditions, see Table 4. NOTE For the ADDR/CMD/CNTL setup and hold specifications in Table 27, it is assumed that the clock control register is set to adjust the memory clocks by ½ applied cycle. This figure shows the DDR4 SDRAM interface output timing for the MCK to MDQS skew measurement (tDDKHMH). QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 75 Electrical characteristics MCK_B[n] MCK[n] tMCK tDDKHMH(max) MDQS tDDKHMH(min) MDQS Figure 13. tDDKHMH timing diagram This figure shows the DDR4 SDRAM output timing diagram. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 76 NXP Semiconductors Electrical characteristics MCK_B MCK tMCK tDDKHAS tDDKHAX ADDR/CMD Write A0 NOOP tDDKHMP tDDKHMH MDQS[n] tDDKHME D0 MDQ[x] tDDKXDEYE D1 tDDKXDEYE Figure 14. DDR4 output timing diagram 3.10 Ethernet interface, Ethernet management interface, IEEE Std 1588™ This section describes the DC and AC electrical characteristics for the Ethernet controller, Ethernet management, and IEEE Std 1588 interfaces. 3.10.1 SGMII interface Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 15, where CTX is the external (on board) AC-coupled capacitor. Each SerDes transmitter differential pair features 100-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to GNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure 85. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 77 Electrical characteristics 3.10.1.1 SGMII clocking requirements for SDn_REF_CLK1_P and SDn_REF_CLK1_N When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock is required on SDn_REF_CLK[1:2]_P and SDn_REF_CLK[1:2]_N pins. SerDes lanes may be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL. For more information on these specifications, see SerDes reference clocks. 3.10.1.2 SGMII DC electrical characteristics This section describes the electrical characteristics for the SGMII interface. 3.10.1.2.1 SGMII and SGMII 2.5G transmit DC specifications This table describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N) as shown in Figure 16. Table 28. SGMII DC transmitter electrical characteristics (XnVDD = 1.35 V)4 Parameter Symbol Min Typ Max Unit Notes Output high voltage VOH - - 1.5 x │VOD│-max mV 1 Output low voltage VOL │VOD│-min/2 - - mV 1 │VOD│ 320 500.0 725.0 mV TECR0[AMP_RED]=0b00 0000 293.8 459.0 665.6 TECR0[AMP_RED]=0b00 0001 266.9 417.0 604.7 TECR0[AMP_RED]=0b00 0011 240.6 376.0 545.2 TECR0[AMP_RED]=0b00 0010 213.1 333.0 482.9 TECR0[AMP_RED]=0b00 0110 186.9 292.0 423.4 TECR0[AMP_RED]=0b00 0111 160.0 250.0 362.5 TECR0[AMP_RED]=0b01 0000 80 100 120 Output differential voltage2, 3, 5 (XVDD-Typ at 1.35 V) Output impedance (differential) RO Ω - Notes: 1. This does not align to DC-coupled SGMII. 2. │VOD│ = │VSD_TXn_P - VSD_TXn_N│. │VOD│ is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 x │VOD│. 3. The │VOD│ value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.35 V, no common mode offset variation. SerDes transmitter is terminated with 100-Ω differential load between SDn _TXn_P and SDn_TXn_N. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 78 NXP Semiconductors Electrical characteristics Table 28. SGMII DC transmitter electrical characteristics (XnVDD = 1.35 V)4 Parameter Symbol Min Typ Max Unit Notes 4. For recommended operating conditions, see Table 4. 5. Example amplitude reduction setting for SGMII on SerDes1 lane A: LNATECR0[AMP_RED] = 0b000001 for an output differential voltage of 459 mV typical. This figure shows an example of a 4-wire AC-coupled SGMII serial link connection. SDn_TXn_P SDn_RXn_P CTX 50 Ω Transmitter Receiver 100 Ω SDn_TXn_N CTX SDn_RXn_N 50 Ω SGMII SerDes Interface SDn_RXn_P CTX SDn_TXn_P 50 Ω Receiver 100 Ω 50 Ω SDn_RXn_N CTX Transmitter SDn_TXn_N Figure 15. 4-wire AC-coupled SGMII serial link connection example This figure shows the SGMII transmitter DC measurement circuit. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 79 Electrical characteristics SGMII SerDes Interface SDn_TXn_P 50 Ω Transmitter VOD 100 Ω 50 Ω SDn_TXn_N Figure 16. SGMII transmitter DC measurement circuit This table defines the SGMII 2.5G transmitter DC electrical characteristics for 3.125 GBaud. Table 29. SGMII 2.5G transmitter DC electrical characteristics (XnVDD = 1.35 V)1 Parameter Symbol Min Typical Max Unit Output differential voltage │VOD│ 400 - 600 mV Output impedance (differential) RO 80 100 120 Ω Notes - Notes: 1. For recommended operating conditions, see Table 4. 3.10.1.2.2 SGMII and SGMII 2.5G DC receiver electrical characteristics This table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. Clock is recovered from the data. Table 30. SGMII DC receiver electrical characteristics 4 Parameter Symbol DC input voltage range Input differential voltage REIDL_TH = 001 REIDL_TH = 001 REIDL_TH = 100 Typ - N/A VRX_DIFFp-p 100 - 175 - 30 65 REIDL_TH = 100 Loss of signal threshold Min VLOS Max Unit Notes - 1 1200 mV 2, 5 - 100 mV 3, 5 - 175 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 80 NXP Semiconductors Electrical characteristics Table 30. SGMII DC receiver electrical characteristics 4 (continued) Parameter Symbol Receiver differential input impedance Min ZRX_DIFF 80 Typ - Max 120 Unit Ω Notes - Notes: 1. Input must be externally AC coupled. 2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage. 3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See PCI Express DC physical layer receiver specifications, and PCI Express AC physical layer receiver specifications, for further explanation. 4. For recommended operating conditions, see Table 4. 5. The REIDL_TH shown in the table refers to the chip's SRDSxLNmGCR1[REIDL_TH] bit field. This table defines the SGMII 2.5G receiver DC electrical characteristics for 3.125 GBaud. Table 31. SGMII 2.5G receiver DC timing specifications 1 Parameter Symbol Min Typical Max Unit Notes Input differential voltage VRX_DIFFp-p 200 - 1200 mV - Loss of signal threshold VLOS 75 - 200 mV - Receiver differential input impedance ZRX_DIFF 80 - 120 Ω - Notes: 1. For recommended operating conditions, see Table 4. 3.10.1.3 SGMII AC timing specifications This section describes the AC timing specifications for the SGMII interface. 3.10.1.3.1 SGMII and SGMII 2.5G transmit AC timing specifications This table provides the SGMII and SGMII 2.5G transmit AC timing specifications. A source synchronous clock is not supported. The AC timing specifications do not include RefClk jitter. Table 32. SGMII transmit AC timing specifications4 Parameter Symbol Min Typ Max Unit Notes Deterministic jitter JD - - 0.17 UI p-p - Total jitter JT - - 0.35 UI p-p 2 Unit Interval: 1.25 GBaud (SGMII) UI 800 - 100 ppm 800 800 + 100 ppm ps 1 Unit Interval: 3.125 GBaud (2.5G SGMII]) UI 320 - 100 ppm 320 320 + 100 ppm ps 1 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 81 Electrical characteristics Table 32. SGMII transmit AC timing specifications4 (continued) Parameter Symbol AC coupling capacitor Min CTX 10 Typ Max - Unit 200 nF Notes 3 Notes: 1. Each UI is 800 ps ± 100 ppm or 320 ps ± 100 ppm. 2. See Figure 18 for single frequency sinusoidal jitter measurements. 3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter output. 4. For recommended operating conditions, see Table 4. 3.10.1.3.2 SGMII AC measurement details Transmitter and receiver AC characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N) or at the receiver inputs (SDn_RXn_P and SDn_RXn_N) respectively, as shown in this figure. D + package pin C = CTX Transmitter silicon + package C = CTX D - package pin R = 50 Ω R = 50 Ω Figure 17. SGMII AC test/measurement load 3.10.1.3.3 SGMII and SGMII 2.5G receiver AC timing specifications This table provides the SGMII and SGMII 2.5G receiver AC timing specifications. The AC timing specifications do not include RefClk jitter. Source synchronous clocking is not supported. Clock is recovered from the data. Table 33. SGMII receiver AC timing specifications3 Parameter Deterministic jitter tolerance Symbol JD Combined deterministic and random jitter tolerance JDR Min Typ Max Unit Notes - - 0.37 UI p-p 1 - - 0.55 UI p-p 1 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 82 NXP Semiconductors Electrical characteristics Table 33. SGMII receiver AC timing specifications3 (continued) Parameter Symbol Min Typ Max Unit Notes Total jitter tolerance JT - - 0.65 UI p-p 1, 2 Bit error ratio BER - - 10-12 - - Unit Interval: 1.25 GBaud (SGMII) UI 800 - 100 ppm 800 800 + 100 ppm ps 1 Unit Interval: 3.125 GBaud (2.5G SGMII]) UI 320 - 100 ppm 320 320 + 100 ppm ps 1 Notes: 1. Measured at receiver 2.Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 18. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. 3. For recommended operating conditions, see Table 4. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of this figure. 8.5 UI p-p Sinuosidal Jitter Amplitude 20 dB/dec 0.10 UI p-p baud/142000 Frequency baud/1667 20 MHz Figure 18. Single-frequency sinusoidal jitter limits 3.10.2 QSGMII interface This section describes the QSGMII clocking and its DC and AC electrical characteristics. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 83 Electrical characteristics 3.10.2.1 QSGMII clocking requirements for SDn_REF_CLKn and SDn_REF_CLKn_B For more information on these specifications, see SerDes reference clocks. 3.10.2.2 QSGMII DC electrical characteristics This section discusses the electrical characteristics for the QSGMII interface. 3.10.2.2.1 QSGMII transmitter DC specifications This table describes the QSGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SDn_TXn and SDn_TXn_B). Table 34. QSGMII DC transmitter electrical characteristics (XnVDD = 1.35V)1 Parameter Symbol Min Typ Max Unit Notes Output differential voltage VDIFF 400 - 900 mV - Differential resistance TRD 80 100 120 Ω - Notes: 1. For recommended operating conditions, see Table 4. 3.10.2.2.2 QSGMII DC receiver electrical characteristics This table defines the QSGMII receiver DC electrical characteristics. Table 35. QSGMII receiver DC timing specifications 1 Parameter Symbol Min Typical Max Unit Notes Input differential voltage VDIFF 100 - 900 mV - Differential resistance RRDIN 80 100 120 Ω - Notes: 1. For recommended operating conditions, see Table 4. 3.10.2.3 QSGMII AC timing specifications This section discusses the AC timing specifications for the QSGMII interface. 3.10.2.3.1 QSGMII transmit AC timing specifications This table provides the QSGMII transmitter AC timing specifications. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 84 NXP Semiconductors Electrical characteristics Table 36. QSGMII transmit AC timing specifications1 Parameter Symbol Min Typ Max Unit Notes Transmitter baud rate TBAUD 5.000 - 100 ppm 5.000 5.000 + 100 ppm Gb/s - Uncorrelated high probability jitter TUHPJ - - 0.15 UI p-p - Total jitter tolerance JT - - 0.30 UI p-p - Notes: 1. For recommended operating conditions, see Table 4. 3.10.2.3.2 QSGMII receiver AC timing Specification This table provides the QSGMII receiver AC timing specifications. Table 37. QSGMII receive AC timing specifications2 Parameter Symbol Min Typ Max Unit Notes Receiver baud rate RBAUD 5.000 - 100 ppm 5.000 5.000 + 100 ppm Gb/s - Uncorrelated bounded high probability jitter RDJ - - 0.15 UI p-p - Correlated bounded high probability jitter RCBHPJ - - 0.30 UI p-p 1 Bounded high probability jitter RBHPJ - - 0.45 UI p-p - Sinusoidal jitter, maximum RSJ-max - - 5.00 UI p-p - Sinusoidal jitter, high frequency RSJ-hf - - 0.05 UI p-p - Total jitter (does not include sinusoidal jitter) RTj - - 0.60 UI p-p - Notes: 1. The jitter (RCBHPJ) and amplitude have to be correlated, for example, by a PCB trace. 2. For recommended operating conditions, see Table 4. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of this figure. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 85 Electrical characteristics 5 UI p-p Sinuosidal Jitter Amplitude 0.05 UI p-p 35.2 kHz Frequency 3 MHz 20 MHz Figure 19. QSGMII single-frequency sinusoidal jitter limits 3.10.3 XFI interface This section describes the XFI clocking requirements and its DC and AC electrical characteristics. 3.10.3.1 XFI clocking requirements for SDn_REF_CLKn_P and SDn_REF_CLKn_N Only SerDes 1 (SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N) may be used for SerDes XFI configurations based on the RCW configuration field SRDS_PRTCL. For more information on these specifications, see SerDes reference clocks. 3.10.3.2 XFI DC electrical characteristics This section describes the DC electrical characteristics for XFI. 3.10.3.2.1 XFI transmitter DC electrical characteristics This table defines the XFI transmitter DC electrical characteristics. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 86 NXP Semiconductors Electrical characteristics Table 38. XFI transmitter DC electrical characteristics (XVDD = 1.35 V)1 Parameter Symbol Output differential voltage Min VTX-DIFF 360 Typical - Max 770 Unit mV Notes LNmTECR 0[AMP_RE D]= 0b000111 De-emphasized differential output VTX-DE- voltage (ratio) RATIO-1.14dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-3.5dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-4.66dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-6.0dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-9.5dB Differential resistance TRD 0.6 1.1 1.6 dB LNmTECR 0[RATIO_P ST1Q]=0b0 0011 3 3.5 4 dB LNmTECR 0[RATIO_P ST1Q]=0b0 1000 4.1 4.6 5.1 dB LNmTECR 0[RATIO_P ST1Q]=0b0 1010 5.5 6.0 6.5 dB LNmTECR 0[RATIO_P ST1Q]=0b0 1100 9 9.5 10 dB LNmTECR 0[RATIO_P ST1Q]=0b1 0000 80 100 120 Ω - Notes: 1. For recommended operating conditions, see Table 4. 3.10.3.2.2 XFI receiver DC electrical characteristics This table defines the XFI receiver DC electrical characteristics. Table 39. XFI receiver DC electrical characteristics 2 Parameter Symbol Min Typical Max Unit Notes Input differential voltage VRX-DIFF 110 - 1050 mV 1 Differential resistance RRD 80 100 120 Ω - 1. Measured at receiver 2. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 87 Electrical characteristics 3.10.3.3 XFI AC timing specifications This section describes the AC timing specifications for XFI. 3.10.3.3.1 XFI transmitter AC timing specifications This table defines the XFI transmitter AC timing specifications. RefClk jitter is not included. Table 40. XFI transmitter AC timing specifications1 Parameter Symbol Min Typical Max Unit Transmitter baud rate TBAUD 10.3125 - 100ppm 10.3125 10.3125 + 100ppm Gb/s Unit Interval UI - 96.96 - ps Deterministic jitter DJ - - 0.15 UI p-p Total jitter TJ - - 0.30 UI p-p Notes: 1. For recommended operating conditions, see Table 4. 3.10.3.3.2 XFI receiver AC timing specifications This table defines the XFI receiver AC timing specifications. RefClk jitter is not included. Table 41. XFI receiver AC timing specifications3 Parameter Symbol Min Typical Max Unit Notes Receiver baud rate RBAUD 10.3125 100ppm 10.3125 10.3125 + 100ppm Gb/s - Unit Interval UI - 96.96 - ps - Total non-EQJ jitter TNON-EQJ - - 0.45 UI p-p 1 Total jitter tolerance TJ - - 0.65 UI p-p 1, 2 1. The total jitter (TJ) consists of Random Jitter (RJ), Duty Cycle Distortion (DCD), Periodic Jitter (PJ), and Inter symbol Interference (ISI). Non-EQJ jitter can include duty cycle distortion (DCD), random jitter (RJ), and periodic jitter (PJ). Non-EQJ jitter is uncorrelated to the primary data stream with exception of the DCD and so cannot be equalized by the receiver under test. It can exhibit a wide spectrum. Non - EQJ = TJ - ISI = RJ + DCD + PJ 2. The XFI channel has a loss budget of 9.6 dB @5.5GHz. The channel loss including connector @ 5.5GHz is 6dB. The channel crosstalk and reflection margin is 3.6dB. Manual tuning of TX Equalization and amplitude will be required for performance optimization. 3. For recommended operating conditions, see Table 4. This figure shows the sinusoidal jitter tolerance of XFI receiver. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 88 NXP Semiconductors Electrical characteristics Sinuosidal Jitter Tolerance (UIp-p) 1.13x 0.2 + 0.1 , f in MHz f -20 dB/Dec 0.17 0.05 0.04 4 8 27.2 80 Frequency (MHz) Figure 20. XFI host receiver input sinusoidal jitter tolerance 3.10.4 10GBase-KR interface This section describes the 10GBase-KR clocking requirements and its DC and AC electrical characteristics. 3.10.4.1 10GBase-KR clocking requirements for SDn_REF_CLKn_P and SDn_REF_CLKn_N Only SerDes 1 (SD1_REF_CLK1_P and SD1_REF_CLK1_N) may be used for SerDes 10GBase-KR configurations based on the RCW Configuration field SRDS_PRTCL. For more information on these specifications, see SerDes reference clocks. 3.10.4.2 10GBase-KR DC electrical characteristics This section describes the DC electrical characteristics for 10GBase-KR. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 89 Electrical characteristics 3.10.4.2.1 10GBase-KR transmitter DC electrical characteristics This table defines the 10GBase-KR transmitter DC electrical characteristics. Table 42. 10GBaseKR transmitter DC electrical characteristics (XVDD = 1.35 V)1 Parameter Symbol Min Typical Max Unit Notes Output differential voltage VTX-DIFF 800 - 1200 mV LNmTECR 0[AMP_RE D]= 0b000000 De-emphasized differential output VTX-DE- 0.6 1.1 1.6 dB - voltage (ratio) RATIO-1.14dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-3.5dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-4.66dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-6.0dB De-emphasized differential output VTX-DE- voltage (ratio) RATIO-9.5dB Differential resistance TRD LNmTECR 0[RATIO_P ST1Q]=0b0 0011 3 3.5 4 dB LNmTECR 0[RATIO_P ST1Q]=0b0 1000 4.1 4.6 5.1 dB LNmTECR 0[RATIO_P ST1Q]=0b0 1010 5.5 6.0 6.5 dB LNmTECR 0[RATIO_P ST1Q]=0b0 1100 9 9.5 10 dB LNmTECR 0[RATIO_P ST1Q]=0b1 0000 80 100 120 Ω - 1. For recommended operating conditions, see Table 4. 3.10.4.2.2 10GBase-KR receiver DC electrical characteristics This table defines the 10GBase-KR receiver DC electrical characteristics. Table 43. 10GBase-KR receiver DC electrical characteristics1 Parameter Input differential voltage Symbol VRX-DIFF Min - Typical - Max 1200 Unit mV Notes - Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 90 NXP Semiconductors Electrical characteristics Table 43. 10GBase-KR receiver DC electrical characteristics1 (continued) Parameter Differential resistance Symbol RRD Min Typical 80 - Max 120 Unit Ω Notes - 1. For recommended operating conditions, see Table 4. 3.10.4.3 10GBase-KR AC timing specifications This section describes the AC timing specifications for 10GBase-KR. 3.10.4.3.1 10GBase-KR transmitter AC timing specifications This table defines the 10GBase-KR transmitter AC timing specifications. RefClk jitter is not included. Table 44. 10GBase-KR transmitter AC timing specifications1 Parameter Symbol Transmitter baud rate TBAUD Min Typical Max Unit 10.3125 - 100 ppm 10.3125 10.3125 + 100 ppm Gb/s Uncorrelated high probability jitter/Random UHPJ/RJ jitter - - 0.15 UI p-p Deterministic jitter DJ - - 0.15 UI p-p Total jitter TJ - - 0.30 UI p-p 1. For recommended operating conditions, see Table 4. 3.10.4.3.2 10GBase-KR receiver AC timing specifications This table defines the 10GBase-KR receiver AC timing specifications. RefClk jitter is not included. Table 45. 10GBase-KR receiver AC timing specifications2 Parameter Symbol Min Typical Max Unit Notes Receiver baud rate RBAUD 10.3125 - 100 ppm 10.3125 10.3125 + 100 Gb/s ppm - Random jitter RJ - - 0.130 UI p-p - Sinusodial jitter, maximum SJ-max - - 0.115 UI p-p - Duty cycle distortion DCD - - 0.035 UI p-p - Total jitter TJ - - See Note 1 UI p-p 1 1. The total jitter (TJ) is per Interference tolerance test IEEE Standard 802.3ap-2007 specified in Annex 69A. 2. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 91 Electrical characteristics 3.10.5 1000Base-KX interface This section discusses the electrical characteristics for the 1000Base-KX. Only ACcoupled operation is supported. 3.10.5.1 1000Base-KX DC electrical characteristics 3.10.5.1.1 1000Base-KX Transmitter DC Specifications This table describes the 1000Base-KX SerDes transmitter DC specification at TP1 per IEEE Std 802.3ap-2007. Transmitter DC characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N). Table 46. 1000Base-KX Transmitter DC Specifications Parameter Symbols Min Typ Max Units Notes Output differential voltage VTX-DIFFp-p 800 - 1600 mV 1 Differential resistance TRD 80 100 120 ohm - Notes: 1. SRDSxLNmTECR0[AMP_RED]=00_0000. 2. For recommended operating conditions, see Table 4. 3.10.5.1.2 1000Base-KX Receiver DC Specifications This table provides the 1000Base-KX receiver DC timing specifications. Table 47. 1000Base-KX Receiver DC Specifications Parameter Symbols Min Typical Max Units Notes Input differential voltage VRX-DIFFp-p - - 1600 mV 1 Differential resistance TRDIN 80 - 120 ohm - Notes: 1. For recommended operating conditions, see Table 4. 3.10.5.2 1000Base-KX AC electrical characteristics QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 92 NXP Semiconductors Electrical characteristics 3.10.5.2.1 1000Base-KX Transmitter AC Specifications This table provides the 1000Base-KX transmitter AC specification. Table 48. 1000Base-KX Transmitter AC Specifications Parameter Symbols Min Typical Max Units Notes Baud Rate TBAUD 1.25-100ppm 1.25 1.25+100pp Gb/s m - Uncorrelated High Probability Jitter/ Random Jitter TUHPJTRJ - - 0.15 UI p-p - Deterministic Jitter TDJ - - 0.10 UI p-p - Total Jitter TTJ - - 0.25 UI p-p 1 Notes: 1. Total jitter is specified at a BER of 10-12. 2. For recommended operating conditions, see Table 4. 3.10.5.2.2 1000Base-KX Receiver AC Specifications This table provides the 1000Base-KX receiver AC specification with parameters guided by IEEE Std 802.3ap-2007. Table 49. 1000Base-KX Receiver AC Specifications Parameter Symbols Min Typical Max Units Notes Receiver Baud Rate TBAUD 1.25-100ppm 1.25 1.25+100pp Gb/s m - Random Jitter RRJ - - 0.15 UI p-p 1 Sinusoidal Jitter, maximum RSJ-max - - 0.10 UI p-p 2 Total Jitter RTJ - - See Note 3 UI p-p 2 Notes: 1. Random jitter is specified at a BER of 10-12. 2. The receiver interference tolerance level of this parameter shall be measured as described in Annex 69A of the IEEE Std 802.3ap-2007. 3. Per IEEE 802.3ap-clause 70. 4. The AC specifications do not include Refclk jitter. 5. For recommended operating conditions, see Table 4. 3.10.6 RGMII electrical specifications This section describes the electrical characteristics for the RGMII interface. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 93 Electrical characteristics 3.10.6.1 RGMII DC electrical characteristics This table provides the DC electrical characteristics for the RGMII interface at LVDD = 2.5 V. Table 50. RGMII DC electrical characteristics (LVDD = 2.5 V)3 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (LVIN=0 V or LVIN= LVDD) IIH — ±50 µA 2 Output high voltage (LVDD = min,IOH = -1.0 mA) VOH 2.00 — V Output low voltage (LVDD = min, IOL = 1.0 mA) VOL — 0.4 V Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 4. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for the RGMII interface at LVDD = 1.8 V. Table 51. RGMII DC electrical characteristics (LVDD = 1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (LVIN = 0 V or LVIN= LVDD) IIN — ±50 µA 2 Output high voltage (LVDD = min, IOH = -0.5 mA) VOH 1.35 — V Output low voltage (LVDD = min, IOL = 0.5 mA) VOL — 0.4 V Notes: 1. The min VIL and max VIH values are based on the min and max LVIN values found in Table 4. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.10.6.2 RGMII AC timing specifications This table provides the RGMII AC timing specifications. Table 52. RGMII AC timing specifications (LVDD = 2.5 /1.8 V)8 Parameter/Condition Data to clock output skew (at transmitter) Symbol1 tSKRGT_TX Min -500 Typ 0 Max 500 Unit ps Notes 7 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 94 NXP Semiconductors Electrical characteristics Table 52. RGMII AC timing specifications (LVDD = 2.5 /1.8 V)8 (continued) Parameter/Condition Symbol1 Min Typ Max Unit Notes Data to clock input skew (at receiver) tSKRGT_RX 1.0 — 2.6 ns 2, 9 Clock period duration tRGT 7.2 8.0 8.8 ns 3 Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 4 Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % — Rise time (20%-80%) tRGTR — — 0.75 ns 5, 6 Fall time (20%-80%) tRGTF — — 0.75 ns 5, 6 Notes: 1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so, additional PCB delay is probably not needed. 3. For 10 Mbps and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Applies to inputs and outputs. 6. The system/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. 7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300 ppm. 8. For recommended operating conditions, see Table 4. 9. For 10 Mbps and 100 Mbps, the max value is unspecified. This figure shows the RGMII AC timing and multiplexing diagrams. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 95 Electrical characteristics tRGTH tRGT GTX_CLK (At MAC, output) tSKRGT_TX TXD S [8:5][3:0] TXD[7:4][3:0] (At MAC, output) TX_CTL (At MAC, output) tSKRGT_TX TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR PHY equivalent to tSKRGT_RX PHY equivalent to tSKRGT_RX TX_CLK (At PHY, input) tRGTH tRGT RX_CLK (At PHY, output) RXD[8:5][3:0] RXD[7:4][3:0] (At PHY, output) RX_CTL (At PHY, output) RXD[8:5] RXD[3:0] RXD[7:4] PHY equivalent to tSKRGT_TX RXD[4] RXDV PHY equivalent to tSKRGT_TX RXD[9] RXERR tSKRGT_RX tSKRGT_RX RX_CLK (At MAC, input) Figure 21. RGMII AC timing and multiplexing diagrams Warning NXP guarantees timings generated from the MAC. Board designers must ensure delays needed at the PHY or the MAC. 3.10.7 Ethernet management interface (EMI) This section describes the electrical characteristics for the Ethernet Management Interface (EMI) interface. Both the interfaces (EMI1 and EMI2) interface timing is compatible with IEEE Std 802.3™ clause 22. 3.10.7.1 Ethernet management interface 1 (EMI1) This section describes the electrical characteristics for the EMI1 interface. The EMI1 interface timing is compatible with IEEE Std 802.3™ clause 22. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 96 NXP Semiconductors Electrical characteristics 3.10.7.1.1 EMI1 DC electrical characteristics This section describes the DC electrical characteristics for EMI1_MDIO and EMI1_MDC. The pins are available on LVDD. See Table 4 for operating voltages. This table provides the EMI1 DC electrical characteristics when LVDD = 2.5 V. Table 53. EMI1 DC electrical characteristics (LVDD = 2.5 V)3 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (LVIN = 0 or LVIN = LVDD) IIN — ±50 µA 2 Output high voltage (LVDD = min, IOH = -1.0 mA) VOH 2.00 — V — Output low voltage (LVDD = min, IOL = 1.0 mA) VOL — 0.40 V — Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 4. 2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the EMI1 DC electrical characteristics when LVDD = 1.8 V. Table 54. EMI1 DC electrical characteristics (LVDD = 1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (LVIN = 0 V or LVIN = LVDD) IIN — ±50 µA 2 Output high voltage (LVDD = min, IOH = -0.5 mA) VOH 1.35 — V Output low voltage (LVDD = min, IOL = 0.5 mA) VOL — 0.4 V Notes: 1. The min VIL and max VIH values are based on the min and max LVIN respective values found in Table 4. 2. The symbol LVIN represents the LVIN symbols referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.10.7.1.2 EMI1 AC timing specifications This table provides the EMI1 AC timing specifications. Table 55. EMI1 AC timing specifications5 Parameter/Condition MDC frequency Symbol1 fMDC Min — Typ — Max 2.5 Unit MHz Notes 2 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 97 Electrical characteristics Table 55. EMI1 AC timing specifications5 (continued) Symbol1 Parameter/Condition Min Typ — Max — Unit MDC clock pulse width high tMDCH 160 ns MDC to MDIO delay tMDKHDX (Y+5) x tenet_clk - 4 — (Y+5) x tenet_clk + 4 ns MDIO to MDC setup time tMDDVKH 8 — — ns MDIO to MDC hold time tMDDXKH 2.6 — — ns Notes — 3 6 Notes: 1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. 2. This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG[MDIO_CLK_DIV] field determines the clock frequency of the MgmtClk Clock EC_MDC. 3. Ethernet clock period (tenet_clk) is equal to Frame Manager Clock period (tFMAN_clk) 4. Y is the value programmed to adjust hold time by MDIO_CFG[MDIO_HOLD]. 5. For recommended operating conditions, see Table 4. 6. See Ethernet A-010717 erratum. This figure shows the Ethernet management interface 1 timing diagram tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX Figure 22. Ethernet management interface 1 timing diagram 3.10.7.2 Ethernet management interface 2 (EMI2) This section describes the electrical characteristics for the EMI2 interface. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 98 NXP Semiconductors Electrical characteristics The EMI2 interface timing is compatible with IEEE Std 802.3™ clause 45. 3.10.7.2.1 EMI2 DC electrical characteristics This section describes the DC electrical characteristics for EMI2_MDIO and EMI2_MDC. The pins are available on TVDD. See Table 4 for operating voltages. This table provides the EMI2 DC electrical characteristics when TVDD = 2.5 V. Table 56. EMI2 DC electrical characteristics (TVDD = 2.5 V)4 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 x TVDD — V 1 Input low voltage VIL — 0.2 x TVDD V 1 Input current (TVIN = 0 or TVIN = TVDD) IIN — ±50 µA 2, 3 Output high voltage (TVDD = min, IOH = -1.0 mA) VOH 2.00 — V — Output low voltage (TVDD = min, IOL = 1.0 mA) VOL — 0.4 V — Notes: 1. The min VIL and max VIH values are based on the respective min and max TVIN values found in Table 4. 2. The symbol VIN, in this case, represents the TVIN symbols referenced in Recommended operating conditions. 3. The symbol TVDD, in this case, represents the TVDD symbols referenced in Recommended operating conditions. 4. For recommended operating conditions, see Table 4. This table provides the EMI2 DC electrical characteristics when TVDD = 1.8 V. Table 57. EMI2 DC electrical characteristics (TVDD = 1.8 V)4 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x TVDD — V 1 Input low voltage VIL — 0.2 x TVDD V 1 Input current (TVIN = 0 V or TVIN = TVDD) IIN — ±50 µA 2, 3 Output high voltage (TVDD = min, IOH = -0.5 mA) VOH 1.35 — V 3 Output low voltage (TVDD = min, IOL = 0.5 mA) VOL — 0.4 V 3 Notes: 1. The min VIL and max VIH values are based on the min and max TVIN respective values found in Table 4. 2. The symbol TVIN represents the TVIN symbols referenced in Recommended operating conditions. 3. The symbol TVDD, in this case, represents the TVDD symbols referenced in Recommended operating conditions. 4. For recommended operating conditions, see Table 4. This table provides the EMI2 DC electrical characteristics when TVDD = 1.2 V. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 99 Electrical characteristics Table 58. EMI2 DC electrical characteristics (TVDD = 1.2 V) 1 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x TVDD — V — Input low voltage VIL — 0.2 x TVDD V — Output low current (VOL = 0.2 V) IOL 4 mA — Output high voltage (TVDD = min, IOH = -100uA) VOH 1.0 — V — Output low voltage (TVDD = min, IOL = 100 uA) VOL — 0.2 V — Input Capacitance CIN — 10 pF — Notes: 1. For recommended operating conditions, see Table 4. 3.10.7.2.2 EMI2 AC timing specifications This table provides the EMI2 AC timing specifications. Table 59. EMI2 AC timing specifications6 Symbol1 Parameter/Condition Min Typ Max Unit Notes MDC frequency fMDC — — 2.5 MHz 2 MDC clock pulse width high tMDCH 160 — — ns — MDC to MDIO delay tMDKHDX (Y+5) x tenet_clk 25 — (Y+5) x tenet_clk) + ns 25 3, 4 MDIO to MDC setup time tMDDVKH 36 — — ns 5 MDIO to MDC hold time (TVDD=1.2V) tMDDXKH 2.6 — — ns 7 MDIO to MDC hold time (TVDD=1.8V / 2.5V) tMDDXKH 1.1 — — ns 7 Notes: 1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. 2. This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG [MDIO_CLK_DIV] field determines the clock frequency of the MgmtClk Clock EC_MDC. 3. Ethernet clock period (tenet_clk) is equal to Frame Manager Clock period (tFMAN_clk) 4. Y is the value programmed to adjust hold time by MDIO_CFG[MDIO_HOLD]. 5. The setup time tMDDVKH is measured at following load conditions • For MDC = 65 pf and for MDIO =75 pf @1.2 V open drain configuration 6. For recommended operating conditions, see Table 4. 7. See Ethernet A-010717 erratum. This figure shows the Ethernet management interface 2 timing diagram QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 100 NXP Semiconductors Electrical characteristics tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX Figure 23. Ethernet management interface 2 timing diagram 3.10.8 IEEE 1588 electrical specifications 3.10.8.1 IEEE 1588 DC electrical characteristics This table provides the IEEE 1588 DC electrical characteristics when operating at LVDD = 2.5 V supply. Table 60. IEEE 1588 DC electrical characteristics(LVDD = 2.5 V)3 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (LVIN= 0 V or LVIN= LVDD) IIH — ±50 µA 2 Output high voltage (LVDD = min, IOH = -1.0 mA) VOH 2.00 — V — Output low voltage (LVDD = min, IOL = 1.0 mA) VOL — 0.40 V — Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 4. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the IEEE 1588 DC electrical characteristics when operating at LVDD = 1.8 V supply. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 101 Electrical characteristics Table 61. IEEE 1588 DC electrical characteristics(LVDD = 1.8 V)3 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (LVIN= 0 V or LVIN= LVDD) IIH — ±50 µA 2 Output high voltage (LVDD = min, IOH = -0.5 mA) VOH 1.35 — V — Output low voltage (LVDD = min, IOL = 0.5 mA) VOL — 0.40 V — Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 4. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.10.8.2 IEEE 1588 AC timing specifications This table provides the IEEE 1588 AC timing specifications. Table 62. IEEE 1588 AC timing specifications5 Parameter/Condition Symbol Min Typ Max Unit Notes TSEC_1588_CLK_IN clock period tT1588CLK 5.0 — TRX_CLK x 7 ns 1, 3 TSEC_1588_CLK_IN duty cycle tT1588CLKH/ tT1588CLK 40 50 60 % 2 TSEC_1588_CLK_IN peak-to-peak jitter tT1588CLKINJ — — 250 ps — Rise time TSEC_1588_CLK_IN (20%-80%) tT1588CLKINR 1.0 — 2.0 ns — Fall time TSEC_1588_CLK_IN (80%-20%) tT1588CLKINF 1.0 — 2.0 ns — TSEC_1588_CLK_OUT clock period tT1588CLKOUT 5.0 — — ns 4 TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/ tT1588CLKOUT 30 50 70 % — TSEC_1588_PULSE_OUT1/2, tT1588OV 0 — 4.0 ns — tT1588TRIGH 2 x tT1588CLK_MAX — — ns 3 TSEC_1588_ALARM_OUT1/2 TSEC_1588_TRIG_IN1/2 pulse width Notes: 1. TRX_CLK is the maximum clock period of the ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference manual for a description of TMR_CTRL registers. 2. This needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference manual for a description of TMR_CTRL registers. 3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively. 4. There are three input clock sources for 1588: TSEC_1588_CLK_IN, RTC, and MAC clock / 2. When using TSEC_1588_CLK_IN, the minimum clock period is 2 x tT1588CLK. 5. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 102 NXP Semiconductors Electrical characteristics This figure shows the data and command output AC timing diagram. tT1588CLKOUT tT1588CLKOUTH TSEC_1588_CLK_OUT tT1588OV TSEC_1588_PULSE_OUT1/2 TSEC_1588_ALARM_OUT1/2 Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is counted starting at the falling edge. Figure 24. IEEE 1588 output AC timing This figure shows the data and command input AC timing diagram. tT1588CLK TSEC_1588_CLK_IN tT1588CLKH TSEC_1588_TRIG_IN1/2 tT1588TRIGH Figure 25. IEEE 1588 input AC timing 3.11 USB 3.0 interface This section describes the DC and AC electrical specifications for the USB 3.0 interface. 3.11.1 USB 3.0 PHY transceiver supply DC voltage This table provides the DC electrical characteristics for the USB 3.0 interface when operating at USB_HVDD = 3.3 V. Table 63. USB 3.0 PHY transceiver supply DC voltage (USB_HVDD = 3.3 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Input current (USB_HVIN = 0 V or USB_HVIN= USB_HVDD) IIN — ±50 µA 2 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 103 Electrical characteristics Table 63. USB 3.0 PHY transceiver supply DC voltage (USB_HVDD = 3.3 V)3 (continued) Parameter Symbol Min Max Unit Notes Output high voltage (USB_HVDD = min, IOH = -2 mA) VOH 2.8 — V — Output low voltage (USB_HVDD = min, IOL = 2 mA) VOL — 0.3 V — Notes: 1. The min VILand max VIH values are based on the respective min and max USB_HVIN values found in Table 4. 2. The symbol USB_HVIN, in this case, represents the USB_HVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.11.2 USB 3.0 DC electrical characteristics This table provides the USB 3.0 transmitter DC electrical characteristics at package pins. Table 64. USB 3.0 transmitter DC electrical characteristics1 Characteristic Symbol Differential output voltage Vtx-diff-pp Low-power differential output voltage Min Max Unit 1000 1200 mVp-p Vtx-diff-pp-low 400 — 1200 mVp-p Tx de-emphasis Vtx-de-ratio 3 — 4 dB Differential impedance ZdiffTX 72 100 120 Ohm Tx common mode impedance RTX-DC 18 — 30 Ohm TTX-CM-DC- — — 200 mV 0 — 10 mV Absolute DC common mode voltage between U1 and U0 800 Nom ACTIVEIDLEDELTA DC electrical idle differential output voltage VTX-IDLEDIFF-DC Note: 1. For recommended operating conditions, see Table 4. This table provides the USB 3.0 receiver DC electrical characteristics at the Rx package pins. Table 65. USB 3.0 receiver DC electrical characteristics Characteristic Symbol Min Nom Max Unit Notes Differential Rx input impedance RRX-DIFF-DC 72 100 120 Ohm — Receiver DC common mode impedance RRX-DC — 30 Ohm — DC input CM input impedance for V > 0 during reset or power down ZRX25 K HIGH-IMPDC — — Ohm — 18 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 104 NXP Semiconductors Electrical characteristics Table 65. USB 3.0 receiver DC electrical characteristics (continued) Characteristic LFPS detect threshold Symbol Min VRX-IDLE- 100 DET-DCDIFFpp Nom — Max 300 Unit mV Notes 1 Note: 1. Below the minimum is noise. Must wake up above the maximum. 3.11.3 USB 3.0 AC timing specifications This table provides the USB 3.0 transmitter AC timing specifications at package pins. Table 66. USB 3.0 transmitter AC timing specifications1 Parameter Symbol Min Nom Max Unit Notes Speed — — 5.0 — Gb/s — Transmitter eye tTX-Eye 0.625 — — UI — Unit interval UI 199.94 — 200.06 ps 2 AC coupling capacitor AC coupling capacitor 75 — 200 nF — Note: 1. For recommended operating conditions, see Table 4. 2. UI does not account for SSC-caused variations. This table provides the USB 3.0 receiver AC timing specifications at Rx package pins. Table 67. USB 3.0 receiver AC timing specifications1 Parameter Symbol Unit interval UI Min 199.94 Nom — Max 200.06 Unit ps Notes 2 Notes: 1. For recommended operating conditions, see Table 4. 2. UI does not account for SSC-caused variations. 3.11.4 USB 3.0 reference clock requirements There are two options for the reference clock of USB PHY: SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B. For more information, see USB 3.0 reference clock requirements. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 105 Electrical characteristics 3.11.5 USB 3.0 LFPS specifications This table provides the key LFPS electrical specifications at the transmitter. Table 68. LFPS electrical specifications at the transmitter Parameter Symbol Min Typ Max Unit Notes Period tPeriod 20 — 100 ns — Peak-to-peak differential amplitude VTX-DIFF-PP-LFPS 800 — 1200 mV — Rise/fall time tRiseFall20-80 — — 4 ns 1 Duty cycle Duty cycle 40 — 60 % 1 Note: 1. Measured at compliance TP1. See Figure 26 for details. This figure shows the transmit normative setup with reference channel as per USB 3.0 specifications. Measurement Tool SMP Reference Test Channel Reference Cable DUT TP1 Figure 26. Transmit normative setup 3.12 Integrated Flash Controller This section describes the DC and AC electrical specifications for the integrated flash controller. 3.12.1 Integrated Flash Controller DC electrical characteristics This table provides the DC electrical characteristics for the integrated flash controller. Table 69. Integrated Flash Controller DC electrical characteristics (1.8 V)3 Parameter Symbol Min Max Unit Note Input high voltage VIH 0.7 x OVDD - V 1 Input low voltage VIL - 0.3 x OVDD V 1 Input current IIN - ±50 μA 2 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 106 NXP Semiconductors Electrical characteristics Table 69. Integrated Flash Controller DC electrical characteristics (1.8 V)3 (continued) Parameter Symbol Min Max Unit Note (VIN = 0 V or VIN = OVDD) Output high voltage VOH 1.6 - V - VOL - 0.32 V - (OVDD = min, IOH = -0.5 mA) Output low voltage (OVDD = min, IOL = 0.5 mA) NOTE: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 4. 2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.12.2 Integrated Flash Controller AC timing specifications This section describes the AC timing specifications for the integrated flash controller. 3.12.2.1 Test condition The figure below provides the AC test load for the integrated flash controller. Output Respective supply / 2 Z0= 50 Ω RL = 50 Ω Figure 27. Integrated Flash Controller AC test load 3.12.2.2 IFC AC timing specifications (GPCM/GASIC) This table describes the input AC timing specifications for the IFC-GPCM and IFCGASIC interface. Table 70. Integrated flash controller input timing specifications for GPCM and GASIC mode (OVDD = 1.8 V)1 Parameter Input setup Symbol tIBIVKH1 Min 4 Max - Unit ns Notes - Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 107 Electrical characteristics Table 70. Integrated flash controller input timing specifications for GPCM and GASIC mode (OVDD = 1.8 V)1 (continued) Parameter Symbol Input hold tIBIXKH1 Min 1 Max - Unit ns Notes - NOTE: 1. For recommended operating conditions, see Table 4. This figure shows the input AC timing diagram for the IFC-GPCM, IFC-GASIC interface. IFC_CLK[0] tIBIXKH1 t IBIVKH 1 Input Signals Figure 28. IFC-GPCM, IFC-GASIC input AC timing specifictions This table describes the output AC timing specifications for the IFC-GPCM and IFCGASIC interfaces. Table 71. Integrated flash controller IFC-GPCM and IFC-GASIC interface output timing specifications (OVDD = 1.8 V)2 Parameter Symbol Min Max Unit Notes IFC_CLK cycle time tIBK 10 - ns - IFC_CLK duty cycle tIBKH/ tIBK 45 55 % - Output delay tIBKLOV1 - 1.5 ns - Output hold tIBKLOX - -2 ns 1 IFC_CLK[0] to IFC_CLK[m] skew tIBKSKEW 0 ±75 ps - NOTE: 1. The output hold is negative. This means that output transition happens earlier than the falling edge of IFC_CLK. 2. For recommended operating conditions, see Table 4. This figure shows the output AC timing diagram for the IFC-GPCM and IFC-GASIC interface. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 108 NXP Semiconductors Electrical characteristics IFC_CLK_0 t IBKLOV1 t IBKLOX Output Signals Figure 29. IFC-GPCM, IFC-GASIC signals 3.12.2.3 IFC AC timing specifications (NOR) This table describes the input timing specifications for the IFC-NOR interface. Table 72. Integrated flash controller input timing specifications for NOR mode (OVDD = 1.8 V)2 Parameter Symbol Min Max Unit Notes Input setup tIBIVKH2 (2 x tIP_CLK) + 2 - ns 1 Input hold tIBIXKH2 (1 x tIP_CLK) + 1 - ns 1 Notes: 1. tIP_CLK is the period of ip clock (not the IFC_CLK) on which IFC is running. 2. For recommended operating conditions, see Table 4. 3. The NOR flash state machine will de-assert OE_B once the flash controller samples data. Hold time tIBIXKH2 given in the datasheet is not a requirement for customer but rather an information used internally for test purpose. The figure below shows the AC input timing diagram for input signals for the IFC-NOR interface. Here TRAD is a programmable delay parameter. See the IFC section of the chip reference manual for more information. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 109 Electrical characteristics (TRAD+1) x tIP_CLK OE_B tIBIXKH2 tIBIVKH2 AD (Data Phase, Read) Figure 30. IFC-NOR interface input AC timings This table describes the output AC timing specifications of IFC-NOR interface. Table 73. Integrated flash controller IFC-NOR interface output timing specifications (OVDD = 1.8 V)2 Parameter Symbol Output delay tIBKLOV2 Min - Max ±1.5 Unit ns Notes 1 NOTE: 1. This effectively means that a signal change may appear anywhere within ±tIBKLOV2 (max) duration, from the point where it's expected to change. 2. For recommended operating conditions, see Table 4. The figure below shows the AC timing diagram for IFC-NOR interface output signals. The timing specs have been illustrated here by taking timings between two signals, CS_B and OE_B as an example. In a read operation, OE_B is supposed to change the TACO (a programmable delay; see the IFC section of the chip reference manual for more information) time after CS_B. Because of the skew between the signals, OE_B may change anywhere within the window of time defined by tIBKLOV2. This concept applies to other IFC-NOR interface output signals as well. The diagram is an example that shows the skew between any two chronological toggling signals as per the protocol. The list of IFC-NOR output signals is as follows: NRALE, NRAVD_B, NRWE_B, NROE_B, CS_B, AD (Address phase). CS_B TACO tIBKLOV2 OE_B Figure 31. IFC-NOR interface output AC timings QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 110 NXP Semiconductors Electrical characteristics 3.12.2.4 IFC AC timing specifications (NAND) This table describes the input timing specifications of the IFC-NAND interface. Table 74. Integrated flash controller input timing specifications for NAND mode (OVDD = 1.8 V)2 Parameter Symbol Min Max Unit Notes Input setup tIBIVKH3 (2 x tIP_CLK) + 2 - ns 1 Input hold tIBIXKH3 1 - ns 1 IFC_RB_B pulse width tIBCH 2 - tIP_CLK 1 NOTE: 1. tIP_CLK is the period of ip clock on which IFC is running. 2. For recommended operating conditions, see Table 4. The figure below shows the AC input timing diagram for input signals of IFC-NAND interface. Here TRAD is a programmable delay parameter. See the IFC section of the chip reference manual for more information. Figure 32. IFC-NAND interface input AC timings NOTE tIP_CLK is the period of ip clock (not the IFC_CLK) on which IFC is running. This table describes the output AC timing specifications for the IFC-NAND interface. Table 75. Integrated flash controller IFC-NAND interface output timing specifications (OVDD = 1.8 V)2 Parameter Output delay Symbol tIBKLOV3 Min - Max ±1.5 Unit ns Notes 1 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 111 Electrical characteristics Table 75. Integrated flash controller IFC-NAND interface output timing specifications (OVDD = 1.8 V)2 (continued) Parameter Symbol Min Max Unit Notes NOTE: 1. This effectively means that a signal change may appear anywhere within tIBKLOV3 (min) to tIBKLOV3 (max) duration, from the point where it's expected to change. 2. For recommended operating conditions, see Table 4. The figure below shows the AC timing diagram for output signals of IFC-NAND interface.The timing specs are shown here by taking the timings between two signals, CS_B and CLE as an example. CLE is supposed to change TCCST (a programmable delay; see the IFC section of the chip reference manual for more information) time after CS_B. Because of the skew between the signals, CLE may change anywhere within window of time defined by tIBKLOV3. This concept applies to other output signals of the IFC-NAND interface as well. The diagram is an example to show the skew between any two chronological toggling signals as per the protocol. The list of output signals is as follows: NDWE_B, NDRE_B, NDALE, WP_B, NDCLE, CS_B, and AD. Figure 33. IFC-NAND interface output AC timings 3.12.2.5 IFC-NAND SDR AC timing specifications This table describes the AC timing specifications for the IFC-NAND SDR interface. These specifications are compliant to the SDR mode of the ONFI specification revision 3.0. Table 76. Integrated flash controller IFC-NAND SDR interface AC timing specifications (OVDD = 1.8 V) Parameter Symbol I/O Min Max Unit Notes Address cycle to data loading time tADL O TADLE 1500(ps) TADLE + 1500(ps) tIP_CLK Figure 34 ALE hold time tALH O TWCHT 1500(ps) TWCHT + 1500(ps) tIP_CLK Figure 35 ALE setup time tALS O TWP - 1500(ps) TWP + 1500(ps) tIP_CLK Figure 35 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 112 NXP Semiconductors Electrical characteristics Table 76. Integrated flash controller IFC-NAND SDR interface AC timing specifications (OVDD = 1.8 V) (continued) Parameter Symbol I/O Min Max Unit Notes ALE to RE_n delay tAR O TWHRE 1500(ps) TWHRE + 1500(ps) tIP_CLK Figure 36 CE_n hold time tCH O 5 + 1500(ps) - ns Figure 35 CE_n high to input hi-Z tCHZ I TRHZ - 1500(ps) TRHZ + 1500(ps) tIP_CLK Figure 37 CLE hold time tCLH O TWCHT 1500(ps) TWCHT + 1500(ps) tIP_CLK Figure 35 CLE to RE_n delay tCLR O TWHRE 1500(ps) TWHRE 1500(ps) tIP_CLK Figure 38 CLE setup time tCLS O TWP - 1500(ps) TWP + 1500(ps) tIP_CLK Figure 35 CE_n high to input hold tCOH I 150 - 1500(ps) - ns Figure 37 CE_n setup time tCS O TCS - 1500(ps) TCS + 1500(ps) tIP_CLK Figure 35 Data hold time tDH O TWCHT 1500(ps) TWCHT + 1500(ps) tIP_CLK Figure 35 Data setup time tDS O TWP - 1500(ps) TWP + 1500(ps) tIP_CLK Figure 35 Busy time for Set Features and Get Features tFEAT O - FTOCNT tIP_CLK Figure 39 Output hi-Z to RE_n low tIR O TWHRE 1500(ps) TWHRE + 1500(ps) tIP_CLK Figure 40 Interface and Timing Mode Change time tITC O - FTOCNT tIP_CLK Figure 39 RE_n cycle time tRC O TRP + TREH 1500(ps) TRP + TREH + 1500(ps) tIP_CLK Figure 37 RE_n access time tREA I - (TRAD - 1) + 2(ns) tIP_CLK Figure 37 RE_n high hold time tREH I TREH TREH tIP_CLK Figure 37 RE_n high to input hold tRHOH I 0 - ns Figure 37 RE_n high to WE_n low tRHW O 100 + 1500(ps) - ns Figure 41 RE_n high to input hi-Z tRHZ I TRHZ - 1500(ps) TRHZ + 1500(ps) tIP_CLK Figure 37 RE_n low to input data hold tRLOH I 0 - ns Figure 42 RE_n pulse width tRP O TRP TRP tIP_CLK Figure 37 Ready to data input cycle (data only) tRR O TRR - 1500(ps) TRR + 1500(ps) tIP_CLK Figure 37 Device reset time, tRST (raw NAND) measured from the falling edge of R/B_n to the rising edge of R/B_n. O - FTOCNT tIP_CLK Figure 43 Device reset time, tRST2 (EZ NAND) measured from the falling edge of R/B_n to the rising edge of R/B_n. O - FTOCNT tIP_CLK Figure 43 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 113 Electrical characteristics Table 76. Integrated flash controller IFC-NAND SDR interface AC timing specifications (OVDD = 1.8 V) (continued) Parameter Symbol I/O Min Max Unit Notes (WE_n high or CLK rising tWB edge) to SR[6] low O TWBE + TWH 1500(ps) TWBE + TWH + tIP_CLK 1500(ps) Figure 35 WE_n cycle time tWC O TWP + TWH TWP + TWH tIP_CLK Figure 44 WE_n high hold time tWH O TWH TWH tIP_CLK Figure 44 Command, address, or data input cycle to data output cycle tWHR O TWHRE + TWH - 1500(ps) TWHRE + TWH + 1500(ps) tIP_CLK Figure 45 WE_n pulse width tWP O TWP TWP tIP_CLK Figure 35 WP_n transition to command cycle tWW O TWW - 1500(ps) TWW + 1500(ps) tIP_CLK Figure 46 Data Input hold tIBIXKH4 I 1 Figure 47 - tIP_CLK NOTE: 1. tIP_CLK is the clock period of the IP clock (on which the IFC IP is running). Note that the IFC IP clock does not come out of the device. This figure shows the tADL timing. WE_B RE_B tADL Cycle type ADDR DATA Figure 34. tADL timing This figure shows the command cycle. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 114 NXP Semiconductors Electrical characteristics tCH tCS CE_n tCALS tCALH tCALS tCALH tCSD CLE ALE WE_n tWH tWP RE_t DQS_t tCAS DQ[7:0] tCAH Command Optional complementary signaling Don't Care Figure 35. Command cycle This figure shows the tAR timings. ALE tAR RE_n Figure 36. tAR timings This figure shows the data input cycle timings. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 115 Electrical characteristics tCHZ tCEA CE_n tRP RE_n tCOH tRP tRP tRHOH tREH tRR tRHZ tRC R/B_n tRHZ tREA D0 IOx tRHZ tREA tRHZ tREA D1 Dn Figure 37. Data input cycle timings This figure shows the tCLR timings. CLE tCLR RE_n Figure 38. tCLR timings This figure shows the tWB, tFEAT, tITC, and tRR timings. CLK ALE WR_B Cycle type CMD DATA ADDR tWB tFEAT/tITC tRR RB_B Figure 39. tWB, tFEAT, tITC, and tRR timings This figure shows the read status timings. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 116 NXP Semiconductors Electrical characteristics tCLR CLE tCLH tCLS tCH tCS tCEA CE_n tWP tCHZ WE_n tCOH tWHR RE_n tRHZ tDS tDH tRHOH 70h IO7-0 Status tIR tREA Figure 40. Read status timings This figure shows the tRHW timings. CLK CLE WR_B Cycle type DIN tRHW CMD Figure 41. tRHW timings This figure shows the EDO mode data input cycle timings. tCHZ CE_n tCOH tRP RE_n tREH tRR tRC tREA R/B_n tRHZ tREA tRHOH tRLOH D0 IOx D1 Dn tCEA Figure 42. EDO mode data input cycle timings This figure shows the tWB and tRST timings. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 117 Electrical characteristics CLK CLE ALE W/R# DQ[7:0] DQS CMD tWB tRST R/B# Figure 43. tWB and tRST timings This figure shows the address latch timings. tCLS CLE tCS CE_n tWC tWP tWH WE_n tALS ALE tALH tDH tDS IO0-7 Address Figure 44. Address latch timings This figure shows the tWHR timings. CLE ALE CLK tWHR Cycle type CMD DATA Figure 45. tWHR timings This figure shows the tWW timings. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 118 NXP Semiconductors Electrical characteristics CLK CLE CMD Cycle Type tWW WP# Bus shall be idle Figure 46. tWW timings This figure shows the tIBIXKH4 timings. Figure 47. tIBIXKH4 timings 3.12.2.6 IFC-NAND NVDDR AC timing specification The table below describes the AC timing specifications for the IFC-NAND NVDDR interface. These specifications are compliant to NVDDR mode of ONFI specification revision 3.0. Table 77. Integrated flash controller IFC-NAND NVDDR interface AC timing specifications (OVDD = 1.8 V) Parameter Symbol I/O Min Max Unit Notes Access window of DQ[7:0] tAC from CLK I 3 - 150 (ps) 20 + 150 (ps) ns Figure 51 Address cycle to data loading time I TADL - tIP_CLK Figure 52 tADL Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 119 Electrical characteristics Table 77. Integrated flash controller IFC-NAND NVDDR interface AC timing specifications (OVDD = 1.8 V) (continued) Parameter Symbol I/O Min Max Unit Notes Command, Address, Data tCADf delay (command to command, address to address, command to address, address to command, command/ address to start of data) Fast O TCAD - 150 (ps) TCAD + 150 (ps) tIP_CLK Figure 48 Command, Address, Data tCADs delay (command to command, address to address, command to address, address to command, command/ address to start of data) slow O TCAD - 150 (ps) TCAD + 150 (ps) tIP_CLK Figure 48 Command/address DQ hold time tCAH O 2 + 150 (ps) - ns Figure 48 CLE and ALE hold time tCALH O 2 + 150 (ps) - ns Figure 48 CLE and ALE setup time tCALS O 2 + 150 (ps) - ns Figure 48 Command/address DQ setup time tCAS O 2 + 150 (ps) - ns Figure 48 CE# hold time tCH O 2 + 150 (ps) - ns Figure 48 Average clock cycle time, tCK(avg) or tCK also known as tCK O 10 - ns Figure 48 Absolute clock period, measured from rising edge to the next consecutive rising edge tCK(abs) O tCK(avg) + tJIT(per) min tCK(avg) + tJIT(per) max ns Figure 48 Clock cycle high tCKH(abs) O 0.45 0.55 tCK Figure 48 Clock cycle low tCKL(abs) O 0.45 0.55 tCK Figure 48 Data input end to W/R# high B16 tCKWR O TCKWR - 150 (ps) TCKWR + 150 (ps) tIP_CLK Figure 51 CE# setup time tCS O TCS - 150 (ps) TCS + 150 (ps) tIP_CLK Figure 50 Data DQ hold time tDH O 1050 - ps Figure 50 Access window of DQS from CLK tDQSCK I - 20 + 150 (ps) ns Figure 51 W/R# low to DQS/DQ driven by device tDQSD I -150 (ps) 18 + 150 (ps) ns Figure 51 DQS output high pulse width tDQSH O 0.45 0.55 tCK Figure 50 W/R# high to DQS/DQ tri- tDQSHZ state by device O RHZ - 150 (ps) RHZ + 150 (ps) tIP_CLK Figure 48 DQS output low pulse width O 0.45 0.55 tCK Figure 50 tDQSL Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 120 NXP Semiconductors Electrical characteristics Table 77. Integrated flash controller IFC-NAND NVDDR interface AC timing specifications (OVDD = 1.8 V) (continued) Parameter Symbol I/O Min Max Unit Notes DQS-DQ skew, DQS to last DQ valid, per access tDQSQ I - 1000 ps Figure 51 Data output to first DQS latching transition tDQSS O 0.75 + 150 (ps) 1.25 - 150 (ps) tCK Figure 50 Data DQ setup time tDS O 1050 - ps Figure 50 DQS falling edge to CLK rising - hold time tDSH O 0.2 + 150 (ps) - tCK Figure 50 DQS falling edge to CLK rising - setup time tDSS O 0.2 + 150 (ps) - tCK Figure 50 Input data valid window tDVW I tDVW = tQH tDQSQ - ns Figure 51 Busy time for Set Features and Get Features tFEAT I - FTOCNT tIP_CLK Figure 53 Half-clock period tHP O tHP = min(tCKL, tCKH) ns Figure 51 Interface and Timing Mode Change time tITC I - FTOCNT tIP_CLK Figure 53 The deviation of a given tCK(abs) from tCK(avg) tJIT(per) O -0.5 0.5 ns NA DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH I tQH = tHP tQHS - tIP_CLK Figure 51 Data input cycle to command, address, or data output cycle tRHW O TRHW - tIP_CLK Figure 54 Ready to data input cycle (data only) tRR I TRR - tIP_CLK Figure 53 Device reset time, tRST (raw NAND) measured from the falling edge of R/B# to the rising edge of R/B#. O FTOCNT FTOCNT tIP_CLK Figure 55 Device reset time, tRST2 (EZ NAND) measured from the falling edge of R/B# to the rising edge of R/B#. O FTOCNT FTOCNT tIP_CLK Figure 55 CLK rising edge to SR[6] low tWB O TWB - 150 (ps) TWB + 150 (ps) tIP_CLK Figure 55 Command, address or data output cycle to data input cycle tWHR O TWHR - tIP_CLK Figure 56 DQS write preamble tWPRE O 1.5 - tCK Figure 50 DQS write postamble tWPST O 1.5 - tCK Figure 50 W/R# low to data input cycle tWRCK I TWRCK - 150 (ps) TWRCK + 150 (ps) tIP_CLK Figure 51 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 121 Electrical characteristics Table 77. Integrated flash controller IFC-NAND NVDDR interface AC timing specifications (OVDD = 1.8 V) (continued) Parameter WP# transition to command cycle Symbol tWW I/O Min O Max TWW - 150 (ps) Unit TWW + 150 (ps) tIP_CLK Notes Figure 57 NOTE: 1. tIP_CLK is the clock period of IP clock (on which IFC IP is running). Note that the IFC IP clock does not come out of device. The following diagrams show the AC timing for the IFC-NAND NVDDR interface. tCH tCS CE_n tCALS tCALH tCALS tCALH tCSD CLE ALE WE_n tWH tWP RE_t DQS_t tCAS DQ[7:0] tCAH Command Optional complementary signaling Don't Care Figure 48. Command cycle QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 122 NXP Semiconductors Electrical characteristics tCH tCS CE_B tCALS tCALH tCALS tCALH tCSD CLE ALE WE_B tWP RE_t DQS_t tCAS DQ[7:0] tCAH Address Optional complementary signaling Don't care Figure 49. Address cycle QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 123 Electrical characteristics tCS1 / tCS2 tCH ODT disabled CE_n ODT enabled tCALS or tCALS2 tCALH tCALS or tCALS2 tCALH tCSD CLE ALE WE_n tDBS RE_t tCDQSS tDSC tWPRE tWPST or tWPRE2 tWPSTH DQS_t tDQSH tDQSL tDQSH DQ[7:0] D0 tDS D1 D2 D3 tDH tDQSL tDQSH DN-2 DN-1 tDS DN tDH Optional complementary signaling Don't care Figure 50. Write cycle Figure 51. Read cycle QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 124 NXP Semiconductors Electrical characteristics CLK CLE ALE tADL Cycle type DATA ADDR Figure 52. tADL timings CLK ALE WR_B Cycle type CMD DATA ADDR tWB tFEAT/tITC tRR RB_B Figure 53. tWB, tFEAT, tITC, tRR timings CLK CLE WR_B Cycle type DIN tRHW CMD Figure 54. tRHW timings CLK CLE ALE W/R# DQ[7:0] DQS R/B# CMD tWB tRST Figure 55. tWB and tRST timings QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 125 Electrical characteristics CLE ALE CLK tWHR Cycle type DATA CMD Figure 56. tWHR timings CLK CLE CMD Cycle Type tWW WP# Bus shall be idle Figure 57. tWW timings 3.13 LPUART interface This section describes the DC and AC electrical specifications for the LPUART interface. 3.13.1 LPUART DC electrical characteristics This table provides the DC electrical characteristics for the LPUART interface when operating at DVDD/EVDD = 3.3 V. Table 78. LPUART DC electrical characteristics (DVDD/EVDD = 3.3 V)2 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x D/ EVDD — V 1 Input low voltage VIL — 0.2 x D/EVDD V 1 Input current (D/EVIN = 0 V or D/EVIN = D/EVDD) IIN — ±50 μA — Output high voltage ( IOH = -2.0 mA) VOH 2.4 — V — Output low voltage ( IOL = 2.0 mA) VOL — 0.4 V — Notes: QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 126 NXP Semiconductors Electrical characteristics Table 78. LPUART DC electrical characteristics (DVDD/EVDD = 3.3 V)2 Parameter Symbol Min Max Unit Notes 1. The min VIL and max VIH values are based on the min and max D/EVDD respective values found in Table 4. 2. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for the LPUART interface when operating at EVDD/ DVDD = 1.8 V. Table 79. LPUART DC electrical characteristics (1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x E/ DVDD — V 1 Input low voltage VIL — 0.2 x E/DVDD V 1 Input current (E/DVIN = 0 V or E/DVIN = E/DVDD) IIN — ±50 μA 2 Output high voltage (E/DVDD = min, IOH = -0.5 mA) VOH 1.35 — V — Output low voltage (DVDD = min, IOL = 0.5 mA) VOL — 0.4 V — Notes: 1. The min VIL and max VIH values are based on the min and max E/DVDD respective values found in Table 4. 2. The symbol E/DVIN represents the input voltage of the supply referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.13.2 LPUART AC timing specifications This table provides the AC timing specifications for the LPUART interface. Table 80. LPUART AC timing specifications Parameter Value Unit Notes Minimum baud rate fPLAT/(2 x 32 x 8192) baud 1, 3, 4 Maximum baud rate fPLAT/(2 x 4) baud 1, 2, 4 Notes: 1. fPLAT refers to the internal platform clock. 2. The actual attainable baud rate is limited by the latency of interrupt processing. 3. Every bit can be over sampled with a sample clock rate of 8 and 64 times (software configurable) and each bit is the majority of the values sampled at the sample rate divided by two, (sample rate/2)+1 and (sample rate/2)+2. 4. The 1-to-0 transition during a data word can cause a resynchronization of the sample point. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 127 Electrical characteristics 3.14 DUART interface This section describes the DC and AC electrical specifications for the DUART interface. 3.14.1 DUART DC electrical characteristics This table provides the DC electrical characteristics for the DUART interface at DVDD = 3.3 V. Table 81. DUART DC electrical characteristics (3.3 V)3 Parameter Symbol Min Max Input high voltage VIH 0.7 x DVDD — Input low voltage VIL Input current (DVIN = 0 V or DVIN = DVDD) Unit Notes V 1 — 0.2 x DVDD V 1 IIN — ±50 µA 2 Output high voltage (DVDD = min, IOH = -2.0 mA) VOH 2.4 — V — Output low voltage (DVDD = min, IOL = 2.0 mA) VOL — 0.4 V — Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 4. 2. The symbol DVIN represents the input voltage of the supply referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for the DUART interface at DVDD = 1.8 V. Table 82. DUART DC electrical characteristics (1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x DVDD — V 1 Input low voltage VIL — 0.2 x DVDD V 1 Input current (DVIN = 0 V or DVIN = DVDD) IIN — ±50 µA 2 Output high voltage (DVDD = min, IOH = -0.5 mA) VOH 1.35 — V — Output low voltage (DVDD = min, IOL = 0.5 mA) VOL — 0.4 V — Notes: 1. The min VIL and max VIH values are based on the min and max DVIN respective values found in Table 4. 2. The symbol DVIN represents the input voltage of the supply referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.14.2 DUART AC timing specifications This table provides the AC timing specifications for the DUART interface. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 128 NXP Semiconductors Electrical characteristics Table 83. DUART AC timing specifications Parameter Value Unit Notes Minimum baud rate fPLAT/(2 x 1,048,576) baud 1, 3 Maximum baud rate fPLAT/(2 x 16) baud 1, 2 Notes: 1. fPLAT refers to the internal platform clock. 2. The actual attainable baud rate is limited by the latency of interrupt processing. 3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. 3.15 Flextimer interface This section describes the DC and AC electrical characteristics for the Flextimer interface. There are Flextimer pins on various power supplies in this device. 3.15.1 Flextimer DC electrical characteristics This table provides the DC electrical characteristics for Flextimer pins operating at DVDD/EVDD = 3.3 V. Table 84. Flextimer DC electrical characteristics (DVDD/EVDD = 3.3 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x D/EVDD — V 1 Input low voltage VIL — 0.2 x D/EVDD V 1 Input current (VIN = 0 V or VIN= D/EVDD) IIN — ±50 μA 2 Output high voltage VOH 2.4 — V — VOL — 0.4 V — (D/EVDD = min, IOH = -2 mA) Output low voltage (D/EVDD = min, IOL = 2 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN/EVIN values found in Table 4. 2. The symbol VIN, in this case, represents the DVIN/EVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for Flextimer pins operating at DVDD/EVDD/LVDD/OVDD = 1.8 V. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 129 Electrical characteristics Table 85. Flextimer DC electrical characteristics (DVDD/EVDD/LVDD/OVDD = 1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x D/E/L/ OVDD — V 1 Input low voltage VIL — 0.2 x D/E/L/VDD V 1 Input low voltage VIL — 0.3 x OVDD V 1 Input current (VIN = 0 V or VIN = D/E/L/ OVDD) IIN — ±50 μA 2 Output high voltage VOH 1.35 — V — VOL — 0.4 V — (D/E/L/OVDD = min, IOH = -0.5 mA) Output low voltage (D/E/L/OVDD = min, IOL = 0.5 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN/EVIN/L/OVIN values found in Table 4. 2. The symbol VIN, in this case, represents the DVIN/EVIN/L/OVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for Flextimer pins operating at LVDD = 2.5 V. Table 86. Flextimer DC electrical characteristics (LVDD= 2.5 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (VIN = 0 V or VIN= LVDD) IIN — ±50 μA 2 Output high voltage VOH 2.0 — V — VOL — 0.4 V — (LVDD = min, IOH = -1 mA) Output low voltage (LVDD = min, IOL = 1 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 4. 2. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.15.2 Flextimer AC timing specifications This table provides the Flextimer AC timing specifications. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 130 NXP Semiconductors Electrical characteristics Table 87. Flextimer AC timing specifications2 Parameter Symbol Flextimer inputs—minimum pulse width tPIWID Min 20 Unit ns Notes 1 Notes: 1. Flextimer inputs and outputs are asynchronous to any visible clock. Flextimer outputs should be synchronized before use by any external synchronous logic. Flextimer inputs are required to be valid for at least tPIWID to ensure proper operation. 2. For recommended operating conditions, see Table 4. This figure provides the AC test load for the Flextimer. Output (L/O) VDD/2 Z0= 50 Ω RL = 50 Ω Figure 58. Flextimer AC test load 3.16 SPI interface This section describes the DC and AC electrical characteristics for the SPI interface. 3.16.1 SPI DC electrical characteristics This table provides the DC electrical characteristics for the SPI interface operating at OVDD = 1.8 V. Table 88. SPI DC electrical characteristics (1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x OVDD — V 1 Input low voltage VIL — 0.3 x OVDD V 1 Input current (VIN = 0 V or VIN = OVDD) IIN — ±50 μA 2 Output high voltage VOH 1.35 — V — VOL — 0.4 V — (OVDD = min, IOH = -0.5 mA) Output low voltage (OVDD = min, IOL = 0.5 mA) Notes: QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 131 Electrical characteristics Table 88. SPI DC electrical characteristics (1.8 V)3 Parameter Symbol Min Max Unit Notes 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 4. 2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.16.2 SPI AC timing specifications This table provides the SPI timing specifications. Table 89. SPI AC timing specifications Parameter Symbol Condition Min Max Unit Notes SCK clock pulse width tSDC — 40% 60% tSCK — CS to SCK delay tCSC Master tp*2 - 5.0 — ns 1, 2 After SCK delay tASC Master tp*2 - 1.0 — ns 1, 3 Data setup time for inputs tNIIVKH Master 9 — ns — Data hold time for inputs tNIIXKH Master 0 — ns — Data valid (after SCK edge) for Outputs tNIKHOV Master — 5 ns — Data hold time for outputs Master 0 — ns — tNIKHOX Notes: 1. tp represents the input clock period for the SPI controller. 2. Refer the CTARx register in QorIQ LS1046ARM for more details. The tCSC = tp*(Delay Scaler Value)*CTARx[PCSSCK] -5.0, where the Delay Scaler Value comes from Table Delay Scaler Encoding. For example, the tCSC = tp*4*3-5.0 when CTARx[PCSSCK] = 0b01, CTARx[CSSCK]=0b0001. 3. Refer the CTARx register in QorIQ LS1046ARM for more details. The tASC = tp*(Delay Scaler Value)*CTARx[PASC] -1.0, where the Delay Scaler Value comes from Table Delay Scaler Encoding. For example, the tASC = tp*8*3-1.0 when CTARx[PASC] = 0b01, CTARx[ASC]=0b0010. This figure shows the SPI timing master when CPHA = 0. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 132 NXP Semiconductors Electrical characteristics tCSC tASC CSx t SDC SCK Output (CPOL = 0) t SCK t SDC SCK Output (CPOL = 1) t NIIVKH SIN t NIIXKH First Data Data t NIKHOX Last Data t NIKHOV SOUT First Data Data Last Data Figure 59. SPI timing master, CPHA = 0 This figure shows the SPI timing master when CPHA = 1. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 133 Electrical characteristics CSx SCK Output (CPOL = 0) tNIIXKH SCK Output (CPOL = 1) tNIIVKH SIN Data First Data Last Data t NIKHOX t NIKHOV SOUT Last Data Data First Data Figure 60. SPI timing master, CPHA = 1 3.17 QSPI interface This section describes the DC and AC electrical characteristics for the QSPI interface. 3.17.1 QSPI DC electrical characteristics This table provides the DC electrical characteristics for the QSPI interface operating at OVDD = 1.8 V. Table 90. QSPI DC electrical characteristics (1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x OVDD — V 1 Input low voltage VIL — 0.3 x OVDD V 1 Input current (VIN = 0 V or VIN = OVDD) IIN — ±50 μA 2 Output high voltage VOH OVDD - 0.2 — V — Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 134 NXP Semiconductors Electrical characteristics Table 90. QSPI DC electrical characteristics (1.8 V)3 (continued) Parameter Symbol Min Max Unit Notes (OVDD = min, IOH = -0.5 mA) Output low voltage VOL — 0.4 V — (OVDD = min, IOL = 0.5 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 4. 2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.17.2 QSPI AC timing specifications This section describes the QuadSPI timing specifications in Single data rate (SDR) mode. All data is based on a negative edge data launch and a positive edge data capture for the flash device. Double data rate (DDR)/Double trasfer rate (DTR) mode is not supported. 3.17.2.1 QSPI timing SDR mode This table provides the QSPI input and output timing in SDR mode. Table 91. SDR mode QSPI input and output timing Parameter Symbol Min Max Unit Clock frequency FSCK — 62.5 MHz Clock rise/fall time TRISE/TFALL 1 — ns CS output hold time tNIKHOX2 -3.4 + j * T — ns CS output delay tNIKHOV2 -3.5 + k * T — ns Setup time for incoming data tNIIVKH 8.6 — ns Hold time requirement for incoming data tNIIXKH 0.4 — ns Output data valid tNIKHOV — 4.5 ns Output data hold tNIKHOX -4.4 — ns NOTE T represents the clock period, j represents qSPI_FLSHCR[TCSH], and k depends on qSPI_FLSHCR[TCSS]. This figure shows the QSPI AC timing in SDR mode. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 135 Electrical characteristics QSPI_CK_A QSPI_CK_B tNIIXKH tNIIVKH Input Signals: tNIKHOX tNIKHOV Output Signals: tNIKHOX2 tNIKHOV2 QSPI_CS_A0 QSPI_CS_A1 QSPI_CS_B0 QSPI_CS_B1 Figure 61. QSPI AC timing — SDR mode 3.18 Enhanced secure digital host controller (eSDHC) This section describes the DC and AC electrical specifications for the eSDHC interface. 3.18.1 eSDHC DC electrical characteristics This table provides the DC electrical characteristics for the eSDHC interface at D/EVDD = 3.3 V. Table 92. eSDHC interface DC electrical characteristics2 Characteristic Symbol Min Max Unit Notes Input high voltage VIH 0.7 x D/EVDD - V 1 Input low voltage VIL - 0.25 x D/EVDD V 1 Output high voltage (D/EVDD = min, IOH = -100 μA) VOH 0.75 x D/EVDD - V - Output low voltage (D/EVDD = min, IOL = 100 μA) VOL - 0.125 x D/EVDD V - Notes: 1. The min VIL and max VIH values are based on the respective min and max D/EVIN values found in Table 4 . 2. At recommended operating conditions with D/EVDD= 3.3 V. This table provides the DC electrical characteristics for the eSDHC interface at D/O/ EVDD = 1.8 V. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 136 NXP Semiconductors Electrical characteristics Table 93. eSDHC interface DC electrical characteristics 3 Characteristic Symbol Min Max Unit Notes Input high voltage VIH 0.7 x D/O/EVDD - V 1 Input low voltage VIL - 0.3 x D/O/EVDD V 1 Output high voltage (D/O/EVDD= min, IOH = -2mA) VOH D/O/EVDD - 0.45 - V - - 0.45 V - Output low voltage (D/O/EVDD= min, IOL = VOL 2mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN/OVIN/EVIN values found in Table 4 . 3. At recommended operating conditions DVDD/OVDD/EVDD= 1.8V. 3.18.2 eSDHC AC timing specifications This section provides the AC timing specifications. This table provides the eSDHC AC timing specifications as defined in Figure 62, Figure 63, and Figure 64. Table 94. eSDHC AC timing specifications (full-speed/high-speed mode)6 Parameter SDHC_CLK clock frequency: Symbol1 fSHSCK Min 0 • SD/SDIO (full-speed/high-speed mode) • eMMC (full-speed/high-speed mode) Max 25/50 Unit Notes MHz 2, 4 26/52 SDHC_CLK clock low time (full-speed/high-speed mode) tSHSCKL 10/7 - ns 4 SDHC_CLK clock high time (full-speed/high-speed mode) tSHSCKH 10/7 - ns 4 SDHC_CLK clock rise and fall times tSHSCKR/ - 3 ns 4 tSHSCKF Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK tSHSIVKH 2.5 - ns 3, 4, 5 Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK tSHSIXKH 2.5 - ns 4, 5 Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tSHSKHOX -3 - ns 4, 5 Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tSHSKHOV - 3 ns 4, 5 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. In full-speed mode, the clock frequency value can be 0-25MHz for an SD/SDIO card and 0-26MHz for an eMMC device. In high-speed mode, the clock frequency value can be 0-50MHz for an SD/SDIO card and 0-52MHz for an eMMC device. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 137 Electrical characteristics Table 94. eSDHC AC timing specifications (full-speed/high-speed mode)6 Symbol1 Parameter Min Max Unit Notes 3. SDHC_SYNC_OUT/IN loop back is recommended to compensate the clock delay. In case the SDHC_SYNC_OUT/IN loopback is not used, to satisfy setup timing, one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1ns for any high-speed MMC card. For any high-speed or default speed mode SD card, the one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1.5ns. 4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF. 5. The parameter values apply to both full-speed and high-speed modes. 6. At recommended operating conditions with EVDD=1.8 V or 3.3V, see Table 4. This figure provides the eSDHC clock input timing diagram. eSDHC external clock operational mode VM VM VM tSHSCKL tSHSCKH tSHSCK tSHSCKR tSHSCKF VM = Midpoint voltage (Respective supply/2) Figure 62. eSDHC clock input timing diagram This figure provides the input AC timing diagram for high-speed mode. VM VM VM VM SDHC_CLK t SHIVKH t SHIXKH SDHC_DAT/SDHC_CMD inputs VM = Midpoint voltage (EVDD/2) Figure 63. eSDHC high-speed mode input AC timing diagram This figure provides the output AC timing diagram for high-speed mode. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 138 NXP Semiconductors Electrical characteristics VM VM VM VM SDHC_CLK SDHC_CMD/SDHC_CMD_DIR SDHC_DAT/SDHC_DATn_DIR outputs t SHKHOV tSHKHOX VM = Midpoint voltage (EVDD/2) Figure 64. eSDHC high-speed mode output AC timing diagram This table provides the eSDHC AC timing specifications for SDR50 mode. Table 95. eSDHC AC timing specifications (SDR 50 mode) Parameter Symbol Min Max Unit Notes SDHC_CLK clock frequency: fSHSCK 0 90 MHz SDHC_CLK duty cycle tSHSCKH/ tSHSCK 45 55 % SDHC_CLK clock rise and fall times tSHSCKR/ - 2 ns 1 tSHSCKF Skew between SD_CLK_SYNC_OUT and SD_CLK - -0.1 0.1 ns 1 Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK_SYNC_IN tSHSIVKH 3.21 - ns 2,1 Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK_SYNC_IN tSHSIXKH 1.1 - ns 2,1 Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, SDHC_DATx_DIR, SDHC_CMD_DIR tSHSKHOX 1.7 - ns 2,1 Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, SDHC_DATx_DIR, SDHC_CMD_DIR tSHSKHOV - 7.21 ns 2,1 Notes: 1. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 30 pF 2. Without a voltage translator 3. At recommended operating conditions with EVDD=1.8 V, see Table 4. This figure provides the eSDHC clock input timing diagram for SDR50 mode. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 139 Electrical characteristics eSDHC external clock operational mode VM VM VM tSHCK tSHCKR tSHCKF VM = Midpoint voltage (EVDD/2) Figure 65. eSDHC SDR50 mode clock input timing diagram This figure provides the eSDHC input AC timing diagram for SDR50 mode. T CLK SDHC_CLK_SYNC_IN T SHIVKH TSHIXKH SDHC_CMD/ SDHC_DAT input Figure 66. eSDHC SDR50 mode input AC timing diagram This figure provides the eSDHC output timing diagram for SDR50 mode. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 140 NXP Semiconductors Electrical characteristics T CLK SD_CLK T SHKHOV SDHC_CMD/SDHC_CMD_DIR SDHC_DAT/SDHC_DATn_DIR output T SHKHOX Figure 67. eSDHC SDR50 mode output timing diagram This table provides the eSDHC AC timing specifications for DDR50/DDR mode. Table 96. eSDHC AC timing specifications (DDR50/DDR)3 Parameter Symbol SDHC_CLK clock frequency fSHCK Min - Max - SD/SDIO DDR50 mode 50 eMMC DDR mode 52 Unit MHz SDHC_CLK duty cycle tSHSCKH/ tSHSCK 47 53 % Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK - -0.1 0.1 ns SDHC_CLK clock rise and fall times tSHCKR/ - - ns SD/SDIO DDR50 mode tSHCKF 4 eMMC DDR mode Input setup times: SDHC_DATx to SDHC_CLK_SYNC_IN 1 - - ns 1, 4 2 1.6 eMMC DDR mode tSHDIXKH - - ns 1.1 SD/SDIO DDR50 mode 1 2 1.1 eMMC DDR mode tSHDKHOX - - ns 1.7 SD/SDIO DDR50 mode 1 2 3.4 eMMC DDR mode Output delay time: SDHC_CLK to SDHC_DATx valid, SDHC_DATx_DIR - 2 2.0 SD/SDIO DDR50 mode Output hold time: SDHC_CLK to SDHC_DATx valid, SDHC_DATx_DIR - 2 tSHDIVKH Input hold times: SDHC_DATx to SDHC_CLK_SYNC_IN Notes tSHDKHOV - 6.1 ns 1 2 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 141 Electrical characteristics Table 96. eSDHC AC timing specifications (DDR50/DDR)3 (continued) Parameter Symbol Min Max Unit Notes 6.2 SD/SDIO DDR50 mode eMMC DDR mode Input setup times: SDHC_CMD to SDHC_CLK_SYNC_IN tSHCIVKH - Input hold times: SDHC_CMD to SDHC_CLK_SYNC_IN tSHCIXKH - SD/SDIO DDR50 mode 1.1 eMMC DDR mode 1.1 tSHCKHOX - - ns 1 2 - ns 1 2 3.9 eMMC DDR mode eMMC DDR mode 2 1.7 SD/SDIO DDR50 mode SD/SDIO DDR50 mode 1 4.5 eMMC DDR mode Output delay time: SDHC_CLK to SDHC_CMD valid, SDHC_CMD_DIR ns 5.3 SD/SDIO DDR50 mode Output hold time: SDHC_CLK to SDHC_CMD valid, SDHC_CMD_DIR - tSHCKHOV - - ns 13.1 1 2 15.3 Notes: 1. CCARD ≤ 10 pF, (1 card). 2. CL = CBUS + CHOST + CCARD ≤ 20 pF for MMC, ≤ 25 pF for Input Data of DDR50, ≤ 30 pF for Input CMD of DDR50. 3. At recommended operating conditions with EVDD = 1.8 or 3.3 V for eMMC DDR mode, EVDD = 1.8 V for DDR50, see Table 4. This figure provides the eSDHC DDR50/DDR mode input AC timing diagram. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 142 NXP Semiconductors Electrical characteristics T SHCK SDHC_CLK_SYNC_IN T T SHDIVKH SHDIXKH SDHC_DAT input T SHCIVKH T SHCIXKH SDHC_CMD input Figure 68. eSDHC DDR50/DDR mode input AC timing diagram This figure provides the eSDHC DDR50/DDR mode output AC timing diagram. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 143 Electrical characteristics T SHCK SDHC_CLK T SHDKHOV SDHC_DAT/ SDHC_DATn_DIR output T SHDKHOX T SHCKHOV SDHC_CMD/ SD_CMD_DIR output T SHCKHOX Figure 69. eSDHC DDR50/DDR mode output AC timing diagram This table provides the eSDHC AC timing specifications for SDR104/eMMC HS200 mode. Table 97. eSDHC AC timing specifications (SDR104/eMMC HS200) Parameter SDHC_CLK clock frequency SD/SDIO SDR104 mode Symbol1 fSHCK Min - eMMC HS200 mode Max 167 Unit MHz 167 Notes 1 - SDHC_CLK duty cycle tSHSCKH/tSHSCK 40 60 % SDHC_CLK clock rise and fall times tSHCKR/tSHCKF - 1 ns 1 Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, SDHC_CMD_DIR, SDHC_DATx_DIR SD/SDIO SDR104 mode TSHKHOX 1.58 - ns 1 Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, SDHC_CMD_DIR, SDHC_DATx_DIR SD/SDIO SDR104 mode 3.94 ns 1 Input data window (UI) SD/SDIO SDR104 mode Unit Interval 1 eMMC HS200 mode 1.6 TSHKHOV - eMMC HS200 mode 3.92 tSHIDV eMMC HS200 mode 0.5 0.475 - Notes: 1. CL = CBUS + CHOST + CCARD ≤ 15pF. 2. At recommended operating conditions with EVDD =1.8 V, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 144 NXP Semiconductors Electrical characteristics This figure provides the eSDHC SDR104/HS200 mode timing diagram. T SHCK SDHC_CLK T SHIDV SDHC_CMD/ SDHC_DAT input DATA T SDHC_CMD/SDHC_CMD_DIR SDHC_DAT/SDHC_DATn_DIR output SHKHOV DATA DATA T SHKHOX Figure 70. eSDHC SDR104/HS200 mode timing diagram 3.19 JTAG controller This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface. 3.19.1 JTAG DC electrical characteristics This table provides the JTAG DC electrical characteristics. Table 98. JTAG DC electrical characteristics (OVDD = 1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x OVDD — V 1 Input low voltage VIL — 0.3 x OVDD V 1 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 145 Electrical characteristics Table 98. JTAG DC electrical characteristics (OVDD = 1.8V)3 (continued) Parameter Symbol Min Max Unit Notes Input current (OVIN = 0 V or OVIN = OVDD) IIN — -100/+50 µA 2, 4 Output high voltage (OVDD = min, IOH = -0.5 mA) VOH 1.35 — V — Output low voltage (OVDD = min, IOL= 0.5 mA) VOL — 0.4 V — Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 4. 2. The symbol VIN, in this case, represents the OVIN symbol found in Table 4. 3. For recommended operating conditions, see Table 4. 4. Per IEEE Std. 1149.1 specification, TDI, TMS, and TRST_B have internal pull-up. 3.19.2 JTAG AC timing specifications This table provides the JTAG AC timing specifications as defined in Figure 71, Figure 72, Figure 73, and Figure 74. Table 99. JTAG AC timing specifications4 Symbol1 Parameter Min Max Unit Notes JTAG external clock frequency of operation fJTG 0 33.3 MHz — JTAG external clock cycle time tJTG 30 — ns — JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns — JTAG external clock rise and fall times tJTGR/tJTGF 0 2 ns — TRST_B assert time tTRST 25 — ns 2 Input setup times tJTDVKH 4 — ns — Input hold times tJTDXKH 10 — ns — tJTKLDV — 15 ns 3 — 10 0 — ns 3 Output valid times Boundary-scan data TDO Output hold times tJTKLDX Notes: 1. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only. 3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 4. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 146 NXP Semiconductors Electrical characteristics This figure shows the AC test load for TDO and the boundary-scan outputs of the device. Output OVDD/2 Z0= 50 Ω RL = 50 Ω Figure 71. AC test load for the JTAG interface This figure shows the JTAG clock input timing diagram. VM VM VM JTAG external clock tJTGR tJTKHKL tJTGF tJTG VM = Midpoint voltage (OVDD/2) Figure 72. JTAG clock input timing diagram This figure shows the TRST_B timing diagram. TRST_B VM VM tTRST VM = Midpoint voltage (OVDD/2) Figure 73. TRST_B timing diagram This figure shows the boundary-scan timing diagram. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 147 Electrical characteristics JTAG External Clock VM VM tJTDVKH tJTDXKH Boundary Data Inputs Input Data Valid tJTKLDV tJTKLDX Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Figure 74. Boundary-scan timing diagram 3.20 I2C interface This section describes the DC and AC electrical characteristics for the I2C interfaces. 3.20.1 I2C DC electrical characteristics This table provides the DC electrical characteristics for the I2C interfaces operating at DVDD = 3.3 V. Table 100. I2C DC electrical characteristics (DVDD = 3.3 V)4 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x DVDD — V 1 Input low voltage VIL — 0.2 x DVDD V 1 Output low voltage VOL — 0.4 V 2 Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3 Input current each I/O pin (input voltage is between 0.1 x DVDD and 0.9 x DVDD(max) II -50 50 µA - Capacitance for each I/O pin CI — 10 pF — (DVDD = min, IOL = 3 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 4. 2. The output voltage (open drain or open collector) condition = 3 mA sink current. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 148 NXP Semiconductors Electrical characteristics Table 100. I2C DC electrical characteristics (DVDD = 3.3 V)4 Parameter Symbol Min Max Unit Notes 3. See the chip reference manual for information about the digital filter used. 4. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for the I2C interfaces operating at DVDD = 1.8 V. Table 101. I2C DC electrical characteristics (DVDD = 1.8 V)5 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x DVDD — V 1 Input low voltage VIL — 0.2 x DVDD V 1 Output low voltage (DVDD = min, IOL = 3 mA) VOL 0 0.36 V 2 Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3 Input current each I/O pin (input voltage is between 0.1 x DVDD and 0.9 II x DVDD(max) -50 50 µA 4 Capacitance for each I/O pin — 10 pF — CI Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 4. 2. The output voltage (open drain or open collector) condition = 3 mA sink current. 3. See the chip reference manual for information about the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if DVDD is switched off. 5. For recommended operating conditions, see Table 4. 3.20.2 I2C AC timing specifications This table provides the AC timing specifications for the I2C interfaces. Table 102. I2C AC timing specifications5 Symbol1 Parameter Min Max Unit Notes SCL clock frequency fI2C 0 400 kHz 2 Low period of the SCL clock tI2CL 1.3 — μs — High period of the SCL clock tI2CH 0.6 — μs — Setup time for a repeated START condition tI2SVKH 0.6 — μs — Hold time (repeated) START condition (after this period, the first clock pulse is generated) tI2SXKL 0.6 — μs — Data setup time tI2DVKH 100 — ns — Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 149 Electrical characteristics Table 102. I2C AC timing specifications5 (continued) Symbol1 Parameter Data input hold time CBUS compatible masters tI2DXKL I2C bus devices Min Max — — 0 — Unit Notes μs 3 Data output delay time tI2OVKL — 0.9 μs 4 Setup time for STOP condition tI2PVKH 0.6 — μs — Bus free time between a STOP and START condition tI2KHDX 1.3 — μs — Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 x DVDD — V — Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 x DVDD — V — Capacitive load for each bus line Cb — pF — 400 Notes: 1. The symbols used for timing specifications herein follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. 2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for SCL (AN2919). 3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919). 4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal. 5. For recommended operating conditions, see Table 4. This figure shows the AC test load for the I2C. Output OVDD/2 Z0= 50 Ω RL = 50 Ω Figure 75. I2C AC test load This figure shows the AC timing diagram for the I2C bus. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 150 NXP Semiconductors Electrical characteristics SDA tI2DVKH tI2CL SCL tI2KHKL tI2SXKL tI2CH tI2SXKL tI2SVKH tI2DXKL, tI2OVKL S tI2KHDX tI2PVKH S P Sr Figure 76. I2C bus AC timing diagram 3.21 GPIO interface This section describes the DC and AC electrical characteristics for the GPIO interface. There are GPIO pins on various power supplies in this device. 3.21.1 GPIO DC electrical characteristics This table provides the DC electrical characteristics for GPIO pins operating at EVDD = 3.3 V. Table 103. GPIO DC electrical characteristics (EVDD = 3.3 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x EVDD — V 1 Input low voltage VIL — 0.2 x EVDD V 1 Input current (VIN = 0 V or VIN= LVDD) IIN — ±50 μA 2 Output high voltage VOH 2.4 — V — VOL — 0.4 V — (EVDD = min, IOH = -2 mA) Output low voltage (EVDD = min, IOL = 2 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max EVIN values found in Table 4. 2. The symbol VIN, in this case, represents the EVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for GPIO pins operating at TVDD/ LVDD = 2.5 V. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 151 Electrical characteristics Table 104. GPIO DC electrical characteristics (TVDD/LVDD = 2.5 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x T/LVDD — V 1 Input low voltage VIL — 0.2 x T/LVDD V 1 Input current (VIN = 0 V or VIN= T/LVDD) IIN — ±50 μA 2 Output high voltage VOH 2.0 — V — VOL — 0.4 V — (T/LVDD = min, IOH = -2 mA) Output low voltage (T/LVDD = min, IOL = 2 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max L/TVIN values found in Table 4. 2. The symbol VIN, in this case, represents the L/TVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for GPIO pins operating at LVDD/ EVDD/DVDD/TVDD/OVDD = 1.8 V. Table 105. GPIO DC electrical characteristics (LVDD/EVDD/DVDD/TVDD/OVDD = 1.8 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x L/E/D/T/OVDD — V 1 Input low voltage VIL — 0.2 x L/E/D/ TVDD V 1 Input low voltage VIL — 0.3 x OVDD V 1 Input current (VIN = 0 V or VIN = L/E/D/T/OVDD) IIN — ±50 μA 2 Output high voltage VOH 1.35 — V — VOL — 0.4 V — (L/E/D/T/OVDD = min, IOH = -0.5 mA) Output low voltage (L/E/D/T/OVDD = min, IOL = 0.5 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN/EVIN/DVIN/TVIN/OVIN values found in Table 4. 2. The symbol VIN, in this case, represents the LVIN/EVIN/DVIN/TVIN/OVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the DC electrical characteristics for GPIO pins operating at TVDD = 1.2 V. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 152 NXP Semiconductors Electrical characteristics Table 106. GPIO DC electrical characteristics (TVDD = 1.2 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x TVDD — V Input low voltage VIL — 0.2 x TVDD V Output low current current (VOL= 0.2 V) IOL 4 Output high voltage VOH 1.0 — V — VOL — 0.2 V — CIN — 10 pF — mA (TVDD = min, IOH = -100uA) Output low voltage (TVDD = min, IOL = 100uA) Input Capacitance Notes: 1. The min VIL and max VIH values are based on the respective min and max TVIN values found in Table 4. 2. The symbol VIN, in this case, represents the TVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. 3.21.2 GPIO AC timing specifications This table provides the GPIO input and output AC timing specifications. Table 107. GPIO Input AC timing specifications Parameter GPIO inputs-minimum pulse width Symbol tPIWID Min 20 Unit ns Notes 1 Notes: 1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation. 2. For recommended operating conditions, see Table 4. This figure provides the AC test load for the GPIO. Output (L/O) VDD/2 Z0= 50 Ω RL = 50 Ω Figure 77. GPIO AC test load QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 153 Electrical characteristics 3.22 GIC interface This section describes the DC and AC electrical characteristics for the GIC interface. 3.22.1 GIC DC electrical characteristics This table provides the DC electrical characteristics for GIC pins operating at DVDD = 3.3 V. Table 108. GIC DC electrical characteristics (DVDD = 3.3 V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x DVDD — V 1 Input low voltage VIL — 0.2 x DVDD V 1 Input current (VIN = 0 V or VIN= DVDD) IIN — ±50 μA 2 Output high voltage VOH 2.4 — V — VOL — 0.4 V — (DVDD = min, IOH = -2 mA) Output low voltage (DVDD = min, IOL = 2 mA) Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 4. 2. The symbol VIN, in this case, represents the DVIN symbol referenced in Table 4. 3. For recommended operating conditions, see Table 4. This table provides the GIC DC electrical characteristics when LVDD = 2.5 V. Table 109. GIC DC electrical characteristics (LVDD = 2.5 V)4 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 x LVDD — V 1 Input low voltage VIL — 0.2 x LVDD V 1 Input current (LVIN = 0 or LVIN = LVDD) IIN — ±50 µA 2, 3 Output high voltage (LVDD = min, IOH = -1.0 mA) VOH 2.00 — V — Output low voltage (LVDD = min, IOL = 1.0 mA) VOL — 0.40 V — Notes: 1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 4. 2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 4. 3. The symbol LVDD, in this case, represents the LVDD symbols referenced in Table 4. 4. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 154 NXP Semiconductors Electrical characteristics This table provides the GIC DC electrical characteristics when LVDD/DVDD/OVDD = 1.8 V. Table 110. GIC DC electrical characteristics (LVDD/ DVDD/ OVDD = 1.8 V)4 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 x L/D/OVDD — V 1 Input low voltage VIL — 0.2 x L/DVDD V 1 Input low voltage VIL — 0.3 x OVDD V 1 Input current (L/D/OVIN = 0 V or L/D/ OVIN = L/D/OVDD) IIN — ±50 µA 2, 3 Output high voltage (L/D/OVDD = min, IOH = -0.5 mA) VOH 1.35 — V 3 — 0.4 V 3 Output low voltage (L/D/OVDD = min, IOL VOL = 0.5 mA) Notes: 1. The min VILand max VIH values are based on the min and max L/D/OVIN respective values found in Table 4. 2. The symbol L/D/OVIN represents the L/D/OVIN symbols referenced in Table 4. 3. The symbol L/D/OVDD, in this case, represents the L/D/OVDD symbols referenced in Table 4. 4. For recommended operating conditions, see Table 4. 3.22.2 GIC AC timing specifications This table provides the GIC input and output AC timing specifications. Table 111. GIC input AC timing specifications2 Characteristic Symbol GIC inputs-minimum pulse width tPIWID Min 3 Max - Unit SYSCLKs Notes 1 1. GIC inputs and outputs are asynchronous to any visible clock. GIC outputs must be synchronized before use by any external synchronous logic. GIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode. 2. For recommended operating conditions, see Table 4. 3.23 High-speed serial interfaces (HSSI) The chip features a Serializer/Deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The SerDes interface can be used for PCI Express, SGMII, and serial ATA (SATA) data transfers. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 155 Electrical characteristics This section describes the most common portion of the SerDes DC electrical specifications: the DC requirement for SerDes reference clocks. The SerDes data lane's transmitter (Tx) and receiver (Rx) reference circuits are also described. 3.23.1 Signal terms definitions The SerDes utilizes differential signaling to transfer data across the serial link. This section defines the terms that are used in the description and specification of differential signals. This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This figure shows the waveform for either a transmitter output (SD_TXn_P and SD_TXn_N) or a receiver input (SD_RXn_P and SD_RXn_N). Each signal swings between A volts and B volts where A > B. SD_TXn_P SD_RXn_P A Volts or Vcm= (A + B)/2 SD_TXn_N SD_RXn_N B Volts or Differential swing, VID orVOD = A - B Differential peak voltage, VDIFFp = |A - B| Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown) Figure 78. Differential voltage definitions for transmitter or receiver Using this waveform, the definitions are as described in the following list. To simplify the illustration, the definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment: Single-Ended Swing The transmitter output signals and the receiver input signals SD_TXn_P, SD_TXn_N, SD_RXn_P and SD_RXn_N each have a peak-to-peak swing of A - B volts. This is also referred to as each signal wire's single-ended swing. Differential Output Voltage, VOD (or Differential Output Swing) The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complementary output voltages: VSD_TXn_P - VSD_TXn_N. The VOD value can be either positive or negative. Differential Input Voltage, VID (or Differential Input Swing) QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 156 NXP Semiconductors Electrical characteristics The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complementary input voltages: VSD_RXn_P- VSD_RXn_N. The VID value can be either positive or negative. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as the differential peak voltage, VDIFFp = |A - B| volts. Differential Peak-to-Peak, VDIFFp-p Because the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2 x VDIFFp = 2 x |(A - B)| volts, which is twice the differential swing in amplitude, or twice the differential peak. For example, the output differential peak-to-peak voltage can also be calculated as VTXDIFFp-p = 2 x |VOD|. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SD_TXn_N, for example) from the non-inverting signal (SD_TXn_P, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. See Figure 83 as an example for differential waveform. Common Mode Voltage, Vcm The common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSD_TXn_P + VSD_TXn_N) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complementary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. It may be different between the receiver input and driver output circuits within the same component. It is also referred to as the DC offset on some occasions. To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the differential signaling environment is fully symmetrical in this example, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV. In other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 157 Electrical characteristics 3.23.2 SerDes reference clocks The SerDes reference clock inputs are applied to an internal phase-locked loop (PLL) whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK[1:2]_P and SDn_REF_CLK[1:2]_N. SerDes may be used for various combinations of the following IP block based on the RCW Configuration field SRDS_PRTCLn: • • • • SGMII (1.25 Gbit/s or 3.125 Gbit/s), QSGMII (5 Gbit/s) XFI (10 Gbit/s) PCIe (2.5 Gbit/s, 5 Gbit/s, and 8 Gbit/s ) SATA (1.5 Gbit/s, 3.0 Gbit/s, and 6.0 Gbit/s) The following sections describe the SerDes reference clock requirements and provide application information. 3.23.2.1 SerDes spread-spectrum clock source recommendations SDn_REF_CLKn_P and SDn_REF_CLKn_N are designed to work with spread-spectrum clocking for the PCI Express protocol only with the spreading specification defined in Table 112. When using spread-spectrum clocking for PCI Express, both ends of the link partners should use the same reference clock. For best results, a source without significant unintended modulation must be used. The SerDes transmitter does not support spread-spectrum clocking for the SATA protocol. The SerDes receiver does support spread-spectrum clocking on receive, which means the SerDes receiver can receive data correctly from a SATA serial link partner using spread-spectrum clocking. Spread-spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread-spectrum-supported protocols. For example, if spread-spectrum clocking is desired on a SerDes reference clock for the PCI Express protocol and the same reference clock is used for any other protocol, such as SATA or SGMII because of the SerDes lane usage mapping option, spread-spectrum clocking cannot be used at all. This table provides the source recommendations for SerDes spread-spectrum clocking. Table 112. SerDes spread-spectrum clock source recommendations 1 Parameter Min Max Unit Notes Frequency modulation 30 33 kHz — Frequency spread +0 -0.5 % 2 Notes: 1. At recommended operating conditions. See Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 158 NXP Semiconductors Electrical characteristics Table 112. SerDes spread-spectrum clock source recommendations 1 Parameter Min Max Unit Notes 2. Only down-spreading is allowed. 3.23.2.2 SerDes reference clock receiver characteristics This figure shows a receiver reference diagram of the SerDes reference clocks. 50 Ω SDn_REF_CLKn_P Input amp SDn_REF_CLKn_N 50 Ω Figure 79. Receiver of SerDes reference clocks The characteristics of the clock signals are as follows: • The SerDes receiver's core power supply voltage requirements (SVDDn) are as specified in Table 4. • The SerDes reference clock receiver reference circuit structure is as follows: • The SDn_REF_CLKn_P and SDn_REF_CLKn_N are internally AC-coupled differential inputs as shown in Figure 79. Each differential clock input (SDn_REF_CLKn_P or SDn_REF_CLKn_N) has on-chip 50-Ω termination to SGNDn followed by on-chip AC-coupling. • The external reference clock driver must be able to drive this termination. • The SerDes reference clock input can be either differential or single-ended. See the differential mode and single-ended mode descriptions in Signal terms definitions for detailed requirements. • The maximum average current requirement also determines the common mode voltage range. • When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is AC-coupled on-chip. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 159 Electrical characteristics • This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0-0.8 V), such that each phase of the differential input has a singleended swing from 0 V to 800 mV with the common mode voltage at 400 mV. • If the device driving the SDn_REF_CLKn_P and SDn_REF_CLKn_N inputs cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip. • The input amplitude requirement is described in detail in the following sections. 3.23.2.3 DC-level requirements for SerDes reference clocks The DC-level requirements for the SerDes reference clock inputs are different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below: • Differential Mode • The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-to-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is same for both external DC-coupled or AC-coupled connection. • For an external DC-coupled connection, as described in Figure 79, the maximum average current requirements set the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV. • This figure shows the SerDes reference clock input requirement for a DCcoupled connection scheme. 200 mV < Input amplitude or differential peak < 800 mV SDn_REF_CLKn_P Vmax < 800 mV 100 mV < Vcm < 400 mV Vmin > 0 V SDn_REF_CLKn_N Figure 80. Differential reference clock input DC requirements (external DC-coupled) • For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 160 NXP Semiconductors Electrical characteristics operate in different common mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGNDn. Each signal wire of the differential inputs is allowed to swing below and above the common mode voltage (SGNDn). • This figure shows the SerDes reference clock input requirement for an ACcoupled connection scheme. 200 mV < Input amplitude or differential peak < 800 mV SDn_REF_CLKn_P Vmax < Vcm + 400 mV Vcm Vmin > Vcm - 400 mV SDn_REF_CLKn_N Figure 81. Differential reference clock input DC requirements (external AC-coupled) • Single-ended mode • The reference clock can also be single-ended. The SDn_REF_CLKn_P input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-topeak (from VMIN to VMAX) with SDn_REF_CLKn_N either left unconnected or tied to ground. • To meet the input amplitude requirement, the reference clock inputs may need to be externally DC- or AC-coupled. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SDn_REF_CLKn_N) through the same source impedance as the clock input (SDn_REF_CLKn_P) in use. • The SDn_REF_CLKn_P input average voltage must be between 200 and 400 mV. • This figure shows the SerDes reference clock input requirement for single-ended signaling mode. 400 mV < SDn_REF_CLKn input amplitude < 800 mV SDn_REF_CLKn_P 0V SDn_REF_CLKn_N Figure 82. Single-ended reference clock input DC requirements QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 161 Electrical characteristics 3.23.2.4 AC requirements for SerDes reference clocks This table provides the AC requirements for SerDes reference clocks for PCI Express protocols running at data rates up to 5 Gbit/s. This includes PCI Express (2.5 GT/s and 5 GT/s), SGMII (1.25 Gbit/s), and SATA (1.5 Gbit/s, 3.0 Gbit/s, and 6.0 Gbit/s). SerDes reference clocks need to be verified by the customer's application design. Table 113. SDn_REF_CLKn_P and SDn_REF_CLKn_N input clock requirements 1 Parameter Symbol Min Typ Max Unit Notes SDn_REF_CLKn_P/ SDn_REF_CLKn_N frequency range tCLK_REF — 100/125/156.25 — MHz 2 SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock frequency tolerance tCLK_TOL -300 — 300 ppm 3 SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock frequency tolerance tCLK_TOL -100 — 100 ppm 4 SDn_REF_CLKn_P/ SDn_REF_CLKn_N reference clock duty cycle tCLK_DUTY 40 50 60 % 5 SDn_REF_CLKn_P/ SDn_REF_CLKn_N max deterministic peak-to-peak jitter at 10-6 BER tCLK_DJ — — 42 ps — SDn_REF_CLKn_P/ SDn_REF_CLKn_N total reference clock jitter at 10-6 BER (peak-to-peak jitter at refClk input) tCLK_TJ — — 86 ps 6 SDn_REF_CLKn_P/ SDn_REF_CLKn_N 10 kHz to 1.5 MHz RMS jitter tREFCLK-LF-RMS — — 3 ps RMS 7 SDn_REF_CLKn_P/ SDn_REF_CLKn_N > 1.5 MHz to Nyquist RMS jitter tREFCLK-HF-RMS — — 3.1 ps RMS 7 SDn_REF_CLKn_P/ SDn_REF_CLKn_N RMS reference clock jitter tREFCLK-RMS-DC — — 1 ps RMS 8 SDn_REF_CLKn_P/ SDn_REF_CLKn_N rising/ falling edge rate tCLKRR/tCLKFR 0.6 — 4 V/ns 9 Differential input high voltage VIH 150 — — mV 5 Differential input low voltage VIL — — -150 mV 5 Rising edge rate (SDn_REF_CLKn_P) to falling edge rate (SDn_REF_CLKn_N) matching Rise-Fall Matching — — 20 % 10, 11 Notes: 1. For recommended operating conditions, see Table 4. 2. Caution: Only 100 and 125 have been tested. In-between values do not work correctly with the rest of the system. 3. For PCI Express (2.5, 5 and 8 GT/s). 4. For SGMII, 2.5GSGMII and QSGMII. 5. Measurement taken from differential waveform. 6. Limits from PCI Express CEM Rev 2.0. 7. For PCI Express 5 GT/s, per PCI Express base specification Rev 3.0. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 162 NXP Semiconductors Electrical characteristics Table 113. SDn_REF_CLKn_P and SDn_REF_CLKn_N input clock requirements 1 Parameter Symbol Min Typ Max Unit Notes 8. For PCI-Express-8 GT/s, per PCI-Express base specification rev 3.0 9. Measured from -150 mV to +150 mV on the differential waveform (derived from SDn_REF_CLKn_P minus SDn_REF_CLKn_N). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See Figure 83. 10. Measurement taken from single-ended waveform. 11. Matching applies to rising edge for SDn_REF_CLKn_P and falling edge rate for SDn_REF_CLKn_N. It is measured using ±75 mV window centered on the median cross point where SDn_REF_CLKn_P rising meets SDn_REF_CLKn_N falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of SDn_REF_CLKn_P must be compared to the fall edge rate of SDn_REF_CLKn_N, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 84. This table lists the AC requirements for SerDes reference clocks for protocols running at data rates greater than 8 GBaud. This includes XFI (10.3125 GBaud), SerDes reference clocks to be guaranteed by the customer's application design. Table 114. SD1_REF_CLKn_P/ SD1_REF_CLKn_N input clock requirements 1 Parameter Symbol Min Typ Max Unit Notes SD1_REF_CLKn_P/ SD1_REF_CLKn_N frequency range tCLK_REF - 156.25 - MHz 2 SD1_REF_CLKn_P/ SD1_REF_CLKn_N clock frequency tolerance tCLK_TOL -100 - 100 ppm - SD1_REF_CLKn_P/ SD1_REF_CLKn_N reference clock duty cycle tCLK_DUTY 40 50 60 % 3 SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band noise @1 kHz - - -85 dBC/Hz 4 SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band noise @10 kHz - - -108 dBC/Hz 4 SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band noise @100 kHz - - -128 dBC/Hz 4 SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band noise @1 MHz - - -138 dBC/Hz 4 SD1_REF_CLKn_P/ SD1_REF_CLKn_N single side band noise @10MHz - - -138 dBC/Hz 4 SD1_REF_CLKn_P/ SD1_REF_CLKn_N random jitter (1.2 MHz to 15 MHz) tCLK_RJ - - 0.8 ps - SD1_REF_CLKn_P/ SD1_REF_CLKn_N total reference clock jitter at 10-12 BER (1.2 MHz to 15 MHz) tCLK_TJ - - 11 ps - - - -75 dBC - SD1_REF_CLKn_P/ SD1_REF_CLKn_N spurious noise (1.2 MHz to 15 MHz) Notes: 1. For recommended operating conditions, see Table 4. 2. Caution: Only 156.25 have been tested. In-between values do not work correctly with the rest of the system. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 163 Electrical characteristics Table 114. SD1_REF_CLKn_P/ SD1_REF_CLKn_N input clock requirements 1 Parameter Symbol Min Typ Max Unit Notes 3. Measurement taken from differential waveform. 4. Per XFP Spec. Rev 4.5, the Module Jitter Generation spec at XFI Optical Output is 10mUI (RMS) and 100 mUI (p-p). In the CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter. This figure shows the differential measurement points for rise and fall time. Rise-edge rate Fall-edge rate VIH = + 150 mV 0.0 V VIL = - 150 mV SDn_REF_CLKn_P SDn_REF_CLKn_N Figure 83. Differential measurement points for rise and fall time This figure shows the single-ended measurement points for rise and fall time matching. SDn_REF_CLKn_N SDn_REF_CLKn_N TFALL TRISE VCROSS MEDIAN + 75 mV VCROSS MEDIAN VCROSS MEDIAN VCROSS MEDIAN - 75 mV SDn_REF_CLKn_P SDn_REF_CLKn_P Figure 84. Single-ended measurement points for rise and fall time matching 3.23.3 SerDes transmitter and receiver reference circuits This figure shows the reference circuits for SerDes data lane's transmitter and receiver. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 164 NXP Semiconductors Electrical characteristics SDn_TXn_P Transmitter SDn_RXn_P 50 Ω 100 Ω SDn_TXn_N SDn_RXn_N Receiver 50 Ω Figure 85. SerDes transmitter and receiver reference circuits The DC and AC specifications of the SerDes data lanes are defined in each interface protocol section below based on the application usage: • • • • PCI Express Serial ATA (SATA) interface SGMII interface XFI interface Note that an external AC-coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in the specification of each protocol section. 3.23.4 PCI Express This section describes the clocking dependencies, as well as the DC and AC electrical specifications for the PCI Express bus. 3.23.4.1 Clocking dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 ppm of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance. The platform clock frequency must be greater than or equal to 400 MHz for PCI Express Gen2. For more details, see Minimum platform frequency requirements for high-speed interfaces. 3.23.4.2 PCI Express DC physical layer specifications This section contains the DC specifications for the physical layer of PCI Express on this chip. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 165 Electrical characteristics 3.23.4.2.1 PCI Express DC physical layer transmitter specifications This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 115. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XVDD = 1.35 V)1 Parameter Symbol Min Typical Max Units Notes 1000 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │ De-emphasized differential VTX-DE-RATIO 3.0 output voltage (ratio) 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTXDIFFp-p of the first bit after a transition. DC differential transmitter impedance 80 100 120 Ω Transmitter DC differential mode low Impedance 40 50 60 Ω Required transmitter D+ as well as D- DC Impedance during all states Differential peak-to-peak output voltage VTX-DIFFp-p ZTX-DIFF-DC Transmitter DC impedance ZTX-DC 800 Notes: 1. For recommended operating conditions, see Table 4. This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 116. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XVDD = 1.35 V)1 Parameter Symbol Min Typical Max Units Notes Differential peak-to-peak output voltage VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │ Low-power differential peak-to-peak output voltage VTX-DIFFp-p_low 400 500 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │ De-emphasized differential VTX-DE-RATIO-3.5dB 3.0 output voltage (ratio) 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. De-emphasized differential VTX-DE-RATIO-6.0dB 5.5 output voltage (ratio) 6.0 6.5 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. DC differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low impedance Transmitter DC Impedance ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D- DC impedance during all states Notes: 1. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 166 NXP Semiconductors Electrical characteristics This table defines the PCI Express 3.0 (8 GT/s) DC characteristics for the differential output at all transmitters. The parameters are specified at the component pins. Table 117. PCI Express 3.0 (8 GT/s) differential transmitter output DC characteristics (XVDD = 1.35 V)3 Parameter Symbol Min Typical Max Units Notes Full swing transmitter voltage with no TX Eq VTX-FS-NO-EQ 800 — 1300 mVp-p See Note 1. Reduced swing transmitter voltage with no TX Eq VTX-RS-NO-EQ 400 — 1300 mV See Note 1. De-emphasized VTX-DE-RATIO-3.5dB 3.0 differential output voltage (ratio) 3.5 4.0 dB — De-emphasized VTX-DE-RATIO-6.0dB 5.5 differential output voltage (ratio) 6.0 6.5 dB — Minimum swing during EIEOS for full swing VTX-EIEOS-FS 250 — — mVp-p See Note 2 Minimum swing during VTX-EIEOS-RS EIEOS for reduced swing 232 — — mVp-p See Note 2 DC differential transmitter ZTX-DIFF-DC impedance 80 100 120 Ω Transmitter DC differential mode low impedance Transmitter DC Impedance 40 50 60 Ω Required transmitter D+ as well as D- DC impedance during all states ZTX-DC Notes: 1. Voltage measurements for VTX-FS-NO-EQ and VTX-RS-NO-EQ are made using the 64-zeroes/64-ones pattern in the compliance pattern. 2. Voltage limits comprehend both full swing and reduced swing modes. The transmitter must reject any changes that would violate this specification. The maximum level is covered in the VTX-FS-NO-EQ measurement which represents the maximum peak voltage the transmitter can drive. The VTX-EIEOS-FS and VTX-EIEOS-RS voltage limits are imposed to guarantee the EIEOS threshold of 175 mVP-P at the receiver pin. This parameter is measured using the actual EIEOS pattern that is part of the compliance pattern and then removing the ISI contribution of the breakout channel. 3. For recommended operating conditions, see Table 4. 3.23.4.2.2 PCI Express DC physical layer receiver specifications This section discusses the PCI Express DC physical layer receiver specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s. This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 167 Electrical characteristics Table 118. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications 4 Parameter Symbol Min Typ Max Units Notes Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-| See Note 1. DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode impedance. See Note 2 DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D- DC Impedance (50 ± 20% tolerance). See Notes 1 and 2. Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as D- DC Impedance when the receiver terminations do not have power. See Note 3. Electrical idle detect threshold 65 - 175 mV VRX-IDLE-DET- VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -VRX- D-| DIFFp-p Measured at the package pins of the receiver Notes: 1. Measured at the package pins with a test load of 50Ω to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. 4. For recommended operating conditions, see Table 4. This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. Table 119. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications 4 Parameter Symbol Min Typ Max Units Notes Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-| See Note 1. DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode impedance. See Note 2 DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as DDC Impedance (50 ± 20% tolerance). See Notes 1 and 2. Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as DDC Impedance when the receiver terminations do not have power. See Note 3. Electrical idle detect threshold VRX-IDLE-DET- 65 - 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ VRX-D-| DIFFp-p Measured at the package pins of the receiver Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 168 NXP Semiconductors Electrical characteristics Table 119. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications 4 (continued) Parameter Symbol Min Typ Max Units Notes Notes: 1. Measured at the package pins with a test load of 50 Ω to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. 4. For recommended operating conditions, see Table 4. This table defines the DC characteristics for the PCI Express 3.0 (8 GT/s) differential input at all receivers. The parameters are specified at the component pins. Table 120. PCI Express 3.0 (8 GT/s) differential receiver input DC characteristics 6 Characteristic Symbol Min Typ Max Units Notes DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode impedance. See Note 2 DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as DDC Impedance (50 ± 20% tolerance). See Notes 1 and 2. Powered down DC input impedance ZRX-HIGH-IMP-DC 50 — — kΩ Required receiver D+ as well as DDC Impedance when the receiver terminations do not have power. See Note 3. Generator launch voltage VRX-LAUNCH-8G — 800 — mV Measured at TP1 per PCI Express base spec. rev 3.0 Eye height (-20dB Channel) VRX-SV-8G 25 — — mV Measured at TP2P per PCI Express base spec. rev 3.0. See Notes 4, 5 Eye height (-12dB Channel) VRX-SV-8G 50 — — mV Measured at TP2P per PCI Express base spec. rev 3.0. See Notes 4, 5 Eye height (-3dB Channel) VRX-SV-8G 200 — — mV Measured at TP2P per PCI Express base spec. rev 3.0. See Notes 4, 5 Electrical idle detect threshold VRX-IDLE-DET- 65 — 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ VRX-D-| DIFFp-p Measured at the package pins of the receiver Notes: 1. Measured at the package pins with a test load of 50 Ω to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 169 Electrical characteristics Table 120. PCI Express 3.0 (8 GT/s) differential receiver input DC characteristics 6 Characteristic Symbol Min Typ Max Units Notes 4. VRX-SV-8G is tested at three different voltages to ensure the receiver device under test is capable of equalizing over a range of channel loss profiles. The "SV" in the parameter names refers to stressed voltage. 5. VRX-SV-8G is referenced to TP2P and is obtained after post processing data captured at TP2. 6. For recommended operating conditions, see Table 4. 3.23.4.3 PCI Express AC physical layer specifications This section describes the AC specifications for the physical layer of PCI Express on this device. 3.23.4.3.1 PCI Express AC physical layer transmitter specifications This section describes the PCI Express AC physical layer transmitter specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 121. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4 Parameter Symbol Min Typ Max Units Notes Unit interval UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations. Minimum transmitter eye width TTX-EYE 0.75 - The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE = 0.25 UI. Does not include spread-spectrum or RefCLK jitter. Includes device random jitter at 10-12. - UI See Notes 1 and 2. Maximum time between the TTX-EYE-MEDIANjitter median and maximum to- MAX-JITTER deviation from the median - - 0.125 UI Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI. See Notes 1 and 2. AC coupling capacitor 75 - 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 3. CTX Notes: QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 170 NXP Semiconductors Electrical characteristics Table 121. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4 Parameter Symbol Min Typ Max Units Notes 1. Specified at the measurement point into a timing and voltage test load as shown in Figure 87 and measured over any 250 consecutive transmitter UIs. 2. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 3. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required. 4. For recommended operating conditions, see Table 4. This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 122. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications3 Parameter Unit Interval Symbol UI Minimum transmitter eye width TTX-EYE Min Typ Max Units Notes 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations. 0.75 The maximum transmitter jitter can be derived as: TTX-MAX-JITTER = 1 - TTX-EYE = 0.25 UI. - - UI See Note 1. Transmitter deterministic jitter > 1.5 MHz TTX-HF-DJ-DD - - 0.15 UI - Transmitter RMS jitter < 1.5 MHz TTX-LF-RMS - 3.0 - ps Reference input clock RMS jitter (< 1.5 MHz) at pin < 1 ps AC coupling capacitor CTX 75 - 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 2. Notes: 1. Specified at the measurement point into a timing and voltage test load as shown in Figure 87 and measured over any 250 consecutive transmitter UIs. 2. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required. 3. For recommended operating conditions, see Table 4. This table defines the PCI Express 3.0 (8 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 171 Electrical characteristics Table 123. PCI Express 3.0 (8 GT/s) differential transmitter output AC specifications4 Parameter Symbol Min Typ Max Units Notes Unit Interval UI 124.9625 125.00 125.0375 ps Each UI is 125 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations. Transmitter uncorrelated total jitter TTX-UTJ — — 31.25 ps p-p — Transmitter uncorrelated deterministic jitter TTX-UDJ-DD — — 12 ps p-p — Total uncorrelated pulse width TTX-UPW-TJ jitter (PWJ) — — 24 ps p-p See Note 1, 2 Deterministic data dependent jitter (DjDD) uncorrelated pulse width jitter (PWJ) TTX-UPW-DJDD — — 10 ps p-p See Note 1, 2 Data dependent jitter TTX-DDJ — — 18 ps p-p See Note 2 AC coupling capacitor CTX 176 — 265 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 3. Notes: 1. PWJ parameters shall be measured after data dependent jitter (DDJ) separation. 2. Measured with optimized preset value after de-embedding to transmitter pin. 3. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required. 4. For recommended operating conditions, see Table 4. 3.23.4.3.2 PCI Express AC physical layer receiver specifications This section discusses the PCI Express AC physical layer receiver specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s. This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 124. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications4 Parameter Unit Interval Symbol UI Minimum receiver eye width TRX-EYE Min Typ Max Units Notes 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations. 0.4 - - UI The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAXJITTER = 1 - TRX-EYE= 0.6 UI. See Notes 1 and 2. Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 172 NXP Semiconductors Electrical characteristics Table 124. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications4 (continued) Parameter Symbol Min Maximum time between the TRX-EYE-MEDIAN- jitter median and maximum to-MAX-JITTER deviation from the median. Typ - Max 0.3 Units UI Notes Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI. See Notes 1, 2 and 3. Notes: 1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 87 must be used as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 2. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data. 4. For recommended operating conditions, see Table 4. This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 125. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications1 Parameter Min Typ Max 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations. Max receiver inherent timing TRX-TJ-CC error - - 0.4 UI The maximum inherent total timing error for common RefClk receiver architecture Max receiver inherent deterministic timing error - - 0.30 UI The maximum inherent deterministic timing error for common RefClk receiver architecture Unit Interval Symbol UI TRX-DJ-DD-CC Units Notes Note: 1. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 173 Electrical characteristics This table defines the AC specifications for the PCI Express 3.0 (8 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 126. PCI Express 3.0 (8 GT/s) differential receiver input AC specifications5 Parameter Symbol Min Typ Max Units Notes Unit Interval UI 124.9625 125.00 125.0375 ps Each UI is 125 ps ± 300 ppm. UI does not account for spreadspectrum clock dictated variations. See Note 1. Eye Width at TP2P TRX-SV-8G 0.3 — 0.35 UI See Note 1 Differential mode interference VRX-SV-DIFF-8G 14 — — mV Frequency = 2.1GHz. See Note 2. Sinusoidal Jitter at 100 MHz TRX-SV-SJ-8G — — 0.1 UI p-p Fixed at 100 MHz. See Note 3. Random Jitter TRX-SV-RJ-8G — — 2.0 ps RMS Random jitter spectrally flat before filtering. See Note 4. Note: 1. TRX-SV-8G is referenced to TP2P and obtained after post processing data captured at TP2. TRX-SV-8G includes the effects of applying the behavioral receiver model and receiver behavioral equalization. 2. VRX-SV-DIFF-8G voltage may need to be adjusted over a wide range for the different loss calibration channels. 3. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency as shown in Figure 86. 4. Random jitter (Rj) is applied over the following range: The low frequency limit may be between 1.5 and 10 MHz, and the upper limit is 1.0 GHz. See Figure 86 for details. Rj may be adjusted to meet the 0.3 UI value for TRX-SV-8G. 5. For recommended operating conditions, see Table 4. 0.03 MHz 100 MHz Sj sweep range Rj (ps RMS) Sj (UI PP) 1.0 UI 20 dB decade Sj 0.1 UI Rj ~ 3.0 ps RMS 0.01 MHz 0.1 MHz 1.0 MHz 10 MHz 100 MHz 1000 MHz Figure 86. Swept sinusoidal jitter mask QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 174 NXP Semiconductors Electrical characteristics 3.23.4.4 Test and measurement load The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/ board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and Dpackage pins. D + package pin C = CTX Transmitter silicon + package C = CTX D - package pin R = 50 Ω R = 50 Ω Figure 87. Test and measurement load 3.23.5 Serial ATA (SATA) interface This section describes the DC and AC electrical specifications for the SATA interface. 3.23.5.1 SATA DC electrical characteristics This section describes the DC electrical characteristics for SATA. 3.23.5.1.1 SATA DC transmitter output characteristics This table provides the differential transmitter output DC characteristics for the SATA interface at Gen1i/1m or 1.5 Gbit/s transmission. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 175 Electrical characteristics Table 127. Gen1i/1m 1.5 G transmitter DC specifications (XVDD = 1.35 V)3 Parameter Symbol Min Typ Max Units Notes Tx differential output voltage VSATA_TXDIFF 400 500 600 mV p-p 1 Tx differential pair impedance ZSATA_TXDIFFIM 85 100 115 Ω 2 Notes: 1. Terminated by 50 Ω load. 2. DC impedance. 3. For recommended operating conditions, see Table 4. This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbit/s transmission. Table 128. Gen 2i/2m 3 G transmitter DC specifications (XVDD = 1.35 V)2 Parameter Symbol Min Typ Max Units Notes Transmitter differential output voltage VSATA_TXDIFF 400 — 700 mV p-p 1 Transmitter differential pair impedance ZSATA_TXDIFFIM 85 100 115 Ω — Notes: 1. Terminated by 50 Ω load. 2. For recommended operating conditions, see Table 4. This table provides the differential transmitter output DC characteristics for the SATA interface at Gen 3i transmission. Table 129. Gen 3i transmitter DC specifications (XVDD = 1.35 V)2 Parameter Symbol Min Typ Max Units Notes Transmitter differential output voltage VSATA_TXDIFF 240 — 900 mV p-p 1 Transmitter differential pair impedance ZSATA_TXDIFFIM 85 100 115 Ω — Notes: 1. Terminated by 50 Ω load. 2. For recommended operating conditions, see Table 4. 3.23.5.1.2 SATA DC receiver input characteristics This table provides the Gen1i/1m or 1.5 Gbit/s differential receiver input DC characteristics for the SATA interface. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 176 NXP Semiconductors Electrical characteristics Table 130. Gen1i/1m 1.5 G receiver input DC specifications 3 Parameter Symbol Differential input voltage VSATA_RXDIFF Min Typical Max Units Notes 240 500 600 mV p-p 1 Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2 OOB signal detection threshold 50 120 240 mV p-p — VSATA_OOB Notes: 1. Voltage relative to common of either signal comprising a differential pair. 2. DC impedance. 3. For recommended operating conditions, see Table 4. This table provides the Gen2i/2m or 3 Gbit/s differential receiver input DC characteristics for the SATA interface. Table 131. Gen2i/2m 3 G receiver input DC specifications 3 Parameter Symbol Min Typical Max Units Notes Differential input voltage VSATA_RXDIFF 240 — 750 mV p-p 1 Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2 OOB signal detection threshold VSATA_OOB 75 120 240 mV p-p 2 Notes: 1. Voltage relative to common of either signal comprising a differential pair. 2. DC impedance. 3. For recommended operating conditions, see Table 4. This table provides the Gen 3i differential receiver input DC characteristics for the SATA interface. Table 132. Gen 3i receiver input DC specifications 3 Parameter Symbol Differential input voltage VSATA_RXDIFF Min Typical Max Units Notes 240 — 1000 mV p-p 1 Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2 OOB signal detection threshold 75 120 200 mV p-p — — Notes: 1. Voltage relative to common of either signal comprising a differential pair. 2. DC impedance. 3. For recommended operating conditions, see Table 4. 3.23.5.2 SATA AC timing specifications This section describes the SATA AC timing specifications. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 177 Electrical characteristics 3.23.5.2.1 AC requirements for SATA REF_CLK This table provides the AC requirements for the SATA reference clock. These requirements must be guaranteed by the customer's application design. Table 133. SATA reference clock input requirements6 Parameter Symbol Min Typ Max Unit Notes SDn_REF_CLK1_P/SDn_REF_CLK1_N frequency range tCLK_REF — 100/125 — MHz 1 SDn_REF_CLK1_P/SDn_REF_CLK1_N clock frequency tolerance tCLK_TOL -350 — +350 ppm — SDn_REF_CLK1_P/SDn_REF_CLK1_N reference clock duty cycle tCLK_DUTY 40 50 60 % 5 SDn_REF_CLK1_P/SDn_REF_CLK1_N cycle- tCLK_CJ to-cycle clock jitter (period jitter) — — 100 ps 2 SDn_REF_CLK1_P/SDn_REF_CLK1_N total tCLK_PJ reference clock jitter, phase jitter (peak-to-peak) -50 — +50 ps 2, 3, 4 Notes: 1. Caution: Only 100 and 125 MHz have been tested. In-between values do not work correctly with the rest of the system. 2. At RefClk input. 3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12. 4. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps. 5. Measurement taken from differential waveform. 6. For recommended operating conditions, see Table 4. 3.23.5.2.2 AC transmitter output characteristics This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 1i/1m or 1.5 Gbit/s transmission. The AC timing specifications do not include RefClk jitter. Table 134. Gen 1i/1m 1.5 G transmitter AC specifications2 Parameter Symbol Min Typ Max Units Notes Channel speed tCH_SPEED — 1.5 — Gbit/s — Unit interval TUI 666.4333 666.6667 670.2333 ps — Total jitter data-data 5 UI USATA_TXTJ5UI — — 0.355 UI p-p 1 Total jitter, data-data 250 UI USATA_TXTJ250UI — — 0.47 UI p-p 1 Deterministic jitter, data-data 5 UI USATA_TXDJ5UI — — 0.175 UI p-p 1 Deterministic jitter, data-data 250 UI USATA_TXDJ250UI — — 0.22 UI p-p 1 Notes: 1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern. 2. For recommended operating conditions, see Table 4. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 178 NXP Semiconductors Electrical characteristics This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 2i/2m or 3.0 Gbit/s transmission. The AC timing specifications do not include RefClk jitter. Table 135. Gen 2i/2m 3 G transmitter AC specifications2 Parameter Symbol Min Typ Max Units Notes Channel speed tCH_SPEED — 3.0 — Gbit/s — Unit Interval TUI 333.2167 333.3333 335.1167 ps — Total jitter fC3dB = fBAUD ÷ 500 USATA_TXTJfB/500 — — 0.37 UI p-p 1 Total jitter fC3dB = fBAUD ÷ 1667 USATA_TXTJfB/1667 — — 0.55 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_TXDJfB/500 — — 0.19 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 1667 — — 0.35 UI p-p 1 USATA_TXDJfB/1667 Notes: 1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern. 2. For recommended operating conditions, see Table 4. This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 3i transmission. The AC timing specifications do not include RefClk jitter. Table 136. Gen 3i transmitter AC specifications 1 Parameter Symbol Min Typ Max Units Speed — — 6.0 — Gbit/s Total jitter before and after compliance interconnect channel JT — — 0.52 UI p-p Random jitter before compliance interconnect channel JR — — 0.18 UI p-p Unit interval UI 166.6083 166.6667 167.5583 ps Notes: 1. For recommended operating conditions, see Table 4. 3.23.5.2.3 AC differential receiver input characteristics This table provides the Gen1i/1m or 1.5 Gbit/s differential receiver input AC characteristics for the SATA interface. The AC timing specifications do not include RefClk jitter. Table 137. Gen 1i/1m 1.5 G receiver AC specifications2 Parameter Unit Interval Symbol TUI Min 666.4333 Typical 666.6667 Max 670.2333 Units ps Notes — Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 179 Electrical characteristics Table 137. Gen 1i/1m 1.5 G receiver AC specifications2 (continued) Parameter Symbol Min Typical Max Units Notes Total jitter data-data 5 UI USATA_RXTJ5UI — — 0.43 UI p-p 1 Total jitter, data-data 250 UI USATA_RXTJ250UI — — 0.60 UI p-p 1 Deterministic jitter, data-data 5 UI USATA_RXDJ5UI — — 0.25 UI p-p 1 Deterministic jitter, data-data 250 UI USATA_RXDJ250UI — — 0.35 UI p-p 1 Notes: 1. Measured at the receiver. 2. For recommended operating conditions, see Table 4. This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbit/s transmission. The AC timing specifications do not include RefClk jitter. Table 138. Gen 2i/2m 3 G receiver AC specifications2 Parameter Symbol Min Typical Max Units Notes Unit Interval TUI 333.2167 333.3333 335.1167 ps — Total jitter fC3dB = fBAUD ÷ 500 USATA_RXTJfB/500 — — 0.60 UI p-p 1 Total jitter fC3dB = fBAUD ÷ 1667 USATA_RXTJfB/1667 — — 0.65 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_RXDJfB/500 — — 0.42 UI p-p 1 — — 0.35 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_RXDJfB/1667 Notes: 1. Measured at the receiver. 2. For recommended operating conditions, see Table 4. This table provides the differential receiver input AC characteristics for the SATA interface at Gen 3i transmission. The AC timing specifications do not include RefClk jitter. Table 139. Gen 3i receiver AC specifications2 Parameter Symbol Min Typical Max Units Notes Total jitter after compliance interconnect channel JT — — 0.60 UI p-p 1 Random jitter before compliance interconnect channel JR — — 0.18 UI p-p 1 Unit interval: 6.0 Gb/s UI 166.6083 166.6667 167.5583 ps — Notes: 1. Measured at the receiver. 2. The AC specifications do not include RefClk jitter. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 180 NXP Semiconductors Security fuse processor 4 Security fuse processor This chip implements the QorIQ platform's trust architecture, supporting capabilities such as secure boot. Use of the trust architecture feature is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the trust architecture and SFP can be found in the chip reference manual. To program SFP fuses, the user is required to supply 1.8 V to the TA_PROG_SFP pin per Power sequencing. TA_PROG_SFP should only be powered for the duration of the fuse programming cycle, with a per device limit of six fuse programming cycles. All other times, TA_PROG_SFP should be connected to GND. The sequencing requirements for raising and lowering TA_PROG_SFP are shown in Figure 9. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature range per Table 4. NOTE Users not implementing the QorIQ platform's trust architecture features should connect TA_PROG_SFP to GND. 5 Hardware design considerations 5.1 Clock ranges This table provides the clocking specifications for the processor core, platform, memory, and integrated flash controller. Table 140. Processor, platform, and memory clocking specifications Characteristic Maximum processor core frequency 1200 MHz Min 1400 MHz Max Min 1600 MHz Max Min Unit Notes 1800 MHz Max Min Max Core cluster group PLL frequency 1000 1200 1000 1400 1000 1600 1000 1800 MHz 1, 2 Platform clock frequency 400 400 400 600 400 700 400 700 MHz 1, 3 Memory Bus Clock Frequency (DDR4) 650 800 650 1050 650 1050 650 1050 MHz 1, 4, 5 IFC clock frequency - 100 - 100 - 100 - 100 MHz FMan 400 600 400 600 400 800 400 800 MHz Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 181 Hardware design considerations Table 140. Processor, platform, and memory clocking specifications (continued) Characteristic Maximum processor core frequency 1200 MHz Min Max 1400 MHz Min 1600 MHz Max Min Max Unit Notes 1800 MHz Min Max 1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies. 2. The memory bus clock speed is half the DDR4 data rate. The DDR4 memory bus clock frequency is limited to min = 650 MHz. 3. The memory bus clock speed is dictated by its own PLL. 4. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by the IFC module input clock (platform clock / 2) divided by the IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information. 5. The minimum platform frequency should meet the requirements in Minimum platform frequency requirements for highspeed interfaces. 6. For supported voltage/frequency options, see the orderable part list of QorIQ LS1046A and LS1026A Multicore Communications Processors at www.nxp.com. 5.1.1 DDR clock ranges The DDR memory controller can run only in asynchronous mode, where the memory bus is clocked with the clock provided on the DDRCLK input pin, which has its own dedicated PLL. This table provides the clocking specifications for the memory bus. Table 141. Memory bus clocking specifications Characteristic Memory bus clock frequency and data rate for DDR4 Min Freq.(MHz) 650 Max Freq.(MHz) 1050 Min Data Rate (MT/s) 1300 Max Data Rate (MT/s) 2100 Notes 1, 2, 3 Notes: 1. Caution: The platform clock to SYSCLK ratio, core to SYSCLK ratio and DDR to SYSCLK (or DDRCLK) ratio settings must be chosen such that the resulting platform frequency, core frequency and DDRCLK frequency do not exceed their respective maximum or minimum operating frequencies. 2. The memory bus clock refers to the chip's memory controllers' Dn_MCK[0:1] and Dn_MCK[0:1] output clocks, running at half of the DDR data rate. 3. The memory bus clock speed is dictated by its own PLL. 4. For supported voltage/frequency options, see the orderable part list of QorIQ LS1046A and LS1026A Multicore Communications Processors at www.nxp.com. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 182 NXP Semiconductors Thermal 5.2 Minimum platform frequency requirements for high-speed interfaces The platform clock frequency must be considered for proper operation of high-speed interfaces as described below. For proper PCI Express operation, the platform clock frequency must be greater than or equal to: 527 MHz x (PCI Express link width) 16 Figure 88. Gen 1 PEX minimum platform frequency 527 MHz x (PCI Express link width) 8 Figure 89. Gen 2 PEX minimum platform frequency 527 MHz x (PCI Express link width) 4 Figure 90. Gen 3 PEX minimum platform frequency See section "Link Width," in the chip reference manual for PCI Express interface width details. Note that "PCI Express link width" in the above equation refers to the negotiated link width as the result of PCI Express link training, which may or may not be the same as the link width POR selection. It refers to the widest port in use, not the combined width of the number ports in use. 5.3 Minimum DPAA frequency requirements The minimum DPAA frequency of 533 MHz is required for 10 G operations. 6 Thermal This table shows the thermal characteristics for the chip. Note that these numbers are based on design estimates and are preliminary. Table 142. Package thermal characteristics Rating Board Symbol Value Unit Notes Junction-to-ambient, natural convection Single-layer board (1s) RΘJA 25.18 °C/W 1 Junction-to-ambient, natural convection Four-layer board (2s2p) RΘJA 14.35 °C/W 1 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 183 Thermal Table 142. Package thermal characteristics (continued) Rating Board Junction-to-ambient, moving air (1 m/s) Single-layer board (1s) Junction-to-ambient, moving air (1 m/s) Symbol RΘJMA Value Unit Notes 15.47 °C/W 1 Four-layer board (2s2p) RΘJMA 9.35 °C/W 1 Junction-to-board - RΘJB 4.66 °C/W 2 Junction-to-case (top) - RΘJC 0.71 °C/W 3 Junction-to-lid top - RΘJLT 0.36 °C/W 4 1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-2A and JESD51-6 (moving air). Thermal test board meets JEDEC specification for this package (JESD51-9). 2. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 3. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4. Junction-to-lid-top thermal resistance is determined using the MIL-STD 883 Method 1012.1. However, instead of the cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the thermal resistance layer between the package and cold plate. 5. Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a specific standardized environment. It is not meant to predict the performance of a package in an application-specific environment Table 143. Thermal resistance with heat sink in open flow Heat sink with thermal grease Air flow Thermal resistance (°C/W) Wakefield 53 x 53 x 25 mm Pin Fin Natural Convection 6.5 0.5 m/s 4.0 1 m/s 2.9 2 m/s 2.4 4 m/s 2.1 Natural Convection 8.8 0.5 m/s 5.3 1 m/s 4.2 2 m/s 3.9 4 m/s 3.3 Natural Convection 12.5 0.5 m/s 8.9 1 m/s 6.7 2 m/s 5.1 4 m/s 4.1 Natural Convection 9.0 0.5 m/s 5.8 1 m/s 4.3 2 m/s 3.2 4 m/s 2.7 Wk698 Aavid 35x31x23 mm Pin Fin av10563 Aavid 30x30x9.4 mm Pin Fin Av 3358 Aavid 43x41x16.5 mm Pin Fin Av 2332 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 184 NXP Semiconductors Thermal Table 143. Thermal resistance with heat sink in open flow (continued) 1. Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. 2. The thermal interface material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease. 3. See Thermal management information, for additional details. 6.1 Recommended thermal model Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local NXP sales office. 6.2 Temperature diode The chip has temperature diodes that can be used to monitor its temperature by using some external temperature monitoring devices (such as ADT7481A™). The following are the specifications of the chip temperature diodes: • Operating range: 10 - 230 μA • Ideality factor over temperature range 85°C - 105°C, n = 1.006 ± 0.003, with approximate error ± 1°C and error under ± 3°C for temperature range 0°C - 85°C. 6.3 Thermal management information This section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design-the heat sink, airflow, and thermal interface material. The recommended attachment method to the heat sink is illustrated in Figure 91. The heat sink should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 15 pounds force (65 N). QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 185 Thermal Heat sink FC-PBGA package (with lid) Heat sink clip Adhesive or thermal interface material Die lid Die Lid adhesive Printed circuit-board Figure 91. Package exploded, cross-sectional view-FC-PBGA The system board designer can choose between several types of heat sinks to place on the device. There are several commercially available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 6.3.1 Internal package conduction resistance For the package, the intrinsic internal conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance • The die junction-to-lid-top thermal resistance • The die junction-to-board thermal resistance This figure shows the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 186 NXP Semiconductors Thermal External resistance Radiation Convection Junction to case top Heat sink Thermal interface material Junction to lid top Die/Package Internal resistance Die junction Package/Solder balls Printed-circuit board External resistance Radiation Convection (Note the internal versus external package resistance) Figure 92. Package with heat sink mounted to a printed-circuit board The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. 6.3.2 Thermal interface materials A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by means of a spring clip attachment to the printed-circuit board (see Figure 91). QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 187 Package information The system board designer can choose among several types of commercially available thermal interface materials. 7 Package information 7.1 Package parameters for the FC-PBGA The package parameters are as provided in the following list. The package type is 23 mm x 23 mm, 780 flip-chip, plastic-ball, grid array. • • • • • • • Package outline - 23 mm x 23 mm Interconnects - 780 Ball Pitch - 0.8 mm Ball Diameter (nominal) - 0.45 mm Ball Height (nominal) - 0.3 mm Solder Balls Composition - 96.5% Sn, 3% Ag, and 0.5% Cu Module height (typical) - 2.31 (minimum), 2.46 mm (typical), and 2.61 mm (maximum) 7.2 Mechanical dimensions of the FC-PBGA This figure shows the mechanical dimensions and bottom surface nomenclature of the chip. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 188 NXP Semiconductors Package information Figure 93. Mechanical dimensions of the FC-PBGA QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 189 Ordering information 1. 2. 3. 4. 5. 6. All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Parallelism measurement shall exclude any effect of mark on top surface of package. All dimensions are symmetric across the package center lines, unless dimensioned otherwise. 7. Pin 1 thru hole shall be centered within foot area. 8. 23.2 mm maximum package assembly (lid + laminate) X and Y. 8 Ordering information This table provides the NXP QorIQ platform part numbering nomenclature. 8.1 Part numbering nomenclature This table provides the NXP QorIQ platform part numbering nomenclature. Table 144. Part numbering nomenclature X = Extended (-40 - 1050C) n c d r E= 8 = LCFC Encryption 780 balls M = 1200 MHz N = NonEncryption P = 1400 MHz Q= 1600 MHz A= Rev 1.0 Package Type A = Arm S = Standard ( 0 - 1050C) Encryption 6 e Die Revision t DDR Data Rate 02 = Two Cores x CPU Speed1,2 04 = Four Cores n Temperature Range Number of Virtual cores Performance Level 1 nn Core Type LS = Layersc Blank="Qualifie ape d" n Unique ID P="Pre-qual" ls Generation Qual status p Q = 1600 MHz 1 = 2100 MHz T = 1800 MHz 1. For the LS1046A family of devices, parts marked with "M" require 0.9 V operating voltage. 2. For the LS1046A family of devices, only parts marked with "P", "Q", and "T" support extended temperature range. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 190 NXP Semiconductors Revision history 8.2 Part marking Parts are marked as in the example shown in this figure. LS10X6XXXXXXX ATWLYYWW MMMMM CCCCC YWWLAZ Legend: LS10X6XXXXXXX is the orderable part number ATWLYYWW is the test traceability code MMMMM is the mask number CCCCC is the country code YWWLAZ is the assembly traceability code Figure 94. Part marking for FC-PBGA chip LS1046A 9 Revision history This table summarizes revisions to this document. QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 191 Revision history Table 145. Revision history Revision Date Description 4 06/2020 • In Table 4 • Updated recommended value of USB_SVIN from "0.3 to USB_SVDD" to "GND to USB_SVDD" • Added note 10 for available temperature range for part numbers • Removed input signals from Table 5 as they are irrelevant for output drive capability • Removed typo "PORESET_B assertion" from step2 of secure boot fuse programming in Power sequencing • In Table 7 and Table 8 • Added note 9 regarding power numbers applicability • Added power numbers for 1200MHz at 1.0V • Added note 10 regarding power numbers applicability for 1200MHz at 1.0V • In Table 9 • Added column for Core Frequency = 1.2 GHz (VDD =1.0V) • For PH20 mode, corrected "run to PH20 state" as "PW15 to PH20 state" • For LPM20, corrected "PH20 to LPM20" as "PW15 to LPM20" • Added note 2 regarding extended temperature range in Table 144 3 07/2019 • Updated Figure 80 2 05/2019 • In Pinout list, • added note 27, 28 • changed the note reference of "D1_MALERT_B" signal from 6 to 27 • changed the note reference of "HRESET_B" signal from 6 to 28 • Removed switchable from I2C/DUART and EVDD • updated Warning • Removed section "General AC timing specifications" • Removed note 1 "Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequencies do not exceed their respective maximum or minimum operating frequencies." from Table 14 • Removed note 1 and 2 from Table 16 • Added Figure 11 • Added notes 6 and 7 in Table 23 • Added note 3 in Table 72 • In Table 89, • added a new column Notes • updated "CS to SCK delay" and "After SCK delay" parameters • removed "SCK cycle time" parameter • Updated section QSPI AC timing specifications • In section QSPI timing SDR mode, • updated "CS output hold time" and "CS output delay" parameters in Table 91 • added a note below the table • Updated Figure 61 • Updated section Temperature diode • Removed jitter specs of GTX_CLK125 from Table 18 • Added note in Power sequencing 1 03/2018 • • • • • • • • • • • In Features, updated two to three for SGMII interfaces supporting 2500 Mbps Updated Figure 92 In Power sequencing, updated 10 ms to 95 ms in second bullet point In Table 9, updated PW20 to PH20 and PCL10 to PH20 In Table 10, updated X1VDD to XVDD and PROG_SFP to TA_PROG_SFP Updated Figure 1 and Figure 2 to show 8 MACs In Table 12, updated PROG_SFP to TA_PROG_SFP Updated Real-time clock timing (RTC) Updated rise/fall time spec to 0.75ns and removed 0.54ns from Table 18 and Table 52 Removed Clock period jitter (peak to peak) row from Table 22 Updated first row of Table 23 Table continues on the next page... QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 192 NXP Semiconductors Revision history Table 145. Revision history (continued) Revision Date Description • • • • • • • • • 0 02/2017 Removed table "PLL lock times" Removed note reference 7 from Table 24 In SGMII interface, updated XGNDn to GNDn Updated note for USB_SDVDD for HS and USB_SVDD for SS in Table 2 Updated eSDHC to SDHC and corrected signal name eSDHC_CMD/DAT0_DIR to SDHC_CMD_DIR/DAT0_DIR in Table 4 Updated TA_BB_VDD power dissipation numbers in Table 11 Added note 9 in Table 52 Added rms clock jitter for PCIe- 8GT/s in Table 113 Added notes to Table 38 and Table 42 initial public release QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020 NXP Semiconductors 193 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. 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