MC06XS4200BFK

NXP Semiconductors Data Sheet: Technical Data Document Number: MC06XS4200 Rev. 6, 3/2022 Dual 24 V, 6.0 mOhm high-side switch 06XS4200 The 06XS4200 device is part of a 24 V dual high-side switch product family with integrated control and a high number of protective and diagnostic functions. It has been designed for truck, bus, and industrial applications. The low RDS(on) channels ( VWAKE Sleep state supply current mA mA μA IPWR(SLEEP) VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0 : 1] connected to ground • TA = 25 °C • TA = 125 °C VDD supply voltage VDD(ON) VDD supply current at VDD = 5.5 V IDD(ON) – 3.0 10.0 – – 60.0 3.0 – 5.5 V mA No SPI communication – – 2.2 8.0 MHz SPI communication(11) – 5.0 – VDD sleep state current at VDD = 5.5 V with or without VPWR IDD(SLEEP) – – 5.0 μA Overvoltage shutdown threshold VPWR(OV) 39 42 45.5 V Overvoltage shutdown hysteresis VPWR(OVHYS) 0.2 0.8 1.5 V VPWR(UV) 5.0 – 6.0 V Undervoltage shutdown threshold(12) VPWR power-on reset (POR) voltage threshold(12) VPWR(POR) 2.2 2.6 4.0 V VDD power-on reset (POR) voltage threshold(12) VDD(POR) 1.5 2.0 2.5 V VDD supply failure voltage threshold (assumed VPWR > VPWR(UV)) VDD(FAIL) 2.2 2.5 2.8 V Notes 10. In extended mode, availability of several device functions (channel control, value of RDS(on), overtemperature protection) is guaranteed, but compliance with the specified values in this document is not. Below 6.0 V, the device is only protected from overheating (thermal shutdown). Above VPWR(OV), the channels can only be turned ON when the overvoltage detection function has been disabled. 11. 12. Typical value guaranteed per design. When the device recovers from undervoltage and returns to normal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period (see Autoretry), the device performs normally. When VPWR drops below VPWR(UV), undervoltage is detected (see Undervoltage fault (Latchable fault) and EMC Performances). 06XS4200 9 NXP Semiconductors Table 4. Static electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. Unit – – 6.0 mΩ – – 6.0 – – 6.0 – – 12 – – 12 – – 12 -0.7 – +0.7 mΩ – – 12 mΩ cm ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) ON-resistance, Drain-to-Source (IHS = 3.0 A, TJ = 25 °C) CSNS_ratio = 0 • VPWR = 8.0 V • VPWR = 28 V RDS(ON)25 • VPWR = 36 V ON-resistance, Drain-to-Source (IHS = 3.0 A,TJ = 150 °C) CSNS_ratio = 0 • VPWR = 8.0 V RDS(ON)150 • VPWR = 28 V • VPWR = 36 V ON-resistance, Drain-to-Source difference from one channel to the other in parallel mode (IHS = 1.0 A,TJ = 150 °C) CSNS_ratio = X ON-resistance, Source-Drain (IHS = -3.0 A, TJ = 150 °C, VPWR = -24 V) ΔRDS(ON)150 RSD(ON)150 Max. detectable wiring length (2.5 mm²) for severe short-circuit detection (see Severe short-circuit fault (latchable fault)): • High slew rate selected • Medium slew rate selected • Low slew rate selected LSHORT Overcurrent detection thresholds with CSNS_ratio bit = 0 (CSR0) Overcurrent detection thresholds with CSNS_ratio bit = 1 (CSR1) Output (HS[x]) leakage current in sleep state (positive value = outgoing) mΩ 14 48 80 30 100 170 60 200 340 I_OCH1_0 90.0 110.0 128.3 I_OCH2_0 58.3 70.0 81.7 I_OCM1_0 36.1 43.3 50.6 I_OCM2_0 22.2 26.7 31.1 I_OCL1_0 15.0 18.0 21.0 I_OCL2_0 10.0 12.0 14.0 I_OCL3_0 5.0 6.0 7.0 I_OCH1_1 30.6 36.7 42.8 I_OCH2_1 19.4 23.3 27.2 I_OCM1_1 12.0 14.4 16.9 I_OCM2_1 7.4 8.9 10.4 I_OCL1_1 5.0 6.0 7.0 I_OCL2_1 3.3 4.0 4.7 I_OCL3_1 1.6 2.0 2.4 IOUT_LEAK A A µA 06XS4200, 06XS4200C VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state) VHS,OFF = VPWR, device in sleep state (VPWR = 24 V) – – +16 -40.0 – +5.0 – -120 -1400 – – – +16 +5.0 +5.0 06XS4200B, 06XS4200D VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state) VHS,OFF = VPWR, device in sleep state (VPWR = 24 V) VHS,OFF = VPWR, device in sleep state (VPWR = 36 V) 06XS4200 NXP Semiconductors 10 Table 4. Static electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) Output biasing current in off-state (positive value = outgoing) 06XS4200B, 06XS4200D with OL_OFF disabled (worst case VPWR = 36 V, VHS,OFF = 34 V) • • • • IOUT_OFF Fast slew rate selected Medium slew rate selected Slow slew rate selected With OL_OFF disabled and ECU ground disconnected (VPWR = 32 V) Switch turn-on threshold for supply overvoltage (VPWR -GND) Switch turn-on threshold for drain-source overvoltage (@ IHS = 100 mA) Switch turn-on threshold for Drain-Source overvoltage difference from one channel to the other in parallel mode (@ IHS = 100 mA) µA -770 -520 -390 0.0 -620 -420 -315 – -460 -310 -240 1000 VD_GND(CLAMP) 58 – 66 V VDS(CLAMP) 58 – 66 V -2.0 – +2.0 V CSR0 – 1/5000 – ΔVDS(CLAMP) Ratio(13) Current Sensing • CSNS_ratio bit = 0 (high-current mode) • CSNS_ratio bit = 1 (low-current mode) – CSR1 – 1/1666.6 – Minimum measurable load current with compensated error(14) I_LOAD_MIN – – 175 mA CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0) ICSR_LEAK -4.0 – +4.0 µA – 15 – – -22 – I_LOAD_ERR_RAND -360 – 360 mA ICSNS,MAX 5.15 – – mA Systematic offset error (see Current sense errors) • 06XS4200, 06XS4200C • 06XS4200B, 06XS4200D I_LOAD_ERR_SYS Random offset error CSNS pin current sourcing capability, absolute upper limit ESR0 output current sensing error (%, level (sense ratio CSR0 selected): uncompensated(15)) at output current mA ESR0_ERR % TJ = -40 °C 9.0 A -13 – 13 4.5 A -12 – 12 2.25 A -17 – 17 1.13 A -31 – 31 9.0 A -10 – 10 4.5 A -9.0 – 9.0 2.25 A -12 – 12 1.13 A -19 – 19 TJ = 125 °C TJ = 25 to 125 °C 9.0 A 4.5 A 2.25 A 1.13 A -10 – 10 -9.0 – 9.0 -12 – 12 -22 – 22 06XS4200 11 NXP Semiconductors Table 4. Static electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) ESR0 output current sensing error (%, after offset compensation(14)) at output current level (sense ratio CSR0 selected): ESR0_ERR(Comp) % TJ = -40 °C 9.0 A -10 – 10 4.5 A -10 – 10 2.25 A -10 – 10 1.13 A -10 – 10 9.0 A -9.0 – 9.0 4.5 A -8.0 – 8.0 2.25 A -9.0 – 9.0 1.13 A -9.0 – 9.0 -9.0 – 9.0 -8.0 – 8.0 -9.0 – 9.0 -9.0 – 9.0 -16 – 16 -12 – 12 -12 – 12 TJ = 125 °C TJ = 25 to 125 °C 9.0 A 4.5 A 2.25 A 1.13 A ESR1 output current sensing error (%, uncompensated (15)) at output current level (sense ratio CSR1 selected): ESR1_ERR TJ = -40 °C 2.25 A % TJ = 125 °C 2.25 A TJ = 25 to 125 °C 2.25 A Notes: 13. Current Sense Ratio CSRX = ICSNS / (IHS[x] + I_LOAD_ERR_SYS) 14. 15. See note (15), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration ESRX_ERR = (ICSNS_MEAS / ICSNS_MODEL) - 1, with ICSNS_MODEL = (I(HS[x]) + I_LOAD_ERR_SYS) * CSRX , (I_LOAD_ERR_SYS defined above, see section Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRX - I_LOAD_ERR_SYS 06XS4200 NXP Semiconductors 12 Table 4. Static electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) ESR1 output current sensing error (% after offset compensation(16)) at output current level (sense ratio CSR1 selected): ESR1_ERR(Comp) % TJ = -40 °C 2.25 A -10 – 10 0.75 A -11 – 11 0.375 A -18 – 18 0.225 A -29 – 29 2.25 A -8.0 – 8.0 0.75 A -10 – 10 0.375 A -12 – 12 0.225 A -16 – 16 -8.0 – 8.0 -10 – 10 -13 – 13 -21 – 21 TJ = 125 °C TJ = 25 to 125 °C 2.25 A 0.75 A 0.375 A 0.225 A ESR0 output current sensing error in parallel mode (%, uncompensated(17)) at outputs current level (sense ratio CSR0 selected): ESR0_ERR_PAR % TJ = -40 °C 9.0 A -10 – 10 4.5 A -11 – 11 9.0 A -8.0 – 8.0 4.5 A -8.0 – 8.0 -8.0 – 8.0 -8.0 – 8.0 VCL(CSNS) 5.5 – 7.5 V IOLD(OFF) 30 – 100 μA VOLD(THRES) 4.0 – 5.5 V TJ = 125 °C TJ = 25 to 125 °C 9.0 A 4.5 A Current sense clamping voltage (condition: R(CSNS) > 10 kOhm) Openload detection current threshold in OFF state Openload fault detection voltage threshold (18) (18) Notes: 16. 17. 18. See note (17), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration. ESRX_ERR = (ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRX , (I_LOAD_ERR_SYS defined above, see section Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRX - I_LOAD_ERR_SYS Minimum required value of OpenLoad impedance for detection of OpenLoad in OFF-state: 200 kΩ.(VOLD(THRES) = VHS @ IOLD(OFF)) 06XS4200 13 NXP Semiconductors Table 4. Static electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) Openload detection current threshold in ON state (see Openload detection in ON state (OL_ON)): IOLD(ON) mA CSNS_ratio bit = 0 06XS4200,06XS4200C 200.0 500.0 999.9 06XS4200B, 06XS4200D 135.0 500.0 999.9 5.0 7.0 10 CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this function) Time period of the periodically activated openload in ON state detection for CSNS_ratio bit = 1 tOLLED 105 150 195 ms Output shorted-to-VPWR detection voltage threshold (channel in OFF state) VOSD(THRES) VPWR-1.2 VPWR-0.8 VPWR-0.4 V Switch turn-on threshold for negative output voltages (protects against negative transients) - (measured at IOUT = 100 mA, channel in OFF state) VCL V 06XS4200,06XS4200C -35 – -24 06XS4200B, 06XS4200D -38 – -32 -2.0 – +2.0 V VHS_TH 0.45*VPWR 0.5*VPWR 0.55*VPWR V TSD 160 175 190 °C VIH 2.0 – 5.5 V VIL -0.3 – 0.8 V VWAKE 1.0 – 2.2 V IDWN 5.0 – 20 μA IUP_CSB 5.0 – 20 μA IUP_CONF 25 – 100 μA CSO – – 20 pF RDWN 125 250 500 kΩ CIN – 4.0 12 pF Switch turn-on threshold for negative output voltages difference from one channel to the other in parallel mode - (measured at IOUT = 100 mA, channel in OFF state) Switching state (ON/OFF) discrimination thresholds Shutdown temperature (Power MOSFET junction; 6.0 V < VPWR < 58 V) ΔVCL ELECTRICAL CHARACTERISTICS OF THE CONTROL INTERFACE PINS Logic input voltage, High(19) Logic input voltage, Low(19) (20) Wake-up threshold voltage (IN[0:1] and RSTB) Internal pull-down current source (on Inputs: CLOCK, SCLK and Internal pull-up current source (input CSB)(22) Internal pull-up current source (input CONF[0:1])(23) Capacitance of SO, FSB and FSOB pins in tri-state Internal pull-down resistance (RSTB and IN[0:1]) Input capacitance(24) SI)(21) Notes 19. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN[0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR and can tolerate voltages up to 58 V. 20. Voltage above which the device wakes up 21. Valid for VSI > 0.8 V and VSCLK > 0.8 V and VCLOCK > 0.8 V. 22. Valid for VCSB < 2.0 V. CSB has an internal pull-up current source derived from VDD 23. Pins CONF[0:1] are connected to an internal current source, derived from an internal voltage regulator (VREG ~ 3.0 V). 24. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing process but is not tested in production. 06XS4200 NXP Semiconductors 14 Table 4. Static electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. VDD-0.4 – – – – 0.4 - 2.0 0 2.0 Lighting applications 1.0 – 10 DC motor applications 50 – Infinite Unit ELECTRICAL CHARACTERISTICS OF THE CONTROL INTERFACE PINS (CONTINUED) SO high-state output voltage VSOH V (IOH = 1.0 mA) SYNC, SO, FSOB and FSB low-state output voltage VSOL V (IOL = -1.0 mA) SYNC, SO, CSNS, FSOB and FSB tri-state leakage current: CONF[0:1]: required values of the external pull-down resistor 4.3 μA ISO(LEAK) (0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V or V(CSNS) = 0 V) RCONF kΩ Dynamic electrical characteristics Table 5. Dynamic electrical characteristics Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. Unit OUTPUT VOLTAGE SWITCHING CHARACTERISTICS Rising and falling edge medium slew rate (SR[1:0] = 00)(25) • VPWR = 16 V • VPWR = 28 V SRR_00 SRF_00 • VPWR = 36 V Rising edge low slew rate (SR[1:0] = • VPWR = 16 V • VPWR = 28 V 01)(25) 0.164 – 0.65 0.28 – 0.79 0.34 – 0.90 0.081 – 0.32 0.14 – 0.395 0.17 – 0.45 SRR_01 SRF_01 • VPWR = 36 V Rising edge high slew rate / SR[1:0] = 10)(25) • VPWR = 16 V • VPWR = 28 V V/μs SRR_10 SRF_10 • VPWR = 36 V Rising/Falling edge slew rate matching per channel V/μs 0.29 – 1.30 0.55 – 1.58 0.68 – 1.80 0.75 – 1.2 -0.1 0.0 +0.1 -0.06 0.0 +0.06 -0.14 0.0 +0.14 39 - 145 SRR/SRF 16 V < VPWR < 36 V Edge slew rate difference from one channel to the other in parallel V/μs mode(25) ΔSR 16 V < VPWR < 36 V V/μs • SR[1:0] = 00 • SR[1:0] = 01 • SR[1:0] = 10 Output Turn-ON and Turn-OFF Delays (medium slew rate: SR[1:0] = 00)(26) 16 V < VPWR < 36 V μs t DLY_00 06XS4200 15 NXP Semiconductors Table 5. Dynamic electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Output turn-on and turn-off delays (low slew rate / SR[1:0] = 01) Symbol (26) 50 - 280 Unit μs μs 22 - 80 -25 0.0 25 Δ t RF_00 f PWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 00 Turn-on and turn-off delay time matching per channel (t DLY(ON) - t DLY(OFF)) Max. t DLY_10 16 V < VPWR < 36 V Turn-on and turn-off delay time matching per channel (t DLY(ON) - t DLY(OFF)) Typ. t DLY_01 16 V < VPWR < 36 V Output turn-on and turn-off delays (high slew rate / SR[1:0] = 10)(26) Min. μs Δ t RF_01 μs f PWM = 200 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 01 • 06XS4200,06XS4200C • 06XS4200B, 06XS4200D -60 0.0 60 -90 0.0 90 Notes 25. Rising and Falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 Ω resistive load (see Figure 4). 26. Turn-on delay time measured as delay between a rising edge of the channel control signal (IN[0 : 1] = 1) and the associated rising edge of the output voltage up to: VHS[0 : 1] = VPWR / 2 (where RL = 5.0 Ω). Turn-OFF delay time is measured as time between a falling edge of the channel control signal (IN[0 : 1] = 0) and the associated falling edge of the output voltage up to the instant at which: VHS[0 : 1] = VPWR / 2 (RL = 5.0 Ohm). 06XS4200 NXP Semiconductors 16 Table 5. Dynamic electrical characteristics (continued) Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min. Typ. Max. -13 0.0 13 Unit SWITCHING CHARACTERISTICS (CONTINUED) Turn-on and turn-off delay time matching per channel (t DLY(ON) - t DLY(OFF)) Δ t RF_10 f PWM = 1.0 kHz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 10 Delay time difference from one channel to the other in parallel mode(27) μs Δ t(DLY) 16 V < VPWR < 36 V μs -21 0.0 21 -25 0.0 25 -41 0.0 41 -50 0.0 50 -12 0.0 12 tFAULT – 5.0 8.0 μs tDETECT – 12.0 17 μs SR[1:0] = 00 • 06XS4200, 06XS4200C • 06XS4200B, 06XS4200D SR[1:0] = 01 • 06XS4200, 06XS4200C • 06XS4200B, 06XS4200D SR[1:0] = 10 Fault detection delay time(28) Output shutdown delay time(29) Current sense output settling time for SR[1:0] = 00 (medium slew rate) (30) 16 V < VPWR < 36 V Current sense output settling time for SR[1:0] = 01(low slew rate)(30) 0.0 - 200 0.0 - 315 μs t CSNSVAL_01 16 V < VPWR < 36 V Current sense output settling time for SR[1:0] = 10 (high slew rate)(30) μs t CSNSVAL_00 μs t CSNSVAL_10 16 V < VPWR < 36 V 0.0 SYNC output signal delay for SR[1:0] = 00 (medium SR) (30) - 165 μs t SYNCVAL_00 06XS4200, 06XS4200C 46 - 155 06XS4200B, 06XS4200D 50 - 160 SYNC output signal delay for SR[1:0] = 01 (low SR)(30) μs t SYNCVAL_01 06XS4200, 06XS4200C 55 - 280 06XS4200B, 06XS4200D 80 - 320 SYNC output signal delay for SR[1:0] = 10 (high SR) (30) t SYNCVAL_10 22 - 80 μs Recommended sync_to_read delay SR[1:0] = 00 (medium slew rate) (30) t SYNREAD_00 0.0 - 200 μs Recommended sync_to_read delay SR[1:0] = 01 (low slew rate) (30) t SYNREAD_01 0.0 - 200 μs t SYNREAD_10 0.0 - 200 μs ms Recommended sync_to_read delay SR[1:0] = 10 (high slew rate) Upper overcurrent threshold duration (30) tOCH1 6.0 8.6 11.2 tOCH2 12.0 17.2 22.4 Notes: 27. Rising and Falling edge slew rates specified for a 20 % to 80 % voltage variation on a 10.0 Ω resistive load (see Figure 4). 28. Time required to detect and report the fault to the FSB pin. 29. Time required to switch off the channel after detection of overtemperature (OT), overcurrent (OC), SC or UV error (time measured between start of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR 30. Settling time ( = t CSNSVAL_XX), SYNC output signal delay ( = t SYNCVAL_XX) and Read-out delay ( = t SYNREAD_XX) are defined for a stepped load current (100 mA< I(LOAD) 2.0 V) IOCH2 Default levels shown as solid lines Dynamic overcurrent window, activated when the IOCLX threshold is crossed Load Current IOCL1 IOCL2 Load current IOCL3 Time t OCM2_M t OCM1_M t OCH2 t OCH1 Figure 6. Overcurrent protection profile for applications with inductive loads (DC motors, solenoids) RSTB VIH 10% VDD VIL tWRSTB tCSB tENBL CSB 90% VDD VIH 10% VDD VIL tRSI tWSCLKh tLEAD tLAG VIH 90% VDD SCLK 10% VDD tSI(SU) VIL tWSCLKl tSI(H) SI Don’t Care 90% VDD 10% VDD tFSI VIH Must be Valid Don’t Care Must be Valid tSOEN SO Tri-stated Don’t Care VIL tSODIS Tri-stated VIH VIL Figure 7. Timing requirements during SPI communication 06XS4200 23 NXP Semiconductors tFSI tRSI VOH 90% VDD 50% SCLK 10% VDD VOL VOH 10% VDD SO VOL tRSO Low to High tVALID tFSO SO High To Low VOH 90% VDD 10% VDD VOL Figure 8. Timing diagram for serial output (SO) data communication turn-on control (from IN_s or CSB) See Figure 4 VHS[0:1] turn-off control (from IN_s or CSB) VPWR 50%VPWR Time VCSNS t DLY_XX 95% of scaled output current VSYNC 5.0 V 0.0 V t DLY_XX (t DLY(ON)) (t DLY(OFF) synchronous Mode t SYNCVAL Track & Hold Mode Time t CSNSVAL_xx t SYNREAD_xx Time Figure 9. Synchronous and Track & Hold current sensing modes: associated delay and settling times 06XS4200 NXP Semiconductors 24 5 Functional description 5.1 Introduction The 06XS4200 is a two-channel, 24 V high-side switch with integrated control and diagnostics designed for truck, bus, and industrial applications. The device provides a high number of protective functions. Both low RDS(on) channels (< 6.0 mOhm) can independently drive various load types like light bulbs, solenoid actuators, or DC motors. Device control and diagnostics are configured through a 16-bit SPI port with daisy chain capability. Independently programmable output voltage slew rates allow satisfying electromagnetic compatibility (EMC) requirements. Both channels can independently be operated in several different switching modes: internal clock, internal PWM mode (fully autonomous operation), external clock, and direct control switching mode. Current sensing with an adjustable ratio is available on both channels, allowing both high-current (bulbs) and low-current (LED) monitoring. By activating the Track & Hold mode, current monitoring can be performed during the switch-Off phase. This allows random access to the current sense functionality. A patented offset compensation technique further enhances current sense accuracy. To avoid turning off during inrush current, while being able to monitor it, the device features a dynamic overcurrent threshold profile. For bulbs, this profile is a stair function with stages of which the height and width are programmable through the SPI port. DC motors can be protected from overheating by activating a specific window-shaped overcurrent profile that allows stall currents of limited duration. Whenever communication with the external micro-controller is lost, the device enters Fail-safe Operation mode, but remains operational, controllable and protected. 5.2 Pin assignment and functions Functions and register bits that are implemented independently for both channels have extension “_s”. Max. ratings of the pins are given in Table 3. 5.2.1 Output current monitoring (CSNS) The CSNS pin allows independent current monitoring of channel 0 or channel 1 up to the steady-state overcurrent threshold. It can also be used to sense the device temperature. The different functions are selected by setting bits CSNS1_en and CSNS0_en to the appropriate value (Table 12). When the CSNS pin is sensed during switch-off in the (optional) Track & Hold mode, it outputs the scaled value of the load current as it was just before turn-Off. When several devices share the same pull-down resistor, the CSNS pins of unused devices must be tri-stated. This is accomplished by setting CSNS0_en = 0 and CSNS1_en = 0 in the GCR register. Settling time (tCSNSVAL_XX) is defined as the time between the instant at the middle of the output voltage’s rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the CSNS-pin has settled to ±5.0% of its final value. Anytime an overcurrent window is active, the CSNS pin is disabled (see Overcurrent detection on resistive and inductive loads). The current and temperature sensing functions are unavailable in Fail-safe mode and in Normal mode when operating without the VDD supply voltage. In order to generate a voltage output, a pull-down resistor is required (R(CSNS) = 1.0 kOhm typ. and 470 < R(CSNS) < 10 k). When the current sense resistor connected to the CSNS pin is disconnected, the CSNS voltage is clamped to VCL(CSNS). The CSNS pin can source currents up to about 5.6 mA. 5.2.2 Current sense synchronization (SYNC) To synchronize current sensing with an external process, the SYNC signal can be connected to a digital input of an external MCU. SYNC is asserted logic low when the current sense signal is accurate and ready to be read. The current sense signal on the CSNS pin has the specified accuracy tSYNREAD_XX seconds after the falling edge on the SYNC pin (Figure 9) and remains valid until a rising edge is generated. The rising edge that is generated by the SYNC pin at the turn-OFF instant (internal or external) may also be used to implement synchronization with the external MCU. Parameter tSYNCVAL_XX is defined as the time between the instant at the middle of the output-voltage rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the SYNC-pin drops below 0.4 V (VSOL). The SYNC pins of different devices can be connected together to save micro-controller input channels. However, in this configuration, the CSNS function of only one device should be active at a time. Otherwise, the MCU does not determine the origin of the SYNC signal. The SYNC pin is open drain and requires an external pull-up resistor to VDD. 06XS4200 25 NXP Semiconductors 5.2.3 Direct control inputs (IN0 and IN1) The IN[0:1] pins allow direct control of both channels. A logic [0] level turns off the channel and a logic[1] level turns it on (Channel control in Normal mode). When the device is in Sleep mode, a transition from logic 0 to logic 1 on any of these pins wake it up (Sleep mode). If it is desired to automatically turn on the channels after a transition to Fail-safe mode, inputs IN[0] and IN[1] must be externally connected to the VPWR pin by a pull-up resistor (e.g. 10 kOhm typ.). However, this prevents the device from going into Sleep mode. Both IN pins are internally connected to a pull-down resistor. 5.2.4 Configuration inputs (CONF0 and CONF1) The CONF[0 :1] input pins allow configuring both channels for the appropriate load type. CONF = 0 activates the bulb overcurrent protection profile, and CONF = 1 the DC motor profile. These inputs are connected to an internal voltage regulator of 3.3 V by an internal pull-up current source IUP. Therefore, CONF = 1 is the default value when these pins are disconnected. Details on how to configure the channels are given in the table Overcurrent Profile Selection. 5.2.5 Fault Status (FSB) This open-drain output is asserted low when any of the following faults occurs (see Fault mode): overcurrent (OC), overtemperature (OT), Output connected to VPWR, Severe short-circuit (SC), Openload in ON state (OL_ON), Openload in OFF state (OL_OFF), External Clock-fail (CLOCK_fail), overvoltage (OV), and undervoltage (UV). Each fault type has its own assigned bit inside the STATR, FAULTR_s, or DIAGR_s register. Fault type identification and fault bit reset are accomplished by reading out these registers. They are part of the SO register (Table 13) and are accessed through the SPI port. 5.2.6 Pwm clock (CLOCK) This pin is the input for an external clock signal that controls the internal PWM module.The clock signal is monitored by the device. The PWM module controls ON-time and turn-ON delay of the selected channels. The CLOCK pin should not be confused with the SCLK pin, which is the clock pin of the SPI interface. CLOCK has an internal pull-down current source (IDWN) to GND. 5.2.7 Reset (RSTB) All SPI register contents are reset when RSTB = 0. When RSTB = 0, the device returns to Sleep mode tIN sec. after the last falling edge of the last active IN[0:1] signal. As long as the Reset input (RSTB pin) is at logic 0 and both direct input states are low, the device remains in Sleep mode (Channel configuration through the SPI). A 0-to-1 transition on RSTB wakes up the device and starts a watchdog timer to check the continuous presence of the SPI signals. To do this, the device monitors the contents of the first bit (WDIN bit) of all SPI words following that transition (regardless the register it is contained in). When this contents is not alternated within a duration tWDTO, SPI communication is considered lost, and Fail-safe mode is entered (Entering Fail-safe mode). RSTB is internally pulled-down to GND by resistor RDWN. 5.2.8 Chip select (CSB) Data communication over the SPI port is enabled when the CSB pin is in the logic [0] state. Data from the Input Shift registers are locked in the addressed SI registers on the rising edge of CSB. The device transfers the contents of one of the 8 internal registers to the SO register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from a logic [1] to a logic [0] state only when SCLK is at logic [0] (Figure 7 and Figure 8). CSB is internally pulled up to VDD through IUP. 5.2.9 SPI serial clock (SCLK) The SCLK pin clocks the SPI data communication of the device. The serial input pin (SI) transfers data to the SI shift registers on the falling edge of the SCLK signal while data in the SO registers are transferred to the SO pin on the rising edge of the SCLK signal. The SCLK pin must be in the low state when CSB makes any transition. For this reason, it is recommended to have the SCLK pin in the logic [0] state when the device is not accessed (CSB is at logic [1]). When CSB is set to logic [1], signals at the SCLK and SI pins are ignored and the SO output is tri-stated (high-impedance). The SCLK pin is connected to an internal pull-down current source IDWN. 06XS4200 NXP Semiconductors 26 5.2.10 Serial input (SI) Serial input (SI) data bits are shifted in at this pin. SI data is read on the falling edge of SCLK. 16-bit data packages are required on the SI pin (see Figure 7), starting with bit D15 (MSB) and ending with D0 (LSB). All the internal device registers are addressed and controlled by a 4-bit address (D9-D12) described in Table 11. Register addresses and function attribution are described in Table 12. The SI pin is internally connected to a pull-down current source, IDWN. 5.2.11 Supply of the digital circuitry (VDD) This pin supplies the SPI circuit (3.3 V or 5.0 V). When lost, all circuitry becomes supplied by a VPWR derived voltage, except the SPI’s SO shift-register that can no longer be read. 5.2.12 Ground (GND) This is the GND pin common for both the SPI and the other circuitry. 5.2.13 Positive supply pin (VPWR) This pin is the positive supply and the common input pin of both switches. A 100 nF ceramic capacitor must be connected between VPWR and GND, close to the device. In addition, it is recommended to put a ceramic capacitor of at least 1.0 µF in parallel with this 100 nF capacitor. 5.2.14 Serial output (SO) The SO pin is a tri-stateable output pin that conveys data from one of the 13 internal SO registers or from the previous SI register to the outside world. The SO pin remains in a high-impedance state (tri-state) until the CSB pin becomes logic [0]. It then transfers the SPI data (device state, configuration, fault information). The SO pin changes state at the rising edge of the SCLK signal. For daisy-chaining, it can be read out on the falling edge of SCLK. VDD must be present before the SO registers can be read. The SO register assignment is described in Table 13. 5.2.15 Power switch output pins (HS0 and HS1) HS0 and HS1 are the output pins of the power switches, to be connected to the loads. A ceramic capacitor (< = 22 nF (+/- 20%) is recommended between these pins and GND for optimal EMC performances. 5.2.16 Fail-safe output (FSOB) This pin (active low) is used to indicate loss of SPI communication or loss of SPI supply voltage, VDD. This open-drain output requires an external pull-up resistor to VPWR. 06XS4200 27 NXP Semiconductors 5.3 Functional internal block description POWER SUPPLY internal regulator MCU INTERFACE MCU INTERFACE and OUTPUT CONTROL SELFPROTECTED High-side SWITCHES HS0-HS1 SPI INTERFACE PARALLEL CONTROL INPUTS PWM CONTROLLER Figure 10. Internal block description 5.3.1 Power supply The device operates with supply voltages from 6.0 to 58 V (VPWR), but is full spec. compliant between 8.0 and 36 V. The VPWR pin supplies power to the internal regulator, analog, and logic circuit blocks. The VDD pin (5.0 V typ.) supplies the output register of the Serial Peripheral Interface (SPI). Consequently, the SPI registers cannot be read without presence of VDD. The employed IC architecture guarantees a low quiescent current in Sleep mode. 5.3.2 Switch output pins HS0 and HS1 HS0 and HS1 are the output pins of the power switches. Both channels are protected against various kinds of short-circuits and have active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic functions are available. For large inductive loads, it is recommended to use a freewheeling diode. The device can be configured to control the output switches in parallel, which guarantees good switching synchronization. 5.3.3 Communication interface and device control In Normal mode the output channels can either be controlled by the direct inputs or by the internal PWM module, which is configured by the SPI register settings. For bidirectional SPI communication, VDD has to be in the authorized range. Failure diagnostics and configuration are also performed through the SPI port. The reported failure types are: Openload, short-circuit to battery, severe shortcircuit to ground, overcurrent, overtemperature, clock-fail, undervoltage, and overvoltage. The SPI port can be supplied either by a 5.0 V or by a 3.3 V voltage supply. For direct input control, VDD is not required. A Pulse Width Modulation (PWM) circuit allows driving loads at frequencies up to 1.0 kHz from an external or an internal clock. SPI communication is required to set these options. 06XS4200 NXP Semiconductors 28 6 Functional device operation 6.1 Operation and operating modes The device possesses two high-side switches (channels) each of which can be controlled independently. The device has four fundamental operating modes: Sleep, Normal, Fail-safe, and Fault mode, as shown in Table 6. Each channel can be controlled in three different ways in Normal mode: by a signal on the Direct Input pin, by an internal clock signal (autonomous operation) or by an external clock signal. For bidirectional SPI communication, a second supply voltage is required (VDD = 5.0 V or 3.3 V). When only the direct inputs IN[x] are used, VDD isn’t required. 6.1.1 Device start-up sequence To put the device in a known configuration and guarantee predictable behavior, the device must undergo a wake-up sequence. However, it should not be woken up earlier than the moment at which VPWR has exceeded its undervoltage threshold, VPWR(UV), and VDD has exceeded its supply failure threshold, VDD(FAIL). In applications using the SPI port, the device is typically put in wake mode by setting RSTB = 1. Wake-up of applications with direct input control can be achieved by having signals IN_ON[0] = 1 or IN_ON[1 ] = 1 (see Figure 11). After wake-up, all SPI register contents are reset (as defined in Table 12 and Table 13) and Normal mode is entered. All the device functions are available 50 µs later (typically). If the start-up sequence is not performed at device start-up, its configuration may be undetermined and correct operation is not guaranteed. In situations where the above described start-up sequence can not be performed, it is recommended to generate a wake-up event after the moment VPWR has reached the undervoltage threshold. 6.1.2 6.1.2.1 Channel configuration through the SPI Setting the channel configuration The channel configuration is determined by the contents of the pulse-width (PWMR_s), the configuration (CONFR_s) and the overcurrent (OCR_s) registers. They allow setting, among others, the following parameters: duty-cycle, delay, Slew Rate, PWM enable (PWM_en), clock selection (CLOCK_sel), prescaler (PR), and direct_input disable (DIR_dis). Extension “_s” means that these registers exist for each of both channels. Function assignment is described in detail in the section SI register addressing. 6.1.2.2 Reading back the channel’s status and settings The channel’s global switching and operating states (ON/OFF, normal/fault) are all contained in the SO-STATR register (see Table 13). The precise fault type can be found by reading out the FAULTR_s and STATR registers. The current channel settings (channel configuration) can be known by reading the PWMR, CONF, OCR, RETRYR, GCR, and DIAG registers (see section Serial output register assignment and further). 6.1.3 Normal mode Normal mode (bit NM = 1) can be entered in two ways: either by driving the device through the direct inputs (IN[x]) or by establishing SPI communication (requires RSTB = high). Bidirectional SPI communication additionally requires the presence of VDD. To maintain the device in Normal mode, communication must take place regularly (see Entering and maintaining Normal mode). The device is in Normal mode (NM) when: • VPWR (and VDD) are within the normal range and • wake-up = 1, and • fail-safe = 0, and • fault = 0. 6.1.3.1 Channel control in Normal mode In direct input mode, the channel’s switching state (ON/OFF) is controlled by the logic state of the direct input signal with the default values (00) of turn-on delay and slew rate, specified in Table 5. 06XS4200 29 NXP Semiconductors In internal clock mode, the switching state is controlled by an internal clock signal (Internal clock and internal PWM (Clock_int_s bit = 1)). Frequency, slew rate, duty-cycle, and turn-on delay are programmable independently for both channels. In external clock mode, the frequency of the external clock controls the output's PWM frequency, but slew rate, duty cycle, and turn-on delay are still programmable. 6.1.3.2 Factors determining the channel’s switching state The switching state of a channel is defined by the instantaneous value of the output voltage. It is defined as “On” when the output voltage V(HS[x]) > VPWR /2 and “Off” when V(HS[x]) < VPWR /2. The channel’s switching state should not be confused with the device’s internal channel control state hson[x] (= High-side On). Signal hson[x] defines the targeted switching state of the channel (On/Off). It is either controlled by the value of the direct input signal or by that of the internal/external clock signals combined with the SPI register settings. The value of hson[x] is given by the following boolean expression: hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and PWM_en[x] = 0)]. In this expression Duty_cycle[x] represents the value of the duty cycle, set by bits D7…D0 of the PWMR register (Table 7). The channel’s actual switching state may differ from the control signal’s state in the following cases: • short circuits to GND, before automatic turn-Off (t < tFAULT) • short circuits to VPWR when the channel is set to Off • VPWR < 13 V when Openload-in-Off-state detection is selected and the load is actually lost • during the turn-on transition as long as V(HS[x])< Vpwr/2 • during the turn-off transition as long as V(HS[x]) > Vpwr/2 6.1.3.3 Entering and maintaining Normal mode A 0-to-1 transition on RSTB, (when both VPWR and VDD are present) or on any of both direct inputs IN[x] (when only supplied by VPWR) puts the device in Normal mode. If desired, the device can be operated in Normal mode without VDD, but this requires that at least one of both direct inputs be regularly turned on (Operation and operating modes). To maintain the device in Normal mode (NM), communication must take place on a regular basis. For SPI communication, the state of the WDIN bit must be alternated at least every 310 ms (typ.) (tWDTO), unless the WD_disable bit is set to 1. For direct input control, the timing requirements are shown in Figure 11. A signal called IN_ON[x] is not directly accessible to the user but is used by the internal logic circuitry to determine the device state. When no activity is detected on a direct input pin (IN[x]) for a time longer than tIN = 250 ms (typ.), timeout is detected and IN_ON[x] goes low. When this occurs on both channels, Sleep mode is entered (Sleep mode), provided reset = RSTB = 0 It enters Fail-safe mode in case of a timeout on SPI communication or when VDD is lost after having been initially present (if this function was previously enabled by setting: VDD_FAIL_EN bit = [1]). Setting watchdog disabled (WD_dis = 1, D4 of the GCR register) avoids entering Fail-safe mode after watchdog timeout. Device behavior upon fault occurrence is explained in the paragraph on Faults (Fault mode). tIN IN[x] IN_ON[x] Figure 11. Relation between signals IN(x) and IN_ON[x] 6.1.3.4 Direct control mode When RSTB = 0 (and also in Fail-safe mode), the channels are merely controlled by the direct input pins IN[x]. All protective functions (OC, OT, SC, OV, UV) are operational including auto-retry. To avoid entering Sleep mode at frequencies < 4.0 Hz, reset should be set to RSTB = 1. 06XS4200 NXP Semiconductors 30 6.1.3.5 Going from Normal to Fail-safe, Fault or Sleep mode The device changes from Normal to Fail-safe (Fail-safe mode), Sleep mode (Sleep mode), or Fault mode (Fault mode), according to the value of the following signals (see Table 6). • wake-up = RSTB or IN_ON[0] or IN_ON[1] • fail-safe = (VDD Failure and VDD_FAIL_en) or (SPI watchdog timeout (tWDTO) and WD_dis = 0) • fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis) Table 6. Device operating modes Mode Wake-up Failsafe Fault Comments Sleep 0 x x All channels are OFF. Normal 1 0 0 The SPI Watchdog is active when: VDD = 5.0 V, WD_dis = 0, RST = 1 Fail-safe 1 1 0 The channels are controlled by the IN inputs. (see page 32) Fault 1 X 1 The channels are OFF, see page 32 x = Don’t care. Sleep (wake-up = 0) (wake-up = 1) and (fail-safe = 1) and (fault = 0) (wake-up = 1) and (fault = 1) (wake-up = 0) (fail-safe = 1) and (wake-up = 1) and (fault = 1) Fail-safe Fault (fail safe = 1) and (wake-up = 1) and (fault = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 0) (wake-up = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 1) Normal (fail-safe = 0) and (wakeup = 1) and (fault = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 0) (fail-safe = 1) and (wake-up = 1) and (fault = 0) Figure 12. Device operating modes 6.1.4 Sleep mode In Sleep mode, the channels and the SPI interface are turned off to minimize current consumption. The device enters Sleep mode (wake-up = 0) when both Direct Input pins IN(x) remain Off longer than tIN sec. (when reset is active; RSTB = 0). This is expressed as follows: • VPWR (and VDD) are within the normal range, and • wake-up = 0 (wake-up = RSTB or IN_ON[0] or IN_ON[1]) • and 06XS4200 31 NXP Semiconductors • fail-safe = X and • fault = X When employed, VDD must be kept in the normal range. Sleep mode is the default mode after the first application of the supply voltage (VPWR), prior to any I/O communication (RSTB and the internal states IN_ON[0:1] are still at logic [0]). All SPI register contents remain in their default state during sleep mode. 6.1.5 6.1.5.1 Fail-safe mode Entering Fail-safe mode Fail-safe mode is entered either upon loss of SPI communication or after loss of optional SPI supply voltage VDD (VDD out of range). The FSOB pin goes low and the channels are only controlled by the direct inputs (IN[0:1]). All protective functions remain fully operational. Previously latched faults are delatched and SPI register contents is reset (except bits POR and PARALLEL). The SPI registers can not be accessed. These conditions are also described by the following expressions: • VPWR is within the normal voltage range, and • wake-up = 1, fault = 0, and • fail-safe = 1 ((VDD Failure and VDD_FAIL_en = 1 before) or (t(SPI)> tWDTO and WD_dis = 0). The last condition describes the loss of SPI communication which is detailed in the next section. 6.1.5.2 Watchdog on SPI communication and Fail-safe mode When VDD is present, the SPI watchdog timer is started upon a rising edge on the RSTB pin. Thereafter the device monitors the state of the first bit (WDIN) of all received SPI words. When the state of this bit is not alternated at least once within a data stream of duration tWDTO = 310 ms typ., the device considers that SPI communication has been lost and enters Fail-safe mode. This behavior can be disabled by setting the bit WD_DIS = 1. The value of watchdog timeout is derived from an internal oscillator. 6.1.5.3 Returning from Fail-safe to Normal mode To exit Fail-safe mode and return to normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device (regardless the register it is contained in and regardless the values of the other bits in this register). Next, a second data word must be received within the timeout period (tWDTO = 310 ms typ.) to be able to change any SPI register contents. Upon entering Normal mode, the FSOB pin returns to logic high and previously set faults and SPI registers are reset, except bits POR, PARALLEL and fault bits of latchable faults that had actually been latched. 6.1.6 Fault mode The device enters Fault mode when any of the following faults occurs in Normal or Fail-safe mode: • Overtemperature fault, (latchable fault) • Overcurrent fault, (latchable fault) • Severe short-circuit fault, (latchable fault) • Output shorted to VPWR in OFF state (default: disabled) • Openload fault in OFF state (default: disabled) • Openload fault in ON state (default: disabled) • External Clock Failure (default: enabled) • Overvoltage fault (enabled by default) • Undervoltage fault, (latchable fault) The Fault Status pin (FSB) asserts a fault occurrence on any channel in real time (active low). Additionally, the assigned fault bit in the STATR_s or FAULTR_s register is set to one. Conversely to the FSB pin, a fault bit remains set until the corresponding register is read, even if the fault has disappeared. These bits can be read via the SO pin. Fault occurrence also results in a turn-off of the incurred channel, except for the following faults: Openload (ON and OFF state), External Clock Failure and Output(s) shorted to VPWR. Under and Overvoltage occurrence causes simultaneous turn-off of both channels. Details on the device’s behavior after the occurrence of one of the above faults can be found in Protection and diagnostic features. Fault mode (Operation and operating modes) is entered when: • VPWR (+VDD) were within the normal voltage range, and • wake-up = 1, and 06XS4200 NXP Semiconductors 32 • fail-safe = X, and • fault = 1 (see Going from Normal to Fail-safe, Fault or Sleep mode) 6.1.6.1 Resetting FAULT bits Registers STATR_s and FAULTR_s contain global and channel-specific fault information. Reading the register where the fault bit is contained clears it, provided failure cause disappearance was detected and the fault wasn’t latched. 6.1.6.2 Entering Fault mode from Fail-safe mode When a Fault occurs in Fail-safe mode, the device is in Fault/Fail-safe mode and behaves according to the description of fault mode. However, SPI registers remain reset and can not be accessed. Only the Direct Inputs control the channels. 6.1.6.3 Returning from Fault mode to Fail-safe mode When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Fail-safe mode and behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset. 6.1.7 Latchable faults An auto-retry function (see Auto-retry) controls how the device responds to the so-called latchable faults. Latchable faults are: overcurrent (OC), severe short-circuit (SC), overtemperature (OT), and undervoltage (UV). If a latchable fault occurs, the channel is turned off, the FSB terminal goes low, and the assigned fault bit is set. These bits can not be reset before the next turn-on event is generated by auto-retry. Next, the channel automatically turns on at a programmable interval (provided auto-retry was enabled and the channel wasn’t latched). If the failure disappears prior to the expiration of the available amount of auto-retries, the FSB pin automatically returns to logic [1], but the fault bit remains set. It can then still be reset by reading the SPI register it is contained in. However, the fault actually gets latched if the failure cause hasn’t disappeared at the first turn-on event following expiration of the available amount of auto-retries (see Auto-retry). In that case, the channel gets latched and the FSB terminal remains low. The fault bit can not be reset by reading out the associated SPI register prior to performing a delatch sequence (Fault delatching). 6.1.7.1 Fault delatching To delatch a latched channel and be able to turn it on again, a delatch sequence must be executed after disappearance of the failure cause. Delatching also resets the fault bit of latched faults (see Resetting FAULT bits). To reset the FSB pin, both channels must be delatched. Delatching is achieved either by alternating the state of the channels’ fault control signal fc[x] (generating a 1_0_1 sequence), or by resetting the auto-retry counter (provided retry is enabled). See Reset of the auto-retry counter. Delatching then actually occurs at the rising edge of the turn-on event. Signal fc[x] is an internal signal used by the device’s internal logic circuitry to control the diagnostic functions. The value of fc[x] depends on the state of the variables IN_ON[x], DIR_dis[x] and ON[x] and is expressed as follows: fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1) Alternating the fc[x] signal is achieved differently according to the way the user controls the device. • In direct-input controlled mode (DIR_dis_s = 0), the IN[x] pin must be set low, remain low for at least tIN seconds, and set high again (be switched On). This might happen automatically when operating at frequencies f fCLOCK(HIGH)), the external clock signal is ignored and a fault is detected (FSB = 0), the CLOCK_fail bit is set (OD2 in the DIAGR register). The state of the ON_s bit in the SPI register then determines the channel’s switching state. To return to external clock mode (and reset FSB), the clock-fail bit must be read and the external clock has to be within the authorized range again. 6.1.8.2 Internal clock and internal PWM (Clock_int_s bit = 1) By using a reference time slot (usually available from an external microcontroller), the period of each of the internal PWM clocks can be changed or calibrated (see Programmable PWM module). Calibration of the default period = 1/fPWM(0) reduces its maximum variation from about +/-30% to +/- 10%. The programming procedure is initialized by sending a dedicated word to the SI-CALR register (see Table 12). Next, the device sets the new value of the switching period in 2 steps. First it measures the time elapsed between the first falling edge on the CSB pin and the next rising edge on the CSB pin (tCSB). Then it changes the value of the internal clock period accordingly. The actual value of the channel’s switching period is obtained by multiplying the internal clock period by 256. tCSB CSB SI SI command ignored tCSB CALR_s Internal clock period of channel s Figure 14. Internal clock calibration When the duration of the negative CSB pulse is outside a predefined time slot (from t CSB(MIN) to t CSB(MAX)), the calibration event is ignored and the internal clock frequency remains unchanged. If the value (fPWM(0)) has not been previously calibrated, it remains at its default level. 6.1.8.3 Synchronization of both channels When internal clock signals are used to drive the PWM modules, perfect synchronization over a long time can not be achieved since both clock signals are independent. However, when the channels are driven by an external clock, perfect synchronization can be achieved by simultaneously setting PWM_en_1 = 1 and PWM_en_0 = 1. The best way to optimize EMC is to use an external clock with a staggered switch on delay (see Table 8). 6.1.9 Parallel operation The channels can be paralleled to drive higher currents. Setting the PARALLEL bit in the GCR register to logic [1] is mandatory in this case. The improved synchronization of both transistors allows an equal current distribution between both channels. In parallel mode, both output pins (HS[x]) must be connected (as well as both IN[x] pins in case of external control). CONF0 and CONF1 must be set to equal values. 1- Device configuration in Parallel mode: There are two ways to configure the On/Off control: SPI-configured PWM control and Direct Input Control. • SPI configured Parallel mode: The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as PARALLEL = 1, the contents of the corresponding registers in bank 1 are replaced by that of bank 0, except bits D6-D8 of the CONFR_1 register (configuration of the Open load/Output short-circuited diagnostics). After setting PARALLEL = 1, contents of SO registers in bank 0 are copied to registers of bank 1 only when new information is written in them. Bits OD3, OD4, and OD5 of both FAULTR_s registers (OLON, OLOFF, OS) are always reported independently. 06XS4200 35 NXP Semiconductors • Direct Input controlled Parallel mode: The IN0 and IN1 pins must be connected externally. 2- Diagnostics in Parallel mode: The Diagnostics in Parallel mode operate as follows: • Openload in OFF state and - Openload in ON state: The OL_ON and OL_OFF bits of both FAULTR registers independently reports failures of the channels according to the settings of bits D7 and D6 of the CONFR_s register. • Current sensing: Refer to the Table 23 for a description of the various current sensing modes. Only the Current sense ratio of bank 0 (D5 of the OCR_0 register) is considered. The corresponding bit in the OCR_1 register is copied from that of the OCR_0 register. • output shorted to battery: The OS-bit (OD3) of each of both FAULT registers independently report this fault, according to the settings of bit D8 of the CONFR_s reg. 3- Protections in Parallel mode: • Overcurrent: -Only the Configuration of overcurrent thresholds and blanking windows of channel 0 are considered. -In case overcurrent (OC) occurs on any channel, both channels are turned-off. Regardless the order of occurrence of overcurrent (OC), both OC-bits (OD0) in the FAULT registers are simultaneously set to logic 1. • severe short-circuit: In case of SC detection on any channel, both channels are turned-off and the SC bits (OD1) in both FAULT registers are simultaneously set to logic 1. • overtemperature: In case of OT detection on any channel, both channels are turned-off and both OT bits in the FAULT registers (OD2) are simultaneously set to logic 1. • auto-retry: Only one 4-bit auto-retry counter specifies the number of successive turn-on events on paralleled channels (RETRYR_0). The counter value in register RETRYR_1 (OD4…OD7) is copied from that in RETRYR_0. To delatch the channels, only channel 0 needs to be delatched. 6.2 6.2.1 6.2.1.1 Protection and diagnostic features Protective functions Overtemperature fault (Latchable fault) The channels have individual overtemperature detection. As soon as a channel’s junction temperature rises above TSD (175 °C typ.), it is turned OFF, the overtemperature bit (OT = OD2) is set, and FSB = 0. FSB can only be reset by turning ON the channel when the junction temperature of both channels has dropped below the threshold: TJ < TSD. Overtemperature is detected in ON and in OFF state: • If the channel is ON, the associated output is switched OFF, the OT bit is set, and FSB = 0. • If the channel is OFF: FSB goes to logic [0] and remain low until the temperature of both channels is below TSD and any of the channels is turned on again. The auto-retry function (if activated) automatically turns on the channel when the junction temperature has dropped below TSD. The OT fault bit can only be reset by reading out the FAULTR register, provided that TJ < TSD and FSB = 1 again. 6.2.1.2 Overcurrent fault (Latchable fault) When an overcurrent (OC) is detected, the channel is immediately turned Off (after t FAULT seconds). The OC-bit is set to 1 and FSB becomes low [0]. Overcurrent is detected anytime the load current crosses an overcurrent threshold or exceeds the window width of the selected overcurrent protection profile. This profile is a stair function with windows the height and width of which are preselected through the SPI port. The maximum allowable value of the load current at a particular moment in time is defined by levels I_OCH and I_OCM and 06XS4200 NXP Semiconductors 36 windows tOCM_x and tOCH (programmable by SPI bits). The steady-state overcurrent protection level I_OCL is defined by the settings of the OCL and HOCR bits. Anytime an overcurrent window is active, current sensing is blanked and SYNC becomes 1. 6.2.1.3 Overcurrent duration counter The load current can spend only a defined amount of time in a particular window of the overcurrent profile. If the time in the window exceeds the selected window width (tOCX) or the overcurrent threshold is crossed, the channel is turned off (OC fault), followed by autoretry (if enabled). An internal overcurrent duration counter is employed for this function. 6.2.1.4 Overcurrent detection on resistive and inductive loads According to the load type (resistive or inductive), one of two different overcurrent profiles should be selected. This is done by connecting a resistor with the appropriate value between the CONF[0:1] pins and GND (Table 9). Table 9. Overcurrent Profile Selection CONF[0:1] Resistor/Voltage Type of Load 1.0 kOhm < R(CONF[x]) < 10 kOhm resistive: CONF = 0, Lighting-Mode or 0 < V(CONF[X) < VIL (0.8 V) R(CONF[x]) > 50 kOhms inductive: CONF = 1, or VIH (2.0 V)< V(CONF) < 5.0 V DC motor mode When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high. This is illustrated by Figure 15. After turn on, the output voltage (second waveform (20 V/div.) and the output current (first waveform, 12 A/div.) rise immediately, but the current sense voltage (third waveform, 2.0 V/div, 1.0 V = 3.0 A) and its synchronization signal SYNC (fourth waveform, 5.0 V/div.) only become active at the end of the selected overcurrent window (duration tOCM2_L). Figure 15. Current sense blanking during overcurrent window activity Activation of the lighting profile is time driven and activation of the DC motor profile is event driven, as explained below. In lighting mode, the height of the overcurrent profile is defined by three different thresholds (I_OCH, I_OCM and I_OCL, which stand for the higher, the middle, and the lower overcurrent threshold), as illustrated by Figure 5. This profile has two adjacent windows the width of which is compatible with typical bulb inrush current profiles. The width of the first of these windows is either tOCH1 or tOCH2. The width of the second window is either tOCM1_L or tOCM2_L (see Table 18). The lighting profile is activated at each turn-on event, including auto-retry, except in switch mode. In switch mode, the profile is activated only at the first turn-on event, but is not renewed. During the on-period, the load current is continuously compared to the programmed overcurrent profile. The channel is switched Off when a threshold is crossed or a window width is exceeded. 06XS4200 37 NXP Semiconductors In DC motor mode, only one overcurrent window exists, defined by only two different thresholds (I_OCH and I_OCL) as illustrated by Figure 6. This window is opened anytime the output current exceeds the selected lower overcurrent threshold (IOCLx). In this case, the allowed overcurrent duration is defined by parameters tOCM1_M, tOCM2_M, tOCH1, and tOCH2. The selection of the different profiles and values is explained in the section Address A0100 — overcurrent protection configuration register (OCR_s). 6.2.1.5 Auto-retry after overcurrent shut off When auto-retry is activated, OC-latching (Overcurrent fault (Latchable fault)) only occurs after expiration of the available amount of auto-retries (described in section Auto-retry). 6.2.1.6 Switch mode operation and overcurrent duration Switch mode is defined as any device operation with a duty cycle lower than 100% at a frequency above fPWM_EXT (min.) or fPWM_INT (min.). The device may operate in Switch mode in internal/external PWM or in direct input mode. In switch mode, the accumulated time spent by the load current in a particular window segment during On-times of successive switching periods is identified by the aforementioned duration counter, and compared to the active segment width. The associated off-times are excluded by the duration counter. The channel is turned-off when the value of the counter exceeds the window width. In Figure 16, overcurrent detection shutdown is shown in case of switch mode operation with a duty cycle of 50% (solid line) and 100% (fully-on, dashed line). The device is turned off much later in switch mode than in fully-on mode, since the duration counter only counts overcurrent during on-times. Figure 16. Overcurrent shutdown in PWM mode (solid line) and fully-on mode (dashed line) 6.2.1.7 Reset of the duration counter Reset of the duration counter is achieved by performing a delatch sequence (Fault delatching). In lighting mode (CONFs = 0), this counter is also reset automatically at each auto-retry (but not in DC motor mode). In DC motor mode, the duration counter is reset either by performing a delatch sequence or (automatically) after occurrence of a new on-period without any overcurrent ([hson[x] = 1). Reset then actually occurs at the first turn-off instant following that on-period. In switch mode, the duration counter is not reset by normal PWM activity unless delatching is performed. 6.2.1.8 Severe short-circuit fault (latchable fault) When a severe short-circuit (SC) is detected at turn-ON (wiring length LLOAD< LSHORT, see Table 4), the channel is shut Off immediately. For wiring lengths above LSHORT, the device is protected from short-circuits by the normal overcurrent protection functions (Overcurrent fault (Latchable fault)). When an SC occurs, FSB goes low (logic [0]), and the SC bit is set, eventually followed by an autoretry. SC is of the latchable fault type (see Protection and diagnostic features and Fault delatching). 6.2.1.9 Overvoltage detection (enabled by default) By default, the supply overvoltage protection (VPWR) is enabled when overvoltage occurs (VPWR > VPWR(OV)), the device turns OFF both channels simultaneously, the FSB pin is asserted low, and the OV fault bit is set to logic [1]. The channels remain OFF until the supply 06XS4200 NXP Semiconductors 38 voltage drops below a threshold voltage VPWR < VPWR(OV) - VPWR(OVHYS). The OV bit can then be reset by reading out the STATR register. The overvoltage protection can be disabled by setting the OV_dis = 1 in the General Configuration (GCR) register. In this case, the FSB pin neither asserts a fault occurrence, nor turn the channels off. However, the fault register (OV bit) still reports an overvoltage occurrence (when VPWR > VPWR(OV)) as a warning. When VPWR > VPWR(OV), the value of the on-resistance on both channels (RDS(on)) still lays within the ranges specified in Table 4. 6.2.1.10 Undervoltage fault (Latchable fault) The channels are always turned off when the supply voltage (VPWR) drops below VPWR(UV). FSB drops to logic [0], and the fault register’s (common) UV bit is set to [1]. When the undervoltage condition then disappears, two different cases exist: • If the channel’s internal control signal hson[x] is off, FSB returns to logic [1], but the UV bit remains set until at least one output is turned on (warning). • If the channel’s control signal is on, the channel only turns on if a delatch or POR sequence is performed prior to the turn on request. The UV bit can then only be reset by reading out the STATR register. Auto-retry (if enabled) starts as soon as the UV condition disappears. 6.2.1.11 Extended mode protection In extended mode (6.0 V < VPWR < 8.0 V or 36 V < VPWR < 58 V), the channels are still fault protected, but compliance with the specified protection levels is not guaranteed. The register settings however (including previously detected faults) remain unaltered, provided VDD is within the authorized range. Below 6.0 V, the channels are only protected from overtemperature, and this fault only reports in the SPI register the moment VPWR has again risen above VPWR(UV). To allow the outputs to remain ON between 36 and 58 V, overvoltage detection should be disabled (by setting OV_dis = 1 in the GCR register). Faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if: • VDD < VDD(FAIL) with VPWR in the normal voltage range • VDD and VPWR are below the VSUPPLY(POR) voltage threshold • The corresponding SPI register is read after the disappearance of the failure cause (and delatching) 6.2.1.12 Drain/source overvoltage protection The device tries to limit the Drain-to-Source voltage by turning on the channel whenever VDS exceeds VDS(CLAMP). When a fault occurs (SC, OC, OT, UV), the device is rapidly switched Off (in t < tFAULT seconds), regardless the value of the selected slew rate. This may induce voltage surges on VPWR and/or the output pin (HS[x]) when connected to an inductive line/load. Turning on the device also dissipates the energy stored in the inductive supply line. This function monitors overvoltage for VPWR > 30 V. For supply voltages VPWR < 30 V, the device is protected from negative output voltages by automatically turning on the channel. The feature remains functional after device ground loss. 6.2.1.13 Supply overvoltage protection In order to protect the device from excessive voltages on the supply lines, the voltage between the device’s supply pins (VPWR and the GND) is monitored. When the VPWR-to-GND voltage exceeds the threshold VD_GND(CLAMP), the channel is automatically turned on. The feature is not operational in cases of ground loss. 6.2.1.14 Negative output voltage protection The device tries to limit the undervoltage on the output pins HS[x] when turning off inductive loads. When the output voltage drops below VCL, the channel is switched on automatically. This feature is not guaranteed after a device ground loss. The energy dissipation capabilities of the circuit are defined by the ECL [0:1] parameters. For inductive loads larger than 20 µH, it is recommended to employ a freewheeling diode. The three different overvoltage protection circuits are symbolically represented in Figure 17. The values of the clamping diodes are those specified in Table 4. Coupling factor k represents the current ratio between the current in the supply voltage measurement diode (zener) and the current injected into the MOSFET’s gate to turn it on. 06XS4200 39 NXP Semiconductors . VPWR K.Iz VDS(CLAMP)-Vth HS[x] DC Vth I2 VD_GND(Clamp) IMEG Load VCL-Vth GND Figure 17. Supply and output voltage protections 6.2.1.15 Reverse voltage protection on VPWR The device can withstand reverse supply voltages on VPWR down to -28 V. Under these conditions, the outputs are automatically turned On and the channel’s On-resistance (RDS(on)) is similar to that during positive supply voltages. No additional components are required to protect the VPWR circuit except series resistors (>8.0 k) between the direct inputs IN[0:1] and VPWR in case they are connected to VPWR. The VDD pin needs reverse voltage protection from an externally connected diode (Figure 23). 6.2.1.16 Load and system ground loss In case of load ground loss, the channel’s state does not change, but the device detects an Openload fault. In case of a system GND loss, the channels are turned off. 6.2.1.17 Device ground loss In the (improbable) case the device loses all of its three ground connections (pins 14, 17, and 22), the channels’ state (On/ Off), depends on several factors: the values of the series resistors connected to the device pins, the voltage of the direct input signals, the device’s momentary current consumption (influenced by the SPI settings) and the state of other high-side switches on the board when there are pins in common like FSB, FSOB and SYNC. In the below description, all voltages are referenced to the system (module) GND. When series resistors are used, the channel state can be controlled by entering Fail-safe mode. The channels are turned off automatically when the voltage applied to the IN[x] input(s) through the series resistor(s) is not higher than VDD and be turned on when the IN[x] input(s) are tied to VPWR. Fail-Safe is entered under the following conditions: • all unused pins are tied to the overall system’s GND connection by resistors > 8.0 k. • any device pin connected to external system components has a series resistors > 8.0 k (except pins VPWR, VDD, HS[0], HS[1] and R(CSNS)>2.0 k) • pins FSB, FSOB and SYNC are in the logic high-state when they are shared with other devices. This means that none of the other devices is in Fault or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, CSNS. When the device GND voltage becomes logic low (V(GND)< VIL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high (V(GND)> VIH), SPI communication is lost and Fail-safe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH. 06XS4200 NXP Semiconductors 40 6.2.2 6.2.2.1 Supply voltages out of range VDD out of range If the external VDD supply voltage is lost (or falls outside the authorized range: VDD VPWR (POR), after a period VPWR < VPWR (POR) (and VDD < VDD (POR) before and after) 2. VDD > VDD (POR) after a period with VDD < VDD (POR) (VPWR < VPWR (POR) before and after) POR is also set at the transition to wake-up (by setting RSTB = 1 or IN[x] = 1) when VPWR > VPWR (POR) (before and after) or VDD >VDD(POR) (before and after). POR is not performed when VPWR > VPWR (POR) after a period VPWR < VPWR (POR) (and VDD > VDD (POR) permanently). (fc[x] = 0) (OpenLoadOFF = 1 or OS = 1 or OV = 1) OFF (fc[x] = 1 and (OV = 0)) (fc[x]= 0 or OV = 1) (fc[x] = 0) (OpenLoadOFF = 1 or OS = 1 or OV = 1) (OpenLoadON = 1) ON Latched OFF (Retry = 1) (count = 16) Auto-retry Loop (after Retry Period and OV = 0 and OT = 0 and UV = 0) OFF (OpenloadOFF = 1 or OS = 1 or OV = 1 or UV = 1 or OT = 1) (fc[x] = 0) (OV = 1) (OpenLoadON = 1) ON (Retry = 1) = > count = count+1 Figure 18. State machine: fault occurrence and auto-retry 06XS4200 41 NXP Semiconductors 6.2.3 Auto-retry The auto-retry circuitry automatically tries to turn on the channel on a cyclic basis. Only faults of the latchable type (overcurrent, severe short-circuit, overtemperature (OT), and undervoltage (UV)) may activate auto-retry. For UV and OT faults, auto-retry only starts after disappearance of the failure cause (when auto-retry is enabled). The retry condition is expressed by: Retry[x] = OC[x] or SC[x] or OT[x] or UV. If Auto-retry has been enabled, its mode of operation depends on the settings of the auto-retry related bits (bits D0...D3 of the SIRETRY_s register, see Table 12) and the available amount of auto-retries (bits OD7...OD4 of the SO-RETRY_s reg.). More details can be found in Amount of auto-retries. If Auto-retry is disabled, latchable faults immediately latches upon their occurrence (see Protection and diagnostic features). 6.2.3.1 Auto-retry configuration To enable the auto-retry function, bit retry_s (D0 of the SI RETRY_s register) has to be set to the appropriate value. Auto-retry is enabled for retry_s = 0 when the channel is configured for lighting applications (CONF = 0). It is enabled for retry_s = 1 for DC motor applications (CONF[x] = 1). Table 10. Auto-retry activation for lamps (CONF = 0) and DC motors (CONF = 1) CONF[x] Retry_s bit auto-retry 0 0 enabled 0 1 disabled 1 0 disabled 1 1 enabled If auto-retry is enabled, an auto-retry sequence starts when the channel’s fault control signal is set to 1 (fc[x] = 1, see Fault delatching) and the retry condition applies (Retry[x] = 1, see Auto-retry). When a failure occurs (fault = 1), the channel automatically switches on again after the auto-retry period. The value of this period (tAUTO) is set through the SPI port (bits D2 and D3 of the RETRY_s register, see Table 22). When the failure cause disappears before expiration of the available amount of auto-retries, the device behaves normally (FSB = 1), but the retry counter keeps its current value and the fault bit remains set until it is cleared. This guarantees a maximum device availability without preventing fault detection. 6.2.3.2 Amount of auto-retries In case the device is configured for an unlimited amount of auto-retries (Retry_unlimited_s = 1), auto-retry continues as long as the device remains powered. The channel never be latches off. In case a limited amount of retries is selected (Retry-unlimited_s = 0), auto-retry continues as long as the value of the 4-bit auto-retry counter does not exceed 15 (bits OD4...OD7 of the RETRY_s register). After 15 retries, the Rfull bit of the STATR (OD4 for channel 0, OD5 for channel 1) register is set to logic high. The amount of available auto-retries is then reduced to one. If the fault still hasn’t disappeared at the next retry, the corresponding channel switches off definitively and the fault is latched (FSB = 0, see Protection and diagnostic features and Fault delatching). Any channel can be turned on at any moment during the auto-retry cycle by performing a delatch sequence. However, this does not reset the retry counter. The value of the auto-retry counter can be read back in Normal mode only (SO-RETRYR register bits OD7-OD4). 6.2.3.3 • • • • • Reset of the auto-retry counter Any one of the below events reset the retry counter: Fail-safe is entered (Fail-safe mode) Sleep mode is left (Sleep mode) POR occurs (Supply voltages out of range) the retry function is set to unlimited (bit Retry-unlimited_s = 1 (D1 = 1)) the retry function is disabled (retry_s bit = D0 of the RETRY_s register under goes a 1-0 transition for CONF = 1 and a 0-1 transition for CONF = 0). 06XS4200 NXP Semiconductors 42 If the channel is latched at the moment the auto-retry counter was reset (case 4), the channel is delatched, and be turned on after one retry period (if retry was enabled). 6.2.3.4 Auto-retry and overcurrent duration During the on-period following an auto-retry, the load current profile is compared to the length and height of the selected overcurrent threshold profile, as described in the section on overcurrent protection (See Overcurrent fault (Latchable fault)). When the lighting profile is activated, the overcurrent duration counter is reset at each auto-retry (to allow sustaining new inrush currents). For DC motor mode however, it is only reset at the turn-off event of the first PWM period without any overcurrent (see Reset of the duration counter). Figures 18 gives a description of the retry state machine with the various transitions between operating modes. 6.2.4 Diagnostic features Diagnostic functions openload-in-On state (OLON), openload-in-Off-state (OLOFF) and output short-circuited to VPWR (OS) are operational over the frequency and duty cycle ranges specified in Table 5. Occurrence of an OLON, OLOFF, or OS fault sets the associated bit in the FAULTR_s register but does not trigger automatic turn-off. Any of these diagnostic functions can be disabled by setting OLON_dis_s = 1, OLOFF_dis_s = 1, or OS_dis_s = 1 (bits D8...D6 of the CONFR reg.). The functions are guaranteed over the specified ranges for output capacitor values up to 22 nF (+/-20%). 6.2.4.1 Output shorted-to-VPWR fault The device detects short-circuits between the output and VPWR. The detection is performed during the Off-state. The output-shortedto-VPWR fault-bit (OS_s) is set whenever the output voltage rises above VOSD(THRES). The fault is reported in real time on the FSB pin and saved by the OS_s bit. Occurrence of this fault does not trigger automatic turn-off. Even if the short-circuit disappears, the OS_s bit does not clear until the FAULTR register is read. The function may be disabled by setting OS_dis_s = 1. The function operates over the duty cycle ranges specified in Diagnostic features. This type of event shall be limited to 1000 min during the vehicle lifetime. In case of permanent output shorted to the battery condition, it is needed to turn-on the corresponding channel. 6.2.4.2 Openload detection in OFF state Openload-in-OFF-state detection (OL_OFF) is performed continuously during each OFF-state (both for CSR0 and CSR1). This function is implemented by injecting a small current into the load (IOLD(OFF)). When the load is disconnected, the output voltage rises above VOLD(THRES). OL_OFF is then detected and the OL_OFF bit in the FAULTR register is set. If disappearance of the open load fault is detected, the FSB output pin returns to a high immediately, but the OL_OFF bit in the fault register remains set until it is cleared by a read out of the FAULTR register. The function may be disabled by setting OLOFF_dis_s = 1. The function operates over the duty cycle ranges specified in section Diagnostic features. 6.2.4.3 Openload detection in ON state (OL_ON) Openload-in-ON state detection (OLON) is performed continuously during the On-state for CSR0 over the ranges specified in section Diagnostic features. An Openload in ON state fault is detected when the load current is lower than the openload current threshold IOLD(ON). This happens at IOLD(ON) = 500 mA (typ.) for high current sense mode (CSR0), and at 7.0 mA (typ.) for low current mode. FSB is asserted low and the OLON bit in the fault register is set to 1 but the channel remains On. FSB goes high as soon as disappearance of the failure cause is detected, but the OL_ON bit remains set. In high current mode (CSR0), openload in ON state detection is done continuously during the On-state and the OLON-bit remains set even if the fault disappears. In high current mode, the OLON-bit is cleared when the FAULTR register is read during the Off state, even if the fault hasn't disappeared. The OLON bit is also cleared when the FAULTR register is read during the ON state, provided the failure cause (load disconnected) has disappeared. In low current mode (CSR1), OL_ON is done periodically instead of continuously and only operates when fast slew rate is selected. When the internal PWM module is used with an internal or external clock (case 1), the period is 150 ms (typ.). When the direct inputs are used (case 2), the period is that of the input signal. The detection instants in both cases are given by the following: 06XS4200 43 NXP Semiconductors 1. In internal PWM (int./ext. clock), low current mode (CSR1), Openload-in-ON state detection is not performed each switching period, but at a fixed frequency of about 7.0 Hz (each tOLLED = 150 ms typ.). The function is available for a duty cycle of 100%. OLON detection is also performed at 7.0 Hz, at the first turn-off event occurring 150 ms after the previous OL_ON detection event (before OS and OL_OFF). 2. In direct input, low current mode (CSR1), OL_ON is performed each switching period (at the turn-off instant) but the duty cycle is restricted to the values. Consequently, when the signal on the IN[x] pin has a duty cycle of 100%, OL_ON is not performed. To solve this problem, either the internal PWM function must be activated with a duty cycle of 100%, or the channel’s direct input must be disabled by setting Dir_dis_s = 1 (bit D5 of the CONFR-s register). The OLON-bit is only reset when the FAULTR register is read after occurrence of an OL_ON-detection event without fault presence. 6.2.4.4 Openload detection in discontinuous conduction mode If small inductive loads (solenoids / DC motors) are driven at low frequencies, discontinuous conduction mode may occur. Undesired openload in ON state errors may then be detected, as the inductor current needs some time to rise above the openload detection threshold after turn-on. This problem can be solved by increasing the switching frequency or by disabling the function and activating openload in Off state detection instead. When small DC motors are driven in discontinuous conduction mode, undesired openload in OFF state detection may also occur when the load current reaches 0 A during the OFF state. This problem can be solved by increasing the switching frequency or by enabling openload in OFF state detection only during a limited time, preferably directly after turn-off (see Diagnostic features). The signal on the SYNC pin can be used to identify the turn-off instant. 6.2.5 Current and temperature sensing The scaled values of either of the output currents or the temperature of the device’s GND pin (#14) can be made available at the CSNS pin. To monitor the current of a particular channel or the general device temperature, the CSNS0_en and CSNS1_en bits in the General Configuration Register (GCR) must be set to the appropriate values. When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high. 6.2.5.1 Instantaneous and sampled current sensing The device offers two possibilities for load current sensing: instantaneous (synchronous) sensing mode and Track & Hold mode (see Figure 9). In synchronous mode, the load current is mirrored through the current sense pin (Output current monitoring (CSNS)) and is therefore synchronous with it. After turn-off, the current sense pin does not output the channel current. In Track & Hold mode however, the current sense pin continues to mirror the load current as it was just before turn-off. Synchronous mode is activated by setting the T_H_en bit to 0, and Track & Hold mode by setting the T_H_en bit to 1. 6.2.5.2 Current sense ratio selection The load current is mirrored through the CSNS pin with a sense ratio (Figure 19) selected by the CSNS_ratio bit in the OCR register. To achieve optimal accuracy at low current levels, the lower current sensing ratio, called CSR1, must be selected. In that case, the overcurrent threshold levels are decreased. The best accuracy that can be obtained for either ratio is shown in Figure 20. The amount of current the CSNS pin can sink is limited to ICSNS,MAX..The CSNS pin must be connected to a pull-down resistor (470 Ohm < R(CSNS) TOTWAR). Reading either FAULT register clears both OTW bits. Bits OD5: OD0 of the Fault register (FAULTR_s) report the faults that occurred on the channel previously selected by bit SOA3 = A0 (Table 14). • bit OD0 = OC_s: overcurrent fault on channel s, • bit OD1 = SC_s: severe short-circuit on channel s, • bit OD3 = OS_s: output shorted to VPWR on channel s, • bit OD4 = OLOFF_s: open load in OFF state on channel s, • bit OD5 = OLON_s: open load in ON state on channel s. (The threshold value above which this fault is triggered depends on the selected current sense ratio; for CSR0 @ 500 mA typ. and for CSR1 @ 7.0 mA typ.). The Fault Status pin (FS) is set to 0 (active Low) upon occurrence of any of the above mentioned faults. Latched faults can only be delatched by the procedure described in Fault delatching. 06XS4200 55 NXP Semiconductors The FAULTR_s register is reset when it is read out, provided that the failure cause has disappeared and latched faults have been delatched. 6.3.16 Previous address SOA3 : SOA0 = A0010 (PWMR_s) The device outputs the contents of the addressed PWMR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). 6.3.17 Previous address SOA3 : SOA0 = A0011 (CONFR_s) The device outputs the contents of the addressed CONFR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). 6.3.18 Previous address SOA3 : SOA0 = A0100 (OCR_s) The device outputs the contents of the addressed OCR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). 6.3.19 Previous address SOA3 : SOA0 = A0101 (RETRYR_s) The device outputs the contents of the addressed RETRYR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). Bit OD8 contains the value of the OFP bit (offset positive), used for current sense offset compensation. Bits OD7: OD4 contain the real time value of the auto-retry counter. When these bits contain [0000], either auto-retry has not been enabled or Auto-retry did not occur. 6.3.20 Previous address SOA3 : SOA0 = 0110 (GCR) The device outputs the contents of the General Configuration Register (GCR) common to both channels. 6.3.21 Previous address SOA3 : SOA0 = 0111 (DIAGR_s) Bit OD8 ( Ch. 1 = CONF1) and bit OD7 ( Ch. 0 = CONF0) of the DIAGR_s register contain the values of the channels’ configuration bits (0 = bulb, 1 = DC motor) Bits OD6:OD5 contain the Product Identification (ID) number, equal to 10 for the present dual 6.0 mOhm product. Bits OD4:OD3 report the logic state of the direct inputs IN[1:0] in real time (1 = On, 0 = OFF), OD4 = Ch. 1, OD3 = Ch. 0. Bit OD2 reports a logic [1] in case an external clock error occurred (if an external clock was selected by Clock_int = 0) Bit OD1:OD0 report logic [1] in case a calibration failure occurred during calibration of a channel’s internal clock period. 06XS4200 NXP Semiconductors 56 7 Typical applications Figure 23 shows the electrical circuit of a typical truck application. A 70 W lamp and 120 W DC motor are driven. As an example, an external circuit is added that takes over load control in case Fail-safe mode is activated (FSOB goes low). This circuit allows keeping full control of both channels in case of SPI failure. VPWR VDD Voltage regulator 100 nF 10 µF 10 µF 100 nF VPWR VDD VPWR VDD VDD 10 k MCU 100 nF 10 k VDD 100 nF I/O CLOCK I/O FSB IN0 IN1 SCLK CSB I/O SO SI 8 k2 75 k GND A/D A/D FSOB SCLK CSB RSTB SI SO CONF0 CONF1 SYNC CSNS 1.0 k2 22 nF 2.0 k VPWR VDD 100 k 10 k 1.0 µF HS0 06XS4200 22 nF LOAD 0 HS1 22 nF M LOAD 1 GND 10 k VPWR External Control Circuitry direct controls (pedals, handles, etc.) Figure 23. Typical application with two different load types 06XS4200 57 NXP Semiconductors . VPWR VDD Voltage regulator 100 nF 10 µF 10 µF 100 nF VPWR VDD VPWR VDD VDD 10 k 100 nF 100 nF 1.0 ¬µF 10 k VDD I/O CLOCK I/O FSB IN0 IN1 MCU SCLK CSB I/O SO SI 75 k 75 k A/D GND VPWR VDD 100 k A/D 1.0 k2 22 nF FSOB SCLK CSB RSTB SI SO CONF0 CONF1 SYNC CSNS HS0 22 nF 06XS4200 M LOAD HS1 GND 2.0 k 10 k VPWR External Control Circuitry direct controls (pedals, handles,...) Figure 24. Two channels in parallel/recommended external current sense circuit 06XS4200 NXP Semiconductors 58 8 Packaging 8.1 Soldering information The 06XS4200 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. The maximum peak temperature during the soldering process should not exceed 260 °C for 10 seconds maximum duration. The AN2467 provides guidelines for Printed Circuit Board design and assembly. 8.2 Marking information The device is identified by the part number: 06XS4200. Device markings indicate information on the week and year of manufacturing. The date is coded with the last four characters of the nine character build information code (e.g. “CTKAH0929”). The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the week. For instance, the date code “0929” indicates the 29th week of the year 2009. 8.3 Package mechanical dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Package Suffix 23-pin PQFN FK Package outline drawing number 98ASA00428D 06XS4200 59 NXP Semiconductors 06XS4200 NXP Semiconductors 60 06XS4200 61 NXP Semiconductors 06XS4200 NXP Semiconductors 62 06XS4200 63 NXP Semiconductors 06XS4200 NXP Semiconductors 64 06XS4200 65 NXP Semiconductors 06XS4200 NXP Semiconductors 66 06XS4200 67 NXP Semiconductors 9 Revision history REVISION DATE DESCRIPTION OF CHANGES 8/2012 • Initial Release 2.0 5/2013 • • Grammatical accuracy and form consistency changes made. No changes to content Revised back page. Updated document properties. Added SMARTMOS sentence to first paragraph 3.0 4/2014 • • • • • • • • Added an Orderable parts table Added 06XS4200BFK to the ordering information Introduction of parameters related to 06XS4200B device (Table 1) Removed RDSON values at 1.0 A. Rectification of the inversion between ∆tDLY values at slow and medium slew rate Removed ECl_rep values Change the ECl_sing value New VD_GND clamp value for 06XS4200B 4.0 4/2014 • No technical changes. Revised back page. Updated document properties. 5/2018 • • • • • Updated as per CIN 201805019I Changed steady-state current value from 9.0 to 12 A listed under features on page 1 Updated IHS[0:1] value in Table 3 (changed 9.0 to 12) Added clarification for diagnostic range to Table 5 Updated load dump duration (changed 500 ms to 350 ms) and changed VPWR from 14 V to 28 V in Table 3 Updated Track & Hold current sensing mode 1.0 5.0 • 6.0 3/2022 • • Changed document status from “Advance Information” to “Technical Data” Added MC06XS4200CFK and MC06XS4200DFK parts to Table 1 as per CIN 202203024I (qualification of new parts in NXP ICN8 fab) 06XS4200 NXP Semiconductors 68 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. Home Page: NXP.com based on the information in this document. NXP reserves the right to make changes without further notice to any Web Support: http://www.nxp.com/support There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP Semiconductors B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2022. Document Number: MC06XS4200 Rev. 6 3/2022