NXP Semiconductors
Data Sheet: Technical Data
Document Number: MC10XS4200
Rev. 8, 3/2022
Dual 24 V, 10 mOhm high-side switch
10XS4200
The 10XS4200 device is part of a 24 V dual high-side switch product family with
integrated control, and a high number of protective and diagnostic functions. It
has been designed for truck, bus, and industrial applications. The low RDS(ON)
channels ( VIH
• 10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
• 10XS4200BAFK and 10XS4200BDFK
IPWR(ON)
VPWR supply current, device in wake-up mode (Standby), channel Off
Openload in OFF-state detection disabled, HS[0 : 1] shorted to ground with
VDD = 5.5 V and RSTB > VWAKE
IPWR(SBY)
Sleep state supply current
VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0 : 1] connected to ground
• TA = 25 °C
• TA = 125 °C
IPWR(SLEEP)
mA
mA
μA
VDD supply voltage
VDD(ON)
3.0
–
5.5
V
VDD supply current at VDD = 5.5 V
• No SPI communication
IDD(ON)
–
–
–
5.0
2.2
–
mA
• 8.0 MHz SPI communication(12)
10XS4200
NXP Semiconductors
8
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
parameter
Symbol
Min.
Typ.
Max.
Unit
VDD sleep state current at VDD = 5.5 V with or without VPWR
IDD(SLEEP)
–
–
5.0
μA
Overvoltage shutdown threshold
VPWR(OV)
39
42
45.5
V
VPWR(OVHYS)
0.2
0.8
1.5
V
VPWR(UV)
5.0
–
6.0
V
VPWR(POR)
2.2
2.6
4.0
V
VDD(POR)
1.5
2.0
2.5
V
VDD(FAIL)
2.2
2.5
2.8
V
Overvoltage shutdown hysteresis
Undervoltage shutdown threshold
(13)
VPWR power-on reset (POR) Voltage
VDD power-on reset (POR) voltage
Threshold(13)
threshold(13)
VDD supply failure voltage threshold (assumed VPWR > VPWR(UV))
Notes
11.
In extended mode, several device functions (channel control, RDS(on) and overtemperature protection) are guaranteed, but compliance with the
specified values in this document is not. Below 6.0 V, the device is only protected from overheating (thermal shutdown). Above VPWR(OV), the
channels can only be turned ON when the overvoltage detection function has been disabled.
12.
Typical value guaranteed per design.
13.
When the device recovers from undervoltage and returns to normal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period (see Autoretry), the device performs normally. When VPWR drops below VPWR(UV), undervoltage is detected see Undervoltage fault (Latchable fault) and
EMC performances.
10XS4200
9
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
parameter
Symbol
Min.
Typ.
Max.
Unit
RDS(ON)25
–
–
–
–
–
–
10
10
10
mΩ
RDS(ON)150
–
–
–
–
–
–
18
18
18
mΩ
ΔRDS(ON)150
-0.8
–
+0.8
mΩ
RSD(ON)150
–
–
18
mΩ
Max. detectable wiring length (2.5 mm²) for severe short-circuit detection
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
• High slew rate selected
• Medium slew rate selected:
• Low slew rate selected:
10XS4200BAFK and 10XS4200BDFK
• High slew rate selected
• Medium slew rate selected
• Low slew rate selected
LSHORT
20
50
100
85
160
280
140
300
600
cm
20
40
75
75
135
250
130
240
430
Overcurrent detection thresholds with CSNS_ratio bit = 0 (CSR0)
I_OCH1_0
I_OCH2_0
I_OCM1_0
I_OCM2_0
I_OCL1_0
I_OCL2_0
I_OCL3_0
55
35
22
13
9.0
6.0
3.0
66
42
26
16
10.8
7.2
3.6
77
49
31
19.5
12.6
8.4
4.2
A
Overcurrent detection thresholds with CSNS_ratio bit = 1(CSR1)
I_OCH1_1
I_OCH2_1
I_OCM1_1
I_OCM2_1
I_OCL1_1
I_OCL2_1
I_OCL3_1
18.3
11.7
7.2
4.4
3.0
2.0
0.96
22
14.0
8.7
5.3
3.6
2.4
1.2
26.5
16.3
10.1
6.2
4.2
2.8
1.44
A
Electrical Characteristics of the Output Stage (HS0 and HS1)
ON-resistance, Drain-to-Source (IHS = 3.0 A, TJ = 25 °C) CSNS_ratio = 0
• VPWR = 8.0 V
• VPWR = 28 V
• VPWR = 36 V
ON-resistance, Drain-to-Source (IHS = 3.0 A,TJ = 150 °C) CSNS_ratio = 0
• VPWR = 8.0 V
• VPWR = 28 V
• VPWR = 36 V
ON-resistance, Drain-to-Source difference from one channel to the other in
parallel mode (IHS = 1.0 A,TJ = 150 °C) CSNS_ratio = X
ON-Resistance, Source-Drain (IHS = -3.0 A, TJ = 150 °C,
VPWR = -24 V)
10XS4200
NXP Semiconductors
10
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
parameter
Symbol
Min.
Typ.
Max.
Unit
–
-40.0
–
–
+16
+5.0
µA
–
-120
-1400
–
–
–
+16
+5.0
+5.0
-620
-440
-330
-495
-360
-280
-380
-280
-230
-770
-520
-390
0
-620
-420
-315
–
-460
-310
-240
1000
VD_GND(CLAMP)
58
–
66
V
VDS(CLAMP)
58
–
66
V
CSR0
CSR1
–
–
1/3000
1/1000
–
–
–
Minimum measurable load current with compensated error (16)
I_LOAD_MIN
–
–
100
mA
CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0)
ICSR_LEAK
-4.0
–
+4.0
µA
I_LOAD_ERR_SYS
–
–
11
-10
–
–
mA
I_LOAD_ERR_RAND
-150
–
150
mA
Electrical Characteristics of the Output Stage (HS0 and HS1) (continued)
Output pin leakage current in sleep state (positive value = outgoing)
10XS4200FK and 10XS4200CFK
• VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state)
• VHS,OFF = VPWR, device in sleep state (VPWR = 24 V)
10XS4200BFK and 10XS4200BAFK, 10XS4200DFK and 10XS4200BDFK
• VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state)
• VHS,OFF = VPWR, device in sleep state (VPWR = 24 V)
• VHS,OFF = VPWR, device in sleep state (VPWR = 36 V)
IOUT_LEAK
Output biasing current in off-state (positive value = outgoing)
10XS4200BFK and 10XS4200DFK
with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
• Fast slew rate selected
• Medium slew rate selected
• Slow slew rate selected
10XS4200BAFK and 10XS4200BDFK
with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
IOUT_OFF
• Fast slew rate selected
• Medium slew rate selected
• Slow slew rate selected
With OL_OFF disabled and ECU ground disconnected (VPWR = 32 V) for
10XS4200B and 10XS4200BA, 10XS4200D and 10XS4200BD
Switch turn-on threshold for supply overvoltage (VPWR -GND)
Switch turn-on threshold for Drain-Source overvoltage (measured at
IOUT = 500 mA
Current sensing ratio (14)
• CSNS_ratio bit = 0 (high current mode)
• CSNS_ratio bit = 1 (low current mode)
Systematic offset error (see Current sense errors)
• 10XS4200FK and 10XS4200CFK
• 10XS4200FK and 10XS4200CFK, 10XS4200BFK and 10XS4200BAFK,
10XS4200DFK and 10XS4200BDFK
Random offset error
µA
Notes:
14.
Current Sense Ratio CSRx = ICSNS / IHS[x]
15.
ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section
Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
16.
See note (15), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further
accuracy improvements can be obtained by performing a 1 or 2 point calibration.
10XS4200
11
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
parameter
Symbol
Min.
Typ.
Max.
-13
-12
-17
-31
–
–
–
–
13
12
17
31
-10
-9.0
-12
-19
–
–
–
–
10
9.0
12
19
-10
-9.0
-12
-22
–
–
–
–
10
9.0
12
22
-10
-10
-10
-10
–
–
–
–
10
10
10
10
-9.0
-8.0
-8.0
-9.0
–
–
–
–
9.0
8.0
8.0
9.0
-9.0
-8.0
-8.0
-9.0
–
–
–
–
9.0
8.0
8.0
9.0
Unit
Electrical Characteristics of the Output Stage (HS0 and HS1) (continued)
ESR0 Output Current Sensing Error (%, uncompensated(17) at output current
level (Sense ratio CSR0 selected):
TJ=-40 °C
• 6.0 A
• 3.0 A
• 1.5 A
• 0.75 A
TJ=125 °C
• 6.0 A
• 3.0 A
• 1.5 A
• 0.75 A
TJ=25 to 125 °C
• 6.0 A
• 3.0 A
• 1.5 A
• 0.75 A
ESR0 Output Current Sensing Error (% after offset compensation(18) at output
current level (Sense ratio CSR0 selected):
TJ=-40 °C
• 6.0 A
• 3.0 A
• 1.5 A
• 0.75 A
TJ=125 °C
• 6.0 A
• 3.0 A
• 1.5 A
• 0.75 A
TJ=25 to 125 °C
• 6.0 A
• 3.0 A
• 1.5 A
• 0.75 A
ESR0_ERR
ESR0_ERR(Comp)
%
%
Notes:
17.
ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section
Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
18.
See note (17), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further
accuracy improvements can be obtained by performing a 1 or 2 point calibration.
10XS4200
NXP Semiconductors
12
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
parameter
Symbol
Min.
Typ.
Max.
-15
–
15
-12
–
12
-12
–
12
-10
-11
-18
-29
–
–
–
–
10
11
18
29
-8.0
-10
-12
-16
–
–
–
–
8.0
10
12
16
-8.0
-10
-13
-21
–
–
–
–
8.0
10
13
21
-10
-11
–
–
10
11
-8.0
-8.0
–
–
8.0
8.0
-8.0
-8.0
–
–
8.0
8.0
5.5
–
7.5
Unit
Electrical Characteristics of the Output stage (HS0 and HS1) (continued)
ESR1 Output Current Sensing Error (%, uncompensated (19) at output current
level (Sense ratio CSR1 selected):
TJ=-40 °C
• 1.5 A
TJ=125 °C
• 1.5 A
TJ=25 to 125 °C
• 1.5 A
ESR1 Output Current Sensing Error (% (level) after offset
output current level (Sense ratio CSR1 selected):
TJ=-40 °C
• 1.5 A
• 0.5 A
• 0.25 A
• 0.15 A
TJ=125 °C
• 1.5 A
• 0.5 A
• 0.25 A
• 0.15 A
TJ=25 to 125 °C
• 1.5 A
• 0.5 A
• 0.25 A
• 0.15 A
ESR1_ERR
%
compensation(20) at
ESR0 Output Current Sensing Error in parallel mode (%, uncompensated(19)) at
outputs Current level (Sense ratio CSR0 selected):
TJ=-40 °C
• 6.0 A
• 3.0 A
TJ=125 °C
• 6.0 A
• 3.0 A
TJ=25 to 125 °C
• 6.0 A
• 3.0 A
Current Sense Clamping Voltage (condition: R(CSNS) > 10 kOhm)
ESR1_ERR(Comp)
ESR0_ERR_PAR
VCL(CSNS)
%
%
V
Notes:
19.
ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section
Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
20.
See note (19), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further
accuracy improvements can be obtained by performing a 1 or 2 point calibration.
10XS4200
13
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
parameter
Symbol
Min.
Typ.
Max.
Unit
IOLD(OFF)
30
–
100
μA
VOLD(THRES)
4.0
–
5.5
V
120
80
5.0
300
300
7.0
600
600
10
Electrical Characteristics of the Output Stage (HS0 and HS1) (continued)
Openload detection current threshold in OFF state (21)
Openload fault detection voltage threshold
(21)
Openload detection current threshold in ON state (see Openload detection in
ON state (OL_ON)):
• CSNS_ratio bit = 0
10XS4200FK and 10XS4200CFK
10XS4200BFK and 10XS4200BAFK, 10XS4200DFK and
10XS4200BDFK
• CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this
function)
IOLD(ON)
mA
Time period of the periodically activated openload in ON state detection for
CSNS_ratio bit = 1
tOLLED
105
150
195
ms
Output shorted-to-VPWR detection voltage threshold (channel in OFF state)
VOSD(THRES)
VPWR-1.2
VPWR-0.8
VPWR-0.4
V
-35
-38
–
–
-24
-32
ΔVCL
-2.0
–
+2.0
V
VHS_TH
0.45*VPWR
0.5*VPWR
0.55*VPWR
V
TSD
160
175
190
°C
VIH
2.0
–
5.5
V
VIL
-0.3
–
0.8
V
VWAKE
1.0
–
2.2
V
IDWN
5.0
–
20
μA
IUP_CSB
5.0
–
20
μA
IUP_CONF
25
–
100
μA
CSO
–
–
20
pF
RDWN
125
250
500
kΩ
CIN
–
4.0
12
pF
Switch turn-on threshold for negative output voltages (protects against negative
transients) - (measured at IOUT = 100 mA, channel in OFF state)
10XS4200FK and 10XS4200CFK
VCL
10XS4200BFK and 10XS4200BAFK, 10XS4200DFK and
10XS4200BDFK
Switch turn-on threshold for negative output voltages difference from one
channel to the other in parallel mode - (measured at IOUT = 100 mA, channel in
OFF state)
Switching state (On/Off) discrimination thresholds
Shutdown temperature (Power MOSFET junction; 6.0 V < VPWR < 58 V)
V
Electrical Characteristics of the Control Interface Pins
Logic input voltage, High(22)
Logic input voltage, Low
(22)
(23)
Wake-up threshold voltage (IN[0:1] and RSTB)
Internal pull-down current source (on inputs: CLOCK, SCLK and
Internal pull-up current source (input
CSB)(25)
Internal pull-up current source (input CONF[0:1])
(26)
Capacitance of SO, FSB and FSOB pins in Tri-state
Internal pull-down resistance (RSTB and IN[0:1])
Input capacitance
(27)
SI)(24)
Notes:
21.
Minimum required value of openload impedance for detection of openload in OFF state: 200 kΩ.(VOLD(THRES) = VHS @ IOLD(OFF))
22.
23.
24.
High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN[0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR
and can tolerate voltages up to 58 V.
Voltage above which the device wakes up
Pull-down current-value for VSI > 0.8 V and VSCLK > 0.8 V and VCLOCK > 0.8 V.
25.
Pull-up current-value for VCSB < 2.0 V. CSB has an internal pull-up current source connected to VDD.
26.
Pins CONF[0:1] are connected to an internal current source, connected itself to an internal voltage regulator (VREG ~ 3.0 V).
27.
Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing process
but is not tested in production.
10XS4200
NXP Semiconductors
14
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
parameter
Symbol
Min.
Typ.
Max.
VDD-0.4
–
–
Unit
Electrical Characteristics of the Control Interface Pins (continued)
SO high-state output voltage
• (IOH = 1.0 mA)
VSOH
SYNC, SO, FSOB and FSB low-state output voltage
• (IOL = -1.0 mA)
VSOL
–
–
0.4
ISO(LEAK)
- 2.0
0.0
2.0
1.0
50
–
–
10
Infinite
SYNC, SO, CSNS, FSOB and FSB tri-state leakage current:
• (0.0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V or
V(CSNS) = 0 V
CONF[0:1] required values of the external pull-down resistor
• Lighting applications
• DC motor applications
RCONF
V
V
μA
kΩ
10XS4200
15
NXP Semiconductors
4.3
Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min.
Typ.
Max.
Unit
0.164
0.28
0.34
–
–
–
0.65
0.79
0.90
V/μs
0.25
0.45
0.5
–
–
–
1.1
1.4
1.5
0.081
0.14
0.17
–
–
–
0.32
0.395
0.45
0.125
0.225
0.25
–
–
–
0.55
0.7
0.75
0.29
0.55
0.68
–
–
–
1.30
1.58
1.80
0.5
0.9
1.0
–
–
–
2.2
2.8
3.0
0.75
1.0
1.2
-0.1
-0.06
0.0
0.0
+0.1
+0.06
-0.14
0.0
+0.14
-0.2
0.0
0.2
Output Voltage Switching Characteristics
Rising and falling edges medium slew rate (SR[1:0] = 00)(28)
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
• VPWR = 16 V
• VPWR = 28 V
SRR_00
SRF_00
• VPWR = 36 V
10XS4200BAFK and 10XS4200BDFK
• VPWR = 16 V
• VPWR = 28 V
• VPWR = 36 V
Rising and falling edges low slew rate (SR[1:0] = 01)(28)
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
• VPWR = 16 V
• VPWR = 28 V
SRR_01
SRF_01
• VPWR = 36 V
10XS4200BAFK and 10XS4200BDFK
• VPWR = 16 V
• VPWR = 28 V
• VPWR = 36 V
Rising and falling edges high slew rate / SR[1:0] = 10)(28)
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
• VPWR = 16 V
• VPWR = 28 V
• VPWR = 36 V
SRR_10
SRF_10
10XS4200BAFK and 10XS4200BDFK
• VPWR = 16 V
• VPWR = 28 V
• VPWR = 36 V
Rising/falling edge slew rate matching (SRR /SRF)
16 V < VPWR < 36 V
Edge slew rate difference from one channel to the other in parallel
• 16 V < VPWR < 36 V
Δ SR
V/μs
V/μs
mode(28)
• SR[1:0] = 00
• SR[1:0] = 01
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
• SR[1:0] = 10
10XS4200BAFK and 10XS4200BDFK
• SR[1:0] = 10
ΔSR
V/μs
10XS4200
NXP Semiconductors
16
Table 5. Dynamic electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min.
Typ.
Max.
32
20
–
–
128
120
59
40
–
–
245
240
18
10
–
–
68
60
-25
0.0
25
-50
-90
0.0
0.0
50
90
-13
0.0
13
Unit
SWITCHING CHARACTERISTICS (continued)
Output turn-on and turn-off delays (medium slew rate: SR[1:0] = 00)
• 16 V < VPWR < 36 V(29)
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
10XS4200BAFK and 10XS4200BDFK
t DLY_00
μs
Output turn-on and turn-off delays (low slew rate / SR[1:0] = 01)
• 16 V < VPWR < 36 V(29)
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
10XS4200BAFK and 10XS4200BDFK
t DLY_01
μs
Output turn-on and turn-off delays (high slew rate / SR[1:0] = 16)
• 16 V < VPWR < 36 V(29)
10XS4200FK and 10XS4200BFK, 10XS4200CFK and 10XS4200DFK
10XS4200BAFK and 10XS4200BDFK
t DLY_10
Turn-on and turn-off delay time matching (t DLY(ON) - t DLY(OFF))
f PWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 00
Δ t RF_00
Turn-on and turn-off delay time matching (t DLY(ON) - t DLY(OFF))
f PWM = 200 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 01
10XS4200FK and 10XS4200BAFK, 10XS4200CFK and 10XS4200BDFK
10XS4200BFK and 10XS4200DFK
Δ t RF_01
Turn-on and turn-off delay time matching (t DLY(ON) - t DLY(OFF))
f PWM = 1.0 kHz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 10
Δ t RF_10
μs
μs
μs
μs
Notes
28.
Rising and falling edge slew rates specified for a 20 to 80% voltage variation on a 10 Ω resistive load (see Figure 4).
29.
Turn-on delay time measured as delay between a rising edge of the channel control signal (IN[0 : 1] = 1 or CSB) and the associated rising edge of
the output voltage up to: VHS[0 : 1] = VPWR / 2 (where RL = 5.0 Ω). Turn-off delay time is measured as time between a falling edge of the channel
control signal (IN[0 : 1] = 0 or CSB pin) and the associated falling edge of the output voltage up to the instant at which: VHS[0 : 1] = VPWR / 2
(RL = 5.0 Ω)
10XS4200
17
NXP Semiconductors
Table 5. Dynamic electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min.
Typ.
Max.
-21
-25
0.0
0.0
21
25
-40
-50
0.0
0.0
40
50
-11
-12
0.0
0.0
11
12
Unit
SWITCHING CHARACTERISTICS (continued)
Delay time difference from one channel to the other in parallel mode(30)
16 V < VPWR < 36 V
SR[1:0] = 00
10XS4200FK and 10XS4200CFK
10XS4200BFK and 10XS4200BAFK, 10XS420DFK and 10XS4200BDFK
SR[1:0] = 01
10XS4200FK and 10XS4200CFK
Δ t(DLY)
10XS4200BFK and 10XS4200BAFK, 10XS420DFK and 10XS4200BDFK
SR[1:0] = 10
10XS4200FK and 10XS4200CFK
10XS4200BFK and 10XS4200BAFK, 10XS420DFK and 10XS4200BDFK
μs
Fault detection delay time(31)
tFAULT
–
5.0
8.0
μs
Output shutdown delay time(32)
tDETECT
–
7.0
12
μs
t CSNSVAL_00
0.0
–
210
μs
0.0
–
200
0.0
–
310
0.0
–
300
0.0
–
175
0.0
–
165
50
50
25
–
–
–
150
160
130
Current sense output settling time for SR[1:0] = 00 (medium slew rate)
10XS4200FK and 10XS4200BFK, 10XS420CFK and 10XS4200DFK
• 16 V < VPWR < 36 V
10XS4200BAFK and 10XS4200BDFK
• 16 V < VPWR < 36 V
Current sense output settling time for SR[1:0] = 01(low slew rate) (33)
10XS4200FK and 10XS4200BFK, 10XS420CFK and 10XS4200DFK
• 16 V < VPWR < 36 V
10XS4200BAFK and 10XS4200BDFK
• 16 V < VPWR < 36 V
Current sense output settling time for SR[1:0] = 10 (high slew rate) (33)
10XS4200FK and 10XS4200BFK, 10XS420CFK and 10XS4200DFK
• 16 V < VPWR < 36 V
10XS4200BAFK and 10XS4200BDFK
• 16 V < VPWR < 36 V
(33)
t CSNSVAL_01
t CSNSVAL_10
μs
μs
SYNC output signal delay for SR[1:0] = 00 (medium SR) (33)
10XS4200FK and 10XS420CFK
10XS4200BFK and 10XS4200DFK
10XS4200BAFK and 10XS4200BDFK
t SYNCVAL_00
μs
Notes:
30.
Rising and Falling edge slew rates specified for a 20 to 80% voltage variation on a 10 Ω resistive load (see Figure 4).
31.
Time required to detect and report the fault to the FSB pin.
32.
Time required to switch off the channel after detection of overtemperature (OT), overcurrent (OC), SC or UV error (time measured between start
of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR
33.
Settling time ( = t CSNSVAL_xx), SYNC output signal delay ( = t SYNCVAL_xx) and Read-out delay ( = t SYNREAD_xx) are defined for a stepped load
current (100 mA< I(LOAD)
