MC13202FCR2

Freescale Semiconductor, Inc. Datasheet: Technical Data Document Number: MC13202 Rev. 2, 04/2015 MC13202 Datasheet with Addendum Rev. 2 of the MC13202 datasheet has two parts: • The addendum to revision 1.5 of the datasheet immediately following this cover page. • Revision 1.5 of the datasheet, following the addendum. The changes described in the addendum have not been implemented in the specified pages. © 2015 Freescale Semiconductor, Inc. All rights reserved. Freescale Semiconductor, Inc. Datasheet Addendum Document Number: MC13202AD Rev. 0, 04/2015 Addendum to Rev. 1.5 of the MC13202 Datasheet This addendum identifies changes to Rev. 1.5 of the MC13202 datasheet. The changes described in this addendum have not been implemented in the specified pages. 1 Case outline drawing change for new QFN-32 package migration Location: Section 10, Page 28 The case outline was changed because of migration from gold wire to copper wire for QFN-32 packages. The case outline details in Section 10 Packaging Information, should be replaced with package document #98ASA00473D case outline details. To view the new case outline details, go to freescale.com and perform a keyword search for the drawing’s document number. If you want the drawing for this package Then use this document number QFN-32 98ASA00473D NOTE For more information about QFN package use, see EB806 Electrical Connection Recommendations for Exposed Pad on QFN and DFN Packages. © 2015 Freescale Semiconductor, Inc. All rights reserved. References to case 1311-03 2 References to case 1311-03 Location: Section 1, Page 1 Section 10, Page 28 Remove the references to case 1311-03. Addendum to MC13201 Technical Data, Rev. 1.3 Freescale Semiconductor, Inc. 3 Freescale Semiconductor Technical Data Document Number: MC13202 Rev. 1.5, 12/2008 MC13202 MC13202 Package Information Plastic Package Case 1311-03 2.4 GHz Low Power Transceiver for the IEEE® 802.15.4 Standard 1 Introduction The MC13202 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13202 contains a complete 802.15.4 physical layer (PHY) modem designed for the IEEE® 802.15.4 Standard which supports peer-to-peer, star, and mesh networking. The MC13202 includes the 802.15.4 PHY/MAC for use with the HCS08 Family of MCUs. The MC13202 can be used with Freescale’s IEEE 802.15.4 MAC and BeeStack, which is Freescale’s ZigBee® compliant protocol stack. Ordering Information Device Device Marking Package MC13202FC 13202 QFN-32 MC13202FCR2 (Tape and Reel) 13202 QFN-32 Contents 1 2 3 4 5 6 7 8 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . 12 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 15 Crystal Oscillator Reference Frequency . . 19 Transceiver RF Configurations and External Connections 22 10Packaging Information . . . . . . . . . . . . . . . . 28 When combined with an appropriate microcontroller (MCU), the MC13202 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBee networking. For Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008. All rights reserved. more detailed information about MC13202 operation, refer to the MC13202 Reference Manual, (MC13202RM). Applications include, but are not limited to, the following: • Residential and commercial automation — Lighting control — Security — Access control — Heating, ventilation, air-conditioning (HVAC) — Automated meter reading (AMR) • Industrial Control — Asset tracking and monitoring — Homeland security — Process management — Environmental monitoring and control — HVAC — Automated meter reading • Health Care — Patient monitoring — Fitness monitoring • Consumer — Human interface devices (keyboard, mice, etc.) — Remote control — Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifiers (PA), onboard RF transmit/receive (T/R) switch for single port use, PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control. 2 Features • • • • • Recommended power supply range: 2.0 to 3.4 V Fully compliant 802.15.4 Standard transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode Operates on one of 16 selectable channels in the 2.4 GHz band -1 to 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical Receive sensitivity of = 15 MHz - 31 30 43 41 53 - dB dB dB dB dB Frequency Error Tolerance - - 200 kHz Symbol Rate Error Tolerance - - 80 ppm Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C) Sensitivity for 1% Packet Error Rate (PER) (+25 °C) Saturation (maximum input level) SENSmax Table 5. Transmitter AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted.) Characteristic Min Typ Max Unit Power Spectral Density (-40 to +85 °C) Absolute limit - -47 - dBm Power Spectral Density (-40 to +85 °C) Relative limit - 47 - -4 -1 2 Nominal Output Power 1 Symbol Pout Maximum Output Power2 Error Vector Magnitude 4 dBm - 20 35 % Output Power Control Range - 30 - dB Over the Air Data Rate - 250 - kbps 2nd Harmonic3 - -48 - dBc 3 - -70 - dBc 3rd Harmonic EVM dBm 1 SPI Register 12 programmed to 0x00BC which sets output power to nominal (-1 dBm typical). SPI Register 12 programmed to 0x00FF which sets output power to maximum. 3 Measured with output power set to nominal (0 dBm) and temperature @ 25 °C 2 MC13202 Technical Data, Rev. 1.5 10 Freescale Semiconductor Table 6. Digital Timing Specifications (VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted. SPI timing parameters are referenced to Figure 8. Symbol Parameter Min Typ Max Unit T0 SPICLK period 125 nS T1 Pulse width, SPICLK low 50 nS T2 Pulse width, SPICLK high 50 nS T3 Delay time, MISO data valid from falling SPICLK 15 nS T4 Setup time, CE low to rising SPICLK 15 nS T5 Delay time, MISO valid from CE low 15 nS T6 Setup time, MOSI valid to rising SPICLK 15 nS T7 Hold time, MOSI valid from rising SPICLK 15 nS RST minimum pulse width low (asserted) 250 nS Figure 6 shows an RF parameter evaluation circuit. VDDA L10 Z4 4.7nH C17 1.0pF GPIO1 PAO_M PAO_P RFIN_P RFIN_M CT_Bias 44 L11 39 38 4.7nH 1 2 5 4 6 10pF IC2 LDB212G4005C-001 36 35 34 3 1 2 C12 10pF L13 OUT2 VDD OUT1 IN GND VCONT 6 C16 5 4 10pF µPG2012TK-E2 Z5 3.3nH MC1320x C18 1.8pF C14 3 1 2 5 4 6 L12 2.2nH C15 1.8pF 2 3 4 5 1 U4 C13 3 J3 SMA_edge_Receptacle_Female 10pF L14 LDB212G4005C-001 3.3nH Figure 6. RF Parametric Evaluation Circuit Table 7. RF Port Impedance Characteristic Symbol Typ Unit Zin 16.1 - j126 16.0 – j123 15.8 – j121 Ω Zin 14.4 – j77.2 14.5 – j74.8 14.6 – j72.5 Ω Zin 18.5 – j148 18.3 – j146 18.2 – j143 Ω RFIN Pins for internal T/R switch configuration, TX mode 2.405 GHz 2.442 GHz 2.480 GHz RFIN Pins for internal or external T/R switch configuration, RX mode 2.405 GHz 2.442 GHz 2.480 GHz PAO Pins for external T/R switch configuration, TX mode 2.405 GHz 2.442 GHz 2.480 GHz MC13202 Technical Data, Rev. 1.5 Freescale Semiconductor 11 6 Functional Description The following sections provide a detailed description of the MC13202 functionality including the operating modes and Serial Peripheral Interface (SPI). 6.1 MC13202 Operational Modes The MC13202 has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 8. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics. Table 8. MC13202 Mode Definitions and Transition Times Mode Off Hibernate Doze Idle Transition Time To or From Idle Definition All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including IRQ 10 - 25 ms to Idle Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is 7 - 20 ms to Idle retained. Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = (300 + 1/CLKO) µs to Idle 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. Crystal Reference Oscillator On with CLKO output available. SPI active. Receive Crystal Reference Oscillator On. Receiver On. 144 µs from Idle Transmit Crystal Reference Oscillator On. Transmitter On. 144 µs from Idle 6.2 Serial Peripheral Interface (SPI) The host microcontroller directs the MC13202, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13202 occurs as multiple 8-bit bursts on the SPI. The SPI signals are: 1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13202. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK. NOTE For Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0. 3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input. 4. Master In/Slave Out (MISO) - The MC13202 presents data to the master on the MISO output. MC13202 Technical Data, Rev. 1.5 12 Freescale Semiconductor A typical interconnection to a microcontroller is shown in Figure 7. MCU MC13202 Shift Register Baud Rate Generator RxD MISO TxD MOSI Sclk SPICLK Chip Enable (CE) Shift Register CE Figure 7. SPI Interface Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory. 6.2.1 SPI Burst Operation The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13202 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure 8. SPI Burst CE 1 2 3 4 5 6 7 8 SPIC L K T4 V alid T6 T5 T2 T1 T3 T0 T7 M ISO M O SI V alid V alid Figure 8. SPI Single Burst Timing Diagram SPI digital timing specifications are shown in Table 6. MC13202 Technical Data, Rev. 1.5 Freescale Semiconductor 13 6.2.2 SPI Transaction Operation Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13202 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to the MC13202 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13202 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. The number of payload bytes sent will always be an even integer. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13202 Reference Manual, (MC13202RM) for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 9. CE C lo c k B u rst S P IC L K M IS O M O SI V a lid V a lid V a lid H eader R e a d d a ta Figure 9. SPI Read Transaction Diagram MC13202 Technical Data, Rev. 1.5 14 Freescale Semiconductor 7 Pin Connections Table 8. Pin Function Description Pin # Pin Name Type Description Functionality 1 RFIN_M RF Input RF input/output negative. When used with internal T/R switch, this is a bi-directional RF port for the internal LNA and PA 2 RFIN_P RF Input RF input/output positive. When used with internal T/R switch, this is a bi-directional RF port for the internal LNA and PA 3 CT_Bias Control voltage Bias voltage/control signal for external When used with internal T/R switch, RF components provides RX ground reference and TX VDDA reference for use with external balun. Can also be used as a control signal for external LNA, PA, or T/R switch. 4 NC 5 PAO_P RF Output /DC Input RF Power Amplifier Output Positive. 6 PAO_M RF Output/DC Input RF Power Amplifier Output Negative. Open drain. Connect to VDDA through a bias network when used with an external balun. Not used when internal T/R switch is used. 7 SM Input 8 GPIO41 Digital Input/ Output General Purpose Input/Output 4. See Footnote 1 9 GPIO31 Digital Input/ Output General Purpose Input/Output 3. See Footnote 1 10 GPIO21 Digital Input/ Output General Purpose Input/Output 2. See Footnote 1 When gpio_alt_en, Register 9, Bit 7 = 1, GPIO2 functions as a “CRC Valid” indicator. 11 GPIO11 Digital Input/ Output General Purpose Input/Output 1. See Footnote 1 When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an “Out of Idle” indicator. 12 RST Digital Input Tie to Ground. Test mode pin. Open drain. Connect to VDDA through a bias network when used with an external balun. Not used when internal T/R switch is used. Must be grounded for normal operation. Active Low Reset. While held low, the IC is in Off Mode and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE Mode, with SPI in default state. MC13202 Technical Data, Rev. 1.5 Freescale Semiconductor 15 Table 8. Pin Function Description (continued) Pin # Pin Name Type Description Functionality 13 RXTXEN2 Digital Input Active High. Low to high transition initiates RX or TX sequence depending on SPI setting. Should be taken high after SPI programming to start RX or TX sequence and should be held high through the sequence. After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode. 14 ATTN2 Digital Input Active Low Attention. Transitions IC See Footnote 2 from either Hibernate or Doze Modes to Idle. 15 CLKO Digital Output Clock output to host MCU. Programmable frequencies of: 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz, 32.786+ kHz (default), and 16.393+ kHz. 16 SPICLK2 Digital Clock Input External clock input for the SPI interface. See Footnote 2 17 MOSI2 Digital Input Master Out/Slave In. Dedicated SPI data input. See Footnote 2 18 MISO3 Digital Output Master In/Slave Out. Dedicated SPI data output. See Footnote 3 19 CE2 Digital Input Active Low Chip Enable. Enables SPI See Footnote 2 transfers. 20 IRQ Digital Output Active Low Interrupt Request. Open drain device. Programmable 40 kΩ internal pull-up. Interrupt can be serviced every 6 µs with 4 kΩ. 21 VDDD Power Output Digital regulated supply bypass. Decouple to ground. 22 VDDINT Power Input Digital interface supply & digital regulator input. Connect to Battery. 2.0 to 3.4 V. Decouple to ground. 23 GPIO51 Digital Input/Output General Purpose Input/Output 5. See Footnote 1 24 GPIO61 Digital Input/Output General Purpose Input/Output 6. See Footnote 1 25 GPIO71 Digital Input/Output General Purpose Input/Output 7. See Footnote 1 26 XTAL1 Input Crystal Reference oscillator input. Connect to 16 MHz crystal and load capacitor. See Footnote 2 MC13202 Technical Data, Rev. 1.5 16 Freescale Semiconductor Table 8. Pin Function Description (continued) Pin # Pin Name Type Description Functionality 27 XTAL2 Input/Output Crystal Reference oscillator output Note: Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13202 Reference Manual for details. Connect to 16 MHz crystal and load capacitor. 28 VDDLO2 Power Input LO2 VDD supply. Connect to VDDA externally. 29 VDDLO1 Power Input LO1 VDD supply. Connect to VDDA externally. 30 VDDVCO Power Output VCO regulated supply bypass. Decouple to ground. 31 VBATT Power Input Analog voltage regulators Input. Connect to Battery. Decouple to ground. 32 VDDA Power Output Analog regulated supply Output. Connect to directly VDDLO1 and VDDLO2 externally and to PAO± through a bias network. Note: Do not use this pin to supply circuitry external to the chip. Decouple to ground. Only active high when CCA, RX, or TX sequences in progress. EP Ground External paddle / flag ground. Connect to ground. 1 The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. 2 During low power modes, input must remain driven by MCU. 3 By default MISO is tri-stated when CE is negated. For low power operation, miso_hiz_en (Bit 11, Register 07) should be set to zero so that MISO is driven low when CE is negated. MC13202 Technical Data, Rev. 1.5 Freescale Semiconductor 17 GPIO7 XTAL1 XTAL2 VDDLO2 VDDLO1 VDDVCO VBATT GPIO6 VDDD EP PAO_P IRQ MC13202 PAO_M CE MISO SM GPIO4 9 10 11 12 13 14 15 SPICLK 8 25 NC CLKO 7 26 VDDINT ATTN 6 27 CT_Bias RXTXEN 5 28 RST 4 29 GPIO5 GPIO1 3 30 RFIN_P GPIO2 2 RFIN_M GPIO3 1 31 VDDA 32 MOSI 24 23 22 21 20 19 18 17 16 Figure 10. Pin Connections (Top View) MC13202 Technical Data, Rev. 1.5 18 Freescale Semiconductor 8 Crystal Oscillator Reference Frequency This section provides application specific information regarding crystal oscillator reference design and recommended crystal usage. 8.1 Crystal Oscillator Design Considerations The 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13202 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal resonant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal resonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - initial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. Whether or not a frequency trim step will be performed in production Freescale requires the use of a 16 MHz crystal with a