Freescale Semiconductor
Technical Data
Document Number: MC17XSF500
Rev. 2.0, 9/2013
Penta 17 mOhm High Side
Switch
17XSF500
The 17XSF500 is the latest achievement in DC motor and lighting
drivers. It belongs to an expanding family to control and diagnose
various types of loads, such as incandescent lamps or light-emitting
diodes (LEDs) with enhanced precision. It combines flexibility through
daisy-chainable SPI 5.0 MHz, extended digital and analog feedbacks,
safety and robustness.
Output edge shaping helps to improve electromagnetic performance.
To avoid shutting off the device upon inrush current, while still being
able to closely track the load current, a dynamic overcurrent threshold
profile is featured. Current of each channel can be sensed with a
programmable sensing ratio. Whenever communication with the
external microcontroller is lost, the device enters a Fail operation mode,
but remains operational, controllable, and protected.
This new generation of high side switch products family facilitates ECU
design thanks to compatible MCU software and PCB foot print for each
device variant.
This family is packaged in a Pb-free power-enhanced SOIC package
with exposed pad which is End of Life Vehicles directive compliant.
This device is powered by SMARTMOS technology.
Features
• Penta 17 m high side switches with high transient current capability
• 16-bit 5.0 MHz SPI control of overcurrent profiles, channel control
including PWM duty cycles, output-ON and -OFF OpenLoad
detections, thermal shutdown and prewarning, and fault reporting
• Output current monitoring with programmable synchronization signal
and supply voltage feedback
• Limp Home mode
• External smart power switch control
• Operating voltage is 7.0 to 18 V with sleep current < 5.0 µA,
extended mode from 6.0 to 28 V
• -16 V reverse polarity and ground disconnect protections
• Compatible PCB foot print and SPI software driver among the family
ENHANCED PENTA HIGH SIDE SWITCH
EK SUFFIX (PB-FREE)
98ASA00368D
32-PIN SOICW-EP
Applications
• Low voltage exterior lighting
• Low voltage industrial lighting
• Low voltage automation systems
• Halogen lamps
• Incandescent bulbs
• Light-emitting diodes (LEDs)
• HID Xenon ballasts
• DC motors
VPWR
VPWR
VPWR VCC
17XSF500
5.0 V
Regulator
GND
VCC
Main
MCU
GND
SO
CSB
SCLK
SI
RSTB
CLK
A/D1
TRG1
PORT
PORT
PORT
PORT
PORT
A/D2
VPWR
VCC
SI
CP
CSB
OUT1
SCLK
SO
OUT2
RSTB
CLK
OUT3
CSNS
SYNCB
OUT4
LIMP
IN1
OUT5
IN2
IN3
IN4
GND OUT6
Solenoid
LED Module
DC Motor
Resistive load
Bulb
OUT
IN VPWR
Smart Power
CSNS
GND
Figure 1. Penta 17 mOhm High Side Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
M
Spare
1
Orderable Parts
This section describes the part numbers available to be purchased along with their differences.
Table 1. Orderable Part Variations
Part Number
MC17XSF500EK
Notes
Temperature
(TA)
(1)
-40 to 125 °C
Package
OUT1
Rds(on)
OUT2
Rds(on)
OUT3
Rds(on)
OUT4
Rds(on)
OUT5
Rds(on)
OUT6
17 m
17 m
17 m
17 m
17 m
Yes
SOIC 32 pins
exposed pad
Notes
1. To Order parts in Tape & Real, add the R2 suffix to the part number.
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://
www.freescale.com and perform a part number search for the following device number: 17XSF500.
MC17XSF500
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table of Contents
2
3
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Relationship Between Ratings and Operating Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 General IC Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1 Self-protected High Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.3 MCU Interface and Device Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5.1 Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5.2 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5.4 Fail Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5.5 Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.6 SPI Interface and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6.2 SPI Input Register and Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6.3 SPI Output Register and Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6.5 Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Functional Block Requirements and Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Self-protected High Side Switches Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.2 Output Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.3 Output Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.4 Output Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.5 Digital Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.6 Analog Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2 Power Supply Functional Block Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2.2 Wake State Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2.3 Supply Voltages Disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3 Communication Interface and Device Control Functional Block Description and Application Information . . . . . . . . . 55
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.2 Fail Mode Input (LIMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.3 MCU Communication Interface Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.4 External Smart Power Control (OUT6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
7
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 Application Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 EMC & EMI Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 EMC/EMI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Fast Transient Pulse Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Robustness Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 PCB Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1 Thermal Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2 R/C Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
59
59
60
60
61
61
61
62
63
64
64
64
65
65
65
69
MC17XSF500
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Internal Block Diagram
VCC
CP
VCC
Power
Supply
Oscillator
UVF
Power-on
Reset
Battery
Clamp
CPF
OTW1
OTW2
Thermal
Prewarning
OTS1
Temperature
Shut-down
SPI
SCLK
SI
SPIF
RSTB
Reverse
Battery
Protection
Fault
Management
OC1
OLON1
OLOFF1
Charge
Pump
Selectable
Slope Control
Selectable Overcurrent Protection
Selectable Openload Detection
Selectable
Current Sensing
LIMP
OUT1
IN1
Output Voltage
Monitoring
OUT1 Channel
OUT1
PWM Module
IN3
OUT2 Channel
Reference
PWM Clock
IN4
Logic
VCC
WAKEB OR
RSTB
Clock Failure
Detection
CLK
VCC
OUT2
OUT3 Channel
OUT3
OUT4
OUT4Channel
Channel
OUT4
OUT5 Channel
OUT5
Power channels
IN2
CLKF
SPI Control
Under-voltage
Detection
OVF
SO
CSB
VPWR
VPWR_PROTECTED
VS
Limp Home Control
VPWR
100 nF
VCC
CSNS
SYNCB
CSNS
5k
Selectable
Delay
VPWR_PROTECTED
Selectable
Analog
Feedback
Smart Power
Switch Drive
A to D Convertion
5k
OUT6
VPWR_PROTECTED
Control die
Temperature
Monitoring
Power
Voltage
Monitoring
GND
Figure 2. Simplified Internal Block Diagram (Penta version)
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
3
Pin Connections
3.1
Pinout Diagram
Transparent Top View
CP
RSTB
CSB
1
32
CLK
2
31
LIMP
3
30
IN4
SCLK
SI
4
29
IN3
5
28
IN2
VCC
SO
6
27
IN1
7
26
CSNS SYNCB
OUT6
8
25
CSNS
GND
9
24
GND
OUT2
OUT2
OUT4
10
23
OUT1
11
22
OUT1
12
21
OUT3
OUT4
OUT4
13
20
OUT3
14
19
OUT3
NC
15
18
OUT5
16
17
OUT5
NC
VPWR
33
Figure 3. 17XSF500 Pinout Diagram
3.2
Pin Definitions
Table 2. 17XSF500 Pin Definitions
Pin Number
Pin Name
Pin Function
Formal Name
Definition
1
CP
Internal
supply
Charge Pump
This pin is the connection for an external capacitor for charge pump use only.
2
RSTB
SPI
Reset
This input pin is used to initialize the device configuration and fault registers,
as well as place the device in a low-current sleep mode. This pin has a
passive internal pull-down.
3
CSB
SPI
Chip Select
This input pin is connected to a chip select output of a master microcontroller
(MCU). When this digital signal is high, SPI signals are ignored. Asserting
this pin low starts a SPI transaction. The transaction is indicated as
completed when this signal returns to a high level. This pin has a passive
internal pull-up to VCC through a diode.
4
SCLK
SPI
Serial Clock
This input pin is connected to the MCU providing the required bit shift clock
for SPI communication. This pin has a passive internal pull-down.
5
SI
SPI
Serial input
This pin is the data input of the SPI communication interface. The data at the
input is sampled on the positive edge of the SCLK. This pin has a passive
internal pull-down.
6
VCC
Power
Supply
MCU Power Supply This pin is a power supply pin is for internal logic, the SPI I/Os, and the OUT6
driver.
MC17XSF500
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 2. 17XSF500 Pin Definitions(continued)
Pin Number
Pin Name
Pin Function
Formal Name
Definition
7
SO
SPI
Serial Output
This output pin is connected to the SPI serial data input pin of the MCU, or to
the SI pin of the next device of a daisy chain of devices. The SPI changes on
the negative edge of SCLK. When CSB is high, this pin is high-impedance.
8
OUT6
Output
9, 24
GND
Ground
Ground
10, 11
OUT2
Output
Channel #2
Protected high side power output pins to the load.
12, 13, 14
OUT4
Output
Channel #4
Protected high side power output pins to the load.
15, 16
NC
N/A
Not Connected
17, 18
OUT5
Output
Channel #5
Protected high side power output pins to the load.
19, 20, 21
OUT3
Output
Channel #3
Protected high side power output pins to the load.
22, 23
OUT1
Output
Channel #1
Protected high side power output pins to the load.
25
CSNS
Feedback
Current Sense
26
CSNS
SYNCB
Feedback
Current Sense
Synchronization
27
IN1
Input
Direct Input #1
This input wakes up the device. This input pin is used to directly control
corresponding channel in Fail mode. During Normal mode, the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down.
28
IN2
Input
Direct Input #2
This input wakes up the device. This input pin is used to directly control
corresponding channel in Fail mode. During Normal mode, the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down
29
IN3
Input
Direct Input #3
This input wakes up the device. This input pin is used to directly control
corresponding channel in Fail mode. During Normal mode, the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down
30
IN4
Input
Direct Input #4
This input wakes up the device. This input pin is used to directly control
corresponding channel in Fail mode. During Normal mode the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down
31
LIMP
Input
Limp Home
The Fail mode can be activated by this digital input. This pin has a passive
internal pull-down.
32
CLK
Input/Output
Device Mode
Feedback
This pin is an input/output pin. It is used to report the device sleep-state
information. It is also used to apply the reference PWM clock which will be
divided by 28 in Normal operating mode. This pin has a passive internal pulldown.
External Solid State This output pin controls an external Smart Power Switch by logic level. This
pin has a passive internal pull-down.
Reference PWM
Clock
33
VPWR
Power
Supply
Supply Power
Supply
These pins are the ground for the logic and analog circuitries of the device.
For ESD and electrical parameter accuracy purpose, the ground pins must
be shorted in the board.
These pins may not be connected.
This pin reports an analog value proportional to the designated OUT[1:5]
output current, or the temperature of the exposed pad, or the supply voltage.
It is used externally to generate a ground referenced voltage for the
microcontroller (MCU). Current recopy and analog voltage feedbacks are
SPI programmable.
This open drain output pin allows synchronizing the MCU A/D conversion.
This pin requires an external pull-up resistor to VCC.
This exposed pad connects to the positive power supply and is the source of
operational power for the device.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
4
General Product Characteristics
4.1
Relationship Between Ratings and Operating Requirements
The analog portion of device is supplied by the voltage applied to the VPWR exposed pad. Thereby the supply of internal circuitry
(logic in case of VCC disconnect, charge pump, gate drive,...) is derived from the VPWR terminal.
Fatal Range
Reverse
protection
Probable
permanent
failure
V
40
V
32
18
7.
0
V
V
Un
de
5.
5
-1
6
V
V
rv
ol
ta
ge
In case of reverse supply:
• the internal supply rail is protected (max. -16 V)
• the output drivers (OUT1… OUT5) are switched on to reduce the power consumption in the drivers, when using
incandescent bulbs
The device’s digital circuitry is powered by the voltage applied to the VCC pin. In case of a VCC disconnection, the logic part is
supplied by the VPWR pin.
The output driver for SPI signals, CLK pin (wake feedback) and OUT6 are supplied by the VCC pin only. This pin shall be
protected externally, in case of a reverse polarity, or in case of high-voltage disturbance.
Degraded
Normal
Degraded
Potential Failure
Operating Range Operating Range Operating Range
- Reduced
- Reduced
Full performance
- Reduced
performance
performance
performance
- Probable failure
- Full protection
- Full protection
in case of shortbut accuracy not
but accuracy not
circuit
guaranteed
guaranteed
- no PMW feature
for UV to 6 V
Fatal Range
Probable
permanent
failure
Fatal Range
40
V
-16
V
Operating Range
Accepted Industry
Standard Practices
Probable
permanent failure
Correct operation
Fatal Range
Probable
permanent failure
Handling Conditions (Power OFF)
Fatal Range
Probable
permanent failure
Not Operating
Range
V
0
V
7.
5.
5
4.
5
V
VC
(2 C P
.0 O
V R
to
4.
0
-0
.
6
V
V)
Figure 4. Ratings vs. Operating Requirements (VPWR Pin)
Degraded Operating
Range
Normal Operating
Range
Degraded Operating
Range
Reduced
performance
Full performance
Reduced
performance
Fatal Range
Probable
permanent failure
Operating Range
Figure 5. Ratings vs. Operating Requirements (VCC Pin)
MC17XSF500
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.2
Maximum Ratings
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Symbol
Description (Rating)
Min.
Max.
Unit
VPWR Voltage Range
-16
40
V
VCC
VCC Logic Supply Voltage
-0.3
7.0
V
VIN
Digital Input Voltage
Notes
ELECTRICAL RATINGS
VPWR
VOUT
• IN1… IN4 and LIMP
-0.3
40
• CLK, SI, SCLK, CSB, and RSTB
-0.3
20
Digital Output Voltage
• SO, CSNS, SYNC, OUT6, CLK
V
(2)
V
(2)
-0.3
20
Negative Digital Input Clamp Current
–
5.0
mA
(3)
IOUT
Power Channel Current
–
5.5
A
(4)
ECL
Power Channel Clamp Energy Capability
mJ
(5)
V
(6)
ICL
VESD
• Initial TJ = 25 °C
–
100
• Initial TJ = 150 °C
–
50
ESD Voltage
• Human Body Model (HBM) - VPWR, Power Channel and GND pins
-8000
+8000
• Human Body Model (HBM) - All other pins
-2000
+2000
• Charge Device Model (CDM) - Corner pins
-750
+750
• Charge Device Model (CDM) - All other pins
-500
+500
Notes
2. Exceeding voltage limits on those pins may cause a malfunction or permanent damage to the device.
3. Maximum current in negative clamping for IN1… IN4, LIMP, RSTB, CLK, SI, SO, SCLK, and CSB pins
4. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
5. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 , VPWR = 14 V). Please refer to Output Clamps section.
6.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device
Model.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
4.3
Thermal Characteristics
Table 4. Thermal Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Symbol
Description (Rating)
Min.
Max.
Unit
Notes
°C
(7)
THERMAL RATINGS
Operating Temperature
TA
• Ambient
-40
+125
TJ
• Junction
-40
+150
-55
+150
°C
–
260
°C
(8) (9)
TSTG
Storage Temperature
TPPRT
Peak Package Reflow Temperature During Reflow
THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
RJB
Junction-to-Board ([1]Soldered to Board)
–
2.5
°C/W
(10)
RJA
Junction-to-Ambient, Natural Convection, Four-layer Board (2s2p)
–
19.4
°C/W
(11) (12)
RJC
Junction-to-Case (Case top surface)
–
14.2
°C/W
(13)
Notes
7. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not
exceed 125C.
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
10. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
11. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
12. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
13. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
4.4
Operating Conditions
This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.
Table 5. Operating Conditions
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Symbol
Ratings
Min
Max
Unit
7.0
18
V
• Jump Start
–
28
• Load dump
–
40
Reverse Supply
-16
–
V
Functional operating supply voltage - Device is fully
functional. All features are operating.
4.5
5.5
V
Functional operating supply voltage - Device is fully
functional. All features are operating.
VPWR
VCC
Over voltage range
Notes
V
MC17XSF500
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.5
Supply Currents
This section describes the current consumption characteristics of the device.
Table 6. Supply Currents
Characteristics noted under conditions 4.5 V VCC 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Ratings
Min
Typ.
Max
Unit
Notes
µA
(14) (15)
(15)
VPWR CURRENT CONSUMPTIONS
IQVPWR
IVPWR
Sleep mode measured at VPWR = 12 V
• TA = 25 °C
–
1.2
5.0
• TA = 125 °C
–
10
30
–
7.0
8.0
mA
Sleep mode measured at VCC = 5.5V
–
0.05
5.0
µA
Operating mode measured at VPWR = 5.5 V (SPI frequency
5.0 MHz)
–
2.8
4.0
Operating mode measured at VPWR = 18 V
VCC CURRENT CONSUMPTIONS
IQVCC
IVCC
mA
Notes
14. With the OUT1… OUT5 power channels grounded
15. With the OUT1… OUT5 power channels opened
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
5
General IC Functional Description and Application
Information
5.1
Introduction
The 17XSF500 is an evolution of the successful Gen3 by providing improved features of a complete family of devices using
Freescale's latest and unique technologies for the controller and the power stages.
It consists of a scalable family of devices compatible, in terms of software driver and package footprint. It allows diagnosing the
light-emitting diodes (LEDs) with an enhanced current sense precision with synchronization pin, as well as driving high power
motors with a perfect control of its current consumption. It combines flexibility through daisy chainable SPI 5.0 MHz, extended
digital and analog feedbacks, safety, and robustness. It integrates an enhanced PWM module with an 8-bit duty cycle capability
and PWM frequency prescaler, per power channel.
5.2
Features
The main attributes of 17XSF500 are:
• Penta high side switches with overload, overtemperature and undervoltage protection
• control output for one external smart power switch
• 16 Bit SPI communication interface with daisy chain capability
• integrated Fail mode (ASIL B compliant functional safety behavior)
• dedicated control inputs for use in Fail mode
• analog feedback pin with SPI programmable multiplexer and sync signal
• channel diagnosis by SPI communication
• advanced current sense mode for LED usage
• synchronous PWM module with external clock, prescaler and multi-phase feature
• excellent EMC behavior
• power net and reverse polarity protection
• ultra low power mode
• scalable and flexible family concept
• board layout compatible SOIC32 package with exposed pad
MC17XSF500
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
5.3
Block Diagram
The choice of multi-die technology in SOIC exposed pad package including low cost vertical trench FET power die associated
with Smart Power control die lead to an optimized solution.
Gen4 - Functional Block Diagram
Power Supply
MCU Interface & Device Control
SPI Interface
Parallel Control Inputs
MCU
Interface
Self-protected
High Side
Switches
OUT[x]
PWM Controller
Supply
MCU Interface & Output Control
Self-protected High Side Switches
Figure 6. Functional Block Diagram
5.3.1
Self-protected High Side Switches
OUT1… OUT5 are the output pins of the power switches. The power channels are protected against various kinds of shortcircuits and have active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic
functions are available.
5.3.2
Power Supply
The device operates with supply voltages from 5.5 to 40 V (VPWR), but is full spec. compliant only between 7.0 and 18 V. The
VPWR pin supplies power to the internal regulator, analog, and logic circuit blocks. The VCC pin (5.0 V typ.) supplies the output
register of the Serial Peripheral Interface (SPI). Consequently, the SPI registers cannot be read without presence of VCC. The
employed IC architecture guarantees a low quiescent current in Sleep mode.
5.3.3
MCU Interface and Device Control
In Normal mode the power output channels are controlled by the embedded PWM module, which is configured by the SPI register
settings. For bidirectional SPI communication, VCC has to be in the authorized range. Failure diagnostics and configuration are
also performed through the SPI port. The reported failure types are: open-load, short-circuit to supply, severe short-circuit to
ground, overcurrent, overtemperature, clock-fail, and under and overvoltage.
The device allows driving loads at different frequencies up to 400 Hz.
5.4
Functional Description
The device has four fundamental operating modes: Sleep, Normal, Fail, and Power off. It possesses multiple high side switches
(power channels) each of which can be controlled independently:
• in Normal mode by SPI interface. For bidirectional SPI communication, a second supply voltage (VCC) is required.
• in Fail mode by the corresponding the direct inputs IN1… IN4. The OUT5 for the Penta version and the OUT6
are off in this mode.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
5.5
Modes of Operation
The operating modes are based on the signals:
• wake = (IN1_ON) OR (IN2_ON) OR (IN3_ON) OR (IN4_ON) OR (RST\). More details in Logic I/O Plausibility
Check section.
• fail = (SPI_fail) OR (LIMP). More details in Loss of Communication Interface section.
Sleep
wake = [0]
wake = [0]
wake = [1]
(VPWR < VPWRPOR) and
(VCC < VCCPOR)
(VPWR < VPWRPOR) and
(VCC < VCCPOR)
Fail
(VPWR > VPWRPOR) or
(VCC > VCCPOR)
Power
off
(VPWR < VPWRPOR) and
(VCC < VCCPOR)
fail = [0] and valid watchdog toggle
Normal
fail = [1]
Figure 7. General IC Operating Modes
5.5.1
Power Off Mode
The power off mode is applied when VPWR and VCC are below the power on reset threshold (VPWR POR, VCC POR).
In power off, no functionality is available but the device is protected by the clamping circuits. Refer to the Supply Voltages
Disconnection section.
5.5.2
Sleep Mode
The sleep mode is used to provide ultra low current consumption. During sleep mode:
• the component is inactive and all outputs are disabled
• the outputs are protected by the clamping circuits
• the pull-up / pull-down resistors are present
The Sleep mode is the default mode of the device after applying the supply voltages (VPWR or VCC) prior to any wake-up condition
(wake = [0]).
The wake-up from Sleep mode is provided by the wake signal.
MC17XSF500
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
5.5.3
Normal Mode
The Normal mode is the regular operating mode of the device. The device is in Normal mode, when the device is in Wake state
(wake = [1]) and no fail condition (fail = [0]) is detected.
During Normal mode:
• the power outputs are under control of the SPI
• the power outputs are controlled by the programmable PWM module
• the power outputs are protected by the overload protection circuit
• the control of the power outputs by SPI programming
• the digital diagnostic feature transfers status of the smart switch via the SPI
• the analog feedback output (CSNS and CSNS SYNC) can be controlled by the SPI
The channel control (CHx) can be summarized:
• CH1… 4 controlled by ONx or iINx (if ir is programmed by the SPI)
• CH5… 6 controlled by ONx
• Rising CHx by definition means starting overcurrent window for OUT1… 5.
5.5.4
Fail Mode
The device enters the Fail mode, when
• the LIMP input pin is high (logic [1])
• or a SPI failure is detected
During Fail mode (wake = [1] & fail = [1]):
• the OUT1… OUT4 outputs are directly controlled by the corresponding control inputs (IN1… IN4)
• the OUT5… OUT6 are turned off
• the PWM module is not available
• while no SPI control is feasible, the SPI diagnosis is functional (depending on the fail mode condition):
•
the SO shall report the content of SO register defined by SOA0… 3 bits
•
the outputs are fully protected in case of an overload, overtemperature and undervoltage
•
no analog feedback is available
•
the max. output overcurrent profile is activated (OCLO and window times)
•
in case of an overload condition or undervoltage, the auto-restart feature controls the OUT1… OUT4 outputs
•
in case of an overtemperature condition or OCHI1 detection or severe short-circuit detection, the
corresponding output is latched OFF until a new wake-up event.
The channel control (CHx) can be summarized:
• CH1… 4 controlled by iINx, while the overcurrent windows are controlled by IN_ONx
• CH5… 6 are off
5.5.5
Mode Transitions
After a wake-up:
• a power on reset is applied and all SPI SI and SO registers are cleared (logic[0])
• the faults are blanked during tBLANKING
The device enters in Normal mode after start-up if following sequence is provided:
• VPWR and VCC power supplies must be above their undervoltage thresholds (Sleep mode)
• generate wake-up event (wake=1) setting RSTB from 0 to 1
The device initialization will be completed after 50 µsec (typ). During this time, the device is robust, in case of VPWR interrupts
higher than 150 nsec.
The transition from “Normal mode” to “Fail mode” is executed immediately when a fail condition is detected.
During the transition, the SPI SI settings are cleared and the SPI SO registers are not cleared.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
When the fail mode condition was a:
• LIMP input, WD toggle timeout, WD toggle sequence or a SPI modulo 16 error, the SPI diagnosis is available
during Fail mode
• SI / SO stuck to static level, the SPI diagnosis is not available during Fail mode
The transition from “Fail mode” to “Normal mode” is enabled, when:
• the fail condition is removed and
• two SPI commands are sent within a valid watchdog cycle (first WD = [0] and then WD = [1])
During this transition
• all SPI SI and SO registers are cleared (logic[0])
• the DSF (device status flag) in the registers #1… #7 and the RCF (Register Clearer flag) in the device status
register #1 are set (logic[1])
To delatch the RCF diagnosis, a read command of the quick status register #1 must be performed.
5.6
SPI Interface and Configurations
5.6.1
Introduction
The SPI is used to
• control the device in case of Normal mode
• provide diagnostics in case of Normal and Fail mode
The SPI is a 16-Bit full-duplex synchronous data transfer interface with daisy chain capability.
The interface consists of 4 I/O lines with 5.0 V CMOS logic levels and termination resistors:
• The SCLK pin clocks the internal shift registers of the device
• The SI pin accepts data into the input shift register on the rising edge of the SCLK signal
• The SO pin changes its state on the rising edge of SCLK and reads out on the falling edge
• The CSB enables the SPI interface
•
with the leading edge of CSB the registers are loaded
• while CSB is logic [0] SI/SO data are shifted
• with the trailing edge of the CSB signal, SPI data is latched into the internal registers
• when CSB is logic [1], the signals at the SCLK and SI pins are ignored and SO is high-impedance
When the RSTB input is
• low (logic [0]), the SPI and the fault registers are reset. The Wake state then depends on the status of the input
pins (IN_ON1… IN_ON4)
• high (logic[1]), the device is in Wake status and the SPI is enabled
The functionality of the SPI is checked by a plausibility check. In case of a SPI failure, the device enters the Fail mode.
5.6.2
SPI Input Register and Bit Descriptions
The first nibble of the 16 bit data word (D15… D12) serves as address bits.
Register
name
SI data
SI address
#
D1 5
D 14
D13
4 Bi t ad ress
D12
D11
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
11 Bi t d ata
11 bits (D10… D1) are used as data bits.
The D11 bit is the WD toggle bit. This bit has to be toggled with each write command.
When the toggling of the bit is not executed within the WD timeout, a SPI fail is detected.
All register values are logic [0] after a reset. The predefined value is off / inactive, unless otherwise noted.
MC17XSF500
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
Register
SI data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Initia lisa tion 1
0
0
0
0
0
WD
WD S E L
S Y NC
E N1
S YNC
E N0
MUX2
M UX1
MUX0
initia lisa tion 2
1
0
0
0
1
WD
OCHI
T HERM AL
OCHI
TRANSIENT
O CHI
OD5
OCHI
OD4
S OA
MODE
O CHI
OD3
C H1 c ontr ol
2
0
0
1
0
WD
P H11
P H01
ON1
PW M71
P WM 61
PW M51
C H2 c ontr ol
3
0
0
1
1
WD
P H12
P H02
ON2
PW M72
P WM 62
PW M52
C H3 c ontr ol
4
0
1
0
0
WD
P H13
P H03
ON3
PW M73
P WM 63
C H4 c ontr ol
5
0
1
0
1
WD
P H14
P H04
ON4
PW M74
C H5 c ontr ol
6
0
1
1
0
WD
P H15
P H05
ON5
PW M75
1
1
1
WD
P H16
P H06
ON6
D3
D2
D1
D0
S OA 3
S OA 2
S OA1
S OA 0
OCHI
OD2
OCHI
O D1
P WM
s y nc
O TW
SE L
P WM 41
P W M31
P WM 21
P WM 11
PW M01
P WM 42
P W M32
P WM 22
P WM 12
PW M02
PW M53
P WM 43
P W M33
P WM 23
P WM 13
PW M03
P WM 64
PW M54
P WM 44
P W M34
P WM 24
P WM 14
PW M04
P WM 65
PW M55
P WM 45
P W M35
P WM 25
P WM 15
PW M05
PW M76
P WM 66
PW M56
P WM 46
P W M36
P WM 26
P WM 16
PW M06
NO HID1 NO HID0
D4
7
0
out put
contr ol
8
1
0
0
0
WD
P S F5
P SF 4
P S F3
PS F2
P S F1
Global P WM
contr ol
9 -1
1
0
0
1
WD
0
X
X
X
X
9 -2
1
0
0
1
WD
1
X
X
GP W M7
10-1
1
0
1
0
WD
0
OCLO5
OCLO4
OCLO 3
OCLO2
O CLO1
NO
O CHI4
NO
OCHI 3
NO
OCHI2
C H6 c ontr ol
ov er curr ent
contr ol
SI address
#
ON6
ON5
ON4
O N3
ON2
ON1
G PW M
GP WM
GP W M
GP WM
GP WM
GPW M
EN5
E N4
E N3
E N2
E N1
E N6
GP WM 6 GP W M5
GP WM 4 GP WM 3 G PW M2
GP WM 1 GP W M0
NO
OCHI 1
A CM
EN5
S HO RT
OCHI5
A CM
E N4
S HORT
OCHI4
ACM
E N3
SHORT
OCHI3
A CM
E N2
S HORT
O CHI2
A CM
E N1
SHORT
OCHI 1
10-2
1
0
1
0
WD
1
NO
OCHI5
input e na ble
11
1
0
1
1
WD
0
X
X
INEN14
INE N04
I NE N13
INE N03
I NE N12
INEN02
INE N11
INEN01
pre sca le r
se ttings
12-1
1
1
0
0
WD
0
P RS15
PRS 05
P RS 14
P RS 04
P RS 13
P RS 03
PRS 12
P RS02
PRS 11
P RS 01
12-2
1
1
0
0
WD
1
X
X
X
X
X
X
X
X
PRS 16
P RS 06
OL contr ol
13-1
1
1
0
1
WD
0
O LO N
OLON
OLON
OLON
OLON
OLOFF
OLO FF
OLOFF
OLOF F
OLOFF
DGL5
DG L4
DGL3
DGL2
OLLE D control
13-2
1
1
0
1
WD
1
res
res
res
res
DGL1
OLLE D
TRI G
EN5
OLLE D
E N5
E N4
OLLED
E N4
E N3
OLLE D
E N3
E N2
OLLED
E N2
E N1
OLLE D
EN1
incr eme nt /
de rc re me nt
te stmode
14
1
1
1
0
WD
INCR
SG N
INCR15
INCR05
INCR14
INCR04
I NCR13
INCR03
I NCR12
INCR02
INCR11
INCR01
15
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
WD #0 ~# 14 = wa tch dog tog gle bi t
SO A0 ~ S OA3
S OA MO DE
M UX0 ~ M UX 2
S Y NC E N0~ S Y NC EN1
#0
SYNC
EN1
0
SYN C Sync sta tus
EN0
0
sy nc off
#0
#0
= a ddre ss of nex t SO data word
= s ing le read a ddre ss of nex t SO data wo rd
#0
#0
= C SN S m ultip lexe r s etti ng
= S YNC d ela y setti ng
0
1
1
0
va lid
trig0
= wa tch dog tim eout sel ect
= o ver temp erature warn ing thre sho ld sel ection
= r eset clo ck mo dule
= OC H I windo w on l oad de man d
= H ID outpu ts s elec ti on
= OC H I1 le vel de pen din g o n con tro l die temp erature
= OC H I1 le vel ad jus te d durin g OFF to ON tra nsitio n
= P WM val ue (8Bi t)
= p has e con tro l
= c han nel on /o ff inc l. OC HI c ontrol
= p uls e skip pin g fea tu re fo r p ower outpu t ch anne ls
= g lob al PWM en abl e
= g lob al PWM va lue (8 Bit)
= a dva nce d curre nt s ense m ode e nab le
= OC LO lev el co ntr ol
= u se sh ort OC HI wi ndo w time
= s ta rt with OCLO thres hol d
= i npu t en able c ontrol
= p re sca ler se tting
= OL l oad in o ff state enab le
= OL ON degl itch ti me
= OL L ED mo de en able
= trig ger for OLLED detetcio n in 100 % d.c.
= P WM inc reme nt / dec reme nt si gn
= P WM inc reme nt / dec reme nt se ttin g
1
1
trig1 /2
#0
#1
#1
OCHI ODx
#1
#1
NO HIDx
#1
OCHI THE RM AL
OCHI T RA NS IE NT
#1
PWM 0x ~ PWM 7x #2~#7
PH0x ~ P H1x #2~#7
ONx #2~#8
#8
PS Fx
# 9-1
GP WM ENx
GP WM 1 ~ G PWM 7
# 9-2
ACM ENx #10 -1
OCLOx #10 -1
S HORT OCHIx #10 -2
NO OCHIx #10 -2
INE N0x ~ INE N1x
#1 1
P RS 0x ~ PRS1x
#1 2
OLOF F ENx #13 -1
OLO N DGLx #13 -1
OLL ED ENx #13 -2
OLL ED TRIG #13 -2
I NCR S GN
#1 4
INCR0x ~ INCR1x
#1 4
WD S E L
OTW S E L
PW M S Y NC
#0
MU X2
0
0
0
0
1
1
1
1
MU X1
0
0
1
1
0
0
1
1
MU X0
0
1
0
1
0
1
0
1
CSN S
off
OUT1 cur rent
OUT2 cur rent
OUT3 cur rent
OUT4 cur rent
OUT5 cur rent
VPWRmmonitor
VBAT
oni to r
con tro l die temp erature
#1
#2~#7
#11
#12
#14
#14
N O HID 1 NO HID0D Selection
0
0
av aila ble for all c han nels
0
1
av aila ble for cha nne l 3 only
1
0
av aila ble for cha nne ls 3 and 4 o nly
1
1
un ava ilab le fo r a ll ch anne ls
PH 1x PH 0x P ha se
0
0
0°
0
1
90°
1
0
18 0°
1
1
27 0°
IN x=0
INx=1
GPWM
ON x INEN 1x INE N0x
E Nx
OU Tx P WM x OU Tx PWMx
0
x
x
x
OFF
x
OFF
x
indiv idual
indiv idual
0
ON
ON
0
0
gl
obal
global
1
ON
ON
indiv idual
0
OFF indiv idual
ON
0
1
gl obal
global
1
OFF
ON
1
indiv idual
0
OFF indiv idual
ON
1
0
gl obal
global
1
OFF
ON
indiv idual
global
0
ON
ON
1
1
gl obal
indiv idual
1
ON
ON
P RS 1x PRS 0x PR S divider
0
0
/4
2 5Hz .... 10 0H z
0
1
/2
5 0Hz .... 20 0H z
x
1
/1
1 00H z .... 4 00H z
inc rem e nt/decr em ent
INC R SGN
0
de crem ent
1
in crem ent
IN C R 1x INC R 0x inc rem e nt/decr em ent
0
0
no i ncrem ent/dec reme nt
0
1
4 LSB
1
8 LSB
0
1 6 LSB
1
1
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
5.6.3
SPI Output Register and Bit Descriptions
The first nibble of the 16 Bit data word (D12… D15) serves as address bits.
All register values are logic [0] after a reset, except DSF and RCF bits. The predefined value is off / inactive unless otherwise
noted.
#2~#6
QSFx
#1
= qu ick s ta tu s (OC o r OTW or OTS or OLON or OLOFF)
C LKF
#1
= PWM clo ck fail flag
0
0
0
R CF
#1
= reg ister c lea r fla g
0
0
1
OC H I1
C PF
#1
= ch arge pum p fl ag
0
1
0
OC H I2
#1 ~# 7 = op en lo ad flag (wi red or of all OL s ign als )
0
1
1
OC H I3
#1 ~# 7 = ov er loa d fl ag (wire d or of all OC a nd OTS sig nal s)
1
0
0
OC LO
#1 ~# 7 = de vic e status flag ( UVF or OVF or CP F or R CF or CL KF o r TM F)
1
0
1
OC H IOD
1
1
0
S SC
1
1
1
n ot u sed
OLF
OVLF
D SF
FM #1 ~# 8 = fail m ode fla g
OLOFFx #2 ~# 6 = op en lo ad in o ff state status b it
OLON x #2 ~# 6 = op en lo ad in o n state status b it
OTWx #2 ~# 6 = ov er te mp eratur e wa rnin g bit
OTS x #2 ~# 6 = ov er te mp eratur e shu td own bit
#9
OC 2x
O C1x
OC 0x ove r cur re nt st atus
n o ove rcu rrent
D EVID 2 DEV ID1 D EVID 0 dev ic e type
0
0
0
P enta3 /2
0
0
1
P enta0 /5
Qu ad2 /2
iLIM P
#7
= status o f LIM P i npu t after de gli tc her (re ported i n rea l tim e)
0
1
0
SPIF
#7
= SPI fa il flag
0
1
1
Qu ad0 /4
U VF
#7
= un der v oltag e fla g
1
0
0
Trip le1 /2
OVF
#7
= ov er vo lta ge flag
1
0
1
Trip le0 /3
TMF
#7
= testmo de a ctiva ti on flag
1
1
0
re s
OU Tx
#8
VPWR/2
time)
= status
status ooff VB
AT/2 ccomparator
omp arato r (re(reported
po rte d in in
reareal
l ti me)
1
1
1
re s
= status o f INx p in after de glitc her (re ported i n real tim e)
iIN x
#8
TOGGLE
#8
= status o f INx _ON s ign als (IN 1_O N or IN2 _ON o r IN 3_ON or IN 4_ ON)
D EVID0 ~ DE VID 2
#9
= de vic e ty pe
D EVID3 ~ DE VID 4
#9
= de vic e fa mil y
D EVID5 ~ DE VID 7
#9
= de sig n status (in cre men te d nu mbe r)
MC17XSF500
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
5.6.4
Timing Diagrams
RSTB
VIH
10% VCC
VIL
tWRST
tCS
tENBL
CSB
90% VCC
VIH
10% VCC
VIL
tRSI
tWSCLKh
tLEAD
tLAG
VIH
90% VCC
SCLK
10% VCC
tSI(SU)
VIL
tWSCLKl
tFSI
tSI(H)
SI
VIH
90% VCC
10% VCC
Don’t Care
Must be Valid
Don’t Care
VIL
tSOEN
SO
Don’t Care
Must be Valid
tSODIS
Tri-stated
Tri-stated
VIH
VIL
Figure 8. Timing Requirements During SPI Communication
tFSI
tRSI
VOH
90% VCC
50%
SCLK
10% VCC
VOL
VOH
10% VCC
SO
VOL
tRSO
Low to High
tVALID
tFSO
SO
High To Low
VOH
90% VCC
10% VC
VOL
Figure 9. Timing Diagram for Serial Output (SO) Data Communication
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
5.6.5
Electrical Characterization
Table 7. Electrical Characteristics
Characteristics noted under conditions 4.5 V VCC 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
SPI SIGNALS CS\, SI, SO, SCLK, SO
fSPI
SPI Clock Frequency
0.5
–
5.0
MHz
VIH
Logic Input High State Level (SI, SCLK, CSB, RSTB)
3.5
–
–
V
Logic Input High State Level for wake-up (RSTB)
3.75
–
–
V
–
–
0.85
V
VIH(WAKE)
VIL
Logic Input Low State Level (SI, SCLK, CSB, RSTB)
VOH
Logic Output High State Level (SO)
VCC -0.4
–
–
V
VOL
Logic Output Low State Level (SO)
–
–
0.4
V
Logic Input Leakage Current in Inactive State (SI = SCLK = RSTB = [0] and
CSB = [1])
-0.5
–
+0.5
µA
Logic Output Tri-state Leakage Current (SO from 0 V to VCC)
-10
–
+1.0
µA
Logic Input Pull-up / Pull-down Resistor
25
–
100
k
Logic Input Capacitance
–
–
20
pF
7.5
10
12.5
µs
SO Rising and Falling Edges with 80 pF
–
–
20
ns
Required High State Duration of SCLK (Required Setup Time)
80
–
–
ns
Required Low State Duration of SCLK (Required Setup Time)
80
–
–
ns
tCS
Required duration from the Rising to the Falling Edge of CSB (Required
Setup Time)
1.0
–
–
µs
tRST
Required Low State Duration for reset RSTB
1.0
–
–
µs
tLEAD
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)
320
–
–
ns
tLAG
Falling Edge of SCLK to Rising Edge of CSB (Required Setup lag Time)
100
–
–
ns
tSI(SU)
SI to Falling Edge of SCLK (Required Setup Time)
20
–
–
ns
tSI(H)
Falling Edge of SCLK to SI (Required hold Time of the SI signal)
20
–
–
ns
tRSI
SI, CSB, SCLK, Max. Rise Time Allowing Operation at Maximum fSPI
–
20
50
ns
tFSI
SI, CSB, SCLK, Max. Fall Time Allowing Operation at Maximum fSPI
–
20
50
ns
tSO(EN)
Time from Falling Edge of CSB to Reach Low-impedance on SO (access
time)
–
–
60
ns
tSO(DIS)
Time from Rising Edge of CSB to Reach Tri-state on SO
–
–
60
ns
IIN
IOUT
RPULL
CIN
tRST_DGL
tSO
tWCLKh
RSTB deglitch Time
(16)
Notes
16. Parameter is derived from simulations.
SPI SIGNALS CS\, SI, SO, SCLK, SO (Continued)
tWCLKl
MC17XSF500
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
Functional Block Requirements and Behaviors
6.1
Self-protected High Side Switches Description and Application
Information
6.1.1
Features
Up to five power outputs are foreseen to drive light as well as DC motor applications. The outputs are optimized for driving bulbs,
but also HID ballasts, LEDs, and other resistive or low inductive loads.
The smart switches are controlled by use of high sophisticated gate drivers. The gate drivers provide:
• output pulse shaping
• output protections
• active clamps
• output diagnostics
6.1.2
Output Pulse Shaping
The outputs are controlled with a closed loop active pulse shaping in order to provide the best compromise between:
• low switching losses
• low EMC emission performance
• minimum propagation delay time
Depending on the programming of the prescaler setting register #12-1, #12-2 the switching speeds of the outputs are adjusted
to the output frequency range of each channel.
The edge shaping shall be designed according the following table:
divider
PWM freq [Hz]
factor
min
max
PWM period [m s]
m in
max
d.c. range [hex]
min
max
d.c. range [LSB]
min
max
min. on/off duty
cycle time [µs]
4
2
25
50
100
200
10
5
40
20
03
07
FB
F7
4
8
252
248
156
156
1
100
400
2,5
10
07
F7
8
248
78
The edge shaping provides full symmetry for rising and falling transition:
• the slopes for the rising and falling edge are matched to provide best EMC emission performance
• the shaping of the upper edges and the lower edges is matched to provide the best EMC emission performance
• the propagation delay time for the rising edge and the falling edge are matched in order to provide true duty cycle
control of the output duty cycle error < 1 LSB at the max. frequency
• a digital regulation loop is used to minimize the duty cycle error of the output signal
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
Figure 10. Typical Power Output Switching (slow & fast slew rate)
6.1.2.1
SPI Control and Configuration
A Synchronous clock module is integrated for optimized control of the outputs. The PWM frequency and output timing during
Normal mode is generated from the clock input (CLK) by the integrated PWM module. In case of clock fail (very low frequency,
very high frequency), the output duty cycle is 100%.
Each output (OUT1… OUT6) can be controlled by an individual channel control register:
Register
SI addre ss
#
C H x contr ol
2~7
D15
D14
D13
channel address
SI data
D12
D11
D10
D9
D8
WD
PH1x
PH0x
Onx
D7
D6
D5
D4
D3
D2
D1
D0
PWM7x PWM6x PWM5x PWM4x PWM3x PWM2x PWM1x PWM0x
where:
• PH0x… PH1x: phase assignment of the output channel x
• ONx: on/off control including overcurrent window control of the output channel x
• PWM0x… PWM7x: 8-bit PWM value individually for each output channel x
The ONx bits are duplicated in the output control register #8, in order to control the outputs with either the CHx control register
or the output control register.
The PRS1x… PRS0x prescaler settings can be set in the prescaler settings register #12-1 and #12-2.
The following changes of the duty cycle are performed asynchronous (with pos. edge of CSB signal)
• turn on with 100% duty cycle (CHx = ON)
• change of duty cycle value to 100%
• turn off (CHx = OFF)
• phase setting (PH0x… PH1x)
• prescaler setting (PRS1x… PRS0x)
A change in phase setting or prescaler setting during CHx = ON may cause an unwanted long ON-time. Therefore it is
recommended to turn off the output(s) before execution of this change.
MC17XSF500
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
The following changes of the duty cycle are performed synchronous (with the next PWM cycle):
• turn on with less than 100% duty cycle (OUTx = ONx)
• change of duty cycle value to less than 100%
A change of the duty cycle value can be achieved by a change of the:
• PWM0x… PWM7x bits in individual channel control register #2… #7
• GPWM EN1… GPWM EN6 bits (change between individual PWM and global PWM settings) in global PWM
control register #9-1
• incremental/decremental register #14
The synchronisation of the switching phases between different devices is provided by the PWM SYNC bit in the initialization 2
register #1.
On a SPI write into initialization 2 register (#1):
• initialization when the bit D1 (PWM SYNC) is logic[1], all counters of the PWM module are reset with the positive
edge of CSB, i.e. the phase synchronization is performed immediately within one SPI frame. It could help to
synchronize different Gen4 devices in the board.
• when the bit D1 is logic[0], no action is executed
The switching frequency can be adjusted for the corresponding channel as described in the table below:
CLK fr eq. [kHz]
min.
max.
25,6
102,4
hex
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
.
.
.
.
03
02
01
00
prescaler setting
PRS1x
PRS0x
0
0
0
1
1
X
divider
factor
PWM duty cycle
dec
[%]
256
100,00%
255
99,61%
254
99,22%
253
98,83%
252
98,44%
251
98,05%
250
97,66%
249
97,27%
96,88%
248
96,48%
247
96,09%
246
245
95,70%
.
.
.
.
.
.
.
.
4
1,56%
3
1,17%
2
0,78%
1
0,39%
4
2
1
S0
FF
F7
F7
F7
F7
F7
F7
F7
PWM fr eq [Hz]
min
max
25
100
50
200
100
400
slew
rate
slow
slow
fast
pulse skipping frame
S1 S2 S3 S4 S5 S6
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF F7 FF FF
FF F7 FF F7 FF FF
FF F7 FF F7 FF F7
F7 F7 FF F7 FF F7
F7 F7 FF F7 F7 F7
F7 F7 F7 F7 F7 F7
PWM resolution
[Bit]
[steps]
8
256
S7
FF
FF
FF
FF
FF
FF
FF
FF
No PWM feature is provided in case of:
• Fail mode
•
INCR SG N increm ent/decre me nt
0
de creme nt
1
incre ment
clock input signal failure
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
6.1.2.2
Global PWM Control
In addition to the individual PWM register, each channel can be assigned independently to a global PWM register.
The setting is controlled by the GPWM EN bits inside the global PWM control register #9-1. When no control by direct input pin
is enabled and the GPWM EN bit is
• low (logic[0]), the output is assigned to individual PWM (default status)
• high (logic[1]), the output is assigned to global PWM
The PWM value of the global PWM channel is controlled by the global PWM control register #9-2.
ONx
0
1
x
x
0
0
0
1
1
0
1
1
iINx=0
CHx
PWMx
OF F
x
ON
individual
global
ON
OF F
individual
OF F
global
ON
individual
ON
global
GPWM
ENx
x
0
1
0
1
0
1
INEN1x INEN0x
iINx=1
CHx
PWMx
OFF
x
ON
individual
global
ON
ON
individual
ON
global
ON
global
ON
individual
When a channel is assigned to global PWM, the switching phase the prescaler and the pulse skipping are according the
corresponding output channel setting.
6.1.2.3
Incremental PWM Control
To reduce the control overhead during soft start/stop of bulbs or DC motors (e.g. theatre dimming), an incremental PWM control
feature is implemented.
With the incremental PWM control feature, the PWM values of all internal channels OUT1… OUT5 can be incremented or
decremented with one SPI frame.
The incremental PWM feature is not available for
• the global PWM channel
• the external channel OUT6
The control is according the increment/decrement register #14:
• INCR SGN: sign of incremental dimming (valid for all channels)
• INCR 1x, INCR 0x increment/decrement
INCR 1x INCR 0x incre ment/decreme nt
0
0
0
1
n o i ncrement/d ecre me nt
4
1
0
8
1
1
16
This feature limits the duty cycle to the rails (00 resp. FF) in order to avoid any overflow.
6.1.2.4
Pulse Skipping
Due to the output pulse shaping feature and the thereof resulting switching delay time of the smart switches, duty cycles close
to 0% resp. 100% can not be generated by the device. Therefore the pulse skipping feature (PSF) is integrated to interpolate this
output duty cycle range in normal mode.
The pulse skipping provides a fixed duty cycle pattern with 8 states to interpolate the duty cycle values between F7 (Hex) and
FF (Hex). The range between 00 (Hex) and 07 (Hex) is not considered to be provided.
The pulse skipping feature
• is available individually for the power output channels (OUT1… OUT5)
• is not available for the external channel (OUT6).
MC17XSF500
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
The feature is enabled with the PSF bits in the output control register #8.
When the corresponding PSF bit is
• low (logic[0]), the pulse skipping feature is disabled on this channel (default status)
• high (logic[1]), the pulse skipping feature is enabled on this channel
6.1.2.5
Input Control
Up to 4 dedicated control inputs (IN1… IN4) are foreseen to
• wake-up the device
• fully control the corresponding output in case of Fail mode
• control the corresponding output in case of Normal mode
The control during Normal mode is according the INEN0x and INEN1x bits in the input enable register #11.
An input deglitcher is provided at each control input in order to avoid high frequency control of the outputs. The internal signal is
called iINx.
The channel control (CHx) can be summarized:
• Normal mode:
•
CH1… 4 controlled by ONx or INx (if it is programmed by the SPI)
•
CH5… 6 controlled by ONx
•
Rising CHx by definition means starting overcurrent window for OUT1… 5
• Fail mode:
•
CH1… 4 controlled by iINx, while the overcurrent windows are controlled by IN_ONx
•
CH5… 6 are off
The input thresholds are logic level compatible, so the input structure of the pins shall be able to withstand supply voltage level
(max.40 V) without damage. External current limit resistors (i.e. 1.0 k...10 k) can be used to handle reverse current conditions.
The inputs have an integrated pull-down resistor.
6.1.2.6
Electrical Characterization
Table 8. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
–
–
–
–
–
17
–
–
–
–
19
30.9
25.5
31
43.5
–
–
–
–
–
–
–
–
0.5
5.0
5.0
25
–
–
–
–
10
20
Unit
Notes
POWER OUTPUTS OUT1… OUT5
RDS(ON)
ON-Resistance, Drain-to-Source
• TJ = 25 °C, VPWR > 12 V
• TJ = 150 °C, VPWR > 12 V
• TJ = 25 °C, VPWR = 7.0 V
• TJ = 25 °C, VPWR = -12 V
• TJ = 150 °C, VPWR = -12 V
ILEAK SLEEP Sleep Mode Output Leakage Current (Output shorted to GND) per Channel
• TJ = 25 °C, VPWR = 12 V
• TJ = 125 °C, VPWR = 12 V
• TJ = 25 °C, VPWR = 35 V
• TJ = 125 °C, VPWR = 35 V
IOUT
OFF
Operational Output Leakage Current in OFF-State per Channel
• TJ = 25°C, VPWR = 18V
• TJ = 125°C, VPWR = 18V
m
µA
µA
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
Table 8. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
4.0
8.0
8.0
–
–
–
252
248
248
Unit
Notes
POWER OUTPUTS OUT1… OUT5 (Continued)
Output PWM Duty Cycle Range (measured at VOUT = VPWR/2)
• Low Frequency Range (25 to 100Hz)
• Medium Frequency Range (50 to 200Hz)
• High Frequency Range (100 to 400Hz)
PWM
LSB
Rising and Falling Edges Slew Rate at VPWR = 14 V (measured from
VOUT = 2.5 V to VPWR -2.5 V)
• Low Frequency Range
• Medium Frequency Range
• High Frequency Range
0.25
0.25
0.55
0.42
0.42
0.84
0.6
0.6
1.25
SR
Rising and Falling Edges Slew Rate Matching at VPWR = 14 V (SRr / SRf)
0.9
1.0
1.1
tDLY
Turn-on and Turn-off Delay Times at VPWR = 14 V
• Low Frequency Range
• Medium Frequency Range
• High Frequency Range
SR
Turn-on and Turn-off Delay Times Matching at VPWR = 14 V
• Low Frequency Range
• Medium Frequency Range
• High Frequency Range
tDLY
tOUTPUT SD Shutdown Delay Time in case of Fault
V/µs
20
20
10
60
60
30
(17)
(17)
µs
(17)
µs
(17)
100
100
50
-20
-20
-10
0.0
0.0
0.0
20
20
10
0.5
2.5
4.5
µs
25.6
–
102.4
kHz
REFERENCE PWM CLOCK
Clock Input Frequency Range
fCLK
Notes
17. With nominal resistive load 5.0.
6.1.3
Output Protections
The power outputs are protected against fault conditions in Normal and Fail mode in case of:
• overload conditions
• harness short-circuit
•
overcurrent protection against ultra-low resistive short-circuit conditions due to smart over current profile &
severe short-circuit protection
• overtemperature protection including overtemperature warning
• under and overvoltage protections
• charge pump monitoring
• reverse supply protection
In case of a fault condition is detected, the corresponding output is directed to shut down immediately after the deglitch time
tFAULT SD.
The turn off in case of a fault shutdown (OCHI1, OCHI2, OCHI3, OCLO, OTS, UV, CPF, OLOFF) is provided by the FTO feature
(fast turn off).
The FTO:
• does not use edge shaping
• is provided with high slew rate to minimize the output turn-off time tOUTPUT SD, in regards to the detected fault
• uses a latch, which keeps the FTO active during an undervoltage condition (0 < VPWR < VPWR UVF)
MC17XSF500
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
Figure 11. Power Output Switching in Nominal Operation and In Case of Fault
Normal mode
In case of a fault condition during Normal mode:
• the status is reported in the quick status register #1 and the corresponding channel status register #2… #6.
To restart the output
• the channel must be restarted by writing the corresponding ON bit in the channel control register #2… #6 or
output control register #8.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
OLOFF
(Ioutx > I oloff thres) or (t > t olof f)
OUTx = 1
(OLOFF ENx = 1)
(rewrite CHx=1) & (tochi1+ to chi2 < t tochi1 + tochi2)
& (fault x=0)
OCHI3
OUTx = HSONx
(CH x=0) o r (fault x=1)
(CHx=0) or (fault x=1)
(CHx=0) or (fault x=1)
(OCLOx=1) & (OCHI ODx= 1)
(NO OCHIx=1) & (fault x=0)
(NO OCHIx =1) & (fault x=0)
(CH x=0) or (fault x=1 )
OCLO
OUTx = HSONx
[(rewrite CHx=1) & (t>t ochi1+tochi2+tochi3)] or
[(set CHx= 1) & (NO OCHIx=1)]
[(t > tochi1+tochi2+tochi3) & (fault x=0)] or
[(NO OCHIx=1) & (fault x=0)]
Definitions of key logic signals:
remark:
(fault x):= (UV) or (OCHI1x) or (OCHI2x) or (OCHI3x) or (OCLOx) or (OTx) or (SSCx)
(set CHx=1):= [(ONx=0) then (ONx=1)] or [(iINx=0) then (iINx=1)]
(rewrite CHx=1):= (rewrite ONx=1) after (fault x=1)
SSCx:= severe short circuit detection
Figure 12. Output Control Diagram in Normal Mode
MC17XSF500
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
Fail mode
In case of an overcurrent (OCHI2, OCHI3, OCLO) or undervoltage, the restart is controlled by the auto-restart feature
I threshold
I OCHI2
I OCHI3
driver turned off in case of
fault_fail x ( = OC or UV)
event during autorestart
driver turned on again with
OCHI2 after fault_fail x
I OCLO
In case of successful autorestart
(no fault_fail x event)
OCLO remains active
tOCHI2
t
time
AUTORESTART
Figure 13. Auto-restart in Fail Mode
In case of an overtemperature (OTSx), or severe short-circuit (SSCx), or OCHI1 overcurrent, the corresponding output enters a
latch off state until the next wake-up cycle or mode change
(INx_ON=0)
auto
restart
autorestart x=1
OC_fail x=0
OUTx=off
(UV =1)
(UV =1) or
(OCLOx=1)
(UV =1) or
(OCHI3x=1)
(UV= 0) &
(t > t autorestart)
(UV =1) or
(OCHI2x=1)
(t > tochi1+tochi2)
& (autorestart=1)
(INx_ON=1)
off
OCHI1
OUTx=off
autorestart x=0
OUTx=iINx
(t > tochi1)
OCHI2
OUT x=iINx
(t > tochi1+t ochi2)
& (autorestart x=0)
OCHI3
OUTx=iINx
(t >tochi1+
tochi2+ tochi3)
OCLO
OUTx=iINx
(INx_ON=0)
(INx_ON=0)
(INx_ON=0)
(OTSx=1) or
(SSCx=1)
(INx_ON=0)
(OTSx=1) or
(SSC x=1) or
(OCHI1x=1)
Definition of key logic signals:
remark:
iINx:= external Inputs IN1~IN4 after deglitcher
SSCx := s evere short circuit detec tion
(OTSx=1) or
(SSCx=1)
latch
OFF
(OT Sx=1) or
(SSCx=1)
OUTx=off
Figure 14. Output Control Diagram in Fail Mode
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
6.1.3.1
Overcurrent Protections
Each output channel is protected against overload conditions by use of a multilevel overcurrent shutdown.
current
IOCHI1
IOCHI2
Overcurrent Threshold Profile
IOCHI3
IOCLO
Lamp Current
tOCHI1
tOCHI2
tOCHI3
Figure 15. Transient Over Current Profile
The current thresholds and the threshold window times are fixed for each type of power channel.
When the output is in PWM mode, the clock for the OCHI time counters (tOCHI1… tOCHI3) is gated (logic AND) with the referring
output control signal:
• the clock for the tOCHI counter is activated when the output = [1] respectively CHx = 1
• the clock for the tOCHI counter is stopped when the output = [0] respectively CHx= 0
current
IOCHI1
IOCHI2
IOCHI3
IOCLO
time
cumulative
tOCHI1
cumulative
tOCHI2
cumulative
tO CHI3
Figure 16. Transient Overcurrent Profile in PWM Mode
This strategy counts the OCHI time only when the bulb is actually heated up. The window counting is stopped in case of UV, CPF
and OTS.
A severe short-circuit protection (SSC) is implemented in order to limit the power dissipation in Normal and Fail modes, in case
of a severe short-circuit event. This feature is active only for a very short period of time, during OFF-to-ON transition. The load
impedance is monitored during the output turn-on.
MC17XSF500
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
Normal mode
The enabling of the high current window (OCHI1… OCHI3) is dependent on CHx signal.
When no control input pin is enabled, the control of the overcurrent window depends on the ON bits inside channel control
registers #2… #7 or the output control register #8.
When the corresponding CHx signal is
• toggled (turn OFF and then ON), the OCHI window counter is reset and the full OCHI windows are applied
current
IOCHI1
Overcurrent Threshold Profile
IOCHI2
IOCHI3
OCLO fault detection
IOCLO
Channel Current
time
ON bit =0
•
ON bit =1
Figure 17. Resetable Overcurrent Profile
rewritten (logic [1]), the OCHI window time is proceeding without reset of the OCHI counter
current
OCLO fault detection
I OCLO
time
ON bit =1 rewriting
Figure 18. Over Current Level Fixed to OCLO
Fail mode
The enabling of the high current window (OCHI1… OCHI3) is dependent on INx_ON toggle signal.
The enabling of output (OUT1… 5) is dependent on CHx signal.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
6.1.3.1.1
Overcurrent Control Programming
A set of overcurrent control programming functions is implemented to provide a flexible and robust system behavior:
HID Ballast Profile (NO_HID)
A smart overcurrent window control strategy is implemented to turn on a HID ballast, even in case of a long power on reset time.
When the output is in 100% PWM mode (including PWM clock failure in Normal mode and iINx=1 in Fail mode), the clock for the
OCHI2 time counter is divided by 8, when no load current is demanded from the output driver.
•
•
the clock for the tOCHI2 counter is divided by 8 when the OpenLoad signal is high (logic[1]), to accommodate the
HID ballast being in power on reset mode
the clock for the tOCHI2 counter is connected directly to the window time counter when the OpenLoad signal is
low (logic[0]), to accommodate the HID demanding load current from the output
current
IOCHI1
IOCHI2
Overcurrent Threshold Profile
IOCHI3
IOCLO
Channel Current
tOCHI1
8 x t OCHI2
tOCHI3
time
Figure 19. HID Ballast Overcurrent Profile
This feature extends the OCHI2 time depending on the status of the HID ballast and ensures to bypass even a long power on
reset time of HID ballast. Nominal tOCHI2 duration is up to 64 ms (instead of 8.0 ms).
This feature is automatically active at the beginning of smart overcurrent window, except for OCHI On Demand as described
below.
The functionality is controlled by the NO_HID1 and NO_HID0 bits inside the initialization #2 register.
When the NO_HID1 and NO_HID0 bits are respectively
• [0 0]: smart HID feature is available for all channels (default status and during Fail mode)
• [0 1]: smart HID feature is available for channel 3 only
• [1 0]: smart HID feature is available for channels 3 and 4 only
• [1 1]: smart HID feature is not available for any channel
OCHI On Demand (OCHI OD)
In some instances, a lamp might be unpowered when its supply is interrupted by the opening of a switch (as in a door), or by
disconnecting the load (as in a trailer harness). In these cases, the driver should be tolerant of the inrush current that will occur
when the load is reconnected. The OCHI On Demand feature allows such control individually for each channel through the OCHI
ODx bits inside the Initialization #2 register.
MC17XSF500
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
When the OCHI ODx bit is:
• low (logic[0]), the channel operates in its normal, default mode. After end of OCHI window timeout the output is
protected with an OCLO threshold.
• high (logic[1], the channel operates in the OCHI On Demand mode and uses the OCHI2 and OCHI3 windows
and times after an OCLO event.
To reset the OCHI ODx bit (logic[0]) and change the response of the channel, first change the bit in the Initialization #2 register
and then turn the channel off. The OCHI ODx bit is also reset after an overcurrent event at the corresponding output.
The fault detection status is reported in the quick status register #1 and the corresponding channel status registers #2… #6, as
presented in Figure 20.
current
solid line: nominal operation
dotted lines: fault conditions
OCHI2 fault reported
IOCHI2
OCHI3 fault reported
IOCHI3
OCLO fault reported
IOCLO
OCHI OD fault reported
tOCHI2
tOCHI3
time
Figure 20. OCHI On Demand Profile
OCLO Threshold Setting
The static overcurrent threshold can be programmed individually for each output in 2 levels in order to adapt low duty cycle
dimming and a variety of loads.
The CSNS recopy factor and OCLO threshold depend on OCLO and ACM settings.
The OCLO setting is controlled by the OCLOx bits inside the overcurrent control register #10-1.
When the OCLOx bit is
• low (logic[0]), the output is protected with the higher OCLO threshold (default status and during Fail mode)
• high (logic[1]), the lower OCLO threshold is applied
SHORT OCHI
The length of the OCHI windows can be shortened by a factor of 2, to accelerate the availability of the CSNS diagnosis, and to
reduce the potential stress inside the switch during an overload condition.
The setting is controlled individually for each output by the SHORT OCHIx bits inside the overload control register #10-2.
When the SHORT OCHIx bit is
• low (logic[0]), the default OCHI window times are applied (default status and during Fail mode)
• high (logic[1]), the short OCHI window times are applied (50% of the regular OCHI window time)
NO OCHI
The switch on process of an output can be done without an OCHI window, to accelerate the availability of the CSNS diagnosis.
The setting is controlled individually for each channel by the NO OCHIx bits inside the overcurrent control register #10-2.
When the NO OCHIx bit is
• low (logic[0]), the regular OCHI window is applied (default status and during Fail mode)
• high (logic[1]), the turn on of the output is provided without OCHI windows
The NO OCHI bit is applied in real time. The OCHI window is left immediately when the NO OCHI is high (logic[1]).
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
The overcurrent threshold i set to OCLO when:
• the NO OCHIx bit is set to logic [1] while CHx is ON or
• CHx turns ON if NO OCHIx is already set
THERMAL OCHI
To minimize the electro-thermal stress inside the device in case of short-circuit, the OCHI1 level can be automatically adjusted
in regards to the control die temperature.
The functionality is controlled for all channels by the OCHI THERMAL bit inside the initialization 2.
When the OCHI THERMAL bit is:
• low (logic[0]), the output is protected with default OCHI1 level
• high (logic[1]), the output is protected with the OCHI1 level reduced by RTHERMAL OCHI = 15% (typ) when the
control die temperature is above TTHERMAL OCHI = 63 °C (typ)
TRANSIENT OCHI
To minimize the electro-thermal stress inside the device in case of short-circuit, the OCHIx levels can be dynamically evaluated
during the OFF-to-ON output transition.
The functionality is controlled for all channels by the OCHI TRANSIENT bit inside the initialization 2 register.
When the OCHI TRANSIENT bit is:
• low (logic[0]), the output is protected with default OCHIx levels
• high (logic[1]), the output is protected with an OCHIx levels depending on the output voltage (VOUT):
•
OCHIx level reduced by RTRANSIENT OCHI = 50% typ for 0 < VOUT < VOUT DETECT (VPWR / 2 typ),
•
Default OCHIx level for VOUT DETECT < VOUT
If the resistive load is less than VPWR/IOCHI1, the overcurrent threshold will be exceeded before output reaches VPWR / 2 and
output current reaches IOCHI1. The output is then switched off at much lower and safer currents.
When the load has significant series inductance, the output current transition falls behind voltage with LLOAD/RLOAD constant
time. The intermediate overcurrent threshold could not reach and the output current continues to rise up to OCHIx levels.
6.1.3.1.2
Electrical Characterization
Table 9. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
42
40
48
46
54.4
54.4
Unit
Notes
POWER OUTPUTS OUT1… OUT5
IOCHI1
High Overcurrent Level 1
• TJ = -40 °C and 25 °C
• TJ = 150 °C
A
IOCHI2
High Overcurrent Level 2
24.5
28.2
32.2
A
IOCHI3
High Overcurrent Level 3
14.8
17.3
19.5
A
IOCLO
Low Overcurrent
8.8
4.4
10.8
5.3
13.2
6.6
4.4
2.2
5.3
2.6
6.6
3.3
0.45
0.5
0.55
0.835
0.85
0.865
• High Level
• Low Level
IOCLO ACM
A
Low Overcurrent in ACM Mode
• High Level
• Low Level
RTRANSIENT High Overcurrent Ratio 1
A
OCHI
RTHERMAL
High Overcurrent Ratio 2
OCHI
MC17XSF500
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 9. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
50
63
70
°C
• Default Value
1.5
2.0
2.5
• SHORT OCHI option
0.75
1.0
1.25
• Default Value
6.0
8.0
10
• SHORT OCHI option
3.0
4.0
5.0
48
24
64
32
80
40
10
–
–
Notes
POWER OUTPUTS OUT1… OUT5 (Continued)
TTHERMAL
Temperature Threshold for IOCHI1 Level Adjustment
OCHI
tOCHI1
tOCHI2
tOCHI3
High Overcurrent Time 1
High Overcurrent Time 2
• SHORT OCHI option
tFAULT SD
Minimum Severe Short-circuit Detection
ms
Fault Deglitch Time
• OCLO and OCHI OD
m
µs
1.0
1.0
2.0
2.0
3.0
3.0
Fault Auto-restart Time in Fail Mode
48
64
80
ms
Fault Blanking Time after Wake-up
–
50
100
µs
• OCHI1… 3 and SSC
tAUTO-
ms
High Overcurrent Time 3
• Default Value
RSC MIN
ms
(18)
RESTART
tBLANKING
Notes
18. Guaranteed by testmode.
6.1.3.2
Overtemperature Protection
A dedicated temperature sensor is located on each power transistor, to protect the transistors and provide SPI status monitoring.
The protection is based on a two stage strategy.
When the temperature at the sensor exceeds the:
• selectable overtemperature warning threshold (TOTW1, TOTW2), the output stays on and the event is reported in
the SPI
• overtemperature threshold (TOTS), the output is switched off immediately after the deglitch time tFAULT SD and the
event is reported in the SPI after the deglitch time tFAULT SD.
6.1.3.2.1
Overtemperature Warning (OTW)
Receiving a overtemperature warning:
• the output remains in current state
• the status is reported in the quick status register #1 and the corresponding channel status register #2… #6
The OTW threshold can be selected by the OTW SEL bit inside the initialization 2 register #1.
When the bit is
• low (logic[0]) the high overtemperature threshold is enabled (default status)
• high (logic[1]) the low overtemperature threshold is enabled
To delatch the OTW bit (OTWx)
• the temperature has to drop below the corresponding overtemperature warning threshold
• a read command of the corresponding channel status register #2… #6 must be performed
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
6.1.3.2.2
Overtemperature Shutdown (OTS)
During an over temperature shutdown:
• the corresponding output is disabled immediately after the deglitch time tFAULT SD.
• the status is reported after tFAULT SD in the quick status register #1 and the corresponding channel status register
#2… #6.
To restart the output after an overtemperature shutdown event in Normal mode:
•
the overtemperature condition must be removed, and the channel must be restarted with a write command of the
ON bit in the corresponding channel control register #2… #6, or in the output control register #8.
To delatch the diagnosis:
• the overtemperature condition must be removed
• a read command of the corresponding channel status register #2… #6 must be performed
To restart the output after an overtemperature shutdown event in Fail mode
• a mode transition is needed. Refer to the Mode Transitions section.
6.1.3.2.3
Electrical Characterization
Table 10. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
°C
(19)
°C
(19)
POWER OUTPUTS OUT1… OUT5
TOW
Overtemperature Warning
• TOW1 level
• TOW2 level
TOTS
tFAULT SD
Over Temperature Shutdown
100
120
115
135
130
150
155
170
185
2.0
5.0
10
Fault Deglitch Time
• OTS
µs
Notes
19. Guaranteed by test mode.
6.1.3.3
6.1.3.3.1
Undervoltage and Overvoltage Protections
Undervoltage
During an undervoltage condition (VPWRPOR < VPWR < VPWR UVF), all outputs (OUT1… OUT5) are switched off immediately after
deglitch time tFAULT SD.
The undervoltage condition is reported after the deglitch time tFAULT SD
• in the device status flag (DSF) in the registers #1… #7
• in the undervoltage flag (UVF) inside the device status register #7
Normal mode
The reactivation of the outputs is controlled by the microcontroller.
To restart the output the undervoltage condition must be removed and:
• a write command of the ON Bit in the corresponding channel control register #2… #6 or in the output control
register #8 must be performed
To delatch the diagnosis:
• the undervoltage condition must be removed
• a read command of the device status register #7 must be performed
Fail mode
MC17XSF500
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
When the device is in Fail mode, the restart of the outputs is controlled by the auto-restart feature.
6.1.3.3.2
Overvoltage
The device is protected against overvoltage on VPWR.
During:
• jump start condition, the device may be operated, but with respect to the device limits
• load dump condition (VPWR LD MAX = 40 V) the device does not conduct energy to the loads
The overvoltage condition (VPWR > VPWR OVF) is reported in the:
• device status flag (DSF) in the registers #1… #7
• overvoltage flag (OVF) inside the device status register #7
To delatch the diagnosis:
• the overvoltage condition must be removed
• a read command of the device status register #7 must be performed
In case of an overvoltage (VPWR > VPWR HIGH), the device is not “short-circuit“ proof.
6.1.3.3.3
Electrical Characterization
Table 11. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
SUPPLY VPWR
VPWR UVF
Supply undervoltage
5.0
5.25
5.5
V
VPWR UVF
Supply undervoltage Hysteresis
200
350
500
mV
VPWR OVF
Supply Overvoltage
28
30
32
V
VPWR OVF
Supply Overvoltage Hysteresis
0.5
1.0
1.5
V
VPWR LD MAX Supply Load Dump Voltage (2.0 min at 25 °C)
40
–
–
V
32
–
–
V
2.0
3.5
5.5
HYS
HYS
VPWR HIGH
tFAULT SD
Maximum Supply Voltage for Short-circuit Protection
Fault Deglitch Time
• UV and OV
6.1.3.4
µs
Charge Pump Protection
The charge pump voltage is monitored to protect the smart switches in case of:
• power up
• failure of external capacitor
• failure of charge pump circuitry
During power up, when the charge pump voltage has not yet settled to its nominal output voltage range, the outputs cannot be
turned on. Any turn on command during this phase is executed immediately after settling of the charge pump.
When the charge pump voltage is not within its nominal output voltage range:
• the power outputs are disabled immediately after the deglitch time tFAULT SD
• the failure status is reported after tFAULT SD in the device status flag DSF in the registers #1… #7 and the CPF in
the quick status register #1
• Any turn on command during this phase is executed, including the OCHI windows immediately after the charge
pump output voltage has reached its valid range
To delatch the diagnosis:
• the charge pump failure condition must be removed
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
•
6.1.3.4.1
a read command of the quick status register #1 is necessary
Electrical Characterization
Table 12. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Charge Pump Capacitor Range (Ceramic type X7R)
47
–
220
nF
VCP MAX
Maximum Charge Pump Voltage
–
–
16
V
tFAULT SD
Fault Deglitch Time
–
4.0
6.0
Notes
CHARGE PUMP CP
CCP
µs
• CPF
6.1.3.5
Reverse Supply Protection
The device is protected against reverse polarity of the VPWR line.
In reverse polarity condition:
• the output transistors OUT1… 5 are turned ON to prevent the device from thermal overload
• the OUT6 pin is pulled down to GND. An external current limit resistor shall be added in series with OUT6 terminal
• no output protection is available in this condition
6.1.4
Output Clamps
6.1.4.1
Negative Output Clamp
In case of an inductive load (L), the energy is dissipated after the turn-off inside the N-channel MOSFET.
When tCL (=Io x L / VCL) > 1.0 ms, the turn-off waveform can be simplified with a rectangle, as shown in Figure 21.
Output Current
Io
time
Output Voltage
tCL
VV
BAT
PWR
time
time
VV
CL
PWR
Figure 21. Simplified Negative Output Clamp Waveform
The energy dissipated in the N-Channel MOSFET is: ECL = 1/2 x L x Io² x (1+ VPWR / |VCL|).
In the case of tCL < 1.0 ms, please contact the factory for guidance.
MC17XSF500
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.1.4.2
Supply Clamp
The device is protected against dynamic overvoltage on the VPWR line by means of an active gate clamp, which activates the
output transistors to limit the supply voltage (VDCCLAMP).
In case of an overload on an output, the corresponding switch is turned off, which leads to high voltage at VPWR with an inductive
VPWR line. The maximum VPWR voltage is limited at VDCCLAMP by active clamp circuitry through the load.
In case of an OpenLoad condition, the positive transient pulses (acc.automotive specification ISO 7637 / pulse 2 and inductive
supply line) shall be handled by the application. In case of negative transients on the VPWR line (acc. ISO7637-2 / pulse 1), the
energy of the pulses is dissipated inside the load, or shall be drained by an external clamping circuit, during a high ohmic load.
6.1.4.3
Electrical Characterization
Table 13. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
41
–
50
V
-21
–
-18
V
Notes
SUPPLY VPWR
VDCCLAMP
Supply Clamp Voltage
POWER OUTPUTS OUT1… OUT5
VCL
6.1.5
Negative Power Channel Clamp Voltage
Digital Diagnostics
The device offers several modes for load status detection in on state and off state through SPI.
6.1.5.1
OpenLoad Detections
6.1.5.1.1
OpenLoad in ON State
OpenLoad detection during ON state is provided for each power output (OUT1… OUT5) based on the current monitoring circuit.
The detection is activated automatically when the output is in on state.
The detection threshold is dependent on:
• the OLLED EN bits inside the OLLED control register #13-2
The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global OpenLoad flag OLF (registers #1… #7)
• the OLON bit of the corresponding channel status registers #2… #6
To delatch the diagnosis
• the OpenLoad condition must be removed
• a read command of the corresponding channel status register #2… #6 must be performed
When an OpenLoad has been detected, the output remains in on state.
The deglitch time of the OpenLoad in on state can be controlled individually for each output in order to be compliant with different
load types.
The setting is dependent on the OLON DGL bits inside the OpenLoad control register #13-1:
• low (logic[0]) the deglitch time is tOLON DGL = 64 µs typ (bulb mode)
• high (logic[1]) the deglitch time is tOLON DGL = 2.0 ms typ (converter mode)
The deglitching filter is reset whenever output falls low and is only active when the output is high.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
6.1.5.1.2
OpenLoad in ON State for LED
For detection of small load currents (e.g. LED) in on state of the switch a special low current detection mode is implemented by
using the OLLED EN bit.
The detection principle is based on a digital decision during regular switch off of the output.
Thereby a current source (IOLLED) is switched on and the falling edge of the output voltage is evaluated by a comparator at
VPWR - 0.75 V (typ).
.
VPWR
VPWR
Figure 22. OpenLoad in ON State Diagram for LED
The OLLED fault is reported when the output voltage is above VPWR - 0.75 V after 2.0 ms off-time, or at each turn-on command
if the off-time < 2.0 ms.
The detection mode is enabled individually for each channel with the OLLED EN bits inside the LED control register #13-2.
When the corresponding OLLED EN bit is
• low (logic[0]), the standard OpenLoad in on state (OLON) is enabled
• high (logic[1]), the OLLED detection is enabled.
The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global OpenLoad flag OLF (register #1… #7)
• the OLON bit of the corresponding channel status register #2… #6
When an OpenLoad has been detected, the output remains in on state.
When output is in PWM operation:
• the detection is performed at the end of the on time of each PWM cycle
• the detection is active during the off time of the PWM signal, up to 2.0 ms max.
The current source (IOLLED) is disabled after “no OLLED” detection or after 2.0 ms.
MC17XSF500
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
hson_1
128*DCLOCK (prescaler = ‘0’)
En_OLLed_1
VPWR
-0.75
VBAT-0.75
OUT_1
OUT_high
check
Analog Comparator output
1 : olled detected
TimeOut = 2.0 msec
0 : no olled detected
Figure 23. OpenLoad in ON State for LED in PWM Operation (OFF time > 2.0 ms)
hson_1
128*DCLOCK (prescaler=‘0’)
En_OLLed_1
VPWR
-0.75
V -0.75
OUT_1
OUT_high
Analog Comparator output
BAT
check
1 : olled detected
0 : no olled detected
TimeOut = 2.0 msec
Figure 24. OpenLoad in ON State for LED in PWM Operation (OFF time < 2.0 ms)
When output is in fully ON operation (100% PWM):
• the detection on all outputs is triggered by setting the OLLED TRIG bit inside the LED control register #13-2
• at the end of detection time, the current source (IOLLED) is disabled 100 µsec (typ.) after the output reactivation.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
OLLED TRIG 1
Note: OLLED TRIG bit is reset after the detection
ONoff & PWM
FF
hson_1
En_OLLed_1
100 sec
100 sec
VPWR
-0.75
V
BAT-0.75
OUT_1
check
OUT_high
Analog Comparator output
Check
Precision ~ 9600 ns
TimeOut = 2.0 msec
1 : olled detected
0 : no olled detected
Figure 25. OpenLoad in ON State for LED in Fully ON Operation
The OLLED TRIG bit is reset after the detection.
To delatch the diagnosis:
• a read command of the corresponding channel status register #2… #6 must be performed
A false “open” result could be reported in the OLON bit:
• for high duty cycles, the PWM off-time becomes too short
• for capacitive load, the output voltage slope becomes too slow
6.1.5.1.3
OpenLoad in OFF State
An OpenLoad in off state detection is provided individually for each power output (OUT1… OUT5).
The detection is enabled individually for each channel by the OLOFF EN bits inside the OpenLoad control register #13-1.
When the corresponding OLOFF EN is
• low (logic[0]), the diagnosis mode is disabled (default status)
• high (logic[1]), the diagnosis mode is started for tOLOFF. It is not possible to restart any OLOFF or disable the
diagnosis mode during active OLOFF state
This detection can be activated independently for each power output (OUT1… OUT5). But when it is activated, it is always
activated synchronously for all selected outputs (with positive edge of CS\).
When the detection is started, the corresponding output channel is turned on with a fixed overcurrent threshold of IOLOFF
threshold.
When this over current threshold:
• is reached within the detection timeout tOLOFF, the output is turned off and the OLOFF EN bit is reset. No OCLOx
and no OLOFFx will be reported
• is not reached within the detection timeout tOLOFF, the output is turned off after tOLOFF and the OLOFF EN bit is
reset. The OLOFFx will be reported
The overcurrent behavior, as commanded by the overcurrent control settings (NO OCHIx, OCHI ODx, SHORTOCHIx, OCLOx,
ACM ENx), is not be affected by applying the OLOFF ENx bit. The same is true for the output current feedback and the current
sense synchronization.
The detection result is reported:
• in the corresponding QSFx bit in the quick status register #1
• in the global OpenLoad flag OLF (register #1… #7)
• in the OLOFF bit of the corresponding channel status register #2… #6
MC17XSF500
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
To delatch the diagnosis a read command of the corresponding channel status register #2… #6 must be performed
In case of any fault during tOLOFF (OTS, UV, CPF,), the OpenLoad in off state detection is disabled and the output(s) is (are)
turned off after the deglitch time tFAULT SD. The corresponding fault is reported in SPI SO registers.
6.1.5.1.4
Electrical Characterization
Table 14. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
30
50
100
100
160
150
18
18
17
–
–
–
–
–
–
OpenLoad Current Threshold in ON state / OLLED mode
2.0
4.0
5.0
mA
Maximum OpenLoad Detection Time / OLLED mode with 100% duty cycle
1.5
2.0
2.6
ms
OpenLoad Detection Time in OFF State
0.9
1.2
1.5
ms
Fault Deglitch Time
• OLOFF
• OLON with OLON DGL = 0
• OLON with OLON DGL = 1
2.0
48
1.5
3.3
64
2.0
5.0
80
2.5
µs
ms
ms
0.385
0.55
0.715
A
Notes
POWER OUTPUTS OUT1… OUT5
IOL
OpenLoad Current Threshold in ON State
• TJ = -40 °C
• TJ = 25 °C and 125 °C
PWM OLON Output PWM Duty Cycle Range for OpenLoad Detection in ON state
• Low Frequency Range (25 to 100Hz)
• Medium Frequency Range (100 to 200Hz)
• High Frequency Range (200 to 400Hz)
IOLLED
tOLLED100
tOLOFF
tFAULT SD
IOLOFF
6.1.5.2
OpenLoad Current Threshold in OFF state
mA
LSB
Output Shorted to VPWR in OFF State
A short to VPWR detection during OFF state is provided individually for each power output OUT1… OUT5, based on an output
voltage comparator referenced to VPWR / 2 (VOUT DETECT) and external pull-down circuitry.
The detection result is reported in the OUTx bits of the I/O status register #8 in real time.
In case of UVF, the OUTx bits are undefined.
6.1.5.2.1
Electrical Characterization
Table 15. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
0.42
0.5
0.58
VPWR
Notes
POWER OUTPUTS OUT1… OUT5
VOUT
Output Voltage Comparator Threshold
DETECT
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
6.1.5.3
SPI Fault Reporting
Protection and monitoring of the outputs during normal mode is provided by digital switch diagnosis via the SPI.
The selection of the SO data word is controlled by the SOA0… SOA3 bits inside the initialization 1 register #0.
The device provides two different reading modes, depending on the SOA MODE bit.
When the SOA MODE bit is:
• low (logic[0]), the programmed SO address will be used for a single read command. After the reading the SO
address returns to quick status register #1 (default state)
• high (logic[1]), the programmed SO address will be used for the next and all further read commands until a new
programming
The “quick status register” #1 provides one glance failure overview. As long as no failure flag is set (logic[1]), no control action
by the µController is necessary.
Register
quick status
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
FM
DSF
OVLF
OLF
CPF
RCF
CLKF
QSF5
QSF4
QSF3
QSF2
QSF1
•
FM: Fail mode indication. This bit is present also in all other SO data words and indicates the fail mode by a
logic[1]. When the device is in Normal mode, the bit is logic[0]
• global device status flags (D10… D8): These flags are also present in the channel status registers #2… #6 and
the device status register #7 and are cleared when all fault bits are cleared by reading the registers #2… #7
• DSF = device status flag (RCF, or UVF, or OVF, or CPF, or CLKF, or TMF). UVF and TMF are also reported in the
device status register #7
• OVLF = overload flag (wired OR of all OC and OTS signals)
• OLF = OpenLoad flag
• CPF: charge pump flag
• RCF: registers clear flag: this flag is set (logic[1]) when all SI and SO registers are reset
• CLKF: clock fail flag. Refer to Logic I/O Plausibility Check section
• QSF1… QSF5: channel quick status flags (QSFx = OC0x, or OC1x, or OC2x, or OTWx, or OTSx, or OLONx, or
OLOFFx)
The SOA address #0 is also mapped to register #1 (D15… D12 bits will report logic [0001]).
When a fault condition is indicated by one of the quick status bits (QSF1… QSF5, OVLF, OLF), the detailed status can be
evaluated by reading of the corresponding channel status registers #2… #6.
Register
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CH 1 status
2
0
0
1
0
FM
DSF
OV LF
OLF
res
OTS 1
OTW1
OC21
OC11
OC01
OLON1
OLOFF 1
CH 2 status
3
0
0
1
1
FM
DSF
OV LF
OLF
res
OTS 2
OTW2
OC22
OC12
OC02
OLON2
OLOFF 2
CH 3 status
4
0
1
0
0
FM
DSF
OV LF
OLF
res
OTS 3
OTW3
OC23
OC13
OC03
OLON3
OLOFF 3
CH 4 status
5
0
1
0
1
FM
DSF
OV LF
OLF
res
OTS 4
OTW4
OC24
OC14
OC04
OLON4
OLOFF 4
CH 5 status
6
0
1
1
0
FM
DSF
OV LF
OLF
res
OTS 5
OTW5
OC25
OC15
OC05
OLON5
OLOFF 5
• OTSx: overtemperature shutdown flag
• OTWx: overtemperature warning flag
• OC0x… OC2x: overcurrent status flags
• OLONx: OpenLoad in on state flag
• OLOFFx: OpenLoad in off state flag
The most recent OC fault is reported by the OC0x… OC2x bits if a new OC occurs before an old OC on the same output was read.
When a fault condition is indicated by one of the global status bits (FM, DSF), the detailed status can be evaluated by reading of
the device status registers #7.
MC17XSF500
44
Analog Integrated Circuit Device Data
Freescale Semiconductor
Register
device status
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7
0
1
1
1
FM
DS F
OV LF
OLF
res
res
res
TM F
OV F
UV F
SP IF
iLIM P
•
TMF: test mode activation flag. Test mode is used for manufacturing testing only. If this bit is set to logic [1], the
MCU shall reset the device.
• OVF: overvoltage flag
• UVF: undervoltage flag
• SPIF: SPI fail flag
• iLIMP (real time reporting after the tIN_DGL, not latched)
The I/O status register #8 can be used for system test, Fail mode test, and the power down procedure.
Registe r
I/O status
SO addres s
SO da ta
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
8
1
0
0
0
FM
re s
TOGGLE
iIN4
iIN3
iIN2
iIN1
OUT5
OUT4
OUT3
OUT2
OUT1
The register provides the status of the control inputs, the toggle signal and the power outputs state in real time (not latched):
• TOGGLE = status of the 4 input toggle signals (IN1_ON or IN2_ON or IN3_ON or IN4_ON), reported in real time
• iINx = status of iINx signal (real time reporting after the tIN_DGL, not latched)
• OUTx = status of output pins OUTx (the detection threshold is VPWR/2) when an undervoltage condition does not
occur
The device can be clearly identified by the device ID register #9 when the supply voltage is within its nominal range.
Register
S O addre ss
#
dev ic e ID
9
D15
1
D14
0
SO da ta
D1 3
0
D12
1
D11
X
D10
X
D9
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
DEVID
7
DEVID
6
DEVID
5
DEVID
4
DEVID
3
DEVID
2
DEVID
1
DEVID
0
The register delivers DEVIDx bits = 41hex for the 17XSF500.
During undervoltage condition (UVF=1), DEVIDx bits report 00hex.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
6.1.6
Analog Diagnostics
The analog feedback circuit (CSNS) is implemented to provide load and device diagnostics during Normal mode. During Fail and
Sleep modes the analog feedback is not available.
The routing of the integrated multiplexer is controlled by MUX0… MUX2 bits inside the initialization 1 register #0.
6.1.6.1
Output Current Monitoring
The current sense monitor provides a current proportional to the current of the selected output (OUT1… OUT5). CSNS output
delivers 1.0 mA full scale range current source reporting channel 1… 5 current feedback (IFSR).
ICSNS
1.0 mA
#2~ #6
OC2x
0
0
0
1
0
1
0
0
0 mA
OC1x OC0x over current status
0
0
no ov erc urrent
O CHI1
O CHI2
ICSNS / IOUT = 1.0
mA / (100% FSR) typ
1
FSR value depends on SPI setting
1 Note:
O CHI3
1
0
0
O CLO
1
0
1
O CHIOD
1
1
0
SSC
1
1
1
not us ed
1% FSR
IOUT
100% FSR
Figure 26. Output Current Sensing
The feedback is suppressed during OCHI window (t < tOCHI1 + tOCHI2 + tOCHI3) and only enabled during low overcurrent shutdown
threshold (OCLO).
During PWM operation the current feedback circuit (CSNS) delivers current only during the on time of the output switch.
Current sense settling time, tCSNS(SET), varies with current amplitude. Current sense valid time, tCSNS(VAL), depends on the PWM
frequency.
An advanced current sense mode (ACM) is implemented in order to diagnose LED loads in Normal mode and to improve current
sense accuracy for low current loads.
In the ACM mode, the offset sign of current sense amplifier is toggled on every CSNS SYNC\ rising edge.
The error amplifier offset contribution to the CSNS error can be fully eliminated from the measurement result by averaging each
two sequential current sense measurements.
The ACM mode is enabled with the ACM ENx bits inside the ACM control register #10-1.
When the ACM ENx bit is:
• low (logic[0]), ACM disabled (default status and during Fail mode)
• high (logic[1]), ACM enabled
In ACM mode:
• the precision of the current recopy feature (CSNS) is improved especially at low output current by averaging
CSNS reporting on sequential PWM periods
• the current sense full scale range (FSR) is reduced by a factor of two
• the overcurrent protection threshold OCLO is reduced by a factor of two
The following figure describes the timings between the selected channel current and the analog feedback current. Current sense
validation time pertains to stabilization time needed after turn on. Current sense settling time pertains to the stabilization time
needed after the load current changes while the output is continuously on, or when another output signal is selected.
MC17XSF500
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
HSONx
tDLY(ON)
tDLY(OFF)
IOUTx
tCSNS(SET)
tCSNS(VAL)
time
time
CSNS
+/- 5% of new value
time
Figure 27. Current Sensing Response Time
Internal circuitry limits the voltage of the CSNS pin when its sense resistor is absent. This feature prevents damage to other
circuitry sharing that electrical node; such as a microcontroller pin.
Several 17XSF500 may be connected to one shared CSNS resistor.
6.1.6.2
Supply Voltage Monitoring
The VPWR monitor provides a voltage proportional to the supply tab. The CSNS voltage is proportional to the VPWR voltage as
shown.
VCSNS
5.0 V
VCSNS / VPWR = ¼ typ
0V
VPWRPOR
20 V
VPWR
Figure 28. Supply Voltage Reporting
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
6.1.6.3
Temperature Monitoring
The average temperature of the control die is monitored by an analog temperature sensor. The CSNS pin can report the voltage
of this sensor.
The chip temperature monitor output voltage is independent of the resistor connected to the CSNS pin, provided the resistor is
within the min/max range of 5.0 k to 50 k. Temperature feedback range, TFB, -40 °C to 150 °C.
VCSNS
VCSNS / TJ = VFBS
VFB
-40°C
25°C
150°C
TJ
Figure 29. Temperature Reporting
6.1.6.4
Analog Diagnostic Synchronization
A current sense synchronization pin is provided to simplify the synchronous sampling of the CSNS signal.
The CSNS SYNC\ pin is an open drain requiring an external 5.0 k (min) pull-up resistor to VCC.
The CSNS SYNC signal is:
• available during normal mode only
• behavior depends on the type of signal selected by the MUX2… MUX0 bits in the initialization 1 register #0. This
signal is either a current proportional to an output current or a voltage proportional to temperature or the supply
voltage.
Current sense signal
When a current sense signal is selected:
• the pin delivers a recopy of the output control signal during on phase of the PWM defined by the SYNC EN0,
SYNC EN1 bits inside the initialization 1 register #0.
MC17XSF500
48
Analog Integrated Circuit Device Data
Freescale Semiconductor
OUT1
time
OUT2
CSNS
SYNC\
CSNS SYNC\ CSNS SYNC\ blanked
active (low)
time
tDLY(ON)+tCSNS(SET)
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
OUT2 for CSNS selected
Figure 30. CSNS SYNC\ Valid Setting
OUT1
time
OUT2
CSNS SYNC\ blanked until
rising edge of the 1st
complete PWM cycle
CSNS
SYNC\
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
time
OUT2 for CSNS selected
Figure 31. CSNS SYNC\ TRIG0 Setting
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
OUT1
time
CSNS SYNC\
active (low)
OUT2
CSNS
SYNC\
CSNS SYNC\ blanked until 1rst valid edge
generated in the middle of the OUT2 pulse
time
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
•
•
•
•
OUT2 for CSNS selected
Figure 32. CSNS SYNC\ TRIG1/2 Setting
the CSNS SYNC\ pulse is suppressed during OCHI and during OFF phase of the PWM
the CSNS SYNC\ is blanked during settling time of the CSNS multiplexer and ACM switching by a fixed time of
tDLY(ON) + tCSNS(SET)
when a PWM clock fail is detected, the CSNS SYNC\ delivers a signal with 50% duty cycle at a fixed period of
6.5 ms
when the output is programmed with 100% PWM, the CSNS SYNC\ delivers a logic[0] a high pulse with the length
of 100 µs typ during the PWM counter overflow for TRIG0 and TRIG1/2 settings, as shown in Figure 33
OUT1
time
OUT2
time
CSNS
SYNC\
tDLY(ON)+tCSNS(SET)
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
OUT2 for CSNS selected
Figure 33. CSNS SYNC\ When the Output is Programmed with 100%
MC17XSF500
50
Analog Integrated Circuit Device Data
Freescale Semiconductor
•
During an output fault, the CSNS SYNC\ signal for current sensing does not deliver a trigger signal until the output
is enabled again.
Temperature signal or VPWR monitor signal.
When a voltage signal (average control die temperature or supply voltage) is selected:
• the CSNS SYNC\ delivers a signal with 50% duty cycle and the period of the lowest prescaler setting
(fCLK / 1024)
• and a PWM clock fail is detected, the CSNS SYNC\ delivers a signal with 50% duty cycle at a fixed period of
6.5ms (tSYNC DEFAULT).
6.1.6.5
Electrical Characterization
Table 16. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Current Sense Resistor Range
5.0
–
50
k
Current Sense Leakage Current when CSNS is disabled
-1.0
–
+1.0
µA
VCS
Current Sense Clamp Voltage
6.0
–
8.0
V
IFSR
Current Sense Full Scale Range
• High OCLO and ACM = 0
• Low OCLO and ACM = 0
• High OCLO and ACM = 1
• Low OCLO and ACM = 1
–
–
–
–
11
5.5
5.5
2.75
–
–
–
–
Notes
CURRENT SENSE CSNS
RCSNS
ICSNS LEAK
ACC ICSNS Current Sense Accuracy for 9.0 V < VPWR < 18 V
• IOUT = 80% FSR
• IOUT = 25% FSR
• IOUT = 10% FSR with ACM = 0
• IOUT = 10% FSR with ACM = 1
•OUT1, OUT2 and OUT5
•OUT3 and OUT4
• IOUT = 5.0% FSR with ACM = 0
• IOUT = 5.0% FSR with ACM = 1
•OUT1, OUT2, and OUT5
•OUT3 and OUT4
ACC ICSNS 1 Current Sense Accuracy for 9.0 V < VPWR < 18 V with 1 calibration point at
25 °C for 2.0% FSR and VPWR = 14 V
CAL 2%
• IOUT = 80% FSR
• IOUT = 25% FSR
• IOUT = 10% FSR
• IOUT = 5.0% FSR
ACC ICSNS 1 Current Sense Accuracy for 9.0 V < VPWR < 18 V with 1 calibration point at
25 °C for 50% FSR and VPWR = 14 V
CAL 50%
• IOUT = 80% FSR
• IOUT = 20% FSR
• IOUT = 15% FSR
• IOUT = 10% FSR
• IOUT = 5.0% FSR
A
-11
-14
-20
–
–
–
+11
+14
+20
-20
-25
-29
–
–
–
+20
+25
+29
-29
-40
–
–
+29
+40
-7.0
-7.0
-20
-29
-7.0
-7.0
-10
-20
-35
–
–
–
–
–
–
–
–
–
%
(20)
%
(20) (22)
%
(20) (22)
+7.0
+7.0
+20
+29
+7.0
+7.0
+10
+20
+35
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
Table 16. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
%
(20) (22)
%
(20) (23)
CURRENT SENSE CSNS (Continued)
ACC ICSNS 2 Current Sense Accuracy for 9.0 V < VPWR < 18 V with 2 calibration points
at 25 °C for 2.0% and 50% FSR and VPWR = 14 V
CAL
• IOUT = 80% FSR
• IOUT = 25% FSR
• IOUT = 10% FSR
-6.0
-6.0
-8.0
–
–
–
+6.0
+6.0
+8.0
-11
-21
–
–
+11
+21
• IOUT = 5.0% FSR
• OUT1 and OUT2
• OUT3, OUT4, and OUT5
ICSNSMIN
Minimum Current Sense Reporting
• for 9.0 V < VPWR < 18 V
• OUT1 and OUT2
• OUT3, OUT4, and OUT5
VPWR
Supply Voltage Feedback Range
–
–
–
–
1.0
2.0
VPWRMA
–
20
V
X
ACC VPWR Supply Feedback Precision
• Default
• 1 calibration point at 25 °C and VPWR = 12 V, for 7.0 V < VPWR < 20 V
• 1 calibration point at 25 °C and VPWR = 12 V, for 6.0 V < VPWR <
7.0 V
%
(22)
(21)
-5.0
-1.0
-2.2
–
–
–
+5.0
+1.0
+2.2
-40
–
150
°C
TFB
Temperature Feedback Range
VFB
Temperature Feedback Voltage at 25 °C
–
2.31
–
V
Coef VFB
Temperature Feedback Thermal Coefficient
–
7.72
–
mV/°C
(22)
ACCTFB
Temperature Feedback Voltage Precision
• Default
• 1 calibration point at 25 °C and VPWR = 7.0 V
°C
(22)
µs
(21)
µs
(24)
tCSNS(SET)
Current Sense Settling Time
• Current Sensing Feedback for IOUT from 75% FSR to 50% FSR
• Current Sensing Feedback for IOUT from 10% FSR to 1.0% FSR
Temperature and Supply Voltage Feedbacks
tCSNS(VAL)
Current Sense Valid Time
Current Sensing Feedback
• Low / Medium Frequency Ranges for IOUT > 20% FSR
–
–
–
–
–
–
–
–
+15
+5.0
40
260
10
Temperature Feedback
Supply Voltage Feedback
10
70
5.0
70
–
–
–
–
–
–
–
–
150
300
75
300
10
15
Current Sense Synchronization Period for PWM Clock Failure
4.8
6.5
8.2
• Low / Medium Frequency Ranges for IOUT < 20% FSR
• High Frequency Range for IOUT > 20% FSR
• High Frequency Range for IOUT < 20% FSR
tSYNC
-15
-5.0
ms
DEFAULT
MC17XSF500
52
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 16. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
5.0
–
–
k
–
–
0.4
V
-1.0
–
+1.0
µA
Notes
CURRENT SENSE SYNCHRONIZATION CSNS SYNC\
RCSNS SYNC Pull-up Current Sense Synchronization Resistor Range
VOL
IOUT MAX
Current Sense Synchronization Logic Output Low State Level at 1.0 mA
Current Sense Synchronization Leakage Current in Tri-state (CSNS SYNC
from 0 V to 5.5 V)
Notes
20. Precision either OCLO and ACM setting.
21. Parameter is derived mainly from simulations.
22. Parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process
variations.
23. Error of 100% without calibration and 50% with 1 calibration point done at 25 °C.
24. Tested at 5% of final value at VPWR = 14 V, current step from 0 A to 2.8 A (or 5.6 A). Parameter guaranteed by design at 1% of final value.
6.2
Power Supply Functional Block Description and Application
Information
6.2.1
Introduction
The device is functional when wake = [1] with supply voltages from 5.5 to 40 V (VPWR), but is fully specification compliant only
between 7.0 and 18 V. The VPWR pin supplies power to the internal regulator, analog, and logic circuit blocks. The VCC pin (5.0
V typ.) supplies the output register of the Serial Peripheral Interface (SPI) and the OUT6 driver. Consequently, the SPI registers
cannot be read without presence of VCC. The employed IC architecture guarantees a low quiescent current in Sleep mode
(wake= [0]).
6.2.2
Wake State Reporting
The CLK input/output pin is also used to report the wake state of the device to the microcontroller as long as RSTB is logic [0].
When the device is in:
• “wake state” and RSTB is inactive, the CLK pin reports a high signal (logic[1])
• “Sleep mode” or the device is wake by the RSTB pin, the CLK is an input pin
6.2.2.1
Electrical Characterization
Table 17. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
VCC - 0.6
–
–
V
Notes
CLOCK INPUT/OUTPUT CLK
VOH
Logic Output High State Level (CLK) at 1.0 mA
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
53
6.2.3
Supply Voltages Disconnection
6.2.3.1
Loss of VPWR
In case of a VPWR disconnection (VPWR < VPWR POR), the device behavior depends on the VCC voltage value:
• VCC < VCC POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults
are cleared.
• VCC > VCC POR: all registers and faults are maintained. OUT1… 5 are shut off immediately. The ON/OFF state of
OUT6 depends on the current SPI configuration. SPI reporting is available when VCC remains within its operating
voltage range (4.5 to 5.5 V).
The wake-up event is not reported to CLK terminal.
The clamping structures (supply clamp, negative output clamp) are available to protect the device.
No current is conducted from VCC to VPWR.
An external current path shall be available to drain the energy from an inductive load in case of supply disconnection occurs when
an output is ON.
6.2.3.2
Loss of VCC
In case of VCC disconnection the device behavior depends on VPWR voltage:
• VPWR < VPWR POR: the device enters the power off mode. All outputs are shut off immediately. All registers and
faults are cleared.
• VPWR > VPWR POR: the SPI is not available. Therefore, the device will enter WD timeout.
The clamping structures (supply clamp, negative output clamp) are available to protect the device.
No current is conducted from VPWR to VCC.
6.2.3.3
Loss of Device GND
During loss of ground, the device cannot drive the loads, therefore the OUT1… OUT5 outputs are switched off and the OUT6
voltage is pulled up.
The device shall not be damaged by this failure condition.
For protection of the digital inputs series resistors (1.0 k typ) can be provided externally in order to limit the current to ICL.
6.2.3.4
Electrical Characterization
Table 18. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Supply Power On Reset
2.0
3.0
4.0
V
VCC Power On Reset
2.0
3.0
4.0
V
-1.5
–
+1.5
V
Notes
SUPPLY VPWR
VPWR POR
VCC
VCC POR
GROUND GND
VGND SHIFT Maximum Ground Shift between GND Pin and Load Grounds
MC17XSF500
54
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.3
Communication Interface and Device Control Functional Block
Description and Application Information
6.3.1
Introduction
In Normal mode the power output channels are controlled by the embedded PWM module, which is configured by the SPI register
settings. For bidirectional SPI communication, VCC has to be in the authorized range. Failure diagnostics and configuration are
also performed through the SPI port. The reported failure types are: OpenLoad, short-circuit to supply, severe short-circuit to
ground, overcurrent, overtemperature, clock fail, and under and overvoltage.
For direct input control, the device shall be in Fail-safe mode. VCC is not required and this mode can be forced by LIMP input pin.
6.3.2
Fail Mode Input (LIMP)
The Fail mode of the component can be activated by LIMP direct input. The Fail mode is activated when the input is logic [1].
In Fail mode, the channel power outputs are controlled by the corresponding inputs. Even though the input thresholds are logic
level compatible, the input structure of the pins shall be able to withstand supply voltage level (max. 40 V) without damage.
External current limit resistors (i.e. 1.0 k...10 k) can be used to handle reverse current conditions. The direct inputs have an
integrated pull-down resistor.
The LIMP input has an integrated pull-down resistor. The status of the LIMP input can be monitored by the LIMP IN bit inside the
device status register #7.
6.3.2.1
Electrical Characterization
Table 19. Electrical Characteristics
Characteristics noted under conditions 4.5 V VPWR 5.5 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
FAIL MODE INPUT LIMP
VIH
Logic Input High State Level
3.5
–
–
V
VIL
Logic Input Low State Level
–
–
1.5
V
IIN
Logic Input Leakage Current in Inactive State (LIMP = [0])
-0.5
–
+0.5
µA
Logic Input Pull-down Resistor
25
–
100
k
Logic Input Capacitance
–
–
20
pF
Logic Input High State Level
3.5
–
–
V
Logic Input High State Level for wake-up
3.75
–
–
V
–
–
1.5
V
RPULL
CIN
(25)
DIRECT INPUTS IN1… IN4
VIH
VIH(WAKE)
VIL
Logic Input Low State Level
IIN
Logic Input Leakage Current in Inactive State (forced to [0])
-0.5
–
+0.5
µA
Logic Input Pull-down Resistor
25
–
100
k
Logic Input Capacitance
–
–
20
pF
RPULL
CIN
(25)
Notes
25. Parameter is derived mainly from simulations.
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
55
6.3.3
MCU Communication Interface Protections
6.3.3.1
Loss of Communication Interface
If a SPI communication error occurs, then the device is switched into Fail mode.
An SPI communication fault is detected if:
• the WD bit is not toggled with each SPI message, or
• WD timeout is reached, or
• protocol length error (modulo 16 check)
The SI stuck to static levels during CSB period and VCC fail (SPI not functional) are indirectly detected by WD toggle error.
The SPI communication error is reported in
• SPI failure flag (SPIF) inside the device status register #7 in the next SPI communication
As long as the device is in Fail mode, the SPIF bit retains its state.
The SPIF bit is delatched during the transition from Fail-to-Normal modes.
6.3.3.2
Logic I/O Plausibility Check
The logic and signal I/O are protected against fatal mistreatment by signal plausibility check according following table:
I/O
Signal check strategy
IN1 ~ IN4
frequency above limit (low pass filter)
LIM P
frequency above limit (low pass filter)
RST\
frequency above limit (low pass filter)
CLK
frequency above limit (low pass filter)
The LIMP and the IN1… IN4 have an input symmetrically deglitch time tIN_DGL = 200 µs (typ).
If the LIMP input is set to logic [1] for a delay longer than 200 µs (typ), the device is switched into Fail mode (internal signal called
iLIMP).
LIMP
tIN_DGL
200µs typ.
tIN_DGL
200µs typ.
time
iLIMP
time
Figure 34. LIMP and iLIMP signal
In case the INx input is set to logic [1] for a delay longer than 200 µs (typ.), the corresponding channel is controlled by the direct
signal (internal signal called iINx).
MC17XSF500
56
Analog Integrated Circuit Device Data
Freescale Semiconductor
INx
tIN_DGL
tIN_DGL
iINx
tIN_DGL
tIN_DGL
tIN_DGL
time
tIN_DGL
200µs typ.
ttoggle
1024ms typ.
ttoggle
time
INx_ON
time
Figure 35. IN, iIN, and IN_ON signal
The RSTB has an input deglitch time tRST_DGL = 10 µs (typ) for the falling edge only.
The CLK has an input symmetrically deglitch time tCLK_DGL = 2.0 µs (typ). Due to the input deglitcher (at the CLK input) a very
high input frequency leads to a clock fail detection.
The CLK fail detection (clock input frequency detection fCLK LOW) is started immediately with the positive edge of the RSTB signal.
If the CLK frequency is below fCLK LOW limit, the output state will depend on the corresponding CHx signal.
As soon as the CLK signal is valid, the output duty cycle depends on the corresponding SPI configuration.
To delatch the CLK fail diagnosis:
• the clock failure condition must be removed
• a read command of the quick status register #1 must be performed
6.3.3.3
Electrical Characterization
Table 20. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
SPI Watchdog Timeout
• WD SEL = 0
• WD SEL = 1
24
96
32
128
40
160
Input Toggle Time for IN1… IN4
768
1024
1280
Input Deglitching Time
• LIMP and IN1… IN4
• CLK
• RST\
150
1.5
7.5
200
2.0
10
250
2.5
12.5
50
100
200
Unit
Notes
LOGIC I/O LIMP IN1… IN4 CLK
tWD
tTOGGLE
tDGL
fCLOCK LOW Clock Low Frequency Detection
ms
ms
µs
Hz
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
6.3.4
External Smart Power Control (OUT6)
The device provides a control output to drive an external smart power device in Normal mode only.
The control is according to the channel 6 settings in the SPI input data register.
• The protection and current feedback of the external SmartMOS device are under the responsibility of the
microcontroller.
• The output delivers a 5.0 V CMOS logic signal from VCC.
The output is protected against overvoltage.
An external current limit resistor (i.e. 1.0 k...10 k) shall be used to handle negative output voltage conditions.
The output has an integrated pull-down resistor to provide a stable OFF condition in Sleep mode and Fail mode.
In case of a ground disconnection, the OUT6 voltage is pulled up. External components are mandatory to define the state of
external smart power device, and to limit possible reverse OUT6 current (i.e. resistor in series).
6.3.4.1
Electrical Characterization
Table 21. Electrical Characteristics
Characteristics noted under conditions 7.0 V VPWR 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
–
–
5.0
µs
5.0
10
20
k
Notes
EXTERNAL SMART POWER OUTPUT OUT6
tOUT6 RISE
OUT6 Rising Edge for 100 pF Capacitive Load
ROUT6 DWN OUT6 Pull-down Resistor
VOH
Logic Output High State Level (OUT6)
VCC - 0.6
–
–
V
VOL
Logic Output Low State Level (OUT6)
–
–
0.6
V
MC17XSF500
58
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
Typical Applications
7.1
Introduction
The 17XSF500 is the latest achievement in drivers for all types of centralized lighting applications.
7.1.1
Application Diagram
VPWR RIGHT
20V
5V Regulator
VBAT
VPWR
VCC
10µ
10n…100n
GND
VCC
VCC
VCC Clamp
100n
100n
5k
CSB
SCLK
SCLK
Main MCU SI
10n
OUT2
Parking Light
10n
Flasher
RSTB
CLK
CLK
A/D1
OUT3
10n
Low Beam
CSNS
10k
TRIG1
GND
OUT1
SO
RSTB
GND
VCC VBAT CP
SI
SO
CSB
SYNCB
A/D2
LIMP
A/D3
IN1
10n
OUT4
10n
OUT5
Fog Light
10n
High Beam
IN2
1k
1k
5k
IN3
OUT6
IN4
VBAT OUT
VPWR
IN
1k
GND
10n
Smart Power
CSNS
GND
CSNS
GND
Spare
1k
GND
IN4
IN3
Smart Power
1k
OUT6
IN
IN2
OUT5
10n
LIMP
SYNCB
Fog Light
OUT4
10n
CSNS
CLK
LIMP
IN1
Watchdog IN2
IN3
GND
IN4
Spare
10n
High Beam
IN1
VBAT
VPWR
VPWR
VBAT OUT
Low Beam
OUT3
10n
OUT2
10n
RSTB
1k
SO
1k
SCLK
1k
CSB
1k
SI
Flasher
Parking Light
OUT1
10n
VCC VBAT CP
1k
100n
10n…100n
20V
100n
VPWR LEFT
Figure 36. Typical Front Lighting Application for Automotive
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
59
7.1.2
Application Instructions
7.1.3
Bill of Material
Table 22. 17XSF500 Bill of Material (26)
Signal
Location
Mission
Value
VPWR
close to Gen4
eXtreme Switch
reduction of emission and immunity
100 nF (X7R 50 V)
CP
close to Gen4
eXtreme Switch
charge pump tank capacitor
100 nF (X7R 50 V)
VCC
close to Gen4
eXtreme Switch
reduction of emission and immunity
10 nF to 100 nF (X7R 16 V)
OUT1… OUT5
close to output
connector
sustain ESG gun and fast transient pulses
10 nF to 22 nF (X7R 50 V)
CSNS
close to MCU
output current sensing
CSNS
close to MCU
low pass filter removing noise
CSNS SYNCB
N/A
pull up resistor for the synchronization of A/D conversion
IN1… IN4
N/A
sustain high-voltage
1.0 k (1.0%)
OUT6
N/A
sustain reverse supply
1.0 k (1.0%)
5.0 k (1.0%)
10 k (1.0%) &
10 nF (X7R 16 V)
5.0 k (1.0%)
To Increase Fast Transient Pulses Robustness
VPWR
close to connector
sustain pulse #1 in case of LED loads or without loads
VPWR
close to Gen4
eXtreme Switch
sustain pulse #2 without loads
20 V zener diode and diode in series
per supply line
additional 10 µF (X7R 50 V)
To Sustain 5.0 V Voltage Regulator Failure Mode
VCC
close to 5.0 V
voltage regulator
prevent high-voltage application on the MCU
5.0 V zener diode and a bipolar
transistor
Notes
26. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings
or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their
application.
MC17XSF500
60
Analog Integrated Circuit Device Data
Freescale Semiconductor
7.2
EMC & EMI Considerations
7.2.1
EMC/EMI Tests
This paragraph gives EMC/EMI performance, according to automotive specifications. Further generic design recommendations
can be e.g. found on the Freescale web site www.freescale.com.
Table 23. 17XSF500 EMC/EMI Performances
Test
Conducted Emission
Conducted Immunity
Automotive
Standard
Criteria
VPWR
CISPR25
Class 5
150 Method
Global pins: VPWR and OUT1… OUT5
Local pins: VCC, CP, and CSNS
IEC 61967-4
150 Method
Global pins: 12-L level (27)
Local pins: 10-K level
IEC 62132-4
Class A related to the outputs state and
the analog diagnostics (20%)
30 dBm for Global pins
12 dBm for Local pins
Signals
Conditions
Global pins: VPWR and OUT1… OUT5
Local pins: VCC
outputs off
outputs on
in PWM
Notes
27. With additional 2.2 nF decoupling capacitor on VPWR
7.2.2
Fast Transient Pulse Tests
This paragraph gives the device performances against fast transient disturbances.
Table 24. 17XSF500 Fast Transient Capability on VPWR
Test
Conditions
Pulse 1
outputs loaded with lamps
other cases with external transient voltage suppressor
Pulse 2a
Pulse 3a / 3b
Pulse 5b (40 V)
Automotive
Standard
Criteria
ISO 7637-2
Class A
outputs loaded
outputs unloaded
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
61
7.3
Robustness Considerations
The short-circuit protections embedded in 17XSF500 are preferred to conventional current limitations, to minimize the thermal
overstress within the device in case of an overload condition. The junction temperature elevation is drastically reduced to a value
which does not affect the device’s reliability. Moreover, the availability of the lighting is guaranteed in Fail mode by the unlimited
auto-restart feature.
Chapter 12 of AEC-Q100 specification published by the Automotive Electronics Council, presents a turn-on into short-circuit
condition. It is not enough because the short-circuit event can also occur in on-state. The 17XSF500 test plan at TA = 70 °C is
presented in Table 25. The tests were performed on 30 parts from 3 engineering lots (total 90 pieces).
Table 25. 17XSF500 Repetitive Short-circuit Test Results at TA = 70 °C
Short-circuit Case
Supply Voltage
Turn-on into short-circuit condition
16 V
Supply Line
0.3 m /2.5 mm²
5.0 m /2.5 mm²
Short-circuit in on-state
(28)
14 V
0.3 m /2.5 mm²
5.0 m /2.5 mm²
Load Line
Cycles without Failure
5.0 m /1.0 mm²
500 k
0.3 m / 1.0 mm²
5.0 m /1.0 mm²
0.3 m / 1.0 mm²
500 k
500 k
500 k
500 k
500 k
Notes
28. The channel was loaded in the on-state with 100 mA.
Table 26. 17XSF500 AECQ100-12 Reliability Test Results at TA = 85 °C and Supply Voltage = 14 V
Short-circuit Case
Supply Line
Load Line
AECQ100-12 Grade
Load short-circuit
5.0 H/10 m
5.0 H/50 m
D
For either conditions, contact our local Field Application Engineer (email: support@freescale.com).
MC17XSF500
62
Analog Integrated Circuit Device Data
Freescale Semiconductor
7.4
PCB Layout Recommendations
This new generation of high-side switch products family facilitates ECU design thanks to compatible MCU software and PCB foot
print for each device variant. The PCB Copper layer is similar for all devices in the family, only the solder Stencil opening is
different.
Figure 37. PCB Copper Layer & Solder Stencil Opening Recommendations
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
63
7.5
Thermal Information
This section is to provide thermal information.
7.5.1
Thermal Transient
Figure 38. Transient Thermal Response Curve
7.5.2
R/C Thermal Model
Contact our local Field Application Engineer (email: support@freescale.com).
MC17XSF500
64
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
Packaging
8.1
Marking Information
Device markings indicate information on the week and year of manufacturing. The date is coded with the last four characters of
the nine character build information code (e.g. “CTKAH1229”). The date is coded as four numerical digits where the first two digits
indicate the year and the last two digits indicate the week. For instance, the date code “1229” indicates the 29th week of the year
2012.
8.2
Package Mechanical Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
Table 27. Package Outline
Package
Suffix
32-Pin SOICW-EP
EK
Package Outline Drawing Number
98ASA00368D
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
65
EK SUFFIX
32-PIN SOIC-EP
98ASA00368D
ISSUE 0
MC17XSF500
66
Analog Integrated Circuit Device Data
Freescale Semiconductor
EK SUFFIX
32-PIN SOIC-EP
98ASA00368D
ISSUE 0
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
67
EK SUFFIX
32-PIN SOIC-EP
98ASA00368D
MC17XSF500
68
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
Revision History
REVISION
DATE
DESCRIPTION OF CHANGES
1.0
9/2013
• Initial release
2.0
9/2013
• Added the note “To achieve high reliability over 10 years of continuous operation, the device's
continuous operating junction temperature should not exceed 125C.” to Operating Temperature
• Corrected one typo error for Power Channel Current
MC17XSF500
Analog Integrated Circuit Device Data
Freescale Semiconductor
69
How to Reach Us:
Information in this document is provided solely to enable system and software implementers to use Freescale products.
Home Page:
freescale.com
on the information in this document.
Web Support:
freescale.com/support
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based
Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no
warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2013 Freescale Semiconductor, Inc.
Document Number: MC17XSF500
Rev. 2.0
9/2013
工商网监
湘ICP备2023018690号
