NXP Semiconductors
Data Sheet: Advance Information
Document Number: MC22XS4200
Rev. 5.0, 6/2018
Dual 24 V, 22 mOhm high-side switch
The 22XS4200 device is part of a 24 V dual high-side switch product family with
integrated control, and a high number of protective and diagnostic functions. It
is designed for truck and bus applications. The low RDS(on) channels ( VIH
–
6.5
8.5
mA
IPWR(SBY)
VPWR supply current, device in Wake-up mode (Standby), channel Off
open load in OFF-state detection disabled, HS[0 : 1] shorted to ground with
VDD = 5.5 V and RSTB > VWAKE
–
6.5
8.5
mA
–
–
3.0
–
10.0
60.0
3.0
–
5.5
V
IPWR(SLEEP)
Sleep state supply current
VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0 : 1] connected to ground
• TA = 25 °C
• TA = 125 °C
μA
VDD(ON)
VDD supply voltage
IDD(ON)
VDD supply current at VDD = 5.5 V
• No SPI communication
• 8.0 MHz SPI communication
–
–
–
5.0
2.2
–
mA
IDD(SLEEP)
VDD sleep state current at VDD = 5.5 V with or without VPWR
–
–
5.0
μA
VPWR(OV)
Overvoltage shutdown threshold
39
42
45.5
V
VPWR(OVHYS)
Overvoltage shutdown hysteresis
0.2
0.8
1.5
V
VPWR(UV)
Undervoltage shutdown threshold
5.0
–
6.0
V
(12)
VPWR Power-on reset (POR) voltage threshold
2.2
2.6
4.0
V
(12)
VDD(POR)
VDD Power-on reset (POR) voltage threshold
1.5
2.0
2.5
V
(12)
VDD(FAIL)
VDD supply failure voltage threshold (assumed VPWR > VPWR(UV))
2.2
2.5
2.8
V
–
–
–
18.7
18.7
18.7
–
–
–
VPWR(POR)
RDS(on)25
ON-Resistance, Drain-to-Source (IHS = 1.0 A, TJ = 25 °C) CSNS_ratio = 0
• VPWR = 8.0 V
• VPWR = 28 V
• VPWR = 36 V
(11)
mΩ
Notes
10. In Extended mode, availability of several device functions (channel control, value of RDS(on), overtemperature protection) is guaranteed, but
compliance with the specified values in this document is not. Below 6.0 V, the device is only protected from overheating (thermal shutdown).
Above VPWR(OV), the channels can only be turned ON when the overvoltage detection function has been disabled.
11.
12.
Typical value guaranteed per design.
When the device recovers from undervoltage and returns to Normal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period (see
Auto-retry), the device performs normally. When VPWR drops below VPWR(UV), undervoltage is detected (see Undervoltage fault (Latchable fault)
and EMC performances).
22XS4200
9
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
–
–
–
–
–
–
43
43
43
-0.9
–
0.9
–
–
43
mΩ
30
55
110
100
175
365
180
300
620
cm
26.4
32
38.5
16.3
20.1
24.5
10.4
12.6
15.2
6.4
7.7
9.3
4.3
5.3
6.3
2.9
3.6
4.3
1.4
1.8
2.2
8.9
10.7
12.8
5.6
6.8
8.2
3.5
4.25
5.1
2.2
2.7
3.2
1.45
1.75
2.1
0.98
1.2
1.45
0.48
0.6
0.72
–
-120
-1400
–
–
–
+5.0
+5.0
+5.0
µA
-620
-440
-330
-495
-360
-280
-380
-280
-230
µA
0
-
1000
Switch turn-on threshold for supply overvoltage (VPWR -GND)
58
–
67
V
Switch turn-on threshold for Drain-Source overvoltage (measured at
IOUT = 500 mA
58
–
66
V
-2.0
–
+2.0
V
Notes
Electrical characteristics of the output stage (HS0 and HS1)
RDS(on)150
ON-Resistance, Drain-to-Source (IHS = 1.0 A,TJ = 150 °C) CSNS_ratio = 0
• VPWR = 8.0 V
• VPWR = 28 V
• VPWR = 36 V
ΔRDS(on)150
RSD(on)150
LSHORT
I_OCH1_0
I_OCH2_0
I_OCM1_0
I_OCM2_0
I_OCL1_0
I_OCL2_0
I_OCL3_0
ON-Resistance, Drain-to-Source difference from one channel to the other in
Parallel mode (IHS = 1.0 A,TJ = 150 °C) CSNS_ratio = X
ON-Resistance, Source-Drain (IHS = -1.0 A, TJ = 150 °C,
VPWR = -24 V)
Max. detectable wiring length (2.5 mm²) for severe short-circuit detection
(see Severe short-circuit fault (Latchable fault)):
• High slew rate selected
• Medium slew rate selected
• Low slew rate selected
Overcurrent detection thresholds with CSNS_ratio bit = 0 (CSR0)
I_OCH1_1
I_OCH2_1
I_OCM1_1
I_OCM2_1
I_OCL1_1
I_OCL2_1
I_OCL3_1
Overcurrent detection thresholds with CSNS_ratio bit = 1(CSR1)
IOUT_LEAK
Output (HS[x]) leakage current in sleep state (positive value = outgoing)
• VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state)
VHS,OFF = VPWR, device in sleep state (VPWR = 24 V)
VHS,OFF = VPWR, device in sleep state (VPWR = 36 V)
mΩ
mΩ
A
A
Output biasing current in off-state (positive value = outgoing)
with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
IOUT_OFF
VD_GND(CLAMP)
VDS(CLAMP)
ΔVDS(CLAMP)
•
•
•
•
Fast slew rate selected
Medium slew rate selected
Slow slew rate selected
With OL_OFF disabled and ECU ground disconnected (VPWR = 32 V)
Switch turn-on threshold for Drain-Source overvoltage difference from one
channel to the other in Parallel mode (at IHS = 500 mA)
22XS4200
NXP Semiconductors
10
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Current Sensing Ratio
• CSNS_ratio bit = 0 (high current mode)
• CSNS_ratio bit = 1 (low current mode)
–
–
1/1500
1/500
–
–
–
(13)
I_LOAD_MIN
Minimum measurable load current with compensated error
–
–
50
mA
(14)
ICSR_LEAK
CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0)
-4.0
–
+4.0
µA
–
-4.0
–
mA
-125
–
125
mA
5.15
–
–
mA
-13
-12
-17
-26
–
–
–
–
13
12
17
26
-10
-9.0
-12
-15
–
–
–
–
10
9.0
12
15
-10
-10
-12
-16
–
–
–
–
10
10
12
16
Electrical characteristics of the output stage (HS0 and HS1) (continued)
CSR0
CSR1
I_LOAD_ERR_SYS
Systematic offset error (see Current sense errors)
I_LOAD_ERR_RAND Random offset error
ICSNS,MAX
CSNS pin current sourcing capability, absolute upper limit
ESR0_ERR
ESR0 output current sensing error (%), uncompensated at output current level
(sense ratio CSR0 selected):
TJ = -40 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 125 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 25 °C to 125 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
%
(15)
Notes:
13. Current sense ratio CSRx = ICSNS / (IHS[x] +I_LOAD_ERR_SYS)
14.
15.
See note (15), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further
accuracy improvements can be obtained by performing a 1 or 2 point calibration (see Application Note).
ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section
Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
22XS4200
11
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
-11
-11
-11
-11
–
–
–
–
11
11
11
11
-9.0
-9.0
-9.0
-10
–
–
–
–
9.0
9.0
9.0
10
-10
-9.0
-9.0
-10
–
–
–
–
10
9.0
9.0
10
-16
–
16
-10
–
10
-12
–
12
-11
-14
-19
-29
–
–
–
–
11
14
19
29
-9.0
-10
-12
-16
–
–
–
–
9.0
10
12
16
-9.0
-11
-13
-21
–
–
–
–
9.0
11
13
21
Unit
Notes
%
(16)
%
(16)
%
(17)
Electrical characteristics of the output stage (HS0 and HS1) (continued)
ESR0 output current sensing error (%) after offset compensation at output
current level (sense ratio CSR0 selected):
TJ = -40 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 125 °C
• 3.0 A
ESR0_ERR(Comp)
• 1.5 A
• 0.75 A
• 0.375 A
TJ = 25 °C to 125 °C
• 3.0 A
• 1.5 A
• 0.75 A
• 0.375 A
ESR1_ERR
ESR1 output current sensing error (%), uncompensated at output current level
(sense ratio CSR1 selected):
TJ = -40 °C
• 0.75 A
TJ = 125 °C
• 0.75 A
TJ = 25 °C to 125 °C
• 0.75 A
ESR1 output current sensing error (%) after offset compensation at output
current level (sense ratio CSR1 selected):
TJ = -40 °C
• 0.75 A
• 0.25 A
• 0.125 A
• 0.075 A
TJ = 125 °C
• 0.75 A
ESR1_ERR(Comp)
• 0.25 A
• 0.125 A
• 0.075 A
TJ = 25 °C to 125 °C
• 0.75 A
• 0.25 A
• 0.125 A
• 0.075 A
Notes:
16. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section
Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS
17.
See note (18), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further
accuracy improvements can be obtained by performing a 1 or 2 point calibration.
22XS4200
NXP Semiconductors
12
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
-10
-11
–
–
10
11
-8.0
-8.0
–
–
8.0
8.0
-9.0
-9.0
–
–
9.0
9.0
Unit
Notes
%
(18)
Electrical characteristics of the output stage (HS0 and HS1) (continued)
ESR0_ERR_PAR
ESR0 output current sensing error in parallel mode (%), uncompensated) at
outputs current level (sense ratio CSR0 selected):
TJ = -40 °C
• 6.0 A
• 3.0 A
TJ = 125 °C
• 6.0 A
• 3.0 A
TJ = 25 °C to 125 °C
• 6.0 A
• 3.0 A
VCL(CSNS)
Current sense clamping voltage (condition: R(CSNS) > 10 kΩ)
5.5
–
7.5
V
IOLD(OFF)
Open load detection current threshold in OFF state
30
–
100
μA
Open load fault detection voltage threshold
4.0
–
5.5
V
40
4.0
150
7.0
300
10
mA
VOLD(THRES)
IOLD(ON)
Open load detection current threshold in ON state (see Open load detection
in On state (OL_ON)):
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this
function)
tOLLED
Time period of the periodically activated open load in ON state detection for
CSNS_ratio bit = 1
105
150
195
ms
VOSD(THRES)
Output shorted-to-VPWR detection voltage threshold (channel in OFF state)
VPWR-1.2
VPWR-0.8
VPWR-0.4
V
Switch turn-on threshold for negative output voltages (protects against
negative transients) - (measured at IOUT = 100mA, channel in OFF state)
-38
–
-32
V
Switch turn-on threshold for negative output voltages difference from one
channel to the other in parallel mode - (measured at IOUT = 100 mA, channel
in OFF state)
-2.0
–
+2.0
V
VCL
ΔVCL
VHS_TH
TSD
Switching State (On/Off) discrimination thresholds
Shutdown temperature (power MOSFET junction; 6.0 V < VPWR < 58 V)
0.45*VPWR 0.5*VPWR 0.55*VPWR
160
175
190
V
°C
Notes:
18. Minimum required value of open load impedance for detection of open load in OFF-state: 200 kΩ.(VOLD(THRES) = VHS at IOLD(OFF))
22XS4200
13
NXP Semiconductors
Table 4. Static electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Electrical characteristics of the control interface pins
VIH
Logic input voltage, high
2.0
–
5.5
V
(19)
VIL
Logic input voltage, low
-0.3
–
0.8
V
(19)
Wake-up threshold voltage (IN[0:1] and RSTB)
1.0
–
2.2
V
(20)
Internal pull-down current source (on inputs: CLOCK, SCLK and SI)
5.0
–
20
μA
(21)
Internal pull-up current source (input CSB)
5.0
–
20
μA
(22)
Internal pull-up current source (input CONF[0:1])
25
–
100
μA
(23)
Capacitance of SO, FSB and FSOB pins in tri-state
–
–
20
pF
125
250
500
kΩ
–
4.0
12
pF
VDD-0.4
–
–
V
–
–
0.4
V
- 2.0
0.0
2.0
μA
1.0
50
–
–
10
Infinite
kΩ
VWAKE
IDWN
IUP_CSB
IUP_CONF
CSO
RDWN
CIN
Internal pull-down resistance (RSTB and IN[0:1])
Input capacitance
VSOH
SO high-state output voltage
• (IOH = 1.0 mA)
VSOL
SYNC, SO, FSOB and FSB low-state output voltage
• (IOL = -1.0 mA)
ISO(LEAK)
RCONF
SYNC, SO, CSNS, FSOB and FSB tri-state leakage current:
• 0.0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V
or V(CSNS) = 0.0 V
CONF[0:1]: Required values of the external pull-down resistor
• Lighting applications
• DC motor applications
(24)
Notes
19. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN[0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR
and can tolerate voltages up to 58 V.
20. Voltage above which the device wakes up
21. Valid for VSI > 0.8 V and VSCLK > 0.8 V and VCLOCK > 0.8 V
22.
Valid for VCSB < 2.0 V. CSB has an internal pull-up current source derived from VDD
23.
Pins CONF[0:1] are connected to an internal current source, derived from an internal voltage regulator (VREG ~ 3.0 V).
24.
Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing process
but is not tested in production.
22XS4200
NXP Semiconductors
14
4.3
Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
0.4
0.6
0.7
–
–
–
1.2
1.8
2.1
0.2
0.3
0.35
–
–
–
0.6
0.9
1.05
0.8
1.2
1.4
–
–
–
2.5
3.6
4.2
0.75
–
1.25
-0.16
-0.08
-0.32
0.0
0.0
0.0
0.16
0.08
0.32
Unit
Notes
V/μs
(25)
V/μs
(25)
V/μs
(25)
V/μs
(25)
Output voltage switching characteristics
SRR_00
SRF_00
SRR_01
SRF_01
SRR_10
SRF_10
Rising and falling edges medium slew rate (SR[1:0] = 00)
• VPWR = 16 V
• VPWR = 28 V
• VPWR = 36 V
Rising and falling edges low slew rate (SR[1:0] = 01)
• VPWR = 16 V
• VPWR = 28 V
• VPWR = 36 V
Rising and falling edges high slew rate / SR[1:0] = 10)
• VPWR = 16 V
• VPWR = 28 V
• VPWR = 36 V
Δ SR
Rising/falling edge slew rate matching (SRR /SRF)
• 16 V < VPWR < 36 V
ΔSR
Edge slew rate difference from one channel to the other in Parallel
mode
16 V < VPWR < 36 V
SR[1:0] = 00
SR[1:0] = 01
SR[1:0] = 10
t DLY_00
Output Turn-ON and Turn-OFF Delays (medium slew rate:
SR[1:0] = 00)
• 16 V < VPWR < 36 V
6.0
–
60
μs
(26)
t DLY_01
Output Turn-ON and Turn-OFF delays (low slew rate / SR[1:0] = 01)
• 16 V < VPWR < 36 V
10
–
120
μs
(26)
t DLY_10
Output Turn-ON and Turn-OFF delays (high slew rate / SR[1:0] = 10)
• 16 V < VPWR < 36 V
4.0
–
35
μs
(26)
Δ t RF_00
Turn-ON and Turn-OFF delay time matching (t DLY(ON) - t DLY(OFF))
• f PWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on
IN[x] = 50 %, SR[1:0] = 00
-25
–
25
μs
Δ t RF_01
Turn-ON and Turn-OFF delay time matching (t DLY(ON) - t DLY(OFF))
• f PWM = 200 Hz, 16 V < VPWR < 36 V, duty cycle on
IN[x] = 50 %, SR[1:0] = 01
-50
–
50
μs
Δ t RF_10
Turn-ON and Turn-OFF Delay time matching (t DLY(ON) - t DLY(OFF))
• f PWM = 1.0 kHz, 16 V < VPWR < 36 V, duty cycle on
IN[x] = 50 %, SR[1:0] = 10
-13
–
13
μs
Notes
25. Rising and falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and delay).
26. Turn-ON delay time measured as delay between a rising edge of the channel control signal (IN[0 : 1] = 1) and the associated rising edge of the
output voltage up to: VHS[0 : 1] = VPWR / 2 (where RL = 25 Ω). Turn-OFF delay time is measured as time between a falling edge of the channel
control signal (IN[0 : 1] = 0) and the associated falling edge of the output voltage up to the instant at which:
VHS[0 : 1] = VPWR / 2 (RL = 25 Ω)
22XS4200
15
NXP Semiconductors
Table 5. Dynamic electrical characteristics (continued)
Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are average
values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
-25
-50
-12
0.0
0.0
0.0
25
50
12
μs
(27)
Output voltage switching characteristics (continued)
Δ t(DLY)
Delay time difference from one channel to the other in Parallel mode
16 V < VPWR < 36 V
SR[1:0] = 00
SR[1:0] = 01
SR[1:0] = 10
tFAULT
Fault detection delay time
–
5.0
8.0
μs
(28)
Output shutdown delay time
–
10
15
μs
(29)
tDETECT
t CSNSVAL_00
Current sense output settling time for SR[1:0] = 00 (medium slew rate)
• 16 V < VPWR < 36 V
0.0
–
200
μs
(30)
t CSNSVAL_01
Current sense output settling time for SR[1:0] = 01(low slew rate)
• 16 V < VPWR < 36 V
0.0
–
315
μs
(30)
t CSNSVAL_10
Current sense output settling time for SR[1:0] = 10 (high slew rate)
• 16 V < VPWR < 36 V
0.0
–
165
μs
(30)
t SYNCVAL_00
SYNC output signal delay for SR[1:0] = 00 (medium SR)
20
–
120
μs
(30)
t SYNCVAL_01
SYNC output signal delay for SR[1:0] = 01 (low SR)
40
–
240
μs
(30)
t SYNCVAL_10
SYNC output signal delay for SR[1:0] = 10 (high SR)
10
–
60
μs
(30)
t SYNREAD_00
Recommended sync_to_read delay SR[1:0] = 00 (medium slew rate)
0.0
–
150
µs
(30)
t SYNREAD_01
Recommended sync_to_read delay SR[1:0] = 01 (low slew rate)
0.0
–
150
µs
(30)
t SYNREAD_10
Recommended sync_to_read delay SR[1:0] = 10 (high slew rate)
0.0
–
150
µs
(30)
Upper overcurrent threshold duration
6.0
12.0
8.6
17.2
11.2
22.4
ms
tOCH1
tOCH2
tOCM1_L
tOCM2_L
Medium overcurrent threshold duration (CONF = 0; Lighting profile)
48
96
67
137
87
178
ms
tOCM1_M
tOCM2_M
Medium overcurrent threshold duration (CONF = 1; DC motor profile)
96
245
137
350
178
455
ms
Notes
27. Rising and falling edge slew rates specified for a 20% to 80% voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and delay).
28. Time required to detect and report the fault to the FSB pin.
29. Time required to switch off the channel after detection of overtemperature (OT), overcurrent (OC), SC or UV error (time measured between start
of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR
30.
Settling time ( = t CSNSVAL_XX), SYNC output signal delay ( = t SYNCVAL_XX) and Read-out delay ( = t SYNREAD_XX) are defined for a stepped load
current (100 mA< I(LOAD)