MC32PF1550A6EP

PF1550 Power management integrated circuit (PMIC) for low power application processors Rev. 7 — 29 September 2021 1 Product data sheet General description The PF1550 is a power management integrated circuit (PMIC) designed specifically for use with i.MX processors on low-power portable, smart wearable and Internet-of-Things (IoT) applications. It is also capable of providing full power solution to i.MX 7ULP, i.MX 6SL, 6UL, 6ULL, and 6SX processors. With three high-efficiency buck converter, three linear regulators, RTC supply, and battery linear charger, the PF1550 can provide power for a complete battery-powered system, including application processors, memory, and system peripherals. 1.1 Features and benefits This section summarizes the PF1550 features: • Input voltage range to PMIC VBUSIN pin via USB bus or AC adapter: 4.1 V to 6.0 V • Buck converters: – SW1, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps – SW2, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps – SW3, 1.0 A; 1.8 V to 3.3 V in 100 mV steps – Soft start – Quiescent current 1.0 μA in ULP mode with light load – Peak efficiency > 90 % – Dynamic voltage scaling on SW1 and SW2 – Modes: forced PWM quasi-fixed frequency mode, adaptive variable-frequency mode – Programmable output voltage, current limit, and soft start • LDO regulators – LDO1, 0.75 V to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode – LDO2, 1.8 V to 3.3 V, 400 mA – LDO3, 0.75 V to 1.5 V/1.8 V to 3.3 V, 300 mA with load switch mode – Quiescent current < 1.5 μA in Low-power mode – Programmable output voltage – Soft start and ramp – Current limit protection PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors • Battery charger – Supports single-cell Lithium Ion/Lithium Polymer batteries – Linear charging (10 mA to 1500 mA input limit) – Up to 6.5 V input operating range – VSYS regulator can withstand transient and DC inputs from 0 V up to +22 V – Programmable charge voltage (3.5 V to 4.44 V) – Programmable charge current (100 mA to 1000 mA) – Programmable charge termination current (5.0 mA to 50 mA) – Integrated 50 mΩ battery isolation MOSFET for operation with no/low battery – Battery supplement mode – Battery discharge overcurrent protection, up to 3.0 A – USB_PHY low dropout linear regulator – Programmable LED driver (status indicator) – JEITA-compliant battery temp sensing and charger control – Key charging parameters can be configured and permanently stored in OTP 2 – I C Control Interface permitting processor control and event detection • LDO/switch supply – RTC supply VSNVS 3.0 V, 2.0 mA – Battery backed memory including coin cell charger • DDR memory reference voltage, VREFDDR, 0.5 V to 0.9 V, 10 mA • OTP (One time programmable) memory for device configuration – User programmable start-up sequence, timing, soft-start, and power-down sequence – Programmable regulator output voltages and charger parameters 2 • I C interface • User programmable Standby, Sleep/Low-power, and Off (REGS_DISABLE) modes • Ambient temperature range −40 °C to 105 °C 1.2 Applications • • • • • • • PF1550 Product data sheet Smart mobile/wearable devices Low-power IoT applications Wireless game controllers Embedded monitoring systems Home automation POS E-Read All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 2 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 2 Application diagram PF1550 Low-power application processor VREFDDR DDR memory DDR memory Interface SW2 Processor ARM core SW1 LDO1 GPS MIPI Processor real-time SOC/GPU SW3 LDO2 SD/MMC/ NAND memory FLASH NAND - NOR interfaces WiFi LDO3 Bluetooth VSNVS SNVS_IN External AMP microphones speakers Audio codec Control signals Parallel control / GPIO I2C communication I2C communication Li-cell charger Sensors Coin cell Mini-USB linear charger USB_PHY Mini-USB connector aaa-023872 Figure 1. Application diagram PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 3 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 2.1 Functional block diagram PF1550 functional block diagram BUCK1 (0.6 V to 1.3875 V, 1.0 A, DVS; 1.1 V to 3.3 V, 1.0 A, no DVS) Linear Li-ion battery charger (22 V surge, power path, 100 mA to 1000 mA charging current) LDO1 (0.75 V to 3.3 V, 300 mA) BUCK2 (0.6 V to 1.3875 V, 1.0 A, DVS; 1.1 V to 3.3 V, 1.0 A, no DVS) Logic and Control I2C/processor interface/ regulator control/ OTP (flexible configuration) BUCK3 (1.8 V to 3.3 V, no DVS) LDO2 (1.8 V to 3.3 V, 400 mA) VSNVS (RTC supply) (3.0 V, 2.0 mA) LDO3 (0.75 V to 3.3 V, 300 mA) DDR voltage reference (VINREFDDR/2, 10 mA) aaa-023873 Figure 2. Functional block diagram PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 4 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors WDI PWRON INTB RESETBMCU ONKEY VDDOTP SDA SCL VDDIO CHGB 2.2 Internal block diagram PF1550 analog core (reference and bias current) SW1FB VCORE LDO SW1IN SW1LX EA and driver PF1550 digital core and state machine SW1 DVS and misc reference VDIG LDO EPAD SW2FB SW2LX EA and driver VSNVS Watchdog timer SW2 DVS and misc reference VDIG coin cell charger OTP memory SW2IN VCORE 32 kHz clock LICELL VSNVS VSYS 16 MHz clock EPAD VBUSIN SW3FB INT2P7 LDO USBPHY LDO SW3IN INT2P7 16 MHz clock / derivative Thermistor monitor THM LDO3OUT LDO3 LDO3IN LDO2OUT Analog reference(s) LDO2 LDO2IN Digital signal(s) VREFDDR VREFDDR divide input by 2 LDO1 LDO1OUT EPAD VBATT LDO1IN EA and driver SW3 and misc reference VINREFDDR SW3LX USBPHY 32 kHz clock / derivative aaa-023874 Figure 3. Internal block diagram 3 Orderable parts The PF1550 is available only with preprogrammed configurations. These preprogrammed devices are identified using the program code from Table 1, which also list the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 85. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 5 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 1. Orderable part variations Part number [1] Temperature (TA) Package Programming options MC32PF1550A0EP 0 - Not programmed MC32PF1550A1EP 1 (Default) MC32PF1550A2EP 2 (i.MX 7ULP with LPDDR3) MC32PF1550A3EP 3 (i.MX 6UL with DDR3L) MC32PF1550A4EP MC32PF1550A5EP [2] 4 (i.MX 7ULP with LPDDR3) −40 °C to 85 °C (for use in consumer applications) 5 (i.MX 6UL with DDR3) MC32PF1550A6EP 6 (i.MX 6ULL with DDR3L) MC32PF1550A7EP 7 (i.MX 6UL with LPDDR2) MC32PF1550A8EP 8 (i.MX 6UL with DDR3L, Edge Sensitive) MC32PF1550A9EP 98ASA00913D, 40-pin QFN 5.0 mm x 5.0 mm with exposed pad MC34PF1550A0EP 9 (i.MX RT1050) 0 - Not programmed MC34PF1550A1EP 1 (Default) MC34PF1550A2EP 2 (i.MX 7ULP with LPDDR3) MC34PF1550A3EP 3 (i.MX 6UL with DDR3L) MC34PF1550A4EP MC34PF1550A5EP −40 °C to 105 °C (for use in industrial applications) [2] 4 (i.MX 7ULP with LPDDR3) 5 (i.MX 6UL with DDR3) MC34PF1550A6EP 6 (i.MX 6ULL with DDR3L) MC34PF1550A7EP 7 (i.MX 6UL with LPDDR2) MC34PF1550A8EP 8 (i.MX 6UL with DDR3L, Edge Sensitive) MC34PF1550A9EP 9 (i.MX RT1050) [1] [2] For tape and reel, add an R2 suffix to the part number. For internal validation only PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 6 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 4 Pinning information 4.1 Pinning CHGB USBPHY INT2P7 VBUSIN VSYS VSYS VBATT VBATT THM LICELL PF1550 40 39 38 37 36 35 34 33 32 31 WDI 1 30 VSNVS SDA 2 29 VLDO1 SCL 3 28 VLDO1IN VDDIO 4 27 SW1FB VDDOTP 5 26 SW1IN PWRON 6 25 SW1LX STANDBY 7 24 VCORE ONKEY 8 23 VDIG INTB 9 22 VINREFDDR RESETBMCU 10 21 VREFDDR EPAD 18 Transparent top view 19 20 VLDO2 17 VLDO2IN 16 SW2IN SW3LX 15 SW2LX VLDO3 14 SW2FB 13 SW3FB 12 SW3IN 11 VLDO3IN (41) aaa-023875 Figure 4. Pinout diagram PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 7 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 4.2 Pin definitions Table 2. Pin description Pin number Pin name 1 WDI Watchdog input from processor 2 SDA SDA when used in I C mode 3 SCL 4 VDDIO 5 VDDOTP 6 PWRON PWRON input 7 STANDBY STANDBY input 8 ONKEY 9 INTB INTB open-drain output 10 RESETBMCU RESETBMCU open-drain output 11 VLDO3IN 12 VLDO3 13 SW3LX 14 SW3IN 15 SW3FB Buck 3 output voltage feedback 16 SW2FB Buck 2 output voltage feedback 17 SW2IN 18 SW2LX 19 VLDO2 20 VLDO2IN 21 VREFDDR 22 VINREFDDR 23 VDIG 24 VCORE 25 SW1LX 26 SW1IN 27 SW1FB 28 VLDO1IN 29 VLDO1 30 VSNVS 31 LICELL 32 THM 33 34 35 36 Block Description 2 2 I/Os SCL when used in I C mode I/O supply voltage Connect to voltage rail between 1.7 V and 3.3 V VDDOTP ONKEY push-button input I/Os LDO3 input supply LDO3 LDO3 output Buck 3 switching node Buck 3 input supply Buck 3 Buck 2 input supply Buck 2 Buck 2 switching node LDO2 output LDO2 LDO2 input supply VREFDDR Product data sheet VREFDDR input supply VCORE regulator output (used within PF1550) Buck 1 switching node Buck 1 input supply Buck 1 Buck 1 feedback input LDO1 input supply LDO1 LDO1 output VSNVS regulator output VSNVS VBATT PF1550 VREFDDR output VDIG regulator output (used within PF1550) IC core Coin cell input CHARGER VSYS Connect to ground in application IC core Thermistor connection Connect thermistor to ground from this pin Battery input Main input voltage to PMIC and output of charger All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 8 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 2. Pin description...continued Pin number Pin name 37 VBUSIN Charger input 38 INT2P7 INT2P7 regulator output (used within PF1550 and as thermistor bias) 39 USBPHY 40 CHGB 41 EPAD 5 Block Description CHARGER USBPHY regulator output Charger LED input connection Connect LED from VSYS to this pin EPAD Exposed pad Connect to ground General product characteristics 5.1 Thermal characteristics Table 3. Thermal ratings Symbol Description (Rating) Min Max Unit −40 −40 105 85 °C −40 125 °C THERMAL RATINGS TA Ambient operating temperature range (industrial) Ambient operating temperature range (consumer) TJ Operating junction temperature range TST Storage temperature range TPPRT [1] −65 150 °C [2] [3] — — °C [4] [5] [6] — Peak package reflow temperature QFN40 THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS RΘJA Junction to ambient thermal resistance, natural convection Four layer board (2s2p) Six layer board (2s4p) Eight layer board (2s6p) RΘJMA Junction to ambient (@200 ft/min) Four layer board (2s2p) RΘJB Junction to board °C/W 27 20.6 17.8 [4] [6] — °C/W 21.4 [7] — 8.8 °C/W RΘJCBOTTOM Junction to case bottom [8] — 1.4 °C/W ΨJT [9] — 0.6 °C/W [1] [2] [3] [4] [5] [6] [7] [8] [9] Junction to package top – Natural convection Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Thermal Protection Thresholds for thermal protection features. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. NXP's package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and moisture sensitivity levels (MSL), go to http://www.nxp.com, search by part number, and enter the core ID to view all orderable parts (for MC33xxxD enter 33xxx), and review parametrics. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 9 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 5.2 Absolute maximum ratings Table 4. Maximum ratings Symbol Description (Rating) Min Max Unit I/O supply voltage. Connect to voltage rail between 1.7 V and 3.3 V. I/Os VDDIO SCL −0.3 3.6 V 2 −0.3 3.6 V 2 SCL when used in I C mode. SCLK when used in SPI mode. SDA SDA when used in I C mode. MISO when used in SPI mode. −0.3 3.6 V RESETBMCU RESETBMCU open-drain output −0.3 3.6 V PWRON PWRON input −0.3 3.6 V STANDBY STANDBY input −0.3 3.6 V ONKEY ONKEY push-button input −0.3 4.8 V INTB INTB open-drain output −0.3 3.6 V WDI Watchdog input from processor −0.3 3.6 V Connect to ground in the application −0.3 10 V SW1IN Buck 1 input supply −0.3 4.8 V SW1LX Buck 1 switching node −0.3 4.8 V SW1FB Buck 1 feedback input −0.3 3.6 V SW2IN Buck 2 input supply −0.3 4.8 V SW2LX Buck 2 switching node −0.3 4.8 V SW2FB Buck 2 output voltage feedback −0.3 3.6 V SW3IN Buck 3 input supply −0.3 4.8 V SW3LX Buck 3 switching node −0.3 4.8 V SW3FB Buck 3 output voltage feedback −0.3 3.6 V VLDO1IN LDO1 input supply −0.3 4.8 V VLDO1 LDO1 output −0.3 3.6 V VLDO2IN LDO2 input supply −0.3 4.8 V VLDO2 LDO2 output −0.3 3.6 V VLDO3IN LDO3 input supply −0.3 4.8 V VLDO3 LDO3 output −0.3 3.6 V VSNVS regulator output −0.3 3.6 V VDDOTP VDDOTP BUCK 1 BUCK 2 BUCK 3 LDO1 LDO2 LDO3 VSNVS VSNVS PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 10 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 4. Maximum ratings...continued Symbol Description (Rating) Min Max Unit LICELL Coin cell input −0.3 3.6 V VBATT Battery input −0.3 4.8 V INT2P7 INT2P7 regulator output (used within PF1550 and as thermistor bias) −0.3 3.6 V THM Thermistor connection. Connect thermistor to ground from this pin. −0.3 3.6 V VBUSIN Charger input −0.3 24 V USBPHY USBPHY regulator output −0.3 5.5 V CHGB Charger LED input connection. Connect LED from VSYS to this pin. −0.3 4.8 V CHARGER INPUT/OUTPUT SUPPLY VINREFDDR VREFDDR input supply −0.3 3.6 V VREFDDR VREFDDR output −0.3 3.6 V VSYS Main input voltage to PMIC and output of charger −0.3 4.8 V VDIG VCOREDIG regulator output (used within PF1550) −0.3 1.65 VCORE VCORE regulator output (used within PF1550) −0.3 1.65 V — — — ±2000 ±750 ±500 V IC CORE ELECTRICAL RATINGS VESD [1] ESD ratings Human body model Charge device model (corner pins) Charge device model (all other pins) [1] Testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM), Robotic (CZAP = 4.0 pF). PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 11 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 5.3 Electrical characteristics 5.3.1 Electrical characteristics – Battery charger All parameters are specified at TA = −40 °C to 105 °C, VBUSIN = 5.0 V, VSYS = 3.7 V, typical external component values, unless otherwise noted. Typical values are characterized at VBUSIN = 5.0 V, VSYS = 3.7 V and 25 °C, unless otherwise noted. Table 5. Global conditions Symbol Parameter Measurement condition Min Typ Max Unit VBUS VBUSIN voltage range Operating voltage VUVLO — VOVLO V VBUS_WITHSTAND VBUSIN maximum withstand voltage rating — — 22 V VBUS_OVLO VBUSIN overvoltage threshold Rising 6.0 6.5 7.0 V VOVLO_HYS VBUSIN overvoltage threshold hysteresis Falling 50 150 250 mV tD-OVLO VBUSIN overvoltage delay 5.0 10 15 µs VUVLO VBUSIN to GND minimum turn on threshold accuracy 3.8 4.0 4.2 V VUVLO-HYS VBUSIN UVLO hysteresis 400 500 600 mV VIN2SYS_50 VBUSIN to VSYS minimum turn VBUS_LIN rising, 50 mV setting 20 on threshold accuracy 50 80 mV VIN2SYS_175 VBUSIN to VSYS minimum turn VBUS_LIN rising, 175 mV on threshold accuracy setting 100 175 250 mV VBUS_LIN_DPM_REG VBUSIN adaptive voltage regulation threshold 4.4 V setting (default) 4.3 4.4 4.5 V VDPM_REG VBUSIN adaptive voltage regulation threshold accuracy Programmable at 3.9 V to 4.6 V −100 — 100 mV Measurement condition Min Typ Max Unit CHARGER INPUTS VBUS rising Table 6. Input currents Symbol Parameter VBUSIN INPUT CURRENT LIMIT ILIM10 Charger input current limit (10 mA settings) 10 mA 6.0 8.5 11 mA ILIM15 Charger input current limit (15 mA settings) 15 mA 10.5 12.75 16 mA ILIM20 Charger input current limit (20 mA settings) 20 mA 14 17 21 mA ILIM25 Charger input current limit (25 mA settings) 25 mA 17.5 21.25 26 mA ILIM30 Charger Input Current Limit (30 mA setting) 30 mA 21 25.5 30 mA ILIM35 Charger input current limit (35 mA settings) 35 mA 24.5 29.75 35 mA ILIM40 Charger input current limit (40 mA settings) 40 mA 28 34 40 mA ILIM45 Charger input current limit (45 mA settings) 45 mA 31.5 38.25 45 mA ILIM50 Charger input current limit (50 mA settings) 50 mA 35 42.5 50 mA ILIM100 Charger input current limit (100 mA settings) 100 mA 85 95 105 mA PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 12 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 6. Input currents...continued Symbol Parameter Measurement condition Min Typ Max Unit ILIM150 Charger input current limit (150 mA settings) 150 mA 125 137.5 160 mA ILIM200 Charger input current limit (200 mA settings) 200 mA 170 190 210 mA ILIM300 Charger input current limit (300 mA setting) 300 mA 260 285 320 mA ILIM400 Charger input current limit (400 mA settings) 400 mA 345 380 425 mA ILIM500 Charger input current limit (500 mA settings) 500 mA 430 475 530 mA ILIM600 Charger input current limit (600 mA settings) 600 mA 520 570 640 mA ILIM700 Charger input current limit (700 mA settings) 700 mA 610 665 750 mA ILIM800 Charger input current limit (800 mA settings) 800 mA 690 760 850 mA ILIM900 Charger input current limit (900 mA settings) 900 mA 780 855 950 mA ILIM1000 Charger input current limit (1000 1000 mA mA settings) 855 950 1100 mA ILIM1500 Charger input current limit (1500 1500 mA mA settings) 1260 1400 1700 mA RINSD Input self-discharge resistance 18 30 42 kΩ IBATTLEAK Leakage current Leakage current from VBATT to VBUSIN. VBATT = 4.2 V, BATFET closed, VBUSIN = 0 V. Current measured into VBATT pin at 25 °C 0 — 5.0 µA IQ_CHARGER Charger quiescent current (BATFET enabled, normal mode) 25 °C only; charger in CC state; ICC = 100 mA 0 2.5 5.0 mA IQ_CHARGER_LQM Charger quiescent current (low power mode, charging enabled, 10 mA to 50 mA input current limit setting, VBATT > 2.8 V and LED driver OFF) 25 °C only; charger in CC state 0 1.5 3.0 mA TSSVBUS_LIN Soft start time (VBUSIN = 5.0 V, time between input LDO enabled and VSYS going to 90 % of regulation No input current limitation event, — measured in Normal mode — 30 ms Table 7. Internal 2.7 V Regulator (INT2P7) Symbol Parameter Min Typ Max Unit VGDRV Output voltage Measurement condition 2.6 2.7 2.8 V IGDRV Output current 5.0 — — mA VDO(GDRV) Dropout voltage 0 — 800 mV Min Typ Max Unit 100 250 550 mΩ 50 75 120 mΩ 0 0.2 10 µA Table 8. Switch impedances and leakage currents Symbol Parameter RVBUS_LIN2SYS VBUSIN to VSYS resistance RBATFET_QFN VBATT to VSYS resistance ISYS VSYS leakage current PF1550 Product data sheet Measurement condition VSYS = 0 V, VBATT = 4.2 V, SHIP mode All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 13 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 8. Switch impedances and leakage currents...continued Symbol Parameter Measurement condition Min Typ Max Unit IBATT_OC VBATT reverse ILIM quiescent current when VBUSIN = 0 V VBUSIN = 0 V, VSYS = VBATT = 4.2 V, BATFET enabled, battery overcurrent enabled — — 100 µA Min Table 9. Linear transients Symbol Parameter Measurement condition Typ Max Unit VPK-PK Load transient peak-to-peak VBUSIN = 5.0 V, VBATT = 3.6 V, 10 ICHG = 500 mA, VSYS load step 1.0 A/µs 400 850 mV VOV_SHT Load transient overshoot VBUSIN = 5.0 V, VBATT = 3.6 V, 0 ICHG = 500 mA, VSYS load step 1.0 A/µs 200 500 mV VUND_SHT Load transient undershoot VBUSIN = 5.0 V, VBATT = 3.6 V, 0 ICHG = 500 mA, VSYS load step 1.0 A/µs 200 500 mV Table 10. Charger characteristics Symbol Parameter Measurement condition Min Typ Max Unit VCHGCV_RANGE CHGCV output voltage range See register map for constant voltage programmable range 3.5 — 4.44 V CVACC CHGCV output accuracy in normal charging — — ±1 % VSYSMIN0 VSYS output voltage (3.5 V option) VSYSMIN = 0x00 (3.5 V option) 3.395 3.5 3.605 V VSYSMIN1 VSYS output voltage (3.7 V option) VSYSMIN = 0x01 (3.7 V option) 3.589 3.7 3.811 V VSYSMIN2 VSYS output voltage (4.3 V option) VSYSMIN = 0x02 (4.3 V option) 4.171 4.3 4.429 V VSYSMINLOOP0 VSYSMIN loop threshold (3.5 V option) 3.0 3.2 3.39 V VSYSMINLOOP1 VSYSMIN loop threshold (3.7 V option) 3.2 3.4 3.585 V VSYSMINLOOP2 VSYSMIN loop threshold (4.3 V option) 3.83 4.0 4.17 V IFC Output current range 100 — 1000 mA IFCACC1 Output current accuracy −10 — 10 % IEOC Charger IEOC range 5.0 — 50 mA tDB(IEOC) Debounce time for charge termination 20 32 44 ms IEOC_ACC_5mA Charger IEOC accuracy (5.0 mA IEOC = 5 mA settings) 1.0 5.0 12 mA IEOC_ACC_10mA Charger IEOC accuracy (10 mA settings) IEOC = 10 mA 4.0 10 16 mA IEOC_ACC_50mA Charger IEOC accuracy (50 mA setting) IEOC = 50 mA 40 50 60 mA VPRECHG Precharge threshold VBATT rising 2.7 2.8 2.9 V VPRECHG_HYS Precharge threshold hysteresis 50 100 150 mV IPRECHG Precharge current 30 45 60 mA IPRECHG.LPM Charging current in LPM and 2.8 V < VBATT < 3.1 V 0.75 1.0 1.25 mA PF1550 Product data sheet Constant current programmable range CHG_CC[4:0] All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 14 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 10. Charger characteristics...continued Symbol Parameter Measurement condition Min Typ Max Unit VRESTART Charger restart threshold (100 mV settings) VBATT below CHGCV[5:0] 50 100 150 mV VRESTART Charger restart threshold (150 mV setting) VBATT below CHGCV[5:0] 100 150 200 mV VRESTART Charger restart threshold (200 mV settings) VBATT below CHGCV[5:0] 150 200 250 mV tDB(VRCH) Debounce time on VRESTART 20 32 44 ms VBATOV BATTOVP range CHGCV x 1.025 CHGCV x 1.05 CHGCV x 1.075 V VBATOV_HYS BATTOVP hysteresis VBATT falling from BATTOVP CHGCV x 0.015 CHGCV x 0.025 CHGCV x 0.035 V Table 11. Power-path management Symbol Parameter Measurement condition Min Typ Max Unit VSPLM Supplement mode voltage threshold Entering supplement mode when VSYS < VBATT 10 40 75 mV Measurement condition Min Typ Max Unit Table 12. Watchdog timer Symbol Parameter tWD Watchdog timer period — 80 — s tWDACC Watchdog timer accuracy −20 0 20 % Table 13. Charger timer Symbol Parameter Measurement condition Min Typ Max Unit tPRECHG Precharge time (fixed 45 mA) Applies to low battery prequalification mode, 500 mA settings — 30 — min tFC Fast charge constant current and constant voltage time Adjustable from 2 to 14 in 2-hour — steps 4.0 — hrs tEOC End-of-charge time Adjustable from 0 to 70 in 10 min — steps 30 — min tacc Timer accuracy All timers associated with the charger block −20 — 20 % tSCIDG Charger state change interrupt delay 0 1.0 2.0 ms tINLIM VBUS_VOK delay from VDIG ready following VBUSIN insertion (see charger startup diagram) 0 100 200 µs Table 14. Battery overcurrent protection Symbol Parameter Measurement condition Min Typ Max Unit tBOVCR Battery overcurrent debounce time Response time to BATFET open (OTP option) 12.8 16 19.2 ms tBOVCRI Battery overcurrent interrupt debounce time Response time to generate interrupt 2.4 3.0 3.6 ms IBOVCR Battery overcurrent threshold range Programmable from 2.0 A to 4.0 A in three steps 2.0 — 4.0 A PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 15 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 14. Battery overcurrent protection...continued Symbol Parameter IBOVCRACC_2A Measurement condition Min Typ Max Unit Battery overcurrent threshold accuracy (2.2 A setting) 1.0 2.2 3.2 A IBOVCRACC_3A Battery overcurrent threshold accuracy (2.8 A setting) 1.6 2.8 4 A IBOVCRACC_4A Battery overcurrent threshold accuracy (3.2 A setting) 2.0 3.2 4.6 A RSYSDISCH SYS self-discharge resistor in SHIP mode 480 600 720 Ω Table 15. Thermal regulation Symbol Parameter Min Typ Max Unit TREG Thermal regulation threshold (80 Temperature at which charge °C setting) current begins to decrease Measurement condition — 80 — °C TREG Thermal regulation threshold (95 Temperature at which charge °C Setting) current begins to decrease — 95 — °C TREG Thermal regulation threshold (110 °C setting) Temperature at which charge current begins to decrease — 110 — °C Measurement condition Min Typ Max Unit Table 16. Battery thermistor monitor Symbol Parameter VNTECREF NTECREF voltage 2.6 2.7 2.8 V VTN10C Thermistor threshold (−10 °C settings) −10 °C 0.79*VNTECREF 0.82*VNTECREF 0.85*VNTECREF V VT0C Thermistor threshold (0 °C settings) 0 °C 0.71*VNTECREF 0.74*VNTECREF 0.77*VNTECREF V VT10C Thermistor threshold (10 °C settings) 10 °C 0.62*VNTECREF 0.65*VNTECREF 0.68*VNTECREF V VT45C Thermistor threshold (45 °C settings) 45 °C 0.31*VNTECREF 0.33*VNTECREF 0.35*VNTECREF V VT55C Thermistor threshold (55 °C settings) 55 °C 0.25*VNTECREF 0.26*VNTECREF 0.27*VNTECREF V VT60C Thermistor threshold (60 °C settings) 60 °C 0.22*VNTECREF 0.23*VNTECREF 0.24*VNTECREF V VT_HYS Battery temperature hysteresis All settings 0.5 2.5 5.0 °C Table 17. USBPHY LDO Symbol Parameter Measurement condition Min Typ Max Unit VUSB_PHY Output voltage IOUT = 10 mA; 3.3 V and 4.9 V settings. VBUSIN = 5.5 V −5.0 — 5.0 % IUSB_PHY Maximum output current 60 — — mA USBRDIS Internal discharge resistance 500 1000 1500 Ω USBCAPSTA Output capacitor for stable operation 0.7 1.0 2.2 µF IQUSB Quiescent supply current — 35 — µA USBPHYLDREG DC load regulation VBUSIN = 5.5 V, 30 µA < IOUT < 60 mA 0 5.0 13 mV USBPHYDO Dropout voltage VBUSIN = 5.0 V, IOUT = 60 mA — 200 350 mV USBPHYILIM Output current limit 65 150 200 mA PF1550 Product data sheet 0 µA < IOUT < 60 mA, MAX ESR = 10 mΩ All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 16 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 17. USBPHY LDO...continued Symbol Parameter Measurement condition Min Typ Max Unit PSRRUSB_PHY PSRR VBUSIN = 5.5 V, COUT = 1.0 µF 55 60 75 dB Measurement condition Min Typ Max Unit Table 18. LED characteristics Symbol Parameter VLED LED input voltage operating range (anode to ground) 3.5 — VSYS V VCHGB_IN CHGB input voltage operating range, LED driver enabled 1.0 — 3.0 V ILED LED current accuracy 4.0 6.0 8 mA TON LED duty cycle range Programmable from 10 % to 100 10 % duty cycle in 10 % steps — 100 % TLEDRUP LED ramp up Settings depend on duty cycle 50 — 500 ms TLEDRDN LED ramp down Settings depend on duty cycle 50 — 500 ms FLED LED frequency Programmable from 0.5 Hz to 256 Hz 0.5 — 256 Hz 5.3.2 Electrical characteristics – SW1 and SW2 All parameters are specified at TA = −40 °C to 105 °C, VSYS = VSWxIN = 2.5 V to 4.5 V, VSWx = 1.2 V, ISWx = 200 mA, typical external component values, fSWx = 2.0 MHz, unless otherwise noted. Typical values are characterized at VSYS = VSWxIN = 3.6 V, VSWx = 1.1 V, ISWx = 100 mA, and 25 °C, unless otherwise noted. Table 19. SW1 and SW2 electrical characteristics Symbol Parameter Min Typ Max Unit VSWxIN Operating input voltage 2.5 — 4.5 V ISWx Rated output current 1000 — — mA VSWx Output voltage accuracy DVS enabled mode (OTP_SWx_DVS_SEL = 0) Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A 0.6 V ≤ VSWx ≤ 1.0 V −15 — 15 mV VSWx Output voltage accuracy DVS enabled mode (OTP_SWx_DVS_SEL = 0) Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A 1.0 V < VSWx ≤ 1.3875 V −2.0 — 2.0 % VSWx Output voltage accuracy DVS enabled mode (OTP_SWx_DVS_SEL = 0) Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A 0.6 V ≤ VSWx ≤ 1.0 V −30 — 30 mV VSWx Output voltage accuracy DVS enabled mode (OTP_SWx_DVS_SEL = 0) Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A 1.0 V < VSWx ≤ 1.3875 V −3.0 — 3.0 % VSWx Output voltage accuracy DVS disabled mode (OTP_SWx_DVS_SEL = 1) Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A 1.1 V ≤ VSWx ≤ 1.5 V −45 — 45 mV VSWx Output voltage accuracy DVS disabled mode (OTP_SWx_DVS_SEL = 1) Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A 1.8 V ≤ VSWx ≤ 3.3 V −3.0 — 3.0 % PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 17 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 19. SW1 and SW2 electrical characteristics...continued Symbol Parameter Min Typ Max Unit VSWx Output voltage accuracy DVS disabled mode (OTP_SWx_DVS_SEL = 1) Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A 1.1 V < VSWx ≤ 1.5 V −55 — 55 mV VSWx Output voltage accuracy DVS disabled mode (OTP_SWx_DVS_SEL = 1) Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A 1.8 V ≤ VSWx ≤ 3.3 V −4.0 — 4.0 % ΔVSWx Output ripple — 5.0 — mV SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ LP/ ULP mode, 1.2 V, 1.0 mA — 88 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 50 mA — 90 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 150 mA — 92 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 400 mA — 89 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 1000 mA — 83 — % ISWxLIMH Current limiter peak (high-side MOSFET) current detection SWxILIM[1:0] = 00 SWxILIM[1:0] = 01 SWxILIM[1:0] = 10 SWxILIM[1:0] = 11 0.7 0.8 1.0 1.4 1.0 1.2 1.5 2.0 1.3 1.6 2.0 2.6 ISWxLIML Current limiter low-side MOSFET current detection (sinking current) 0.7 1.0 1.3 ISWxQ Quiescent current (at 25 °C) Low-power mode with DVS disabled (OTP_SWx_DVS_SEL = 1) — 1.0 — ISWxQ Quiescent current (at 25 °C) Low-power mode with DVS enabled (OTP_SWx_DVS_SEL = 0) — 6.0 — ISWxQ Quiescent current (at 25 °C) Normal power mode with DVS disabled (OTP_SWx_DVS_SEL = 1) — 5.5 — ISWxQ Quiescent current (at 25 °C) Normal power mode with DVS enabled (OTP_SWx_DVS_SEL = 0) — 10 — VSWxOSH Startup overshoot (Normal mode) ISWx = 0 mA DVS speed = 12.5 mV/4 µs, VSYS = VSWxIN = 3.6 V, VSWx = 1.35 V — — 25 mV tONSWx Turn on time 10 % to 90 % of end value DVS speed = 12.5 mV/4 µs, VSYS = VSWxIN = 3.6 V, VSWx = 1.35 V — — 500 µs VSWxLOTR Transient load regulation (Normal power mode) Transient load = 50 mA to 250 mA, di/dt = 200 mA/μs Overshoot Undershoot — — 25 25 — — RONSWxP SWx P-MOSFET RDS(on) at VSWxIN = 3.6 V — 200 — mΩ RONSWxN SWx N-MOSFET RDS(on) at VSWxIN = 3.6 V — 150 — mΩ RSWxDIS Turn off discharge resistance — 500 — Ω PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 A A µA µA µA µA mV © NXP B.V. 2021. All rights reserved. 18 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 5.3.3 Electrical characteristics – SW3 All parameters are specified at TA = −40 °C to 105 °C, VSYS = VSW3IN = 2.5 V to 4.5 V, VSW3 = 1.8 V, ISW3 = 200 mA, typical external component values, fSW3 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VSYS = VSW3IN = 3.6 V, VSW3 = 1.8 V, ISW3 = 200 mA, and 25 °C, unless otherwise noted. Table 20. SW3 electrical characteristics Symbol Parameter Min Typ Max Unit VSW3IN Operating input voltage 2.5 — 4.5 V VSW3 Output voltage accuracy (all voltage settings) Normal power mode, 2.5 V < VSW3IN < 4.5 V, 0 < ISW3 < 1.0 A −2.0 — 2.0 VSW3 Output voltage accuracy (all voltage settings) Low-power mode, 2.5 V < VSW3IN < 4.5 V, 0 < ISW3 < 0.1 A −3.0 — 3.0 ΔVSW3 Output ripple — 5.0 — SW3EFF Efficiency VSW3IN = 3.6 V, LSW3 = 1.0 µH, DCR = 50 mΩ LP/ ULP Mode, 1.8 V, 1.0 mA — 88 — SW3EFF Efficiency VSW3IN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.8 V, 50 mA — 90 — SW3EFF Efficiency VSW3IN = 3.6 V, LSWx = 1.0 mH, DCR = 50 mΩ Normal power mode, 1.8 V, 100 mA — 91 — SW3EFF Efficiency VSW3IN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.8 V, 400 mA — 92 — SW3EFF Efficiency VSW3IN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.8 V, 1000 mA — 83 — % % mV % % % % % ISW3LIMH Current limiter peak (high-side MOSFET) current detection SW3ILIM[1:0] = 00 SW3ILIM[1:0] = 01 SW3ILIM[1:0] = 10 SW3ILIM[1:0] = 11 0.7 0.8 1.0 1.4 1.0 1.2 1.5 2.0 1.3 1.6 2.0 2.6 ISW3LIML Current limiter low-side MOSFET current detection (sinking current) 0.7 1.0 1.3 ISW3Q Quiescent current (at 25 °C) Low-power mode — 1.0 — VSW3OSH Start-up overshoot (Normal mode) ISW3 = 0 mA VSYS = VSW3IN = 3.6 V, VSW3 = 1.8 V — — 50 mV tONSW3 Turn on time 10 % to 90 % of end value VSYS = VSW3IN = 3.6 V, VSW3 = 1.8 V — — 500 µs VSW3LOTR Transient load regulation (Normal power mode) Transient load = 50 mA to 250 mA, di/dt = 200 mA/μs Overshoot Undershoot — — 50 50 — — RONSW3N SW3 N-MOSFET RDS(on) at VSW3IN = 3.6 V — 150 — mΩ RONSW3P SW3 P-MOSFET RDS(on) at VSW3IN = 3.6 V — 200 — mΩ RSW3DIS Turn off discharge resistance — 300 — Ω PF1550 Product data sheet A A µA mV All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 19 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 5.3.4 Electrical characteristics – LDO1 All parameters are specified at TA = −40 °C to 105 °C, VSYS = 2.5 V to 4.5 V, VLDOIN1 = 3.6 V, VLDO1[4:0] = 11111, ILDO1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VSYS = 3.6 V, VLDOIN1 = 3.6 V, VLDO1[4:0] = 11111, ILDO1 = 10 mA, and 25 °C, unless otherwise noted. Table 21. LDO1 electrical characteristics Symbol Parameter Min Typ Max Unit VLDO1IN Operating input voltage VLDO1 + 250 mV ≤ VSYS ≤ 4.5 V 1.0 — 4.5 VLDO1NOM Nominal output voltage — See Table 41 — V ILDO1MAX Rated output load current, Normal mode 300 — — mA ILDO1MAXLPM Rated output load current, Low-power mode 10 — — mA VLDO1TOL Output voltage tolerance, Normal mode VLDO1INMIN < VLDO1IN < 4.5 V, 0 mA < ILDO1 ≤ 300 mA 0.8 V ≤ VLDO1 < 1.8 V 1.8 V ≤ VLDO1 ≤ 3.3 V VLDO1INMIN < VLDO1IN < 4.5 V, 0 mA < ILDO1 < 10 mA (Low-power mode) V % −2.5 −2.5 −4.0 — — — 2.5 2.5 4.0 ILDO1LIM Current limit ILDO1 when VLDO1 is forced to VLDO1NOM/2 320 — 1000 mA ILDO1OCP LDO1FAULTI threshold (also used to disable LDO1 when REGSCPEN = 1) 320 — 1000 mA ILDO1Q Quiescent current (at 25 °C) No load, change in IVSYS and IVLDOIN1 When LDO1 enabled in Normal mode When LDO1 enabled in Low-power mode — — 17 2.5 — — RDSON_QFN_LDO1 Dropout on resistance — — 350 PSRRLDO1 PSRR ILDO1 = 150 mA, 20 Hz to 20 kHz VLDO1 = 3.30 V, VLDO1IN = 3.8 V, VSYS = 4.2 V — 56 — TRVLDO1 Turn on time 10 % to 90 % of end value VLDO1INMIN < VLDO1IN ≤ 4.5 V, ILDO1 = 0.0 mA — 200 500 RLDO1DIS Turn off discharge resistance — 250 — LDO1OUTOSHT Start-up overshoot (% of final value) VLDO1INMIN < VLDO1IN ≤ 4.5 V, ILDO1 = 0.0 mA — 1.0 2.0 VLDO1LOTR Transient load response VLDO1INMIN < VLDO1IN ≤ 4.5 V, ILDO1 = 10 mA to 200 mA in 10 μs Overshoot Undershoot µA mΩ dB µs Ω % mV — — 50 50 — — 5.3.5 Electrical characteristics – LDO2 All parameters are specified at TA = −40 °C to 105 °C, VSYS = 3.6 V, VLDOIN2 = 3.6 V, VLDO2[3:0] = 1111, ILDO2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VSYS = 3.6 V, VLDOIN2 = 3.6 V, VLDO2[3:0] = 1111, ILDO2 = 10 mA, and 25 °C, unless otherwise noted. Table 22. LDO2 electrical characteristics Symbol Parameter Min Typ Max VLDO2IN Operating input voltage 1.8 V ≤ VLDO2NOM ≤ 2.5 V 2.6 V ≤ VLDO2NOM ≤ 3.3 V 2.8 VLDO2NOM + 0.250 – – 4.5 4.5 PF1550 Product data sheet Unit V All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 20 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 22. LDO2 electrical characteristics...continued Symbol Parameter Min Typ Max Unit VLDO2NOM Nominal output voltage — See Table 43 — V ILDO2MAX Rated output load current, Normal mode 400 — — mA ILDO2MAXLPM Rated output load current, Low-power mode 10 — — mA VLDO2TOL Output voltage tolerance VLDO2INMIN < VLDO2IN < 4.5 V 10.0 mA ≤ ILDO2 < 400 mA 0.0 mA < ILDO2 < 10 mA (Low-power mode) % −2.0 −4.0 — — 2.0 4.0 450 750 1050 mA — 1050 mA ILDO2LIM Current limit ILDO2 when VLDO2 is forced to VLDO2NOM/2 ILDO2OCP LDO2FAULTI threshold (also used to disable LDO2 when 450 REGSCPEN = 1) ILDO2Q Quiescent Current (25 °C) No load, change in IVSYS and IVLDO2IN When VLDO2 enabled in Normal mode When VLDO2 enabled in Low-power mode — — 15 1.5 — — RDSON_QFN_LDO2 Dropout on resistance — — 300 PSRRVLDO2 PSRR ILDO2 = 200 mA, 20 Hz to 20 kHz VLDO2 = 3.30 V, VLDO2IN = 3.9 V, VSYS = 4.2 V — 60 — tONLDO2 Turn on time 10 % to 90 % of end value VLDO2INMIN < VLDO2IN ≤ 4.5 V, ILDO2 = 0.0 mA — 200 500 µs RLDO2DIS Turn off discharge resistance — 250 — Ω LDO2OUTOSHT Start-up overshoot (% of final value) VLDO2INMIN < VLDO2IN ≤ 4.5 V, ILDO2 = 0.0 mA — 1.0 2.0 % VLDO2LOTR Transient load response VLDO2INMIN < VLDO2IN ≤ 4.5 V, ILDO2 = 10 mA to 100 mA in 10 μs Overshoot — Undershoot — µA mΩ dB mV 50 50 — — 5.3.6 Electrical characteristics – LDO3 All parameters are specified at TA = −40 °C to 105 °C, VSYS = 2.5 V to 4.5 V, VLDOIN3 = 3.6 V, VLDO3[4:0] = 11111, ILDO3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VSYS = 3.6 V, VLDOIN3 = 3.6 V, VLDO3[4:0] = 11111, ILDO3 = 10 mA, and 25 °C, unless otherwise noted. Table 23. LDO3 electrical characteristics Symbol Parameter Min Typ Max Unit VLDO3IN Operating input voltage VLDO3 + 250 mV ≤ VSYS ≤ 4.5 V 1.0 — 4.5 V VLDO3NOM Nominal output voltage — See Table 41 — V ILDO3MAX Rated output load current, Normal mode 300 — — mA ILDO3MAXLPM Rated output load current, Low-power mode 10 — — mA VLDO3TOL Output voltage tolerance, Normal mode VLDO3INMIN < VLDO3IN < 4.5 V, 0 mA < ILDO3 < 300 mA 0.8 V ≤ VLDO3 < 1.8 V 1.8 V ≤ VLDO3 ≤ 3.3 V VLDO3INMIN < VLDO3IN < 4.5 V, 0 mA < ILDO3 < 10 mA (Low-power mode) ILDO3LIM PF1550 Product data sheet Current limit ILDO3 when VLDO3 is forced to VLDO3NOM/2 % −2.5 −2.5 −4.0 — — — 2.5 2.5 4.0 320 — 1000 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 mA © NXP B.V. 2021. All rights reserved. 21 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 23. LDO3 electrical characteristics...continued Symbol Parameter Min Typ Max Unit ILDO3OCP LDO3FAULTI threshold (also used to disable LDO3 when 320 REGSCPEN = 1) — 1000 mA ILDO3Q Quiescent current (at 25 °C) No load, change in IVSYS and IVLDOIN3 When LDO3 enabled in Normal mode When LDO3 enabled in Low-power mode — — 17 2.5 — — RDSON_QFN_LDO3 Dropout on resistance — — 350 PSRRLDO3 PSRR ILDO3 = 150 mA, 20 Hz to 20 kHz VLDO3 = 3.30 V, VLDO3IN = 3.8 V, VSYS = 4.2 V — 56 — TRVLDO3 Turn on time 10 % to 90 % of end value VLDO3INMIN < VLDO3IN < 4.5 V, ILDO3 = 0.0 mA — 200 500 RLDO3DIS Turn off discharge resistance — 250 — LDO3OUTOSHT Start-up overshoot (% of final value) VLDO3INMIN < VLDO3IN ≤ 4.5 V, ILDO3 = 0.0 mA — 1.0 2.0 VLDO3LOTR Transient load response VLDO3INMIN < VLDO3IN ≤ 4.5 V, ILDO3 = 10 mA to 100 mA in 10 μs Overshoot — Undershoot — µA mΩ dB µs Ω % mV 50 50 — — 5.3.7 Electrical characteristics – VREFDDR TA = −40 to 105 °C, VSYS = 2.5 V to 4.5 V, IREFDDR = 0.0 mA, VINREFDDR = 1.35 V and typical external component values, unless otherwise noted. Typical values are characterized at VSYS = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.35 V, and 25 °C, unless otherwise noted. Table 24. VREFDDR electrical characteristics Symbol Parameter Min Typ Max Unit VINREFDDR Operating input voltage range 0.9 — 1.8 V VREFDDR Output voltage, 0.9 V < VINREFDDR < 1.8 V, 0 mA < IREFDDR < 10 mA — VINREFDDR/2 — V VREFDDRTOL Output voltage tolerance, as a percentage of VINREFDDR, 1.2 V 49.25 < VINREFDDR < 1.65 V, 0 mA < IREFDDR < 10 mA 50 50.75 % IREFDDRQ Quiescent current (at 25 °C) — 1.1 — µA IREFDDRLM Current limit, IREFDDR when VREFDDR is forced to VINREFDDR/4 10.5 24 38 mA tONREFDDR Turn on time, 10 % to 90 % of end value, VINREFDDR = 1.2 V to — 1.65 V, IREFDDR = 0.0 mA — 100 µs 5.3.8 Electrical characteristics – VSNVS All parameters are specified at TA = −40 °C to 105 °C, VSYS = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VSYS = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted. Table 25. VSNVS electrical characteristics Symbol Parameter Min Typ Max VSNVSIN Operating input voltage Valid coin cell range Valid VSYS 1.8 2.45 — — 3.3 4.5 PF1550 Product data sheet Unit V All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 22 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 25. VSNVS electrical characteristics...continued Symbol Parameter Min Typ Max Unit ISNVS Operating load current VSNVSINMIN < VSNVSIN < VSNVSINMAX 2000 — — µA VTL1 VSYS threshold (VSYS powered to coin cell powered) — UVDET failing — V VTH1 VSYS threshold (coin cell powered to VSYS powered) — UVDET rising — V VSNVS Output voltage (when running from VSYS) 0 µA < ISNVS < 2000 µA −7.0 % 3.0 7.0 % V Output voltage (when running from LICELL) 0 µA < ISNVS < 2000 µA 2.84 V < VCOIN < 3.3 V VCOIN − 0.20 — — VSNVSDROP Dropout voltage VSYS = 2.9 V ISNVS = 2000 µA — — 220 ISNVSLIM Current limit VSYS > VTH1 5200 — 24000 VSNVSTON Turn on time (load capacitor, 0.47 µF) 10 % to 90 % of final value VSNVS VCOIN = 0.0 V, ISNVS = 0 µA — — 3.0 VSNVSOSH Start-up overshoot ISNVS = 5.0 µA dVSYS/dt = 50 mV/µs — 40 70 RDSONSNVS Internal switch RDS(on) VCOIN = 2.6 V — — 100 mV µA ms mV Ω 5.3.9 Electrical characteristics – IC level bias currents All parameters are specified at 25 °C, VSYS = 3.6 V, VBUSIN = 0 V, typical external component values, unless otherwise noted. Typical values are characterized at VSYS = 3.6 V, VSNVS = 3.0 V, and 25 °C, unless otherwise noted. Table 26. IC level electrical characteristics Mode PF1550 conditions System conditions Typ Max Unit Coin cell VSNVS from LICELL All other blocks off VSYS = 0.0 V No load on VSNVS 1.5 4.0 µA CORE_OFF VSNVS from VSYS Wake-up from ONKEY active All other blocks off VSYS > UVDET No load on VSNVS, PMIC able to wake up 1.5 4.0 µA Sleep VSNVS from VSYS Wake-up from PWRON active Trimmed reference active DDR I/O rail in Low-power mode VREFDDR disabled No load on VSNVS. DDR memories in selfrefresh. 12.5 25 µA Standby/Suspend VSNVS from either VSYS or LICELL SW1 in ultra Low-power mode SW2 in ultra Low-power mode SW3 in ultra Low-power mode Trimmed reference active VLDO1 is disabled VLDO2 enabled in Low-power mode VLDO3 enabled in Low-power mode VREFDDR enabled No load on VSNVS. Processor enabled in Low-power mode. 23 46 µA PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 23 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 26. IC level electrical characteristics...continued Mode PF1550 conditions System conditions Typ Max Unit REGS_DISABLE VSNVS from VSYS Wake-up from ONKEY active Most other blocks off VSYS > UVDET No load on VSNVS, PMIC able to wake up 14 20 µA SHIP BATFET open, no LICELL connected VSYS = 0 V, only awake from ONKEY enabled 0.45 1.0 µA 6 Detailed description The PF1550 PMIC features three high efficiency low quiescent current buck regulators, three LDO regulators, a DDR voltage reference to supply voltages for the application processor and peripheral devices. Additionally, PF1550 incorporates a single cell Li-ion linear battery charger with a USBPHY regulator. The buck regulators provide the supply to processor cores and to other low voltage circuits such as I/O and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for the processor cores for power optimization. The three LDO regulators are general purpose to power various processor rails, system connectivity devices and/or peripherals. Depending on the system power configuration, the general purpose LDO regulators can be directly supplied from the main system supply VSYS or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN. A specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operation. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS (Secure Non-Volatile Storage) /RTC (Real Time Clock) circuitry on the processor. VSNVS is powered from VSYS or from a coin cell. To accommodate applications that do not include Li-ion battery, the PF1550 battery charger regulates the input voltage at VBUSIN pin down to maximum of 4.5 V at VSYS through the power path circuit. Table 27. Voltage regulators PF1550 Product data sheet Supply Output voltage (V) Programming step size (mV) Load current (mA) SW1 / SW2 0.60 to 1.3875 / 1.1 to 3.3 12.5 / variable 1000 SW3 1.80 to 3.30 100 1000 LDO1 0.75 to 1.50 1.80 to 3.30 50 100 300 LDO2 1.80 to 3.30 100 400 LDO3 0.75 to 1.50 1.80 to 3.30 50 100 300 USBPHY 3.3 or 4.9 — 60 VSNVS 3.0 N/A 2 VREFDDR 0.5*VINREFDDR N/A 10 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 24 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 6.1 Buck regulators The PF1550 features three high-efficiency buck regulators with internal compensation. Each buck regulator is capable of meeting optimum power efficiency operation using reduced power variable-frequency pulse skip switching scheme at light loads as well as operating in forced PWM quasi-fixed frequency switching mode at higher loads. The switching regulator controller combines the advantages of hysteretic and voltage mode control which provides outstanding load regulation and transient response, low output ripple voltage, and seamless transition between pulse-skip mode and Active Quasifixed frequency switching mode. The control circuitry includes an AC loop which senses the output voltage (at SWxFB pin) and directly feeds it to a fast comparator stage. This comparator sets the switching frequency, which is almost constant for steady state operating conditions. It also provides immediate response to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The transition into and out of low-power pulse-skip switching mode takes place automatically according to the load current to maintain optimum power efficiency. Additionally, further power savings through cutting the buck circuitry quiescent current can be achieved by activating a Low-power mode 2 upon entering either STANDBY or SLEEP PMIC power mode or as commanded via I C control bits. In SW1 and SW2. An OTP option enables or disables DVS in the regulators. When DVS is disabled and the low-power bit is set, the regulator enters an Ultra Low Power (ULP) mode that cuts the operating quiescent current even, in order to reach extremely low standby power levels needed for ultra low power processors such as that from Kinetis K and L series. As indicated above, the buck controller supports PWM (Pulse Width Modulation) mode for medium and high load conditions and low-power variable-frequency pulse skip mode at light loads. During high current mode, it operates in continuous conduction and the switching frequency is up to 2.0 MHz with a controlled on-time variation depending on the input voltage and output voltage. If the load current decreases, the converter seamlessly enters the pulse-skip mode to cut the operating quiescent current and maintain high efficiency down to very light loads. In pulse-skip mode, the switching frequency varies linearly with the load current. Since the controller supports both power modes within one single building block, the transition from normal power mode to lower power pulse-skip mode and vice versa is seamless without dramatic effects on the output voltage. In the adopted pulse-skip scheme, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a non-switching (pause) period where most of the internal circuits are shut down to achieve a lowest quiescent current. During this time, the load current is supported by the output capacitor. The duration of the pause period depends on the load current and the inductor peak current. 6.2 SW1 and SW2 detailed description SW1 and SW2 are identical buck regulators designed to carry a nominal load current of 1.0 A. Detailed characteristics and features of SW1 and SW2 are described in this section. Being identical, reference is made only to SWx though the same specifications apply to SW1 and SW2. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 25 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 6.2.1 SWx dynamic voltage scaling description SWx integrates an optional DVS circuit that is enabled via OTP. To reduce overall power consumption, when DVS is enabled SWx output voltage can be varied depending on the mode or activity level of the processor. • Normal operation: 2 The output voltage is selected by I C bits SWx_VOLT[5:0]. A voltage transition initiated 2 2 by I C is governed by the SWx_DVSSPEED I C bit as shown in Table 28. • Standby mode: 2 The output voltage can be selected by I C bits SWx_STBY_VOLT[5:0]. Voltage 2 transitions initiated by a Standby event are governed by the SWx_DVSSPEED I C bit as shown in Table 28. This applies only when DVS is enabled. • Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected 2 by I C bits SWx_SLP_VOLT[5:0]. Voltage transitions initiated by a turn off event are 2 governed by the SWx_DVSSPEED I C bit for SWx as shown in Table 28. This applies only when DVS is enabled. As shown in Figure 5, during a falling DVS transition, dv/dt of the output voltage depends on the load current. Setting the SWx_FPWM_IN_DVS bit forces the regulator in the FPWM mode during the falling transition allowing it to accurately track the DVS reference, removing the load dependency. The SWx_FPWM_IN_DVS bit is active only when OTP_SWx_DVS_SEL = 0. Table 28. SWx DVS setting selection SWx_DVS speed Function 0 12.5 mV step each 2.0 µs 1 12.5 mV step each 4.0 µs Requested set point Output voltage with light load Internally controlled steps Output voltage Example actual output voltage Initial set point Actual output voltage Voltage change request Request for higher voltage Internally controlled steps Request for lower voltage Initiated by I2C programming, standby control or DVS control Possible output voltage window aaa-023876 Figure 5. SWx DVS transitions 6.2.2 SWx DVS and non-DVS operation SWx has two distinct modes of operation selectable via OTP: • DVS enabled: a DVS reference is activated and output accuracy of the regulator is tight at the cost of slightly higher quiescent current. See Section 5.3 "Electrical characteristics" for details. In Figure 6, DVS FB and DVS REF are enabled via OTP for this mode of operation. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 26 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors • DVS disabled: the regulator operates as a traditional buck converter with a fixed reference and soft-start. The quiescent current in this mode is lower at the cost of output accuracy and transient response. See Section 5.3 "Electrical characteristics" for details. In Figure 6, VREF FB and VREF are enabled via OTP for this mode of operation. VIN TON iLim Low PWR ibias sel VREF FB sel COMP CTRL logic Low PWR ZCD iLim VREF DVS REF TOFF VOUT Driver DVS FB VOUT Bias control VREF FB VREF Programmable resistor divider VOUT: 1.1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.0, 3.3 (three bits) Fixed bandgap reference with soft-start function Reduced accuracy and transient capabilities OR DVS FB DVS REF Fixed DVS feedback and compensation Programmable DVS feedback and compensation aaa-023877 Figure 6. SWx DVS and non-DVS selection 6.2.3 Regulator control To improve system efficiency, the buck regulators can operate in different switching/ bias modes. The changing between DCM (Discontinuous Conduction Mode) / CCM (Continuous Conduction Mode) takes place automatically based on detecting the load 2 current level. It can be enforced by one of the following means: I C programming, exiting/ entering the Standby mode, exiting/entering Sleep/ Low-power mode. Available modes for buck regulators are presented in Table 29. These switching modes are available with OTP_SWx_DVS_SEL = 0 and OTP_SWx_DVS_SEL = 1. Table 30 shows the bit settings for operating the buck converter is these modes based on the PMIC operating state. Table 29. Buck regulator operating modes Mode OFF Description The regulator is switched off and the output voltage is discharged using an internal resistor. Adaptive This is the default mode of operation of the buck regulator. In this mode, the regulator operates in a quasi-fixed frequency switching mode at moderate and high loads, with pulse skip (variable switching frequency) scheme at light load for optimized efficiency. F-PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. Low-power To further extend power savings when the load current is minimal, this mode cuts the quiescent current of the buck converter by reducing the bias to the comparator. The regulator is operated in Low-power modes (Standby and/or 2 Sleep) with the proper I C setting. See Table 30. The following table shows actions to control different bits for SW1 and SW2. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 27 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 30. Buck mode control PMIC state SWx_EN SWx_STBY SWx_OMODE SWx_LPWR SWx_FPWM SWx operating mode Run/Standby/Sleep 0 X X X X SW disabled Run 1 X X 0 0 SW enabled. Operates in DCM at light loads Run 1 X X 0 1 SW enabled. Forced PWM mode Run 1 X X 1 0 SW Enabled. Does not operate in Lowpower mode. Run 1 X X 1 1 SW enabled. Forced PWM mode – not Low-power mode. Standby 1 0 X X X SW disabled Standby 1 1 X 0 0 SW enabled. Operates in DCM at light loads. Standby 1 1 X 0 1 SW enabled. Forced PWM mode. Standby 1 1 X 1 0 SW enabled. Operates in Low-power mode. Standby 1 1 X 1 1 SW enabled. Forced PWM mode – not Low-power mode. Sleep 1 X 0 X X SW disabled Sleep 1 X 1 0 0 SW enabled. Operates in DCM at light loads. Sleep 1 X 1 0 1 SW enabled. Forced PWM mode. Sleep 1 X 1 1 0 SW enabled. Operates in Low-power mode. Sleep 1 X 1 1 1 SW enabled. Forced PWM mode – not Low-power mode. 6.2.4 Current limit protection SWx features high and low-side FET current limit. When current through the FETs go above their respective thresholds, the FET is turned-off to prevent further increase in current. The protection is enabled in a cycle-by-cycle mode. Hitting either current limit sets the corresponding interrupt sense bits. If the faults persist for longer than the 8.0 ms debounce time, the interrupt status bit is set. 6.2.5 Output voltage setting in SWx Output voltage of SWx is programmable via OTP. During startup (REGS_DISABLE mode to RUN mode), contents of the OTP_SWx_VOLT[5:0] are mapped into the SWx_VOLT[5:0], SWx_STBY_VOLT[5:0], and SWx_SLP_VOLT[5:0] register which set the regulator output voltage during Run, Standby, and Sleep modes respectively. In the DVS enabled mode (OTP_SWx_DVS_SEL = 0), values of SWx_VOLT[5:0], 2 SWx_STBY[VOLT[5:0], and SWx_SLP_VOLT[5:0] can be changed via I C after the PMIC starts up (RESETBMCU is released). In the DVS disabled mode (OTP_SWx_DVS_SEL = 1), value of SWx_VOLT[5:0], SWx_STBY[VOLT[5:0], and SWx_SLP_VOLT[5:0] are read-only and must not be written to. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 28 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 31. SW1 and SW2 output voltage setting Set point SWx_VOLT[5:0] SWx_STBY_VOLT[5:0] SWx_SLP_VOLT[5:0] Output voltage with DVS enabled OTP_SWx_DVS_SEL = 0 Output voltage with DVS disabled OTP_SWx_DVS_SEL = 1 0 000000 0.6000 1.10 1 000001 0.6125 1.20 2 000010 0.6250 1.35 3 000011 0.6375 1.50 4 000100 0.6500 1.80 5 000101 0.6625 2.50 6 000110 0.6750 3.00 7 000111 0.6875 3.30 8 001000 0.7000 3.30 9 001001 0.7125 3.30 10 001010 0.7250 3.30 11 001011 0.7375 3.30 12 001100 0.7500 3.30 13 001101 0.7625 3.30 14 001110 0.7750 3.30 15 001111 0.7875 3.30 16 010000 0.8000 3.30 17 010001 0.8125 3.30 18 010010 0.8250 3.30 19 010011 0.8375 3.30 20 010100 0.8500 3.30 21 010101 0.8625 3.30 22 010110 0.8750 3.30 23 010111 0.8875 3.30 24 011000 0.9000 3.30 25 011001 0.9125 3.30 26 011010 0.9250 3.30 27 011011 0.9375 3.30 28 011100 0.9500 3.30 29 011101 0.9625 3.30 30 011110 0.9750 3.30 31 011111 0.9875 3.30 32 100000 1.0000 3.30 33 100001 1.0125 3.30 34 100010 1.0250 3.30 PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 29 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 31. SW1 and SW2 output voltage setting...continued Set point SWx_VOLT[5:0] SWx_STBY_VOLT[5:0] SWx_SLP_VOLT[5:0] Output voltage with DVS enabled OTP_SWx_DVS_SEL = 0 Output voltage with DVS disabled OTP_SWx_DVS_SEL = 1 35 100011 1.0375 3.30 36 100100 1.0500 3.30 37 100101 1.0625 3.30 38 100110 1.0750 3.30 39 100111 1.0875 3.30 40 101000 1.1000 3.30 41 101001 1.1125 3.30 42 101010 1.125 3.30 43 101011 1.1375 3.30 44 101100 1.1500 3.30 45 101101 1.1625 3.30 46 101110 1.1750 3.30 47 101111 1.1875 3.30 48 110000 1.2000 3.30 49 110001 1.2125 3.30 50 110010 1.2250 3.30 51 110011 1.2375 3.30 52 110100 1.2500 3.30 53 110101 1.2625 3.30 54 110110 1.2750 3.30 55 110111 1.2875 3.30 56 111000 1.3000 3.30 57 111001 1.3125 3.30 58 111010 1.3250 3.30 59 111011 1.3375 3.30 60 111100 1.3500 3.30 61 111101 1.3625 3.30 62 111110 1.3750 3.30 63 111111 1.3875 3.30 PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 30 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 6.2.6 SWx external components Table 32 shows the combination of inductor and capacitor values that work with the SWx regulator. The design is optimized for a 1.0 µH inductor. Table 32. Acceptable inductance and capacitance values Inductance / capacitance 2 x 10 µF 1.0 µH Table 33 and Table 34 show example inductor and capacitor part numbers respectively. Table 33. Example inductor part numbers Part number Size (mm) 1.0 µH DFE201610E 2.0 x 1.6 57 mΩ, 3.6 A DFE201610P 2.0 x 1.6 70 mΩ, 3.1 A DFE201210U 2.0 x 1.2 95 mΩ, 3.1 A DFE160810S 1.6 x 0.8 120 mΩ, 2.0 A DFE201208S 2.0 x 1.2 86 mΩ, 2.4 A DFE160808S 1.6 x 0.8 144 mΩ, 1.9 A Table 34. Example capacitor part numbers Murata part number Description GRM188R60J106ME47D 6.3 V, 10 µF, 0402, X5R GRM188D70J106MA73 6.3 V, 10 µF, 0402, X7R GRM188R61A106KE69 10 µF 10 V 10 % X5R 0603 .95 mm GRM219R61A106KE44 10 µF 10 V 10 % X5R 0805 .95 mm 6.3 SW3 detailed description SW3 is a buck regulator designed to carry a nominal load current of 1.0 A. The output voltage is programmable from 1.8 V to 3.3 V in 100 mV steps. Dynamic voltage scaling is not supported in this regulator. VIN VOUT TON iLim Low PWR VREF COMP Low PWR TOFF VOUT ZCD iLim Bias control VREF FB VREF CTRL logic Driver VREF FB ibias Programmable resistor divider VOUT (four bits): 1.8 V to 3.3 V in 100 mV steps Fixed bandgap reference with soft-start function Reduced accuracy and transient capabilities aaa-023878 Figure 7. SW3 block diagram PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 31 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 6.3.1 Regulator control To improve system efficiency, the buck regulator can operate in different switching/ bias modes. The changing between DCM/CCM takes place automatically based on 2 detecting the load current level. It can be enforced by one of the following means: I C programming, exiting/entering the Standby mode, exiting/entering Sleep/ Low-power mode. Available modes for buck regulators are presented in Table 35 . Table 36 shows the bit settings for operating the buck converter in these modes based on the PMIC operating state. Table 35. SW3 buck regulator operating modes Mode Description OFF The regulator is switched off and the output voltage is discharged using an internal resistor. Adaptive This is the default mode of operation of the buck regulator. In this mode, the regulator operates in a quasi-fixed frequency switching mode at moderate and high loads, with pulse skip (variable switching frequency) scheme at light load for optimized efficiency. F-PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. Low-power To further extend power savings when the load current is minimal, this mode cuts the quiescent current of the buck converter by reducing the bias to the comparator. The regulator 2 is operated in low power modes (Standby and/or Sleep) with the proper I C setting. See Table 36. Table 36. SW3 buck mode control PMIC state SW3_EN SW3_STBY SW3_OMODE SW3_LPWR SW3_FPWM Run/Stan dby/Sleep 0 X X X X SW disabled Run 1 X X 0 0 SW enabled Operates in DCM at light loads Run 1 X X 0 1 SW enabled Forced PWM mode Run 1 X X 1 0 SW enabled Does not operate in Lowpower mode Run 1 X X 1 1 SW enabled Forced PWM mode Standby 1 0 X X X SW disabled Standby 1 1 X 0 0 SW enabled Operates in DCM at light loads Standby 1 1 X 0 1 SW enabled Forced PWM mode Standby 1 1 X 1 0 SW Enabled Operates in Low-power mode Standby 1 1 X 1 1 SW enabled Forced PWM mode Sleep 1 X 0 X X SW disabled PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 SW3 operating mode © NXP B.V. 2021. All rights reserved. 32 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 36. SW3 buck mode control...continued PMIC state SW3_EN SW3_STBY SW3_OMODE SW3_LPWR SW3_FPWM Sleep 1 X 1 0 0 SW3 operating mode SW enabled Operates in DCM at light loads Sleep 1 X 1 0 1 SW enabled Forced PWM mode Sleep 1 X 1 1 0 SW enabled Operates in Low-power mode Sleep 1 X 1 1 1 SW enabled Forced PWM mode 6.3.2 Current limit protection SW3 features high and low-side FET current limit. When current through the FETs go above their respective thresholds, the FET is turned-off to prevent further increase in current. The protection is enabled in a cycle-by-cycle mode. Hitting either current limit sets the corresponding interrupt sense bits. If the faults persist for longer than the 8.0 ms debounce time, the interrupt status bit is set. 6.3.3 Output voltage setting in SW3 Output voltage of SW3 is programmable via OTP. During start-up (REGS_DISABLE mode to RUN mode), contents of the OTP_SW3_VOLT[5:0] are mapped into the SW3_VOLT[5:0], SW3_STBY_VOLT[5:0], and SW3_SLP_VOLT[5:0] register which set the regulator output voltage during Run, Standby, and Sleep modes respectively. Values of SW3_VOLT[5:0], SW3_STBY[VOLT[5:0], and SW3_SLP_VOLT[5:0] are readonly and cannot be written to. Table 37. SW3 output voltage setting PF1550 Product data sheet Set point SW3_VOLT[3:0] SW3_STBY_VOLT[3:0] SW3_SLP_VOLT[3:0] Output voltage (V) 0 0000 1.80 1 0001 1.90 2 0010 2.00 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 33 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 37. SW3 output voltage setting...continued Set point SW3_VOLT[3:0] SW3_STBY_VOLT[3:0] SW3_SLP_VOLT[3:0] Output voltage (V) 14 1110 3.20 15 1111 3.30 6.3.4 SW3 external components Table 38 shows the combination of inductor and capacitor values that work with the SW3 regulator. Table 38. Acceptable inductance and capacitance values Inductance / capacitance 2 x 10 µF 1.0 µH Table 39 and Table 40 show example inductor and capacitor part numbers respectively. Table 39. Example inductor part numbers Part number Size (mm) 1.0 µH DFE201610E 2.0 x 1.6 57 mΩ, 3.6 A DFE201610P 2.0 x 1.6 70 mΩ, 3.1 A DFE201210U 2.0 x 1.2 95 mΩ, 3.1 A DFE160810S 1.6 x 0.8 120 mΩ, 2.0 A DFE201208S 2.0 x 1.2 86 mΩ, 2.4 A DFE160808S 1.6 x 0.8 144 mΩ, 1.9 A Table 40. Example capacitor part numbers 7 Murata part number Description GRM188R60J106ME47D 6.3 V, 10 µF, 0402, X5R GRM188D70J106MA73 6.3 V, 10 µF, 0402, X7R GRM188R61A106KE69 10 µF 10 V 10 % X5R 0603 .95 mm GRM219R61A106KE44 10 µF 10 V 10 % X5R 0805 .95 mm Low dropout linear regulators, VREFDDR and VSNVS 7.1 General description This section describes the LDO regulators provided by the PF1550. All regulators use the main band gap as reference. When a regulator is disabled, the output is discharged by an internal pulldown. VLDO1 and VLDO3 can be used as load switches by setting the corresponding Load Switch enable bit OTP_VLDOx_LS. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 34 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors All general-purpose LDOs have short-circuit protection capability. The short-circuit protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected and REGSCPEN bit is set, the LDO is disabled by resetting its VLDOxEN bit, while at the same time, an interrupt VLDOxFAULTI is generated to flag the fault to the system processor. The VLDOxFAULTI interrupt is maskable through the VLDOxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators are not automatically be disabled upon a short-circuit detection. However, the current limiter continues to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators are disabled if an overloaded condition occurs. A fault interrupt, VLDOxFAULTI is generated in an overload condition regardless of the state of the REGSCPEN bit. Each LDO features a Low-power mode where the quiescent current consumed is significantly lower than in regulator operation. In the Low-power mode, load current of each regulator is limited to 10 mA. 7.2 LDO1 and LDO3 detailed description LDO1 and LDO3 are identical 300 mA low dropout (LDO) regulators that provide output 2 voltage with high accuracy and are programmable through I C interface bits. Being identical, reference is made to these LDOs as LDOy. To support this wide input range, LDOy circuit incorporates a PMOS pass FET as well as an NMOS pass FET. The LDO uses the main band gap as its reference. The regulator incorporates a soft-start circuit that ramps the internal reference in order to provide smooth output waveform with minimal overshooting during power-up. When the regulator is disabled, the output is discharged by an internal pulldown resistor. Additionally, the LDO can be used as a load switch by setting the corresponding Load Switch enable bit OTP_LDOy_LS. Moreover, LDOy includes current limit protection with the option to turn off the LDO when an overcurrent is detected. 7.2.1 Features summary • Input range LDO from 1.0 V to 4.5 V • Programmable output voltage between 0.75 V to 1.5 V (uses NMOS) or 1.8 V and 3.3 V (uses PMOS) with 2 % accuracy • Soft-start ramp control during power-up and discharge mechanism during power-down • Low quiescent current (~ 2.5 µA) at Low-power mode • Current limit protection • Configurable into load switch via OTP bit PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 35 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 7.2.2 LDOy block diagram VINx VDD VREF LDOxIN LDOxEN LDOxLPWR LDOxOUT I 2C interface CLDOx LDOx Discharge aaa-023879 Figure 8. LDOy Block Diagram 7.2.3 LDOy external components Use a 4.7 µF X5R/X7R capacitor from output to ground with a voltage rating at least 2 times the nominal output voltage. 7.2.4 LDOy output voltage setting LDOy output voltage is programmed by setting the LDOy[4:0] bits as shown in Table 41. Table 41. LDOy output voltage setting PF1550 Product data sheet Set point LDOy[4:0] LDOy output (V) 0 00000 0.7500 1 00001 0.8000 2 00010 0.8500 3 00011 0.9000 4 00100 0.9500 5 00101 1.0000 6 00110 1.0500 7 00111 1.1000 8 01000 1.1500 9 01001 1.2000 10 01010 1.2500 11 01011 1.3000 12 01100 1.3500 13 01101 1.4000 14 01110 1.4500 15 01111 1.5000 16 10000 1.8000 17 10001 1.9000 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 36 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 41. LDOy output voltage setting...continued Set point LDOy[4:0] LDOy output (V) 18 10010 2.0000 19 10011 2.1000 20 10100 2.2000 21 10101 2.3000 22 10110 2.4000 23 10111 2.5000 24 11000 2.6000 25 11001 2.7000 26 11010 2.8000 27 11011 2.9000 28 11100 3.0000 29 11101 3.1000 30 11110 3.2000 31 11111 3.3000 7.2.5 LDOy low-power mode operation LDOy can operate in a Low-power mode with reduced quiescent current. The Low-power mode can be activated in Standby and Sleep modes by setting the LDOy_LPWR bit as shown in Table 42. Maximum load current is limited to 10 mA when operating in the Lowpower mode. Table 42. LDOy control bits PMIC state LDOy_EN LDOy_STBY LDOy_OMODE LDOy_LPWR LDOy operating mode Run/Standby/Sleep 0 X X X LDO disabled Run 1 X X X LDO enabled Standby 1 0 X X LDO disabled Standby 1 1 X 0 LDO enabled Standby 1 1 X 1 LDO enabled in Low-power mode Sleep 1 X 0 X LDO disabled Sleep 1 X 1 0 LDO enabled Sleep 1 X 1 1 LDO enabled in Low-power mode 7.2.6 LDOy current limit protection LDOy has built in current limit protection. When the load current exceeds the current limit threshold, the regulator goes from a voltage regulation mode to a current regulation mode that limits the available output current. By setting the REGSCPEN bit, LDOy can be automatically disabled in the event of an overcurrent situation. In the event of an overcurrent, the LDO is disabled by resetting its LDOy_EN bit, while at the same time an interrupt LDOy_FAULTI is generated to flag the fault to the system processor. The LDOy_FAULTI interrupt is maskable through the LDOy_FAULTM mask bit. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 37 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors If REGSCPEN is not set, the regulator will not be automatically disabled, but will instead enter the current limit mode. By default, the REGSCPEN is not set; therefore, at startup none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, LDOy_FAULTI, is generated in an overload condition regardless of the state of the REGSCPEN bit. Current limit is not active when LDOy is operated in the load switch mode. 7.2.7 LDOy load switch mode The LDOy path can be turned into a switch by setting the OTP_LDOy_LS bit. Setting this bit fully turns on the LDO pass FET. This could be useful if power domain partitioning or additional isolation is needed on the system application. Soft-start is engaged during start-up of the load switch to reduce inrush currents. 7.3 LDO2 detailed description LDO2 is a 400 mA low dropout (LDO) regulator that provides output voltage with high 2 accuracy and programmable through I C/ interface bits. To support this wide input range, the LDO circuit incorporates a PMOS pass FET. The LDO uses the main bandgap as its reference. The regulator incorporates a soft-start circuit that ramps the internal reference in order to provide smooth output waveform with minimal overshooting during power-up. When the regulator is disabled, the output is discharged by an internal pull-down resistor. The pulldown is also activated when RESETBMCU is low. Moreover, LDO2 includes current limit protection with option to turn off the LDO when an overcurrent is detected. 7.3.1 LDO2 features summary • • • • • PF1550 Product data sheet Input range LDO from 2.8 V to 4.5 V Programmable output voltage between 1.8 V and 3.3 V with 2 % accuracy Soft-start ramp control during power-up and discharge mechanism during power-down Low quiescent current (~ 1.5 µA) at Low-power mode Current limit protection All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 38 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 7.3.2 LDO2 block diagram LDOxIN VREF LDOxIN LDOxEN LDOxLPWR LDOxOUT I 2C interface CLDOx LDOx Discharge aaa-023880 Figure 9. LDO2 block diagram 7.3.3 LDO2 external components Use a 10 µF X5R/X7R capacitor from output to ground with a voltage rating at least 2 times the nominal output voltage. 7.3.4 LDO2 output voltage setting LDO2 output voltage is programmed by setting the VLDO2[3:0] bits as shown in Table 43. Table 43. LDO2 output voltage setting PF1550 Product data sheet Set point VLDO2[3:0] VLDO2 output (V) 0 0000 1.80 1 0001 1.90 2 0010 2.00 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 39 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 7.3.5 LDO2 Low-power mode operation LDO2 can operate in a Low-power mode with reduced quiescent current. The Low-power mode can be activated in Standby and Sleep modes by setting the LDO2LPWR bit as shown in Table 44. Maximum load current is limited to 10 mA when operating in the Lowpower mode. Table 44. LDO2 control bits PMIC state LDO2EN LDO2STBY LDO2OMODE LDO2LPWR Run 0 X X X LDO2 operating mode LDO disabled Run 1 X X X LDO enabled Standby 1 0 X X LDO disabled Standby 1 1 X 0 LDO enabled Standby 1 1 X 1 LDO enabled in Low-power mode Sleep 1 X 0 X LDO disabled Sleep 1 X 1 0 LDO enabled Sleep 1 X 1 1 LDO enabled in Low-power mode 7.3.6 LDO2 current limit protection LDO2 has built in current limit protection. When the load current exceeds the current limit threshold, the regulator goes from a voltage regulation mode to a current regulation mode limiting the available output current. By setting the REGSCPEN bit, LDO2 can be automatically disabled in the event of an overcurrent situation. In the event of an overcurrent, the LDO is disabled by resetting its VLDO2EN bit, while at the same time an interrupt VLDO2FAULTI is generated to flag the fault to the system processor. The VLDO2FAULTI interrupt is maskable through the VLDO2FAULTM mask bit. If REGSCPEN is not set, the regulator is not automatically disabled, but instead enters the current limit mode. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators are disabled if an overloaded condition occurs. A fault interrupt, VLDO2FAULTI is generated in an overload condition regardless of the state of the REGSCPEN bit. 7.4 VREFDDR reference VREFDDR is an internal NMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input voltage. It is typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then utilizes a voltage follower to drive the load. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 40 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors VINREFDDR VINREFDDR Discharge VREFDDR VREFDDR CREFDDR 1.0 μF aaa-023881 Figure 10. VREFDDR block diagram 7.5 VSNVS LDO/switch VSNVS powers the low-power SNVS/RTC domain on the processor. It derives its power from either VSYS or a coin cell. When powered by both, VSYS powers VSNVS if VSYS > VTH threshold and LICELL powers VSNVS when VSYS < VTL. When powered by VSYS, VSNVS is an LDO capable of supplying 2.0 mA at 3.0 V. When powered by coin cell, VSNVS output tracks the coin cell voltage with a switch. In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across the switch. Upon subsequent removal of VSYS, with the coin cell attached, VSNVS changes configuration from an LDO to a switch. V PF1550 SYS Coin cell charger 1.8 to 3.3 V V Input sense selector REF VSNVS Coin cell LDO/LOAD switch I2C interface aaa-023882 Figure 11. VSNVS block diagram PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 41 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 8 Battery charger description The PF1550 charger is an integrated 1-cell Li+ charger with a single VBUS power input and dual path output. All power switches for charging and switching the load between battery and external power are included on chip. No external MOSFETs, blocking diodes or current sense resistors are required. The VBUS input operates from 4.0 V to 6.5 V with up to 22 V overvoltage protection. The PF1550 internally blocks current from the battery and system back to the inputs when no input supply is present. Other features include precharge battery conditioning and timer, fast charge timer, battery overvoltage protection, charge status and fault outputs, battery thermistor monitor and thermal regulation. Figure 12 shows a high level internal block diagram of the charger block. The PMIC is powered from the VSYS node in the PF1550. 5.0 V 37 HIGH VOLTAGE BLOCKING LDO MOSFET VBUSIN 2.2 F 25 V 0603 3.3 V 39 USBPHY 1.0 F 6.3 V 0603 LED_PWM VOUT PHY LDO 6 LED_FREQ ENABLE VFB OVP LDO 6.5 V 2 LED_CURRENT 5 ILIM 5 LED driver VSYS1 35 VSYS2 36 CHGB 40 4.2 V 22 F 10 V 0603 22 F 10 V 0603 47 0402 VSYS LED 2 VSYS_MIN BATTERY ISOLATION MOSFET VBUS_ILIMIT Linear charger + BATFET control CHARGER 3 DPM_THRESHOLD CC_TIMEOUT PRECHARGE_TIMEOUT EOC_TIMEOUT ENABLE 100 K 0402 4.7 K 0402 100 K 0402 0.1 F 6.3 V 0603 3 2 EOC TIMER WATCHDOG VDDIO SCL SDA 1 WDI 9 INTB CV_CHARGE Control logic + I2C registers 2 VBATT1 33 VBATT2 34 CV charge 3.5 V to 4.44 V V_PRECHARGE_THRESHOLD WEAK_BATTERY _THRESHOLD 2P7 supply INT2P7 38 RESTART _THRESHOLD CC TIMER PRECHARGE TIMER THM 32 EPAD GND REG_TEMP 10 K 0402 2.2 F 6.3 V 0603 + Battery pack 4.7 F 10 V 0603 CC charge 100 mA to 1.0 A 3.7 V Li-ion T t 2 THERMAL 4.7 K 0402 3 2 I2C INTERFACE 4 1 3 5 5 2 1 1 1 FAULTS 1.8 V 3 IBATT 2 VDPM I_EOC 6 VBATT I_PRECHARGE 5 TIMERS CC_CHARGE 1 CC_ADJ - 10 K thermistor CV_ADJ THM_HOT THM_WARM THM_COOL THM_COLD aaa-023883 Figure 12. Battery charger internal block diagram PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 42 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 8.1 Operating modes and behavioral description Startup sequence, USB insert, VBATT = 0 V 0V VBATT 5.0 V VBUSIN INT2P7 VBUS_VALID INT2P7 TSSVBUS_LIN BGOK 1.5 V VCORE 1.5 V VCOREDIG > 100 ms (min) VSYS SLEEP Linear on USBPHY (3.3 V) VDDIO VBUS_ILIM VSYSMIN Default mode OTP selectable (linear on or charger on) Charger state Charger detection 4.3 V External supply 0V SLEEP Charger on 1.8 V Processor detection sequence Commanded by processor SLEEP Based on adaptor type 0x00 (100 mA) aaa-025039 Figure 13. Charger low battery (Startup sequence, USB insert, VBATT = 0 V) PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 43 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Startup sequence, USB insert, VBATT = 3.8 V VBATT 3.8 V 5.0 V VBUSIN 2.7 V INT2P7 VBUS_VALID 1.5 V VCORE 1.5 V VCOREDIG 4.3 V > 100 ms (min) VSYS 3.8 V Charger state Default mode OTP selectable (linear on or charger on) SLEEP Linear on USBPHY (3.3 V) External supply VDDIO Charger detection VSYSMIN Charger on 1.8 V 0V SLEEP Processor detection sequence VBUS_ILIM SLEEP Based on adaptor type 0x00 (100 mA) aaa-025040 Figure 14. Charger healthy battery (Startup sequence, USB insert, VBATT = 3.8 V) Table 45. Battery regulation voltage register BATTERY REGULATION VOLTAGE REGISTER ADDR: 0x8F D7 BITS: POR: D6 D5 D4 D3 0 1 0 1 VSYSMIN 0 D2 D1 D0 0 1 1 CHGCV ACCESS: The VSYSMIN value is programmable via OTP as per the following table. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 44 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 46. VSYSMIN setting VSYSMIN[1:0] setting VSYSMIN setting (V) 00 3.5 01 3.7 10 4.3 11 Reserved The VSYSMIN setting is the "normal" regulation point for VSYS. This parameter sets the point where the VSYS loop starts taking control and regulates the output. 4.3 V is the recommended setting to ensure that there is enough headroom before reaching UVDET (PMIC undervoltage detection, 2.9 V typ.). Selecting lower settings causes the VSYS loop to start regulating, and reduces charging current to lower the VSYS threshold, thus reducing the headroom. Typically, the VSYS output range can go as low as 300 mV below the VSYSMIN setting. Therefore, the recommended setting for the VSYS output should be between 4.0 V to 4.3 V. 8.2 Charger input source detection The charger input is compared with several voltage thresholds to determine if it is valid. A charger input must meet the following three characteristics to be valid: • VBUS must be above VUVLO (4.2 V max.) to be valid • VBUS must be below its overvoltage lockout threshold (VOVLO (6.0 V min.)) • VBUS must be above the system voltage by VIN2SYS (50 mV / 175 mV programmable via OTP) The VBUS input generates an input interrupt when its status changes. The input status can be read with VBUS_OK and VBUS_SNS registers. Interrupts can be masked with VBUS_M register. Note: Adaptor removal is defined as VBUS < VUVLO. VBUS_xx VBUS_UVLO VVBUS_xx_UVLO VBUS_xx VVBUS_xx_OVLO VBUS_xx_OVLO VIN2SYS SYS VBUS_xx_INVLD VBUS_INVLD LIN2SYS aaa-025038 Figure 15. Input source detection delay 8.3 Input self-discharge for reliable charger input interrupt To ensure that a rapid removal and reinsertion of a charge source always results in a charger input interrupt, the charger input presents loading to the input capacitor to ensure that when the charge source is removed the input voltage decays below the UVLO threshold in a reasonable time. A 2.2 µF input capacitance charged up to the maximum OVLO threshold (VOVLO) decays down to the minimum UVLO threshold within 300 ms (tINSD). The input self-discharge is PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 45 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors implemented by with a 30 kΩ resistor (RINSD) from VBUSIN input to ground. The input self-discharge resistor is deactivated in the low-power mode to reduce total quiescent current. 8.4 Charger state diagram NO INPUT POWER or CHARGER DISABLED CHG_SNS = 0x08 CHG_OK = 0 ICHG = 0 CHG Timer = 0 WD Timer = 0 WATCHDOG Suspend WDT_SNS = 1 CHG_OK = 0 ICHG = 0 WD Timer > tWD (CHG Timer = Suspend, only if WDTEN = 1) INPUT is VALID (VBUS_VALID = 1) and MODE PROGRAMMED FOR CHARGER ENABLED (CHG Timer = Start) WDTCLR=TRUE (WD Timer = 0 & Resume CHG Timer = Resume) From: any prequal state, any fast charge state, end-of-charge, done or timer fault Returns to: the same state that it came from Battery overvoltage BATT_SNS = 0X05 BAT_OK = 0 ICHG = 0 VBATT > VBATOV For time > tBATOV TJ < TSHDN (CHG Timer = Suspend WD Timer = Suspend) LOW-BATTERY PRECHARGE MODE CHG_SNS = 0x00 CHG_OK = 1 ICHG ≤ IPRECHG.LB From: any precharge state, any fast charge state, end-of-charge, done Returns to: the same state that it came from CHG Timer > tPRECHG VBATT > VPRECHG.LB (Soft Start, CHG Timer = 0) TIMER FAULT CHG_SNS = 0x06 CHG_OK = 0 ICHG = 0 CHG Timer > tFC VBATT = 99 % of VBATREG for 32 ms VBATT < 95 % of VBATREG FAST CHARGE (CV) CHG_SNS = 0x02 CHG_OK = 1 ICHG ≤ IFC and ICHG > IEOC Battery Thermistor Suspend Mode CHG_SNS = 0x07 CHG_OK = 0 ICHG = 0 Battery Temperature > THOT OR Battery Temperature < TCOLD VBATT < (VBATREG - VRESTART) (No Soft Start, CHG Timer = Restart) Battery Temperature < THOT AND Battery Temperature > TCOLD VBATT < (VBATREG - VRESTART) (Resume charge timer) (No Soft Start, CHG Timer = Restart) From: any precharge state, any fast charge state, end-of-charge, done Returns to: the same state that it came from TJ > TSHDN (CHG Timer = 0 WD Timer = 0) Thermal Shutdown CHG_SNS = 0x0A CHG_OK = 0 ICHG = 0 FAST CHARGE (CC) CHG_SNS = 0x01 CHG_OK = 1 VBATT ≤ VBATREG ICHG ≤ IFC and ICHG > IEOC VBATT < VBATOV (Resume charge timer) INPUT is INVALID ANY STATE except thermal shutdown Direct Transition VBATT < VPRECHG.LB (CHG Timer = 0) CHG_OPER[3:0] PROGRAMMED THE CHARGER TO BE OFF CHG Timer > tFC ICHG < IEOC for tSCIDG (CHG Timer = 0 and Suspend) END-OF-CHARGE CHG_SNS = 0x03 CHG_OK = 1 ICHG ≤ IEOC CHG Timer > tEOC DONE CHG_SNS = 0x04 CHG_OK = 0 ICHG = 0 aaa-025042 Figure 16. Charger state diagram 8.5 Charging profile The battery is charged in three modes. Linear control of the BATFET has two subset modes (Trickle and Linear constant current mode). PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 46 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Battery voltage • Linear control of BATFET – Trickle (programmable from 55 mA/100 mA based on battery voltage) – Linear constant current mode from 100 mA to 1000 mA • Constant current (CC) • Constant voltage (CV) VBATREG VRESTART VSYS VLOW_BATT VBATT (> 0 V) Time Battery current ICHARGE_CC IEOC IPRECHARGE End-of-charge (EOC) Fast charge constant voltage (CV) Restart fast charge (CV) Fast charge constant current (CC) DONE (VSYS loaded) Time End-of-charge (EOC) Low battery recovery State Battery disconnected IBAT (0 A) aaa-023884 Figure 17. Charging profile 8.5.1 Precharge state The precharge state is entered when the main-battery voltage is less than VPRECHG.LB which is precharge (low battery) charging voltage threshold set by PRECHGLB_THRS[6:5]. After being in this state for tSCIDG, a CHG_I interrupt is generated, CHG_OK bit is set, and CHG_SNS register is set to 0x00. In the precharge state, the charge current into the battery is equal or lower than IPRECHG.LB (45 mA typ). Following events causes the state machine to exit this state: 1. When the main battery voltage rises above VPRECHG.LB, the charger enters the next state in the charging cycle: “Fast-Charge Constant Current" state. 2. If the battery charger remains in this state for longer than tPRECHG, the charger state machine transitions to the “Timer Fault” state. 3. If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state. Note: The precharge state works with battery voltages down to 0 V. The low 0 V operation typically allows this battery charger to revive batteries that have an “open” internal pack protector. Typically, the pack internal protection circuit isolates the Lithium-ion cell if the battery pack has detected an overcurrent, undervoltage, or PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 47 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors overvoltage. When a battery with an “open” internal pack protector is used with this charger, the low-battery precharge mode forces a small current into the 0 V battery. This current raises the pack’s terminal voltage above the pack revive threshold, causing the internal pack protection switch to reconnect the Lithium-ion cell. A normal battery pack typically could stay in the low-battery precharge state for several minutes. If a battery pack stays in low-battery precharge for longer than tPRECHG, it may be defective. 8.5.2 Fast charge constant current state The fast-charge constant current (CC) state occurs when the main-battery voltage is greater than the precharge threshold and less than the battery regulation threshold (VPRECHG.LB < VBATT < VCHGCV). In the fast-charge CC state, the current into the battery is less than or equal to IFC (excluding accuracy IFCACC). Charge current may be less than IFC for any of the following reasons: • The charger input is in input current limit • The charger input voltage is low • The system load is consuming adapter current. When the voltage drop between VBUS and VSYS is below the VIN2SYS threshold, charging stops and charge current drops down to 0 A. Note: The system load always gets priority over the battery charge current. The system load always gets priority over the battery charge current. The following events cause the state machine to exit this state: • When the main battery voltage rises above VBATREG, the charger enters the next state in the charging cycle: "Fast Charge (CV)". • If the battery charger remains in this state for longer than tFC, the charger state machine transitions to the "Timer Fault" state. • If the watchdog timer is not serviced, the charger state machine transitions to the "Watchdog Suspend" state. The battery charger dissipates the most power in the fast-charge constant current state. This power dissipation causes the internal die temperature to rise. If the die temperature exceeds the threshold set by REGTEMP[1:0], IFC is reduced. This is covered in Section 8.8.1 "Thermal regulation". Table 47. Charger current control register CHARGER CURRENT CONTROL REGISTER ADDR: 0x8E D7 D6 BITS: RESERVED POR: 0 ACCESS: — D5 D4 D3 0 0 PRECHGLB_THRESHOLD 0 0 D2 D1 D0 0 0 CHG_CC 0 2 The fast charge current is programmable via I C using the bits in Table 48. Table 48. Constant current charge settings PF1550 Product data sheet CHG_CC[4:0] setting IFC current (mA) 00000 100 00001 150 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 48 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 48. Constant current charge settings...continued CHG_CC[4:0] setting IFC current (mA) 00010 200 00011 250 00100 300 00101 350 00110 400 00111 450 01000 500 01001 550 01010 600 01011 650 01100 700 01101 750 01110 800 01111 850 10000 900 10001 950 10010 1000 10011 1050 (Reserved) 10100 1100 (Reserved) 10101 1150 (Reserved) 10110 1200 (Reserved) 10111 1250 (Reserved) 11000 1300 (Reserved) 11001 1350 (Reserved) 11010 1400 (Reserved) 11011 1450 (Reserved) 11100 1500 (Reserved) 11101 1550 (Reserved) 11110 1600 (Reserved) 11111 1650 (Reserved) To insure proper operation, the maximum CC current selected must be one setting below input current limit (in charger normal mode). In normal mode, when VSYS < VSYSMINLOOPx (VSYSMINLOOPx = VSYSMINx − 300 mV), digital logic automatically controls maximum CC current (one setting lower than charger input current limit ILIM setting). If 100 mA input current limit is selected, the charge current is forced to 50 mA to allow enough current for VSYS. The Charger Low-power mode (CLPM) is entered automatically when the 50 mA input current limit setting, or lower, is selected and when VBATT > 2.8 V. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 49 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 8.5.3 Fast charge constant voltage state The fast-charge constant voltage (CV) state occurs when the battery voltage rises to VBATREG from the fast-charge CC state. In the fast-charge CV state, the battery charger maintains VBATREG across the battery and the charge current is less than or equal to IFC. Charger current decreases exponentially in this state as the battery becomes fully charged. The BATFET control circuitry may reduce the charge current for any of the following reasons: • The charger input is in input current limit • The charger input voltage is low • The system load is consuming adapter current. The system load always gets priority over the battery charge current. The following events cause the state machine to exit this state: • When the charger current is below IEOC for tSCIDG, the charger enters the next state in the charging cycle: “End-of-Charge”. • If the battery charger remains in this state for longer than tFC, the charger state machine transitions to the “Timer Fault” state. • If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state. Note: During the CC to CV transition, the charge current can be momentarily higher than IFC. This current is safe and does not result in over charging the battery. After this transition, the charge current decays and is less than or equal to IFC. Table 49. Battery regulation voltage register BATTERY REGULATION VOLTAGE REGISTER ADDR: 0x8F D7 BITS: POR: D6 D5 D4 D3 VSYSMIN 0 D2 D1 D0 0 1 1 CHGCV 0 1 0 1 ACCESS: 2 The CV setting is programmable via I C using the bits in Table 50. Table 50. CV settings PF1550 Product data sheet CHGCV[5:0] Output voltage (V) 000000 3.50 000001 3.50 000010 3.50 000011 3.50 000100 3.50 000101 3.50 000110 3.50 000111 3.50 001000 3.50 001001 3.52 001010 3.54 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 50 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 50. CV settings...continued CHGCV[5:0] Output voltage (V) 001011 3.56 001100 3.58 001101 3.60 001110 3.62 001111 3.64 010000 3.66 010001 3.68 010010 3.70 010011 3.72 010100 3.74 010101 3.76 010110 3.78 010111 3.80 011000 3.82 011001 3.84 011010 3.86 011011 3.88 011100 3.90 011101 3.92 011110 3.94 011111 3.96 100000 3.98 100001 4.00 100010 4.02 100011 4.04 100100 4.06 100101 4.08 100110 4.10 100111 4.12 101000 4.14 101001 4.16 101010 4.18 101011 PF1550 Product data sheet [1] 4.20 101100 4.22 101101 4.24 101110 4.26 101111 4.28 110000 4.30 110001 4.32 110010 4.34 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 51 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 50. CV settings...continued [1] CHGCV[5:0] Output voltage (V) 110011 4.36 110100 4.38 110101 4.40 110110 4.42 110111 4.44 111000 4.44 111001 4.44 111010 4.44 111011 4.44 111100 4.44 111101 4.44 111110 4.44 111111 4.44 Default setting Table 51. Charger timers register CHARGER TIMERS REGISTER ADDR: 0x8A D7 D6 BITS: TPRECHG RESERVED POR: 0 0 ACCESS: D5 D4 D3 D2 1 0 EOCTIME 0 D1 D0 FCHGTIME 0 1 0 — 2 The fast charge timer is programmable via I C through the bits in Table 52: Table 52. Fast charge timer settings FCHGTIME[2:0] setting Fast charge timer duration (Hours) 000 Disable 001 2 010 4 011 6 100 8 101 10 110 12 111 14 The fast charge timer fault can occur in the fast charge mode, the system draws current such that the charger state machine is technically in the "fast charge" state but the battery is not really in "fast charge". This can happen if the current available from the charger input is not sufficient to provide system load as well as charge the battery. It is up to the processor to react to the timer fault accordingly. It can decide to restart charging (via CHG_OPER), or accept it as an actual timer fault. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 52 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 8.5.4 End-of-charge state The end-of-charge state can only be entered from the fast-charge CV state when the charger current decreases below IEOC for tSCIDG. After being in the top-off state for tSCIDG + tDB(EOC), an interrupt is generated, CHG_OK is set and CHG_SNS = 0x03. In the endof-charge state, the battery charger tries to maintain VCHGCV across the battery and typically the charge current is less than or equal to IEOC. The BATFET control circuitry may reduce the charge current lower than the battery may otherwise consume for any of the following reasons: • The charger input is in input current limit • The charger input voltage is low • The system load is consuming adapter current. The system load always gets priority over the battery charge current. The following events cause the state machine to exit this state: • After being in this state for the end-of-charge time (tEOC), the charger enters the next state in the charging cycle: “DONE”. • If VBATT < VBATREG – VRESTART, the charger goes back to the “FAST CHARGE (CC)” state. • If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state. Table 53. Charger EOC configuration register CHARGER EOC CONFIGURATION REGISTER ADDR: 0x8D D7 D6 BITS: EOC_MODE POR: 0 D5 D4 IEOC 1 0 0 D3 D2 EOC_EXIT FRC_ BATT_ISO D1 0 0 D0 CHG_RESTART 0 1 ACCESS: The EOC current value is programmable per the following table: Table 54. EOC current thresholds PF1550 Product data sheet IEOC[2:0] setting IEOC current (mA) 000 5 001 10 010 20 011 30 100 50 101 Reserved 110 Reserved 111 Reserved All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 53 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 55. Charger timers register CHARGER TIMERS REGISTER ADDR: 0x8A D7 D6 BITS: TPRECHG RESERVED POR: 0 0 ACCESS: D5 D4 D3 D2 1 0 EOCTIME 0 0 D1 D0 FCHGTIME 1 0 — The EOC State timer is programmable per the following table: Table 56. EOC state timer settings EOCTIME[2:0] setting EOC timer duration (Minutes) 000 0 (16 seconds debounce) 001 10 010 20 011 30 100 40 101 50 110 60 111 70 8.5.5 Done state The battery charger enters its done state after the charger has been in the end-ofcharge state for tEOC. After being in this state for tSCIDG, a CHG_I interrupt is generated, CHG_OK is cleared and CHG_SNS = 0x04. The following events cause the state machine to exit this state: • If VBATT < VBATREG – VRESTART, the charger goes back to the "FAST CHARGE (CC)" state • If the watchdog timer is not serviced, the charger state machine transitions to the "Watchdog Suspend" state In the done state, the charge current into the battery (ICHG) is 0 A. In the done state, the charger presents a very light load to the battery. If the system load presented to the battery is low ( Tgreset 2. From the REGS_DISABLE mode if the GOTO_CORE_OFF bit is set PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 74 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors This state cannot be entered if a charger is plugged in. In this state, the internal core of the PMIC is turned off to reduce quiescent current. VSNVS is the only regulator that is supplied to external loads. 10.2.3 SHIP In this mode, the MBATT switch between VSYS and VBATT is opened. All the PMIC supplies including VSNVS are turned off. The SHIP mode is entered if the GOTO_SHIP bit is set in the REGS_DISABLE state. The only way to exit from this mode is by a charger attach event. The state machine exits to the REGS_DISABLE state when this happens. A battery reattach can also be used to exit SHIP mode. 10.3 Turn on events A turn on event takes the PMIC from the REGS_DISABLE state to the RUN state (transition H in Figure 26). The turn on events are: 1. PWRON logic high with PWRON_CFG = 0 2. PWRON H -> L with PWRON_CFG = 1 VSYS > UVDETrising and TJ < TSHDN_fall are preconditions for a turn on event to occur. The turn on is to be completed after the RESETBMCU pin is deasserted. The WDI pin is masked till the RESETBMCU pin is deasserted. 10.4 Turn off events A turn off event takes the PMIC state machine from one of the “System On” states (RUN, STANDBY, or SLEEP) to the REGS_DISABLE state. The power-down sequence is followed during all of the turn off events. The turn off events are: 1. 2. 3. 4. Thermal Shutdown (TJ > TSHDN_rise) PWRON logic low with OTP_PWRON_CFG = 0 PWRON low > 4.0 s with OTP_PWRON_CFG = 1 && PWRONRSTEN = 1 WDI = 0. This occurs when the processor watchdog expires and pulls the WDI pin low to create a hard reset. 5. ON_KEY pressed low > Tgreset && ON_KEY_RST_EN = 1. This facilitates creating a hard reset when pressing the ON_KEY button without processor intervention. 6. GOTO_SHIP = 1. This is used to initiate the device to go into the SHIP mode. When GOTO_SHIP bit is set to 1, the state machine proceeds from one of the “System On” states to the REGS_DISABLE mode to the SHIP mode. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 75 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 10.5 State diagram and transition conditions Table 83. State transition table Transi Description tion PWRON_CFG = 0 (Level sensitive) PWRON_CFG = 1 (Edge sensitive) A Standby to Run (STANDBY pin = 0 && STANDBYINV bit = 0) OR (STANDBY pin = 1 && STANDBYINV bit = 1) (STANDBY pin = 0 && STANDBYINV bit = 0) OR (STANDBY pin = 1 && STANDBYINV bit = 1) B Run to Standby (STANDBY pin = 1 && STANDBYINV bit = 0) OR (STANDBY pin = 0 && STANDBYINV bit = 1) (STANDBY pin = 1 && STANDBYINV bit = 0) OR (STANDBY pin = 0 && STANDBYINV bit = 1) C Standby to Sleep (PWRON = 0) && (Any SWxOMODE = 1 || Any LDOxOMODE = 1) (PWRON High to Low and PWRON = 0 > 4s) && (PWRONRSTEN = 1) && (Any SWxOMODE = 1 || Any LDOxOMODE = 1) E Sleep to Run PWRON = 1 PWRON High to Low to High F Run to Sleep (PWRON = 0) && (Any SWxOMODE = 1 || Any LDOxOMODE = 1) (PWRON High to Low and PWRON = 0 > 4s) && (PWRONRSTEN = 1) && (Any SWxOMODE = 1 || Any LDOxOMODE = 1) G Run/Standby/ Sleep to REGS_ DISABLE (Thermal shutdown) OR (GOTO_SHIP = 1) OR (PWRON = 0 && All SWxOMODE = 0 && All LDOxOMODE = 0) OR [2] (WDI = 0) OR (ONKEY High to Low and ONKEY = 0 > Tgreset && ONKEY_RST_EN = 1) OR [3][4] (VSYS < UVDET_Fall) (Thermal shutdown) OR (GOTO_SHIP = 1) OR (PWRON High to Low and PWRON = 0 > 4s && PWRONRSTEN = 1 && All SWxOMODE = 0 && All LDOxOMODE = 0) OR (PWRON High to Low and PWRON = 0 > 4s when in Sleep state) OR [2] (WDI = 0) OR (ONKEY High to Low and ONKEY = 0 > Tgreset and ONKEY_RST_EN = 1) OR [3] (VSYS < UVDET_Fall) PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 [1] © NXP B.V. 2021. All rights reserved. 76 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 83. State transition table...continued Transi Description tion PWRON_CFG = 0 (Level sensitive) PWRON_CFG = 1 (Edge sensitive) H (PWRON = 1 ) (PWRON High to Low ) OR (If entered REGS_DISABLE via long press on PWRON && RESTARTEN = 1 && PWRON stays Low > 1.0s) OR (Charger attach) REGS_DISABLE to Run (Only if VSYS > UVDET and TJ < TSHDN_fall) [5] [6] I REGS_DISABLE to CORE_OFF (Only if VBUS_ INVALID = 1) (GOTO_CORE_OFF = 1 && ONKEY = 1) OR (ONKEY High to Low and ONKEY = 0 > [7][8] Tgreset && ONKEY_RST_EN = 1) (GOTO_CORE_OFF = 1 && ONKEY = 1) OR (ONKEY High to Low and ONKEY = 0 > [7][9] Tgreset && ONKEY_RST_EN = 1) J REGS_DISABLE to SHIP GOTO_SHIP = 1 && VBUS_INVALID = [10] 1 GOTO_SHIP = 1 && VBUS_INVALID = [10] 1 K CORE_OFF to REGS_DISABLE (ONKEY High to Low and ONKEY = 0 > 1000 ms) OR (Charger attach) (ONKEY High to Low and ONKEY = 0 > 1000 ms) OR (Charger attach) L SHIP to REGS_ DISABLE (Charger attach) OR (Battery reattach) (Charger attach) OR (Battery reattach) [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] This low period is < 4.0s. If it is longer than 4.0s, it transitions to G PWRON pin is pulled low by processor after WDI = 0. Follows regulator power-down sequence for this transition REGS_DISABLE is a transitionary state when GOTO_SHIP = 1. The state machine does not stay at G when GOTO_SHIP = 1 WDI pin is masked until RESETBMCU is deasserted. Debounce on PWRON programmable via PWRONDBNC[1:0] PWRON pin is pulled low by processor after ONKEY = 0 > Tgreset. GOTO_CORE_OFF is set by user when system is ON. For other products, a secondary processor is used to set this bit while in REGS_DISABLE GOTO_CORE_OFF must be set by user when system is ON VBUSIN pin voltage < 1.0 V 10.6 Regulator power-up sequencer Start-up sequence of all the switching and linear regulators in the PF1550 is programmable. VSNVS's sequence is not programmable but is always the first regulator to power up when the PF1550 is powered up via a cold start (from no input to valid input). When SYS is first applied to the PF1550 (either by applying a battery, or by plugging in a charger), VSNVS comes up first. The switching and linear regulators power up based on their programmed OTP sequence using the respective OTP_XX_SEQ[2:0] when transitioning from REGS_DISABLE to the RUN state. RESETBMCU is pulled low from VCOREDIG POR until the end of the power-up sequencer. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 77 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors RESETBMCU is pulled high 2.0 ms to 1024 ms after the last regulator powers up. This delay is OTP programmable through the OTP_POR_DLY[2:0] bits. When transitioning from STANDBY mode to RUN mode, the power-up sequencer is activated only if any of the regulators turn back on during this transition. The power-up sequencer ends as soon as the last regulator powers up, rather than waiting for a fixed time. The power-up sequencer is always activated when transitioning from Sleep to Run modes. The sequencer ends as soon as the last regulator powers up, rather than waiting for a fixed time. The PWRUP_I interrupt is set to indicate completion of transition from STANDBY to RUN and SLEEP to RUN. The PWRUP_I interrupt is set while transitioning from STANDBY to RUN even if the sequencers were not used. This is used to indicate that the transition is complete. 10.7 Regulator power-down sequencer The power-down sequencer performs the functional opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0], VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_PWRDN_SEQ[2:0] setting. This way, by default powerdown is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-down sequencer is bypassed and all the regulators are turned off at once. During transition from Run to Standby, the power-down sequencer is activated if any of the regulators are turned off during this transition. If regulators are not turned off during this transition, the power-down sequencer is bypassed and the transition happens at once (any associated DVS transitions still take time). During transition from Run to Sleep, the power-down sequencer is always activated. However, if all XXX_PWRDN_SEQ[2:0] = 0, the transition happens immediately. The PWRDN_I interrupt is set during transition from Run to Sleep and Run to Standby even if regulators are not turned off during these transitions. 11 Device start up 11.1 Startup timing diagram The startup timing of the regulators is programmable through OTP, Figure 27 shows the startup timing of the regulators as determined by their OTP A4 sequence. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 78 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors battery attach UVDET VSYS tD1 tR1 VSNVS tR2 tD2 PWRON tD3 tR3 Time Slot 0 tR3 tD3 LDO1, 3 Time Slot 1 tR3 tD3 LDO2 SW3 Time Slot 2 tD5 tR3 tD3 SW2 VREFDDR Time Slot 3 tD5 tD3 SW1 Time Slot 4 tR3 tD5 tR4 tD4 RESETBMCU aaa-028499 Figure 27. A4 startup and power down sequence Table 84. A4 startup and power down sequence timing Parameter Description tD1 tR1 tD2 [1] Min. Typ. Max. Unit Turn-on delay of VSNVS — 0.6 — ms Rise time of VSNVS — 0.1 — ms User determined delay — — — ms — ms tR2 Rise time of PWRON — [2] tD3 Power up delay between regulators • OTP_SEQ_CLK_SPEED = 0 • OTP_SEQ_CLK_SPEED = 1 — — 0.5 2.0 — — — 0.2 — ms ms [3] [4] tR3 Rise time of regulators tD4 Turn-on delay of RESETBMCU — 2.0 — ms tR4 Rise time of RESETBMCU — 0.2 — ms tD5 Power down delay between regulators — 2.0 — ms [1] [2] [3] [4] All regulators avoid drop-out mode at startup Depends on the external signal driving PWRON A4 configuration Rise time is a function of slew rate of regulators and nominal voltage selected. 11.2 Device start up configuration Table 85. PF1550 start up configuration Pre-programmed OTP configuration Registers A1 A2 A3 A4 A5 A6 A7 A8 A9 Default I C address 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 OTP_VSNVS_VOLT[2:0] 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V OTP_SW1_VOLT[5:0] 1.1 V 1.0 V 1.3875 V 1.1 V 1.3875 V 1.275 V 1.3875 V 1.3875 V 3.3 V 1 5 3 4 3 3 3 3 3 1.1 V 1.2 V 1.35 V 1.2 V 1.5 V 1.35 V 1.2 V 1.35 V 3.3 V 2 5 3 3 3 3 3 3 3 2 OTP_SW1_PWRUP_SEQ[2:0] OTP_SW2_VOLT[5:0] OTP_SW2_PWRUP_SEQ[2:0] PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 79 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 85. PF1550 start up configuration...continued Pre-programmed OTP configuration Registers OTP_SW3_VOLT[5:0] OTP_SW3_PWRUP_SEQ[2:0] OTP_LDO1_VOLT[4:0] OTP_LDO1_PWRUP_SEQ[2:0] OTP_LDO2_VOLT[3:0] OTP_LDO2_PWRUP_SEQ[2:0] A1 A2 A3 A4 A5 A6 A7 A8 A9 1.8 V 1.8 V 3.3 V 1.8 V 3.3 V 3.3 V 1.8 V 3.3 V 3.0 V 3 1 3 2 3 3 3 3 3 1.0 V 1.8 V 1.8 V 3.3 V 1.8 V 1.8 V 3.3 V 1.8 V 2.8 V 4 1 3 1 3 3 3 3 3 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 4 1 2 2 2 2 2 2 3 1.0 V 1.8 V 3.3 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 1.8 V OTP_LDO3_PWRUP_SEQ[2:0] 5 1 3 1 3 3 3 3 3 OTP_VREFDDR_PWRUP_SEQ[2:0] 5 5 3 3 3 3 3 3 OTP_LDO3_VOLT[4:0] OTP_SW1_DVS_SEL Non-DVS mode OTP_SW2_DVS_SEL DVS mode DVS mode Non-DVS mode 3 Non-DVS mode Non-DVS mode DVS mode Non-DVS mode LDO Mode OTP_LDO1_LS_EN OTP_LDO3_LS_EN LDO Mode LS Mode OTP_SW1_RDIS_ENB Enabled OTP_SW2_RDIS_ENB Enabled Enabled OTP_SW3_RDIS_ENB 12.5 mV step each 4.0 µs OTP_SW1_DVSSPEED OTP_SW2_DVSSPEED Non-DVS mode 12.5 mV step each 4.0 µs 12.5 mV step each 2.0 µs Non-DVS mode OTP_SWx_EN_AND_STBY_EN SW1, SW2, SW3 Enabled in RUN and STANDBY OTP_LDOx_EN_AND_STBY_EN LDO1, LDO2, LDO3, VREFDDR Enabled in RUN and STANDBY Level Sensitive OTP_PWRON_CFG OTP_SEQ_CLK_SPEED Edge Sensitive Level Sensitive Charger = ON, Linear = ON Charger = OFF, Linear = ON 2 ms Time Slots 0.5 ms Time Slots OTP_TGRESET[1:0] 4 secs Global Reset Timer OTP_POR_DLY[2:0] 2 ms RESETBMCU Power-Up Delay Rising 3.0 V; Falling 2.9 V OTP_UVDET[1:0] I2C Deglitch Filter Disabled OTP_I2C_DEGLITCH_EN OTP_CHGR_OPER[1:0] Charger = ON, Linear = ON Charger = OFF, Linear = ON Charger = ON, Linear = ON Charger = ON, Linear = ON Charger = ON, Linear = ON Charger = OFF, Linear = ON Charger = ON, Linear = ON Pre-charge timer = 30 minutes OTP_CHGR_TPRECHG End-Of-Charge Debounce = 16 secs OTP_CHGR_EOCTIME[2:0] OTP_CHGR_FCHGTIME[2:0] Fast-Charge Timer Disabled OTP_CHGR_EOC_MODE Linear ON in the DONE state 100 mV below CHGCV OTP_CHGR_CHG_RESTART[1:0] CC = 100 mA OTP_CHGR_CHG_CC[4:0] CC = 100 mA CC = 500 mA VSYSMIN = 4.3 V OTP_CHGR_VSYSMIN[1:0] VSYSMIN = 3.7 V VSYSMIN = 4.3 V VSYSMIN = 3.7 V CV = 4.2 V OTP_CHGR_CHGCV[5:0] OTP_CHGR_VBUS_LIN_ILIM[4:0] VBUS ILIM = 1500 mA VBUS ILIM = 500 mA OTP_CHGR_VBUS_DPM_REG[2:0] 3.9 V OTP_CHGR_USBPHYLDO 3.9 V 3.9 V 4.5 V 3.9 V 3.9 V 3.9 V 3.9 V 3.9 V USBPHY LDO Enabled USBPHY LDO Disabled USBPHY = 3.3 V OTP_CHGR_USBPHY OTP_CHGR_ACTDISPHY USBPHY Active Discharge Disabled USBPHY Active Discharge Enabled 12 Register map 12.1 Specific PMIC Registers (Offset is 0x00) The following pages contain description of the various registers in the PF1550. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 80 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 86. Register DEVICE_ID - ADDR 0x00 Name Bit R/W Default DEVICE_ID 2 to 0 R 100 FAMILY 7 to 3 R 01111 Description Loaded from fuses 000 — Devices with "00" at the end of the part number, such as "PF1500" 001 — Future use 010 — Future use 011 — Future use 100 — Devices with "50" at the end of the part number, such as "PF1550" 101 — Future use 110 — Future use 111 — Future use Identifies PMIC 01111 — 0b0_1111 for "15" used to denote the "PF1550" Table 87. Register OTP_FLAVOR - ADDR 0x01 Name UNUSED Bit R/W Default 7 to 0 R 0x00 Description Blown by ATE to indicate flavor of OTP used 0x00 — OTP not burned 0x01 — A1 0x02 — A2 0x03 — A3 continues... Table 88. Register SILICON_REV - ADDR 0x02 Name Bit R/W Default Description METAL_LAYER_REV 2 to 0 R 001 Unused FULL_LAYER_REV 5 to 3 R 010 Unused FAB_FIN 7 to 6 R 00 Unused Table 89. Register INT_CATEGORY - ADDR 0x06 Name Bit R/W Default CHG_INT 0 R 0 This bit is set high if any of the charger interrupt status bits are set 0 — No charger interrupt bit is set, cleared, or did not occur 1 — "OR" function of all charger interrupt status bit SW1_INT 1 R 0 This bit is set high if any of the Buck 1 interrupt status bits are set 0 — SW1 interrupts cleared or did not occur 1 — Any of the SW1 interrupt status bits are set SW2_INT 2 R 0 This bit is set high if any of the Buck 2 interrupt status bits are set 0 — SW2 interrupts cleared or did not occur 1 — Any of the SW2 interrupt status bits are set SW3_INT 3 R 0 This bit is set high if any of the Buck 3 interrupt status bits are set 0 — SW3 interrupts cleared or did not occur 1 — any of the SW3 interrupt status bits are set PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 81 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 89. Register INT_CATEGORY - ADDR 0x06...continued Name Bit R/W Default LDO_INT 4 R 0 Description This bit is set high if any of the LDO interrupt status bits are set. This includes LDO1, LDO2, and LDO3. 0 — LDO interrupts cleared or did not occur 1 — Any of the LDO interrupt status bits are set ONKEY_INT 5 R 0 This bit is set high if any of the interrupts associated with ONKEY push-button are set. 0 — ONKEY related interrupts cleared or did not occur 1 — Any of the ONKEY interrupt status bits are set TEMP_INT 6 R 0 This bit is set if any of the interrupts associated with the die temperature monitor are set 0 — PMIC junction temperature related interrupts cleared or did not occur 1 — any of the PMIC junction temperature interrupts status bits are set MISC_INT 7 R 0 This bit is set if interrupts not covered by the above mentioned categories occur 0 — Other interrupts (not covered by categories above) cleared, or did not occur 1 — Status bit of other interrupts (not covered by categories above) is set Table 90. Register SW_INT_STAT0 - ADDR 0x08 Name Bit SW1_LS_I 0 SW2_LS_I 1 SW3_LS_I UNUSED [1] R/W RW1C Default [1] Description 0 SW1 low-side current limit interrupt status. This bit is set if the current limit fault persists for longer than the debounce time. 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared RW1C 0 SW2 low-side current limit interrupt status. This bit is set if the current limit fault persists for longer than the debounce time. 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 2 RW1C 0 SW3 low-side current limit interrupt status. This bit is set if the current limit fault persists for longer than the debounce time. 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 7 to 3 — — Unused Read or Write 1 to clear the bit Table 91. Register SW_INT_MASK0 - ADDR 0x09 Name SW1_LS_M PF1550 Product data sheet Bit R/W Default 0 RW 1 Description SW1 low-side current limit interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 82 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 91. Register SW_INT_MASK0 - ADDR 0x09...continued Name Bit R/W Default SW2_LS_M 1 RW 1 SW2 low-side current limit interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. SW3_LS_M 2 RW 1 SW3 low-side current limit interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. 7 to 3 — — Unused UNUSED Description Table 92. Register SW_INT_SENSE0 - ADDR 0x0A Name Bit R/W Default SW1_LS_S 0 R 0 SW1 low-side current limit interrupt sense. Sense is high as long as fault persists (post-debounce). 0 — Fault removed 1 — Fault exists SW2_LS_S 1 R 0 SW2 low-side current limit interrupt sense. Sense is high as long as fault persists (post-debounce). 0 — Fault removed 1 — Fault exists SW3_LS_S 2 R 0 SW3 low-side current limit interrupt sense. Sense is high as long as fault persists (post-debounce) 0 — Fault removed 1 — Fault exists 7 to 3 — — Unused UNUSED Description Table 93. Register SW_INT_STAT1 - ADDR 0x0B Name Bit SW1_HS_I 0 SW2_HS_I 1 SW3_HS_I UNUSED [1] R/W RW1C Default [1] Description 0 SW1 high-side current limit interrupt 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared RW1C 0 SW2 high-side current limit interrupt 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 2 RW1C 0 SW3 high-side current limit interrupt 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 7 to 3 — — Unused Read or Write 1 to clear the bit PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 83 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 94. Register SW_INT_MASK1 - ADDR 0x0C Name Bit R/W Default SW1_HS_M 0 RW 1 SW1 high-side current limit interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. SW2_HS_M 1 RW 1 SW2 high-side current limit interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. SW3_HS_M 2 RW 1 SW3 high-side current limit interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. 7 to 3 — — Unused UNUSED Description Table 95. Register SW_INT_SENSE1 - ADDR 0x0D Name Bit R/W Default SW1_HS_S 0 R 0 SW1 high-side current limit interrupt sense. This bit should not toggle within a switching cycle (at buck switching frequency), but report the sense status within the switching cycle. 0 — Fault removed 1 — Fault exists SW2_HS_S 1 R 0 SW2 high-side current limit interrupt sense. This bit should not toggle within a switching cycle (at buck switching frequency), but report the sense status within the switching cycle. 0 — Fault removed 1 — Fault exists SW3_HS_S 2 R 0 SW3 high-side current limit interrupt sense. This bit should not toggle within a switching cycle (at buck switching frequency), but report the sense status within the switching cycle. 0 — Fault removed 1 — Fault exists 7 to 3 — — Unused UNUSED Description Table 96. Register SW_INT_STAT2 - ADDR 0x0E Name Bit SW1_DVS_DONE_I 0 SW2_DVS_DONE_I 1 PF1550 Product data sheet R/W RW1C Default [1] RW1C Description 0 Interrupt to indicate SW1 DVS complete. This interrupt should occur every time regulator output voltage is changed (either via 2 I C within a given state, or if there is change in voltage when transitioning states, Run to Standby, for example). 0 — DVS not complete and/or bit cleared 1 — DVS complete 0 Interrupt to indicate SW2 DVS complete. This interrupt should occur every time regulator output voltage is changed (either via 2 I C within a given state, or if there is change in voltage when transitioning states, Run to Standby, for example). 0 — DVS not complete and/or bit cleared 1 — DVS complete All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 84 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 96. Register SW_INT_STAT2 - ADDR 0x0E...continued Name UNUSED [1] Bit R/W Default 7 to 2 — — Description Unused Read or Write 1 to clear the bit Table 97. Register SW_INT_MASK2 - ADDR 0x0F Name Bit R/W Default SW1_DVS_DONE_M 0 RW 1 Mask for interrupt that indicates SW1 DVS complete 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. SW2_DVS_DONE_M 1 RW 1 Mask for interrupt that indicates SW2 DVS complete 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. 7 to 2 — — Unused UNUSED Description Table 98. Register SW_INT_SENSE2 - ADDR 0x10 Name Bit R/W Default SW1_DVS_S 0 R 0 Indicates DVS in progress for SW1 0 — DVS not in progress 1 — DVS in progress SW2_DVS_S 1 R 0 Indicates DVS in progress for SW2 0 — DVS not in progress 1 — DVS in progress 7 to 2 — — Unused UNUSED Description Table 99. Register LDO_INT_STAT0 - ADDR 0x18 Name Bit LDO1_FAULTI 0 LDO2_FAULTI 1 LDO3_FAULTI UNUSED [1] R/W RW1C Default [1] Description 0 LDO1 current limit interrupt 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared RW1C 0 LDO2 current limit interrupt 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 2 RW1C 0 LDO3 current limit interrupt 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 7 to 3 — — Unused Read or Write 1 to clear the bit PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 85 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 100. Register LDO_INT_MASK0 - ADDR 0x19 Name Bit R/W Default LDO1_FAULTM 0 RW 1 LDO1 current limit fault interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. LDO2_FAULTM 1 RW 1 LDO2 current limit fault interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. LDO3_FAULTM 2 RW 1 LDO3 current limit fault interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. 7 to 3 — — Unused UNUSED Description Table 101. Register LDO_INT_SENSE0 - ADDR 0x1A Name Bit R/W Default LDO1_FAULTS 0 R 0 LDO1 fault interrupt sense 0 — Fault removed 1 — Fault exists LDO2_FAULTS 1 R 0 LDO2 fault interrupt sense 0 — Fault removed 1 — Fault exists LDO3_FAULTS 2 R 0 LDO3 fault interrupt sense 0 — Fault removed 1 — Fault exists 7 to 3 — — Unused UNUSED Description Table 102. Register TEMP_INT_STAT0 - ADDR 0x20 Name Bit THERM110I 0 UNUSED 1 THERM125I UNUSED [1] R/W RW1C Default [1] Description 0 Die temperature crosses 110 °C interrupt. Bidirectional interrupt. 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared — — Unused 2 RW1C 0 Die temperature crosses 125 °C interrupt. Bidirectional interrupt. 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 7 to 3 — — Unused Read or Write 1 to clear the bit PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 86 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 103. Register TEMP_INT_MASK0 - ADDR 0x21 Name Bit R/W Default THERM110M 0 RW 1 Die temperature crosses 110 °C interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. UNUSED 1 — — Unused THERM125M 2 RW 1 Die temperature crosses 125 °C interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. 7 to 3 — — Unused UNUSED Description Table 104. Register TEMP_INT_SENSE0 - ADDR 0x22 Name Bit R/W Default THERM110S 0 R 0 110 °C interrupt sense 0 — Die temperature below 110 °C 1 — Die temperature above 110 °C UNUSED 1 — — Unused THERM125S 2 R 0 125 °C interrupt sense 0 — Die temperature below 125 °C 1 — Die temperature above 125 °C 7 to 3 — — Unused UNUSED Description Table 105. Register ONKEY_INT_STAT0 - ADDR 0x24 Name Bit ONKEY_PUSHI 0 ONKEY_1SI 1 ONKEY_2SI ONKEY_3SI PF1550 Product data sheet R/W RW1C Default [1] Description 0 Interrupt to indicate a push of the ONKEY button. Goes high after debounce. 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared. Interrupt occurs whenever ONKEY button is pushed low for longer than the falling edge debounce setting. Interrupt also occurs whenever ONKEY button is released high for longer than the rising edge debounce setting, provided it went past the falling edge debounce time. In other words, this interrupt occurs whenever a change in status of the ONKEY_PUSHS sense bit occurs. RW1C 0 Interrupt after ONKEY pressed for > 1 s 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 2 RW1C 0 Interrupt after ONKEY pressed for > 2 s 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 3 RW1C 0 Interrupt after ONKEY pressed for > 3 s 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 87 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 105. Register ONKEY_INT_STAT0 - ADDR 0x24...continued Name Bit R/W Default ONKEY_4SI 4 RW1C 0 Interrupt after ONKEY pressed for > 4 s 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared ONKEY_8SI 5 RW1C 0 Interrupt after ONKEY pressed for > 8 s 0 — Interrupt cleared or did not occur 1 — Interrupt occurred and/or not cleared 7 to 6 — — Unused UNUSED [1] Description Read or Write 1 to clear the bit Table 106. Register ONKEY_INT_MASK0 - ADDR 0x25 Name Bit R/W Default ONKEY_PUSHM 0 RW 1 Interrupt mask for ONKEY_PUSH_I 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. ONKEY_1SM 1 RW 1 Interrupt mask for ONKEY_1SI 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. ONKEY_2SM 2 RW 1 Interrupt mask for ONKEY_2SI 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is NOT pulled low if corresponding interrupt status bit is set. ONKEY_3SM 3 RW 1 Interrupt mask for ONKEY_3SI 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. ONKEY_4SM 4 RW 1 Interrupt mask for ONKEY_4SI 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. ONKEY_8SM 5 RW 1 Interrupt mask for ONKEY_8SI 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. 7 to 6 — — Unused UNUSED PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 88 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 107. Register ONKEY_INT_SENSE0 - ADDR 0x26 Name Bit R/W Default ONKEY_PUSHS 0 R 0 Push interrupt sense 0 — ONKEY not pushed low. This bit follows debounced version of the ONKEY button being released. 1 — ONKEY pushed low. This follows the ONKEY button after the debounce circuit (debounce is programmable). ONKEY_1SS 1 R 0 1 s interrupt sense or cleared after ONKEY button is released 0 — ONKEY not pushed low for >1 s or cleared after ONKEY button is released. 1 — ONKEY pushed and being held low > 1 s. This bit is cleared when ONKEY_PUSHS goes back to 0 when the push-button is released. ONKEY_2SS 2 R 0 2 s interrupt sense or cleared after ONKEY button is released 0 — ONKEY not pushed low for >1 s or cleared after ONKEY button is released. 1 — ONKEY pushed and being held low > 1 s. This bit is cleared when ONKEY_PUSHS goes back to 0 when the push-button is released. ONKEY_3SS 3 R 0 3 s interrupt sense or cleared after ONKEY button is released 0 — ONKEY not pushed low for >1 s or cleared after ONKEY button is released 1 — ONKEY pushed and being held low > 1 s. This bit is cleared when ONKEY_PUSHS goes back to 0 when the push-button is released. ONKEY_4SS 4 R 0 4 s interrupt sense or cleared after ONKEY button is released 0 — ONKEY not pushed low for >1 s or cleared after ONKEY button is released. 1 — ONKEY pushed and being held low > 1 s. This bit is cleared when ONKEY_PUSHS goes back to 0 when the push-button is released. ONKEY_8SS 5 R 0 8 s interrupt sense or cleared after ONKEY button is released 0 — ONKEY not pushed low for >1 s or cleared after ONKEY button is released. 1 — ONKEY pushed and being held low > 1 s. This bit is cleared when ONKEY_PUSHS goes back to 0 when the push-button is released. 7 to 6 — — Unused UNUSED Description Table 108. Register MISC_INT_STAT0 - ADDR 0x28 Name Bit PWRUP_I 0 PWRDN_I 1 PWRON_I 2 PF1550 Product data sheet R/W RW1C Default [1] Description 0 Interrupt to indicate completion of transition from STANDBY to RUN and from SLEEP to RUN 0 — Interrupt cleared or has not occurred 1 — Interrupt has occurred RW1C 0 Interrupt to indicate completion of transition from RUN to STANDBY and from RUN to SLEEP 0 — Interrupt cleared or has not occurred 1 — Interrupt has occurred RW1C 0 Power on button event interrupt 0 — Interrupt cleared or has not occurred 1 — Interrupt has occurred All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 89 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 108. Register MISC_INT_STAT0 - ADDR 0x28...continued Name Bit R/W Default LOW_SYS_WARN_I 3 RW1C 0 LOW_SYS_WARN threshold crossed interrupt 0 — Interrupt cleared or has not occurred 1 — Interrupt has occurred SYS_OVLO_I 4 RW1C 0 SYS_OVLO threshold crossed interrupt 0 — Interrupt cleared or has not occurred 1 — Interrupt has occurred 7 to 5 — — Unused UNUSED [1] Description Read or Write 1 to clear the bit Table 109. Register MISC_INT_MASK0- ADDR 0x29 Name Bit PWRUP_M 0 PWRDN_M 1 PWRON_M R/W Default [1] 1 Mask for Interrupt to indicate completion on transition from STANDBY to RUN and from SLEEP to RUN 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. RW 1 Mask for Interrupt to indicate completion on transition from RUN to STANDBY and from RUN to SLEEP 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. 2 RW 1 Power on button event interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. LOW_SYS_WARN_M 3 RW 1 LOW_SYS_WARN threshold crossed interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. SYS_OVLO_M 4 RW 1 SYS_OVLO threshold crossed interrupt mask 0 — Mask removed. INTB pin is pulled low if corresponding interrupt status bit is set. 1 — Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set. 7 to 5 — — Unused UNUSED [1] RW Description Asynchronous Set, Read, and Write Table 110. Register MISC_INT_SENSE0 - ADDR 0x2A Name PWRUP_S PF1550 Product data sheet Bit R/W Default 0 R 0 Description Sense for interrupt to indicate completion on transition from STANDBY to RUN and from SLEEP to RUN 0 — Transition not in progress 1 — Transition in progress All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 90 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 110. Register MISC_INT_SENSE0 - ADDR 0x2A...continued Name Bit R/W Default PWRDN_S 1 R 0 Interrupt to indicate completion on transition from RUN to STANDBY and from RUN to SLEEP 0 — Transition not in progress 1 — Transition in progress PWRON_S 2 R 0 Power on button event interrupt sense 0 — PWRON low 1 — PWRON high LOW_SYS_WARN_S 3 R 0 LOW_SYS_WARN threshold crossed interrupt sense 0 — SYS > LOW_SYS_WARN 1 — SYS < LOW_SYS_WARN SYS_OVLO_S 4 R 0 SYS_OVLO threshold crossed interrupt sense 0 — SYS < SYS_OVLO 1 — SYS > SYS_OVLO 7 to 5 — — Unused UNUSED Description Table 111. Register COINCELL_CONTROL - ADDR 0x30 Name Bit R/W Default VCOIN 3 to 0 RW 0000 4 RW 0 Coin cell charger enable 0 — Charger disabled 1 — Charger enabled 7 to 5 — — Unused COINCHEN UNUSED Description Coin cell charger charging voltage 0000 — 1.8 V 0111 — 3.3 V (goes up in 100 mV step per LSB) Table 112. Register SW1_VOLT - ADDR 0x32 Name Bit SW1_VOLT 5 to 0 UNUSED 7 to 5 [1] R/W Default [1] RW1S — Description — SW1 voltage setting register (Run mode) 000000 — See Table 31 for voltage settings 111111 — See Table 31 for voltage settings Reset condition — POR — Unused Load from OTP fuse, Read, and Write Table 113. Register SW1_STBY_VOLT - ADDR 0x33 Name Bit SW1_STBY_VOLT 5 to 0 UNUSED 7 to 6 [1] R/W Default [1] RW1S — Description — SW1 output voltage setting register (Standby mode). The default value here should be identical to SW1_VOLT[5:0] register. 000000 — See Table 31 for voltage settings 111111 — See Table 31 for voltage settings — Unused Load from OTP fuse, Read, and Write PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 91 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 114. Register SW1_SLP_VOLT - ADDR 0x34 Name Bit SW1_SLP_VOLT 5 to 0 UNUSED 7 to 6 [1] R/W Default [1] RW1S — Description — SW1 output voltage setting register (Sleep mode). The default value here should be identical to SW1_VOLT[5:0] register. 000000 — See Table 31 for voltage settings 111111 — See Table 31 for voltage settings — Unused Load from OTP fuse, Read, and Write Table 115. Register SW1_CTRL - ADDR 0x35 Name Bit R/W Default [1] SW1_EN 0 0 Enables buck regulator. Loaded from OTP based on the sequence settings. User can turn off regulator by clearing this bit. 0 — Regulator disabled in Run mode 1 — Regulator enabled in Run mode SW1_STBY_EN 1 RW1S 0 Enables buck regulator in Standby mode. User can turn off regulator by clearing this bit. The default value of this bit should be equal to the SW1_EN bit (based on OTP). 0 — Regulator disabled in Standby mode 1 — Regulator enabled in Standby mode SW1_OMODE 2 RW [2] 0 Enables buck regulator in Sleep mode. User can turn off regulator by clearing this bit. 0 — Regulator disabled in Sleep mode 1 — Regulator enabled in Sleep mode SW1_LPWR 3 RW 0 Enables the buck to enter Low-power mode during Standby and Sleep 0 — Regulator not in Low-power mode 1 — Regulator in Low-power mode during Standby or Sleep modes SW1_DVSSPEED 4 RW1S 0 Controls slew rate of DVS transitions. Loaded from OTP and changeable by user after boot up. Not used when OTP_SW1_ DVS_SEL = 1. 0 — DVS rate at 12.5 mV/2 μs 1 — DVS rate at 12.5 mV/4 μs SW1_FPWM_IN_DVS 5 RW 0 Enables CCM operation during DVS down 0 — does not force FPWM during DVS 1 — forces regulator to track the DVS reference while it is falling rather than relying on the load current to pull the voltage low SW1_FPWM 6 RW 0 Forces buck to go into CCM mode 0 — Not in FPWM mode 1 — Forced in PWM mode irrespective of load current SW1_RDIS_ENB 7 RW1S 0 Controls discharge resistor on output when regulator disabled 0 — Enables discharge resistor on output when regulator disabled. Resistor connected at FB pin when regulator disabled to force capacitor discharge. 1 — Disables discharge resistor on output when regulator disabled. Resistor not connected at FB pin when regulator disabled. Relies on leakage/residue load to discharge output capacitor. [1] [2] RW1S Description Load from OTP fuse, Read, and Write Asynchronous Set, Read, and Write PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 92 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 116. Register SW1_SLP_VOLT - ADDR 0x36 Name Bit SW1_ILIM 1 to 0 UNUSED 3 to 2 SW1_TMODE_SEL UNUSED [1] R/W Default [1] RW1S Description 00 Sets current limit of SW1 regulator 00 — Typical current limit of 1.0 A 01 — Typical current limit of 1.2 A 10 — Typical current limit of 1.5 A 11 — Typical current limit of 2.0 A — — Unused 4 RW 0 0 — TON control 1 — TOFF control 7 to 5 — — Unused Load from OTP fuse, Read, and Write Table 117. Register SW2_VOLT - ADDR 0x38 Name Bit SW2_VOLT 5 to 0 UNUSED 7 to 6 [1] R/W Default [1] RW1S — Description — SW2 voltage setting register (Run mode) 000000 —See Table 31 for voltage settings 111111 — See Table 31 for voltage settings — Unused Load from OTP fuse, Read, and Write Table 118. Register SW2_STBY_VOLT - ADDR 0x39 Name Bit SW2_STBY_VOLT 5 to 0 UNUSED 7 to 6 [1] R/W Default [1] RW1S — Description — SW2 output voltage setting register (Standby mode). The default value here should be identical to SW2_VOLT[5:0] register. 000000 — See Table 31 for voltage settings 111111 — See Table 31 for voltage settings — Unused Load from OTP fuse, Read, and Write Table 119. Register SW2_SLP_VOLT - ADDR 0x3A Name Bit SW2_SLP_VOLT 5 to 0 UNUSED 7 to 6 [1] R/W Default [1] RW1S — Description — SW2 output voltage setting register (Sleep mode). The default value here should be identical to SW2_VOLT[5:0] register. 000000 — See Table 31 for voltage settings 111111 — See Table 31 for voltage settings — Unused Load from OTP fuse, Read, and Write PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 93 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 120. Register SW2_CTRL - ADDR 0x3B Name Bit SW2_EN 0 SW2_STBY_EN 1 SW2_OMODE R/W Default [1] Description 0 Enables buck regulator. Loaded from OTP based on the sequence settings. User can turn off regulator by clearing this bit. 0 — Regulator disabled in Run mode 1 — Regulator enabled in Run mode RW1S 0 Enables buck regulator in Standby mode. User can turn off regulator by clearing this bit. The default value of this bit should be equal to the SW1_EN bit (based on OTP). 0 — Regulator disabled in Standby mode 1 — Regulator enabled in Standby mode 2 RW 0 Enables buck regulator in Sleep mode. User can turn off regulator by clearing this bit. 0 — Regulator disabled in Sleep mode 1 — Regulator enabled in Sleep mode SW2_LPWR 3 RW 0 Enables the buck to enter Low-power mode during Standby and Sleep modes 0 — Regulator not in Low-power mode 1 — Regulator in Low-power mode during Standby or Sleep SW2_DVSSPEED 4 RW1S 0 Controls slew rate of DVS transitions. Loaded from OTP and changeable by user after boot up. Not used when OTP_SW2_ DVS_SEL = 1. 0 — DVS rate at 12.5 mV/2 μs 1 — DVS rate at 12.5 mV/4 μs SW2_FPWM_IN_DVS 5 RW 0 Enables CCM operation during DVS down 0 — does not force FPWM during DVS 1 — forces regulator to track the DVS reference while it is falling rather than relying on the load current to pull the voltage low SW2_FPWM 6 RW 0 Forces buck to go into CCM mode 0 — Not in FPWM mode 1 — Forced in PWM mode irrespective of load current. SW2_RDIS_ENB 7 RW1S 0 Controls discharge resistor on output when regulator disabled 0 — Enables discharge resistor on output when regulator disabled. Resistor connected at FB pin when regulator disabled to force capacitor discharge. 1 — Disables discharge resistor on output when regulator disabled. Resistor not connected at FB pin when regulator disabled. Relies on leakage/residue load to discharge output capacitor. [1] RW1S Load from OTP fuse, Read, and Write Table 121. Register SW2_CTRL1 - ADDR 0x3C Name Bit R/W Default SW2_ILIM 1 to 0 RW1S 00 Sets current limit of SW2 regulator 00 — Typical current limit of 1.0 A 01 — Typical current limit of 1.2 A 10 — Typical current limit of 1.5 A 11 — Typical current limit of 2.0 A UNUSED 3 to 2 — — Unused 4 RW 0 0 — TON control 1 — TOFF control 7 to 5 — — Unused SW2_TMODE_SEL UNUSED PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 94 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 122. Register SW3_VOLT - ADDR 0x3E Name Bit R/W Default SW3_VOLT 3 to 0 RW1S — Description SW3 voltage setting register (Run mode). Loaded from fuses. Read only because DVS is not supported in this regulator. 0000 — See Table 37 for voltage settings 1111 — See Table 37 for voltage settings UNUSED 7 to 4 — — Unused Table 123. Register SW3_STBY_VOLT - ADDR 0x3F Name Bit R/W Default Description SW3_STBY_VOLT 3 to 0 RW1S — SW3 voltage setting register (Standby mode). Loaded from fuses. Read only because DVS is not supported in this regulator. 0000 — See Table 37 for voltage settings 1111 —See Table 37 for voltage settings UNUSED 7 to 4 — — Unused Table 124. Register SW3_SLP_VOLT - ADDR 0x40 Name Bit R/W Default Description SW3_SLP_VOLT 3 to 0 RW1S — SW3 voltage setting register (Sleep mode). Loaded from fuses. Read only because DVS is not supported in this regulator. 0000 — See Table 37 for voltage settings 1111 — See Table 37 for voltage settings UNUSED 7 to 4 — — Unused Table 125. Register SW3_CTRL - ADDR 0x41 Name Bit R/W Default SW3_EN 0 RW1S 0 Enables buck regulator. Loaded from OTP based on the sequence settings. User can turn off regulator by clearing this bit. 0 — Regulator disabled in Run mode 1 — Regulator enabled in Run mode SW3_STBY_EN 1 RW1S 0 Enables buck regulator in Standby mode. User can turn off regulator by clearing this bit. The default value of this bit should be equal to the SW1_EN bit (based on OTP). 0 — Regulator disabled in Standby mode 1 — Regulator enabled in Standby mode SW3_OMODE 2 RW 0 Enables buck regulator in Sleep mode. User can turn off regulator by clearing this bit. 0 — Regulator disabled in Sleep mode 1 — Regulator enabled in Sleep mode SW3_LPWR 3 RW 0 Enables the buck to enter Low-power mode during Standby and Sleep modes 0 — Regulator not in Low-power mode 1 — Regulator in Low-power mode while in Standby or Sleep UNUSED 4 — — Unused UNUSED 5 — — Unused PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 95 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 125. Register SW3_CTRL - ADDR 0x41...continued Name Bit R/W Default SW3_FPWM 6 RW 0 Description Forces buck to go into CCM mode 0 — Not in FPWM mode 1 — Forced in PWM mode irrespective of load current SW3_RDIS_ENB 7 RW1S 0 Controls discharge resistor on output when regulator disabled 0 — Enables discharge resistor on output when regulator disabled. Resistor connected at FB pin when regulator disabled to force capacitor discharge. 1 — Disables discharge resistor on output when regulator disabled. Resistor not connected at FB pin when regulator disabled. Relies on leakage/residue load to discharge output capacitor. Table 126. Register SW3_CTRL1 - ADDR 0x42 Name Bit R/W Default SW3_ILIM 1 to 0 RW1S 00 Sets current limit of SW3 regulator 00 — Typical current limit of 1.0 A 01 — Typical current limit of 1.2 A 10 — Typical current limit of 1.5 A 11 — Typical current limit of 2.0 A UNUSED 3 to 2 — — Unused 4 RW 0 0 — TON control 1 — TOFF control 7 to 5 — — Unused SW3_TMODE_SEL UNUSED Description Table 127. Register VSNVS_CTRL - ADDR 0x48 Name VSNVS_VOLT Bit R/W Default Description 2 to 0 RW1S 000 CLKPULSE 3 RW 0 Not used in PF1550. Placeholder for future products. Optional bit used for evaluation (see IP block) FORCEBOS 4 RW 0 Optional bit for evaluation 0 — BOS circuit activated only when VSYS < UVDET 1 — Forces best of supply circuit irrespective of UVDET LIBGDIS 5 RW 0 Use to reduce quiescent current in coin cell mode 0 — VSNVS local band gap enabled in coin cell mode 1 — VSNVS local band gap disabled in coin cell mode to save quiescent current UNUSED 7 to 6 — — Unused Table 128. Register VREFDDR_CTRL - ADDR 0x4A Name VREFDDR_EN PF1550 Product data sheet Bit R/W Default 0 RW1S 0 Description 0 — Disables VREFDDR regulator 1 — Enables VREFDDR regulator. This is set by the OTP sequence. All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 96 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 128. Register VREFDDR_CTRL - ADDR 0x4A...continued Name Bit R/W Default VREFDDR_STBY_EN 1 RW1S 0 The default value for this should be same as VREFDDREN 0 — Disables VREFDDR regulator in Standby mode 1 — Enables VREFDDR regulator in Standby mode if VREFDDREN = 1 VREFDDR_OMODE 2 RW 0 0 — Keeps VREFDDR off in Off mode 1 — Enables VREFDDR in Sleep mode if VREFDDREN = 1 VREFDDR_LPWR 3 RW 0 0 — Disables VREFDDR Low-power mode 1 — Enables VREFDDR Low-power mode 7 to 4 — — Unused UNUSED Description Table 129. Register LDO1_VOLT - ADDR 0x4C Name Bit R/W Default LDO1_VOLT 4 to 0 RW1S — Description LDO1 output voltage setting register. Loaded from OTP. 00000 — See Table 41 for voltage settings 11111 — See Table 41 for voltage settings UNUSED 7 to 5 — — Unused Table 130. Register LDO1_CTRL - ADDR 0x4D Name Bit R/W Default VLDO1_EN 0 RW1S 0 Enables LDO regulator. Loaded from OTP based on the sequence settings. User can turn off regulator by clearing this bit. 0 — Disables regulator 1 — Enables regulator VLDO1_STBY_EN 1 RW1S 0 Enables LDO in Standby mode. Default value of this bit should be same as VLDO1_EN. 0 — Disables regulator 1 — Enables regulator VLDO1_OMODE 2 RW 0 Enables LDO in Sleep mode 0 — Disables regulator 1 — Enables regulator VLDO1_LPWR 3 RW 0 Forces LDO to Low-power mode in Sleep and Standby modes 0 — Not in Low-power mode during Standby and Sleep 1 — Regulator in Low-power mode during Standby and Sleep LDO1_LS_EN 4 RW1S 0 This is loaded from OTP_LDOy_LS_EN and changeable from 0 to 1 on power-up. Changing from 1 to 0 is not allowed. 0 — Sets LDOy in LDO mode 1 — Sets LDOy to a load switch (fully on) mode 7 to 5 — — Unused UNUSED Description Table 131. Register LDO2_VOLT - ADDR 0x4F Name LDO2_VOLT PF1550 Product data sheet Bit R/W Default 3 to 0 RW1S — Description LDO2 output voltage setting register. Loaded from OTP. 0000 — See Table 43 for voltage settings 1111 — See Table 43 for voltage settings All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 97 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 131. Register LDO2_VOLT - ADDR 0x4F...continued Name UNUSED Bit R/W Default 7 to 4 — — Description Unused Table 132. Register LDO2_CTRL - ADDR 0x50 Name Bit R/W Default VLDO2_EN 0 RW1S 0 Enables LDO regulator. Loaded from OTP based on the sequence settings. User can turn off regulator by clearing this bit. 0 — Disables regulator 1 — Enables regulator VLDO2_STBY_EN 1 RW1S 0 Enables LDO in Standby mode. Default value of this bit should be same as VLDO1_EN. 0 — Disables regulator 1 — Enables regulator VLDO2_OMODE 2 RW 0 Enables LDO in Sleep mode 0 — Disables regulator 1 — Enables regulator VLDO2_LPWR 3 RW 0 Forces LDO to Low-power mode in Sleep and Standby modes 0 — Not in Low-power mode during Standby and Sleep 1 — Regulator in Low-power mode during Standby and Sleep 7 to 4 — — Unused UNUSED Description Table 133. Register LDO3_VOLT - ADDR 0x52 Name Bit R/W Default Description LDO3_VOLT 4 to 0 RW1S — LDO3 output voltage setting register. Loaded from OTP. 00000 — See Table 41 for voltage settings 11111 — See Table 41 for voltage settings UNUSED 7 to 5 — — Unused Table 134. Register LDO3_CTRL - ADDR 0x53 Name Bit R/W Default VLDO3_EN 0 RW1S 0 Enables LDO regulator. Loaded from OTP based on the sequence settings. User can turn off regulator by clearing this bit. 0 — Disables regulator 1 — Enables regulator VLDO3_STBY_EN 1 RW1S 0 Enables LDO in Standby mode. Default value of this bit should be same as VLDO1_EN. 0 — Disables regulator 1 — Enables regulator VLDO3_OMODE 2 RW 0 Enables LDO in Sleep mode 0 — Disables regulator 1 — Enables regulator VLDO3_LPWR 3 RW 0 Forces LDO to Low-power mode in Sleep and Standby modes 0 — Not in Low-power mode during Standby and Sleep 1 — Regulator in Low-power mode during Standby and Sleep PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 98 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 134. Register LDO3_CTRL - ADDR 0x53...continued Name LDO3_LS_EN UNUSED Bit R/W Default 4 RW1S 0 Description This is loaded from OTP_LDOy_LS_EN and changeable from 0 to 1 on power up. Changing from 1 to 0 is not allowed. 0 — sets LDOy in LDO mode 1 — sets LDOy to a load switch (fully on) mode 7 to 5 — — Unused Table 135. Register PWRCTRL0 - ADDR 0x58 Name Bit R/W Default Description STANDBYDLY 1 to 0 RW 01 Controls delay of Standby pin after synchronization 0 — No additional delay 1 — 32 kHz cycle additional delay 2 — 32 kHz cycle additional delay 3 — 32 kHz cycle additional delay STANDBYINV 2 RW 0 Controls polarity of STANDBY pin 0 — Standby pin input active high 1 — Standby pin input active low POR_DLY 5 to 3 RW1S 000 Controls delay of RESETBMCU pin after power up (loaded from OTP) 000 — RESETBMCU goes high 2 ms after last regulator 010 — RESETBMCU goes high 4 ms after last regulator 011 — RESETBMCU goes high 8 ms after last regulator 100 — RESETBMCU goes high 16 ms after last regulator 101 — RESETBMCU goes high 128 ms after last regulator 110 — RESETBMCU goes high 256 ms after last regulator 111 — RESETBMCU goes high 1024 ms after last regulator TGRESET 7 to 6 RW1S 00 Controls duration for which ONKEY has to be pushed low for a global reset (part goes to REGS_DISABLE) 00 — 4 s 01 — 8 s 10 — 12 s 11 — 16 s Table 136. Register PWRCTRL1 - ADDR 0x59 Name Bit R/W Default PWRONDBNC 1 to 0 RW 00 Controls debounce of PWRON when in push-button mode (PWRON_CFG = 1) 00 — 31.25 ms falling edge; 31.25 ms rising edge 01 — 31.25 ms falling edge; 31.25 ms rising edge 10 — 125 ms falling edge; 31.25 ms rising edge 11 — 750 ms falling edge; 31.25 ms rising edge ONKEYDBNC 3 to 2 RW 00 Controls debounce of ONKEY push-button 00 — 31.25 ms falling edge; 31.25 ms rising edge 01 — 31.25 ms falling edge; 31.25 ms rising edge 10 — 125 ms falling edge; 31.25 ms rising edge 11 — 750 ms falling edge; 31.25 ms rising edge PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 99 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 136. Register PWRCTRL1 - ADDR 0x59...continued Name Bit R/W Default PWRONRSTEN 4 RW 0 Description Enables going to REGS_DISABLE or Sleep mode when PWRON_CFG = 1. See Section 10 "PF1550 state machine" for details. 0 — Long press on PWRON button does not take state to REGS_DISABLE or Sleep 1 — Long press on PWRON button takes state to REGS_DISABLE or Sleep RESTARTEN 5 RW 0 Enables restart of system when PWRON push-button is held low for 5 s 0 — No impact 1 — When going to REGS_DISABLE via a long press of PWRON button, holding it low for 1 more second takes state back to RUN (Equally, a 5 second push restarts the system) REGSCPEN 6 RW 0 Shuts down LDO if it enters a current limit fault. Controls LDO1, LDO2, and LDO3. 0 — LDO does not shut down in the event of a current limit fault. Continues to current limit 1 — LDO is turned off when it encounters a current limit fault ONKEY_RST_EN 7 RW 1 Enables turning off of system via ONKEY. See Section 10 "PF1550 state machine" for details. 0 — ONKEY cannot be used to turn off or restart system 1 — ONKEY can be used to turn off or restart system Table 137. Register PWRCTRL2 - ADDR 0x5A Name Bit R/W Default Description UVDET 1 to 0 RW1S 00 Sets UVDET threshold 00 — Rising 2.65 V; Falling 2.55 V 01 — Rising 2.8 V; Falling 2.7 V 10 — Rising 3.0 V; Falling 2.9 V 11 — Rising 3.1 V; Falling 3.0 V LOW_SYS_WARN 3 to 2 RW 00 Sets LOW_SYS_WARN threshold 00 — Rising 3.3 V; Falling 3.1 V 01 — Rising 3.5 V; Falling 3.3 V 10 — Rising 3.7 V; Falling 3.5 V 11 — Rising 3.9 V; Falling 3.7 V UNUSED 7 to 4 — — Unused Table 138. Register PWRCTRL3 - ADDR 0x5B Name Bit R/W Default GOTO_SHIP 0 RW 0 Set this bit to go to SHIP mode from any state. See Section 10 "PF1550 state machine" for details. 0 — No impact 1 — PF1550 enters SHIP mode GOTO_CORE_OFF 1 RW 0 Set this bit to go to CORE_OFF mode once in REGS_DISABLE state 0 — No impact 1 — PF1550 enters CORE_OFF mode when in REGS_DISABLE state 7 to 2 — — Unused UNUSED PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 100 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 139. Register SW1_PWRDN_SEQ - ADDR 0x5F Name Bit R/W Default SW1_PWRDN_SEQ 2 to 0 RW1S 000 UNUSED 7 to 3 — — Description This contains same value as power-up sequence value by default. Power-up sequence is in mirror registers. xxx = The power-down sequencer performs the function opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_ SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_ PWRDN_SEQ[2:0] setting. This way, by default, power-down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_ PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the powerdown sequencer is bypassed and all the regulators are turned off at once. Unused Table 140. Register SW2_PWRDN_SEQ - ADDR 0x60 Name Bit R/W Default SW2_PWRDN_SEQ 2 to 0 RW1S 000 UNUSED 7 to 3 — — PF1550 Product data sheet Description This contains same value as power-up sequence value by default. Power-up sequence is in mirror registers. xxx = The power-down sequencer performs the function opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_ SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_ PWRDN_SEQ[2:0] setting. This way, by default, power-down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_ PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the powerdown sequencer is bypassed and all the regulators are turned off at once. Unused All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 101 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 141. Register SW2_PWRDN_SEQ - ADDR 0x61 Name Bit R/W Default SW3_PWRDN_SEQ 2 to 0 RW1S 000 UNUSED 7 to 3 — — Description This contains same value as power-up sequence value by default. Power-up sequence is in mirror registers. xxx = The power-down sequencer performs the function opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_ SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_ PWRDN_SEQ[2:0] setting. This way, by default, power-down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_ PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the powerdown sequencer is bypassed and all the regulators are turned off at once. Unused Table 142. Register LDO1_PWRDN_SEQ - ADDR 0x62 Name Bit R/W Default LDO1_PWRDN_SEQ 2 to 0 RW1S 000 UNUSED 7 to 3 — — PF1550 Product data sheet Description This contains same value as power-up sequence value by default. Power-up sequence is in mirror registers. xxx = The power-down sequencer performs the function opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_ SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_ PWRDN_SEQ[2:0] setting. This way, by default, power-down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_ PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the powerdown sequencer is bypassed and all the regulators are turned off at once. Unused All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 102 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 143. Register LDO2_PWRDN_SEQ - ADDR 0x63 Name Bit R/W Default LDO2_PWRDN_SEQ 2 to 0 RW1S 000 UNUSED 7 to 3 — — Description This contains same value as power-up sequence value by default. Power-up sequence is in mirror registers. xxx = The power-down sequencer performs the functional opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_ PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_ SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_ PWRDN_SEQ[2:0] setting. This way, by default, power-down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_ PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the powerdown sequencer is bypassed and all the regulators are turned off at once. Unused Table 144. Register LDO3_PWRDN_SEQ - ADDR 0x64 Name Bit R/W Default LDO3_PWRDN_SEQ 2 to 0 RW1S 000 UNUSED 7 to 3 — — PF1550 Product data sheet Description This contains same value as power-up sequence value by default. Power-up sequence is in mirror registers. xxx = The power-down sequencer performs the function opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_ SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_ PWRDN_SEQ[2:0] setting. This way, by default, power-down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_ PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the powerdown sequencer is bypassed and all the regulators are turned off at once. Unused All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 103 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 145. Register VREFDDR_PWRDN_SEQ - ADDR 0x65 Name Bit R/W Default VREFDDR_PWRDN_S EQ 2 to 0 RW1S 000 UNUSED 7 to 3 — — Description This contains same value as power-up sequence value by default. Power-up sequence is in mirror registers. xxx = The power-down sequencer performs the function opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_ SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_ PWRDN_SEQ[2:0] setting. This way, by default, power-down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_ PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the powerdown sequencer is bypassed and all the regulators are turned off at once. Unused Table 146. Register STATE_INFO - ADDR 0x67 Name Bit R/W Default Description STATE 5 to 0 R 000000 Indicates machine state 000000 — Wait status 001100 — RUN state 001101 — STANDBY state 001110 — SLEEP/LPSR state 101011 — REGS_DISABLE state Other bits are reserved UNUSED 7 to 6 — — Unused Table 147. Register I2C_ADDR - ADDR 0x68 Name I2C_SLAVE_ADDR_L SBS USE_DEFAULT_ADD R PF1550 Product data sheet Bit R/W Default 2 to 0 R 000 7 RW 0 Description Loaded from fuses. But read only in functional space. 000 — Slave Address: 0x08 001 — Slave Address: 0x09 010 — Slave Address: 0x0A 011 — Slave Address: 0x0B 100 — Slave Address: 0x0C 101 — Slave Address: 0x0D 110 — Slave Address: 0x0E 111 — Slave Address: 0x0F DEFAULT ADDR All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 104 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 148. Register RC_16MHZ - ADDR 0x6B Name Bit R/W Default REQ_16MHZ 0 RW 0 Enables 16 MHz clock 0 — 16 MHz clock enable controlled by state machine 1 — 16 MHz clock always enabled REQ_ACORE_ON 1 RW 0 Controls Analog core enable 0 — Analog core enable controlled by state machine 1 — Analog core always on REQ_ACORE_HIPWR 2 RW 0 Controls Low-power mode of the analog core 0 — Analog core Low-power mode controlled by state machine 1 — Analog core never in Low-power mode 7 to 3 — — Unused UNUSED Description Table 149. Register KEY1 - ADDR 0x6B Name Bit R/W Default KEY1 7 to 0 RW 0x00 Description Unused 12.2 Specific Charger Registers (Offset is 0x80) Table 150. Register CHG_INT - ADDR 0x00 Name Bit SUP_I 0 BAT2SOC_I 1 BAT_I R/W Default [1] 0 Supplement mode interrupt 0 — The SUP_OK bit interrupt has not occurred or been cleared 1 — The SUP_OK bit interrupt has occurred Reset condition — VCOREDIG_RSTB RW1S 0 VBATT to VSYS overcurrent interrupt 0 — The BAT2SOC_OK interrupt has not occurred or been cleared 1— The BAT2SOC _OK bit interrupt has occurred Reset condition — VCOREDIG_RSTB 2 RW1S 0 Battery interrupt 0 — The BAT_OK interrupt has not occurred or been cleared 1 — The BAT_OK interrupt has occurred Reset condition — VCOREDIG_RSTB CHG_I 3 RW1S 0 Charger interrupt 0 — The CHG_OK interrupt has not occurred or been cleared 1 — The CHG_OK interrupt has occurred Reset condition — VCOREDIG_RSTB RSVD4 4 RW1S 0 Unused VBUS_I 5 RW1S 0 VBUS interrupt 0 — The VBUS_OK interrupt has not occurred or been cleared 1 — The VBUS_OK interrupt has occurred Reset condition — VCOREDIG_RSTB VBUS_DPM_I 6 RW1S 0 VBUS_DPM interrupt 0 — The VBUS_DPM _OK interrupt has not occurred or been cleared 1 — The VBUS_DPM _OK interrupt has occurred Reset condition — VCOREDIG_RSTB PF1550 Product data sheet RW1S Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 105 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 150. Register CHG_INT - ADDR 0x00...continued Name Bit R/W Default THM_I 7 RW1S 0 [1] Description THM interrupt. Occurs when Warm/Cool thresholds are crossed or when thermal foldback is active. After the interrupt has occurred, THM_OK bit can be read to know the source of the interrupt. If THM_OK = 0, warm/cool thresholds are crossed If THM_OK = 1, thermal foldback is active 0 — THM interrupt has not occurred or has been cleared 1 — THM interrupt has occurred Reset condition — VCOREDIG_RSTB Load from OTP fuse, Read, and Write Table 151. Register CHG_INT_MASK - ADDR 0x02 Name Bit R/W Default SUP_M 0 RW 1 Supplement mode interrupt mask 0 — Unmasked 1 — Masked Reset condition — VCOREDIG_RSTB BAT2SOC_M 1 RW 1 VBATT to VSYS overcurrent interrupt mask 0 — Unmasked 1 — Masked Reset condition — VCOREDIG_RSTB BAT_M 2 RW 1 Battery interrupt mask 0 — Unmasked 1 — Masked Reset condition — VCOREDIG_RSTB CHG_M 3 RW 1 Charger interrupt mask 0 — Unmasked 1 — Masked Reset condition — VCOREDIG_RSTB RSVD4 4 RW 1 Unused VBUS_M 5 RW 1 VBUS interrupt mask 0 — Unmasked 1 — Masked Reset condition — VCOREDIG_RSTB VBUS_DPM_M 6 RW 1 VBUS_DPM interrupt mask 0 — Unmasked 1 — Masked Reset condition — VCOREDIG_RSTB THM_M 7 RW 1 THM interrupt mask 0 — Unmasked 1 — Masked Reset condition — VCOREDIG_RSTB PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 106 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 152. Register CHG_INT_OK - ADDR 0x04 Name Bit R/W Default SUP_OK 0 R 0 Description Supplement mode indicator 0 — Supplement mode not detected 1 — Supplement mode detected Reset condition — VCOREDIG_RSTB BAT2SOC_OK 1 R 0 Single-bit battery overcurrent indicator 0 — Battery to VSYS has not hit overcurrent limit 1 — Battery to VSYS has hit overcurrent limit (BATTOC_SNS bit = 1) Reset condition — VCOREDIG_RSTB BAT_OK 2 R 1 Single-bit battery status indicator. See BATT_SNS for more information. 0 — The battery has an issue or the charger has been suspended, for example, BATT_SNS = 0x02 or 0x05 or 0x06 1 — The battery is okay, for example, BATT_SNS ≠ 0x02 or 0x05 or 0x06 Reset condition — VCOREDIG_RSTB CHG_OK 3 R 0 Single-bit charger status indicator. See CHG_SNS for more information. Reset condition — VCOREDIG_RSTB 0 — The charger is not charging, has suspended charging or Thermal Reg = 1, for example, CHG_SNS ≠ 0x00 or 0x01 or 0x02 or 0x03 1 — The charger is okay, for example, CHG_SNS = 0x00 or 0x01 or 0x02 or 0x03 Reset condition — VCOREDIG_RSTB RSVD4 4 R 0 Unused VBUS_OK 5 R 0 Single-bit VBUS_LIN input status indicator. See VBUS_LIN_SNS for more information. 0 — The VBUS_LIN input is invalid. For example, VBUS_VALID = 0. 1 — The VBUS_LIN input is valid. For example, VBUS_VALID = 1. Reset condition — VCOREDIG_RSTB VBUS_DPM_OK 6 R 0 VBUS_DPM status indicator. This register provides status of input Dynamic Power Management threshold. 0 — Not in VBUS_DPM mode 1 — VBUS_DPM mode Reset condition — VCOREDIG_RSTB THM_OK 7 R 1 Thermistor status indicator. This register provides information on whether battery temperature is within or outside the thermistor cool/warm thresholds. 0 — Thermistor outside cool and warm thresholds 1 — Thermistor between cool and warm thresholds Reset condition — VCOREDIG_RSTB Table 153. Register VBUS_SNS - ADDR 0x06 Name RSVD0 VBUS_UVLO_SNS PF1550 Product data sheet Bit R/W Default Description 1 to 0 R 00 Unused 2 R 1 0 — VBUS_ LIN > VBUS_LIN_UVLO 1 — VBUS_ LIN < VBUS_LIN_UVLO or when VBUS is detached All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 107 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 153. Register VBUS_SNS - ADDR 0x06...continued Name Bit R/W Default VBUS_IN2SYS_SNS 3 R 1 Description 0 — VBUS_ LIN > VBATT + VIN2SYS 1 — VBUS_ LIN < VBATT + VIN2SYS VBUS_OVLO_SNS 4 R 0 0 — VBUS_ LIN < VBUS_LIN_OVLO 1 — VBUS_ LIN > VBUS_LIN_OVLO VBUS_VALID 5 R 0 0 — VBUS is not valid 1 — VBUS is valid, VBUS_LIN > VBUS_LIN_UVLO, VBUS_LIN > VBATT + VIN2SYS, VBUS_LIN < VBUS_LIN_OVLO Reset condition — VCOREDIG_RSTB RSVD6 6 R 0 Unused VBUS_DPM_SNS 7 R 0 VBUS_LIN DPM sense details 0 — VBUS _LIN DPM threshold has not been triggered 1 — VBUS_LIN DPM threshold has been triggered Table 154. Register CHG_SNS - ADDR 0x07 Name Bit R/W Default 3 to 0 R 1000 RSVD4 4 R 0 Unused WDT_SNS 5 R 0 Watchdog sense bit 0 — Watchdog timer has not expired 1 — Charger is off because the watchdog timer expired, CHG_OK = 0 Reset condition — VCOREDIG_RSTB CHG_SNS PF1550 Product data sheet Description Charger sense 0 — Charger is in precharge mode, CHG_OK = 1, VBATT < VPRECHG.LB, TJ < TSHDN 1 — Charger is in fast-charge constant current mode, CHG_OK = 1, VBATT < VBATREG, TJ < TSHDN 2 — Charger is in fast-charge constant voltage mode, CHG_OK = 1, VBATT = VBATREG, TJ < TSHDN 3 — Charger is in end-of-charge mode, CHG_OK = 1, VBATT ≥ VBATREG, IBAT = IEOC, TJ < TSHDN 4 — Charger is in done mode, CHG_OK = 0, VBATT > VBATREG-VRESTART, TJ < TSHDN 5 — Reserved 6 — Charger is in timer fault mode, CHG_OK = 0, VBATT < VBATOV, if BATT_SNS = 0b001 then VBATT < VBATPC, TJ < TSHDN 7 — Charger is in thermistor suspend mode, CHG_OK = 0, VBATT < VBATOV, if BATT_SNS = 0b001 then VBATT < VPRECHG.LB, TJ < TSHDN 8 — Charger is off, input invalid and/or charger is disabled, CHG_OK = 0 9 — Battery overvoltage condition 10 — Charger is off and TJ > TSHDN, CHG_OK = 0 11 — Reserved 12 — Charger block is in Linear only mode, not charging, CHG_OK = 0 13 — Reserved 14 — Reserved 15 — Reserved Reset condition — VCOREDIG_RSTB All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 108 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 154. Register CHG_SNS - ADDR 0x07...continued Name Bit R/W Default THM_SNS 6 R 0 Description Cool/Warm sense bit 0 — Thermistor temperature is between cool and warm thresholds 1 — Thermistor temperature is < Cool, or > Warm threshold Reset condition — VCOREDIG_RSTB TREG_SNS 7 R 0 Temperature regulation sense 0 — The junction temperature is less than the threshold set by REGTEMP and the full charge current limit is available 1 — The junction temperature is greater than the threshold set by REGTEMP and the charge current limit may be folding back to reduce power dissipation Reset condition — VCOREDIG_RSTB Table 155. Register BATT_SNS - ADDR 0x08 Name Bit R/W Default BATT_SNS 2 to 0 R 000 0 — 0x00 = No valid VBUS input 1 — 0x01 = VBATT < VPRECHG.LB 2 — 0x02 = the battery cannot charge beyond the precharge threshold and charging has suspended and is in timer fault mode. This condition is also reported in the CHG_SNS as 0x06. 3 — Reserved 4 — 0x04 = VPRECHG.LB < VBATT 5 — 0x05 = the battery voltage is greater than the battery overvoltage flag threshold (VBATOV). Tthis flag is generated only when there is a valid input. 6 — 0x06 = battery not detected with a valid input and after system wake-up 7 — Reserved Reset condition — VCOREDIG_RSTB RSVD3 4 to 3 RW 00 Unused 5 R 0 VBATT to VSYS overcurrent fault 0 — No fault 1 — VBATT to VSYS in high current fault Reset condition — VCOREDIG_RSTB 7 to 6 RW 00 Unused BATTOC_SNS RSVD6 Description Table 156. Register CHG_OPER- ADDR 0x09 Name CHG_OPER UNUSED PF1550 Product data sheet Bit 1 to 0 2 R/W Default [1] Description RW1S 01 Charger operation configuration 0 — charger = off, linear = off. The BATFET switch is on to allow the battery to support the system. 1 — charger = off, linear = on. When there is a valid VBUS input and no battery, the linear regulator regulates the VSYS voltage to VSYSMIN[1:0]. 2 — charger = on, linear = on. When there is a valid input, the battery is charging. VSYS is the larger of VSYSMIN and VBATT + IBAT * RBATFET. 3 — Reserved Reset condition — VCOREDIG_RSTB RW 0 Unused All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 109 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 156. Register CHG_OPER- ADDR 0x09...continued Name Bit R/W Default WDTEN 3 RW 0 Enable watchdog timer bit. While enabled, the system controller must reset the watchdog timer within the timer period (tWD) for the charger to operate normally. Reset the watchdog timer by programming WDTCLR = 0x01. 0 — Watchdog timer disabled 1 — Watchdog timer enabled Reset condition — VCOREDIG_RSTB DISBATFET 4 RW 0 VBATT to VSYS FET disable control 0 — VBATT to VSYS FET is controlled by internal state machine 1 — VBATT to VSYS FET is forced off Reset condition — VCOREDIG_RSTB 7 to 5 RW 000 UNUSED [1] Description Unused Load from OTP fuse, Read, and Write Table 157. Register CHG_TMR - ADDR 0x0A Name Bit R/W Default Description FCHGTIME 2 to 0 RW1S 010 Fast-charge timer duration (tFC) 0 — Disable 1 — 2 hrs 2 — 4 hrs 3 — 6 hrs 4 — 8 hrs 5 — 10 hrs 6 — 12 hrs 7 — 14 hrs Reset condition — VCOREDIG_RSTB EOCTIME 5 to 3 RW1S 001 End-of-charge timer setting 0 — 0 min (16 secs debounce) 1 — 10 min 2 — 20 min 3 — 30 min 4 — 40 min 5 — 50 min 6 — 60 min 7 — 70 min Reset condition — VCOREDIG_RSTB RSVD6 6 R 0 Unused TPRECHG 7 RW1S 0 Precharge timer value. Used for low battery. 0 — Precharge timer value = 30 min 1 — Precharge timer value = 45 min Reset condition — VCOREDIG_RSTB PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 110 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 158. Register CHG_EOC_CNFG - ADDR 0x0D Name Bit R/W Default 1 to 0 RW1S 01 Charger restart threshold 00 — 0x00 = 100 mV below the value programmed by CHG_CV_PRM 01 — 0x01 = 150 mV below the value programmed by CHG_CV_PRM 02 — 0x02 = 200 mV below the value programmed by CHG_CV_PRM 03 — 0x03 = disabled Reset condition — VCOREDIG_RSTB FORCE_BATT_ISO 2 RW1S 0 Unused EOC_EXIT 3 RW1S 0 Unused 6 to 4 RW 100 7 RW1S 0 CHG_RESTART IEOC EOC_MODE PF1550 Product data sheet Description End-of-charge current threshold. End-of-charge occurs during fast-charge constant voltage mode and end-of-charge current measured as battery decays to the value programmed in this register. This transition starts the end-of-charge timer (tEOC). 0 — 5 mA 1 — 10 mA 2 — 20 mA 3 — 30 mA 4 — 50 mA 5 — Reserved 6 — Reserved 7 — Reserved Reset condition — VCOREDIG_RSTB Unused All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 111 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 159. Register CHG_CURR_CNFG - ADDR 0x0E Name Bit R/W Default CHG_CC 4 to 0 RW1S 00000 PRECHGLB_THRS 6 to 5 RW1S 00 Precharge (low battery) charging voltage threshold setting 0 — 2.8 V 1 — 2.7 V (Reserved) 2 — 2.9 V (Reserved) 3 — 3.0 V (Reserved) Reset condition — VCOREDIG_RSTB 7 RW 0 Reserved RSVD7 PF1550 Product data sheet Description Fast charge current selection. When the charger is enabled, the charge current limit is set by these bits. These bits range from 100 mA to 1.0 A. 0 — 100 mA 1 — 150 mA 2 — 200 mA 3 — 250 mA 4 — 300 mA 5 — 350 mA 6 — 400 mA 7 — 450 mA 8 — 500 mA 9 — 550 mA 10 — 600 mA 11 — 650 mA 12 — 700 mA 13 — 750 mA 14 — 800 mA 15 — 850 mA 16 — 900 mA 17 — 950 mA 18 — 1000 mA 19 — 1050 mA (Reserved) 20 — 1100 mA (Reserved) 21 — 1150 mA (Reserved) 22 — 1200 mA (Reserved) 23 — 1250 mA (Reserved) 24 — 1300 mA (Reserved) 25 — 1350 mA (Reserved) 26 — 1400 mA (Reserved) 27 — 1450 mA (Reserved) 28 — 1500 mA (Reserved) 29 — 1550 mA (Reserved) 30 — 1600 mA (Reserved) 31 — 1650 mA (Reserved) Reset condition — VCOREDIG_RSTB All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 112 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 160. Register BATT_REG - ADDR 0x0F Name CHGCV PF1550 Product data sheet Bit R/W Default Description 5 to 0 RW1S 101011 Battery termination voltage setting 0 — 3.50 V 1 — 3.50 V 2 — 3.50 V 3 — 3.50 V 4 — 3.50 V 5 — 3.50 V 6 — 3.50 V 7 — 3.50 V 8 — 3.50 V 9 — 3.52 V 10 — 3.54 V 11 — 3.56 V 12 — 3.58 V 13 — 3.60 V 14 — 3.62 V 15 — 3.64 V 16 — 3.66 V 17 — 3.68 V 18 — 3.70 V 19 — 3.72 V 20 — 3.74 V 21 — 3.76 V 22 — 3.78 V 23 — 3.80 V 24 — 3.82 V 25 — 3.84 V 26 — 3.86 V 27 — 3.88 V 28 — 3.90 V 29 — 3.92 V 30 — 3.94 V 31 — 3.96 V 32 — 3.98 V 33 — 4.00 V 34 — 4.02 V 35 — 4.04 V 36 — 4.06 V 37 — 4.08 V 38 — 4.10 V 39 — 4.12 V 40 — 4.14 V 41 — 4.16 V 42 — 4.18 V 43 — 4.20 V 44 — 4.22 V 45 — 4.24 V 46 — 4.26 V All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 113 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 160. Register BATT_REG - ADDR 0x0F...continued Name Bit R/W Default Description 47 — 4.28 V 48 — 4.30 V 49 — 4.32 V 50 — 4.34 V 51 — 4.36 V 52 — 4.38 V 53 — 4.40 V 54 — 4.42 V 55 — 4.44 V 56 — 4.44 V 57 — 4.44 V 58 — 4.44 V 59 — 4.44 V 60 — 4.44 V 61 — 4.44 V 62 — 4.44 V 63 — 4.44 V Reset condition — VCOREDIG_RSTB VSYSMIN 7 to 6 RW1S 00 Minimum system regulation voltage (VSYSMIN) 0 — 3.5 V 1 — 3.7 V 2 — 4.3 V 3 — Reserved Reset condition — VCOREDIG_RSTB Table 161. Register BATFET_CNFG - ADDR 0x11 Name Bit R/W Default 1 to 0 RW 00 Watchdog timer clear bits. Writing "01" to these bits clears the watchdog timer when the watchdog timer is enabled. 0 — The watchdog timer is not cleared 1 — The watchdog timer is cleared 2 — The watchdog timer is not cleared 3 — The watchdog timer is not cleared Reset condition — VCOREDIG_RSTB WD_BATFET_OFF 2 RW 0 Watchdog timer BATFET control 0 — Not used in PF1550. See WDFLT_BFET_EN bit in Fault_BATFET_CNFG register. 1 — Not used in PF1550. See WDFLT_BFET_EN bit in Fault_BATFET_CNFG register. Reset condition — VCOREDIG_RSTB BOVRC_DISBATFET 3 RW1S 0 Disable BATFET in case of battery overcurrent limit 0 — Charger controls BATFET switch; BATFET is turned off in case of battery overcurrent occurs for 16 ms (default) 1 — BATFET is not turned off when battery overcurrent occurs. Charger operation remains undisturbed by overcurrent event. Reset condition — VCOREDIG_RSTB WDTCLR PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 114 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 161. Register BATFET_CNFG - ADDR 0x11...continued Name Bit R/W Default 5 to 4 RW1S 11 VBATT to VSYS FET overcurrent threshold, 2 bits adjustment 0 — Disabled 1 — 2.2 A typ 2 — 2.8 A typ 3 — 3.2 A typ Reset condition — VCOREDIG_RSTB WD_TIME 6 RW 0 Sets watchdog timer value 0 — 80 s 0 — 32 s Reset condition — VCOREDIG_RSTB BOVRC_NOVBUS 7 RW 0 Enables/disables battery overcurrent protection when no VBUS is present 0 — Disables battery overcurrent protection when no VBUS is present 1 — Enables battery overcurrent protection when no VBUS is present Reset condition — VCOREDIG_RSTB BATFET_OC Description Table 162. Register THM_REG_CNFG - ADDR 0x12 Name Bit R/W Default THM_CNFG 1 to 0 RW1S 01 Thermistor configuration. 2 bits adjustment. 0 — Thermistor not in control of charger. TCOOL and TWARM interrupts are still generated. Thermistor Suspend mode is not entered in this setting. CC and CV values are not altered when TCOOL/cold, TWARM/hot thresholds are crossed. 1 — Thermistor control in charger. Charging stops when battery temperature > THOT or < TCOLD. 2 — JEITA 1 settings - Thermistor control in charger. Charging current and battery regulation voltage is reduced at battery temperature > TWARM and < TCOOL. 3 — JEITA 2 settings - Thermistor control in charger. Charging current is reduced at battery temperature > TWARM and < TCOOL. Charger voltage is not changed. Reset condition — VCOREDIG_RSTB REGTEMP 3 to 2 RW1S 01 Junction temperature thermal regulation loop set point. 2-bit adjustments. The charger's target current limit starts to fold back and the TREG_SNS bit is set if the junction temperature is greater than the REGTEMP set point. 0 — 80 °C 1 — 95 °C 2 — 110 °C 3 — 125 °C (Reserved) Reset condition — VCOREDIG_RSTB THM_COLD 4 RW1S 0 Thermistor cold temperature selection 0 — 0 °C 1 — –10 °C Reset condition — VCOREDIG_RSTB THM_HOT 5 RW1S 0 Thermistor hot temperature selection 0 — 60 °C 1 — 55 °C Reset condition — VCOREDIG_RSTB RSVD6 6 RW 0 Unused PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 115 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 162. Register THM_REG_CNFG - ADDR 0x12...continued Name TEMP_FB_EN Bit R/W Default 7 RW1S 0 Description Enable/disable thermal foldback current function 0 — Thermal foldback disabled 1 — Thermal foldback enabled Reset condition — VCOREDIG_RSTB Table 163. Register VBUS_INLIM_CNFG - ADDR 0x14 Name Bit R/W Default RSVD0 2 to 0 RW 000 VBUS_LIN_ILIM 7 to 3 RW1S 01101 PF1550 Product data sheet Description Unused Maximum input current limit selection. 5-bit adjustment from 10 mA to 1500 mA. 0 — 10 mA 1 — 15 mA 2 — 20 mA 3 — 25 mA 4 — 30 mA 5 — 35 mA 6 — 40 mA 7 — 45 mA 8 — 50 mA 9 — 100 mA 10 — 150 mA 11 — 200 mA 12 — 300 mA 13 — 400 mA 14 — 500 mA 15 — 600 mA 16 — 700 mA 17 — 800 mA 18 — 900 mA 19 — 1000 mA 20 — 1500 mA 21 — Reserved 22 — Reserved 23 — Reserved 24 — Reserved 25 — Reserved 26 — Reserved 27 — Reserved 28 — Reserved 29 — Reserved 30 — Reserved 31 — Reserved Reset condition — CHGPOK_RSTB All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 116 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 164. Register VBUS_LIN_DPM - ADDR 0x15 Name Bit R/W Default VBUS_DPM_REG 2 to 0 RW1S 000 Description VBUS regulation voltage (DPM mode) 0 — 3.90 V 1 — 4.00 V 2 — 4.10 V 3 — 4.20 V 4 — 4.30 V 5 — 4.40 V 6 — 4.50 V 7 — 4.60 V Reset condition — VCOREDIG_RSTB PRECHGDBATT_T HRSH 4 to 3 RW1S 00 Precharge threshold 0 — Reserved 1 — Reserved 2 — Reserved 3 — Reserved VIN_DPM_STOP 5 RW1S 0 Dynamic input power management panic stop threshold 0 — 200 mV 1 — 250 mV Reset condition — VCOREDIG_RSTB RSVD6 6 R 0 Unused FET_SCALE 7 RW1S 0 Enables/disables BATFET scaling 0 — Reserved 1 — Reserved Reset condition — VCOREDIG_RSTB Table 165. Register USB_PHY_LDO_CNFG - ADDR 0x16 Name Bit R/W Default ACTDISPHY 0 RW1S 1 Active discharger enable bit for USBPHY 0 — No active discharge 1 — Active discharge when regulator disabled Reset condition — VCOREDIG_RSTB USBPHY 1 RW1S 0 USBPHY voltage setting register 0 — 3.3 V 1 — 4.9 V Reset condition — VCOREDIG_RSTB USBPHYLDO 2 RW1S 0 USBPHY LDO enable 0 — Disabled 1 — Enabled Reset condition — VCOREDIG_RSTB RSVD3 3 RW 0 Unused RSVD4 5 to 4 RW 00 Unused RSVD6 7 to 6 RW 00 Unused PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 117 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 166. Register DBNC_DELAY_TIME - ADDR 0x18 Name Bit R/W Default VBUS_OV_TDB 1 to 0 RW1S 00 Description VBUS overvoltage debounce delay 0 — 10 µs (Reserved) 1 — 100 µs 2 — 1 ms 3 — 10 ms Reset condition — VCOREDIG_RSTB USB_PHY_TDB 3 to 2 RW1S 00 USBPHY debounce timer - not used in PF1550 0 — 0 ms 1 — 16 ms 2 — 32 ms 3 — Not used Reset condition — VCOREDIG_RSTB SYS_WKUP_DLY 5 to 4 RW1S 00 System wake-up time 0 — 8.0 ms 1 — 16 ms 2 — 32 ms 3 — 100 ms Reset condition — VCOREDIG_RSTB RSVD6 7 to 6 RW 00 Unused Table 167. Register CHG_INT_CNFG - ADDR 0x19 Name Bit R/W Default CHG_INT_GEN 0 RW1S 0 Determines if an interrupt is generated at every mode transition in charger 0 — Interrupt is not generated at every mode transition except transition from Fast Charge to CV 1 — Interrupt is generated at every mode transition (Fast Charge, CV, EOC, DONE, No Charger) Reset condition — VCOREDIG_RSTB EOC_INT 1 RW1S 0 Interrupt bit generated at end-of-charge 0 — No interrupt bit is generated when end-of- charge current is triggered 1 — Interrupt bit is generated when end-of-charge current is triggered Reset condition — VCOREDIG_RSTB 7 to 2 RW 000000 RSVD2 Description Unused Table 168. Register THM_ADJ_SETTING - ADDR 0x1A Name Bit R/W Default THM_WARM 0 RW1S 0 Thermistor warm threshold setting 0 — 45 °C 1 — 50 °C Reset condition — VCOREDIG_RSTB THM_COOL 1 RW1S 0 Thermistor cool threshold setting 0 — 15 °C 1 — 10 °C Reset condition — VCOREDIG_RSTB PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 118 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 168. Register THM_ADJ_SETTING - ADDR 0x1A...continued Name Bit R/W Default CV_ADJ 3 to 2 RW1S 00 Description JEITA Thermistor battery termination voltage subtraction setting 0 — 60 mV 1 — 100 mV 2 — 160 mV 3 — 200 mv Reset condition — VCOREDIG_RSTB CC_ADJ 5 to 4 RW1S 00 JEITA Thermistor battery charging current setting (percentage of IFC) 0 — 25 % 1 — 50 % 2 — 75 % 3 — 100 % Reset condition — VCOREDIG_RSTB RSVD6 7 to 6 RW 00 Unused Table 169. Register VBUS2SYS_CNFG - ADDR 0x1B Name VBUS2SYS_TDB VBUS2SYS_THRSH RSVD3 PF1550 Product data sheet Bit R/W Default 1 to 0 RW1S 00 Description VBUS to VSYS comparator debounce time 0 — Reserved 1 — 100 µs 2 — 1 ms 3 — 10 ms Reset condition — VCOREDIG_RSTB 2 RW1S 0 VBUS to VSYS comparator threshold setting 0 — 50 mV 1 — 175 mV Reset condition — VCOREDIG_RSTB 7 to 3 RW 00000 Unused All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 119 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 170. Register LED_PWM - ADDR 0x1C Name Bit R/W Default Description LED_PWM 5 to 0 RW 000000 LED PWM duty cycle setting 0 — 0/32 (Off) 1 — 1/32 2 — 2/32 3 — 3/32 4 — 4/32 5 — 5/32 6 — 6/32 7 — 7/32 8 — 8/32 9 — 9/32 10 — 10/32 11 — 11/32 12 — 12/32 13 — 13/32 14 — 14/32 15 — 15/32 16 — 16/32 17 — 17/32 18 — 18/32 19 — 19/32 20 — 20/32 21 — 21/32 22 — 22/32 23 — 23/32 24 — 24/32 25 — 25/32 26 — 26/32 27 — 27/32 28 — 28/32 29 — 29/32 30 — 30/32 31 — 31/32 32 and higher — 32/32 Reset condition — VCOREDIG_RSTB LED_RAMP 6 RW 0 Enable PWM ramp enable 0 — Ramp disable 1 — Ramp enable Reset condition — VCOREDIG_RSTB LED_EN 7 RW 0 LED driver enable 0 — Disabled 1 — Enabled Reset condition — VCOREDIG_RSTB Table 171. Register FAULT_BATFET_CNFG - ADDR 0x1D Name OVFLT_BFET_EN PF1550 Product data sheet Bit R/W Default 0 RW1S 0 Description BATFET control during battery overvoltage 0 — BATFET is opened during battery overvoltage 1 — BATFET remains closed Reset condition — VCOREDIG_RSTB All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 120 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 171. Register FAULT_BATFET_CNFG - ADDR 0x1D...continued Name Bit R/W Default WDFLT_BFET_EN 1 RW1S 0 BATFET control during watchdog fault 0 — BATFET is opened during watchdog fault 1 — BATFET remains closed Reset condition — VCOREDIG_RSTB THMSUS_BFET_EN 2 RW1S 0 BATFET control during thermistor fault (< Cold or > Hot) 0 — BATFET is opened during battery thermistor fault 1 — BATFET remains closed Reset condition — VCOREDIG_RSTB TSHDN_BFET_EN 3 RW1S 0 BATFET control during thermal shutdown 0 — BATFET is opened during thermal shutdown 1 — BATFET remains closed Reset condition — VCOREDIG_RSTB TMRFLT_BFET_EN 4 RW1S 0 BATFET control during charger timer fault 0 — BATFET is opened during charger timer fault 1 — BATFET remains closed Reset condition — POR RSVD5 5 RW1S 0 Unused 7 to 6 RW1S 00 Reserved CTRL_CHGR_BET A_ SEL Description Table 172. Register LED_CNFG - ADDR 0x1E Name Bit R/W Default LED_FREQ 1 to 0 RW 00 LED driver PWM frequency setting 0 — 1.0 Hz 1 — 0.5 Hz 2 — 256 Hz 3 — 8.0 Hz Reset condition — VCOREDIG_RSTB LED_CURRENT 3 to 2 RW1S 00 LED driver current amplitude setting 0 — Reserved 1 — 6.0 mA 2 — Reserved 3 — Reserved Reset condition — VCOREDIG_RSTB LED_CFG 4 RW1S 0 Controls LED on/blinking mode 0 — LED on during charging; flashing during charger fault; off in DONE state 1 — LED flashing during charging; on during charger fault; off in DONE state Reset condition — VCOREDIG_RSTB LEDOVRD 5 RW 0 Enable software control of LED 0 — LED controlled by state machine 1 — LED controlled via software Reset condition — VCOREDIG_RSTB 7 to 6 RW 00 Unused RSVD4 PF1550 Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 121 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 173. Register LED_CNFG - ADDR 0x1F Name CHGR_KEY2 Bit R/W Default 7 to 0 RW 0x00 Description Reserved 12.3 Register PMIC bitmap VCOREDIG_PORB PS_END_RSTB [1] [2] REGS_DISABLE_TOG_RSTB [1] [2] [3] [3] Bits reset by invalid VCOREDIG Bits reset by PORB or RESETBMCU Bits reset by pulse to REGS_DISABLE mode Table 174. Register PMIC bitmap Address Register name BITS[7:0] 7 0x00 0x01 0x02 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F DEVICE_ID OTP_FLAVOR SILICON_REV INT_CATEGORY SW_INT_STAT0 SW_INT_MASK0 SW_INT_ SENSE0 SW_INT_STAT1 SW_INT_MASK1 SW_INT_ SENSE1 SW_INT_STAT2 SW_INT_MASK2 6 5 4 3 2 FAMILY[3:7] Name 1 0 DEVICE_ID[2:0] Reset 0 1 1 1 1 1 0 0 Type R R R R R R R R Name — — Reset 0 0 0 0 0 0 0 0 Type — — R R R R R R OTP_FLAVOR[5:0] FAB_FIN[7:6] Name FULL_LAYER_REV[5:3] METAL_LAYER_REV[2:0] Reset 0 0 0 0 1 0 0 0 Type R R R R R R R R Name MISC_INT TEMP_INT Reset 0 0 0 0 0 0 0 0 Type R R R R R R R R Name — — — — — SW3_LS_I SW2_LS_I SW1_LS_I Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1C RW1C RW1C Name — — — — — Reset 0 0 0 0 0 1 1 1 Type — — — — — RW RW RW Name — — — — — SW3_LS_S SW2_LS_S SW1_LS_S Reset 0 0 0 0 0 0 0 0 Type — — — — — R R R Name — — — — — SW3_HS_I SW2_HS_I SW1_HS_I Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1C RW1C RW1C Name — — — — — Reset 0 0 0 0 0 1 1 1 Type — — — — — RW RW RW Name — — — — — SW3_HS_S SW2_HS_S SW1_HS_S Reset 0 0 0 0 0 0 0 0 Type — — — — — R R R Name — — — — — — ONKEY_INT LDO_INT SW3_INT SW2_INT SW3_LS_M SW3_HS_M SW1_INT SW2_LS_M SW2_HS_M SW2_DVS_ DONE_I CHG_INT SW1_LS_M SW1_HS_M SW1_DVS_ DONE_I Reset 0 0 0 0 0 0 0 0 Type — — — — — — RW1C RW1C Name — — — — — — SW2_DVS_ DONE_M SW1_DVS_ DONE_M Reset 0 0 0 0 0 0 1 1 Type — — — — — — RW RW PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 122 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 174. Register PMIC bitmap...continued Address Register name 0x10 0x18 0x19 0x1A 0x20 0x21 0x22 0x24 0x25 0x26 0x28 0x29 0x2A 0x30 0x32 0x33 0x34 0x35 SW_INT_ SENSE2 LDO_INT_STAT0 LDO_INT_ MASK0 LDO_INT_ SENSE0 TEMP_INT_ STAT0 TEMP_INT_ MASK0 TEMP_INT_ SENSE0 ONKEY_INT_ STAT0 ONKEY_INT_ MASK0 ONKEY_INT_ SENSE0 MISC_INT_ STAT0 MISC_INT_ MASK0 MISC_INT_ SENSE0 COINCELL_ CONTROL SW1_VOLT SW1_STBY_ VOLT SW1_SLP_VOLT SW1_CTRL BITS[7:0] Name 7 6 5 4 3 2 — — — — — — 1 SW2_DVS_S 0 SW1_DVS_S Reset 0 0 0 0 0 0 0 0 Type — — — — — — R R Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1C RW1C RW1C Name — — — — — Reset 0 0 0 0 0 1 1 1 Type — — — — — RW RW RW Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — R R R Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1C — RW1C Name — — — — — THERM125M — THERM110M Reset 0 0 0 0 1 1 1 1 Type — — — — — RW — RW Name — — — — — LDO3_FAULTI LDO2_FAULTI LDO3_FAULTM LDO3_FAULTS LDO2_FAULTM LDO2_FAULTS THERM125I — THERM125S — LDO1_FAULTI LDO1_FAULTM LDO1_FAULTS THERM110I THERM110S Reset 0 0 0 0 0 0 0 0 Type — — — — — R — R Name — — ONKEY_8SI Reset 0 0 0 0 0 0 0 0 Type — — RW1C RW1C RW1C RW1C RW1C RW1C Name — — ONKEY_8SM ONKEY_4SM ONKEY_3SM ONKEY_2SM ONKEY_1SM Reset 0 0 1 1 1 1 1 1 Type — — RW RW RW RW RW RW Name — — ONKEY_8SS Reset 0 0 0 0 0 0 0 0 Type — — R R R R R R Name — — — PWRON_I PWRDN_I PWRUP_I ONKEY_4SI ONKEY_4SS SYS_OVLO_I ONKEY_3SI ONKEY_2SI ONKEY_3SS LOW_SYS_ WARN_I ONKEY_2SS ONKEY_1SI ONKEY_1SS ONKEY_PUSHI ONKEY_PUSHM ONKEY_PUSHS Reset 0 0 0 0 0 0 0 0 Type — — — RW1C RW1C RW1C RW1C RW1C Name — — — SYS_OVLO_M LOW_SYS_ WARN_M PWRON_M PWRDN_M PWRUP_M Reset 0 0 0 1 1 1 1 1 Type — — — RW RW RW RW RW Name — — — LOW_SYS_ WARN_S PWRON_S PWRDN_S SYS_OVLO_S PWRUP_S Reset 0 0 0 0 0 0 0 0 Type — — — R R R R R Reset 0 0 0 0 0 0 0 0 Type — — — RW RW RW RW RW Name — — Reset 0 0 0 0 0 0 0 0 Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — Reset 0 0 0 0 0 0 0 0 Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — Reset 0 0 0 0 0 0 0 0 Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name Name VCOIN[3:0] COINCHEN SW1_RDIS_ENB SW1_FPWM SW1_VOLT[5:0] SW1_STBY_VOLT[5:0] SW1_SLP_VOLT[5:0] SW1_FPWM_ IN_DVS SW1_ DVSSPEED SW1_LPWR SW1_OMODE SW1_STBY_EN SW1_EN Reset 0 0 0 0 0 0 0 0 Type RW1S RW RW RW1S RW RW RW1S RW1S PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 123 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 174. Register PMIC bitmap...continued Address Register name 0x36 0x38 0x39 0x3A 0x3B 0x3C 0x3E 0x3F 0x40 0x41 0x42 0x48 0x4A 0x4C 0x4D 0x4F 0x50 0x52 0x53 SW1_CTRL1 SW2_VOLT SW2_STBY_ VOLT SW2_SLP_VOLT SW2_CTRL SW2_CTRL1 SW3_VOLT SW3_STBY_ VOLT SW3_SLP_VOLT SW3_CTRL SW3_CTRL1 VSNVS_CTRL VREFDDR_ CTRL LDO1_VOLT LDO1_CTRL LDO2_VOLT LDO2_CTRL LDO3_VOLT LDO3_CTRL BITS[7:0] Name 7 6 5 4 — — — SW1_TMODE_SEL 3 2 — 1 0 SW1_ILIM[1:0] — Reset 0 0 0 0 0 0 0 0 Type — — — RW — — RW1S RW1S Name — — Reset 0 0 0 0 0 0 0 0 Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — Reset 0 0 0 0 0 0 0 0 Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — Reset 0 0 0 0 0 0 0 0 Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name SW2_RDIS_ENB SW2_FPWM SW2_VOLT[5:0] SW2_STBY_VOLT[5:0] SW2_SLP_VOLT[5:0] SW2_FPWM_ IN_DVS SW2_ DVSSPEED SW2_LPWR SW2_OMODE SW2_STBY_EN SW2_EN Reset 0 0 0 0 0 0 0 0 Type RW1S RW RW RW1S RW RW RW1S RW1S Name — — — SW2_TMODE_SEL — — Reset 0 0 0 0 0 0 0 0 Type — — — RW — — RW1S RW1S Name — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — RW1S RW1S RW1S RW1S Name — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — RW1S RW1S RW1S RW1S Name — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — RW1S RW1S RW1S RW1S Name SW3_RDIS_ENB SW3_FPWM — SW3_ DVSSPEED SW2_ILIM[1:0] SW3_VOLT[3:0] SW3_STBY_VOLT[3:0] SW3_SLP_VOLT[3:0] SW3_LPWR SW3_OMODE SW3_STBY_EN SW3_EN Reset 0 0 0 0 0 0 0 0 Type RW1S RW — RW1S RW RW RW1S RW1S Name — — — SW3_TMODE_SEL — — Reset 0 0 0 0 0 0 0 0 Type — — — RW — — RW1S RW1S Name — — Reset 0 0 0 0 0 0 0 0 Type — — RW RW RW RW1S RW1S RW1S Name — — — — LIBGDIS FORCEBOS SW3_ILIM[1:0] VSNVS_VOLT[2:0] CLKPULSE VREFDDR_ LPWR VREFDDR_ OMODE VREFDDR_ STBY_EN VREFDDR_EN Reset 0 0 0 0 0 0 0 0 Type — — — — RW RW RW1S RW1S Name — — — Reset 0 0 0 0 0 0 0 0 Type — — — RW1S RW1S RW1S RW1S RW1S Name — — — Reset 0 0 0 0 0 0 0 0 Type — — — RW1S RW RW RW1S RW1S Name — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — RW1S RW1S RW1S RW1S Name — — — — LDO2_LPWR Reset 0 0 0 0 0 0 0 0 Type — — — — RW RW RW1S RW1S Name — — — Reset 0 0 0 0 0 0 0 0 Type — — — RW1S RW1S RW1S RW1S RW1S Name — — — Reset 0 0 0 PF1550 Product data sheet LDO1_VOLT[4:0] LDO1_LS_EN LDO1_LPWR LDO1_OMODE LDO1_STB Y_EN VLDO1_EN LDO2_VOLT[3:0] LDO2_OMODE LDO2_STB Y_EN VLDO2_EN LDO3_VOLT[4:0] LDO3_LS_EN LDO3_LPWR 0 0 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 LDO3_OMODE 0 LDO3_STB Y_EN 0 VLDO3_EN 0 © NXP B.V. 2021. All rights reserved. 124 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 174. Register PMIC bitmap...continued Address Register name BITS[7:0] Type 0x58 0x59 015A 0x5B 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x67 0x68 0x69 0x6A 0x6B 0x6F PWRCTRL0 PWRCTRL1 PWRCTRL2 PWRCTRL3 SW1_PWRDN_ SEQ SW2_PWRDN_ SEQ SW3_PWRDN_ SEQ LDO1_PWRDN_ SEQ LDO2_PWRDN_ SEQ LDO3_PWRDN_ SEQ VREFDDR_ PWRDN_S EQ STATE_INFO I2C_ADDR IO_DRV0 IO_DRV1 RC_16MHZ KEY1 7 6 5 4 3 2 1 0 — — — RW1S RW RW RW1S RW1S TGRESET[7:6] Name POR_DLY[5:3] STANDBYDLY[1:0] STANDBYINV Reset 0 0 0 0 0 0 0 1 Type RW1S RW1S RW1S RW1S RW1S RW RW RW Name ONKEY_RST_EN REGSCPEN RESTARTEN Reset 1 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW Name — — — — LOW_SYS_WARN[3:2] Reset 0 0 0 0 0 0 0 0 Type — — — — RW RW RW1S RW1S ONKEYDBNC[3:2] PWRONRSTEN PWRONDBNC[1:0] — Name UVDET[1:0] GOTO_CORE_ OFF GOTO_SHIP Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1S RW1S RW1S Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1S RW1S RW1S Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1S RW1S RW1S Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1S RW1S RW1S Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1S RW1S RW1S Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1S RW1S RW1S Name — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — RW1S RW1S RW1S Name — — Reset 0 0 0 0 0 0 0 0 Type — — R R R R R R — — — — Name USE_DEFAULT_ ADDR SW1_PWRDN_SEQ[2:0] SW2_PWRDN_SEQ[2:0] SW3_PWRDN_SEQ[2:0] LDO1_PWRDN_SEQ[2:0] LDO2_PWRDN_SEQ[2:0] LDO3_PWRDN_SEQ[2:0] VREFDDR_PWRDN_SEQ[2:0] STATE[5:0] I2C_SLAVE_ADDR_LSBS[2:0] Reset 0 0 0 0 0 0 0 0 Type RW — — — — R R R Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Type — — — — — — RW RW Name — — — — — REQ_ACORE_ HIPWR REQ_ACORE_ON REQ_16MHZ Reset 0 0 0 0 0 0 0 0 Type — — — — — RW RW RW Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW KEY1[7:0] Name PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 125 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 12.4 Register charger bitmap CHGPOK_RSTB [1] VCOREDIG_RSTB [1] [2] [2] Bits reset by invalid VBUSIN Bits reset by invalid VCOREDIG Table 175. Register charger bitmap Address Register name BITS[7:0] 7 0x00 0x02 0x04 0x06 0x07 0x08 0x09 0x0A 0x0D 0x0E 0x0F 0x11 0x12 0x14 0x15 CHG_INT CHG_INT_MASK CHG_INT_OK VBUS_SNS CHG_SNS BATT_SNS CHG_OPER CHG_TMR CHG_EOC_CNFG CHG_CURR_CNFG BATT_REG BATFET_CNFG THM_REG_CNFG VBUS_INLIM_CNFG VBUS_LIN_DPM PF1550 Product data sheet Name 6 THM_I VBUS_DPM_I 5 4 VBUS_I 3 RSVD4 2 CHG_I 1 BAT_I 0 BAT2SOC_I SUP_I Reset 0 0 0 0 0 0 0 0 Type RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C Name THM_M VBUS_DPM_M VBUS_M RSVD4 CHG_M BAT_M BAT2SOC_M SUP_M Reset 1 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW RW Name THM_OK Reset 1 0 0 0 0 1 0 0 Type R R R R R R R R Name VBUS_DPM_OK VBUS_DPM_ SNS RSVD6 VBUS_OK VBUS_VALID_ SNS RSVD4 CHG_OK VBUS_OVLO_ SNS BAT_OK VBUS_IN2SYS_ SNS BAT2SOC_OK SUP_OK RSVD0[1:0] VBUS_UVLO_ SNS Reset 0 0 0 0 1 1 0 0 Type R R R R R R R R Name TREG_SNS THM_SNS WDT_SNS CHG_SNS[3:0] RSVD4 Reset 0 0 0 0 1 0 0 0 Type R R R R R R R R RSVD6[7:6] Name RSVD3[4:3] BATTOC_SNS BATT_SNS[2:0] Reset 0 0 0 0 0 0 0 0 Type RW RW R RW RW R R R RSVD5[7:5] Name DISBATFET WDTEN CHG_OPER[1:0] RSVD2 Reset 0 0 0 0 0 0 0 1 Type RW RW RW RW RW RW RW1S RW1S Name TPRECHG EOCTIME[5:3]FCHGTIME[2:0] RSVD6 Reset 0 0 0 0 1 0 1 0 Type RW1S R RW1S RW1S RW1S RW1S RW1S RW1S Name IEOC[6:4] EOC_MODE EOC_EXIT FORCE_BATT_ ISO CHG_RESTART[1:0] Reset 0 1 0 0 0 0 0 1 Type RW1S RW RW RW RW1S RW1S RW1S RW1S Name PRECHGLB_THRSH[6:5] RSVD7 CHG_CC[4:0] Reset 0 0 0 0 0 0 0 0 Type RW RW1S RW1S RW1S RW1S RW1S RW1S RW1S MINVSYS[7:6] Name CHGCV[5:0] Reset 0 0 1 0 1 0 1 1 Type RW1S RW1S RW1S RW1S RW1S RW1S RW1S RW1S Name BOVRC_ NOVBUS BATFET_OC[5:4] WD_TIME BOVRC_ DISBATFET WDTCLR[1:0] WD_BATFET_ OFF Reset 0 0 1 1 0 0 0 0 Type RW RW RW1S RW1S RW1S RW RW RW Name TEMP_FB_EN RSVD6 THM_HOT REGTEMP[3:2] THM_COLD THM_CNFG[1:0] Reset 0 0 0 0 0 1 0 1 Type RW1S RW RW1S RW1S RW1S RW1S RW1S RW1S Reset 0 1 1 0 1 0 0 0 Type RW1S RW1S RW1S RW1S RW1S RW RW RW VBUS_LIN_ILIM[7:3] Name Name FET_SCALE RSVD6 VIN_DPM_ STOP RSVD0[2:0] PRECHGDBATT_THRSH[4:3] VBUS_DPM_REG[2:0] Reset 0 0 0 0 0 0 0 0 Type RW1S R RW1S RW1S RW1S RW1S RW1S RW1S All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 126 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 175. Register charger bitmap...continued Address Register name BITS[7:0] 7 0x16 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F USB_PHY_LDO_CNFG DBNC_DELAY_TIME CHG_INT_CNFG THM_ADJ_SETTING VBUS2SYS_CNFG LED_PWM FAULT_BATFET_CNFG LED_CNFG CHGR_KEY2 PF1550 Product data sheet 6 5 4 RSVD6[7:6] Name 3 RSVD4[5:4] 2 RSVD3 USBPHYLDO 1 0 USBPHY ACTDISPHY Reset 0 0 0 0 0 0 0 1 Type RW RW RW RW RW RW1S RW1S RW1S SYS_WKUP_DLY[5:4] USB_PHY_TDB[3:2] VBUS_OV_TDB[1:0] Reset 0 RSVD6[7:6] 0 0 0 0 0 0 0 Type RW RW RW1S RW1S RW1S RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW1S RW1S Name RSVD2[7:2] Name RSVD6[7:6] Name EOC_INT CC_ADJ[5:4] CV_ADJ[3:2] CHG_INT_GEN THM_COOL THM_WARM Reset 0 0 0 0 0 0 0 0 Type RW RW RW1S RW1S RW1S RW1S RW1S RW1S RSVD3[7:3] Name VBUS2SYS_ THRSH VBUS2SYS_TDB[1:0] Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW1S RW1S RW1S Name LED_EN LED_PWM[5:0] LED_RAMP Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW RSVD5 TMRFLT_BFET_ EN Name CTRL_CHGR_BETA_SEL[7:6] TSHDN_BFET_ EN THMSUS_ BFET_EN WDFLT_ BFEET_EN OVFLT_BFEET_ EN Reset 0 0 0 0 0 0 0 0 Type RW1S RW1S RW1S RW1S RW1S RW1S RW1S RW1S RSVD4[7:6] Name LEDOVRD LED_CURRENT[3:2] LED_CFG LED_FREQ[1:0] Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW1S RW1S RW1S RW RW Reset 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW CHGR_KEY2[7:0] Name All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 127 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 12.5 Register OTP bitmap Table 176. Register OTP bitmap Address Register name Value BIT[7:0] 7 0x1C 0x1D 0x1E 0x1F 0x20 OTP_PMIC_ CFG0 6 UNUSED 5 4 UNUSED UNUSED 3 OTP_PWRGD_ EN 2 OTP_SEQ_ CLK_SPEED 1 0 OTP_PWRON_ CFG A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x04 0 0 0 0 0 1 0 0 A3 0x04 0 0 0 0 0 1 0 0 A4 0x04 0 0 0 0 0 1 0 0 A5 0x04 0 0 0 0 0 1 0 0 A6 0x04 0 0 0 0 0 1 0 0 A7 0x04 0 0 0 0 0 1 0 0 A8 0x04 0 0 0 0 0 1 1 0 A9 0x04 0 0 0 0 0 1 0 0 OTP_SW1 OTP_SW1_ DVSSPEED OTP_SW1_VOLT[5:0] OTP_SW1_RDIS_ ENB A1 (Default) 0x80 1 0 0 0 0 0 0 0 A2 0xA0 1 0 1 0 0 0 0 0 A3 0XBF 1 0 1 1 1 1 1 1 A4 0XA8 1 0 1 0 1 0 0 0 A5 0XBF 1 0 1 1 1 1 1 1 A6 0XB6 1 0 1 1 0 1 1 0 A7 0XBF 1 0 1 1 1 1 1 1 A8 0XBF 1 0 1 1 1 1 1 1 A9 0XBF 1 0 1 1 1 1 1 OTP_SW1_SW2 OTP_SW2_VOLT[5:0] OTP_SW1_ DVS_SEL 1 OTP_SW1_ EN_AND_ STBY_EN A1 (Default) 0XA3 1 0 1 0 0 0 1 1 A2 0x05 0 0 0 0 0 1 0 1 A3 0x09 0 0 0 0 1 0 0 1 A4 0xC1 1 1 0 0 0 0 0 1 A5 0x0D 0 0 0 0 1 1 0 1 A6 0x09 0 0 0 0 1 0 0 1 A7 0x05 0 0 0 0 0 1 0 1 A8 0x09 0 0 0 0 1 0 0 1 A9 0xFF 1 1 1 1 1 1 1 OTP_SW2_SW3 OTP_SW3_VOLT[3:0] OTP_SW2_ DVS_SEL OTP_SW2_ EN_AND_ STBY_EN OTP_SW2_ DVSSPEED 1 OTP_SW2_ RDIS_ENB A1 (Default) 0x04 0 0 0 0 0 1 0 0 A2 0x0E 0 0 0 0 1 1 1 0 A3 0xFE 1 1 1 1 1 1 1 0 A4 0x06 0 0 0 0 0 1 1 0 A5 0xFE 1 1 1 1 1 1 1 0 A6 0xFE 1 1 1 1 1 1 1 0 A7 0x0E 0 0 0 0 1 1 1 0 A8 0xFE 1 1 1 1 1 1 1 0 A9 0xCE 1 1 0 0 1 1 1 OTP_SW3__ SWxILIM OTP_SW3_ILIM[1:0] OTP_SW2_ILIM[1:0] OTP_SW1_ILIM[1:0] OTP_SW3_ EN_AND_ STBY_EN 0 OTP_SW3_ RDIS_ENB A1 (Default) 0XFE 1 1 1 1 1 1 1 0 A2 0xFE 1 1 1 1 1 1 1 0 A3 0xFE 1 1 1 1 1 1 1 0 A4 0xFE 1 1 1 1 1 1 1 0 A5 0xFE 1 1 1 1 1 1 1 0 A6 0xFE 1 1 1 1 1 1 1 0 A7 0xFE 1 1 1 1 1 1 1 0 A8 0xFE 1 1 1 1 1 1 1 0 A9 0xFE 1 1 1 1 1 1 1 0 PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 128 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 176. Register OTP bitmap...continued Address Register name Value BIT[7:0] 7 0x21 0x22 0x23 0x24 0x25 0x26 OTP_VREF_ LDO1 6 5 4 3 2 1 OTP_LDO1_VOLT[4:0] OTP_LDO1_LS_EN OTP_ VREFDDREN_ AND_STBY_EN 0 UNUSED A1 (Default) 0x16 0 0 0 1 0 1 1 0 A2 0x42 0 1 0 0 0 0 1 0 A3 0x42 0 1 0 0 0 0 1 0 A4 0x7E 0 1 1 1 1 1 1 0 A5 0x42 0 1 0 0 0 0 1 0 A6 0x42 0 1 0 0 0 0 1 0 A7 0x7E 0 1 1 1 1 1 1 0 A8 0x42 0 1 0 0 0 0 1 0 A9 0x6A 0 1 1 0 1 0 1 OTP_LDO1_ LDO2 UNUSED OTP_LDO2_EN_ AND_STBY_EN OTP_LDO2_VOLT[3:0] UNUSED 0 OTP_LDO1_ EN_AND_ STBY_EN A1 (Default) 0x4F 0 1 0 0 1 1 1 1 A2 0x5F 0 1 0 1 1 1 1 1 A3 0x5F 0 1 0 1 1 1 1 1 A4 0x5F 0 1 0 1 1 1 1 1 A5 0x5F 0 1 0 1 1 1 1 1 A6 0x5F 0 1 0 1 1 1 1 1 A7 0x5F 0 1 0 1 1 1 1 1 A8 0x5F 0 1 0 1 1 1 1 1 A9 0x5F 0 1 0 1 1 1 1 1 OTP_LDO3 UNUSED OTP_LDO3_ EN_AND_ STBY_EN OTP_LDO3_VOLT[4:0] OTP_LDO3_ LS_EN A1 (Default) 0x65 0 1 1 0 0 1 0 1 A2 0x50 0 1 0 1 0 0 0 0 A3 0x5F 0 1 0 1 1 1 1 1 A4 0x50 0 1 0 1 0 0 0 0 A5 0x5F 0 1 0 1 1 1 1 1 A6 0x5F 0 1 0 1 1 1 1 1 A7 0x5F 0 1 0 1 1 1 1 1 A8 0x5F 0 1 0 1 1 1 1 1 A9 0x50 0 1 0 1 0 0 0 0 OTP_PMIC_ CFG1 OTP_UVDET[1:0] UNUSED OTP_POR_DLY[2:0] OTP_TGRESET[1:0] A1 (Default) 0x40 0 1 0 0 0 0 0 0 A2 0x40 0 1 0 0 0 0 0 0 A3 0x40 0 1 0 0 0 0 0 0 A4 0x40 0 1 0 0 0 0 0 0 A5 0x40 0 1 0 0 0 0 0 0 A6 0x40 0 1 0 0 0 0 0 0 A7 0x40 0 1 0 0 0 0 0 0 A8 0x40 0 1 0 0 0 0 0 0 A9 0x40 0 1 0 0 0 0 0 0 OTP_SW1_ SW2_SEQ UNUSED OTP_SW2_PWRUP_SEQ[2:0] UNUSED OTP_SW1_PWRUP_SEQ[2:0] A1 (Default) 0x11 0 0 0 1 0 0 0 1 A2 0x2D 0 0 1 0 1 1 0 1 A3 0x1B 0 0 0 1 1 0 1 1 A4 0x1C 0 0 0 1 1 1 0 0 A5 0x1B 0 0 0 1 1 0 1 1 A6 0x1B 0 0 0 1 1 0 1 1 A7 0x1B 0 0 0 1 1 0 1 1 A8 0x1B 0 0 0 1 1 0 1 1 A9 0x1B 0 0 0 1 1 0 1 1 OTP_SW3_ LDO1_SEQ A1 (Default) PF1550 Product data sheet UNUSED 0x23 OTP_LDO1_PWRUP_SEQ[2:0] UNUSED 0 0 1 0 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 OTP_SW3_PWRUP_SEQ[2:0] 0 0 1 1 © NXP B.V. 2021. All rights reserved. 129 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 176. Register OTP bitmap...continued Address 0x27 0x28 0x29 0x2A 0x2B Register name Value BIT[7:0] 4 3 2 1 0 A2 0x09 0 0 0 0 1 0 0 1 A3 0x1B 0 0 0 1 1 0 1 1 A4 0x0A 0 0 0 0 1 0 1 0 A5 0x1B 0 0 0 1 1 0 1 1 A6 0x1B 0 0 0 1 1 0 1 1 A7 0x1B 0 0 0 1 1 0 1 1 A8 0x1B 0 0 0 1 1 0 1 1 A9 0x1B 0 0 0 1 1 0 1 1 OTP_LDO2_ LDO3_SEQ 7 6 5 UNUSED OTP_LDO3_PWRUP_SEQ[2:0] UNUSED OTP_LDO2_PWRUP_SEQ[2:0] A1 (Default) 0x2C 0 0 1 0 1 1 0 0 A2 0x09 0 0 0 0 1 0 0 1 A3 0x1A 0 0 0 1 1 0 1 0 A4 0x0A 0 0 0 0 1 0 1 0 A5 0x1A 0 0 0 1 1 0 1 0 A6 0x1A 0 0 0 1 1 0 1 0 A7 0x1A 0 0 0 1 1 0 1 0 A8 0x1A 0 0 0 1 1 0 1 0 A9 0x1B 0 0 0 1 1 0 1 1 OTP_PMIC_ CFG2 OTP_I2C_SLV_ADDR[2:0] OTP_SHIP_ COREOFF_CYA OTP_VREFDDR_PWRUP_SEQ[2:0] OTP_I2C_ DEGLITCH_EN[0] A1 (Default) 0x05 0 0 0 0 0 1 0 1 A2 0x05 0 0 0 0 0 1 0 1 A3 0x03 0 0 0 0 0 0 1 1 A4 0x03 0 0 0 0 0 0 1 1 A5 0x03 0 0 0 0 0 0 1 1 A6 0x03 0 0 0 0 0 0 1 1 A7 0x03 0 0 0 0 0 0 1 1 A8 0x03 0 0 0 0 0 0 1 1 A9 0x03 0 0 0 0 0 0 1 UNUSED UNUSED RSVD UNUSED UNUSED Reserved (OTP_VSNVS_VOLT[2:0]) 1 Reserved (OTP_FORCE_ LICELL) A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 RSVD OTP_PMIC_SPARE0[7:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 OTP_CHG_CFG0 Reserved (OTP_ CHGR_ THM_WARM) OTP_CHGR_EOCTIME[2:0] Reserved (OTP_ CHGR_ THM_COOL) OTP_CHGR_ TPRECHG OTP_CHGR_OPER[1:0] A1 (Default) 0x02 0 0 0 0 0 0 1 0 A2 0x01 0 0 0 0 0 0 0 1 A3 0x02 0 0 0 0 0 0 1 0 A4 0x02 0 0 0 0 0 0 1 0 A5 0x02 0 0 0 0 0 0 1 0 A6 0x01 0 0 0 0 0 0 0 1 PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 130 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 176. Register OTP bitmap...continued Address 0x2C 0x2D 0x2E 0x2F 0x30 Register name Value BIT[7:0] 4 3 2 1 0 A7 0x02 0 0 0 0 0 0 1 0 A8 0x02 0 0 0 0 0 0 1 0 A9 0x01 0 0 0 0 0 0 0 1 OTP_CHG_CFG1 7 6 5 OTP_CHGR_CHG_RESTART[1:0] Reserved (OTP_ CHGR_ FORCE_BATT_ ISO) Reserved (OTP_ CHGR_ EOC_EXIT) OTP_CHGR_FCHGTIME[2:0] Reserved (OTP_ CHGR_ EOC_MODE) A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 OTP_CHG_CFG2 OTP_CHGR_VSYSMIN[1:0] OTP_CHGR_CHG_CC[4:0] 0 OTP_CHGR_ TEMPFB_EN A1 (Default) 0x80 1 0 0 0 0 0 0 0 A2 0x80 1 0 0 0 0 0 0 0 A3 0x80 1 0 0 0 0 0 0 0 A4 0x90 1 0 0 1 0 0 0 0 A5 0x80 1 0 0 0 0 0 0 0 A6 0x40 0 1 0 0 0 0 0 0 A7 0x80 1 0 0 0 0 0 0 0 A8 0x80 1 0 0 0 0 0 0 0 A9 0x40 0 1 0 0 0 0 0 0 OTP_CHG_CFG3 OTP_CHGR_BATFET_OC[1:0] OTP_CHGR_CHGCV[5:0] A1 (Default) 0x2B 0 0 1 0 1 0 1 1 A2 0x2B 0 0 1 0 1 0 1 1 A3 0x2B 0 0 1 0 1 0 1 1 A4 0x2B 0 0 1 0 1 0 1 1 A5 0x2B 0 0 1 0 1 0 1 1 A6 0x2B 0 0 1 0 1 0 1 1 A7 0x2B 0 0 1 0 1 0 1 1 A8 0x2B 0 0 1 0 1 0 1 1 A9 0x2B 0 0 1 0 1 0 1 OTP_CHG_CFG4 OTP_CHGR_THM_CNFG[1:0] UNUSED OTP_CHGR_REGTEMP[1:0] OTP_CHGR_ THM_COLD OTP_CHGR_ THM_HOT 1 OTP_CHGR_ BOVRC_ DISBATFET A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 OTP_CHG_CFG5 UNUSED UNUSED OTP_CHGR_VBUS_LIN_ILIM[4:0] OTP_CHGR_ VIN_DPM_STOP A1 (Default) 0x0E 0 0 0 0 1 1 1 0 A2 0x14 0 0 0 1 0 1 0 0 A3 0x14 0 0 0 1 0 1 0 0 A4 0x14 0 0 0 1 0 1 0 0 A5 0x14 0 0 0 1 0 1 0 0 A6 0x14 0 0 0 1 0 1 0 0 A7 0x14 0 0 0 1 0 1 0 0 A8 0x14 0 0 0 1 0 1 0 0 A9 0x14 0 0 0 1 0 1 0 0 PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 131 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 176. Register OTP bitmap...continued Address Register name Value BIT[7:0] 7 0x31 0x32 0x33 0x34 0x35 0x36 OTP_CHG_CFG6 6 OTP_CHGR_SYS_WKUP_DLY[1:0] 5 OTP_CHGR_ ACTDISPHY 4 OTP_CHGR_ USBPHY 3 2 1 0 OTP_CHGR_VBUS_DPM_REG[2:0] OTP_CHGR_ USBPHYLDO A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x28 0 0 1 0 1 0 0 0 A3 0x28 0 0 1 0 1 0 0 0 A4 0x2E 0 0 1 0 1 1 1 0 A5 0x28 0 0 1 0 1 0 0 0 A6 0x28 0 0 1 0 1 0 0 0 A7 0x28 0 0 1 0 1 0 0 0 A8 0x28 0 0 1 0 1 0 0 0 A9 0x28 0 0 1 0 1 0 0 0 OTP_CHG_CFG7 OTP_CHGR_CC_ADJ[1:0] OTP_CHGR_ CHG_INT_EN OTP_CHGR_ EOC_INT OTP_CHGR_VBUS_OV_TDB[1:0] Reserved (OTP_CHGR_USB_PHY_ TDB[1:0]) A1 (Default) 0x04 0 0 0 0 0 1 0 0 A2 0x04 0 0 0 0 0 1 0 0 A3 0x04 0 0 0 0 0 1 0 0 A4 0x14 0 0 0 1 0 1 0 0 A5 0x04 0 0 0 0 0 1 0 0 A6 0x04 0 0 0 0 0 1 0 0 A7 0x04 0 0 0 0 0 1 0 0 A8 0x04 0 0 0 0 0 1 0 0 A9 0x04 0 0 0 0 0 1 0 0 OTP_CHG_CFG8 OTP_CHGR_LED_CURRENT[1:0] UNUSED OTP_CHGR_VBUS2SYS_TDB[1:0] OTP_CHGR_ VBUS2SYS_ THRSH OTP_CHGR_CV_ADJ[1:0] A1 (Default) 0x28 0 0 1 0 1 0 0 0 A2 0x28 0 0 1 0 1 0 0 0 A3 0x28 0 0 1 0 1 0 0 0 A4 0x28 0 0 1 0 1 0 0 0 A5 0x28 0 0 1 0 1 0 0 0 A6 0x28 0 0 1 0 1 0 0 0 A7 0x28 0 0 1 0 1 0 0 0 A8 0x28 0 0 1 0 1 0 0 0 A9 0x28 0 0 1 0 1 0 0 0 OTP_CHG_CFG9 OTP_CHGR_LED_ CNFG OTP_CHGR_OVFLT_ BFET_EN OTP_CHGR_ WDFLT_BFET_ EN OTP_CHGR_ THMSUS_BFET_ EN OTP_CHGR_ TSHDN_BFET_ EN OTP_CHGR_ TMRFLT_ BFET_EN Reserved (OTP_CHGR_BETA_SEL[1:0]) A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 OTP_CHG_ CFG10 UNUSED UNUSED UNUSED Reserved (OTP_ CHGR_ FET_SCALE) Reserved (OTP_CHGR_PRECHG_ LOWBATT_THRSH[1:0]) OTP_CHGR_PRECHG_ LOWBATT_THRSH[1:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 RSVD OTP_CHGR_SPARE0[7:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 132 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 176. Register OTP bitmap...continued Address 0x37 Register name Value BIT[7:0] 4 3 2 1 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 CRC[1]LSB — — — — — — — OTP_CRC_LSB 7 6 5 A1 (Default) 0xB5 1 0 1 1 0 1 0 1 A2 0xB5 1 0 1 1 0 1 0 1 A3 0xB5 1 0 1 1 0 1 0 1 A4 0xB5 1 0 1 1 0 1 0 1 A5 0xB5 1 0 1 1 0 1 0 1 A6 0xB5 1 0 1 1 0 1 0 1 A7 0xB5 1 0 1 1 0 1 0 1 A8 0xB5 1 0 1 1 0 1 0 1 A9 0xB5 1 0 1 1 0 1 0 1 13 Application details 13.1 Example schematic Figure 28 shows a typical schematic of the PF1550 with key external components. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 133 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 1 2 3 5.0 V VBUS D- DM D+ 4 ID 5 GND PHY PWR DP i.MX 7ULP (USB) UID 3.3 V 37 2.2 F 25 V 1.0 F 6.3 V 26 4.7 F 6.3 V 17 4.7 F 6.3 V 14 4.7 F 6.3 V 31 0.1 F 6.3 V 22 1.0 F 6.3 V 28 1.0 F 6.3 V 20 1.0 F 6.3 V 4 4.7 K 0.1 F 6.3 V 4.7 K I2C SCL 3 2 I2C SDA i.MX 7ULP 100 K (Interface) USBPHY 100 K 100 K 100 K SW1FB SW1IN SW2FB SW2LX SW2IN SW3FB SW3IN SW3LX LICELL VSNVS VLDO1IN VLDO2IN VDDIO VREFDDR VLDO1 VLDO2 VLDO3 CHGB VCORE SCL VDIG SDA VDDOTP 100 K VBATT1 VBATT2 9 INTB 10 RESETBMCU 6 PWRON 1 WDI 7 STANDBY INTB (GPIO) POR_B PMIC_ON_REQ WDOG_B PMIC_STBY_REQ VBATT ON/OFF 100 K 8 36 4.2 V 10 F 6.3 V 27 22 F 10 V 22 F 10 V 25 ONKEY INT2P7 THM EP VSYS 0.6 V to 1.3785 V @ 1.0 A (DVS) 1.0 H 10 F 6.3 V 16 18 10 F 6.3 V 1.2 V @ 1.0 A (DVS) 1.0 H 10 F 6.3 V VDD_DIG1 VDD_HSIC 10 F 6.3 V i.MX 7ULP (Core) 15 1.8 V @ 1.0 A 13 1.0 H 10 F 6.3 V VDD_PTC 10 F 6.3 V VDD_PTD 30 VDD_RTC 0.47 F 6.3 V PF1550 VINREFDDR VBATT 35 SW1LX 11 VLDO3IN 1.0 F 6.3 V 1.8 V VSYS1 VSYS2 39 VSYS VBUSIN 21 0.5 V to 0.9 V @ 10 mA 0.9 V 1.8 V LPDDR2 1.2 V 1.0 F 6.3 V 29 0.75 V to 3.3 V @ 300 mA 3.3 V 4.7 F 6.3 V 19 Peripherals 1.8 V to 3.3 V @ 400 mA 1.8 V 10 F 6.3 V 12 0.75 V to 3.3 V @ 300 mA 4.7 F 6.3 V 47 Ω 40 24 23 1.0 F 6.3 V 5 VSYS 1.0 F 6.3 V VBATT 33 34 CV charge 3.5 V to 4.44 V 10 K 38 2.2 F 6.3 V 32 GND + Battery pack 4.7 F 10 V CC charge 100 mA to 1.0 A 3.7 V Li-Ion T t - 10 K thermistor aaa-023890 Figure 28. Typical schematic 13.2 Bill of materials The following table shows an example bill of materials to be used with the PF1550. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 134 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 177. Bill of materials Function Description VCORE Block Analog IC supply CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 VDIG Digital IC supply CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 Charger analog supply CAP CER 2.2 µF 6.3 V 20% X5R 0201 1 USBPHY USB PHY output capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 VBUSIN INT2P7 VBUSIN bypass capacitor CAP CER 2.2 µF 25 V 20 % X5R 0402 1 VSYS VSYS capacitor 22 µF, 10 V, MLCC, X5R 2 VBATT Bypass capacitor between VBATT and [1] VSYS 10 µF, 6.3 V, MLCC, X5R 1 VDDIO VDDIO bypass capacitor CAP CER 0.1 uF 6.3 V 20 % X5R 0201 1 THM Thermistor bias resistor 10 kOhm, 0201 1 BUCK1 inductor 1.0 µH, +/−20 %, 120 mOhm typ, 1700 mA 1 BUCK1 input capacitor 4.7 µF, 6.3 V, MLCC, X5R 1 BUCK1 output capacitor 10 µF, 6.3 V, MLCC, X5R 2 BUCK2 inductor 1.0 µH, +/−20 %, 120 mOhm typ, 1700 mA 1 BUCK2 input capacitor 4.7 µF, 6.3 V, MLCC, X5R 1 BUCK2 output capacitor 10 µF, 6.3V, MLCC, X5R 2 BUCK3 inductor 1.0 µH, +/-20 %, 120 mOhm typ, 1700 mA 1 BUCK3 input capacitor 4.7 µF, 6.3 V, MLCC, X5R 1 BUCK3 output capacitor 10 µF, 6.3 V, MLCC, X5R 2 LDO1 input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 LDO1 output capacitor 4.7 µF, 6.3 V, MLCC, X5R 1 LDO2 input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 LDO2 output capacitor 10 µF, 6.3 V, MLCC, X5R 1 LDO3 input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 LDO3 output capacitor 4.7 µF, 6.3 V, MLCC, X5R 1 VREFDDR input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 VREFDDR output capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1 VSNVS VSNVS output capacitor CAP CER 0.47 µF 6.3 V 20 % X5R 0201 1 LICELL LICELL bypass capacitor CAP CER 0.1 µF 6.3 V 20 % X5R 0201 1 Buck 1 Buck 2 Buck 3 LDO1 LDO2 LDO3 VREFDDR [1] Qty ONLY for < 20mA EOC current threshold settings and to allow a smooth transition from CV to EOC state PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 135 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 13.3 PF1550 layout guidelines 13.3.1 General board recommendations • It is recommended to use an eight layer board stack-up arranged as follows: – High current signal – GND – Signal – Power – Power – Signal – GND • Allocate TOP and BOTTOM PCB layers for POWER ROUTING (high current signals), copper-pour the unused area. • Use internal layers sandwiched between two GND planes for the SIGNAL routing. 13.3.2 Component placement It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output capacitors. 13.3.3 General routing requirements • Some recommended things to keep in mind for manufacturability: – Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole – Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper – Minimum allowed spacing between line and hole pad is 3.5 mils – Minimum allowed spacing between line and line is 3.0 mils • Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high-power signals, like the ones on the SWxIN, SWxLX. They could be also shielded. • Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). • Avoid coupling traces between important signal/low noise supplies (like VCORE, VDIG) from any switching node (for example, SW1LX, SW2LX, SW3LX). • Make sure that all components related to a specific block are referenced to the corresponding ground. 13.3.4 Parallel routing requirements 2 • I C signal routing – CLK is the fastest signal of the system, so it must be given special care. – To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 136 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors adjacent layers. Make sure that the ground plane is uniform throughout the whole signal trace length. – These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane. – Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals. DO Signal DON’T Signal Ground plane Ground planes aaa-023891 Figure 29. Recommended shielding for critical signals 13.3.5 Switching regulator layout recommendations • Per design, the switching regulators in PF1550 are designed to operate with only one input bulk capacitor. However, it is recommended to add a high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins. • Make high-current ripple traces low-inductance (short, high W/L ratio). • Make high-current traces wide or copper islands. VIN SWxIN CIN_HF Driver controller CIN SWxLX L COUT Compensation SWxFB aaa-023892 Figure 30. Generic buck regulator architecture PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 137 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Route FB trace on any layer away from noisy nodes VIN GND COUT CIN SWxFB VOUT CIN_HF SWxIN Inductor SWxLX aaa-023893 Figure 31. Layout example for buck regulators 13.4 Thermal information 13.4.1 Rating data The thermal rating data of the packages has been simulated with the results listed in Table 3 . Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (ThetaJMA) is used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org/. 13.4.2 Estimation of junction temperature An estimation of the chip junction temperature TJ can be obtained from the equation: TJ= TA+ (RθJA x PD) with: TA = Ambient temperature for the package in °C RθJA = Junction to ambient thermal resistance in °C/W PD= Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 138 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors At a known board temperature, the junction temperature TJ is estimated using the following equation TJ= TB+ (RθJBx PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W 14 Package outline The PF1550 uses a 40-pin QFN 5.0 mm x 5.0 mm with exposed pad, case number 98ASA00913D. This drawing is available for download at http://www.nxp.com. Figure 32. Package outline for HVQFN40 (SOT1369-4) PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 139 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Figure 33. Package outline detail for HVQFN40 (SOT1369-4) PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 140 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Figure 34. Package outline notes for HVQFN40 (SOT1369-4) PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 141 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 15 Revision history Table 178. Revision history Document ID Release date Data sheet status Change notice Supersedes PF1550 v.7.0 20210929 Product data sheet CIN 202109033I PF1550 v.6.0 Modifications • • • • PF1550 v.6.0 20210305 Modifications • Section 14: added "Optional Detail G with 0.15 mm lead edge package option" to package outline drawings PF1550 v.5.0 20190610 Modifications Updated as per CIN 201904033I • Table 1: added MC32PF1550A9EP and MC34PF1550A9EP parts • Table 77: replaced "0.2 * VSNVS" by "0.4" and "0.8 * VSNVS" by "1.4" • Section 9.3: added Table 78 • Section 9.4: added Table 79 • Table 81: replaced "0.2 * VBATT" by "0.4", "0.8 * VBATT" by "1.4" and 3.6 by 4.8 • Section 11.1: updated Figure 27 • Table 85: added OTP configuration for A9 • Section 8.8.4: updated Figure 23 • Table 165: updated description for USBPHYLDO (replaced 0 by 1) • Figure 12, Figure 28: replaced "INT_2P7" by "INT2P7" and 1.0 µF by 2.2 µF • Section 12.5: added A9 OTP • Global: changed document status from Advance information to Product PF1550 v.4.0 20180928 Modifications • Added MC32PF1550A0EP, MC32PF1550A8EP, MC34PF1550A0EP, and MC34PF1550A8EP parts to Table 1 • Added OTP configuration for A8 to Table 85 PF1550 v.3.0 20180502 Modifications • Changed PC parts to MC in Table 1 • Updated programming option for MC32PF1550A7EP and MC34PF1550A7EP (replaced LPDDR3 by LPDDR2) in Table 1 • Updated SDA and SCL pin description in Table 2 • Updated A7 OTP configuration for OTP_SW3_VOLT[5:0] and OTP_LDO1_VOLT[4:0] registers (replaced 3.3 V by 1.8 V and 1.8 V by 3.3 V) in Table 85 and modified Table 176 to reflect A7 OTP option updates • Updated min. and max. input current values in Table 6 PF1550 v.2.0 20180202 PF1550 Product data sheet Global: replaced “BAT_SNS” by “BATT_SNS” Figure 16: replaced “BAT_SNS=0x09” by “BATT_SNS=0X05” Section 8.9.4: replaced “BAT_SNS=0x09” by “BATT_SNS=0X05” Table 152: updated the description for BAT_OK (“BAT_SNS = 0x06 or 0x07 or 0x09” replaced by “BATT_SNS = 0x02 or 0x05 or 0x06” and “BAT_SNS ≠ 0x06 or 0x07 or 0x09” replaced by “BATT_SNS ≠0x02 or 0x05 or 0x06”) • Table 152: updated the description for BAT2SOC_OK (replaced “BATT_SNS Bit 5 = 0b1” by “BATTOC_SNS bit = 1”) Product data sheet Product data sheet Advance information Advance information Advance information All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 PCN 202012012F01 — — — — PF1550 v.5.0 PF1550 v.4.0 PF1550 v.3.0 PF1550 v.2.0 PF1550 v.1.0 © NXP B.V. 2021. All rights reserved. 142 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Table 178. Revision history...continued Document ID Release date Modifications • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • PF1550 v.1.0 PF1550 Product data sheet Data sheet status Change notice Supersedes Updated Figure 10 Updated Figure 28 Updated description in Section 7.3.6 "LDO2 current limit protection" Changed capacitor value from 4.7 µF to 10 µF in Section 7.3.3 "LDO2 external components" Updated Figure 15, Figure 17, Figure 28 Changed the value of LDO2 output capacitor from 4.7 µF to 10 µF in Table 177 Updated Figure 3 (changed VUSB to VBUSIN Updated Figure 4 (changed VDO3IN to VLDO3IN) Corrected typos in Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, Table 11, Table 13, Table 14, Table 17, and Table 18 Updated quiescent current ILDO1Q from 4.0 to 4.5 in Table 21 and added new parameter Updated and added new parameters to Table 19 and Table 20 Updated values for ILDO2LIM in Table 22 Updated quiescent current ILDO3Q from 4.0 to 4.5 in Table 23 Updated typical and maximum value for REGS_DISABLE and SHIP MODE in Table 26 Updated Section 6.3.3 "Output voltage setting in SW3" Updated Figure 12, Figure 13, and Figure 14 Changed OTP_SW2_DVS_SEL to DVS mode for A4 configuration in Table 85 Changed OTP configuration for SW1 to 1.3875 V in Table 85 Updated Table 176 and Table 177 Updated IQ_CHARGER_LQM max. value from 2.5 to 3.0 in Table 6 Updated values for VSWx in Table 19 Updated ILDO1Q and ILDO3Q values from 22 to 25 in Table 21 and Table 23 Added part numbers to Table 1 Updated typical value for tFC in Table 13 Updated ISWxLIMH values in Table 19 and Table 20 Updated Figure 16 and Figure 17 Added Section 9.7 Added OTP configuration for A5 to Table 85 Updated Table 1 Added A6 and A7 OTP configurations to Table 85 Updated Figure 3, Figure 16, and Figure 28 Added Figure 27 Updated values for ISWxLIMH and ISW3LIMH in Table 19 and Table 20 Added ripple parameter to Table 20 Updated values for frequency in Table 72 Updated Table 116, Table 121, Table 126, Table 167, and Table 174 Updated Section 12.5 Replaced MINVSYS by VSYSMIN Changed document status from Product preview to Advance information 20161012 Product preview All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 — — © NXP B.V. 2021. All rights reserved. 143 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 16 Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 16.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without PF1550 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 144 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. 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Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. PF1550 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 145 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Tab. 24. Tab. 25. Tab. 26. Tab. 27. Tab. 28. Tab. 29. Tab. 30. Tab. 31. Tab. 32. Tab. 33. Tab. 34. Tab. 35. Tab. 36. Tab. 37. Tab. 38. Tab. 39. Tab. 40. Tab. 41. Tab. 42. Tab. 43. Tab. 44. Tab. 45. Tab. 46. Tab. 47. Tab. 48. Tab. 49. Tab. 50. Tab. 51. Tab. 52. Tab. 53. Tab. 54. Orderable part variations ...................................6 Pin description ...................................................8 Thermal ratings ................................................. 9 Maximum ratings ............................................. 10 Global conditions .............................................12 Input currents .................................................. 12 Internal 2.7 V Regulator (INT2P7) ...................13 Switch impedances and leakage currents ....... 13 Linear transients ..............................................14 Charger characteristics ................................... 14 Power-path management ................................ 15 Watchdog timer ............................................... 15 Charger timer .................................................. 15 Battery overcurrent protection ......................... 15 Thermal regulation .......................................... 16 Battery thermistor monitor ............................... 16 USBPHY LDO ................................................. 16 LED characteristics ......................................... 17 SW1 and SW2 electrical characteristics ..........17 SW3 electrical characteristics ......................... 19 LDO1 electrical characteristics ........................20 LDO2 electrical characteristics ........................20 LDO3 electrical characteristics ........................21 VREFDDR electrical characteristics ................ 22 VSNVS electrical characteristics ..................... 22 IC level electrical characteristics ..................... 23 Voltage regulators ........................................... 24 SWx DVS setting selection ............................. 26 Buck regulator operating modes ..................... 27 Buck mode control .......................................... 28 SW1 and SW2 output voltage setting ..............29 Acceptable inductance and capacitance values .............................................................. 31 Example inductor part numbers ...................... 31 Example capacitor part numbers .....................31 SW3 buck regulator operating modes ............. 32 SW3 buck mode control ..................................32 SW3 output voltage setting ............................. 33 Acceptable inductance and capacitance values .............................................................. 34 Example inductor part numbers ...................... 34 Example capacitor part numbers .....................34 LDOy output voltage setting ............................36 LDOy control bits ............................................ 37 LDO2 output voltage setting ............................39 LDO2 control bits ............................................ 40 Battery regulation voltage register ...................44 VSYSMIN setting ............................................ 45 Charger current control register ...................... 48 Constant current charge settings .................... 48 Battery regulation voltage register ...................50 CV settings ......................................................50 Charger timers register ................................... 52 Fast charge timer settings ...............................52 Charger EOC configuration register ................ 53 EOC current thresholds ...................................53 PF1550 Product data sheet Tab. 55. Tab. 56. Tab. 57. Tab. 58. Tab. 59. Tab. 60. Tab. 61. Tab. 62. Tab. 63. Tab. 64. Tab. 65. Tab. 66. Tab. 67. Tab. 68. Tab. 69. Tab. 70. Tab. 71. Tab. 72. Tab. 73. Tab. 74. Tab. 75. Tab. 76. Tab. 77. Tab. 78. Tab. 79. Tab. 80. Tab. 81. Tab. 82. Tab. 83. Tab. 84. Tab. 85. Tab. 86. Tab. 87. Tab. 88. Tab. 89. Tab. 90. Tab. 91. Tab. 92. Tab. 93. Tab. 94. Tab. 95. Tab. 96. Tab. 97. Tab. 98. Tab. 99. Tab. 100. Tab. 101. Tab. 102. Tab. 103. Tab. 104. Tab. 105. Tab. 106. Charger timers register ................................... 54 EOC state timer settings ................................. 54 VBUS input current limit register ..................... 56 Input current limit settings ............................... 56 Thermal regulation .......................................... 57 Temperature regulation control register ...........59 Thermal regulation settings ............................. 59 VBUS linear dynamic input voltage register .... 61 Input voltage regulation thresholds ................. 61 JEITA thermal control ......................................62 Temperature regulation control register ...........62 JEITA temperature control register ..................63 CV voltage adjustment settings .......................64 CC current adjustment settings ....................... 64 Battery overcurrent thresholds ........................ 66 LED modes ..................................................... 67 LED enable conditions .................................... 67 LED frequency setting .....................................68 PWRON pin OTP configuration options .......... 68 PWRON pin logic level ....................................68 PWRONDBNC settings ................................... 69 Standby pin polarity control .............................69 STANDBY pin logic level .................................69 RESETBMCU pin logic level ........................... 70 INTB pin logic level ......................................... 70 WDI pin logic level .......................................... 70 ONKEY pin logic level .....................................71 ONKEYDBNC settings .................................... 71 State transition table ....................................... 76 A4 startup and power down sequence timing ............................................................... 79 PF1550 start up configuration ......................... 79 Register DEVICE_ID - ADDR 0x00 .................81 Register OTP_FLAVOR - ADDR 0x01 ............ 81 Register SILICON_REV - ADDR 0x02 ............ 81 Register INT_CATEGORY - ADDR 0x06 ........ 81 Register SW_INT_STAT0 - ADDR 0x08 ..........82 Register SW_INT_MASK0 - ADDR 0x09 ........ 82 Register SW_INT_SENSE0 - ADDR 0x0A ...... 83 Register SW_INT_STAT1 - ADDR 0x0B ......... 83 Register SW_INT_MASK1 - ADDR 0x0C ........84 Register SW_INT_SENSE1 - ADDR 0x0D ......84 Register SW_INT_STAT2 - ADDR 0x0E ......... 84 Register SW_INT_MASK2 - ADDR 0x0F ........ 85 Register SW_INT_SENSE2 - ADDR 0x10 ...... 85 Register LDO_INT_STAT0 - ADDR 0x18 ........ 85 Register LDO_INT_MASK0 - ADDR 0x19 .......86 Register LDO_INT_SENSE0 - ADDR 0x1A .... 86 Register TEMP_INT_STAT0 - ADDR 0x20 ......86 Register TEMP_INT_MASK0 - ADDR 0x21 .... 87 Register TEMP_INT_SENSE0 - ADDR 0x22 .................................................................87 Register ONKEY_INT_STAT0 - ADDR 0x24 .................................................................87 Register ONKEY_INT_MASK0 - ADDR 0x25 .................................................................88 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 146 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Tab. 107. Register ONKEY_INT_SENSE0 - ADDR 0x26 .................................................................89 Tab. 108. Register MISC_INT_STAT0 - ADDR 0x28 .......89 Tab. 109. Register MISC_INT_MASK0- ADDR 0x29 ...... 90 Tab. 110. Register MISC_INT_SENSE0 - ADDR 0x2A ................................................................ 90 Tab. 111. Register COINCELL_CONTROL - ADDR 0x30 .................................................................91 Tab. 112. Register SW1_VOLT - ADDR 0x32 .................91 Tab. 113. Register SW1_STBY_VOLT - ADDR 0x33 ......91 Tab. 114. Register SW1_SLP_VOLT - ADDR 0x34 ........ 92 Tab. 115. Register SW1_CTRL - ADDR 0x35 .................92 Tab. 116. Register SW1_SLP_VOLT - ADDR 0x36 ........ 93 Tab. 117. Register SW2_VOLT - ADDR 0x38 .................93 Tab. 118. Register SW2_STBY_VOLT - ADDR 0x39 ......93 Tab. 119. Register SW2_SLP_VOLT - ADDR 0x3A ........ 93 Tab. 120. Register SW2_CTRL - ADDR 0x3B ................ 94 Tab. 121. Register SW2_CTRL1 - ADDR 0x3C .............. 94 Tab. 122. Register SW3_VOLT - ADDR 0x3E ................ 95 Tab. 123. Register SW3_STBY_VOLT - ADDR 0x3F ......95 Tab. 124. Register SW3_SLP_VOLT - ADDR 0x40 ........ 95 Tab. 125. Register SW3_CTRL - ADDR 0x41 .................95 Tab. 126. Register SW3_CTRL1 - ADDR 0x42 ...............96 Tab. 127. Register VSNVS_CTRL - ADDR 0x48 ............ 96 Tab. 128. Register VREFDDR_CTRL - ADDR 0x4A ....... 96 Tab. 129. Register LDO1_VOLT - ADDR 0x4C ...............97 Tab. 130. Register LDO1_CTRL - ADDR 0x4D .............. 97 Tab. 131. Register LDO2_VOLT - ADDR 0x4F ............... 97 Tab. 132. Register LDO2_CTRL - ADDR 0x50 ............... 98 Tab. 133. Register LDO3_VOLT - ADDR 0x52 ............... 98 Tab. 134. Register LDO3_CTRL - ADDR 0x53 ............... 98 Tab. 135. Register PWRCTRL0 - ADDR 0x58 ................ 99 Tab. 136. Register PWRCTRL1 - ADDR 0x59 ................ 99 Tab. 137. Register PWRCTRL2 - ADDR 0x5A ..............100 Tab. 138. Register PWRCTRL3 - ADDR 0x5B ..............100 Tab. 139. Register SW1_PWRDN_SEQ - ADDR 0x5F ...............................................................101 Tab. 140. Register SW2_PWRDN_SEQ - ADDR 0x60 ...............................................................101 Tab. 141. Register SW2_PWRDN_SEQ - ADDR 0x61 ...............................................................102 Tab. 142. Register LDO1_PWRDN_SEQ - ADDR 0x62 ...............................................................102 Tab. 143. Register LDO2_PWRDN_SEQ - ADDR 0x63 ...............................................................103 Tab. 144. Register LDO3_PWRDN_SEQ - ADDR 0x64 ...............................................................103 Tab. 145. Register VREFDDR_PWRDN_SEQ ADDR 0x65 ................................................... 104 Tab. 146. Register STATE_INFO - ADDR 0x67 ............ 104 Tab. 147. Register I2C_ADDR - ADDR 0x68 ................ 104 Tab. 148. Register RC_16MHZ - ADDR 0x6B .............. 105 Tab. 149. Register KEY1 - ADDR 0x6B ........................ 105 Tab. 150. Register CHG_INT - ADDR 0x00 .................. 105 Tab. 151. Register CHG_INT_MASK - ADDR 0x02 ...... 106 Tab. 152. Register CHG_INT_OK - ADDR 0x04 ........... 107 Tab. 153. Register VBUS_SNS - ADDR 0x06 ...............107 Tab. 154. Register CHG_SNS - ADDR 0x07 ................ 108 Tab. 155. Register BATT_SNS - ADDR 0x08 ............... 109 Tab. 156. Register CHG_OPER- ADDR 0x09 ...............109 Tab. 157. Register CHG_TMR - ADDR 0x0A ................110 Tab. 158. Register CHG_EOC_CNFG - ADDR 0x0D ....111 Tab. 159. Register CHG_CURR_CNFG - ADDR 0x0E .............................................................. 112 Tab. 160. Register BATT_REG - ADDR 0x0F ............... 113 Tab. 161. Register BATFET_CNFG - ADDR 0x11 .........114 Tab. 162. Register THM_REG_CNFG - ADDR 0x12 .... 115 Tab. 163. Register VBUS_INLIM_CNFG - ADDR 0x14 ...............................................................116 Tab. 164. Register VBUS_LIN_DPM - ADDR 0x15 .......117 Tab. 165. Register USB_PHY_LDO_CNFG - ADDR 0x16 ...............................................................117 Tab. 166. Register DBNC_DELAY_TIME - ADDR 0x18 ...............................................................118 Tab. 167. Register CHG_INT_CNFG - ADDR 0x19 ...... 118 Tab. 168. Register THM_ADJ_SETTING - ADDR 0x1A .............................................................. 118 Tab. 169. Register VBUS2SYS_CNFG - ADDR 0x1B ...119 Tab. 170. Register LED_PWM - ADDR 0x1C ............... 120 Tab. 171. Register FAULT_BATFET_CNFG - ADDR 0x1D .............................................................. 120 Tab. 172. Register LED_CNFG - ADDR 0x1E .............. 121 Tab. 173. Register LED_CNFG - ADDR 0x1F .............. 122 Tab. 174. Register PMIC bitmap ................................... 122 Tab. 175. Register charger bitmap ................................126 Tab. 176. Register OTP bitmap .....................................128 Tab. 177. Bill of materials ..............................................135 Tab. 178. Revision history ............................................. 142 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Application diagram ...........................................3 Functional block diagram .................................. 4 Internal block diagram .......................................5 Pinout diagram .................................................. 7 SWx DVS transitions .......................................26 SWx DVS and non-DVS selection ...................27 SW3 block diagram .........................................31 LDOy Block Diagram .......................................36 LDO2 block diagram ....................................... 39 VREFDDR block diagram ............................... 41 PF1550 Product data sheet Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Fig. 17. Fig. 18. VSNVS block diagram .....................................41 Battery charger internal block diagram ............42 Charger low battery (Startup sequence, USB insert, VBATT = 0 V) .............................. 43 Charger healthy battery (Startup sequence, USB insert, VBATT = 3.8 V) ............................44 Input source detection delay ........................... 45 Charger state diagram .................................... 46 Charging profile ...............................................47 Thermal regulation .......................................... 57 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 147 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Thermal regulation (Current versus Temp, example with REGTEMP[1:0] = 00 and hysteresis ........................................................ 58 Thermal regulation (Current, Temp versus Time, example with REGTEMP[1:0] = 00 and hysteresis ................................................. 58 Response to input voltage droop during charging ...........................................................60 DPM function ...................................................61 CC charge current and CV charge voltage adjustment ....................................................... 63 Response to battery overcurrent ..................... 66 I2C sequence .................................................. 72 PF1550 Product data sheet Fig. 26. Fig. 27. Fig. 28. Fig. 29. Fig. 30. Fig. 31. Fig. 32. Fig. 33. Fig. 34. PMIC state machine ........................................73 A4 startup and power down sequence ............ 79 Typical schematic .......................................... 134 Recommended shielding for critical signals ...137 Generic buck regulator architecture .............. 137 Layout example for buck regulators .............. 138 Package outline for HVQFN40 (SOT1369-4) ..................................................139 Package outline detail for HVQFN40 (SOT1369-4) ..................................................140 Package outline notes for HVQFN40 (SOT1369-4) ..................................................141 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 148 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors Contents 1 1.1 1.2 2 2.1 2.2 3 4 4.1 4.2 5 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 6.3.1 6.3.2 6.3.3 6.3.4 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 General description ............................................ 1 Features and benefits ........................................1 Applications ........................................................2 Application diagram ............................................3 Functional block diagram ...................................4 Internal block diagram ....................................... 5 Orderable parts ................................................... 5 Pinning information ............................................ 7 Pinning ............................................................... 7 Pin definitions .................................................... 8 General product characteristics ........................ 9 Thermal characteristics ......................................9 Absolute maximum ratings .............................. 10 Electrical characteristics .................................. 12 Electrical characteristics – Battery charger ...... 12 Electrical characteristics – SW1 and SW2 ....... 17 Electrical characteristics – SW3 ...................... 19 Electrical characteristics – LDO1 .....................20 Electrical characteristics – LDO2 .....................20 Electrical characteristics – LDO3 .....................21 Electrical characteristics – VREFDDR ............. 22 Electrical characteristics – VSNVS .................. 22 Electrical characteristics – IC level bias currents ............................................................ 23 Detailed description ..........................................24 Buck regulators ................................................25 SW1 and SW2 detailed description ................. 25 SWx dynamic voltage scaling description ........ 26 SWx DVS and non-DVS operation .................. 26 Regulator control ............................................. 27 Current limit protection .................................... 28 Output voltage setting in SWx ......................... 28 SWx external components ...............................31 SW3 detailed description .................................31 Regulator control ............................................. 32 Current limit protection .................................... 33 Output voltage setting in SW3 ......................... 33 SW3 external components .............................. 34 Low dropout linear regulators, VREFDDR and VSNVS ........................................................ 34 General description ..........................................34 LDO1 and LDO3 detailed description .............. 35 Features summary ...........................................35 LDOy block diagram ........................................ 36 LDOy external components ............................. 36 LDOy output voltage setting ............................ 36 LDOy low-power mode operation .................... 37 LDOy current limit protection ........................... 37 LDOy load switch mode .................................. 38 LDO2 detailed description ............................... 38 LDO2 features summary ................................. 38 LDO2 block diagram ........................................39 LDO2 external components ............................. 39 LDO2 output voltage setting ............................ 39 LDO2 Low-power mode operation ...................40 LDO2 current limit protection ...........................40 PF1550 Product data sheet 7.4 7.5 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5 8.9.6 8.10 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.7.1 9.7.2 10 10.1 10.1.1 10.1.2 10.1.3 10.2 10.2.1 10.2.2 10.2.3 10.3 10.4 10.5 VREFDDR reference ....................................... 40 VSNVS LDO/switch ......................................... 41 Battery charger description ............................. 42 Operating modes and behavioral description ........................................................43 Charger input source detection ....................... 45 Input self-discharge for reliable charger input interrupt ...................................................45 Charger state diagram .....................................46 Charging profile ............................................... 46 Precharge state ............................................... 47 Fast charge constant current state .................. 48 Fast charge constant voltage state ..................50 End-of-charge state ......................................... 53 Done state ....................................................... 54 Battery supplement mode ................................54 Power path features ........................................ 55 VSYS regulation .............................................. 55 Input current limit .............................................55 Battery thermistor ............................................ 56 BATFET soft start ............................................ 57 Thermal ............................................................57 Thermal regulation ...........................................57 Thermal foldback ............................................. 58 Input voltage regulation mode ......................... 59 JEITA thermal control ...................................... 62 Fault states ...................................................... 64 Timer fault state ...............................................64 Watchdog timer state .......................................65 Thermal shutdown state .................................. 65 Battery overvoltage state .................................65 Charger fault priority ........................................ 65 Battery overcurrent limit ...................................66 LED indicator ................................................... 67 Control and interface signals .......................... 68 PWRON ........................................................... 68 STANDBY ........................................................ 69 RESETBMCU .................................................. 69 INTB .................................................................70 WDI .................................................................. 70 ONKEY ............................................................ 71 Control interface I2C block description ............ 71 I2C device ID ...................................................71 I2C operation ................................................... 72 PF1550 state machine ...................................... 72 System ON states ........................................... 73 Run state ......................................................... 73 STANDBY state ............................................... 74 SLEEP state .................................................... 74 System OFF states ..........................................74 REGS_DISABLE ..............................................74 CORE_OFF ..................................................... 74 SHIP .................................................................75 Turn on events ................................................ 75 Turn off events .................................................75 State diagram and transition conditions ...........76 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 September 2021 © NXP B.V. 2021. All rights reserved. 149 / 150 PF1550 NXP Semiconductors Power management integrated circuit (PMIC) for low power application processors 10.6 Regulator power-up sequencer ....................... 77 10.7 Regulator power-down sequencer ................... 78 11 Device start up .................................................. 78 11.1 Startup timing diagram .................................... 78 11.2 Device start up configuration ........................... 79 12 Register map ..................................................... 80 12.1 Specific PMIC Registers (Offset is 0x00) ......... 80 12.2 Specific Charger Registers (Offset is 0x80) ... 105 12.3 Register PMIC bitmap ................................... 122 12.4 Register charger bitmap ................................ 126 12.5 Register OTP bitmap ..................................... 128 13 Application details .......................................... 133 13.1 Example schematic ........................................133 13.2 Bill of materials .............................................. 134 13.3 PF1550 layout guidelines .............................. 136 13.3.1 General board recommendations .................. 136 13.3.2 Component placement ...................................136 13.3.3 General routing requirements ........................ 136 13.3.4 Parallel routing requirements .........................136 13.3.5 Switching regulator layout recommendations .......................................... 137 13.4 Thermal information .......................................138 13.4.1 Rating data .................................................... 138 13.4.2 Estimation of junction temperature ................ 138 14 Package outline ...............................................139 15 Revision history .............................................. 142 16 Legal information ............................................ 144 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 September 2021 Document identifier: PF1550