MC33771BTB1AE

MC33771B_SDS Battery cell controller IC Rev. 6.0 — 22 June 2020 1 Product short data sheet General description The 33771 is a SMARTMOS lithium-ion battery cell controller IC designed for automotive applications, such as hybrid electric (HEV) and electric vehicles (EV) along with industrial applications, such as energy storage systems (ESS) and uninterruptible power supply (UPS) systems. The device performs ADC conversions of the differential cell voltages and current, as well as battery coulomb counting and battery temperature measurements. The information is digitally transmitted through the Serial Peripheral Interface (SPI) or Transformer Isolation (TPL) to a microcontroller for processing. 2 Features • • • • • • • • • • • • • • • • • 9.6 V ≤ VPWR ≤ 61.6 V operation, 75 V transient 7 to 14 cells management Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI Addressable on initialization 0.8 mV maximum total voltage measurement error Synchronized cell voltage/current measurement with coulomb count Total stack voltage measurement Seven GPIO/temperature sensor inputs 5.0 V at 5.0 mA reference supply output Automatic over/undervoltage and temperature detection routable to fault pin Integrated sleep mode over/undervoltage and temperature monitoring Onboard 300 mA passive cell balancing with diagnostics Hot plug capable Detection of internal and external faults, as open lines, shorts, and leakages Designed to support ISO 26262, up to ASIL D safety system Fully compatible with the MC33772 for a maximum of six cells Qualified in compliance with AEC–Q100 MC33771B_SDS NXP Semiconductors Battery cell controller IC 3 Simplified application diagram RDTX_OUT+ VCOM VPWR2 + CT14 CGND CB14 VANA + FAULT SDA CBn SCL CB2:1_C battery reference DGND CTn CT1 battery reference AGND CB14:13_C CT13 14 cell voltage measure VCOM RDTX_OUT- VPWR1 SPI_COM_EN MC33771 CB1 CTREF battery reference GNDREF GNDFLG FAULT RESET EEPROM (OPTIONAL) VCOM GPIOy GPIOx CSB CSB SO MISO SI/RDTX_IN+ MOSI SCLK/RDTX_IN- SCLK GPIO0 MCU VCOM GPIO1 ISENSE+ GPIO2 GPIO3 current measure GPIO4 ISENSE- GPIO5 GPIO6 battery reference aaa-027844 Figure 1. Simplified application diagram, SPI use case MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 2 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC RDTX_OUT+ RDTX_OUT- VPWR1 CT14 CGND CB14 + AGND FAULT CTn SDA CBn SCL CB2:1_C + EEPROM (OPTIONAL) SO MC33771 CB1 CSB SPI_COM_EN RESET SI/RDTX_IN+ CTREF cluster # 2 reference T1 SCLK/RDTX_IN- GNDREF cluster # 2 reference cluster # 2 reference DGND CT13 CT1 cluster # 2 reference VANA CB14:13_C 14 cell voltage measure VCOM cluster # 2 VCOM VPWR2 GPIO0 GNDFLG GPIO1 ISENSE+ VCOM cluster # 2 GPIO2 GPIO3 GPIO4 ISENSE- GPIO5 GPIO6 + VPWR1 RDTX_OUT+ VPWR2 RDTX_OUT- CT14 VCOM CB14 CGND FAULT CTn SDA CTREF GNDREF cluster # 1 reference GNDFLG ISENSE+ SO MC33771 BATTERY PACK CONTROLLER EEPROM (OPTIONAL) SCL CT1 CB1 cluster # 1 reference DGND CBn CB2:1_C cluster # 1 reference AGND CT13 + VCOM cluster # 1 VANA CB14:13_C 14 cell voltage measure cluster # 2 reference CSB SPI_COM_EN RESET SI/RDTX_IN+ cluster # 1 reference T1 T1 GPIO1 MCU MC33664 SPI2 SCLK/RDTX_INGPIO0 SPI1 VCOM cluster # 1 GPIO2 GPIO3 GPIO4 current measure ISENSE- GPIO5 GPIO6 cluster # 1 reference aaa-027845 Figure 2. Simplified application diagram, TPL use case 4 Applications • • • • MC33771BSDS Product short data sheet Automotive: 48 V and high-voltage battery packs E-bikes, e-scooters Energy storage systems Uninterruptible power supply (UPS) All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 3 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 5 Ordering information 5.1 Part numbers definition MC33771B x y z AE/R2 Table 1. Part number breakdown Code x y z MC33771BSDS Product short data sheet Option Description S x = S (SPI communication type) T x = T (TPL communication type) A y = A (Advanced) B y = B (Basic) P y = P (Premium) 1 z = 1 (7 to 14 channels) 2 z = 2 (7 to 8 channels) AE Package suffix R2 Tape and reel indicator All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 4 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 5.2 Part numbers list This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.nxp.com. Table 2. Advanced orderable part table Temperature range is −40 to 105 °C Package type is 64-pin LQFP-EP Orderable part Number of channels OV/UV Precision GPIO as temperature channels and OT/UT Current channel or coulomb count SPI communication protocol MC33771BSA1AE 7 to 14 Yes Yes No MC33771BSA2AE 7 to 8 Yes Yes No TPL differential communication protocol MC33771BTA1AE 7 to 14 Yes Yes No MC33771BTA2AE 7 to 8 Yes Yes No OV/UV Precision GPIO as temperature channels and OT/UT Current channel or coulomb count Table 3. Basic orderable part table Temperature range is −40 to 105 °C Package type is 64-pin LQFP-EP Orderable part Number of channels SPI communication protocol MC33771BSB1AE 7 to 14 Yes No No MC33771BSB2AE 7 to 8 Yes No No TPL differential communication protocol MC33771BTB1AE 7 to 14 Yes No No MC33771BTB2AE 7 to 8 Yes No No OV/UV Precision GPIO as temperature channels and OT/UT Current channel or coulomb count Table 4. Premium orderable part table Temperature range is −40 to 105 °C Package type is 64-pin LQFP-EP Orderable part Number of channels SPI communication protocol MC33771BSP1AE 7 to 14 Yes Yes Yes MC33771BSP2AE 7 to 8 Yes Yes Yes TPL differential communication protocol MC33771BTP1AE 7 to 14 Yes Yes Yes MC33771BTP2AE 7 to 8 Yes Yes Yes MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 5 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 6 Pinning information 49 GPIO0 50 GPIO1 51 GPIO2 52 GPIO3 53 GPIO4 54 GPIO5 55 GPIO6 56 ISENSE+ 57 ISENSE- 58 AGND 59 DGND 60 VANA 61 SCL 62 SDA terminal 1 index area 63 RESET 64 GNDREF 6.1 Pinout diagram VPWR2 1 48 RDTX_OUT+ VPWR1 2 47 SI/RDTX_IN+ CT_14 3 46 SCLK/RDXT_IN- CB_14 4 45 RDTX_OUT- CB_14:13C 5 44 CGND CB_13 6 43 VCOM CT_13 7 42 SO CT_12 8 CB_12 9 41 CSB 65 GNDFLAG 40 FAULT CB_12:11_C 10 39 SPI_COM_EN CB_11 11 38 CT_REF CT_11 12 37 CT_1 CT_10 13 36 CB_1 CB_10 14 35 CB_2:1_C CT_3 32 CB_3 31 CB_4:3_C 30 CB_4 29 CT_4 28 CT_5 27 CB_5 26 CB_6:5_C 25 CB_6 24 CT_6 23 CT_7 22 CB_7 21 CB_8:7_C 20 CB_8 19 33 CT_2 CT_8 18 34 CB_2 CB_9 16 CT_9 17 CB_10:9_C 15 aaa-027847 Transparent top view Figure 3. Pinout diagram 6.2 Pin definitions Table 5. Pin definitions MC33771BSDS Product short data sheet Number Name Function Definition 1 VPWR2 Input Power input to the 33771 2 VPWR1 Input Power input to the 33771 3 CT_14 Input Cell pin 14 input. Terminate to LPF resistor. 4 CB_14 Output Cell balance driver. Terminate to cell 14 cell balance load resistor. 5 CB_14:13_C Output Cell balance 14:13 common. Terminate to cell 14 and 13 common pin. 6 CB_13 Output Cell balance driver. Terminate to cell 13 cell balance load resistor. 7 CT_13 Input Cell pin 13 input. Terminate to LPF resistor. 8 CT_12 Input Cell pin 12 input. Terminate to LPF resistor. All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 6 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC MC33771BSDS Product short data sheet Number Name Function Definition 9 CB_12 Output Cell balance driver. Terminate to cell 12 cell balance load resistor. 10 CB_12:11_C Output Cell balance 12:11 common. Terminate to cell 12 and 11 common pin. 11 CB_11 Output Cell balance driver. Terminate to cell 11 cell balance load resistor. 12 CT_11 Input Cell pin 11 input. Terminate to LPF resistor. 13 CT_10 Input Cell pin 10 input. Terminate to LPF resistor. 14 CB_10 Output Cell balance driver. Terminate to cell 10 cell balance load resistor. 15 CB_10:9_C Output Cell balance 10:9 common. Terminate to cell 10 and 9 common pin. 16 CB_9 Output Cell balance driver. Terminate to cell 9 cell balance load resistor. 17 CT_9 Input Cell pin 9 input. Terminate to LPF resistor. 18 CT_8 Input Cell pin 8 input. Terminate to LPF resistor. 19 CB_8 Output Cell balance driver. Terminate to cell 8 cell balance load resistor. 20 CB_8:7_C Output Cell balance 8:7 common. Terminate to cell 8 and 7 common pin. 21 CB_7 Output Cell balance driver. Terminate to cell 7 cell balance load resistor. 22 CT_7 Input Cell pin 7 input. Terminate to LPF resistor. 23 CT_6 Input Cell pin 6 input. Terminate to LPF resistor. 24 CB_6 Output Cell balance driver. Terminate to cell 6 cell balance load resistor. 25 CB_6:5_C Output Cell balance 6:5 common. Terminate to cell 6 and 5 common pin. 26 CB_5 Output Cell balance driver. Terminate to cell 5 cell balance load resistor. 27 CT_5 Input Cell pin 5 input. Terminate to LPF resistor. 28 CT_4 Input Cell pin 4 input. Terminate to LPF resistor. 29 CB_4 Output Cell balance driver. Terminate to cell 4 cell balance load resistor. 30 CB_4:3_C Output Cell balance 4:3 common. Terminate to cell 4 and 3 common pin. 31 CB_3 Output Cell balance driver. Terminate to cell 3 cell balance load resistor. 32 CT_3 Input Cell pin 3 input. Terminate to LPF resistor. 33 CT_2 Input Cell pin 2 input. Terminate to LPF resistor. 34 CB_2 Output Cell balance driver. Terminate to cell 2 cell balance load resistor. All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 7 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC MC33771BSDS Product short data sheet Number Name Function Definition 35 CB_2:1_C Output Cell Balance 2:1 common. Terminate to cell 2 and 1 common pin. 36 CB_1 Output Cell balance driver. Terminate to cell 1 cell balance load resistor. 37 CT_1 Input Cell pin 1 input. Terminate to LPF resistor. 38 CT_REF Input Cell pin REF input. Terminate to LPF resistor. 39 SPI_COM_EN Input SPI communication enable, pin must be high for the SPI to be active 40 FAULT Output Fault output dependent on user defined internal or external faults. If not used, it must be left open. 41 CSB Input SPI chip select 42 SO Output SPI serial output 43 VCOM Output Communication regulator output. Decouple with 2.2 µF ceramic. 44 CGND Ground Communication decoupling ground. Terminate to GNDREF 45 RDTX_OUT- I/O Receive/transmit output negative 46 SCLK/RDTX_IN- I/O SPI clock or receive/transmit input negative 47 SI/RDTX_IN+ I/O SPI serial input or receiver/transmit input positive 48 RDTX_OUT+ I/O Receive/transmit output positive 49 GPIO0 I/O General purpose analog input or GPIO or wake-up or fault daisy chain 50 GPIO1 I/O General purpose analog input or GPIO 51 GPIO2 I/O General purpose analog input or GPIO or conversion trigger 52 GPIO3 I/O General purpose analog input or GPIO 53 GPIO4 I/O General purpose analog input or GPIO 54 GPIO5 I/O General purpose analog input or GPIO 55 GPIO6 I/O General purpose analog input or GPIO 56 ISENSE+ Input Current measurement input+ 57 ISENSE- Input Current measurement input− 58 AGND Ground Analog ground, terminate to GNDREF 59 DGND Ground Digital ground, terminate to GNDREF 60 VANA Output Precision ADC analog supply. Decouple with ceramic 47 nF ceramic capacitor to AGND. 61 SCL I/O I C clock 62 SDA I/O I C data 2 2 All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 8 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 7 Number Name Function Definition 63 RESET Input RESET is an active high input. RESET has an internal pull down. If not used, it can be tied to GND. 64 GNDREF Ground Ground reference for device. Terminate to reference of battery cluster. 65 GNDFLAG Ground Device flag. Terminate to lowest potential of battery cluster. General product characteristics 7.1 Ratings and operating requirements relationship The operating voltage range pertains to the VPWR pins referenced to the AGND pins. Table 6. Ratings vs. operating requirements Fatal range Handling range – no permanent failure • Permanent Lower limited operating range Normal operating range Upper limited operating range failure might • No permanent failure, • 100 % functional • IC parameters might be out occur but IC functionality is not of specification guaranteed • Detection of VPWR overvoltage is functional Fatal range • Permanent failure might occur VPWR < −0.3 V 75 V < VPWR 7.6 V ≤ VPWR < 9.6 V Reset range: –0.3 V ≤ VPWR < 7.6 V 9.6 V ≤ VPWR ≤ 61.6 V 61.6 V < VPWR ≤ 75 V In both upper and lower limited operating range, no information can be provided about IC performance. Only the detection of VPWR overvoltage is guaranteed in the upper limited operating range. Performance in normal operating range is guaranteed only if there is a minimum of seven battery cells in the stack. 7.2 Maximum ratings Table 7. Maximum ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (rating) Min Max Unit VPWR1, VPWR2 Supply input voltage −0.3 75 V CT14 Cell terminal voltage −0.3 75 V VPWR to CT14 Voltage across VPWR1,2 pins pair and CT14 pin −10 10.5 V −0.3 6.0 V Electrical ratings [1] CTN to CTN-1 Cell terminal differential voltage CTN(CURRENT) Cell terminal input current — ±500 µA CBN to CBN:N-1_C CBN:N-1_C to CBN-1 Cell balance differential voltage — 10 V CBN-1_C to CTn-1 Cell balance input to cell terminal input −10 +10 V MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 9 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Description (rating) Min Max Unit VISENSE ISENSE+ and ISENSE– pin voltage −0.3 2.5 V VCOM Maximum voltage may be applied to VCOM pin from external source — 5.8 V VANA Maximum voltage may be applied to VANA pin — 3.1 V VGPIO0 GPIO0 pin voltage –0.3 6.5 V VGPIOx GPIOx pins (x = 1 to 6) voltage –0.3 VCOM + 0.5 V VDIG Voltage I C pins (SDA, SCL) –0.3 VCOM + 0.5 V VRESET RESET pin –0.3 6.5 V VCSB CSB pin –0.3 6.5 V VSPI_COMM_EN SPI_COMM_EN –0.3 6.5 V VSO SO pin –0.3 VCOM + 0.5 V VGPIO5,6 Maximum voltage for GPIO5 and GPIO6 pins used as current input −0.3 2.5 V FAULT Maximum applied voltage to pin −0.3 7.0 V VCOMM Maximum voltage to pins RDTX_OUT+, RDTX_OUT–, SI/RDTX_ IN+, CLK/RDTX_IN– −10.0 10.0 V fSPI SPI frequency (SPI mode) — 4.2 MHz BRTPL Transformer communication bit rate (TPL mode) 1.9 2.1 Mbps fTPL Transformer signal frequency (TPL mode) 3.8 4.2 MHz VESD ESD voltage Human body model (HBM) Charge device model (CDM) Charge device model corner pins (CDM) — — — ±2000 ±500 ±750 VESD ESD voltage (VPWR1, VPWR2, CTx, CBx, GPIOx, ISENSE+, ISENSE−, RDTX_OUT+, RDTX_OUT−, SI/RDTX_IN+, SCLK/ RDTX_IN−) Human body model (HBM) VESD [1] [2] 2 ESD voltage (CTREF, CTx, CBx, GPIOx, ISENSE+, ISENSE−, RDTX_OUT+, RDTX_OUT−, SI/RDTX_IN+, SCLK/ RDTX_IN−) IEC 61000-4-2, Unpowered (Gun configuration: 330Ω / 150pF) HMM, Unpowered (Gun configuration: 330Ω / 150pF) ISO 10605:2009, Unpowered (Gun configuration: 2 kΩ / 150pF) ISO 10605:2009, Powered (Gun configuration: 2 kΩ / 150pF) V [2] V — ±4000 V — — — — ±8000 ±8000 ±8000 ±8000 Adjacent CT pins may experience an overvoltage that exceeds their maximum rating during OV/UV functional verification test or during open line diagnostic test. Nevertheless, the IC is completely tolerant to this special situation. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM) (CZAP = 4.0 pF). MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 10 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 7.3 Thermal characteristics Table 8. Thermal ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (rating) Min Max Unit TA TJ Operating temperature Ambient Junction −40 −40 +105 +150 TSTG Storage temperature −55 +150 °C — 260 °C Thermal ratings TPPRT °C Peak package reflow temperature [1] [2] Thermal resistance and package dissipation ratings RΘJB Junction-to-board (bottom exposed pad soldered to board) 64 LQFP EP [3] — 10 °C/W RΘJA Junction-to-ambient, natural convection, single-layer board (1s) 64 LQFP EP [4] — 59 °C/W RΘJA Junction-to-ambient, natural convection, four-layer board (2s2p) 64 LQFP EP [4] — 27 °C/W RΘJCTOP Junction-to-case top (exposed pad) 64 LQFP EP [6] — 14 °C/W Junction-to-case bottom (exposed pad) 64 LQFP EP [7] — 0.97 °C/W Junction to package top, natural convection [8] — 3 °C/W RΘJCBOTTOM ΨJT [1] [2] [3] [4] [5] [6] [7] [8] [5] [5] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts (MC33xxxD enter 33xxx), and review parametrics. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1), with the cold plate temperature used for the case temperature. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letter (Ψ) is not available, the thermal characterization parameter is written as Psi-JT. 7.4 Electrical characteristics Table 9. Static and dynamic electrical characteristics Characteristics noted under conditions 9.6 V ≤ VPWR ≤ 61.6 V, −40 °C ≤ TA ≤ 105 °C, GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 56 V, TA = 25 °C, unless otherwise noted. Symbol Parameter Min Typ Max Supply voltage Full parameter specification 9.6 — 61.6 Unit Power management VPWR(FO) MC33771BSDS Product short data sheet V All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 11 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter IVPWR Supply current (base value) Normal mode, cell balance OFF, ADC inactive, SPI communication inactive, IVCOM = 0 mA Normal mode, cell balance OFF, ADC inactive, TPL communication inactive, IVCOM = 0 mA Min Typ Max — 5.4 — — 8.0 — Unit mA IVPWR(TPL_TX) Supply current adder when TPL communication active — 50 — mA IVPWR(CBON) Supply current adder to set all 14 cell balance switches ON — 0.97 — mA IVPWR(ADC) Delta supply current to perform ADC conversions (addend) ADC1-A,B continuously converting ADC2 continuously converting — — 3.0 1.4 — — IVPWR(SS) Supply current in sleep mode and in idle mode, communication inactive, cell balance off, cyclic measurement off, oscillator monitor on SPI mode (25 °C) TPL mode (25 °C) mA µA — 40 — — 68 — IVPWR(CKMON) Clock monitor current consumption — 5 — µA VPWR(OV_FLAG) VPWR overvoltage fault threshold (flag) — 65 — V VPWR(LV_FLAG) VPWR low-voltage warning threshold (flag) — 12 — V VPWR(UV_POR) VPWR undervoltage shutdown threshold (POR) — 8.5 — V VPWR(HYS) VPWR UV hysteresis voltage — 200 — mV tVPWR(FILTER) VPWR OV, LV filter — 50 — µs VCOM VCOM output voltage — 5.0 — V IVCOM VCOM output current allocated for external use — — 5.0 mA VCOM(UV) VCOM undervoltage fault threshold — 4.4 — V VCOM_HYS VCOM undervoltage hysteresis — 100 — mV tVCOM(FLT_TIMER) VCOM undervoltage fault timer — 10 — µs tVCOM(RETRY) VCOM fault retry timer — 10 — ms VCOM(OV) VCOM overvoltage fault threshold 5.4 — 5.9 V ILIM(OC) VCOM current limit 65 — 140 mA RVCOM(SS) VCOM sleep mode pull-down resistor — 2.0 — kΩ VANA VANA output voltage (not used by external circuits) Decouple with 47 nF X7R 0603 or 0402 — 2.65 — VANA(UV) VANA undervoltage fault threshold — 2.4 — V VANA_HYS VANA undervoltage hysteresis — 50 — mV VANA(FLT_TIMER) VANA undervoltage fault timer — 11 — µs VANA(OV) VANA overvoltage fault threshold — 2.8 — V tVANA(RETRY) VANA fault retry timer — 10 — ms ILIM(OC) VANA current limit 5.0 — 10 mA RVANA_RPD VANA sleep mode pull-down resistor — 1.0 — kΩ tVANA VANA rise time (CL = 47 nF ceramic X7R only) — — 100 µs VCOM power supply VANA power supply V ADC1-A, ADC1-B MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 12 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit CTn(LEAKAGE) Cell terminal input leakage current (except in SLEEP mode when cell balancing is ON) — 10 — nA CTn(FV) Cell terminal input current - functional verification — 0.365 — mA CTN Cell terminal input current during conversion — 50 — nA RPD Cell terminal open load detection pull-down resistor — 950 — Ω VVPWR_RES VPWR terminal measurement resolution — 2.44141 — mV/LSB VVPWR_RNG VPWR terminal measurement range 9.6 — 75 V VPWRTERM_ERR VPWR terminal measurement accuracy −0.5 — 0.5 % VCT_RNG ADC differential input voltage range for CTn to CTn-1 0.0 — 4.85 V VCT_ANx_RES Cell voltage and ANx resolution in 15-bit MEAS_xxxx registers — 152.58789 — µV/LSB VERR33RT Cell voltage measurement error VCELL = 3.3 V, TA = 25 °C −0.8 ±0.4 0.8 mV VERR Cell voltage measurement error 0.1 V ≤ VCELL ≤ 4.8 V, −40 °C ≤ TA ≤ 105 °C (or −40 °C ≤ TJ ≤ 125 °C) — ±0.7 — VERR_1 Cell voltage measurement error 0 V ≤ VCELL ≤ 1.5 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤ 85 °C) — ±0.4 — VERR_2 Cell voltage measurement error 1.5 V ≤ VCELL ≤ 2.7 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤ 85 °C) — ±0.4 — VERR_3 Cell voltage measurement error 2.7 V ≤ VCELL ≤ 3.7 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤ 85 °C) — ±0.5 — VERR_4 Cell voltage measurement error 3.7 V ≤ VCELL ≤ 4.3 V, −40 °C ≤ TA ≤ 60 °C (or −40 °C ≤ TJ ≤ 85 °C) — ±0.7 — VERR_5 Cell voltage measurement error 1.5 V ≤ VCELL ≤ 4.5 V, −40 °C ≤ TA ≤ 105 °C (or −40 °C ≤ TJ ≤ 125 °C) — ±0.7 — VANx_ERR Magnitude of ANx error in the entire measurement range: Ratiometric measurement Absolute measurement after soldering and aging, input in the range [1.0, 4.5] V Absolute measurement after soldering and aging, input in the range [0, 4.85] V, for −40 °C < TA < 60 °C) Absolute measurement after soldering and aging, input in the range [0, 4.85] V, for −40 °C < TA < 105 °C) — — — — 16 10 −8.0 — 8.0 −11 — 11 mV mV mV mV mV mV mV tVCONV Single channel net conversion time 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 6.77 9.43 14.75 25.36 — — — — µs VV_NOISE Conversion noise 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 1800 1000 600 400 — — — — −300 — 300 µVrms ADC2/current sense module VINC ISENSE+/ISENSE− input voltage (reference to AGND) MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 mV © NXP B.V. 2020. All rights reserved. 13 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit VIND ISENSE+/ISENSE− differential input voltage range −150 — 150 mV VISENSEX(OFFSET) ISENSE+/ISENSE− input voltage offset error — — 0.5 µV IGAINERR ISENSE error including nonlinearities −0.5 — 0.5 % IISENSE_OL ISENSE open load injected current — 130 — µA VISENSE_OL ISENSE open load detection threshold — 460 — mV V2RES Current sense user register resolution — 0.6 — µV/LSB VPGA_SAT PGA saturation half-range Gain = 256 Gain = 64 Gain = 16 Gain = 4 — — — — 4.9 19.5 78.1 150.0 — — — — VPGA_ITH Voltage threshold for PGA gain increase Gain = 256 Gain = 64 Gain = 16 Gain = 4 — — — — — 2.344 9.375 37.50 — — — — VPGA_DTH Voltage threshold for PGA gain decrease Gain = 256 Gain = 64 Gain = 16 Gain = 4 — — — — 4.298 17.188 68.750 — — — — — tAZC_SETTLE Time to perform auto-zero procedure after enabling the current channel — 200 — tICONV ADC conversion time including PGA settling time 13 bit resolution 14 bit resolution 15 bit resolution 16 bit resolution — — — — 19.00 21.67 27.00 37.67 — — — — VI_NOISE Noise error at 16-bit conversion — 3.01 — µVrms VI_NOISE Noise error at 13-bit conversion — 8.33 — µVrms ADCCLK ADC2 and ADC1-A,B clocking frequency — 6.0 — MHz VDS(CLAMP) Cell balance driver VDS active clamp voltage — 11 — V VOUT(FLT_TH) Output fault detection voltage threshold Balance off (open load) Balance on (shorted load) — 0.55 — RPD_CB Output OFF open load detection pull-down resistor Balance off, open load detect disabled — 2.0 — IOUT(LKG) Output leakage current Balance off, open load detect disabled at VDS = 4.0 V — — 1.0 RDS(on) Drain-to-source on resistance IOUT = 300 mA, TJ = 105 °C IOUT = 300 mA, TJ = 25 °C IOUT = 300 mA, TJ = −40 °C — — — — 0.5 0.4 0.80 — — ILIM_CB Driver current limitation (shorted resistor) 310 — 950 mA tCB_AUTOP CB_AUTO_PAUSE timing — 4.0 — µs tON Cell balance driver turn on RL = 15 Ω — 350 — mV mV mV µs µs Cell balance drivers MC33771BSDS Product short data sheet V kΩ µA Ω µs All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 14 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit tOFF Cell balance driver turn off RL = 15 Ω — 200 — tBAL_DEGLICTH Short/open detect filter time — 20 — µs µs Internal temperature measurement IC_TEMP1_ERR IC temperature measurement error −3.0 — 3.0 K IC_TEMP1_RES IC temperature resolution — 0.032 — K/LSB TSD_TH Thermal shutdown — 170 — °C TSD_HYS Thermal shutdown hysteresis — 10 — °C Default operational parameters VCTOV(TH) Cell overvoltage threshold (8 bits), typical value is default value after reset 0.0 4.2 5.0 V VCTOV(RES) Cell overvoltage threshold resolution — 19.53125 — mV/LSB VCTUV(TH) Cell undervoltage threshold (8 bits), typical value is default value after reset 0.0 2.5 5.0 V VCTUV(RES) Cell undervoltage threshold resolution — 19.53125 — mV/LSB VGPIO_OT(TH) GPIOx configured as ANx input overtemperature threshold from POR — 1.16 — V VGPIO_OT(RES) Temperature voltage threshold resolution — 4.8828125 — mV/LSB VGPIO_UT(TH) GPIOx configured as ANx input undertemperature threshold from POR — 3.82 V VGPIO_UT(RES) Temperature voltage threshold resolution — 4.8828125 — mV/LSB — General purpose input/output GPIOx VIH Input high-voltage (3.3 V compatible) 2.0 — — V VIL Input low-voltage (3.3 V compatible) — — 1.0 V VHYS Input hysteresis — 100 — mV IIL Input leakage current Pins tristate, VIN = VCOM or AGND −100 — 100 IIDL Differential Input Leakage Current GPIO 5,6 GPIO 5,6 configured as digital inputs for current measurement −30 — 30 VOH Output high-voltage IOH = −0.5 mA VCOM − 0.8 — — V VOL Output low-voltage IOL = +0.5 mA — — 0.8 V VADC Analog ADC input voltage range for ratiometric measurements AGND — VCOM V VOL(TH) Analog input open pin detect threshold — 0.15 — V ROPENPD Internal open detection pull-down resistor 3.8 5.0 — kΩ tGPIO0_WU GPIO0 WU de-glitch filter — 50 — µs tGPIO0_FLT GPIO0 daisy chain de-glitch filter both edges — 20 — µs tGPIO2_SOC GPIO2 convert trigger de-glitch filter — 2.0 — µs tGPIOx_DIN GPIOx configured as digital input de-glitch filter 2.5 — 5.6 µs VIH_RST Input high-voltage (3.3 V compatible) 2.0 — — V VIL_RST Input low-voltage (3.3 V compatible) — — 1.0 V VHYS Input hysteresis — 0.6 — V nA nA Reset input MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 15 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit tRESETFLT RESET de-glitch filter — 100 — µs RRESET_PD Input logic pull down (RESET) — 100 — kΩ VIH Input high-voltage (3.3 V compatible) 2.0 — — V VIL Input low-voltage (3.3 V compatible) — — 1.0 V VHYS Input hysteresis — 450 — mV RSPI_COM_EN_PD Input pull-down resistor (SPI_COM_EN) — 100 — kΩ — 150 — Ω SPI_COM_EN input Bus switch for TPL communication RXTERM Bus termination resistor (open resistor when bus switch is closed) Remark: If the bus switch is closed, then the termination resistor is open, else the termination resistor is connected. At the end of the daisy chain, the switch must be open, so that the transmission line is properly terminated. Digital interface VFAULT_HA FAULT output (high active, IOH = 1.0 mA) 4.0 4.9 6.0 V IFAULT_CL FAULT output current limit 3.0 — 40 mA RFAULT_PD FAULT output pull-down resistance — 100 — kΩ VIH_COMM Voltage threshold to detect the input as high SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL (NOTE: needs to be 3.3 V compatible) — — 2.0 VIL_COMM Voltage threshold to detect the input as low SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL 0.8 — — VHYS Input hysteresis SI/RDTX_IN+, SCLK/RDTX_IN−, CSB, SDA, SCL — 80 — ILOGIC_SS Sleep state input logic current CSB −100 — 100 RSCLK_PD Input logic pull-down resistance (SCLK/RDTX_IN–, SI/RDTX+) — 20 — kΩ RI_PU Input logic pull-up resistance to VCOM (CSB, SDA, SCL) — 100 — kΩ ISO_TRI Tristate SO input current 0 V to VCOM −2.0 — 2.0 µA VSO_HIGH SO high-state output voltage with ISO(HIGH) = −2.0 mA VCOM − 0.4 — — V VSO_LOW SO, SDA, SLK low-state output voltage with ISO(HIGH) = −2.0 mA — — 0.4 V CSBWU_FLT CSB wake-up de-glitch filter, low to high transition — 50 — µs V V mV nA System timing tCELL_CONV tSYNC Time needed to acquire all 14 cell voltages and the current after an on demand conversion 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 59 80 123 208 — — — — V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 13 bit ADC1-A,B at 14 bit, ADC2 at 13 bit ADC1-A,B at 15 bit, ADC2 at 13 bit ADC1-A,B at 16 bit, ADC2 at 13 bit — — — — 48.16 53.50 64.16 85.50 — — — — MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 µs µs © NXP B.V. 2020. All rights reserved. 16 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max tSYNC V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 14 bit ADC1-A,B at 14 bit, ADC2 at 14 bit ADC1-A,B at 15 bit, ADC2 at 14 bit ADC1-A,B at 16 bit, ADC2 at 14 bit — — — — 52.14 57.48 68.14 89.48 — — — — tSYNC V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 15 bit ADC1-A,B at 14 bit, ADC2 at 15 bit ADC1-A,B at 15 bit, ADC2 at 15 bit ADC1-A,B at 16 bit, ADC2 at 15 bit — — — — 62.12 65.46 76.12 97.46 — — — — tSYNC V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 16 bit ADC1-A,B at 14 bit, ADC2 at 16 bit ADC1-A,B at 15 bit, ADC2 at 16 bit ADC1-A,B at 16 bit, ADC2 at 16 bit — — — — 120.51 117.84 112.51 113.39 — — — — tVPWR(READY) Time after VPWR connection for the IC to be ready for initialization — — 5.0 tWAKE-UP Sleep mode to normal mode device ready Wake-up from fault Wake-up from GPIO Wake-up from network Wake-up from CSB — — — — — — — — 400 400 400 400 Unit µs µs µs ms µs Sleep mode to normal mode time after TPL bus wake-up — — 1.0 ms tWAKE_DELAY Time between wake pulses — 600 — µs tIDLE Idle timeout after POR — 60 — s tWAKE_INIT Wake-up signaling timeout after POR — 0.65 — s tBALANCE Cell balance timer range 0.5 — 511 min tCYCLE Cyclic acquisition timer range 0.0 — 8.5 s tFAULT Fault detection to activation of fault pin Normal mode — — 56 tDIAG Diagnostic mode timeout 0.047 1.0 8.5 tEOC SOC to data ready (includes post processing of data) 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 148 201 307 520 — — — — tSETTLE Time after SOC to begin converting with ADC1-A,B — 12.28 — tSYS_MEAS1 Time needed to send an SOC command and read back 96 cell voltages, 48 temperatures, 1 current, and 1 coulomb counter and ADC1-A,B configured as follows: 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution tSYS_MEAS2 Time needed to send an SOC command and read back 96 cell voltages, 1 current, and 1 coulomb counter and ADC1-A,B configured as follows: 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 µs s µs µs ms — — — — 3.73 3.78 3.89 4.10 — — — — ms — — — — 2.64 2.69 2.80 3.01 — — — — © NXP B.V. 2020. All rights reserved. 17 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter tCLST_TPL Time needed to send an SOC command and read back 14 cell voltages, 7 temperatures, 1 current, and 1 coulomb counter with TPL communication working at 2.0 Mbps and ADC1-A,B configured as follows: 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution tCLST_SPI Min Typ Max Unit ms — — — — Time needed to send an SOC command and read back 14 cell voltages, 7 temperatures, 1 current, and 1 coulomb counter with SPI communication working at 4.0 Mbps and ADC1-A,B configured as follows: 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution 0.79 0.85 0.95 1.16 — — — — ms — — — — 0.48 0.54 0.64 0.86 — — — — tI2C_DOWNLOAD Time to download EEPROM calibration after POR — — 1.0 ms tI2C_ACCESS EEPROM access time, EEPROM write (depends on device selection) — 5.0 — ms tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 00 — 500 — tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 01 — 1.0 — tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 10 — 10 — tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 11 — 100 — tWAVE_DC_ON Daisy chain duty cycle on time — 500 550 µs tCOM_LOSS Time out to reset the IC in the absence of communication — 1024 — ms µs ms ms ms SPI interface CLK/RDTX_IN– frequency [1] — — 4.0 MHz SCLK/RDTX_IN– high time (A) [1] 125 — — ns SCLK/RDTX_IN– high time (B) [1] 125 — — ns tSCK SCLK/RDTX_IN− period (A+B) [1] 250 — — ns tFALL SCLK/RDTX_IN− falling time — — 15 ns tRISE SCLK/RDTX_IN− rising time — — 15 ns SCLK/RDTX_IN− setup time (O) [1] 20 — — ns SCLK/RDTX_IN– hold time (P) [1] 20 — — ns SI/RDTX_IN+ setup time (F) [1] 40 — — ns tSI_HOLD SI/RDTX_IN+ hold time (G) [1] 40 — — ns tSO_VALID SO data valid, rising edge of SCLK/RDTX_IN− to SO data valid (I) [1] — — 40 ns SO enable time (H) [1] — — 40 ns SO disable time (K) [1] — — 40 ns CSB lead time (L) [1] 100 — — ns tCSB_LAG CSB lag time (M) [1] 100 — — ns tTD Sequential data transfer delay (N) [1] 1.0 — — µs FSCK tSCK _H tSCK _L tSET tHOLD tSI_SETUP tSO_EN tSO_DISABLE tCSB_LEAD MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 18 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit VRDTX INTH Differential receiver threshold — 580 — mV VRDTX INHYS Differential receiver threshold hysteresis — 100 — mV tRES Slave response after write command (echo) — 2.35 — µs TPL interface [1] See Figure 4 7.5 Timing diagrams CSB N Don't care level O L A B M P Don't care level SCLK H SO Tri-state K I MSB LSB F SI Tri-state G MSB LSB aaa-027848 Figure 4. Low-voltage SPI interface timing Figure 5. Transformer communication signaling MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 19 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 8 Packaging 8.1 Package mechanical dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Table 10. Package Outline Package 64-pin LQFP-EP MC33771BSDS Product short data sheet Suffix Package outline drawing number AE 98ASA10763D All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 20 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 21 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 22 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 23 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Figure 6. Package outline MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 24 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 9 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes MC33771BSDS v.6.0 20200622 Product data sheet — MC33771BSDS v.5.0 Modifications: Updated to align with full data sheet, MC33771B v.6.0 MC33771BSDS v.5.0 20180502 — MC33771BSDS v.1 Modifications: Updated to align with full data sheet, MC33771B v.5.0 MC33771BSDS v.1 20180419 — — MC33771BSDS Product short data sheet Technical data Product preview All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 25 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC 10 Legal information 10.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 10.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 10.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without MC33771BSDS Product short data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 26 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 10.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. SMARTMOS — is a trademark of NXP B.V. MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 27 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Part number breakdown ....................................4 Advanced orderable part table .......................... 5 Basic orderable part table ................................. 5 Premium orderable part table ............................5 Pin definitions ....................................................6 Ratings vs. operating requirements ...................9 Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Maximum ratings ...............................................9 Thermal ratings ............................................... 11 Static and dynamic electrical characteristics ... 11 Package Outline .............................................. 20 Revision history ...............................................25 Fig. 4. Fig. 5. Fig. 6. Low-voltage SPI interface timing .....................19 Transformer communication signaling .............19 Package outline ...............................................24 Figures Fig. 1. Fig. 2. Fig. 3. Simplified application diagram, SPI use case .... 2 Simplified application diagram, TPL use case ................................................................... 3 Pinout diagram .................................................. 6 MC33771BSDS Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 22 June 2020 © NXP B.V. 2020. All rights reserved. 28 / 29 MC33771B_SDS NXP Semiconductors Battery cell controller IC Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 8 8.1 9 10 General description ............................................ 1 Features ............................................................... 1 Simplified application diagram .......................... 2 Applications .........................................................3 Ordering information .......................................... 4 Part numbers definition ......................................4 Part numbers list ............................................... 5 Pinning information ............................................ 6 Pinout diagram .................................................. 6 Pin definitions .................................................... 6 General product characteristics ........................ 9 Ratings and operating requirements relationship .........................................................9 Maximum ratings ............................................... 9 Thermal characteristics ....................................11 Electrical characteristics .................................. 11 Timing diagrams .............................................. 19 Packaging .......................................................... 20 Package mechanical dimensions .................... 20 Revision history ................................................ 25 Legal information .............................................. 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2020. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 June 2020 Document identifier: MC33771BSDS