MC33772BTP1AE

MC33772B Battery cell controller IC Rev. 6.0 — 2 April 2020 1 Short data sheet: technical data General description The 33772 is a SMARTMOS lithium-ion battery cell controller IC designed for automotive applications, such as hybrid electric (HEV) and electric vehicles (EV) along with industrial applications, such as energy storage systems (ESS) and uninterruptible power supply (UPS) systems. The device performs ADC conversions of the differential cell voltages and current, as well as battery coulomb counting and battery temperature measurements. The information is digitally transmitted through the Serial Peripheral Interface (SPI) or Transformer Isolation (TPL) to a microcontroller for processing. 2 Features • • • • • • • • • • • • • • • • • 5.0 V ≤ VPWR ≤ 30 V operation, 40 V transient 3 to 6 cells management 0.8 mV total cell voltage measurement error Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI Addressable on initialization Synchronized cell voltage/current measurement with coulomb count Total stack voltage measurement Seven GPIO/temperature sensor inputs 5.0 V reference supply output with 5 mA capability Automatic over/undervoltage and temperature detection routable to fault pin Integrated sleep mode over/undervoltage and temperature monitoring Onboard 300 mA passive cell balancing with diagnostics Hot plug capable Detection of internal and external faults, as open lines, shorts, and leakages Designed to support ISO 26262 up to ASIL D safety system Fully compatible with the MC33771 for a maximum of 14 cells Qualified in compliance with AEC-Q100 MC33772B NXP Semiconductors Battery cell controller IC 3 Simplified application diagram RDTX_OUT+ VCOM VPWR2 + CT6 CGND CB6 VPRE AGND CT5 CTn SDA CBn SCL CB2:1_C SPI_COM_EN VCP MC33772 CB1 CTREF GNDSUB battery reference battery reference DGND CT1 + battery reference VANA CB6:5_C 6 cell voltage measure VCOM RDTX_OUT- VPWR1 GNDFLG ISENSE+ GNDCP FAULT RESET CSB SO EEPROM (OPTIONAL) VPRE battery reference GPIOy GPIOx CSB MISO SI/RDTX_IN+ MOSI SCLK/RDTX_IN- SCLK GPIO0 MCU VCOM GPIO1 current measure GPIO2 ISENSE- GPIO3 GPIO4 GPIO5 GPIO6 battery reference aaa-029758 Figure 1. Simplified application diagram, SPI use case MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 2 / 27 MC33772B NXP Semiconductors Battery cell controller IC VPWR1 RDTX_OUT+ VPWR2 RDTX_OUT- CT6 CB6 + VCOM cluster # 2 VCOM CGND CB6:5_C cluster # 2 reference VPRE CT5 VANA AGND cluster # 2 reference DGND 6 cell voltage measure CTn FAULT CBn SDA SCL SO CT1 MC33772 RESET SI/RDTX_IN+ CB1 VCP GNDSUB GNDCP GNDFLG GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 ISENSE+ ISENSE- VPWR1 RDTX_OUT+ VPWR2 RDTX_OUT- CT6 T1 cluster # 2 reference VCOM cluster # 2 cluster # 2 reference VCOM cluster # 1 VCOM CB6 + cluster # 2 reference SCLK/RDTX_IN- CTREF cluster # 2 reference CSB SPI_COM_EN CB2:1_C + EEPROM (OPTIONAL) CGND CB6:5_C cluster # 1 reference VPRE CT5 VANA AGND cluster # 1 reference DGND 6 cell voltage measure CTn FAULT CBn SDA SCL SO CT1 CB2:1_C + CB1 CTREF GNDSUB GNDFLG cluster # 1 reference current measure ISENSE+ ISENSE- MC33772 BATTERY PACK CONTROLLER EEPROM (OPTIONAL) CSB SPI_COM_EN RESET SI/RDTX_IN+ cluster # 1 reference T1 T1 GNDCP GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 MCU MC33664 SPI2 SCLK/RDTX_INVCP SPI1 cluster # 1 reference VCOM cluster # 1 cluster # 1 reference aaa-029759 Figure 2. Simplified application diagram, TPL use case MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 3 / 27 MC33772B NXP Semiconductors Battery cell controller IC 4 Applications • • • • • 5 Automotive: 12 V to high-voltage battery packs E-bikes, e-scooters Energy Storage Systems (ESS) Uninterruptible Power Supply (UPS) Battery junction box Ordering information 5.1 Part numbers definition MC33772B x y z AE/R2 Table 1. Part number breakdown Code x y z MC33772B_SDS Short data sheet: technical data Option Description S x = S (SPI communication type) T x = T (TPL communication type) A y = A (Advanced) B y = B (Basic) C y = C (Current) P y = P (Premium) 0 z = 0 (0 channels) 1 z = 1 (3 to 6 channels) 2 z = 2 (3 to 4 channels) AE Package suffix R2 Tape and reel indicator All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 4 / 27 MC33772B NXP Semiconductors Battery cell controller IC 5.2 Part numbers list This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided at http://www.nxp.com. Table 2. Orderable part variations Part Number [1] Precise differential Number of cell voltage monitored cells CTx Cell OV/UV Cell balancing Precision GPIO as temperature measurement channel and OT/UT Functional verification and diagnostics Current measurement channel and coulomb counter Communication SPI TPL MC33772BSA1AE Yes Yes 3 to 6 Yes Yes Yes No Yes No MC33772BSA2AE Yes Yes 3 to 4 Yes Yes Yes No Yes No MC33772BSP1AE Yes Yes 3 to 6 Yes Yes Yes Yes Yes No MC33772BSP2AE Yes Yes 3 to 4 Yes Yes Yes Yes Yes No MC33772BTA1AE Yes Yes 3 to 6 Yes Yes Yes No Yes Yes MC33772BTA2AE Yes Yes 3 to 4 Yes Yes Yes No Yes Yes MC33772BTB1AE Yes Yes 3 to 6 No No No No Yes Yes MC33772BTC0AE No No 0 No Yes Yes Yes Yes Yes MC33772BTP1AE Yes Yes 3 to 6 Yes Yes Yes Yes Yes Yes MC33772BTP2AE Yes Yes 3 to 4 Yes Yes Yes Yes Yes Yes [1] To order parts in tape and reel, add an R2 suffix to the part number. MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 5 / 27 MC33772B NXP Semiconductors Battery cell controller IC 6 Pinning information 37 AN1/GPIO1 38 AN2/GPIO2 39 AN3/GPIO3 40 AN4/GPIO4 41 AN5/GPIO5 42 AN6/GPIO6 43 ISENSE+ 44 ISENSE- 45 AGND 46 DGND terminal 1 index area 47 VANA 48 GNDSUB 6.1 Pinout diagram VPWR2 1 36 AN0/GPIO0 VPWR1 2 35 RDTX_OUT+ FAULT 3 34 SI/RDTX_IN+ VPRE 4 33 SCLK/RDTX_IN- VCP 5 GNDCP 6 CT_6 7 CB_6 8 29 CSB CB_6:5_C 9 28 VDDIO 32 RDTX_OUT31 CGND 48 LQFP-EP GNDFLAG 30 VCOM Transparent top view RESET 24 SPI_COM_EN 23 CT_REF 22 CT_1 21 CB_1 20 CB_2:1_C 19 CB_2 18 CT_2 17 CT_3 16 25 SDA CB_3 15 26 SCL CT_4 12 CB_4 13 27 SO CT_5 11 CB_4:3_C 14 CB_5 10 aaa-029761 Figure 3. Pinout diagram 6.2 Pin definitions Table 3. Pin definitions Pin number Pin name Pin function Definition 1 VPWR2 Input Power supply input to the 33772 2 VPWR1 Input Power supply input to the 33772 3 FAULT Output Fault output dependent on user defined internal or external faults. If not used, it must be left open. 4 VPRE Output Pre-regulator voltage. Connect to 470 nF capacitor. 5 VCP Output Charge pump capacitor ground, decouple with 10 nF. 6 GNDCP Ground Charge pump capacitor ground 7 CT_6 Input Cell terminal pin 6 input. Terminate to LPF resistor. 8 CB_6 Output Cell balance driver. Terminate to cell 6 cell balance load resistor. 9 CB_6:5_C Output Cell balance 6:5 common. Terminate to cell 6 and 5 common pin. 10 CB_5 Output Cell balance driver. Terminate to cell 5 cell balance load resistor. 11 CT_5 Input Cell terminal pin 5 input. Terminate to LPF resistor. 12 CT_4 Input Cell terminal pin 4 input. Terminate to LPF resistor. 13 CB_4 Output Cell balance driver. Terminate to cell 4 cell balance load resistor. MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 6 / 27 MC33772B NXP Semiconductors Battery cell controller IC Pin number Pin name Pin function Definition 14 CB_4:3_C Output Cell balance 4:3 common. Terminate to cell 4 and 3 common pin. 15 CB_3 Output Cell balance driver. Terminate to cell 3 cell balance load resistor. 16 CT_3 Input Cell terminal pin 3 input. Terminate to LPF resistor. 17 CT_2 Input Cell pin 2 input. Terminate to LPF resistor. 18 CB_2 Output Cell balance driver. Terminate to cell 2 cell balance load resistor. 19 CB_2:1_C Output Cell balance 2:1 common. Terminate to cell 2 and 1 common pin. 20 CB_1 Output Cell balance driver. Terminate to cell 1 cell balance load resistor. 21 CT_1 Input Cell pin 1 input. Terminate to LPF resistor. 22 CT_REF Input Cell terminal REF input. Terminate to LPF resistor. 23 SPI_COM_EN Input SPI communication enable input. Wire to VPRE to use SPI communication, else wire to ground to use TPL communication. 24 RESET Input RESET is an active high input. RESET has an internal pull down. If not used, it can be shorted to GND. 25 SDA I/O I C data 26 SCL I/O I C clock 27 SO Output SPI serial output 28 VDDIO Input IO voltage for I C and SPI interfaces. Voltage level corresponding to Logic 1 will be the same as VDDIO. 29 CSB Input SPI active low chip select. If not used, it must be shorted to ground. 30 VCOM Output Communication regulator output, decouple with 2.2 µF to CGND. 31 CGND Ground Communication decoupling ground, terminate to GNDSUB. 32 RDTX_OUT− I/O TPL receive/transmit output negative 33 SCLK/RDTX_IN- I/O SPI clock or TPL receive/transmit input negative 34 SI/RDTX_IN+ I/O SPI serial input or TPL receive/transmit input positive 35 RDTX_OUT+ I/O TPL receive/transmit output positive 36 AN0 GPIO0 I/O General purpose input/output 37 AN1 GPIO1 I/O General purpose input/output 38 AN2 GPIO2 I/O General purpose input/output 39 AN3 GPIO3 I/O General purpose input/output 40 AN4 GPIO4 I/O General purpose input/output 41 AN5 GPIO5 I/O General purpose input/output 42 AN6 GPIO6 I/O General purpose input/output 43 ISENSE+ Input Current measurement input + 44 ISENSE− Input Current measurement input − 45 AGND I/O Analog ground, terminate to GNDSUB 46 DGND I/O Digital ground, terminate to GNDSUB 47 VANA Output Precision ADC analog supply. Decouple with 47 nF capacitor to AGND. 48 GNDSUB Ground Ground reference for device, terminate to reference of battery cluster. 49 GNDFLAG Ground Exposed pad, terminate to lowest potential of the battery cluster and to heat dissipation area of PCB. MC33772B_SDS Short data sheet: technical data 2 2 2 All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 7 / 27 MC33772B NXP Semiconductors Battery cell controller IC 7 General product characteristics 7.1 Ratings and operating requirements relationship The operating voltage range pertains to the VPWR pins referenced to the AGND pins. Table 4. Ratings vs. operating requirements Fatal range Lower limited operating range Normal operating range Permanent failure may occur No permanent failure, but IC functionality is not guaranteed 100 % functional VPWR < −0.3 V 5.0 V ≤ VPWR ≤ 6.0 V (SPI) 6.4 V ≤ VPWR ≤ 7.0 V (TPL) Reset range: –0.3 V ≤ VPWR ≤ 5.0 V (SPI) –0.3 V ≤ VPWR ≤ 6.4 V (TPL) POR with VPWR falling: 4.8 V ≤ VPWR < 5.0 V (SPI) 6.1 V ≤ VPWR < 6.4 V (TPL) POR with VPWR rising: 5.6 V ≤ VPWR < 6.0 V (SPI) 6.6 V ≤ VPWR < 7.0 V (TPL) 6.0 V ≤ VPWR ≤ 30 V (SPI) 7.0 V ≤ VPWR ≤ 30 V (TPL) Upper limited operating range Fatal range Permanent failure may occur 30 V < VPWR ≤ 40 V 40 V < VPWR IC parameters might be out of specification. Detection of VPWR overvoltage is functional Handling range - No permanent failure In both upper and lower limited operating range, no information can be provided about IC performance. Only the detection of VPWR overvoltage is guaranteed in the upper limited operating range. Performance in normal operating range is guaranteed only if there is a minimum of three battery cells in the stack. 7.2 Maximum ratings Table 5. Maximum ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction or permanent damage to the device. Symbol Description (rating) Min Max Unit Electrical ratings VPWR1, VPWR2 Supply input voltage –0.3 40 V CT6 Cell terminal voltage −0.3 40 V VPWR to CT6 Voltage across VPWR1,2 pins pair and CT6 pin CTN to CTN-1 Cell terminal differential voltage CTN(CURRENT) CBN to CBN:N-1_C CBN:N-1_C to CBN-1 CBN-1 to CTN-1 VISENSE VCOM VANA −10 10 V −0.3 6.7 V Cell terminal input current — ±500 µA Cell balance differential voltage — 10 V Cell balance input to cell terminal input −10 +10 V ISENSE+ and ISENSE– pin voltage −0.5 2.5 V Maximum voltage may be applied to VCOM pin from external source — 5.8 V Maximum voltage may be applied to VANA pin — 3.1 V MC33772B_SDS Short data sheet: technical data [1] All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 8 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Description (rating) Min Max Unit VPRE Maximum voltage which may be applied to VPRE pin from external source — 7.0 V VCP Maximum voltage which may be applied to VCP pin from external source — 14 V VDDIO Maximum voltage which may be applied to VDDIO pin from external source — 5.8 V VGPIO0 GPIO0 pin voltage –0.3 6.5 V VGPIOx GPIOx pins (x = 1 to 6) voltage –0.3 VCOM + 0.5 V VDIG Voltage I C pins (SDA, SCL) –0.3 VDDIO + 0.5 V VRESET RESET pin –0.3 6.5 V VCSB CSB pin –0.3 6.5 V VSPI_COMM_EN SPI_COMM_EN –0.3 7.0 VSO SO pin –0.3 VDDIO + 0.5 V VGPIO5,6 Maximum voltage for GPIO5 and GPIO6 pins used as current input −0.3 2.5 V FAULT Maximum applied voltage to pin −0.3 7.0 V VCOMM Maximum voltage to pins RDTX_OUT+, RDTX_OUT–, SI/RDTX_IN+, CLK/RDTX_IN– −10 10 V fSPI SPI frequency (SPI mode) — 4.2 MHz BRTPL Transformer communication bit rate (TPL mode) 1.9 2.1 Mbps fTPL Transformer signal frequency (TPL mode) 3.8 4.2 MHz VESD ESD voltage Human body model (HBM) Charge device model (CDM) Charge device model corner pins (CDM) — — — ±2000 ±500 ±750 VESD ESD voltage (CTx, CBx, GPIOx, ISENSE+, ISENSE–, RDTX_OUT+, RDTX_OUT–, SI/RDTX_IN+, SCLK/ RDTX_IN–) Human body model (HBM) VESD ESD voltage (CTREF, CTx,, GPIOx, ISENSE+, ISENSE−, RDTX_ OUT+, RDTX_OUT−, SI/RDTX_IN+, SCLK/ RDTX_IN−) IEC 61000-4-2, Unpowered (Gun configuration: 330 Ω / 150 pF) HMM, Unpowered (Gun configuration: 330 Ω / 150 pF) ISO 10605:2009, Unpowered (Gun configuration: 2 kΩ / 150 pF) ISO 10605:2009, Powered (Gun configuration: 2 kΩ / 150 pF) [1] [2] 2 V V [2] V — ±4000 V — — — — ±8000 ±8000 ±8000 ±8000 Adjacent CT pins may experience an overvoltage that exceeds their maximum rating during OV/UV functional verification test or during open line diagnostic test. Nevertheless, the IC is completely tolerant to this special situation. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω). 7.3 Thermal characteristics Table 6. Thermal ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings might cause a malfunction or permanent damage to the device. Symbol Description (rating) Min Max Unit TA TA TJ Operating temperature Ambient (SPI application) Ambient (TPL application) Junction –40 –40 –40 +125 +105 +150 TSTG Storage temperature −55 +150 °C TPPRT Peak package reflow temperature — 260 °C Thermal ratings °C [1] [2] Thermal resistance and package dissipation ratings MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 9 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Description (rating) RΘJB Junction-to-board (bottom exposed pad soldered to board) 48 LQFP EP Min Max Unit [3] — 11 °C/W RΘJA Junction-to-ambient, natural convection, singlelayer board (1s) 48 LQFP EP [4] [5] — 72 °C/W RΘJA Junction-to-ambient, natural convection, fourlayer board (2s2p) 48 LQFP EP [4] [5] — 30 °C/W RΘJCTOP Junction-to-case top (exposed pad) 48 LQFP EP [6] — 24 °C/W RΘJCBOTTOM Junction-to-case bottom (exposed pad) 48 LQFP EP [7] — 0.98 °C/W ΨJT Junction to package top, natural convection [8] — 4 °C/W [1] [2] [3] [4] [5] [6] [7] [8] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts (MC33xxxD enter 33xxx), and review parametrics. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1), with the cold plate temperature used for the case temperature. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letter (Ψ) is not available, the thermal characterization parameter is written as Psi-JT. MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 10 / 27 MC33772B NXP Semiconductors Battery cell controller IC 7.4 Electrical characteristics Table 7. Static and dynamic electrical characteristics Characteristics noted under conditions: 6.0 V ≤ VPWR ≤ 30 V (SPI mode) or 7.0 V ≤ VPWR ≤ 30 V (TPL mode), −40 °C ≤ TA ≤ 125 °C (SPI mode) or –40 °C ≤ TA ≤ 105 °C (TPL mode), GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Symbol Parameter Min Typ Max Unit Power management VPWR(FO) IVPWR Supply voltage Full parameter specification (SPI application) Full parameter specification (TPL application) V Supply current (base value) Normal mode, cell balance OFF, ADC inactive, SPI communication inactive, IVCOM = 0 mA Normal mode, cell balance OFF, ADC inactive, TPL communication inactive, IVCOM = 0 mA 6.0 7.0 — — 30 30 — 6.0 — — 8.0 — mA IVPWR(TPL_TX) Supply current adder when TPL communication active — 50 — mA IVPWR(CBON) Supply current adder to set all 6 cell balance switches ON — 2.0 — mA IVPWR(ADC) Delta supply current to perform ADC conversions (addend) ADC1-A,B continuously converting ADC2 continuously converting IVPWR(SS) mA — — 4.7 1.0 — — SPI mode (TA = 25 °C) — 32 — SPI mode (−40 °C ≤ TA ≤ 85 °C) — — 60 SPI mode (TA = 125 °C) — 42 — TPL mode (TA = 25 °C) — 75 — TPL mode (−40 °C ≤ TA ≤ 85 °C) — — 100 TPL mode (TA = 125 °C) — — 130 SPI mode (TA = 25 °C) — 40 — SPI mode (−40 °C ≤ TA ≤ 85 °C) — — 75 SPI mode (TA = 125 °C) — 42 — TPL mode (TA = 25 °C) — 80 — TPL mode (−40 °C ≤ TA ≤ 85 °C) — — 120 TPL mode (TA = 125 °C) — — 130 5 — µA 33.5 — V 7.8 — V Supply current in sleep and idle modes, communication inactive, cell balance off, oscillator monitor on, cyclic measurement off µA Except for 20 V < VPWR ≤ 30 V and within 1200 ms since entering into sleep mode from normal mode IVPWR(CKMON) Clock monitor current consumption — VPWR(OV_FLAG) VPWR overvoltage fault threshold (flag) — VPWR(LV_FLAG) VPWR low-voltage warning threshold (flag) VPWR(UV_POR) VPWR undervoltage shutdown threshold (POR), falling VPWR SPI mode TPL mode MC33772B_SDS Short data sheet: technical data — V — — All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 µA 4.9 6.25 — — © NXP B.V. 2020. All rights reserved. 11 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Parameter VPWR(UV_RIS) Min Typ Max Unit VPWR undervoltage shutdown threshold (POR), rising VPWR SPI mode TPL mode — — 5.8 6.8 — — VPWR OV, LV filter — 50 — Pre-regulator voltage range - decouple with 470 nF SPI mode, ILoad = 15 mA SPI mode, ILoad = 15 mA, 5.0 ≤ VPWR < 6.0 V TPL mode, ILoad = 70 mA — 4.9 — 5.75 — 6.5 — — — PRE undervoltage threshold leading to a reset — 4.25 — V Charge pump voltage range 2 × VPRE – 2 — 2 × VPRE V Undervoltage threshold for VCP minus VPRE — 1.5 — V — 4.15 — V tVPWR(FILTER) V µs VPRE power supply VPRE VPRE(UV_TH) V VCP power supply VCP VCP(UV_TH) VDDIO power supply VDDIO 2 IO supply for I C and SPI interfaces - voltage range VCOM power supply VCOM VCOM output voltage — 5.0 — V IVCOM VCOM output current allocated for external use — — 5.0 mA VCOM(UV) VCOM undervoltage fault threshold — 4.4 — V VCOM_HYS VCOM undervoltage hysteresis — 100 — mV tVCOM(FLT_TIMER) VCOM undervoltage fault timer — 10 — µs VCOM fault retry timer — 10 — ms VCOM overvoltage fault threshold 5.4 — 5.9 V VCOM current limit in TPL mode VCOM current limit SPI mode 65 35 — — 140 140 mA tVCOM(RETRY) VCOM(OV) ILIM(OC) RVCOM(SS) VCOM sleep mode pulldown resistor — 2.0 — kΩ VCOM rise time (CL = 2.2 µF ceramic X7R only) — — 400 µs VANA output voltage (not used by external circuits) Decouple with 47 nF X7R 0603 or 0402 — 2.65 — VANA(UV) VANA undervoltage fault threshold — 2.4 — V VANA_HYS VANA undervoltage hysteresis — 50 — mV VANA(FLT_TIMER) VANA undervoltage fault timer — 11 — µs VANA overvoltage fault threshold — 2.8 — V VANA fault retry timer — 10 — ms tVCOM VANA power supply VANA VANA(OV) tVANA(RETRY) ILIM(OC) V VANA current limit 5 — 10 mA VANA sleep mode pull-down resistor — 1.0 — kΩ VANA rise time (CL = 47 nF ceramic X7R only) — — 100 µs Cell terminal input leakage current — 10 — nA CTN Cell terminal input current during conversion — 50 — nA RPD Cell terminal open load detection pulldown resistor — 950 — Ω RVANA_RPD tVANA ADC1-A, ADC1-B CTn(LEAKAGE) MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 12 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit VVPWR_RES VPWR terminal measurement resolution — 2.44148 — VVPWR_RNG VPWR terminal measurement range SPI application TPL application 5.0 7.0 — — 36 36 VPWR terminal measurement accuracy −0.5 — 0.5 % ADC differential input voltage range for CTn to CTn-1 0.0 — 4.85 V VCT_ANx_RES Cell voltage and ANx resolution in 15-bit MEAS_xxxx registers — 152.58789 — µV/LSB VERR33RT Cell voltage measurement error VCELL = 3.3 V, TA = 25 °C — ±0.4 — VERR Cell voltage measurement error 0.1 V ≤ VCELL ≤ 4.85 V ±0.7 — VPWRTERM_ERR VCT_RNG V mV — mV VERR_1 Cell voltage measurement error 0 V ≤ VCELL ≤ 1.5 V, –40 °C ≤ TA ≤ 60 °C (or –40 °C ≤ TJ ≤ 85 °C) — ±0.4 — VERR_2 Cell voltage measurement error 1.5 V ≤ VCELL ≤ 2.7 V, –40 °C ≤ TA ≤ 60 °C (or –40 °C ≤ TJ ≤ 85 °C) — ±0.4 — VERR_3 Cell voltage measurement error 2.7 V ≤ VCELL ≤ 3.7 V, –40 °C ≤ TA ≤ 60 °C (or –40 °C ≤ TJ ≤ 85 °C) — ±0.5 — VERR_4 Cell voltage measurement error 3.7 V ≤ VCELL ≤ 4.3 V, –40 °C ≤ TA ≤ 60 °C (or –40 °C ≤ TJ ≤ 85 °C) — ±0.7 — — ±0.7 — VERR_5 Cell voltage measurement error 1.5 V ≤ VCELL ≤ 4.5 V VANx_ERR Magnitude of ANx error in the entire measurement range: Ratiometric measurement Absolute measurement, input in the range [1.0, 4.5] V Absolute measurement, input in the range [0, 4.85] V mV/LSB mV mV mV mV mV mV — — — — 16 10 — — 15 Single channel net conversion time 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 6.77 9.43 14.75 25.36 — — — — Conversion noise 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 1800 1000 600 400 — — — — VINC ISENSE+/ISENSE− input voltage (reference to AGND) −300 — 300 mV VIND ISENSE+/ISENSE− differential input voltage range −150 — 150 mV ISENSE+/ISENSE− input voltage offset error — — 0.5 µV ISENSE error including nonlinearities −0.5 — 0.5 % ISENSE open load injected current — 130 — µA tVCONV VV_NOISE µs µVrms ADC2/current sense module VISENSEX(OFFSET) IGAINERR IISENSE_OL MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 13 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit VISENSE_OL ISENSE open load detection threshold — 460 — mV V2RES µV/LSB Current sense user register resolution — 0.6 — VPGA_SAT PGA saturation half-range Gain = 256 Gain = 64 Gain = 16 Gain = 4 — — — — 4.9 19.5 78.1 150 — — — — VPGA_ITH Voltage threshold for PGA gain increase Gain = 256 Gain = 64 Gain = 16 Gain = 4 — — — — — 2.344 9.375 37.50 — — — — VPGA_DTH Voltage threshold for PGA gain decrease Gain = 256 Gain = 64 Gain = 16 Gain = 4 — — — — 4.298 17.188 68.750 — — — — — — 200 — ADC conversion time including PGA settling time 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 19.00 21.67 27.00 37.67 — — — — VI_NOISE Noise at 16-bit conversion — 3.01 — µVrms VI_NOISE Noise error at 13-bit conversion — 8.33 — µVrms ADCCLK ADC2 and ADC1-A,B clocking frequency — 6.0 — MHz Cell balance driver VDS active clamp voltage — 11 — V Output fault detection voltage threshold Balance off (open load) Balance on (shorted load) — 0.55 — — 2.0 — — — 1.0 — — 15 — — 49 tAZC_SETTLE tICONV Time to perform auto-zero procedure after enabling the current channel mV mV mV µs µs Cell balance drivers VDS(CLAMP) VOUT(FLT_TH) RPD_CB Output OFF open load detection pull-down resistor Balance off, open load detect disabled IOUT(LKG) IOUT(LKG_DIAG) Output leakage current Balance off, open load detect disabled at VDS = 4.0 V Output leakage current in diagnostic mode CB_x pins, with balance OFF, open load detect disabled, VDS = 4.0 V CB_X:X-1_C pins, with balance OFF, open load detect disabled, VDS = 4.0 V V kΩ µA µA RDS(on) Drain-to-source on resistance IOUT = 300 mA, TJ = 125 °C IOUT = 300 mA, TJ = 25 °C IOUT = 300 mA, TJ = −40 °C — — — — 0.5 0.4 0.80 — — ILIM_CB Driver current limitation (shorted resistor) 310 — 950 Cell balance driver turn on RL = 15 Ω — 350 — tON MC33772B_SDS Short data sheet: technical data Ω µs All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 mA © NXP B.V. 2020. All rights reserved. 14 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit tOFF Cell balance driver turn off RL = 15 Ω — 200 — µs tBAL_DEGLICTH Short/open detect filter time — 20 — µs Internal temperature measurement IC_TEMP1_ERR IC temperature measurement error −3.0 — 3.0 K IC_TEMP1_RES IC temperature resolution — 0.032 — K/LSB Thermal shutdown — 170 — °C Thermal shutdown hysteresis — 10 — °C TSD_TH TSD_HYS Default operational parameters VCTOV(TH) Cell overvoltage threshold (8 bits) 0.0 4.2 5.0 V VCTOV(RES) Cell overvoltage threshold resolution — 19.53125 — mV/LSB VCTUV(TH) Cell undervoltage threshold (8 bits) 0.0 2.5 5.0 V VCTUV(RES) Cell undervoltage threshold resolution — 19.53125 — mV/LSB VGPIO_OT(TH) GPIOx configured as ANx input overtemperature threshold from POR — 1.16 — V VGPIO_OT(RES) Overtemperature voltage threshold resolution — 4.8828125 — mV/LSB VGPIO_UT(TH) GPIOx configured as ANx input undertemperature threshold from POR — 3.82 — V VGPIO_UT(RES) Undertemperature voltage threshold resolution — 4.8828125 — mV/LSB General purpose input/output GPIOx VIH Input high-voltage (3.3 V compatible) 2.0 — — V VIL Input low-voltage (3.3 V compatible) — — 1.0 V Input hysteresis — 100 — mV −100 — 100 VHYS IIL Input leakage current Pins tri-state, VIN = VCOM or AGND nA IIDL Differential input leakage current GPIO 5,6 GPIO 5,6 configured as digital inputs for current measurement −30 — 30 VOH Output high-voltage IOH = −0.5 mA VCOM − 0.8 — — V VOL Output low-voltage IOL = +0.5 mA — — 0.8 V VADC Analog ADC input voltage range for ratiometric measurements AGND — VCOM V Analog input open pin detect threshold — 0.15 — V ROPENPD Internal open detection pull-down resistor 3.8 5.0 — kΩ tGPIO0_WU GPIO0 WU de-glitch filter — 50 — µs tGPIO0_FLT GPIO0 daisy chain de-glitch filter both edges — 20 — µs tGPIO2_SOC GPIO2 convert trigger de-glitch filter — 2.0 — µs tGPIOx_DIN GPIOx configured as digital input de-glitch filter 2.5 — 5.6 µs VIH_RST Input high-voltage (3.3 V compatible) 2.0 — — V VIL_RST Input low-voltage (3.3 V compatible) — — 1.0 V Input hysteresis — 0.6 — V RESET de-glitch filter — 100 — µs VOL(TH) nA Reset input VHYS tRESETFLT MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 15 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Parameter RRESET_PD Min Typ Max Unit Input logic pull down (RESET) — 100 — kΩ VIH Input high-voltage (3.3 V compatible) 2.0 — — V VIL Input low-voltage (3.3 V compatible) — — 1.0 V Input hysteresis — 450 — mV Bus termination resistor (open resistor when bus switch is closed) — 150 — Ω SPI_COM_EN input VHYS Bus switch for TPL communication RXTERM Remark: If the bus switch is closed, then the termination resistor is open, else the termination resistor is connected. At the end of the daisy chain, the switch must be open, so that the transmission line is properly terminated. Digital interface VFAULT_HA FAULT output (high active, IOH = 1.0 mA) FAULT output (High Active, IOH = 1.0 mA), SPI mode, 5.0 ≤ VPWR < 6.0 V 3.9 2.9 4.9 — 6.0 6.0 V IFAULT_CL FAULT output current limit 3.0 — 25 mA FAULT output pulldown resistance — 100 — kΩ — — 2.0 RFAULT_PD VIH_COMM Voltage threshold to detect the input as high SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL (NOTE: needs to be 3.3 V compatible) V VIL_COMM Voltage threshold to detect the input as low SI/RDTX_IN+, SCLK/RDTX_IN–, CSB, SDA, SCL 0.8 — — V VHYS Input hysteresis SI/RDTX_IN+, SCLK/RDTX_IN−, CSB, SDA, SCL — 100 — −100 — 100 mV ILOGIC_SS Sleep state input logic current CSB RSCLK_PD Input logic pulldown resistance (SCLK/RDTX_IN–, SI/RDTX+) — 20 — kΩ RI_PU Input logic pullup resistance to VCOM (CSB, SDA, SCL) — 100 — kΩ ISO_TRI Tri-state SO input current 0 V to VCOM −2.0 — 2.0 µA VSO_HIGH SO high-state output voltage with ISO(HIGH) = −2.0 mA VDDIO − 0.4 — — V VSO_LOW SO, SDA, SLK low-state output voltage with ISO(HIGH) = −2.0 mA — — 0.4 V CSB wake-up de-glitch filter, low to high transition — 50 — µs CSBWU_FLT nA System timing tCELL_CONV tSYNC Time needed to acquire all 6 cell voltages and the current after an on demand conversion 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 13 bit ADC1-A,B at 14 bit, ADC2 at 13 bit ADC1-A,B at 15 bit, ADC2 at 13 bit ADC1-A,B at 16 bit, ADC2 at 13 bit MC33772B_SDS Short data sheet: technical data µs — — — — 41 57 89 152 — — — — — — — — 41.39 42.71 47.37 95.14 — — — — µs All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 16 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Parameter Min Typ Max Unit tSYNC V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 14 bit ADC1-A,B at 14 bit, ADC2 at 14 bit ADC1-A,B at 15 bit, ADC2 at 14 bit ADC1-A,B at 16 bit, ADC2 at 14 bit — — — — 46.73 48.05 50.71 92.47 — — — — tSYNC V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 15 bit ADC1-A,B at 14 bit, ADC2 at 15 bit ADC1-A,B at 15 bit, ADC2 at 15 bit ADC1-A,B at 16 bit, ADC2 at 15 bit — — — — 57.39 58.71 61.37 87.14 — — — — tSYNC V/I synchronization time ADC1-A,B at 13 bit, ADC2 at 16 bit ADC1-A,B at 14 bit, ADC2 at 16 bit ADC1-A,B at 15 bit, ADC2 at 16 bit ADC1-A,B at 16 bit, ADC2 at 16 bit — — — — 78.73 80.05 82.71 88.02 — — — — — — 5.0 Sleep mode to normal mode device ready Wake-up from fault Wake-up from GPIO Wake-up from network Wake-up from CSB — — — — — — — — 400 400 400 400 Sleep mode to normal mode time after TPL bus wake-up — — 1.0 ms Time between wake pulses — 600 — µs tVPWR(READY) tWAKE-UP Time after VPWR connection for the IC to be ready for initialization tWAKE_DELAY tIDLE µs µs µs ms µs Idle timeout after POR — 60 — s tWAKE_INIT Wake-up signaling timeout after POR — 0.65 — s tBALANCE Cell balance timer range 0.5 — 511 min tCYCLE Cyclic acquisition timer range 0.0 — 8.5 s tFAULT Fault detection to activation of fault pin Normal mode — — 56 SOC to data ready (includes post processing of data) 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution — — — — 148 201 307 520 — — — — tSETTLE Time after SOC to begin converting with ADC1-A,B — 12.28 — tCLST_TPL Time needed to send an SOC command and read back 6 cell voltages, 7 temperatures, 1 current, and 1 coulomb counter with TPL communication working at 2.0 Mbps and ADC1-A,B configured as follows: 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution tEOC MC33772B_SDS Short data sheet: technical data µs µs ms — — — — All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 µs 0.79 0.85 0.95 1.16 — — — — © NXP B.V. 2020. All rights reserved. 17 / 27 MC33772B NXP Semiconductors Battery cell controller IC Symbol Parameter tCLST_SPI Min Time needed to send an SOC command and read back 6 cell voltages, 7 temperatures, 1 current, and 1 coulomb counter with SPI communication working at 4.0 Mbps and ADC1-A,B configured as follows: 13-bit resolution 14-bit resolution 15-bit resolution 16-bit resolution tI2C_DOWNLOAD tI2C_ACCESS Typ Max Unit ms — — — — 0.48 0.54 0.64 0.86 — — — — Time to download EEPROM calibration after POR — — 1.0 ms EEPROM access time, EEPROM write (depends on device selection) — 5.0 — ms tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 00 — 500 — µs tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 01 — 1.0 — tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 10 — 10 — tWAVE_DC_BITx Daisy chain duty cycle off time tWAVE_DC_BITx = 11 — 100 — tWAVE_DC_ON Daisy chain duty cycle on time — 500 550 µs tCOM_LOSS Time out to reset the IC in the absence of communication — 1024 — ms ms ms ms SPI interface FSCK CLK/RDTX_IN– frequency — — 4.0 MHz SCLK/RDTX_IN– high time (A) [1] 125 — — ns SCLK/RDTX_IN– high time (B) [1] 125 — — ns tSCK SCLK/RDTX_IN− period (A+B) [1] 250 — — ns tFALL SCLK/RDTX_IN− falling time — — 15 ns tRISE SCLK/RDTX_IN− rising time — — 15 ns SCLK/RDTX_IN− setup time (O) [1] 20 — — ns SCLK/RDTX_IN– hold time (P) [1] 20 — — ns SI/RDTX_IN+ setup time (F) [1] 40 — — ns tSI_HOLD SI/RDTX_IN+ hold time (G) [1] 40 — — ns tSO_VALID SO data valid, rising edge of SCLK/ RDTX_IN− to SO data valid (I) [1] — — 40 ns tSO_EN SO enable time (H) [1] — — 40 ns tSO_DISABLE SO disable time (K) [1] — — 40 ns CSB lead time (L) [1] 100 — — ns CSB lag time (M) [1] 100 — — ns Sequential data transfer delay (N) [1] 1.0 — — µs tSCK _H tSCK _L tSET tHOLD tSI_SETUP tCSB_LEAD tCSB_LAG tTD TPL interface [1] [2] [2] See Figure 4 Detailed application information about how to build a TPL daisy chain can be found in the AN12605 application note dedicated to communication. MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 18 / 27 MC33772B NXP Semiconductors Battery cell controller IC 7.5 Timing diagrams CSB N Don't care level O L A M B P Don't care level SCLK H SO Tri-state K I MSB F SI Tri-state LSB G MSB LSB aaa-027848 Figure 4. Low-voltage SPI interface timing 3.75 V Start of message Bit 39 Logic 1 Bit 38 Logic 1 Bit 37 Logic 0 Bit 36 Logic 0 Bit 2 Logic 1 Bit 1 Logic 0 Bit 0 End of Logic 0 message RDTX_IN+ 2.5 V RDTX_IN1.25 V two pulse positive sine two pulse negative sine aaa-027849 Figure 5. Transformer communication signaling 8 Packaging 8.1 Package mechanical dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Table 8. Package Outline Package 48-pin LQFP-EP MC33772B_SDS Short data sheet: technical data Suffix Package outline drawing number AE All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 SOT1571-1 © NXP B.V. 2020. All rights reserved. 19 / 27 MC33772B NXP Semiconductors Battery cell controller IC MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 20 / 27 MC33772B NXP Semiconductors Battery cell controller IC MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 21 / 27 MC33772B NXP Semiconductors Battery cell controller IC Figure 6. Package outline MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 22 / 27 MC33772B NXP Semiconductors Battery cell controller IC 9 Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes MC33772B_SDS v.6.0 20200402 Technical data 202003032I MC33772B_SDS v.5.0 Modifications • Revision updated to match full data sheet MC33772B_SDS v.5.0 20181108 Technical data 201806036I MC33772B_SDS v.4.0 MC33772B_SDS v.4.0 20180731 Technical data — MC33772B_SDS v.3.0 MC33772B_SDS v.3.0 20180608 Technical data — — MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 23 / 27 MC33772B NXP Semiconductors Battery cell controller IC 10 Legal information 10.1 Data sheet status Document status [1][2] Product status [3] Definition [short] Data sheet: product preview Development This document contains certain information on a product under development. NXP reserves the right to change or discontinue this product without notice. [short] Data sheet: advance information Qualification This document contains information on a new product. Specifications and information herein are subject to change without notice. [short] Data sheet: technical data Production This document contains the product specification. NXP Semiconductors reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 10.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. MC33772B_SDS Short data sheet: technical data Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 24 / 27 MC33772B NXP Semiconductors Battery cell controller IC malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 10.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. SMARTMOS — is a trademark of NXP B.V. MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 25 / 27 MC33772B NXP Semiconductors Battery cell controller IC Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Part number breakdown ....................................4 Orderable part variations ...................................5 Pin definitions ....................................................6 Ratings vs. operating requirements ...................8 Maximum ratings ...............................................8 Tab. 6. Tab. 7. Tab. 8. Tab. 9. Thermal ratings ................................................. 9 Static and dynamic electrical characteristics ... 11 Package Outline .............................................. 19 Revision history ...............................................23 Fig. 4. Fig. 5. Fig. 6. Low-voltage SPI interface timing .....................19 Transformer communication signaling .............19 Package outline ...............................................20 Figures Fig. 1. Fig. 2. Fig. 3. Simplified application diagram, SPI use case .... 2 Simplified application diagram, TPL use case ................................................................... 3 Pinout diagram .................................................. 6 MC33772B_SDS Short data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 6.0 — 2 April 2020 © NXP B.V. 2020. All rights reserved. 26 / 27 MC33772B NXP Semiconductors Battery cell controller IC Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 8 8.1 9 10 General description ............................................ 1 Features ............................................................... 1 Simplified application diagram .......................... 2 Applications .........................................................4 Ordering information .......................................... 4 Part numbers definition ......................................4 Part numbers list ............................................... 5 Pinning information ............................................ 6 Pinout diagram .................................................. 6 Pin definitions .................................................... 6 General product characteristics ........................ 8 Ratings and operating requirements relationship .........................................................8 Maximum ratings ............................................... 8 Thermal characteristics ......................................9 Electrical characteristics .................................. 11 Timing diagrams .............................................. 19 Packaging .......................................................... 19 Package mechanical dimensions .................... 19 Revision history ................................................ 23 Legal information .............................................. 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2020. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 April 2020 Document identifier: MC33772B_SDS