NXP Semiconductors
Data sheet: Technical Data
Document Number: MC33814
Rev. 9.0, 10/2016
Two cylinder small engine control IC
33814
Powered by SMARTMOS technology, the 33814 delivers a cost-optimized IC
solution for managing one and two-cylinder engines. With six drivers, three predrivers, a 5.0 V regulator for the MCU, a protected external sensor supply, and a
high level of integration, the IC offers an ideal response to contemporary market
requirements. The innovative VRS system optimizes noise immunity under
cranking conditions. Diagnostic and protection features present on all outputs allow
applications to operate with greater safety.
TWO CYLINDER SMALL ENGINE
CONTROL IC
Features:
• Operates over supply voltage range of 4.5 V < VPWR < 36 V
• Start-up/shut-down control and power sequence logic with KEYSW input
• MCU supply: VCC is a 5.0 V (±2.0%, 200 mA) regulated supply
• Sensor supply: VPROT (100 mA) is a VCC tracking protected sensor supply
• Three configurable pre-drivers for IGBT or general purpose gate MOSFETs for
ignition and O2 sensor (HEGO) heater:
• PWM
• Overcurrent shutdown
• Short-to-battery shutdown
• Six low-side drivers with full diagnostics, self-protection and PWM control:
• Two fuel injector drivers, RDS(on) = 0.6 Ω, ILIMIT = 1.8 A, to drive typical 12 Ω
high-impedance injectors
• Relay 1 driver, RDS(on) = 0.4 Ω, ILIMIT = 3.0 A, to drive fuel pump
• Relay 2 driver, RDS(on) = 1.5 Ω, ILIMIT = 1.2 A, to drive power relay
• Lamp driver, RDS(on) = 1.5 Ω, ILIMIT = 1.2 A, to drive warning lamp or an LED
• Programmable Tachometer Driver, RDS(on) = 20 Ω, Ishutdown = 60 mA, to drive
a Tachometer display
• Innovative configurable VRS conditioning circuit, with two different parameter
settings for engine cranking and running mode and an optional automatic mode
to improve noise immunity in cranking conditions
• K-line (ISO9141)
• MCU reset generator and programmable watchdog
• MCU Interface: 16-bit SPI and parallel interface with 5.0 V IO capability
98ASA00737D
AE SUFFIX (PB-FREE)
48-PIN LQFP-EP
Applications:
Small Engine Control for:
• Motor scooters
• Small motorcycles
• Lawn mowers
• Lawn trimmers
• Snow blowers
• Chain saws
• Gasoline-driven electrical generators
• Outboard motors
.
MC33814
VBAT
Keyswitch
VBAT
MCU
VCC
KEYSW VPROT ROUT2
VPWR
LAMPOUT
VPPREF
ROUT1
TACHOUT
VPPSENS
O2HFB
O2HOUT
VCC
O2HSENSP
RESETB
O2HSENSN
+5.0 V
RESETB
SPI
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Crankshaft VRS
4
SPI
MRX
MTX
BATSW
RIN1
RIN2
IGNIN1
IGNIN2
INJIN1
INJIN2
VRSOUT
O2HIN
VRSP
VRSN
GND
VBAT
Relay 2
(Power)
MIL
Relay 1
(Fuel Pump)
TACHOMETER
O2 Heater
VBAT
INJOUT1
Injectors
VBAT
INJOUT2
ISO9141
ISO9141
IGNFB1
IGNOUT1
IGNFB2
IGNOUT2
IGNSENSP
IGNSENSN
Figure 1. 33814 simplified application diagram
© 2016 NXP B.V.
5.0 V Sensor Supply
VBAT
Table of Contents
1
2
3
4
5
6
7
8
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General IC functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5 Drivers blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.6 Pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.7 VRS circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.8 ISO9141 bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.9 Mode code and revision number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.10 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.11 SPI registers mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.1 Output OFF open load fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.2 Low voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3 Low-side injector driver voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.4 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
33814
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NXP Semiconductors
1
Orderable parts
Table 1. Orderable part variations
Part Number (1)
Temperature (TA)
Package
MC33814AE
-40 °C to 125 °C
48 LQFP-EP
Notes
1. To order parts in Tape and Reel, add the R2 suffix to the part number.
33814
NXP Semiconductors
3
2
Internal block diagram
VPWR
POR,
Overvoltage
Undervoltage
Pre-
VPPREF
Regulator
VPPSENS
VCC
RESETB
VPP
+5.0 V
Tracking
Regulator
VCC
LOGIC CONTROL
CSB
SI
SCLK
SO
VPROT
VCC
+5.0 V
Regulator
Watchdog
SPI INTERFACE
and REGISTERS
Typical of all 6 Driver Outputs
INJOUT1
O2HIN
INJOUT2
INJIN1
Gate Control
INJIN2
Current Limit
Temperature Limit
Short/Open
(1 of 6 shown)
VClamp
75 µA
IGNIN1
ROUT2
lLimit
+
–
LAMPOUT
RS
TACHOUT
INJGND1
INJGND2
SPI Control
PARALLEL
CONTROL
Parallel Control
IGNIN2
ROUT1
RGND1
VPWR
RGND2
VAnalog
RIN1
V10.0 Analog
V2.5 Logic
VLogic
RIN2
MRX
VCC
ISO9141
ISO9141
CONTROLLER
MTX
KEYSW
Bandgap
SLEEP/RUN
START LOGIC
BATSW
Bias
Pre-drivers
To ROUT2
Driver
Ignition 1
Ignition 2
Oscillator
To Logic
Control
lLimit
+
–
O2 Heater
Divider
VRSP
VRSN
(SPI CONTROL)
To Logic
Control
Divide by “N”
–
+
VCC
+
–
IGNOUT1
IGNFB2
IGNOUT2
IGNSENSP
IGNSENSN
O2HFB
O2HOUT
O2HSENSP
O2HSENSN
(SPI)
N=1-32
VRS CIRCUIT
lLimit
IGNFB1
To TACHOUT Driver
VRSOUT
Note: All current sinks and sources ~50µA except where indicated
GND
Figure 2. Simplified internal block diagram
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NXP Semiconductors
Pin connections
3.1
Pinout diagram
37
38
39
40
41
42
43
44
45
46
1
36
2
35
3
34
4
33
32
5
6
31
EP
7
30
24
23
22
21
20
19
18
25
17
26
12
16
27
11
15
28
10
14
29
9
13
8
RIN1
RIN2
O2HIN
IGNIN1
IGNIN2
INJIN1
INJIN2
BATSW
MTX
MRX
TACHOUT
NC
SI
VPPREF
GND
SO
VCC
VPPSENS
RESETB
VPROT
LAMPOUT
RGND2
ROUT2
NC
O2HFB
O2HOUT
IGNSENSP
IGNSENSN
O2HSENSN
O2HSENSP
VRSOUT
VRSP
VRSN
CSB
VPWR
SCLK
47
Transparent Top View
48
IGNOUT2
IGNFB2
IGNOUT1
IGNFB1
ISO9141
INJOUT1
INJGND1
ROUT1
RGND1
INJOUT2
INJGND2
KEYSW
3
Figure 3. 33814 Pin connections
3.2
Pin definitions
Table 2. 33814 pin definitions
Pin
Pin Name
Pin
Function
Formal Name
Description
1
O2HFB
Input
O2 Sensor Heater
Feedback Input
Voltage feedback from drain of O2 Sensor Heater driver FET. If used as IGBT driver,
voltage feedback from collector of IGBT through 10:1 voltage divider (9R:1R).
2
O2HOUT
Output
O2 Sensor Heater
Output
Pre-driver output for O2 Sensor Heater driven by SPI input or O2HIN pin
3
IGNSENSP
Input
Positive input to the ignition current sense differential amplifier.
Ignition Current
Sense Input Positive Measures current in IGBT emitter resistor (or MOSFET source resistor) for IGNOUT1
and IGNOUT2, if used
4
IGNSENSN
Input
Negative input to the ignition current sense differential amplifier.
Ignition Current
Sense Input Negative Measures current in IGBT emitter resistor (or MOSFET source resistor) for IGNOUT1
and IGNOUT2, if used
5
O2HSENSN
Input
Negative input to the O2 heater current sense differential amplifier.
O2 Heater Current
Sense Input Negative Measures current in of O2 heater driver MOSFET source resistor (or IGBT emitter
resistor), if used
6
O2HSENSP
Input
Positive input to the O2 heater current sense differential amplifier.
O2 Heater Current
Sense Input Positive Measures current in of O2 heater driver MOSFET source resistor (or MOSFET source
resistor) for IGNOUT1 and IGNOUT2, if used
7
VRSOUT
Output
VRS Conditioned
Output
5.0 V Logic Level Output from conditioned VRS differential inputs VRSP, VRSN
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NXP Semiconductors
5
Table 2. 33814 pin definitions
Pin
Pin Name
Pin
Function
8
VRSP
Input
Variable Reluctance The VRSP and VRSN form a differential input for the Variable Reluctance Sensor
Sensor Positive Input attached to the crankshaft toothed wheel.
9
VRSN
Input
Variable Reluctance
The VRSP and VRSN form a differential input for the Variable Reluctance Sensor
Sensor Negative
attached to the crankshaft toothed wheel.
Input
10
CSB
Input
11
VPWR
Supply Input
12
SCLK
Input
SPI Clock Input
The SCLK input pin is used to clock in and out the serial data on the SI and SO pins
while being addressed by the CSB.
13
SI
Input
SPI Data Input
The SI input pin is used to receive serial data into the device from the MCU.
14
VPPREF
Output
15
GND
Ground
Ground
16
SO
Output
SPI Data Output
The SO output pin is used to transmit serial data from the device to the MCU.
17
VCC
Supply
VCC Supply
Protected Output
5.0 Volt supply output for MCU VCC. This output supplies the VCC voltage for 5.0 Volt
MCUs. It is short-circuit and overcurrent protected.
18
VPPSENS
Input
Voltage Sense from
VPP
Feedback to internal VPP 6.5 Volt regulator from external pass transistor
19
RESETB
Output
RESETB Output to
MCU
5.0 V Logic level reset signal used to reset the MCU during under and overvoltage
conditions and for initial power-up, down and watchdog timeouts
20
VPROT
Output
Sensor Supply
Protected Output
21
LAMPOUT
Output
22
RGND2
Ground
23
ROUT2
Output
24, 25
N.C.
No Connect
Unused pin
26
TACHOUT
Output
Tachometer output
27
MRX
Output
Low-side Driver
Output
28
MTX
Input
29
BATSW
Output
Battery Switch
This output is a 5.0 V logic level that is high when KEYSW is high. It is only low when
KEYSW is low. It can also be controlled via the SPI.
30
INJIN2
Input
Injector Driver Input 2
5.0 V logic level input from the MCU to control the injector 2 driver output. (Can also be
controlled via the SPI)
31
INJIN1
Input
Injector Driver Input 1
5.0 V logic level input from the MCU to control the injector 1 driver output. (Can also be
controlled via the SPI)
32
IGNIN2
Input
Ignition Input 2
5.0 V logic level input from MCU controlling the ignition coil # 2 current flow and spark.
(Can also be controlled via the SPI)
33
IGNIN1
Input
Ignition Input 1
5.0 V logic level input from MCU controlling the ignition coil # 1 current flow and spark.
(Can also be controlled via the SPI)
34
O2HIN
Input
O2 Sensor Heater
Input
5.0 V logic level input used to turn on and off the O2HOUT driver. The O2HOUT driver
can also be turned on and off via the SPI if this pin is not present in a different package.
35
RIN2
Input
Relay Driver Input 2
Formal Name
SPI Chip Select
Description
The Chip Select input pin is an active low signal sent by the MCU to indicate that the
device is being addressed.
Main Voltage Supply VPWR is the main voltage supply input for the device. Should be connected to a 12 Volt
Input
battery with reverse battery protection and adequate transient protection.
VPP Reference Base
Base drive for external PNP pass transistor
Drive
Ground pin, return for all voltage supplies
The VPROT Output is a protected 5.0 Volt output that tracks the VCC voltage but
isolates the VCC output against shorts to ground and to battery. It is intended to supply
sensors which are located off of the ECU board.
Warning Lamp Output Low-side driver output for MIL (warning lamp) driven by SPI input command
ROUT2 Power
Ground
Ground connection for ROUT 2 low-side driver. Must be tied to VPWR Ground.
Relay Driver 2 Output Low-side relay driver output # 2 driven by SPI input command or RIN2 logic input
This pin provides the low-side drive for a tachometer gauge or alternatively as a SPI
controlled low-side driver, or oscillator output.
Output 5.0 V logic level ISO9141 data to the MCU from the ISO9141 IN/OUT pin
ISO9141 MCU Data
Input 5.0 V logic level ISO9141 data from the MCU to the ISO9141 IN/OUT pin
Input
5.0 V logic level input from the MCU to control the relay 2 driver output ROUT2. The
ROUT2 driver can also be turned on and off via the SPI if this pin is not present in a
different package.
33814
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NXP Semiconductors
Table 2. 33814 pin definitions
Pin
Pin Name
Pin
Function
Formal Name
36
RIN1
Input
Relay Driver Input 1
Description
5.0 V logic level input from the MCU to control the relay 1 driver output ROUT1. The
ROUT1 driver can also be turned on and off via the SPI if this pin is not present in a
different package.
37
KEYSW
Input
Key Switch Input
The Key Switch Input is a VPWR level signal that indicates that the Key is inserted and
turned to the ON/OFF position. In the ON position the (KEYSW = VBAT) the IC is
enabled and BATSW = HIGH (Relay 2 ON if programmed in the SPI). In the OFF
position the IC is in Sleep mode, only when the PWREN bit in the SPI register is also
low.
38
INJGND2
Ground
Injector Driver 2
Ground
Ground connection for injector 2 low-side driver. Must be tied to VPWR ground
39
INJOUT2
Output
Injector Driver 2
Output
Low-side driver output for injector 2 driven by the SPI input or by parallel input INJIN2
40
RGND1
Ground
ROUT1 Power
Ground
Ground connection for ROUT 1 low-side driver. Must be tied to VPWR ground
41
ROUT1
Output
42
INJGND1
Ground
Injector Driver 1
Ground
Ground connection for injector 1 low-side driver. Must be tied to VPWR ground
43
INJOUT1
Output
Injector Driver 1
Output
Low-side driver output for injector 1 driven by the SPI input or by parallel input INJIN1
44
ISO9141
Input/Output
ISO9141 K-Line
Bidirectional Serial
Data Signal
ISO9141 pin is VPWR level IN/OUT signal which is connected to an external ECU tester
that uses the ISO9141 protocol.The output is open drain with an internal 32 kΩ pull-up
resistor and the Input is a ratiometric VPWR level threshold comparator.
45
IGNFB1
Input
Feedback from
Collector 1
Voltage feedback from collector of ignition # 1 driver IGBT through 10:1 voltage divider
(9R:1R)(or voltage feedback from the drain of the FET connected to IGNOUT1, if
selected)
46
IGNOUT1
Output
Ignition Output 1
Relay Driver 1 Output Low-side relay driver output # 1 driven by the SPI input command or RIN1 logic input
47
IGNFB2
Input
Feedback from
Collector 2
48
IGNOUT2
Output
Ignition Output 2
Output to gate of IGBT or GPGD for ignition # 1
Voltage feedback from collector of ignition # 2 driver IGBT through 10:1 voltage divider
(9R:1R)(or voltage feedback from the drain of the IGNOUT2 FET, if selected)
Output to gate of IGBT or GPGD for ignition # 2
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4
General product characteristics
4.1
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or permanent device
damage.
Symbol
Parameter
Min.
Max.
Unit
VPWR Supply Voltage
-0.3
45
VDC
VPP Supply Voltage (If supplied externally and not using internal VPP regulator)
• VPPREF
• VPPSENSE
-0.3
-0.3
45
10
VDC
VCC Regulator
-0.3
7.0
VDC
VPROT
VPROT Regulator
-0.3
VPWR
VDC
VIL, VIH
SPI Interface and Logic Input Voltage (VSI, VSCLK, VCSB, VRIN1, VRIN2, VINJIN1,
VINJIN2, VIGNIN1, VIGNIN2, VO2HIN, VMTX)
-0.3
VCC
VDC
VIL, VIH
SPI Interface and Logic Output Voltage (VSO, VBATSW, VMRX,VVRSOUT)
-0.3
VCC
VDC
VOUTX
All Low-side Drivers Drain Voltage (VINJOUT1, VINJOUT2, VROUT1, VROUT2,
VLAMPOUT, VTACHOUT)
-0.3
VCLAMP
VDC
VGDX
All Pre-drivers Output Voltage (VIGNOUT1, VIGNOUT2, VO2HOUT)
-0.3
10
VDC
VGDFB
All Pre-driver Feedback Inputs Voltage (VIGNFB1, VIGNFB2, VO2HFB)
-1.5
60
VDC
VISENS
All Pre-driver Current Sense Inputs Voltage
(VIGNSENSN, VIGNSENSP, VO2HSENSN,VO2HSENSP)
-0.3
1.0
VDC
VKEYSW
KEYSW Input Voltage (VKEYSW)
-18
VPWR
VDC
VRESETB
RESETB Output Voltage (VRESETB)
-0.3
VCC
VDC
VISO9141
ISO9141 Input/Output Voltage (VISO9141)
-18
VPWR
VDC
Notes
ELECTRICAL RATINGS
VPWR
VPP_Ext
VCC
VVRS_IN
Maximum Voltage for VRSN and VRSP inputs to ground
-0.5
6.0
VDC
IVRSX_IN
Maximum Current for VRSN and VRSP inputs (internal diodes limit voltage)
-
15
mA
ECLAMP
Output Clamp Energy (INJOUT1, INJOUT2, ROUT1, ROUT2)
• TJUNCTION = 150 °C, IOUT = 1.0 A
-
100
mJ
Output Clamp Energy (LAMPOUT)
• TJUNCTION = 150 °C, IOUT = 0.5 A
-
35
mJ
-
±2000
±750
±500
ECLAMP_LAMP
VESD1
VESD2
VESD3
ESD Voltage
• Human Body Model (HBM)
• Charge Device Model (CDM) (corner pins)
• Charge Device Model (CDM)
V
(2)
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model.
33814
8
NXP Semiconductors
Table 3. Maximum ratings
All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or permanent device
damage.
Symbol
Parameter
Min.
Max.
Unit
Operating Temperature (Automotive grade version)
• Ambient
• Junction
• Case
-40
-40
-40
125
150
125
°C
TSTG
Storage Temperature
-55
150
°C
TPPRT
Peak Package Reflow Temperature During Reflow
-
Note 4
°C
29
2.4
29
2.4
°C/W
Notes
THERMAL RATINGS
TA
TJ
TC
(3) (4)
,
Thermal Resistance and Package Dissipation Ratings
RθJA
RθJC
Thermal Resistance
• Junction-to-Ambient (LQFP-48-EP Package) (Single Layer Board)
• Junction-to-Case (LQFP-48-EP Package)
Notes
3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
4. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes), enter the core ID to view all orderable
parts and review parametrics.
33814
NXP Semiconductors
9
4.2
Static electrical characteristics
Table 4. Power input static electrical characteristics
Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
2.5
4.5
6.0
-
45
36
18
Unit
Notes
V
(5)
POWER INPUT (VPWR)
VPWR (LS)
VPWR (FO)
VPWR (FP)
Supply Voltage (measured at VPWR pin)
• Logic Stable Range
• Full Operational Range
• Full Parameter Specification Range
IVPWR (ON)
Supply Current
• All Outputs Disabled (Normal Mode), excludes base current to the
external pnp
-
10.0
14.0
mA
IVPWR (SS)
Sleep State Supply Current (Must have PWREN = 0 and KEYSW ≤
0.8 V for sleep state),
• VPWR = 18 V
-
10
20
μA
VPWR(OV)
VPWR Overvoltage Shutdown Threshold Voltage (OV Reset)
37.5
39
42
V
VPWR Overvoltage Shutdown Hysteresis Voltage
0.5
1.5
3.0
V
VCC Power On Reset Voltage Threshold (POR), (rising voltage)
3.9
-
4.9
V
VCC Undervoltage Shutdown Threshold Voltage (UV Reset), (falling
voltage)
2.9
-
3.9
V
VCC(UV/POR-HYS)
VCC POR and Undervoltage Shutdown Hysteresis Voltage
100
-
-
mV
VCC,NONOVERLAP
VCC POR and Undervoltage Non-overlap (POR-UV)
0.8
1.0
1.2
V
VPPSENS Output Voltage
5.85
6.5
7.15
V
VPPREF Current Limit
-5.0
-15
-20
mA
Output Capacitance External (ceramic)
2.2
-
25
μF
VPPSENS Quiescent Current (excluding external PNP current)
-
-
3
mA
REGLINE_VPP
Line Regulation IVCC = 100 mA, IVPROT = 50 mA, 9.0 V < VPWR < 18 V
and Diodes Inc. FZT753TA PNP
-
2.0
25
mV
VDROPOUT_VPP
Dropout Voltage (Minimal Input/Output Voltage, tracks input below)
IVCC = 100 mA, IVPROT = 50 mA and Diodes Inc. FZT753TA PNP
-
-
500
mV
4.9
5.0
5.1
V
VCC Output Current Continuous
-
-
200
mA
VPROT Output Voltage (tracks VCC)
IVCC = 100 mA, IVPROT = 50 mA 9.0 V < VPWR < 18 V
-
-
25
mV
VPROT Output Current Continuous
-
-
100
mA
VCC Output Current Limiting
200
-
500
mA
VPROT Output Current Limiting
110
-
260
mA
Output Capacitance External (VCC and VPROT) without reverse
protection diode
2.2
-
47
μF
VPWR(OV-HYS)
VCC(POR)
VCC(UV)
(6)
(7)
VOLTAGE PRE-REGULATOR OUTPUT (VPPREF, VPPSENS)
VPPSENS
IVPPREF_CL
VOCE
IVPPSENS
VOLTAGE REGULATOR OUTPUTS (VCC, VPROT)
VCC
IVCC_C
IVCC-VPROT|
IVPROT_C
IVCC_CL
IVPROT_CL
VOCE
Notes
5.
6.
7.
8.
VCC Output Voltage 0 ≤ IVCC ≤ IVCC_C
(8)
This parameter is guaranteed by design but is not production tested.
Overvoltage thresholds minimum and maximum include hysteresis.
Undervoltage thresholds minimum and maximum include hysteresis
Guaranteed at 9.0 V ≤ VPWR ≤ 18 V
33814
10
NXP Semiconductors
Table 4. Power input static electrical characteristics
Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
4.9
5.0
5.1
V
Notes
VOLTAGE REGULATOR OUTPUTS (VCC, VPROT) (CONTINUED)
VCC
VCC Output Voltage 0 ≤ IVCC ≤ IVCC_C
REGLINE_VB
Line Regulation (Both VCC and VPROT)
IVCC =100 mA, IPROT = 50 mA, 9.0 V< VPWR < 18 V
-
2.0
25
mV
REGLOAD_VB
Load Regulation (Both VCC and VPROT) measured from 10% - 90% of
IVCC_C and IPROT_C, VPWR = 13 V
-
20
35
mV
Dropout Voltage (Both VCC and VPROT) (Minimal Input/Output Voltage
IVCC = 100 mA, IVPROT = 50 mA, tracks input below)
-
-
500
mV
Output Fault Detection Voltage Threshold, Outputs programmed OFF
(Open Load), Outputs programmed ON (Short to Battery)
2.0
2.5
3.0
V
I(OFF)OCO
Output OFF Open Load Detection Current (INJ1, INJ2, RELAY1,
RELAY2 AND LAMP)
• VDRAIN = 18 V, Outputs Programmed OFF
40
75
115
μA
I(OFF)TACH
Output OFF Open Load Detection Current TachOut
10
-
30
μA
IOUT (LKG)
Output Leakage Current
• VDRAIN = 24 V, Open Load Detection Disabled and Output
commanded OFF
-
-
20
μA
Overtemperature Shutdown (OT)
155
-
185
°C
(9)
Overtemperature Shutdown Hysteresis
5.0
10
15
°C
(9)
Output Clamp Voltage
• ID = 20 mA
48
53
60
-
-
0.6
Ω
1.8
-
3.0
A
-
-
0.4
Ω
3.0
-
6.0
A
-
-
1.5
Ω
1.2
-
2.4
A
-
-
1.5
Ω
1.2
-
2.4
A
VDROPOUT_VCC/
VPROT
ALL LOW-SIDE DRIVERS (INJOUT1, INJOUT2, ROUT1, ROUT2, LAMPOUT, TACHOUT)
VOUT (FLT-TH)
TLIM
TLIM (HYS)
VOC
(9)
V
INJOUT1, INJOUT2
RDS (ON)_INJx
Drain-to-Source ON Resistance
• IOUT = 1.0 A TJ = 150 °C, VPWR = 13 V
IOUT (LIM)_INJx
Output Self Limiting Current
ROUT1
RDS (ON)_R1
Driver Drain-to-Source ON Resistance
• IOUT = 700 mA, TJ = 150 °C, VPWR = 13 V
IOUT (LIM)_R1
Output Self-limiting Current (Has inrush current timer)
ROUT2
RDS (ON)_R2
Driver Drain-to-Source ON Resistance
• IOUT = 350 mA, TJ = 150 °C, VPWR = 13 V
IOUT (LIM)_R2
Output Self-limiting Current
LAMPOUT
RDS (ON)_LAMP
Driver Drain-to-Source ON Resistance
• IOUT = 1.0 A, TJ = 150 °C, VPWR = 13 V
IOUT (LIM)_LAMP
Output Self-limiting Current (Has inrush current timer)
Notes
9. This parameter is guaranteed by design, however it is not production tested.
33814
NXP Semiconductors
11
Table 4. Power input static electrical characteristics
Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
-
-
20
Ω
60
-
110
mA
7.0
0.0
8.0
0.375
9.0
0.5
V
Notes
TACHOUT
RDS (ON)_TACH
IOUT (SHUTDOWN)_
TACH
Driver Drain-to-Source ON Resistance
• IOUT = 50 mA, TJ = 150 °C, VPWR = 13 V
Output Current Shutdown
ALL PRE-DRIVERS (IGNOUT1, IGNOUT2 AND O2HOUT)
VGS(ON)
VGS(OFF)
Pre-driver Output Voltage, VPWR = 13 V
• IGD = 500 μA
• IGD = -500 μA
IIGN_GD_H
IGNOUTx Output Source Current (IGNOUT1 and IGNOUT2 by default)
• 1.0 ≤ VGD ≤ 3.0, VPWR = 13 V
10
-
-
mA
I(OFF)OCO
Output OFF Open Load Detection Current
• VDRAIN = 18 V, Outputs Programmed OFF
40
75
115
μA
GPGD Output Source Current (O2HOUT by default) at 1.0 ≤ VGD ≤ 3.0,
VPWR = 13 V
10
-
-
mA
Pre-driver Fault Detection Voltage Threshold, Outputs programmed
OFF (open load), Outputs programmed ON (short to battery)
• IGD = 500 μA
• IGD = -500 μA
100
1.0
250
2.5
400
4.0
mV
V
Output Clamp Voltage
48
53
60
V
Overcurrent Voltage Threshold for O2HOUT
• VO2HSENSN to VO2HSENSP
180
200
220
mV
180
360
200
400
220
440
mV
Current Sense Input Offset Current (IGNSENSP,IGNSENSN,
O2HSENSN, O2HSENSP)
-
-
15
μA
Current Sense Input Bias Current
-
-
15
μA
IGPGD_GD_H
VIGNFB (FLT-TH)
VGPGD(FLT_TH)
VCLAMP
VSENS-TH
VSENS-TH
VSENS-TH
ISENS-OFFSET
ISENS-BIAS
Overcurrent Voltage Threshold for IGNOUT1 and IGNOUT2
• VIGNSENSN to VIGNSENSP (IGNIN1 or IGNIN2 = 1)
• VIGNSENSN to VIGNSENSP (IGNIN1 and IGNIN2 = 1)
ISO-9141 TRANSCEIVER PARAMETERS (8.0 V < VPWR < 18 V)
VIL_ISO
Input Low Voltage at ISO I/O pin
-
-
0.3xVPWR
V
VIH_ISO
Input High Voltage at ISO I/O pin
0.7*VPWR
-
-
V
0.15x
VPWR
-
-
V
VHYST_ISO
Input Hysteresis at ISO I/O pin
VOL_ISO
Output Low-voltage at ISO I/O pin
-
-
0.2xVPWR
V
VOH_ISO
Output High-voltage at ISO I/O pin
0.8x
VPWRR
-
-
V
IPU
Internal pull-up resistor to VPWR
-
32
-
kΩ
50
100
150
mA
0.01
3.0
10
nF
-
12
-
mA
ILIM_ISO
Output current limit at ISO I/O pin (MTX = 0)
CL_ISO
Load capacitance at ISO I/O pin
(10)
I_ISO
Output load current at ISO I/O pin (MTX = 0, RLOAD = 1.0 kΩ, ±10%)
TLIM
Overtemperature Shutdown (OT)
155
-
185
°C
(10)
Overtemperature Shutdown Hysteresis
5.0
10
15
°C
(10)
TLIM (HYS)
Notes
10. This parameter is guaranteed by design, however it is not production tested.
33814
12
NXP Semiconductors
Table 4. Power input static electrical characteristics
Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VRS CONDITIONER INPUT
VVRS_THRESH
Comparator Thresholds
-
See Table variable via
SPI or dynamically
mV
Threshold Accuracy
AccuTHRESH
IBIASRSX
Steady State Condition (±20% only valid for VRS DAC thresholds
110 mV and higher.All other thresholds guaranteed monotonic only.)
Input Bias Current VRSP and VRSN (2.5 V common mode must be off)
-
-
-5.0
±20
%
5.0
µA
VCLAMP_P
VRS Positive Clamp Voltage at ICLAMP = 10 mA
5.5
-
5.8
V
VCLAMP_N
VRS Negative Clamp Voltage at ICLAMP = 10 mA
-0.45
-
-0.22
V
DIGITAL INTERFACE (MRX, MTX,CSB, SI, SCLK, SO, RINX,O2HIN, INJINX, IGNINX, BATSW, VRSOUT, RESETB)
VIH
Input Logic High-voltage Thresholds
0.7 x VCC
-
VCC + 0.3
V
VIL
Input Logic Low-voltage Thresholds
GND - 0.3
-
0.2 x VCC
V
500
-
-
mV
VHYS
CIN
Input Logic Voltage Hysteresis
-
-
20
pF
I LOGIC_SS
Sleep Mode Input Logic Current
• KEYSW = 0 V
-10
-
10
μA
(11)
ILOGIC_PD
Input Logic Pull-down Current INJIN1, INJIN2, RIN1, RIN2, SI, SCLK,
IGNIN1, IGNIN2, O2HIN
• 0.8 V to 5.0 V
30
50
100
μA
(11)
SO Tri-state Output (in Tri-state mode, CSB = 1)
• 0 V to 5.0 V
-10
-
10
CSB Input Current
• CSB = VCC
-10
-
10
ILOGIC_PU
Input Logic Pull-up Current - CSB and MTX
• 0.0 to 4.2 V
-20
-40
-90
ICSB(LKG)
CSB Leakage Current to VCC
• CSB = 5.0 V, KEYSW = 0.0 V
-
-
10
I TRISO
ICSB
Input Logic Capacitance
VSO_HIGH
VMRX_HIGH
SO, MRX High-state Output Voltage (CSB =0 for SO)
• ISO-HIGH = -1.0 mA
VCC - 0.4
-
-
VSO_LOW
VMRX_LOW
SO, MRX Low-state Output Voltage (CSB =0 for SO)
• ISO-LOW = 1.0 mA
-
-
0.4
μA
μA
μA
μA
V
V
VBATSW_HIGH
BATSW High-state Output Voltage
• ISO-HIGH = -10 mA
VCC - 1.0
-
-
VBATSW_LOW
BATSW Low-state Output Voltage
• ISO-LOW = 10 mA
-
-
1.0
VKEYSW_HIGH
KEYSW High-state Input Voltage
4.5
-
VPWR
V
VKEYSW_LOW
KEYSW Low-state Input Voltage
-0.3
-
2.5
V
VKEYSW_HYS
KEYSW Hysteresis
100
-
-
mV
V
V
Notes
11. This parameter is guaranteed by design, however it is not production tested.
33814
NXP Semiconductors
13
Table 4. Power input static electrical characteristics
Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
DIGITAL INTERFACE (MRX, MTX,CSB, SI, SCLK, SO, RINX,O2HIN, INJINX, IGNINX, BATSW, VRSOUT, RESETB) (CONTINUED)
VVRSOUT_LOW
VRS Low-state Output Voltage
• IVRS-LOW = 1.0 mA
-
-
0.4
V
VVRSOUT_HIGH
VRS High-state Output Voltage
• IVRS-HIGH = 1.0 mA
VCC -0.4
-
5.0
V
-
-
0.4
V
10
-
25
μA
200
-
500
kΩ
VRESET_LOW
RESET Low-state Output Voltage
• IRESET-LOW = 1.0 mA
IRESET_
LEAKAGE_HIGH
RESET High-state Leakage Current
RRESET_PULDOWN RESET Pull-down Resistor
33814
14
NXP Semiconductors
4.3
Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics (13)
Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.
Symbol
Characteristic
Min
Typ
Max
Unit
Required Low State Duration on VCC for Power On Reset
• VCC ≤ 0.2 V
1.0
-
-
μs
Power on RESET pulse width
100
-
-
μs
-
12.7
-
ms
Notes
POWER INPUT
t RESET
t(POR)
t(KEYSW_FILTER)
KEYSW Filter Time
(12)
WATCHDOG TIMER
WDMAX
WDMIN
WDRESET
-
-
10
sec.
Minimum Time Value Watchdog can be loaded with
1.0
-
-
ms
Reset Pulse Width when Watchdog times out
100
-
-
μs
0
-
50
%
-
1.0
-
%
Delay from CSB to Change in VRS Comparator Threshold
-
-
10
μs
(12)
Delay from CSB to Change in VRS Output Blank Time
-
-
10
μs
(12)
Maximum Time Value Watchdog can be loaded with (default time)
VRS CONDITIONING INPUT
OUTPUTBLANK
Output Blanking Time Programming Range
(% of previous out pulse 0 to 15/32 in 1/32 steps, 15/32 = 46.9%)
OUTPUTDEGLITCH Output Deglitch Filter Time (1/128 of the previous output pulse)
DELAYTHRESH
DELAYOBT
ISO9141 TRANSCEIVER
ISOBR
Typical ISO9141 Data Rate
-
10
-
kbps
tTXDF
Turn OFF Delay MTX Input to ISO Output
-
-
2.0
μs
Turn ON/OFF Delay ISO Input to MRX Output
-
-
1.0
μs
tRXR, tRXF
Rise and Fall Time MRX Output (measured from 10% to 90%)
-
-
1.0
μs
tTXR, tTXF
Maximum Rise and Fall Time MTX Input (measured from 10% to 90%)
-
-
1.0
μs
tRXDF, tRXDR
ALL LOW-SIDE DRIVERS
tSC1
Output ON Current Limit Fault Filter Timer
30
60
90
µs
tREF
Output Retry Timer
7.0
10
13
ms
tINRUSH
Inrush Current Delay Timer
7.0
10
13
ms
t(OFF)OC
Output OFF Open-circuit Fault Filter Timer
100
-
400
µs
t SR(RISE)
Output Slew Rate, INJOUT1, INJOUT2, ROUT1, ROUT2 and
LAMPOUT
• RLOAD = 500 Ω, VLOAD = 14 V
1.0
5.0
10
V/μs
t SR(FALL)
Output Slew Rate, INJOUT1, INJOUT2, ROUT1, ROUT2 and
LAMPOUT
• RLOAD = 500 Ω, VLOAD = 14 V
1.0
5.0
10
V/μs
tPHL
Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50% VDD to Output voltage 90% of VLOAD (INJ1, INJ2,
ROUT1, ROUT2, LAMP)
-
1.0
5.0
µs
tPHL
Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50% VDD to Output voltage 90% of VLOAD
(TACHOMETER)
-
1.0
6.0
µs
(12)
Notes
12. Guaranteed by Design
13. internal oscillator of 4.0 MHz ±10% typical for VPWR = 13 V, at room temp.
33814
NXP Semiconductors
15
Table 5. Dynamic electrical characteristics (13)
Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.
Symbol
Characteristic
Min
Typ
Max
Unit
tPLH
Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)
• Input at 50% VDD to Output voltage 10% of VLOAD (INJ1, INJ2,
ROUT1, ROUT2, LAMP)
-
1.0
5.0
µs
tPLH
Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)
• Input at 50% VDD to Output voltage 10% of VLOAD
(TACHOMETER)
-
1.0
6.0
µs
6.0
-
14
V/μs
Notes
ALL LOW-SIDE DRIVERS (CONTINUED)
t SR(FALL)
Output Slew Rate, Tachout
• RLOAD = 500 Ω, VLOAD = 14 V
ALL GATE PRE-DRIVER (IGN1, IGN2 AND O2H)
t(OFF)OC
Output OFF Open-circuit Fault Filter Timer
100
-
400
µs
tSC1
Overcurrent (short-circuit) Fault Filter Timer
30
-
90
µs
tPLH
Propagation Delay (Input Rising Edge OR CSB to Output Rising Edge)
• Input at 50% VDD to Output voltage 10% of VGS(ON)
-
1.0
5.0
µs
tPHL
Propagation Delay (Input Falling Edge OR CSB to Output Falling Edge)
• Input at 50% VDD to Output voltage 90% of VGS(ON)
-
1.0
5.0
µs
SPI DIGITAL INTERFACE TIMING (14)
t LEAD
Falling Edge of CSB to Rising Edge of SCLK
• Required Setup Time
100
-
-
ns
t LAG
Falling Edge of SCLK to Rising Edge of CSB
• Required Setup Time
50
-
-
ns
t SI (SU)
SI to Rising Edge of SCLK
• Required Setup Time
16
-
-
ns
t SI (HOLD)
Rising Edge of SCLK to SI
• Required Hold Time
20
-
-
ns
-
5.0
-
ns
-
5.0
-
ns
-
-
55
ns
-
-
55
ns
-
25
55
ns
-
-
1.0
µs
t R (SI)
t F (SI)
SI, CSB, SCLK Signal Rise Time (15)
SI, CSB, SCLK Signal Fall Time
(15)
t SO (EN)
Time from Falling Edge of CSB to SO Low-impedance
t SO (DIS)
Time from Rising Edge of CSB to SO High-impedance
t VALID
tSTR
Time from Falling Edge of SCLK to SO Data Valid
(14)
Sequential Transfer Rate
• Time required between data transfers
(17)
(16)
Notes
14. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface (variable with magnitude input
frequency).
15. Rise and Fall time of incoming SI, CSB and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output states data to be terminated at SO pin.
17. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.
33814
16
NXP Semiconductors
4.4
Timing diagrams
CSB
0.2 VDD
tLEAD
tLAG
0.7 VDD
SCLK
0.2 VDD
tSI(SU)
0.7 VDD
0.2 VDD
SI
tSI(HOLD)
MSB in
tSO(EN)
SO
tVALID
0.7 VDD
0.2 VDD
MSB out
tSO(DIS)
LSB out
Figure 4. Timing diagram
33814
NXP Semiconductors
17
4.5
Typical electrical characteristics
4.5.1
Driver and gate driver characteristics
10
Gate Pre-Drive Vol vs Vpwr @ 25 deg C
Gate Pre-Drive Voh vs Vpwr @ 25 deg C
9
0.18
8
0.16
7
0.14
6
0.12
5
0.1
4
0.08
Iload
3
2
500uA
1
1mA
0
0
5
10
15
100uA
0.06
100uA
0.04
500uA
0.02
1mA
0
20
0
5
10
15
20
Vpwr (V)
Figure 5. Typical electrical specifications
33814
18
NXP Semiconductors
Inj Driver Rdson vs Vpwr 25 deg C
0.27
0.25
)s
m 0.23
h
(o 0.21
n
so
d 0.19
R
0.17
0.15
4
6
8
10
12
14
Vpwr (V)
Figure 6. Typical electrical specifications (continued)
4.5.2
VCC and VPROT characteristics
Figure 7. VCC voltage vs. VPWR at 125 °C
Figure 9. VCC voltage vs. VPWR at -40 °C
Figure 8. VCC voltage vs. VPWR at 25 °C
Figure 10. VPROT voltage vs. VPWR at 125 °C
33814
NXP Semiconductors
19
Figure 11. VPROT voltage vs. VPWR at 25 °C
Figure 12. VPROT voltage vs. VPWR at -40 °C
33814
20
NXP Semiconductors
5
General IC functional description and application
information
5.1
System controller
5.1.1
System control signals
5.1.1.1
KEYSW input pin
KEYSW is the input from the vehicle ignition key switch. This signal is at VBAT (12 V) when the key is inserted and turned to the ON
position. When the key is in the OFF position and/or removed from the key switch, this input is pulled to ground by an internal pull-down
resistor. This pin is internally protected against a reverse battery condition by an internal diode. The state of the KEYSW input is also
available as a bit in the SPI Status Register.
5.1.1.2
BATSW output pin
The BATSW output pin is a 5.0 V logic level output, which by default is an indication of the state of the KEYSW input.
5.1.1.3
PWREN SPI control register BIT
The PWREN signal is a bit in the SPI Control Register #1 allowing “Prepare to shutdown” state transition.
5.1.2
5.1.2.1
Operating modes
Power On Reset (POR)
Applying VPWR and bringing KEYSW high (VBAT), longer than the KEYSW filter time, generates a Power On Reset (POR) and places the
device in the Normal operating state. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing
an erroneous POR. Upon enabling the device (KEYSW High), outputs are activated based on the initial state of the control register or
parallel input. All three supplies, VPP, VCC and VPROT, are enabled when KEYSW is brought high.
Table 6. Operational states
KEYSW Input
PWREN SPI Bit
Input
BATSWB Output
All Supplies
STATE
L
L
L
OFF
Sleep
H
L
H
ON
NORMAL
H
H
H
ON
NORMAL
L
H
L
ON
Prepare to shutdown
33814
NXP Semiconductors
21
VPWR_OV=1 ||
VCC_UV=1||
VCC_POR=1
RESET
Y
KE
SW
=1
KE
YS
W
SLEEP
(Engine/Key is off)
RESETB=0
BATSW=0
OV – Over
Voltage
Overvoltage
UV – Under
Voltage
Undervoltage
WD = Watchdog
Watch Dog
TD = Time Delay
POR = Power On Reset
&& = logic AND
|| = logic OR
(SPI Bus Usable)
RESETB=1
BATSW=0
Passive State
&&
=0 1
W =
YS EN
E
R
K W
P
SET=1
PREPARE TO
SHUTDOWN
(SPI Bus Usable)
RESETB=1
BATSW=1
5 uS
TD = ~2
RE
N=
0
NORMAL
KEYSW=0 &&
PWREN=0
SPI_RE
PW
KEYSW=0
V
VC PW
TD C_ R_
= P O OV =
12 R 0
8 =0 &
uS + &
W
V D_
VC PW T I M
C _ R _ EO
UV OV U
=1 =1 T=1
||
||
=0
KEYSW=1 || WD_TIMEOUT=1 ||
VPWR_OV=1 || VCC_UV=1
VPWR_UV=1
from any state
(Resets ASIC & MCU)
RESETB=0
BATSW=1
PWREN=1
SPI_RESET
(Resets ASIC Only)
RESETB=1
BATSW=1
Active States
Figure 13. 33814 functional state diagram
5.1.2.2
Normal state
The default Normal state is entered when power is applied to the VPWR and KEYSW pins. Note that the device is designed to have VPWR
present before KEYSW is brought high. It is acceptable to bring VPWR and KEYSW high simultaneously. However it is not recommended
to bring KEYSW high while VPWR is low.
SPI register settings from Power On Reset (POR) are as follows:
• All outputs turned off
• Off State open load detection enabled (LSD)
• Default values in the SPI Configuration, Control and Status registers
5.1.2.3
Sleep state
When KEYSW signal is low and the PWREN SPI Control register bit is also low, the 33814 enters into Sleep mode. In the Sleep state, all
outputs, current sources and sinks are off and the device consumes less than IVPWR (SS). When KEYSW signal goes high, it wakes up the
IC, turns on the VPP regulator and a Power On Reset signal is generated.
5.1.2.4
Prepare to shutdown state
The purpose of the PWREN signal is to allow the MCU to control the shutdown of power to itself when the user turns off the KEYSW. This
may be necessary to allow the MCU the time required to perform its pre-shutdown routines. When the MCU wants to shutdown the power
supplies in the 33814, it must write a logic zero (0) to the PWREN bit in the SPI Control register. Only the state of the PWREN bit in the
SPI Control register controls the shutdown of the 33814 power supplies. In this state, only the outputs are turned off (except ROUT2 if the
Shutdown Disable bit is set. See 5.5.3.3. Using ROUT2 as a power relay, page 35).
33814
22
NXP Semiconductors
5.1.2.5
Power On Self-test (POST)
When a power on occurs after a POR, it may be desired to go through an initial Power On Self-test routine to ensure the SPI is working
correctly and the status registers in the 33814 are viable. After a POR, all the registers in the 33814 contain their ‘default’ values, as
indicated in the SPI register tables later in this document. The watchdog is also set to its default timeout value of 10 seconds, so any POST
routine must be accomplished within this time frame or a WD reset may occur.
To perform a POST routine, the MCU should first send a SPI message to set the POST enable bit in the SPI control register 1, bit 6. Once
this bit is set, the status registers are disconnected from the analog and logic portions of the 33814 and are connected only to the SPI
circuitry. The POST can then write various data patterns to the status registers and verify that none of the bits are ‘stuck’ and state of the
bit is accurately reflected. Note that bits in the status register labeled ‘x’ are not implemented and testing these bits may result in erroneous
data. After testing all the status registers and confirming they are viable, the status registers can be set back to their default values by
clearing the POST Enable bit back to 0. The POST enable bit allows the MCU to write ones (1s) to the Status registers.
Normally, the status register can only be cleared to zeros by the MCU and ones can be written to the status register only by the 33814
internal logic. This is designed to prevent the MCU from missing any reported fault bits and, for the 33814, to prevent system status errors
resulting from the MCU erroneously writing a one (1) to a fault bit.
Once the POST enable bit is set back to a zero (0) by the MCU, the status register returns to the condition where the 33814 can only write
ones (1s) to it and the MCU can only write zeros (0s) to it. Again, it is important to note that any POST routine should be designed to take
less than 10 seconds to avoid a watchdog reset from occurring and truncating the POST routine, because the WD reset clears the POST
Enable bit as well.
5.1.3
BATSW output functionality
The BATSW output pin has several functionalities:
•
By default, the BATSW output pin is an indication of the state of the KEYSW input.
•
The BATSW output can also be used to control an LS driver, such as the Relay ROUT2 driver by connecting the BATSW output
to the RIN2 input.
•
The BATSW output can also be configured as a low current LED high-side driver controlled through the SPI interface.
5.1.3.1
BATSW pin as a KEYSW input indication
When KEYSW is at VBAT (12 V) level, the BATSW output is a logic 1 (5.0 V) and when KEYSW is at ground (0 V) level, BATSW is at a
logic 0. The BATSW output may be used to inform the MCU the user is trying to shutdown the vehicle.
5.1.3.2
BATSW pin as an LS driver control
The BATSW output can also be used to control an LS driver, such as the Relay ROUT2 driver, by connecting the BATSW output to the
RIN2 input. (see 5.5.3.3. Using ROUT2 as a power relay, page 35)
5.1.3.3
BATSW pin as an LED driver
If the BATSW signal is not needed by the MCU or to control the Relay 2 output, it can be configured as a low current LED high-side driver
controlled through the SPI interface. As a high-side driver, BATSW can be PWM’d to allow an LED to be dimmed. A bit in the SPI Battery
Switch Logic Output Configuration register called ‘HSD’, controls whether the BATSW output is a simple high-side driver, or controlled by
KEYSW as indicated previously.
MC33814
300
BATSW
.01μF
OffBoard
LED
GND
Figure 14. Recommended Circuit to Use BATSW as an LED Driver
33814
NXP Semiconductors
23
If the BATSW output is used to control an LED, the LED cathode should be tied to ground and the LED anode should be connected to the
BATSW pin through an external resistor. The value of the external resistor should be 340 Ω or greater. Care must be taken if the BATSW
output is sent off-board due to the chance of shorts to the battery or shorts to ground, for which the output is not protected. At a minimum,
this output should be protected by a diode, a current limit resistor and an ESD capacitor (0.01 µF ceramic).
5.1.4
System SPI registers
5.1.4.1
SPI configuration registers
Table 7. Battery switch logic output configuration register
Reg # Hex
6
6
Battery Switch Logic Output
7
6
5
4
3
2
1
0
R/W
HSD Mode
x
x
x
x
x
PWM
Freq.1
PWM
Freq. 0
Reset
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 8. Battery switch logic output configuration register field
Field
Description
7-HSD Mode
1-0 PWM Freq.x
BATSW Mode selection
0 - BATSW is controlled by KEYSW
1 - BATSW is used as a high-side driver
PWM Frequency and Duty Cycle Mode (18)
00 - PWM Freq.: None or Ext.Pin - D/C: None or ext.Pin
01 - PWM Freq.:100 Hz-D/C: Internal
10 - PWM Freq.: 1 KHz-D/C: Internal
11 - PWM Freq.:On ext. pin /100 -D/C: Internal
Notes
18. See 5.5.2.2. Pulse Width Modulation mode, page 33
5.1.4.2
SPI control registers
Table 9. Other OFF/ON control register
Reg # Hex
1
8
1
8
Other OFF/ON Control
Batsw
7
6
5
4
3
2
1
0
R/W
Pwren
OFF/ON
POST
Enable
OFF/ON
X
VProt
ON/OFF
X
Batsw
OFF/ON
Tach
OFF/ON
RESET
internal
only
Reset
(0)
(0)
(0)
(1)
(0)
(0)
(1)
(0)
R/W
X
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Reset
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 10. Other OFF/ON control register field description
Field
Description
7-Pwren OFF/ON
Power Enable
0-Power Disable (allowing sleep mode entry)
1-Power Enable (allowing Prepare to Shutdown mode entry)
Power On Self Test Enable
6-POST Enable OFF/ON 0-POST Disable
1-POST Enable
2-BATSW OFF/ON
BATSW Output Control
0-BATSW Output OFF
1-BATSW Output ON
33814
24
NXP Semiconductors
Table 11. BATSW control register field description
Field
Description
PWM Duty Cycle Setting with 1% increment 0000000 to
1100100 (Dec. 100) represent 0% to 100%
1100100 (Dec. 100) to 1111111 (Dec.127) all map to 100%.
6-0 PWM x
5.1.4.3
SPI status registers
Table 12. Power supply and any system fault status register
Reg # Hex
13
D
Power Supply and Any
System Faults
7
6
5
4
3
2
1
0
R/W
Any
System
Faults
Keysw
Pwren
Batsw
SPI Error
VPROT
Short to
Battery
VPROT
Overtemp
OT
VPROT
Short to
Ground
Reset
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
Table 13. Power supply and any system fault status register field description
Field
Description
System-wide any fault bit whose stats is the OR of all the other “Any fault” bits in the other status
7-Any System Fault 0-No Fault reported
1-At least one Fault is reported (19)
6-Keysw
5-PWREN
4-Batsw
KEYSW Pin Status:
0-KEYSW is high (VBAT Present)
1-KEYSW is low (Prepare to Shutdown mode)
PWREN Status
0-PWREN Control bit is low
1-PWREN Control bit is high
BATSW Pin Status
0-BATSW Pin is low
1-BATSW Pin is high
Notes
19. The MCU must interrogate all the other status registers to determine the actual fault(s) present.
5.2
Watchdog
5.2.1
Watchdog Normal operation
The watchdog is a programmable timer used to monitor the operation of the MCU. The timer programming is done by the Watchdog
Parameters SPI Configuration Register by selection the Time Multiplier Value (bit 6-4) and the Time Value (bit 3-0).
Watchdog Timer = Time Multiplier Value (1.0 s,100 ms, or 10 ms) X Time Value (1 to 10)
Using this technique, time values from 1.0 ms. to 10 seconds can be programmed into the watchdog.(default value is 10 s)
When the MCU is executing code properly, its program code should contain instructions to periodically send a SPI message to the
watchdog SPI control register to refresh the watchdog. The watchdog timer, once refreshed, reloads the time interval value stored in the
SPI watchdog configuration register and begins counting time again. Under normal operating conditions this sequence continues until the
MCU shuts down, typically, when the KEYSW is turned off.
33814
NXP Semiconductors
25
5.2.2
Watchdog Fault operation
In the event that something goes wrong during the MCU program execution, such as an unexpected breakpoint or some other program
hang-up such as the execution of a HALT instruction, the watchdog may not be refreshed. When the WD time interval value programmed
in the SPI Configuration register elapses, the watchdog issues a RESETB pulse. This RESETB pulse causes the MCU to restart its
program and correct operation should be restored. After any RESETB (power-on or other), the watchdog SPI configuration register
contains the default value for the refresh time (10 seconds). The watchdog is also enabled by default. The MCU, in its initialization (startup) code, can choose to change this default value and/or disable the watchdog by sending a SPI command to write new information in the
watchdog SPI configuration register.
5.2.3
Disabling the Watchdog timer
A watchdog reset occurs, by default, 10 seconds after the POR. If the MCU needs to be programmed in-circuit, a means of disabling the
watchdog must be provided to avoid interrupting the MCU programming procedure. This disable mechanism can be a jumper between the
RESETB pin of the 33814 and the MCU’s Reset input pin. Alternatively, an isolation resistor can be placed between the RESETB pin on
the 33814 and the MCU’s reset input pin, allowing the MCU’s reset pin to be pulled high independently of the 33814 RESETB. The
watchdog can also be disabled via a bit in the SPI WD configuration register.
5.2.4
Watchdog SPI register
5.2.4.1
Watchdog SPI configuration register
Table 14. Watchdog parameters configuration registers
Reg # Hex
10
A
7
Watchdog Parameters
R/W
Disable/
Enable
Reset
(1)
6
5
4
3
2
1
0
Load Time Load Time Load Time Load Time Load Time Load Time Load Time
x1 sec
x100 ms
x10 ms
8
4
2
1
(1)
(0)
(0)
(1)
(0)
(1)
(0)
Table 15. Watchdog parameter - register field descriptions
Field
7-Disable/Enable
6-Load Time x1 sec
Description
Watchdog Enable/Disable
0-Watchdog Disable
1-Watchdog Enable (Default State)
Time Multiplier Value (20)
0- Disable
1- Multiplier value = 1.0 sec (Default State)
Time Multiplier Value (20)
5-Load Time x100 ms 0- Disable (Default State)
1- Multiplier value = 100 ms
4-Load Time x10 ms
Time Multiplier Value (20)
0- Disable (Default State)
1- Multiplier value = 10 ms
Bits 3, 2, 1, 0 are a binary coded decimal (BCD) value from 1 to 10. (11 to 16
3-0 Load Time Value are mapped to 10 and 0 is mapped to 1)
Default state = 1010 = X10
Notes
20. There are three time multiplier values so only one bit, 6, 5, or 4 may be set at one time. Setting
more than one bit results in the highest multiplier value getting precedence.
33814
26
NXP Semiconductors
5.2.4.2
Watchdog SPI control register
Table 16. Watchdog control registers
Reg # Hex
12
C
7
Watchdog
R/W
WDRFSH
Reset
(0)
6
5
4
3
2
1
0
Load Time Load Time Load Time Load Time Load Time Load Time Load Time
x1 sec
x100 ms
x10 ms
8
4
2
1
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 17. Watchdog control - register field descriptions
Field
Description
Watchdog Refresh
0-No Watchdog refresh action
1-Refresh the watchdog timer. (reload the time value from the Watchdog
Parameters Register)
7-WDRFSH
6-Load Time x1 sec
Temporary Time Multiplier Value (21)
0- Disable
1- Multiplier value = 1.0 sec
Temporary Time Multiplier Value (21)
5-Load Time x100 ms 0- Disable
1- Multiplier value = 100 ms
Temporary Time Multiplier Value (21)
4-Load Time x10 ms 0- Disable
1- Multiplier value = 10 ms
3-0 Load Time Value
Bits 3, 2, 1, 0 are a Temporary Binary coded decimal (BCD) value from 1 to 10.
(11 to 16 are mapped to 10 and 0 is mapped to 1)
Notes
21. There are three time multiplier values so only one bit, 6, 5, or 4 may be set at one time. Setting
more than one bit results in the highest multiplier value getting precedence.
Note: The watchdog SPI Control Register can also be loaded with a time value to temporarily set a different value in the watchdog timer
for the next cycle. When Bits 6 thru 0 in the watchdog SPI control register are zero, the value stored in the watchdog SPI configuration
register loads into the watchdog timer. If there is a temporary time value written into the watchdog SPI control register, the value loads
into the watchdog. The watchdog SPI control register is automatically cleared to zero when the watchdog timer is loaded. Unless a new
temporary time value is again written to the watchdog SPI Control Register, the next watchdog timer load is from the value stored in the
watchdog SPI configuration register,
5.2.4.3
Watchdog SPI status register
Table 18. Watchdog status register
Reg # Hex
10
A
Watchdog State
7
6
5
4
3
2
1
0
R/W
Enable/
Disable
WD timer
bit 6
WD timer
bit 5
WD timer
bit 4
WD timer
bit 3
WD timer
bit 2
WD timer
bit 1
WD timer
bit 0
Reset
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 19. Watchdog status - register field descriptions
Field
7-Enable/Disable
6-0 WD Timer bit x
Description
Watchdog Enable/Disable Status
0-Watchdog disable
1-Watchdog Enable
Reflecting the Watchdog Timer value
Each step represents the WD timer/127
33814
NXP Semiconductors
27
5.3
System reset
5.3.1
RESETB output pin
The RESETB pin is a 5.0 volt logic, low level output used to reset the MCU.The RESETB pin is an open drain output. Without power on
the 33814 circuit, the RESETB pin is held low by an internal pull-down resistor. In a typical application, the RESETB pin must be pulled
up externally by a pull-up resistor to VCC.
5.3.2
Reset sources
When power is applied to the circuit and the voltage on the VCC pin reaches the lower voltage threshold, the RESETB pin remains at a
low level (open drain FET turned on) for a period of time equal to the time value WDRESET. After this time period, the RESETB pin goes
high and stays high until a reset pulse is generated due to any of the following events:
•
A watchdog timer timeout event occurs
•
An undervoltage event on VCC occurs
•
An overvoltage event on VPWR occurs
A Power On Reset (POR) is always provided upon power ON (anytime the IC goes from sleep state to active state).
5.3.3
Internal reset
The SPI control register includes a bit labeled ‘Reset’. When this bit is set to a one (1) by the MCU, it instructs the 33814 to perform an
internal reset. This reset does NOT toggle the RESETB output pin. However, it causes all internal registers to be initialized back to their
default values (including clearing the reset bit in the SPI control register).
Table 20. Other OFF/ON control register
Reg # Hex
1
1
Other OFF/ON Control
7
6
5
4
3
2
1
0
R/W
Pwren
OFF/ON
POST
Enable
OFF/ON
X
VProt
ON/OFF
X
Batsw
OFF/ON
Tach
OFF/ON
RESET
internal
only
Reset
(0)
(0)
(0)
(1)
(0)
(0)
(1)
(0)
Table 21. Other OFF/ON register field descriptions
Field
Description
Reset Internal Only Command
0-RESET Internal Only 0-Do not perform an internal reset
1-Perform an internal reset
5.4
Power supplies
5.4.1
Pin description
5.4.1.1
PWR supply input
The VPWR pin is the battery input to the 33814 IC. The VPWR pin requires an external reverse battery and adequate transient voltage
protection. The VPWR pin should be bypassed to ground, as close to the IC as possible, with a 0.1 µF ceramic capacitor.
5.4.1.2
VPPREF output
The VPPREF output pin is used to drive the base of an external regulator PNP pass transistor. It is not recommended that this voltage be
brought off of the module PC board, because it may not have adequate protection to prevent damage to the PNP pass transistor under
short-to-ground or short-to-battery conditions.
33814
28
NXP Semiconductors
5.4.1.3
VPPSENS input
The VPPSENS pin is used to monitor the VPP pre-regulator output voltage from the external pass transistor’s collector and to supply the
input voltage to the VCC and VPROT regulators. The VPPSENS pin should be bypassed to ground, as close to the IC as possible, with a
0.1 µF ceramic capacitor and a higher value electrolytic capacitor in parallel. The VPPSENS pin should not be used to supply other
components. The external regulator PNPN pass transistor should be dedicated to the 33814.
5.4.1.4
VCC output (5.0 V supply)
The VCC output supplies 5.0 V power to the system MCU and other on-board peripherals. An external capacitor VOCE is recommend.
5.4.1.5
VPROT output (5.0 V protected supply)
The VPROT Output is a protected 5.0 Volt output that tracks the VCC voltage. The VPROT output should be protected against ESD by
means of a 0.1 µF ceramic capacitor on the output and a higher value electrolytic capacitor in parallel. An external capacitor VOCE is also
recommended.
5.4.1.6
GND
The GND pin provides the ground reference for the VPWR, VPP, VPROT and VCC supplies. The GND pin is used as a return for both the
power supplies, as well as power a ground for some of the lower current output drivers. The higher current output drivers have their own
ground pins. All ground pins (INJGND1, INJGND2, RGND1 and RGND2) and the exposed pad must be directly connected to this pin and
to the negative battery terminal. There is no separate ground pin associated with the LAMPOUT driver. It shares a ground with ROUT2.
5.4.2
5.4.2.1
Power supplies functions
Power supply
The 33814 is designed to operate from VPWRMIN to VPWRMAX on the VPWR pin. The VPWR pin supplies power to all internal regulators
and analog and logic circuit blocks. All IC analog current and internal logic current is provided from the VPWR pin. An overvoltage
comparator monitors this pin. When an overvoltage condition is present, all outputs and voltage regulators are shut off for protection.
5.4.2.2
VPP pre-regulator
The VPP pre-regulator supplies the input voltage to the VCC and VPROT regulators. The VPP regulator is a low drop-out (LDO) regulator.
It provides a regulated output voltage when the input is greater than its specified voltage level and it follows the input voltage when it is
below its specified voltage level.
The VPP regulator uses an external PNP transistor as a pass element. This allows the user to choose the PNP’s size and package
considerations to meet the system requirements. The amount of power the external PNP transistor has to dissipate depends on the
maximum voltage the system can be expected to run at and the maximum expected current drawn from the VCC and VPROT regulators.
The VPPSENS pin is used to feedback the value of the VPP voltage for regulation. Since the VPP regulator is not intended to supply offthe-board loads, there is no short-to-ground or short-to-battery protection on the output of the external PNP.
5.4.2.3
VCC regulator
The VCC regulator obtains its input voltage from the VPP pre-regulator. The VCC regulator output is used for supplying 5.0 V to the MCU
and for setting communication threshold levels via the internal SPI SO driver. The VCC regulator contains an internal pass transistor
protecting against overcurrent.
A Power On Reset (POR) circuit monitors the VCC output voltage level. When the VCC voltage exceeds the VCC(POR) threshold, the
RESETB line is held low for an additional delay time t(POR) before being brought to a logic one level. An undervoltage (UV) circuit monitors
the output of the VCC regulator. When the voltage goes below the VCC(UV) threshold for more than the VCC filter time, t(VCC-UV), the
RESETB line is asserted to a logic zero state and remains there until the POR condition is met.
33814
NXP Semiconductors
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5.4.2.4
VPROT regulator
The protected output VPROT is a tracking regulator using the VCC output as a reference. Because the VPROT regulator is expected to supply
5.0 V to external sensors and other off-board peripherals in the vehicle, it is well protected against shorts-to battery, shorts-to-ground,
overcurrent and overtemperature.The VPROT supply is enabled at power-on, but can be disabled via the SPI Control Register.
5.4.2.5
Power up sequence
Table 22. Power up sequence
t
Actions
t0
Battery connected to VPWR Pin
t1
User turns on ignition switch, KeySw => High
• Internal regulators, band gap reference and bias current generator are enabled
t2 = t1+ ~5.0 μs
Internal PORb de-asserted after internal 2.5 V regulator to the logic core stabilizes
• Logic and oscillator are enabled
• Start KeySw filter time
t3 = t2+ ~12.7 ms
KeySW filter time period expires
• Enable VPP pre-regulator
• Soft start sets turn on ramp to ~ 400 μs
VPPSENS exceeds 4.8 V, enables VCC & VPROT regulators
• Soft start sets turn on ramps to ~ 2.0 ms
t4 = t3+ (< 400 μs)
• BatSw buffer receives power
• Output rises with VCC
t5 = t4+ (< 2.0 ms)
t6 = t5+ ~128 μs
VCC exceed POR Threshold ~4.6 V
• Start POR Timing ~128 μs
POR Time period expires
• Release RESETB pin
~5µs
t0 t1 t2
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