MC33901WEFR2

Freescale Semiconductor Technical Data Document Number: MC33901 Rev. 3.0, 6/2015 High-speed CAN Transceiver The MC33901/34901 are SMARTMOS high-speed (up to 1.0 Mbits/s) CAN transceivers providing the physical interface between the CAN protocol controller of an MCU and the physical dual wires CAN bus. They are packaged in an 8-pin SOIC with market standard pinout, and offer excellent EMC and ESD performance without the need for external filter components. Four devices variations are available: - Versions with and without CAN bus wake-up. - Versions with and without TXD dominant protection. Features • Very low-current consumption in standby mode • Compatible with 3.3 V or 5.0 V MCU interface • Standby mode with remote CAN wake-up on some versions. • Pin and function compatible with market standard Cost efficient robustness: • High system level ESD performance • Very high electromagnetic Immunity and low electromagnetic emission without common mode choke or other external components. Fail-safe behaviors: • TXD Dominant timeout, on the 33901 version. • Ideal passive when unpowered, CAN bus leakage current RXD low, bus recessive => RXD high). The delay between bus dominant and RXD low, and bus recessive and RXD high is longer than in Normal mode (refer to tTGLT). The three events must occur within the tWU_TO timeout. Figure 10 illustrates the wake-up detection and reporting (toggling) mechanism. If the three events do not occur within the TWU_TO timeout, the wake-up and toggling mechanism are not active. This is illustrated in Figure 11. The three events and the timeout function avoid a permanent dominant state on the bus that would generate a permanent wake-up situation, which would prevent the system from entering low power mode. 4.3.3 Unpowered Mode When VIO is below VIO UV, the device is in unpowered mode. The CAN bus is in high-impedance and is unable to transmit, receive, or report bus wake-up events. 4.4 Fail-safe Mechanisms The device implements various protection, detection, and predictable fail-safe mechanisms. 33901 10 Analog Integrated Circuit Device Data Freescale Semiconductor 4.4.1 STB and TXD Input Pins The STB input pin has an internal integrated pull-up structure to the VIO supply pin. If STB is open, the device is set to Standby mode to ensure predictable behavior and minimize system current consumption. The TXD input pin also has an internal integrated pull-up structure to the VIO supply pin. If TXD is open, the CAN driver is set to the recessive state to minimize current consumption and ensure that no false dominant bit is transmitted on the bus. 4.4.2 TXD Dominant Timeout Detection If TXD is set low for a time longer than the TXD DOM parameter, the CAN drivers are disabled and the CAN bus returns to recessive state. This prevents the bus from being set to the dominant state permanently in case a fault sets the TXD input to low level permanently. The device recovers from this when a high level is detected on TXD. Refer to Figures 12. 4.4.3 CAN Current Limitation The current flowing in and out of the CANH and CANL driver is limited to a maximum of 100 mA, in case of a short-circuit (parameter for ILIM). 4.4.4 CAN Overtemperature If the driver temperature exceeds TSD, the driver is turned off to protect the device. A hysteresis is implemented in this protection feature. The device overtemperature and recovery conditions are shown in Figure 7 “Overtemperature behavior”. The driver remains disabled until the temperature has fallen below the OT threshold minus the hysteresis and a TXD high to low transition is detected. Overtemperature Threshold Temperature Hysteresis Hysteresis Event 1 Event 1 Event 2 Event 2 Event 4 Event 3 TXD Event 3 high low dominant recessive dominant dominant BUS Event 1: overtemperature detection. CAN driver disable. Event 2: temperature falls below “overtemperature threshold minus hysteresis” => CAN driver remains disable. Event 3: temperature below “overtemperature threshold minus hysteresis” and TxD high to low transition => CAN driver enable. Event 4: temperature above “overtemperature threshold minus hysteresis” and TxD high to low transition => CAN driver remains disable. Figure 7. Overtemperature behavior 4.4.5 VDD and VIO Supply Voltage Monitoring For MC3x901WEF and MC3x901SEF versions: The device monitors the VDD and VIO supply inputs. If VDD falls below VDD UV (VDD_UV), the device is set in Standby mode. This ensures a predictable behavior due to the loss of VDD. CAN driver, receiver, or bus biasing cannot operate any longer. In this case, the bus wakeup is available as VIO remains active. If VIO falls below VIO UV (VIO_UV), the device is set to an unpowered condition. This ensures a predictable behavior due to the loss of VIO, CAN driver, receiver, or bus biasing can not operate any longer. This sets the bus in high-impedance and in ideal passive behavior. 33901 Analog Integrated Circuit Device Data Freescale Semiconductor 11 For MC3x901WNEF and MC3x901SNEF versions: As VIO is internally connected to VDD, VIO voltage depends on the VDD supply. If VDD is between VIO_UV and VDD_UV, the device is set in Standby mode. If VDD is below VIO UV, the device is set in unpowered mode. 4.4.6 Bus Dominant State Behavior in Standby Mode In device Standby mode, a bus dominant condition due, for instance to a short-circuit or a fault in one of the other CAN nodes, does not generate a permanent wake-up event, by virtue of the multiple events (dominant, recessive, dominant) and timeout required to detect and report bus wake-ups. 4.5 Device Operation Summary The following table summarizes the device operation and the state of the input output pins, depending on the operating mode and power supply conditions. Table 6. Operation for VIO Devices STANDBY AND NORMAL MODES FOR MC3X901 VERSION MODE Normal Standby Description Nominal supply and normal mode VDD range from 4.5 V to 5.5 V VIO range from 2.8 V to 5.5 V STB TXD RXD CAN Low TXD High => bus recessive TXD Low => bus dominant Report CAN state (bus recessive => RXD high, bus dominant => RXD low). CANH and CANL drivers controlled by TXD input. Differential receiver report bus state on RXD pins. Biasing circuitry provides approx 2.5 in recessive state. Disabled No effect. on CAN bus. Report bus wake up via toggling mechanism for MC3x901WNEF. RXD High level for MC3x901SNEF CAN driver and differential receiver disabled. Bus biased to GND via internal RIN resistors for MC3x901WNEF. Bus high-impedance for MC3x901SNEF. Enabled on MC3x901WNEF Not available on MC3x901SNEF Nominal from 0 V from 2.8 V High or supply and to 5.5 V to 5.5 V floating standby mode Wake-up UNDERVOLTAGE AND LOSS OF POWER CONDITIONS FOR MC3X901 VERSION MODE Description VDD range VIO range Device in standby mode from 0 V from 2.8 V Standby to due to loss of to 5.5 V due to VDD VDD (VDD fall VDD_UV (5) loss (4) below VDD UV) Device in unpowered Unpowered state due to due to VIO low VIO. CAN loss bus highimpedance (4) from 0 V to VIO_UV STB X (3) X TXD RXD CAN Wake up X Report bus wake up via toggling mechanism for MC3x901WEF. RXD High level for MC3x901SEF CAN driver and differential receiver disabled. Bus biased to GND via internal RIN resistors for MC3x901WEF. Bus high-impedance for MC3x901SEF. Enabled on MC33901WEF Not available on MC33901SEF. X Pulled up to VIO down to VIO approx 1.5 V. CAN driver and differential receiver disabled. High-impedance, with ideal passive behavior. Not available. Notes 3. STB pin has no effect. Device enters in standby mode. 4. VDD consumption < 10 uA down to VDD approx 1.5 V. 5. VIO consumption < 10 uA down to VIO approx 1.5 V. If STB is high or floating. 33901 12 Analog Integrated Circuit Device Data Freescale Semiconductor Table 7. Operation for Non-VIO Devices STANDBY AND NORMAL MODES FOR MC3X901N VERSIONS MODE Description VDD range Normal Nominal supply and normal mode from 4.5 V to 5.5 V Standby Nominal supply and standby mode from 2.8 V to 5.5 V STB TXD RXD CAN Low TXD High => bus recessive TXD Low => bus dominant Report CAN state (bus recessive => RXD high, bus dominant => RXD low) CANH and CANL drivers controlled by TXD input. Differential receiver report bus state on RXD pins. Biasing circuitry provides approx 2.5 in recessive state Disabled No effect. on CAN bus. Report bus wake up via toggling mechanism for MC3x901WEF. RXD High level for MC3x901SEF CAN driver and differential receiver disabled. Bus biased to GND via internal RIN resistors for MC3x901WEF. Bus high-impedance for MC3x901SEF Enabled on MC33901WEF Not available on MC33901SEF High or floating Wake-up UNDERVOLTAGE AND LOSS OF POWER CONDITIONS FOR MC3X901N VERSIONS MODE Description VDD range Device in unpowered Unpowered state due to due to VDD low VDD and loss so VIO. CAN bus highimpedance from 0 V to VIO_UV STB X TXD X RXD Pulled up to VIO down to VIO approx 1.5 V. CAN CAN driver and differential receiver disabled. High-impedance, with ideal passive behavior Wake-up Not available. 33901 Analog Integrated Circuit Device Data Freescale Semiconductor 13 4.6 Electrical Characteristics Table 8. Static Electrical Characteristics Characteristics noted under conditions 4.5 V  VDD  5.5 V, 2.8 V  VIO  5.5 V, - 40 C  TA  125 C, GND = 0 V, R on CAN bus  (RL) = 60 , unless otherwise noted. Typical values noted reflect the approximate parameter at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes POWER INPUT VDD VDD VDD Supply Voltage Range • Nominal Operation 4.5 – 5.5 V VDD_UV VDD Undervoltage threshold 3.0 – 4.5 V – – – – – 40 – — 5.0 65 5.0 15 mA mA µA µA 2.8 – 5.5 V VIO Under voltage threshold – – 2.8 V VIO supply current • Normal mode, TXD high • Normal mode, TXD low or CAN bus in dominant state • Standby mode, CAN bus in recessive state • Standby mode, wake-up filter and wake-up time out running – – – – – – 5.0 – 200 1.0 10 150 µA mA µA µA 0.7 – 200 – – – – 0.3 – VIO V mV – 100 – k Input voltages • High level Input Voltage • Low level input voltage • Input threshold hysteresis 0.7 – 200 – – 300 – 0.3 – VIO V mV Pull-up resistor to VIO 5.0 – 50 k Output current • RXD high, VRXD high = VIO - 0.4 V • RXD low, VRXD high = 0.4 V -5.0 1.0 -2.5 2.5 -1.0 5.0 25 50 90 IVDD VDD supply current • Normal mode, TXD High • Normal mode, TXD Low • Standby mode (MC3x901) • Standby mode (MC3x901N) POWER INPUT VIO VIO VIO_UV IVIO Vio Supply Voltage Range • Nominal Operation STB INPUT VSTB RPU-STB Input voltages • High level Input Voltage • Low level input voltage • Input threshold hysteresis Pull-up resistor to VIO TXD INPUT VTXD RPU-TXD RXD OUTPUT IRXD RPU-RXD Pull-up resistor to VIO (in standby mode, without toggling - no wake-up report) mA k 33901 14 Analog Integrated Circuit Device Data Freescale Semiconductor Table 8. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V  VDD  5.5 V, 2.8 V  VIO  5.5 V, - 40 C  TA  125 C, GND = 0 V, R on CAN bus  (RL) = 60 , unless otherwise noted. Typical values noted reflect the approximate parameter at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Recessive voltage, TXD high, no load • CANL recessive voltage • CANH recessive voltage 2.0 2.0 2.5 2.5 3.0 3.0 V VDIFF_REC CANH - CANL differential recessive voltage, TXD high, no load -50 – 50 mV VREC_SM Recessive voltage, sleep mode, no load • CANL recessive voltage • CANH recessive voltage -0.1 -0.1 – – 0.1 0.1 V Dominant voltage, TXD low (t < TXDOM), RL = 45  to 65  • CANL dominant voltage • CANH dominant voltage 0.5 2.75 – – 2.25 4.5 V CANH - CANL differential dominant voltage, RL = 45  to 65  TxDLOW 1.5 2.0 3.0 V Driver symmetry CANH + CANL 0.9 1.0 1.1 VDD 40 -100 – – 100 -40 mA Notes CANL AND CANH TERMINALS VREC VDOM VDIFF_DOM VSYM ILIM Current limitation, TXD low (t < TXDOM) • CANL current limitation, CANL 5.0 V to 28 V • CANH current limitation, CANH = 0 V VDIFF_THR CANH - CANL Differential input threshold 0.5 – 0.9 V VDIFF_HYS CANH - CANL Differential input voltage hysteresis 50 – 400 mV CANH - CANL Differential input threshold, in standby mode 0.4 – 1.15 V VCM Common Mode Voltage -12 – 12 V RIN Input resistance • CANL input resistance • CANH input resistance 5.0 5.0 – – 50 50 k CANH, CANL differential input resistance 10 – 100 k Input resistance matching -3.0 – 3.0 % IIN_UPWR CANL or CANH input current, device unpowered, VDD = VIO = 0 V, VCANL and VCANH 0 V to 5.0 V range • VDD connected with R = 0 k to GND • VDD connected with R=47 k to GND -10 -10 – – 10 10 RIN_UPWR CANL, CANH input resistance, VCANL = VCANH = 12 V 10 – – k CCAN_CAP CANL, CANH input capacitance (guaranteed by design and characterization) – 20 – pF CDIF_CAP CANL, CANH differential input capacitance (guaranteed by design and characterization) – 10 – pF 150 185 – °C VDIFF_THR_S RIN_DIFF RIN_MATCH TSD Temperature Shutdown µA 33901 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Table 9. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V  VDD  5.5 V, 2.8 V  VIO  5.5 V, - 40 C  TA  125 C, GND = 0 V, R on CAN bus (RL) = 60 , unless otherwise noted. Typical values noted reflect the approximate parameter at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes 2.5 – 16 ms (6) – – 255 ns TIMING PARAMETERS tXDOM TXD DOM tLOOP T loop tWU_FLT1 TWU filter1 0.5 – 5.0 µs (7) tWU_FLT2 TWU filter2 0.08 – 1.0 µs (7) – – 1.3 µs (7) 1.5 – 7.0 ms (7) – 120 300 µs 40 us tTGLT tWU_TO tDELAY_PWR tDELAY_SN Tdelay during toggling Twake up timeout Delay between power-up and device ready Transition time from Standby to Normal mode (STB high to low) Notes 6. MC33901 & MC33901N versions only 7. MC3x901WEF and MC3x901WNEF versions only 5.0 V 1.0 F 100 nF VIO STB VDD CANH MC33901 TXD 60  100 pF CANL RXD 15 pF GND Figure 8. Timing Test Circuit 33901 16 Analog Integrated Circuit Device Data Freescale Semiconductor high TXD low CANH CANL dominant 0.9 V VDIFF (CANH - CANL) 0.5 V recessive high 0.7 VIO RXD 0.3 VIO low tLOOP (R-D) tLOOP (D-R) Figure 9. CAN Timing Diagram recessive dominant dominant recessive dominant recessive BUS t_WUFL1 t_WUFL2 1st event 2nd event t_WUFL2 3rd event T_TOG T_TOG T_TOG T_TOG high RXD low t_WUTO note: 1st, 2nd and 3rd event must occurs within t_WUTO timing. Figure 10. Wake-up Pattern Timing Illustration 33901 Analog Integrated Circuit Device Data Freescale Semiconductor 17 dominant recessive dominant recessive BUS t_WUFL1 1st event t_WUFL1 t_wUFL2 2nd event 1st event t_WUFL2 2nd event t_WUTO (expired) high RXD note: only the 1st and the 2nd event occurred within t_WUTO timing. Figure 11. Timeout Wake-up Timing Illustration recovery condition: TXD high high TXD low dominant recessive dominant dominant BUS TXD_dom timeout TXD_dom timeout TXD_dom timeout TXD dom timeout expired RXD high low Figure 12. TXD Dominant Timeout Detection Illustration 33901 18 Analog Integrated Circuit Device Data Freescale Semiconductor 5 5.1 Typical Applications Application Diagrams VPWR D 5.0 V Reg. VCC MCU 5.0 V C1 VIO VDD CANH STB Port_xx MC3x901xEF TXD TXD CAN controller RXD R1 CANL RXD C1: 1.0 µF R1: application dependant (ex: 60, 120 ohm or other value) GND Figure 13. Single Supply Typical Application Schematic for MC3x901xEF VPWR D 5.0 V Reg. VCC MCU Port_xx 5.0 V VDD C1 CANH STB MC3x901xNEF TXD CAN controller RXD TXD R1 CANL RXD GND C1: 1.0 µF R1: application dependant (ex: 60, 120 ohm or other value) Figure 14. Single Supply Typical Application Schematic for MC3x901xNEF 33901 Analog Integrated Circuit Device Data Freescale Semiconductor 19 5.0 V Reg VPWR D 5.0 V C2 3.3-5.0 V Reg 3.3 - 5.0 V VCC MCU C1 VIO VDD STB Port_xx CANH MC3x901xEF TXD TXD CAN controller RXD R1 CANL RXD GND C1: 1.0 µF C2: 1.0 µF R1: application dependant (ex: 60, 120 ohm or other value) Figure 15. Dual Supply Typical Application Schematic for MC3x901xEF CANH C3 R2 R2, R3: application dependant (ex: 60 ohm or other value): R3 C3: application dependant (ex: 4.7 nF or other value): CANL Figure 16. Example of Bus Termination Options 33901 20 Analog Integrated Circuit Device Data Freescale Semiconductor 6 6.1 Packaging Package Mechanical Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 10. Packaging Information Package Suffix 8-Pin SOICN EF Package Outline Drawing Number 98ASA42564B . 33901 Analog Integrated Circuit Device Data Freescale Semiconductor 21 . 33901 22 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Revision History REVISION 1.0 2.0 3.0 DATE DESCRIPTION OF CHANGES 12/2013 4/2015 6/2015 • Initial release • Changed Advance Information to Technical Data • Added information for high-speed (up to 1.0 Mbit/s) • Added VREC_SM (CANH, CANL recessive voltage, sleep mode) to Table 7 • Added VSYM (Driver symmetry) to Table 7 • Added IIN_UPWR to Table 7 • Added MC33901xNEF and MC34901xNEF parts to Table 1, Orderable Parts • Added additions to all figures and tables to include the variations for the new part numbers 33901 Analog Integrated Circuit Device Data Freescale Semiconductor 23 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. 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