MC33931EKR2

MC33931 5.0 A throttle control H-bridge Rev. 5.0 — 10 September 2018 1 Data sheet: technical data General description The 33931 is a monolithic H-bridge power IC in a robust thermally enhanced package. It is designed primarily for automotive electronic throttle control, but is applicable to any low voltage DC servo motor control application within the current and voltage limits stated in this specification. It meets the stringent requirements of automotive applications and is fully AEC-Q100 grade 1 qualified. The 33931 H-bridge is able to control inductive loads with currents up to 5.0 A peak. RMS current capability is subject to the degree of heat sinking provided to the device package. Internal peak-current limiting (regulation) is activated at load currents above 6.5 A ± 1.5 A. Output loads can be pulse-width modulated at frequencies up to 11 kHz. A load current feedback feature provides a proportional (0.24 % of the load current) current output suitable for monitoring by a microcontroller’s A/D input. A status flag output reports undervoltage, overcurrent and overtemperature fault conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. The disable inputs are provided to force the H-bridge outputs to 3-state (high-impedance OFF state). VPWR VDD 33931 SF FB VPWR CCP OUT1 IN1 MCU MOTOR IN2 OUT2 D1 EN/D2 PGND AGND Figure 1. Simplified application diagram 2 Features and benefits • • • • • • • • • 5.0 to 28 V continuous operation (transient operation from 5.0 to 40 V) 235 mΩ maximum RDS(on) @ TJ = 150 °C (each H-bridge MOSFET) 3.0 V and 5.0 V TTL / CMOS logic compatible inputs Overcurrent limiting (regulation) via internal constant-off-time PWM Output short-circuit protection (short to VPWR or GND) Temperature dependent current limit threshold reduction All inputs have an internal source/sink to define the default (floating input) state Sleep mode with current draw < 50 µA AEC-Q100 grade 1 qualified MC33931 NXP Semiconductors 5.0 A throttle control H-bridge 3 Applications • • • • 4 Electronic throttle control (ETC) Exhaust gas recirculation (EGR) Turbo flap control Industrial and medical pumps and motor control Ordering information Table 1. Ordering information Type number [1] Package Name Description MC33931VW HSOP44 HSOP44, plastic, thermal enhanced small outline package; 44 terminals; 0.65 mm pitch; 15.9 mm x 11 mm x 3 mm body MC33931EK HSOP32 HSOP32, plastic, heat sink, small outline; leaded package; 32 terminals; 0.65 mm pitch; 11 mm x 7.5 mm x 2.2 mm body [1] Operating temperature Version SOT1305-2 TA = −40 °C to 125 °C SOT1746-1 To order parts in tape and reel, add the R2 suffix to the part number. 5 Block diagram VPWR LOGIC SUPPLY CCP VDD VCP CHARGE PUMP HS1 HS2 OUT1 TO GATES OUT2 HS1 LS1 LS2 LS1 IN1 IN2 HS2 EN/D2 GATE DRIVE AND PROTECTION LOGIC D1 SF PGND LS2 VSENSE ILIM PWM FB AGND CURRENT MIRROR AND CONSTANT OFF-TIME PWM CURRENT REGULATOR PGND Figure 2. Block diagram MC33931 Data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 10 September 2018 © NXP B.V. 2018. All rights reserved. 2 / 29 MC33931 NXP Semiconductors 5.0 A throttle control H-bridge 6 Pinning information 6.1 Pinning AGND Tab D1 FB EN/D2 VPWR VPWR VPWR OUT1 OUT1 OUT1 PGND PGND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 SF IN1 IN2 CCP VPWR VPWR OUT2 OUT2 OUT2 PGND PGND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C Tab Figure 3. Pin configuration for HSOP44 AGND 1 32 D1 2 31 IN1 FB 3 30 N/C N/C 4 29 IN2 EN/D2 5 28 CCP N/C 6 27 N/C VPWR 7 26 VPWR VPWR 8 25 VPWR N/C 9 24 N/C OUT1 10 23 OUT2 OUT1 11 22 OUT2 N/C 12 21 N/C N/C N/C SF 13 20 N/C 14 19 N/C PGND 15 18 PGND PGND 16 17 PGND Figure 4. Pin configuration for HSOP32 6.2 Pin description For functional description of each pin, see Section 7.2 "Functional pin description". Table 2. Pin description Symbol Pin HSOP (VW) Pin SOICW-EP Function (EK) Name Description D1 1 2 Logic input Disable input 1 (active high) When D1 is logic high, both OUT1 and OUT2 are 3-stated. Schmitt trigger input with ~80 μA source so default condition = disabled. FB 2 3 Analog output Feedback The load current feedback output provides ground referenced 0.24 % of the high-side output current (tie to GND through a resistor if not used) EN/D2 3 5 Logic input Enable input When EN/D2 is logic high, the H-bridge is operational. When EN/D2 is logic low, the H-bridge outputs are 3-stated and placed in Sleep mode (logic input with ~ 80 μA sink so default condition = Sleep mode). VPWR 4, 5, 6, 40, 39 7, 8, 25, 26 Power input Positive power supply These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. MC33931 Data sheet: technical data All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 10 September 2018 © NXP B.V. 2018. All rights reserved. 3 / 29 MC33931 NXP Semiconductors 5.0 A throttle control H-bridge Symbol Pin HSOP (VW) Pin SOICW-EP Function (EK) Name Description OUT1 7, 8, 9 10, 11 Power output H-bridge output 1 Source of HS1 and drain of LS1 PGND 10, 11, 34, 35 15, 16, 17, 18 Power ground Power ground High-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the PCB. OUT2 36, 37, 38 22, 23 Power output H-bridge output 2 Source of HS2 and drain of LS2 CCP 41 28 Analog output Charge pump capacitor External reservoir capacitor connection for the internal charge pump; connected to VPWR. Allowable values are 30 nF to [1] 100 nF IN2 42 29 Logic input Input 2 Logic input control of OUT2; e.g., when IN2 is logic high, OUT2 is set to VPWR, and when IN2 is logic low, OUT2 is set to PGND (Schmitt trigger input with ~ 80 μA source so default condition = OUT2 high) IN1 43 31 Logic input Input 1 Logic input control of OUT1; e.g., when IN1 is logic high, OUT1 is set to VPWR, and when IN1 is logic low, OUT1 is set to PGND (Schmitt trigger input with ~ 80 μA source so default condition = OUT1 high) SF 44 32 Logic output - open drain Status flag (active low) Open drain active low status flag output requires an external pull-up resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VSFLOW < 0.4 V @ 0.3 mA. Maximum permissible pull-up voltage < 7.0 V. AGND TAB 1 Analog ground Analog signal ground The low-current analog signal ground must be connected to PGND via lowimpedance path (