MC33FS4503CAE

FS6500, FS4500 Safety Power System Basis Chip with CAN FD and LIN Transceivers Rev. 1.0 — 14 December 2017 1 Short data sheet: advance information General description The FS6500/FS4500 SMARTMOS devices are a multi-output, power supply, integrated circuit, including CAN Flexible Data (FD) and/or LIN transceivers, dedicated to the automotive market. Multiple switching and linear voltage regulators, including low-power mode (32 μA) are available with various wake-up capabilities. An advanced power management scheme is implemented to maintain high efficiency over a wide range of input voltages (down to 2.7 V) and output current ranges (up to 2.2 A). The FS6500/FS4500 includes configurable fail-safe/fail silent safety behavior and features, with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2 and -5 standards. The LIN interface fulfills LIN protocol specifications 2.0, 2.1, 2.2, and SAEJ2602-2. 2 Features • Battery voltage sensing and MUX output pin • Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck • Family of devices to supply MCU core from 1.0 V to 5.0 V, with SMPS (0.8 A, 1.5 A or 2.2 A) or LDO (0.5 A) • 36 V maximum input operating voltage • Linear voltage regulator dedicated to auxiliary functions, or to sensor supply (VCCA tracker or independent), 5.0 V or 3.3 V • Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os supply (VCCA), 5.0 V or 3.3 V • 3.3 V keep alive memory supply available in low-power mode • Long duration timer, counting up to 6 months with 1.0 s resolution • Multiple wake-up sources in low-power mode: CAN, LIN, IOs, LDT • Five configurable I/Os 3 Applications • • • • Drive train electrification (BMS, hybrid EV and HEV, inverter, DCDC, alterno starter) Drive train - chassis and safety (active suspension, steering, safety domain gateway) Power train (EMS, TCU, gear box) ADAS (LDW, Radar, sensor fusion safety area) FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers 4 Simplified application diagram Figure 1. FS6500C simplified application diagram - buck boost configuration - FS1B   VCORE VPRE +Battery (KL30) BOOT_CORE SW_CORE VPRE GATE_LS BOOT_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 VSUP3 VSENSE VAUX_E DEBUG mode VCCA ADC Input Vstandby IO_5/VKAM MOSI MISO SCLK NCS IO_0 SPI INTB IO_4 To switch CAN BUS RSTB CANH CANL LIN BUS TXD LIN RXDL FS0B GNDA GND_COM DGND IO_3 IO_2 Reset CAN TXDL VDDIO Fail-safe Drive NMI VDDIO RXD VSUP3 AD ref. voltage VCORE or VCCA MUX_OUT CAN-5V MCU FCRBM VCCA_E VDDIO DEBUG Ignition Key (KL15) VPRE COMP_CORE VCCA FS6500L VAUX SELECT VPRE FB_CORE VCCA_B VAUX_B VAUX VCORE_SNS VDD LIN VDDIO FCCU Figure 2. FS6500L simplified application diagram - buck configuration - LIN - VCCA =100 mA FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 2 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers Figure 3. FS4500C simplified application diagram - buck boost configuration - FS1B 5 Ordering information 5.1 Part numbers definition MC33FS c 5 x y z AE/R2 Table 1. Part number breakdown Code Option c 4 series 6 series x Description Linear DCDC 0.5 A or 0.8 A VCORE current 1.5 A 2 2.2 A 0 none 1 FS1B 2 z VCORE type 0 1 y Variable Functions LDT 3 FS1B, LDT 4 LDT, VKAM ON by default N none C Physical interface L FS6500-FS4500SDS Short data sheet: advance information CAN FD CAN FD and LIN All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 3 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers 5.2 Part numbers list Table 2. Orderable part variations Part number FS1B LDT VCORE VCORE type VKAM on CAN FD LIN MC33FS4500CAE 0 0 0.5 A Linear by SPI 1 0 MC33FS4500LAE 0 0 0.5 A Linear by SPI 1 1 MC33FS4500NAE 0 0 0.5 A Linear by SPI 0 0 MC33FS4501CAE 1 0 0.5 A Linear by SPI 1 0 MC33FS4501NAE 1 0 0.5 A Linear by SPI 0 0 MC33FS4502CAE 0 1 0.5 A Linear by SPI 1 0 MC33FS4502LAE 0 1 0.5 A Linear by SPI 1 1 MC33FS4502NAE 0 1 0.5 A Linear by SPI 0 0 MC33FS4503CAE 1 1 0.5 A Linear by SPI 1 0 MC33FS4503NAE 1 1 0.5 A Linear by SPI 0 0 MC33FS6500CAE 0 0 0.8 A DC DC by SPI 1 0 MC33FS6500LAE 0 0 0.8 A DC DC by SPI 1 1 MC33FS6500NAE 0 0 0.8 A DC DC by SPI 0 0 MC33FS6501CAE 1 0 0.8 A DC DC by SPI 1 0 MC33FS6501NAE 1 0 0.8 A DC DC by SPI 0 0 MC33FS6502CAE 0 1 0.8 A DC DC by SPI 1 0 MC33FS6502LAE 0 1 0.8 A DC DC by SPI 1 1 MC33FS6502NAE 0 1 0.8 A DC DC by SPI 0 0 MC33FS6503CAE 1 1 0.8 A DC DC by SPI 1 0 MC33FS6503NAE 1 1 0.8 A DC DC by SPI 0 0 MC33FS6504LAE 0 1 0.8 A DC DC by default 1 1 0 0 1.5 A DC DC by SPI 1 0 MC33FS6510LAE 0 0 1.5 A DC DC by SPI 1 1 MC33FS6510NAE 0 0 1.5 A DC DC by SPI 0 0 MC33FS6511CAE 1 0 1.5 A DC DC by SPI 1 0 MC33FS6511NAE 1 0 1.5 A DC DC by SPI 0 0 MC33FS6512CAE 0 1 1.5 A DC DC by SPI 1 0 MC33FS6512LAE 0 1 1.5 A DC DC by SPI 1 1 MC33FS6512NAE 0 1 1.5 A DC DC by SPI 0 0 MC33FS6513CAE 1 1 1.5 A DC DC by SPI 1 0 MC33FS6513NAE 1 1 1.5 A DC DC by SPI 0 0 MC33FS6514LAE 0 1 1.5 A DC DC by default 1 1 MC33FS6520CAE 0 0 2.2 A DC DC by SPI 1 0 MC33FS6520LAE 0 0 2.2 A DC DC by SPI 1 1 MC33FS6520NAE 0 0 2.2 A DC DC by SPI 0 0 MC33FS6521CAE 1 0 2.2 A DC DC by SPI 1 0 MC33FS6521NAE 1 0 2.2 A DC DC by SPI 0 0 MC33FS6522CAE 0 1 2.2 A DC DC by SPI 1 0 MC33FS6522LAE 0 1 2.2 A DC DC by SPI 1 1 MC33FS6522NAE 0 1 2.2 A DC DC by SPI 0 0 MC33FS6523CAE 1 1 2.2 A DC DC by SPI 1 0 MC33FS6523NAE 1 1 2.2 A DC DC by SPI 0 0 MC33FS6510CAE [1] [2] Temperature (TA) –40 °C to 125 °C Package 48-pin LQFP exposed pad Notes [1] [2] To order parts in tape and reel, add the R2 suffix to the part number. LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B is not, and vice versa. VKAM on by default is available on certain part numbers only. FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 4 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers 6 Block diagram COMP_CORE BOOT_CORE VCORE_SNS FB_CORE SW_CORE DGND VPRE GATE_LS BOOT_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 VPRE TSD TSD VPRE SMPS VCORE SMPS VPRE TSD VAUX_E VAUX_B VAUX VPRE TSD VAUX Linear Regulator VPRE TSD VCAN Linear Regulator CAN-5V VCCA_E VCCA_B VCCA VCCA Linear Regulator VSUP3 VREF VSENSE (2.5 V) VPRE VPRE Analog Reference #1 MUX Interface Charge Pump IO_0 SELECT IO_2 I/Os Interface IO_3 OSC Main V2p5d Main VKAM Power Management State Machine 5 IO_4 IO_5/VKAM MUX_OUT DEBUG Debug INTB NCS SCLK MOSI MISO SPI Main * GNDA VKAM Select VSUP3 IO_0 Die Temp MISO FS CAN/LIN diag VSENSE_MON VSUP_MON VSUP3 VDDIO Long * Duration Timer Select Debug CAN-5V VAUX VCCA FB_CORE V2p5d FS VPRE Voltage Regulator SUPERVISOR (Over & undervoltage) FCRBM 5 VSENSE OSC FS Analog Reference #2 FS VPRE SPI FS VSUP3 Fail -safe Machine VPRE FS1B delay * & driver CAN-5V RXDL LIN Interface * LIN Fail-safe logic & supply FS1B VPU_FS RXD TXD CAN Flexible Data Interface * CANH CANL GND_COM RSTB FS0B VSUP3 TXDL Part Number dependent * Figure 4. FS6500/FS4500 with CAN and LIN simplified internal block diagram FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 5 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers Pinning information VCCA VCCA_B VCCA_E VAUX_E VAUX_B VAUX VPRE 42 41 40 39 38 37 GATE_LS 44 43 BOOT_PRE DGND 45 47 46 SW_PRE1 SW_PRE2 48 Pinning VSUP1 1 36 BOOT_CORE VSUP2 2 35 SW_CORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 COMP_CORE FS1B 5 32 FB_CORE GND_COM 6 31 SELECT VDDIO CAN_5V 7 30 CANH 8 29 INTB CANL 9 28 NCS 24 RSTB VPRE 37 23 VAUX 38 NC VAUX_B 39 22 VAUX_E VPU_FS TXD VCCA_E 41 40 RXD IO_3 VCCA_B 42 IO_2 VCCA 43 MUX_OUT GATE_LS 44 AGND 45 DEBUG BOOT_PRE DGND 46 FCRBM 21 MISO 20 25 19 12 18 MOSI IO_0 17 SCLK 26 16 27 11 15 10 14 IO_4 IO_5/VKAM 13 7.1 FS0B 7 SW_PRE1 SW_PRE2 48 47 Figure 5. FS6500 pinout with CAN and FS1B VSUP1 1 36 BOOT_CORE VSUP2 2 35 SW_CORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 COMP_CORE LIN 5 32 FB_CORE GND_COM 6 31 SELECT 20 21 22 23 24 TXD RXD TXDL RXDL RSTB MISO 19 MOSI 25 IO_3 26 12 18 11 IO_0 17 IO_5/VKAM IO_2 SCLK MUX_OUT NCS 27 16 28 10 15 9 IO_4 AGND CANL DEBUG INTB 14 VDDIO 29 13 30 8 FS0B 7 CANH FCRBM CAN_5V Figure 6. FS6500 pinout with CAN and LIN FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 6 / 20 FS6500, FS4500 NXP Semiconductors VAUX VPRE 37 VCCA_E 41 VAUX_B VCCA_B 42 38 VCCA 43 VAUX_E GATE_LS 44 39 DGND 45 40 SW_PRE2 BOOT_PRE 46 SW_PRE1 47 48 Safety Power System Basis Chip with CAN FD and LIN Transceivers VSUP1 1 36 BOOT_CORE VSUP2 2 35 SW_CORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 COMP_CORE FB_CORE NC 5 32 GND_COM 6 31 SELECT CAN_5V 7 30 VDDIO NC 8 29 INTB NC 9 28 NCS 24 RSTB 23 NC 20 NC 22 19 IO_3 NC 18 IO_2 21 17 NC 16 AGND MISO MUX_OUT 25 15 12 DEBUG MOSI IO_0 14 SCLK 26 13 27 11 FS0B 10 FCRBM IO_4 IO_5/VKAM SW_PRE1 SW_PRE2 BOOT_PRE DGND GATE_LS VCCA VCCA_B VCCA_E VAUX_E VAUX_B VAUX VPRE 48 47 46 45 44 43 42 41 40 39 38 37 Figure 7. FS6500 pinout without CAN, without LIN VSUP1 1 36 NC VSUP2 2 35 VCORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 NC FS1B 5 32 FB_CORE GND_COM 6 31 SELECT VDDIO CAN_5V 7 30 CANH 8 29 INTB CANL 9 28 NCS 16 17 18 19 20 21 22 23 24 AGND IO_2 IO_3 TXD RXD VPU_FS NC RSTB MISO MUX_OUT 25 15 12 DEBUG MOSI IO_0 14 SCLK 26 13 27 11 FS0B 10 FCRBM IO_4 IO_5/VKAM Figure 8. FS4500 pinout with CAN and FS1B 7.2 Pin description Table 3.  FS6500/FS4500 pin definition Pin Symbol Type Definition 1 VSUP1 A_IN Power supply of the device. An external reverse battery protection diode in series is mandatory. FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 7 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers Pin Symbol Type Definition 2 VSUP2 A_IN Second power supply. Protected by the external reverse battery protection diode used for VSUP1. VSUP1 and VSUP2 must be connected together externally. 3 VSENSE A_IN Sensing of the battery voltage. Must be connected prior to the reverse battery protection diode. 4 VSUP3 A_IN Third power supply dedicated to the device supply. Protected by the external reverse battery protection diode used for VSUP1. Must be connected between the reverse protection diode and the input PI filter. LIN A_IN/OUT LIN single-wire bus transmitter and receiver or FS1B D_OUT Second output of the safety block (active low). The pin is asserted low at start-up and when a fault condition is detected, with a configurable delay or duration versus FS0B output terminal. Open drain structure. 5 LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B is not, and vice versa. If neither LIN, nor FS1B functions are used, this pin must be left open. 6 GND_COM GROUND Dedicated ground for physical layers 7 CAN_5V A_OUT Output voltage for the embedded CAN FD interface 8 CANH A_IN/OUT CAN output high. If CAN function is not used, this pin must be left open. 9 CANL A_IN/OUT CAN output low. If CAN function is not used, this pin must be left open. 10 IO_4 D_IN A_OUT Can be used as digital input (load dump proof) with wake-up capability or as an output gate driver Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes (when used in conjunction with IO_5). Wake-up capability: Can be selectable to wake-up on edges or levels Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI. IO_5/VKAM A_IN D_IN A_OUT Can be used as digital input with wake-up capability or as an analog output providing keep alive memory supply in low-power mode. Analog input: Pin status can be read through the MUX output terminal Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes (when used in conjunction with IO_4). Wake-up capability: Can be selectable to wake-up on edges or levels Supply output: Provide keep alive memory supply in low-power mode 11 VKAM can be enabled or disabled by default at power up. The differentiation is made by part numbers. 12 IO_0 A_IN D_IN Can be used as analog or digital input (load dump proof) with wake-up capability (selectable) Analog input: Pin status can be read through the MUX output terminal Digital input: Pin status can be read through the SPI Wake-up capability: Can be selectable to wake-up on edges or levels 13 FCRBM A_IN Feedback core resistor bridge monitoring: For safety purposes, this pin is used to monitor the middle point of a redundant resistor bridge connected on VCORE (in parallel to the one used to set the VCORE voltage). If not used, this pin must be connected directly to FB_CORE. 14 FS0B D_OUT First output of the safety block (active low). The pin is asserted low at start-up and when a fault condition is detected. Open drain structure. 15 DEBUG D_IN Debug mode entry input 16 AGND GROUND Analog ground connection 17 MUX_OUT A_OUT Multiplexed output to be connected to a MCU ADC. Selection of the analog parameter is available at MUX-OUT through the SPI. 18 19 IO_2:3 D_IN Digital input pin with wake-up capability (logic level compatible) Digital input: Pin status can be read through the SPI. Can be used to monitor FCCU error signals from MCU for safety purposes. Wake-up capability: Can be selectable to wake-up on edges or levels FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 8 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers Pin Symbol Type Definition 20 TXD D_IN Transceiver input from the MCU which controls the state of the CAN bus. Internal pullup to VDDIO. If CAN function is not used, this pin must be left open. 21 RXD D_OUT Receiver output which reports the state of the CAN bus to the MCU If CAN function is not used, this pin must be left open TXDL D_IN Transceiver input from the MCU controlling the state of the LIN bus. Internal pull-up to VDDIO. or VPU_FS A_OUT Pull-up output for FS1B function 22 LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B is not, and vice versa. If neither LIN, nor FS1B functions are used, this pin must be left open. 23 RXDL D_OUT Receiver output reporting the state of the LIN bus to the MCU. If LIN function is not used, this pin must be left open. 24 RSTB D_OUT This output is asserted low when the safety block reports a failure. The main function is to reset the MCU. Reset input voltage is also monitored in order to detect external reset and fault condition. Open drain structure. 25 MISO D_OUT SPI bus. Master input slave output 26 MOSI D_IN SPI bus. Master output slave input 27 SCLK D_IN SPI Bus. Serial clock 28 NCS D_IN Not chip select (active low) 29 INTB D_OUT This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is configurable. Internal pull-up to VDDIO. 30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os. 31 SELECT D_IN Hardware selection pin for VAUX and VCCA output voltages 32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier. 33 COMP_COR E A_OUT Compensation network. Output of the error amplifier. For FS4500 series, this pin must be left open (NC). 34 VCORE_SNS A_IN VCORE input voltage sense 35 SW_CORE A_OUT VCORE output switching point for FS6500 series or VCORE A_OUT VCORE output voltage for FS4500 series 36 BOOT_COR E A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive. For FS4500 series, this pin must be left open (NC). 37 VPRE A_IN VPRE input voltage sense 38 VAUX A_OUT VAUX output voltage. External PNP ballast transistor. Collector connection 39 VAUX_B A_OUT VAUX voltage regulator. External PNP ballast transistor. Base connection 40 VAUX_E A_OUT VAUX voltage regulator. External PNP ballast transistor. Emitter connection 41 VCCA_E A_OUT VCCA voltage regulator. External PNP ballast transistor. Emitter connection 42 VCCA_B A_OUT VCCA voltage regulator. External PNP ballast transistor. Base connection 43 VCCA A_OUT VCCA output voltage. External PNP ballast transistor. Collector connection 44 GATE_LS A_OUT Low-side MOSFET gate drive for non-inverting buck-boost configuration 45 DGND GROUND Digital ground connection 46 BOOT_PRE A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive 47 SW_PRE2 A_OUT Second pre-regulator output switching point 48 SW_PRE1 A_OUT First pre-regulator output switching point FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 9 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers 8 Maximum ratings Table 4.  Maximum ratings All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes VSUP1/2/3 DC voltage at power supply pins –1.0 to 40 V [1] VSENSE DC voltage at battery sense pin (with ext R in series mandatory) –14 to 40 V VSW1,2 DC voltage at SW_PRE1 and SW_PRE2 pins –1.0 to 40 V VPRE DC voltage at VPRE pin –0.3 to 8 V VGATE_LS DC voltage at Gate_LS pin –0.3 to 8 V VBOOT_PRE DC voltage at BOOT_PRE pin –1.0 to 50 V VSW_CORE DC voltage at SW_CORE pin –1.0 to 8 V VCORE_SNS DC voltage at VCORE_SNS pin 0.0 to 8 V VBOOT_CORE DC voltage at BOOT_CORE pin 0.0 to 15 V VFB_CORE DC voltage at FB_CORE pin –0.3 to 2.5 V VCOMP_CORE DC voltage at COMP_CORE pin –0.3 to 2.5 V VFCRBM DC voltage at FCRBM pin –0.3 to 8 V VAUX_B,E DC voltage at VAUX_B, VAUX_E pins –0.3 to 40 V VAUX DC voltage at VAUX pin –2.0 to 40 V VCCA_B,E DC voltage at VCCA_B, VCCA_E pins –0.3 to 8 V VCCA DC voltage at VCCA pin –0.3 to 8 V VDDIO DC voltage at VDDIO pin –0.3 to 8 V VCAN_5V DC voltage on CAN_5V pin –0.3 to 8 V VPU_FS DC voltage at VPU_FS pin –0.3 to 8 V VFSxB DC voltage at FS0B, FS1B pins (with ext R in series mandatory) –0.3 to 40 V VDEBUG DC voltage at DEBUG pin –0.3 to 40 V VIO_0,4 DC voltage at IO_0, IO_4 pins (with ext R in series mandatory) –0.3 to 40 V VIO_5 DC voltage at IO_5 pin –0.3 to 20 V VKAM DC voltage at VKAM pin –0.3 to 8 V VDIG DC voltage at INTB, RSTB, MISO, MOSI, NCS, SCLK, MUX_OUT, RXD, TXD, IO_2, IO_3 pins –0.3 to 8 V VSELECT DC voltage at SELECT pin –0.3 to 8 V VBUS_CAN DC voltage on CANL, CANH pins –27 to 40 V VBUS_LIN DC voltage on LIN pin –18 to 40 V I_ISENSE VSENSE maximum current capability –5.0 to 5.0 mA I_IO0, 4, 5 IOs maximum current capability (IO_0, IO_4, IO_5) –5.0 to 5.0 mA Electrical ratings FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 10 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers Symbol Ratings Value Unit VESD-HBM1 VESD-HBM2 VESD-HBM3 VESD-HBM4 Human body model (JESD22/A114) – 100 pF, 1.5 kΩ • All pins • VSUP1,2,3, VSENSE, VAUX, IO_0,4, FS0B, FS1B, DEBUG • CANH, CANL • LIN ±2.0 ±4.0 ±6.0 ±8.0 kV kV kV kV VESD-CDM1 VESD-CDM2 Charge device model (JESD22/C101): • All pins • Corner pins ±500 ±750 V V Notes ESD voltage [2] System level ESD (gun test) • VSUP1, 2, 3, VSENSE, VAUX, IO_0, 4, 5, FS0B, FS1B VESD-GUN1 330 Ω/150 pF unpowered according to IEC61000-4-2 ±8.0 kV VESD-GUN2 330 Ω/150 pF unpowered according to OEM LIN, CAN, FLexray Conformance ±8.0 kV VESD-GUN3 2.0 kΩ/150 pF unpowered according to ISO10605.2008 ±8.0 kV VESD-GUN4 2.0 kΩ/330 pF powered according to ISO10605.2008 • CANH, CANL ±8.0 kV VESD-GUN5 330 Ω/150 pF unpowered according to IEC61000-4-2 ±15.0 kV VESD-GUN6 330 Ω/150 pF unpowered according to OEM LIN, CAN, FLexray conformance ±12.0 kV VESD-GUN7 2.0 kΩ/150 pF unpowered according to ISO10605.2008 ±15.0 kV VESD-GUN8 2.0 kΩ/330 pF powered according to ISO10605.2008 • LIN ±12.0 kV VESD-GUN9 330 Ω/150 pF unpowered according to IEC61000-4-2: ±12.0 kV VESD-GUN10 330 Ω/150 pF unpowered according to OEM LIN, CAN, flexray conformance ±12.0 kV VESD-GUN11 2.0 kΩ/150 pF unpowered according to ISO10605.2008 ±12.0 kV VESD-GUN12 2.0 kΩ/330 pF powered according to ISO10605.2008 ±12.0 kV TA Ambient temperature –40 to 125 °C TJ Junction temperature –40 to 150 °C TSTG Storage temperature –55 to 150 °C Thermal ratings Thermal resistance RθJA Thermal resistance junction to ambient 30 °C/W [3] RθJCTOP Thermal resistance junction to case top 23.8 °C/W [4] RθJCBOTTOM Thermal resistance junction to case bottom 0.9 °C/W [5] [1] [2] [3] [4] [5] All VSUPs (VSUP1/2/3) must be connected to the same supply Compared to AGND Per JEDEC JESD51-6 with the board (JESD51-7) horizontal Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1). Thermal resistance between the die and the solder pad on the bottom of the packaged based on simulation without any interface resistance. FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 11 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers 9 Packaging 9.1 Package mechanical dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing's document number. Table 5. Package mechanical dimensions Package Suffix Package outline drawing number 7.0 × 7.0, 48–Pin LQFP exposed pad, with 0.5 mm pitch, and a 4.5 × 4.5 exposed pad AE 98ASA00173D FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 12 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 13 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 14 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 15 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers 10 References The following are URLs where you can obtain information on related NXP products and application solutions. NXP.com support pages Description URL AN5238 Hardware design and product guidelines http://www.nxp.com/AN5238-DOWNLOAD AN4388 Quad flat package (QFP) http://www.nxp.com/files/analog/doc/app_note/AN4388.pdf Power dissipation tool (Excel file) http://www.nxp.com/files/analog/software_tools/FS6500-FS4500-powerdissipation-calculator.xlsx VCORE compensation network simulation tool (CNC) Upon demand FMEDA FS6500/FS4500 FMEDA Upon demand FS6500-FS4500SMUG FS6500/FS4500 Safety Manual – user guide https://www.nxp.com/webapp/Download?colCode=FS6500-FS4500SMUG FS6500-FS4500 Power System Basis Chip with CAN Flexible Data and LIN Transceivers data sheet https://www.nxp.com/webapp/Download?colCode=FS6500-FS4500 KITFS6522LAEEVM FS6500 evaluation board with LIN (no FS1B) http://www.nxp.com/KITFS6522LAEEVM KITFS4503CAEEVM FS4500 evaluation board with FS1B (no LIN) http://www.nxp.com/KITFS4503CAEEVM KITFS6523CAEEVM FS6500 evaluation board with FS1B (no LIN) http://www.nxp.com/KITFS6523CAEEVM FS6500 product summary page http://www.nxp.com/FS6500 FS4500 product summary page http://www.nxp.com/FS4500 Analog power management home page http://www.nxp.com/products/power-management 11 Revision history Table 6. Revision history Document ID Release date Data sheet status Change notice Supersedes FS6500-FS4500SDS v.1.0 20171214 Data sheet: advance information — — FS6500-FS4500SDS Short data sheet: advance information All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 16 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers 12 Legal information 12.1 Data sheet status Document status [1][2] Product status [3] Definition [short] Data sheet: product preview Development This document contains certain information on a product under development. NXP reserves the right to change or discontinue this product without notice. [short] Data sheet: advance information Qualification This document contains information on a new product. Specifications and information herein are subject to change without notice. [short] Data sheet: technical data Production This document contains the product specification. NXP Semiconductors reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a technical data data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the technical data data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without FS6500-FS4500SDS Short data sheet: advance information Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 17 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. FS6500-FS4500SDS Short data sheet: advance information 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — is a trademark of NXP B.V. SafeAssure — is a trademark of NXP B.V. SMARTMOS — is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 18 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers Tables Tab. 1. Tab. 2. Tab. 3. Part number breakdown ....................................3 Orderable part variations ...................................4 FS6500/FS4500 pin definition ........................... 7 Tab. 4. Tab. 5. Tab. 6. Maximum ratings ............................................. 10 Package mechanical dimensions .................... 12 Revision history ...............................................16 Fig. 4. FS6500/FS4500 with CAN and LIN simplified internal block diagram ....................... 5 FS6500 pinout with CAN and FS1B ..................6 FS6500 pinout with CAN and LIN ..................... 6 FS6500 pinout without CAN, without LIN .......... 7 FS4500 pinout with CAN and FS1B ..................7 Figures Fig. 1. Fig. 2. Fig. 3. FS6500C simplified application diagram buck boost configuration - FS1B ....................... 2 FS6500L simplified application diagram buck configuration - LIN - VCCA =100 mA ........ 2 FS4500C simplified application diagram buck boost configuration - FS1B ....................... 3 FS6500-FS4500SDS Short data sheet: advance information Fig. 5. Fig. 6. Fig. 7. Fig. 8. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 14 December 2017 © NXP B.V. 2017. All rights reserved. 19 / 20 FS6500, FS4500 NXP Semiconductors Safety Power System Basis Chip with CAN FD and LIN Transceivers Contents 1 2 3 4 5 5.1 5.2 6 7 7.1 7.2 8 9 9.1 10 11 12 General description ............................................ 1 Features ............................................................... 1 Applications .........................................................1 Simplified application diagram .......................... 2 Ordering information .......................................... 3 Part numbers definition ......................................3 Part numbers list ............................................... 4 Block diagram ..................................................... 5 Pinning information ............................................ 6 Pinning ............................................................... 6 Pin description ................................................... 7 Maximum ratings ...............................................10 Packaging .......................................................... 12 Package mechanical dimensions .................... 12 References ......................................................... 16 Revision history ................................................ 16 Legal information .............................................. 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 December 2017 Document identifier: FS6500-FS4500SDS