MC33FS4507LAE

FS6500, FS4500: ASIL B Safety power system basis chip with CAN FD and LIN transceivers Rev. 3 — 14 April 2021 1 Product short data sheet General description The FS6500/FS4500 SMARTMOS devices are a multi-output, power supply, integrated circuit, including CAN Flexible Data (FD) and/or LIN transceivers, dedicated to the automotive market. Multiple switching and linear voltage regulators, including low-power mode (32 μA) are available with various wake-up capabilities. An advanced power management scheme is implemented to maintain high efficiency over a wide range of input voltages (down to 2.7 V) and output current ranges (up to 2.2 A). The FS6500/FS4500 includes configurable fail-safe/fail silent safety behavior and features, with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL B). (12) The built-in CAN FD interface fulfills the ISO 11898-2 (22) interface fulfills LIN protocol specifications 2.0, 2.1 and -5 , 2.2 (23) (13) standards. The LIN , and SAE J2602-2 (24) . High temperature capability up to TA = 125 °C and TJ = 150 °C, compliant with AECQ100 Grade 1 automotive qualification. 2 Features and benefits • Battery voltage sensing and MUX output pin • Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck • Family of devices to supply MCU core from 1.0 V to 5.0 V, with SMPS (0.8 A, 1.5 A or 2.2 A) or LDO (0.5 A) • Linear voltage regulator dedicated to auxiliary functions, or to sensor supply (VCCA tracker or independent), 5.0 V, or 3.3 V • Linear voltage regulator dedicated to MCU Analog/Digital (A/D) reference voltage or I/Os supply (VCCA), 5.0 V, or 3.3 V • 3.3 V keep alive memory supply available in low-power mode • Long duration timer, counting up to 6 months with 1.0 s resolution • Multiple wake-up sources in low-power mode: CAN, LIN, IOs, LDT • Five configurable I/Os 3 Applications • Drive Train Electrification (BMS, Hybrid EV and HEV, Inverter, DC-DC, Alterno Starter) • Drive Train - Chassis and Safety (Active Suspension, Steering, Safety Domain Gateway) • Power Train (EMS, TCU, Gear Box) • ADAS (LDW, Radar, Sensor Fusion Safety area) FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers • On board charger • Motor control Simplified application diagrams VPRE VDD BOOT_CORE VCORE_SNS VCORE VPRE GATE_LS BOOT_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 +battery (KL30) SW_CORE 4 FB_CORE VSUP3 VSENSE VAUX_E VAUX_B VAUX VPRE COMP_CORE VAUX VCCA_E VCCA_B CAN-5V VCCA DEBUG mode DEBUG ignition key (KL15) to switch VDDIO IO_0 VCCA VCORE or VCCA MUX_OUT FS6500C IO_4 AD ref. voltage ADC Input IO_5/VKAM Vstandby MOSI CANH CAN BUS MCU FCRBM SELECT MISO CANL SPI SCLK NCS VPU-FS INTB RSTB fail-safe delay FS1B Reset TXD RXD V DDIO fail-safe drive NMI V DDIO CAN IO_2 FS0B IO_3 GNDA GND_COM DGND aaa-037808 Figure 1. FS6500C simplified application diagram - buck boost configuration - FS1B     FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 2 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers VPRE VDD VCORE_SNS BOOT_CORE SW_CORE VCORE VPRE GATE_LS BOOT_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 +battery (KL30) FB_CORE VSUP3 VSENSE VAUX_E VAUX_B VAUX VPRE COMP_CORE VAUX MCU FCRBM SELECT VCCA_E VCCA_B CAN-5V VCCA DEBUG mode DEBUG ignition key (KL15) to switch VDDIO IO_0 AD ref. voltage MUX_OUT FS4500C IO_4 ADC Input IO_5/VKAM Vstandby MOSI CANH CAN BUS VCCA VCORE or V CCA MISO CANL SPI SCLK NCS VPU-FS INTB RSTB fail-safe delay FS1B Reset TXD CAN RXD VDDIO fail-safe drive NMI VDDIO IO_2 FS0B IO_3 GNDA GND_COM DGND aaa-037809 Figure 2. FS4500C simplified application diagram - buck boost configuration - FS1B 5 Ordering information 5.1 Part number definition MC33FS c 5 x y z AE/R2 Table 1. Part number breakdown Code Option c 4 series Variable VCORE type 6 series x 0 1 y VCORE current 1.5 A 2.2 A 5 None Functions FS1B LDT 8 FS1B and LDT N None C K Physical interface L Product short data sheet DC-DC 2 7 FS6500-FS4500SDS-ASILB Linear 0.5 A or 0.8 A 6 z Description All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 CAN FD LIN only CAN FD and LIN © NXP B.V. 2021. All rights reserved. 3 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 5.2 Part numbers list Table 2. Orderable part variations Part Number Temperature (TA) Package FS1B LDT VCORE VCORE type VKAM On CAN FD LIN ASIL MC33FS4505NAE 0 0 0.5 A Linear by SPI 0 0 B MC33FS4505CAE 0 0 0.5 A Linear by SPI 1 0 B MC33FS4505KAE 0 0 0.5 A Linear By SPI 0 1 B MC33FS4505LAE 0 0 0.5 A Linear By SPI 1 1 B MC33FS4506NAE 1 0 0.5 A Linear by SPI 0 0 B MC33FS4506CAE 1 0 0.5 A Linear by SPI 1 0 B MC33FS4507NAE 0 1 0.5 A Linear by SPI 0 0 B MC33FS4507CAE 0 1 0.5 A Linear by SPI 1 0 B MC33FS4507KAE 0 1 0.5 A Linear by SPI 0 1 B MC33FS4507LAE 0 1 0.5 A Linear by SPI 1 1 B MC33FS4508NAE 1 1 0.5 A Linear by SPI 0 0 B MC33FS4508CAE 1 1 0.5 A Linear by SPI 1 0 B MC33FS6505NAE 0 0 0.8 A DC-DC by SPI 0 0 B MC33FS6505CAE 0 0 0.8 A DC-DC by SPI 1 0 B MC33FS6505KAE 0 0 0.8 A DC-DC by SPI 0 1 B MC33FS6505LAE 0 0 0.8 A DC-DC by SPI 1 1 B MC33FS6506NAE 1 0 0.8 A DC-DC by SPI 0 0 B 1 0 0.8 A DC-DC by SPI 1 0 B 0 1 0.8 A DC-DC by SPI 0 0 B 0 1 0.8 A DC-DC by SPI 1 0 B MC33FS6507KAE 0 1 0.8 A DC-DC by SPI 0 1 B MC33FS6507LAE 0 1 0.8 A DC-DC by SPI 1 1 B MC33FS6508NAE 1 1 0.8 A DC-DC by SPI 0 0 B MC33FS6508CAE 1 1 0.8 A DC-DC by SPI 1 0 B MC33FS6515NAE 0 0 1.5 A DC-DC by SPI 0 0 B MC33FS6515CAE 0 0 1.5 A DC-DC by SPI 1 0 B MC33FS6515KAE 0 0 1.5 A DC-DC by SPI 0 1 B MC33FS6506CAE MC33FS6507NAE MC33FS6507CAE –40 °C to 125 °C 48-pin LQFP exposed pad MC33FS6515LAE 0 0 1.5 A DC-DC by SPI 1 1 B MC33FS6516NAE 1 0 1.5 A DC-DC by SPI 0 0 B MC33FS6516CAE 1 0 1.5 A DC-DC by SPI 1 0 B MC33FS6517NAE 0 1 1.5 A DC-DC by SPI 0 0 B MC33FS6517CAE 0 1 1.5 A DC-DC by SPI 1 0 B MC33FS6517KAE 0 1 1.5 A DC-DC by SPI 0 1 B MC33FS6517LAE 0 1 1.5 A DC-DC by SPI 1 1 B MC33FS6518NAE 1 1 1.5 A DC-DC by SPI 0 0 B MC33FS6518CAE 1 1 1.5 A DC-DC by SPI 1 0 B MC33FS6525NAE 0 0 2.2 A DC-DC by SPI 0 0 B MC33FS6525CAE 0 0 2.2 A DC-DC by SPI 1 0 B FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 Notes [1] © NXP B.V. 2021. All rights reserved. 4 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Table 2. Orderable part variations...continued Part Number Temperature (TA) Package FS1B LDT VCORE VCORE type VKAM On CAN FD LIN ASIL MC33FS6525KAE 0 0 2.2 A DC-DC by SPI 0 1 B MC33FS6525LAE 0 0 2.2 A DC-DC by SPI 1 1 B MC33FS6526NAE 1 0 2.2 A DC-DC by SPI 0 0 B MC33FS6526CAE 1 0 2.2 A DC-DC by SPI 1 0 B MC33FS6527NAE 0 1 2.2 A DC-DC by SPI 0 0 B MC33FS6527CAE 0 1 2.2 A DC-DC by SPI 1 0 B MC33FS6527KAE 0 1 2.2 A DC-DC by SPI 0 1 B MC33FS6527LAE 0 1 2.2 A DC-DC by SPI 1 1 B MC33FS6528NAE 1 1 2.2 A DC-DC by SPI 0 0 B MC33FS6528CAE 1 1 2.2 A DC-DC by SPI 1 0 B [1] Notes To order parts in tape and reel, add the R2 suffix to the part number. FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 5 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers TSD TSD VAUX_B Vpre Vpre Vpre Vsup3 TDS Vcan LINEAR REGULATOR Vpre Vpre ANALOG REFERENCE #1 I/Os INTERFACE IO_4 MUX INTERFACE IO_0 select Vsup3 VKAM Vref Die Vsense (2.5 V) Temp CHARGE PUMP SELECT IO_0 VCCA_E TSD Vcca LINEAR REGULATOR Vaux LINEAR REGULATOR VAUX IO_5/VKAM COMP_CORE Vcore SMPS VAUX_E IO_3 BOOT_CORE TSD Vpre SMPS IO_2 VCORE_SNS Vpre VSUP3 CAN-5V FB_CORE SW_CORE DGND VPRE GATE_LS BOOT_PRE SW_PRE2 SW_PRE1 VSUP2 Block diagram VSUP1 6 V2p5d MAIN OSC MAIN POWER MANAGEMENT STATE MACHINE 5 VCCA_B VCCA GNDA MUX_OUT VKAM DEBUG debug INTB NCS SCLK SPI MAIN (1) MOSI MISO MIFO FS VDDIO CAN/LIN diag Vsense_mon Vsup_mon LONG Vsup3 DURATION TIMER(1) FB_core CAN-5 V Vaux Vcca Vpre FCRBM VOLTAGE REGULATOR SUPERVISOR (OVER AND UNDERVOLTAGE) debug select V2p5d FS 5 ANALOG REFERENCE #2 FS Vpre SPI FS OSC FS Vsup3 FAIL SAFE MACHINE Vsup3 Vpre FS1B DELAY (1) AND DRIVER CAN-5 V VSENSE RSTB FS0B FS1B VPU_FS RXD CANH CAN FLEXIBLE DATA INTERFACE(1) CANL TXD GND_COM RXDL LIN LIN INTERFACE(1) fail safe logic and supply TXDL part number dependent (1) aaa-037733 Figure 3. FS6500/FS4500 with CAN and LIN simplified internal block diagram FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 6 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 7 Pinning information 37 VPRE 38 VAUX 39 VAUX_B 41 VCCA_E 40 VAUX_E 42 VCCA_B 43 VCCA 44 GATE_LS 45 DGND 47 SW_PRE2 46 BOOT_PRE 48 SW_PRE1 7.1 Pinning information VSUP1 1 36 BOOT_CORE VSUP2 2 35 SW_CORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 COMP_CORE FS1B 5 32 FB_CORE GND_COM 6 31 SELECT CAN_5V 7 30 VDDIO CANH 8 29 INTB CANL 9 28 NCS RSTB 24 VPU_FS 22 39 VAUX_B 37 VPRE RXD 21 40 VAUX_E n.c. 23 TXD 20 41 VCCA_E 38 VAUX IO_3 19 42 VCCA_B IO_2 18 AGND 16 25 MISO MUX_OUT 17 IO_0 12 DEBUG 15 26 MOSI FS0B 14 27 SCLK IO_5/VKAM 11 FCRBM 13 IO_4 10 aaa-037734 Figure 4. FS6500 pinout with CAN and FS1B 43 VCCA 44 GATE_LS 45 DGND 46 BOOT_PRE 47 SW_PRE2 48 SW_PRE1   VSUP1 1 36 BOOT_CORE VSUP2 2 35 SW_CORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 COMP_CORE LIN 5 32 FB_CORE GND_COM 6 31 SELECT CAN_5V 7 30 VDDIO CANH 8 29 INTB CANL 9 28 NCS RSTB 24 TXDL 22 RXDL 23 RXD 21 TXD 20 IO_3 19 IO_2 18 AGND 16 25 MISO MUX_OUT 17 IO_0 12 DEBUG 15 26 MOSI FS0B 14 27 SCLK IO_5/VKAM 11 FCRBM 13 IO_4 10 aaa-037735 Figure 5. FS6500 pinout with CAN and LIN FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 7 / 26 FS6500, FS4500: ASIL B NXP Semiconductors 37 VPRE 38 VAUX 39 VAUX_B 41 VCCA_E 40 VAUX_E 42 VCCA_B 43 VCCA 44 GATE_LS 45 DGND 47 SW_PRE2 46 BOOT_PRE 48 SW_PRE1 Safety power system basis chip with CAN FD and LIN transceivers VSUP1 1 36 BOOT_CORE VSUP2 2 35 SW_CORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 COMP_CORE n.c. 5 32 FB_CORE GND_COM 6 31 SELECT CAN_5V 7 30 VDDIO n.c 8 29 INTB n.c 9 28 NCS n.c. 22 n.c. 23 RSTB 24 39 VAUX_B 38 VAUX 37 VPRE n.c. 21 n.c. 20 IO_3 19 IO_2 18 AGND 16 25 MISO MUX_OUT 17 IO_0 12 DEBUG 15 26 MOSI FS0B 14 27 SCLK IO_5/VKAM 11 FCRBM 13 IO_4 10 aaa-037736 Figure 6. FS6500 pinout without CAN, without LIN 40 VAUX_E 41 VCCA_E 42 VCCA_B 43 VCCA 44 GATE_LS 45 DGND 46 BOOT_PRE 47 SW_PRE2 48 SW_PRE1   VSUP1 1 36 n.c. VSUP2 2 35 VCORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 n.c. FS1B 5 32 FB_CORE GND_COM 6 31 SELECT CAN_5V 7 30 VDDIO CANH 8 29 INTB CANL 9 28 NCS RSTB 24 n.c. 23 VPU_FS 22 RXD 21 TXD 20 IO_3 19 IO_2 18 AGND 16 25 MISO MUX_OUT 17 IO_0 12 DEBUG 15 26 MOSI FS0B 14 27 SCLK IO_5/VKAM 11 FCRBM 13 IO_4 10 aaa-037737 Figure 7. FS4500 pinout with CAN and FS1B   FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 8 / 26 FS6500, FS4500: ASIL B NXP Semiconductors 37 VPRE 38 VAUX 39 VAUX_B 41 VCCA_E 40 VAUX_E 42 VCCA_B 43 VCCA 44 GATE_LS 45 DGND 47 SW_PRE2 46 BOOT_PRE 48 SW_PRE1 Safety power system basis chip with CAN FD and LIN transceivers VSUP1 1 36 n.c. VSUP2 2 35 VCORE VSENSE 3 34 VCORE_SNS VSUP3 4 33 n.c. LIN 5 32 FB_CORE GND_COM 6 31 SELECT CAN_5V 7 30 VDDIO n.c. 8 29 INTB n.c. 9 28 NCS RSTB 24 TXDL 22 RXDL 23 n.c. 21 n.c. 20 IO_3 19 IO_2 18 AGND 16 25 MISO MUX_OUT 17 IO_0 12 DEBUG 15 26 MOSI FS0B 14 27 SCLK IO_5/VKAM 11 FCRBM 13 IO_4 10 aaa-039387 Figure 8. FS4500 pinout with LIN, without CAN 7.2 Pin description A functional description of each pin can be found in the full data sheet. Table 3. FS6500/FS4500 pin definition Pin Pin name number Type Definition 1 VSUP1 A_IN Power supply of the device. An external reverse battery protection diode in series is mandatory 2 VSUP2 A_IN Second power supply. Protected by the external reverse battery protection diode used for VSUP1. VSUP1 and VSUP2 must be connected together externally. 3 VSENSE A_IN Sensing of the battery voltage. Must be connected prior to the reverse battery protection diode. 4 VSUP3 A_IN Third power supply dedicated to the device supply. Protected by the external reverse battery protection diode used for VSUP1. Must be connected between the reverse protection diode and the input PI filter. 5 LIN A_IN/OUT LIN single-wire bus transmitter and receiver. or FS1B D_OUT Second output of the safety block (active low). The pin is asserted low at start-up and when a fault condition is detected, with a configurable delay or duration versus FS0B output terminal. Open drain structure. LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B is not, and vice versa. If neither LIN, nor FS1B functions are used, this pin must be left open. 6 GND_COM GROUND Dedicated ground for physical layers 7 CAN_5V A_OUT Output voltage for the embedded CAN FD interface 8 CANH A_IN/OUT CAN output high. If CAN function is not used, this pin must be left open. 9 CANL A_IN/OUT CAN output low. If CAN function is not used, this pin must be left open. FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 9 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Table 3. FS6500/FS4500 pin definition...continued Pin Pin name number Type Definition 10 IO_4 D_IN A_OUT Can be used as digital input (load dump proof) with wake-up capability or as an output gate driver Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes (when used with IO_5). Wake-up capability: Can be selectable to wake-up on edges or levels. Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI. 11 IO_5/VKAM A_IN D_IN A_OUT Can be used as digital input with wake-up capability or as an analog output providing keep alive memory supply in low-power mode. Analog input: Pin status can be read through the MUX output terminal Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes (when used with IO_4). Wake-up capability: Can be selectable to wake-up on edges or levels. Supply output: Provide keep alive memory supply in low-power mode 12 IO_0 A_IN D_IN Can be used as analog or digital input (load dump proof) with wake-up capability (selectable) Analog input: Pin status can be read through the MUX output terminal Digital input: Pin status can be read through the SPI. Wake-up capability: Can be selectable to wake-up on edges or levels. 13 FCRBM A_IN Feedback core resistor bridge monitoring: For safety purposes, this pin is used to monitor the middle point of a redundant resistor bridge connected on VCORE (in parallel to the one used to set the VCORE voltage). If not used, this pin must be connected directly to FB_CORE. 14 FS0B D_OUT First output of the safety block (active low). The pin is asserted low at start-up and when a fault condition is detected. Open drain structure. 15 DEBUG D_IN Debug mode entry input 16 AGND GROUND Analog ground connection 17 MUX_OUT A_OUT Multiplexed output to be connected to a MCU ADC. Selection of the analog parameter is available at MUX-OUT through the SPI. 18 19 IO_2:3 D_IN Digital input pin with wake-up capability (logic level compatible) Digital input: Pin status can be read through the SPI. Wake-up capability: Can be selectable to wake-up on edges or levels. 20 TXD D_IN Transceiver input from the MCU which controls the state of the CAN-bus. Internal pull-up to VDDIO. If CAN function is not used, this pin must be left open. 21 RXD D_OUT Receiver output which reports the state of the CAN-bus to the MCU If CAN function is not used, this pin must be left open. 22 TXDL D_IN Transceiver input from the MCU controlling the state of the LIN bus. Internal pull-up to VDDIO. or VPU_FS A_OUT Pull-up output for FS1B function. LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B is not, and vice versa. If neither LIN, nor FS1B functions are used, this pin must be left open. 23 RXDL FS6500-FS4500SDS-ASILB Product short data sheet D_OUT Receiver output reporting the state of the LIN bus to the MCU. If LIN function is not used, this pin must be left open. All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 10 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Table 3. FS6500/FS4500 pin definition...continued Pin Pin name number Type Definition 24 RSTB D_OUT This output is asserted low when the safety block reports a failure. The main function is to reset the MCU. Reset input voltage is also monitored in order to detect external reset and fault condition. Open drain structure. 25 MISO D_OUT SPI bus. Master input slave output 26 MOSI D_IN SPI bus. Master output slave input 27 SCLK D_IN SPI Bus. Serial clock 28 NCS D_IN Not chip select (active low) 29 INTB D_OUT This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is configurable. Internal pull-up to VDDIO. 30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os. 31 SELECT D_IN Hardware selection pin for VAUX and VCCA output voltages 32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier. 33 COMP_ CORE A_OUT Compensation network. Output of the error amplifier. For FS4500 series, this pin must be left open (NC). 34 VCORE_ SNS A_IN VCORE input voltage sense 35 SW_CORE A_OUT VCORE output switching point for FS6500 series or VCORE A_OUT VCORE output voltage for FS4500 series 36 BOOT_ CORE A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive For FS4500 series, this pin must be left open (NC). 37 VPRE A_IN VPRE input voltage sense 38 VAUX A_OUT VAUX output voltage. External PNP ballast transistor. Collector connection 39 VAUX_B A_OUT VAUX voltage regulator. External PNP ballast transistor. Base connection 40 VAUX_E A_OUT VAUX voltage regulator. External PNP ballast transistor. Emitter connection 41 VCCA_E A_OUT VCCA voltage regulator. External PNP ballast transistor. Emitter connection 42 VCCA_B A_OUT VCCA voltage regulator. External PNP ballast transistor. Base connection 43 VCCA A_OUT VCCA output voltage. External PNP ballast transistor. Collector connection 44 GATE_LS A_OUT Low-side MOSFET gate drive for non-inverting buck-boost configuration 45 DGND GROUND Digital ground connection 46 BOOT_PRE A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive 47 SW_PRE2 A_OUT Second pre-regulator output switching point 48 SW_PRE1 A_OUT First pre-regulator output switching point FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 11 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 8 Maximum ratings Table 4. Maximum ratings All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes [1] Electrical ratings VSUP1/2/3 DC voltage at power supply pins –1.0 to 40 V VSENSE DC voltage at battery sense pin (with ext R in series mandatory) –14 to 40 V VSW1,2 DC voltage at SW_PRE1 and SW_PRE2 Pins –1.0 to 40 V VPRE DC voltage at VPRE Pin –0.3 to 8 V VGATE_LS DC voltage at Gate_LS pin –0.3 to 8 V VBOOT_PRE DC voltage at BOOT_PRE pin –1.0 to 50 V VSW_CORE DC voltage at SW_CORE pin –1.0 to 8 V VCORE_SNS DC voltage at VCORE_SNS pin 0.0 to 8 V VBOOT_CORE DC voltage at BOOT_CORE pin 0.0 to 15 V VFB_CORE DC voltage at FB_CORE pin –0.3 to 2.5 V VCOMP_CORE DC voltage at COMP_CORE pin –0.3 to 2.5 V VFCRBM DC voltage at FCRBM pin –0.3 to 8 V VAUX_B,E DC voltage at VAUX_B, VAUX_E pins –0.3 to 40 V VAUX DC voltage at VAUX pin –2.0 to 40 V VCCA_B,E DC voltage at VCCA_B, VCCA_E pins –0.3 to 8 V VCCA DC voltage at VCCA pin –0.3 to 8 V VDDIO DC voltage at VDDIO pin –0.3 to 8 V VCAN_5V DC voltage on CAN_5V pin –0.3 to 8 V VPU_FS DC voltage at VPU_FS pin –0.3 to 8 V VFSxB DC voltage at FS0B, FS1B pins (with ext R in series mandatory) –0.3 to 40 V VDEBUG DC voltage at DEBUG pin –0.3 to 40 V VIO_0,4 DC voltage at IO_0, IO_4 pins (with ext R in series mandatory) –0.3 to 40 V VIO_5 DC voltage at IO_5 pin –0.3 to 20 V VKAM DC voltage at VKAM pin –0.3 to 8 V VDIG DC voltage at INTB, RSTB, MISO, MOSI, NCS, SCLK, MUX_OUT, RXD, TXD, RXDL, TXDL, IO_2, IO_3 pins –0.3 to 8 V VSELECT DC voltage at SELECT pin –0.3 to 8 V VBUS_CAN DC voltage on CANL, CANH pins –27 to 40 V I_Isense VSENSE maximum current capability –5.0 to 5.0 mA I_IO0, 4, 5 IOs maximum current capability (IO_0, IO_4, IO_5) –5.0 to 5.0 mA ESD voltage (19) Human body model (JESD22/A114) – 100 pF, 1.5 kΩ VESD-HBM1 • All pins ±2.0 kV VESD-HBM2 • VSUP1, 2, 3, VSENSE, VAUX, IO_0,4, FS0B, FS1B, DEBUG ±4.0 kV VESD-HBM3 • CANH, CANL ±6.0 kV VESD-HBM4 • LIN ±8.0 kV FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 [2] © NXP B.V. 2021. All rights reserved. 12 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Table 4. Maximum ratings ...continued All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes (20) Charge device model (JESD22/C101) : VESD-CDM1 • All pins ±500 V VESD-CDM2 • Corner pins ±750 V System level ESD (gun test) • VSUP1, 2, 3, VSENSE, VAUX, IO_0, 4, 5, FS0B, FS1B VESD-GUN1 330 Ω/150 pF unpowered according to IEC 61000-4-2: ±8.0 kV VESD-GUN2 330 Ω/150 pF unpowered according to OEM LIN, CAN, FlexRay Conformance ±8.0 kV ±8.0 kV ±8.0 kV (16) VESD-GUN3 2.0 kΩ/150 pF unpowered according to ISO 10605 VESD-GUN4 2.0 kΩ/330 pF powered according to ISO 10605 (15) (15) • CANH, CANL VESD-GUN5 330 Ω/150 pF unpowered according to IEC 61000-4-2: ±15.0 kV VESD-GUN6 330 Ω/150 pF unpowered according to OEM LIN, CAN, FlexRay Conformance ±12.0 kV ±15.0 kV ±12.0 kV (16) VESD-GUN7 2.0 kΩ/150 pF unpowered according to ISO 10605 VESD-GUN8 2.0 kΩ/330 pF powered according to ISO 10605 (15) (15) • LIN VESD-GUN9 330 Ω/150 pF unpowered according to IEC 61000-4-2: ±12.0 kV VESD-GUN10 330 Ω/150 pF unpowered according to OEM LIN, CAN, FlexRay conformance ±12.0 kV ±12.0 kV ±12.0 kV (16) VESD-GUN11 2.0 kΩ/150 pF unpowered according to ISO 10605 VESD-GUN12 2.0 kΩ/330 pF powered according to ISO 10605 (15) (15) Thermal ratings TA Ambient temperature –40 to 125 °C TJ Junction temperature –40 to 150 °C TSTG Storage temperature –55 to 150 °C Thermal resistance RθJA Thermal resistance junction to ambient 30 °C/W [3] RθJCTOP Thermal resistance junction to case top 23.8 °C/W [4] RθJCBOTTOM Thermal resistance junction to case bottom 0.9 °C/W [5] [1] [2] [3] All VSUPS (VSUP1/2/3) must be connected to the same supply (Figure 1). Compared to AGND. [4] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1) . Thermal resistance between the die and the solder pad on the bottom of the packaged based on simulation without any interface resistance. [5] (17) Per JEDEC JESD51-6 FS6500-FS4500SDS-ASILB Product short data sheet with the board (JESD51-7) (18) horizontal. All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 (21) © NXP B.V. 2021. All rights reserved. 13 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 9 Packaging 9.1 Package mechanical dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Table 5. Package mechanical dimensions Package Suffix Package outline drawing number 7.0 × 7.0, 48–Pin LQFP exposed pad, with 0.5 mm pitch, and a 4.5 × 4.5 exposed pad AE 98ASA00173D FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 14 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 9.2 Package outline Figure 9. SOT1571-1 Rev F FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 15 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Figure 10. SOT1571-1 Rev. F Detail View FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 16 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Figure 11. SOT1571-1 Rev F Notes FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 17 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 10 Soldering Figure 12. SOT1571-1 Rev. F - PCB design guidelines - solder mask opening pattern FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 18 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Figure 13. SOT1571-1 Rev. F - PCB design guidelines - I/O pads and solderable area FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 19 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Figure 14. SOT1571-1 Rev. F - PCB design guidelines - solder paste stencil FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 20 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 11 References Obtain additional information on related NXP products and application solutions through the documents and URLs listed below. (1) AN5238 - FS6500 and FS4500 Safe System Basis Chip Hardware Design and Product Guidelines - Application Note https://www.nxp.com/AN5238-DOWNLOAD (2) AN4388 - Quad Flat Package (QFP) https://www.nxp.com/files/analog/doc/app_note/AN4388.pdf (3) FS6500-FS4500PDTCALC - Power dissipation tool (Excel File) https://www.nxp.com/files/analog/software_tools/FS6500-FS4500-power-dissipation-calculator.xlsx (4) VCORE compensation network simulation tool (CNC) (5) FMEDA - FS6500/FS4500 ASILB FMEDA (6) UM11498 - FS6500/FS4500 ASILB Safety manual – user guide (7) KITFS6507LAEEVM - FS6507, System Basis Chip, ASIL B, DC-DC 0.8 A Vcore, LDT, CAN, LIN https://www.nxp.com/KITFS6507LAEEVM (8) KITFS4508CAEEVM - FS4508, System Basis Chip, ASIL B, Linear 0.5 A Vcore, FS1b, LDT, CAN https://www.nxp.com/KITFS4508CAEEVM (9) FS6500 product summary page https://www.nxp.com/FS6500 [1] [1] (10) FS4500 product summary page https://www.nxp.com/FS4500 (11) Analog power management homepage https://www.nxp.com/products/power-management (12) ISO 11898-2:2003 - Road vehicles — Controller area network (CAN) — Part 2: High-speed medium access unit https://www.iso.org/standard/33423.html (13) ISO 11898-5:2007 - Road vehicles — Controller area network (CAN) — Part 5: High-speed medium access unit with low-power mode https://www.iso.org/contents/data/standard/04/12/41284.html (14) ISO 7637-2:2011 - Road vehicles — Electrical disturbances from conduction and coupling — Part 2: Electrical transient conduction along supply lines only https://www.iso.org/standard/50925.html (15) ISO 10605:2008 - Road vehicles — Test methods for electrical disturbances from electrostatic discharge https://www.iso.org/standard/41937.html (16) IEC 61000-4-2:2008 - Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques Electrostatic discharge immunity test https://webstore.iec.ch/publication/4189 (17) JESD51- 6 - INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR) (18) JESD51-7 - HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES (19) JESD22-A114F - ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING HUMAN BODY MODEL (HBM) (20) JESD22-C101F - FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS (21) MIL-STD-883-1, Method 1012.1 - TEST METHOD STANDARD MICROCIRCUITS FS6500-FS4500SDS-ASILB Product short data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 21 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers (22) LIN Specification Package Revision 2.1:2006 https://www.lin-cia.org/fileadmin/microsites/lin-cia.org/resources/documents/LIN-Spec_Pac2_1.pdf (23) LIN Specification Package Revision 2.2A:2010 https://www.lin-cia.org/fileadmin/microsites/lin-cia.org/resources/documents/LIN_2.2A.pdf (24) SAE J2602-2:201211 - LIN Network for Vehicle Applications Conformance Test https://www.sae.org/standards/content/j2602/2_201211/ [1] Available upon request. 12 Revision history Table 6. Revision history Document ID Release date Data sheet status Supersedes FS6500-FS4500SDS-ASILB v.3.0 20210414 Product FS6500-FS4500SDS-ASILB v.2.0 Modifications • Section 1: replaced "0.8 A" by "1.5 A" • Section 2: replaced "Family of devices to supply MCU core from 1.0 V to 5.0 V, with SMPS (0.8 A) or LDO (0.5 A)" to "Family of devices to supply MCU core from 1.0 V to 5.0 V, with SMPS (0.8 A, 1.5 A or 2.2 A) or LDO (0.5 A)" • Section 5: updated Table 1 and Table 2 (added new part numbers) FS6500-FS4500SDS-ASILB v.2.0 20210111 Modifications • Revised data sheet status from "Preliminary" to "Product". • Section 5.2, revised Table 2 changing "PC33..." parts to "MC33...." • Section 7.2, pin number 11, removed "VKAM can be enabled or disabled by default at power up. The differentiation is made by part numbers." FS6500-FS4500SDS-ASILB v.1.3 20201106 Modifications • Initial release (Short data sheet version aligned to full data sheet, FS6500, FS4500: ASILB, v.1.3) FS6500-FS4500SDS-ASILB Product short data sheet Product Preliminary All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 FS6500-FS4500SDS-ASILB v.1.3 — © NXP B.V. 2021. All rights reserved. 22 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers 13 Legal information 13.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 13.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without FS6500-FS4500SDS-ASILB Product short data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 23 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL-classified accordingly. If FS6500-FS4500SDS-ASILB Product short data sheet this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. SafeAssure — is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 24 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Tables Tab. 1. Tab. 2. Tab. 3. Part number breakdown ....................................3 Orderable part variations ...................................4 FS6500/FS4500 pin definition ........................... 9 Tab. 4. Tab. 5. Tab. 6. Maximum ratings ............................................. 12 Package mechanical dimensions .................... 14 Revision history ...............................................22 Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. FS4500 pinout with LIN, without CAN ............... 9 SOT1571-1 Rev F ...........................................15 SOT1571-1 Rev. F Detail View ....................... 16 SOT1571-1 Rev F Notes ................................ 17 SOT1571-1 Rev. F - PCB design guidelines - solder mask opening pattern ........................ 18 SOT1571-1 Rev. F - PCB design guidelines - I/O pads and solderable area ....................... 19 SOT1571-1 Rev. F - PCB design guidelines - solder paste stencil .......................................20 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. FS6500C simplified application diagram buck boost configuration - FS1B ....................... 2 FS4500C simplified application diagram buck boost configuration - FS1B ....................... 3 FS6500/FS4500 with CAN and LIN simplified internal block diagram ....................... 6 FS6500 pinout with CAN and FS1B ..................7 FS6500 pinout with CAN and LIN ..................... 7 FS6500 pinout without CAN, without LIN .......... 8 FS4500 pinout with CAN and FS1B ..................8 FS6500-FS4500SDS-ASILB Product short data sheet Fig. 13. Fig. 14. All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 April 2021 © NXP B.V. 2021. All rights reserved. 25 / 26 FS6500, FS4500: ASIL B NXP Semiconductors Safety power system basis chip with CAN FD and LIN transceivers Contents 1 2 3 4 5 5.1 5.2 6 7 7.1 7.2 8 9 9.1 9.2 10 11 12 13 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................1 Simplified application diagrams ........................ 2 Ordering information .......................................... 3 Part number definition ....................................... 3 Part numbers list ............................................... 4 Block diagram ..................................................... 6 Pinning information ............................................ 7 Pinning information ............................................ 7 Pin description ................................................... 9 Maximum ratings ...............................................12 Packaging .......................................................... 14 Package mechanical dimensions .................... 14 Package outline ............................................... 15 Soldering ............................................................18 References ......................................................... 21 Revision history ................................................ 22 Legal information .............................................. 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 April 2021 Document identifier: FS6500-FS4500SDS-ASILB